166458Sdfr/*- 2135590Smarcel * Copyright (c) 2003,2004 Marcel Moolenaar 366458Sdfr * Copyright (c) 2000 Doug Rabson 466458Sdfr * All rights reserved. 566458Sdfr * 666458Sdfr * Redistribution and use in source and binary forms, with or without 766458Sdfr * modification, are permitted provided that the following conditions 866458Sdfr * are met: 966458Sdfr * 1. Redistributions of source code must retain the above copyright 1066458Sdfr * notice, this list of conditions and the following disclaimer. 1166458Sdfr * 2. Redistributions in binary form must reproduce the above copyright 1266458Sdfr * notice, this list of conditions and the following disclaimer in the 1366458Sdfr * documentation and/or other materials provided with the distribution. 1466458Sdfr * 1566458Sdfr * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 1666458Sdfr * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 1766458Sdfr * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 1866458Sdfr * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 1966458Sdfr * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 2066458Sdfr * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 2166458Sdfr * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2266458Sdfr * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 2366458Sdfr * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 2466458Sdfr * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 2566458Sdfr * SUCH DAMAGE. 2666458Sdfr */ 2766458Sdfr 2866458Sdfr#include <machine/asm.h> 29135783Smarcel__FBSDID("$FreeBSD$"); 30135783Smarcel 31199502Smarcel#include "opt_xtrace.h" 32171665Smarcel 3383906Sdfr#include <machine/pte.h> 3466458Sdfr#include <assym.s> 3566458Sdfr 3666458Sdfr/* 37199566Smarcel * Nested TLB restart tokens. These are used by the 38199566Smarcel * nested TLB handler for jumping back to the code 39199566Smarcel * where the nested TLB was caused. 40199566Smarcel */ 41199566Smarcel#define NTLBRT_SAVE 0x12c12c 42199566Smarcel#define NTLBRT_RESTORE 0x12c12d 43199566Smarcel 44199566Smarcel/* 45115084Smarcel * ar.k7 = kernel memory stack 46115084Smarcel * ar.k6 = kernel register stack 47115084Smarcel * ar.k5 = EPC gateway page 48115084Smarcel * ar.k4 = PCPU data 4966458Sdfr */ 5066458Sdfr 51221271Smarcel .section .ivt.data, "aw" 52221271Smarcel 53221271Smarcel .global ia64_kptdir 54221271Smarcelia64_kptdir: data8 0 55221271Smarcel 56171665Smarcel#ifdef EXCEPTION_TRACING 57171665Smarcel 58171665Smarcel .global xtrace, xhead 59171665Smarcelxtrace: .space 1024*5*8 60171665Smarcelxhead: data8 xtrace 61171665Smarcel 62171665Smarcel#define XTRACE(offset) \ 63171665Smarcel{ .mmi ; \ 64171665Smarcel mov r24=ar.itc ; \ 65171665Smarcel mov r25=cr.iip ; \ 66171665Smarcel mov r27=offset ; \ 67171665Smarcel} ; \ 68171665Smarcel{ .mlx ; \ 69171665Smarcel mov r28=cr.ifa ; \ 70171665Smarcel movl r29=xhead ;; \ 71171665Smarcel} ; \ 72171665Smarcel{ .mmi ; \ 73171665Smarcel ld8 r29=[r29] ;; \ 74171665Smarcel st8 [r29]=r24,8 ; \ 75171665Smarcel nop 0 ;; \ 76171665Smarcel} ; \ 77171665Smarcel{ .mmi ; \ 78171665Smarcel st8 [r29]=r27,8 ;; \ 79171665Smarcel mov r24=cr.isr ; \ 80171665Smarcel add r27=8,r29 ;; \ 81171665Smarcel} ; \ 82171665Smarcel{ .mmi ; \ 83171665Smarcel st8 [r29]=r25,16 ;; \ 84171665Smarcel st8 [r27]=r28,16 ; \ 85171665Smarcel mov r25=pr ;; \ 86171665Smarcel} ; \ 87171665Smarcel{ .mlx ; \ 88171665Smarcel st8 [r29]=r24 ; \ 89171665Smarcel movl r28=xhead ;; \ 90171665Smarcel} ; \ 91171665Smarcel{ .mii ; \ 92171665Smarcel cmp.eq p15,p0=r27,r28 ; \ 93171665Smarcel addl r29=1024*5*8,r0 ;; \ 94171665Smarcel(p15) sub r27=r28,r29 ;; \ 95171665Smarcel} ; \ 96204184Smarcel{ .mmi ; \ 97171665Smarcel st8 [r28]=r27 ; \ 98204184Smarcel nop 0 ; \ 99204184Smarcel mov pr=r25,0x1ffff ;; \ 100171665Smarcel} 101171665Smarcel 102171665Smarcel#else 103171665Smarcel 104171665Smarcel#define XTRACE(offset) 105171665Smarcel 106171665Smarcel#endif 107171665Smarcel 108221271Smarcel .section .ivt.text, "ax" 109115084Smarcel 11066458Sdfr/* 111115084Smarcel * exception_save: save interrupted state 112115084Smarcel * 113115084Smarcel * Arguments: 114115084Smarcel * r16 address of bundle that contains the branch. The 115115084Smarcel * return address will be the next bundle. 116115084Smarcel * r17 the value to save as ifa in the trapframe. This 117115084Smarcel * normally is cr.ifa, but some interruptions set 118115084Smarcel * set cr.iim and not cr.ifa. 119115084Smarcel * 120115084Smarcel * Returns: 121115084Smarcel * p15 interrupted from user stack 122115084Smarcel * p14 interrupted from kernel stack 123115084Smarcel * p13 interrupted from user backing store 124115084Smarcel * p12 interrupted from kernel backing store 125115084Smarcel * p11 interrupts were enabled 126115084Smarcel * p10 interrupts were disabled 127115084Smarcel */ 128134502SmarcelENTRY_NOPROFILE(exception_save, 0) 129115084Smarcel{ .mii 130115084Smarcel mov r20=ar.unat 131115084Smarcel extr.u r31=sp,61,3 132115084Smarcel mov r18=pr 133115084Smarcel ;; 134115084Smarcel} 135115084Smarcel{ .mmi 136221271Smarcel cmp.le p14,p15=IA64_VM_MINKERN_REGION,r31 137115084Smarcel ;; 138115084Smarcel(p15) mov r23=ar.k7 // kernel memory stack 139115084Smarcel(p14) mov r23=sp 140115084Smarcel ;; 141115084Smarcel} 142115084Smarcel{ .mii 143115084Smarcel mov r21=ar.rsc 144115084Smarcel add r30=-SIZEOF_TRAPFRAME,r23 145115084Smarcel ;; 146115084Smarcel dep r30=0,r30,0,10 147115084Smarcel ;; 148115084Smarcel} 149115084Smarcel{ .mmi 150115084Smarcel mov ar.rsc=0 151115084Smarcel mov r22=cr.iip 152199566Smarcel addl r29=NTLBRT_SAVE,r0 // 22-bit restart token. 153115084Smarcel ;; 154115084Smarcel} 155115084Smarcel 156115084Smarcel /* 157223700Smarcel * We have a 1KB aligned trapframe, pointed to by r30. We can't 158223700Smarcel * reliably write to the trapframe using virtual addressing, due 159223700Smarcel * to the fact that TC entries we depend on can be removed by: 160223700Smarcel * 1. ptc.g instructions issued by other threads/cores/CPUs, or 161223700Smarcel * 2. TC modifications in another thread on the same core. 162223700Smarcel * When our TC entry gets removed, we get nested TLB faults and 163223700Smarcel * since no state is saved, we can only deal with those when 164223700Smarcel * explicitly coded and expected. 165223700Smarcel * As such, we switch to physical addressing and account for the 166223700Smarcel * fact that the tpa instruction can cause a nested TLB fault. 167223700Smarcel * Since the data nested TLB fault does not preserve any state, 168223700Smarcel * we have to be careful what we clobber. Consequently, we have 169223700Smarcel * to be careful what we use here. Below a list of registers that 170223700Smarcel * are considered alive: 171115084Smarcel * r16,r17=arguments 172115084Smarcel * r18=pr, r19=length, r20=unat, r21=rsc, r22=iip, r23=TOS 173223700Smarcel * r29=restart token 174223700Smarcel * r30=trapframe pointers 175115084Smarcel * p14,p15=memory stack switch 176115084Smarcel */ 177223700Smarcelexception_save_restart: 178223700Smarcel tpa r24=r30 // Nested TLB fault possible 179223700Smarcel sub r19=r23,r30 180223700Smarcel nop 0 181223700Smarcel ;; 182209085Smarcel 183223700Smarcel rsm psr.dt 184223700Smarcel add r29=16,r19 // Clobber restart token 185223700Smarcel mov r30=r24 186209085Smarcel ;; 187223700Smarcel srlz.d 188223700Smarcel add r31=8,r24 189209085Smarcel ;; 190209085Smarcel 191223700Smarcel // r18=pr, r19=length, r20=unat, r21=rsc, r22=iip, r23=TOS 192223700Smarcel // r29=delta 193115084Smarcel{ .mmi 194115084Smarcel st8 [r30]=r19,16 // length 195115084Smarcel st8 [r31]=r0,16 // flags 196115084Smarcel ;; 197115084Smarcel} 198115084Smarcel{ .mmi 199115084Smarcel st8.spill [r30]=sp,16 // sp 200115084Smarcel st8 [r31]=r20,16 // unat 201221893Smarcel sub sp=r23,r29 202115084Smarcel ;; 203115084Smarcel} 204115084Smarcel{ .mmi 205115084Smarcel mov r19=ar.rnat 206115084Smarcel mov r20=ar.bspstore 207115084Smarcel mov r23=rp 208115084Smarcel ;; 209115084Smarcel} 210115084Smarcel // r18=pr, r19=rnat, r20=bspstore, r21=rsc, r22=iip, r23=rp 211223700Smarcel // r24=pfs 212115084Smarcel{ .mmi 213115084Smarcel st8 [r30]=r23,16 // rp 214115084Smarcel st8 [r31]=r18,16 // pr 215115084Smarcel mov r24=ar.pfs 216115084Smarcel ;; 217115084Smarcel} 218115084Smarcel{ .mmb 219115084Smarcel st8 [r30]=r24,16 // pfs 220115084Smarcel st8 [r31]=r20,16 // bspstore 221115084Smarcel cover 222115084Smarcel ;; 223115084Smarcel} 224115084Smarcel{ .mmi 225115084Smarcel mov r18=ar.fpsr 226115084Smarcel mov r23=cr.ipsr 227115084Smarcel extr.u r24=r20,61,3 228115084Smarcel ;; 229115084Smarcel} 230115084Smarcel // r18=fpsr, r19=rnat, r20=bspstore, r21=rsc, r22=iip, r23=ipsr 231115084Smarcel{ .mmi 232115084Smarcel st8 [r30]=r19,16 // rnat 233115084Smarcel st8 [r31]=r0,16 // __spare 234221271Smarcel cmp.le p12,p13=IA64_VM_MINKERN_REGION,r24 235115084Smarcel ;; 236115084Smarcel} 237115084Smarcel{ .mmi 238115084Smarcel st8.spill [r30]=r13,16 // tp 239115084Smarcel st8 [r31]=r21,16 // rsc 240115084Smarcel tbit.nz p11,p10=r23,14 // p11=interrupts enabled 241115084Smarcel ;; 242115084Smarcel} 243115084Smarcel{ .mmi 244121635Smarcel(p13) mov r21=ar.k6 // kernel register stack 245121635Smarcel ;; 246115084Smarcel st8 [r30]=r18,16 // fpsr 247121635Smarcel(p13) dep r20=r20,r21,0,9 // align dirty registers 248115084Smarcel ;; 249115084Smarcel} 250200240Smarcel // r19=rnat, r20=bspstore, r22=iip, r23=ipsr 251115084Smarcel{ .mmi 252115084Smarcel st8 [r31]=r23,16 // psr 253115274Smarcel(p13) mov ar.bspstore=r20 254115084Smarcel nop 0 255115084Smarcel ;; 256115084Smarcel} 257204184Smarcel{ .mmi 258200240Smarcel(p13) mov ar.rnat=r19 259115084Smarcel mov r18=ar.bsp 260200240Smarcel nop 0 261115084Smarcel ;; 262115084Smarcel} 263115084Smarcel{ .mmi 264200240Smarcel mov r19=cr.ifs 265115084Smarcel st8.spill [r30]=gp,16 // gp 266200240Smarcel sub r18=r18,r20 267115084Smarcel ;; 268115084Smarcel} 269223700Smarcel // r18=ndirty, r19=ifs, r22=iip 270204184Smarcel{ .mmi 271200240Smarcel st8 [r31]=r18,16 // ndirty 272115084Smarcel st8 [r30]=r19,16 // cfm 273115084Smarcel nop 0 274115084Smarcel ;; 275115084Smarcel} 276115084Smarcel{ .mmi 277115084Smarcel mov r18=cr.isr 278200240Smarcel st8 [r31]=r22,16 // iip 279115084Smarcel add r29=16,r30 280115084Smarcel ;; 281115084Smarcel} 282204184Smarcel{ .mmi 283200240Smarcel st8 [r30]=r17,24 // ifa 284200240Smarcel st8 [r31]=r18,24 // isr 285200240Smarcel nop 0 286115084Smarcel ;; 287115084Smarcel} 288115084Smarcel{ .mmi 289115084Smarcel .mem.offset 0,0 290115084Smarcel st8.spill [r30]=r2,16 // r2 291115084Smarcel .mem.offset 8,0 292115084Smarcel st8.spill [r31]=r3,16 // r3 293115084Smarcel add r2=9*8,r29 294115084Smarcel ;; 295115084Smarcel} 296115084Smarcel{ .mmi 297115084Smarcel .mem.offset 0,0 298115084Smarcel st8.spill [r30]=r8,16 // r8 299115084Smarcel .mem.offset 8,0 300115084Smarcel st8.spill [r31]=r9,16 // r9 301115084Smarcel add r3=8,r2 302115084Smarcel ;; 303115084Smarcel} 304115084Smarcel{ .mmi 305115084Smarcel .mem.offset 0,0 306115084Smarcel st8.spill [r30]=r10,16 // r10 307115084Smarcel .mem.offset 8,0 308115084Smarcel st8.spill [r31]=r11,16 // r11 309115084Smarcel add r8=16,r16 310115084Smarcel ;; 311115084Smarcel} 312115084Smarcel{ .mmi 313115084Smarcel .mem.offset 0,0 314115084Smarcel st8.spill [r30]=r14 // r14 315115084Smarcel .mem.offset 8,0 316115084Smarcel st8.spill [r31]=r15 // r15 317115084Smarcel mov r9=r29 318115084Smarcel} 319115084Smarcel{ .mmb 320115084Smarcel mov r10=ar.csd 321115084Smarcel mov r11=ar.ssd 322115084Smarcel bsw.1 323115084Smarcel ;; 324115084Smarcel} 325115084Smarcel{ .mmi 326115084Smarcel .mem.offset 0,0 327115084Smarcel st8.spill [r2]=r16,16 // r16 328115084Smarcel .mem.offset 8,0 329115084Smarcel st8.spill [r3]=r17,16 // r17 330115084Smarcel mov r14=b6 331115084Smarcel ;; 332115084Smarcel} 333115084Smarcel{ .mmi 334115084Smarcel .mem.offset 0,0 335115084Smarcel st8.spill [r2]=r18,16 // r18 336115084Smarcel .mem.offset 8,0 337115084Smarcel st8.spill [r3]=r19,16 // r19 338115084Smarcel mov r15=b7 339115084Smarcel ;; 340115084Smarcel} 341115084Smarcel{ .mmi 342115084Smarcel .mem.offset 0,0 343115084Smarcel st8.spill [r2]=r20,16 // r20 344115084Smarcel .mem.offset 8,0 345115084Smarcel st8.spill [r3]=r21,16 // r21 346115084Smarcel mov b7=r8 347115084Smarcel ;; 348115084Smarcel} 349115084Smarcel{ .mmi 350115084Smarcel .mem.offset 0,0 351115084Smarcel st8.spill [r2]=r22,16 // r22 352115084Smarcel .mem.offset 8,0 353115084Smarcel st8.spill [r3]=r23,16 // r23 354115084Smarcel ;; 355115084Smarcel} 356115084Smarcel 357115084Smarcel .mem.offset 0,0 358115084Smarcel st8.spill [r2]=r24,16 // r24 359115084Smarcel .mem.offset 8,0 360115084Smarcel st8.spill [r3]=r25,16 // r25 361115084Smarcel ;; 362115084Smarcel .mem.offset 0,0 363115084Smarcel st8.spill [r2]=r26,16 // r26 364115084Smarcel .mem.offset 8,0 365115084Smarcel st8.spill [r3]=r27,16 // r27 366115084Smarcel ;; 367115084Smarcel .mem.offset 0,0 368115084Smarcel st8.spill [r2]=r28,16 // r28 369115084Smarcel .mem.offset 8,0 370115084Smarcel st8.spill [r3]=r29,16 // r29 371115084Smarcel ;; 372115084Smarcel .mem.offset 0,0 373115084Smarcel st8.spill [r2]=r30,16 // r30 374115084Smarcel .mem.offset 8,0 375115084Smarcel st8.spill [r3]=r31,16 // r31 376115084Smarcel ;; 377115084Smarcel 378115084Smarcel{ .mmi 379115084Smarcel st8 [r2]=r14,16 // b6 380115084Smarcel mov r17=ar.unat 381115084Smarcel nop 0 382115084Smarcel ;; 383115084Smarcel} 384115084Smarcel{ .mmi 385115084Smarcel st8 [r3]=r15,16 // b7 386115084Smarcel mov r16=ar.ccv 387115084Smarcel nop 0 388115084Smarcel ;; 389115084Smarcel} 390115084Smarcel{ .mmi 391115084Smarcel st8 [r2]=r16,16 // ccv 392115084Smarcel st8 [r3]=r10,16 // csd 393115084Smarcel nop 0 394115084Smarcel ;; 395115084Smarcel} 396115084Smarcel{ .mmi 397115084Smarcel st8 [r2]=r11,24 // ssd 398115084Smarcel st8 [r9]=r17 399115084Smarcel nop 0 400115084Smarcel ;; 401115084Smarcel} 402115084Smarcel 403115084Smarcel stf.spill [r3]=f6,32 // f6 404115084Smarcel stf.spill [r2]=f7,32 // f7 405115084Smarcel ;; 406115084Smarcel stf.spill [r3]=f8,32 // f8 407115084Smarcel stf.spill [r2]=f9,32 // f9 408115084Smarcel ;; 409115084Smarcel stf.spill [r3]=f10,32 // f10 410115084Smarcel stf.spill [r2]=f11,32 // f11 411115084Smarcel ;; 412115084Smarcel stf.spill [r3]=f12,32 // f12 413115084Smarcel stf.spill [r2]=f13,32 // f13 414115084Smarcel ;; 415115084Smarcel stf.spill [r3]=f14 // f14 416115084Smarcel stf.spill [r2]=f15 // f15 417115084Smarcel ;; 418115084Smarcel{ .mmi 419115084Smarcel mov ar.rsc=3 420115084Smarcel mov r13=ar.k4 421115084Smarcel nop 0 422115084Smarcel ;; 423115084Smarcel} 424115084Smarcel{ .mlx 425223700Smarcel ssm psr.dt|psr.ic|psr.dfh 426115084Smarcel movl gp=__gp 427115084Smarcel ;; 428115084Smarcel} 429204184Smarcel{ .mib 430115084Smarcel srlz.d 431115084Smarcel nop 0 432115084Smarcel br.sptk b7 433115084Smarcel ;; 434115084Smarcel} 435115084SmarcelEND(exception_save) 436115084Smarcel 437115084Smarcel/* 438115084Smarcel * exception_restore: restore interrupted state 439115084Smarcel * 440115084Smarcel * Arguments: 441115084Smarcel * sp+16 trapframe pointer 442115084Smarcel */ 443134502SmarcelENTRY_NOPROFILE(exception_restore, 0) 444115084Smarcel{ .mmi 445115084Smarcel rsm psr.i 446223700Smarcel add sp=16,sp 447223700Smarcel nop 0 448115084Smarcel ;; 449115084Smarcel} 450223700Smarcel 451223700Smarcel // The next instruction can fault. Let it be... 452223700Smarcel tpa r9=sp 453223700Smarcel ;; 454223700Smarcel rsm psr.dt|psr.ic 455223700Smarcel add r8=SIZEOF_SPECIAL+16,r9 456223700Smarcel ;; 457171666Smarcel srlz.d 458223700Smarcel add r2=SIZEOF_TRAPFRAME-16,r9 459223700Smarcel add r3=SIZEOF_TRAPFRAME-32,r9 460115084Smarcel ;; 461223700Smarcel 462223700Smarcel{ .mmi 463115084Smarcel ldf.fill f15=[r2],-32 // f15 464115084Smarcel ldf.fill f14=[r3],-32 // f14 465223700Smarcel nop 0 466115084Smarcel ;; 467223700Smarcel} 468223700Smarcel{ .mmi 469115084Smarcel ldf.fill f13=[r2],-32 // f13 470115084Smarcel ldf.fill f12=[r3],-32 // f12 471223700Smarcel nop 0 472115084Smarcel ;; 473223700Smarcel} 474223700Smarcel{ .mmi 475115084Smarcel ldf.fill f11=[r2],-32 // f11 476115084Smarcel ldf.fill f10=[r3],-32 // f10 477223700Smarcel nop 0 478115084Smarcel ;; 479223700Smarcel} 480223700Smarcel{ .mmi 481115084Smarcel ldf.fill f9=[r2],-32 // f9 482115084Smarcel ldf.fill f8=[r3],-32 // f8 483223700Smarcel nop 0 484115084Smarcel ;; 485223700Smarcel} 486223700Smarcel{ .mmi 487115084Smarcel ldf.fill f7=[r2],-24 // f7 488115084Smarcel ldf.fill f6=[r3],-16 // f6 489223700Smarcel nop 0 490115084Smarcel ;; 491223700Smarcel} 492115084Smarcel{ .mmi 493115084Smarcel ld8 r8=[r8] // unat (after) 494115084Smarcel ;; 495115084Smarcel mov ar.unat=r8 496115084Smarcel nop 0 497115084Smarcel ;; 498115084Smarcel} 499115084Smarcel 500115084Smarcel ld8 r10=[r2],-16 // ssd 501115084Smarcel ld8 r11=[r3],-16 // csd 502115084Smarcel ;; 503115084Smarcel mov ar.ssd=r10 504115084Smarcel mov ar.csd=r11 505115084Smarcel 506115084Smarcel ld8 r14=[r2],-16 // ccv 507115084Smarcel ld8 r15=[r3],-16 // b7 508115084Smarcel ;; 509115084Smarcel 510115084Smarcel{ .mmi 511115084Smarcel mov ar.ccv=r14 512115084Smarcel ld8 r8=[r2],-16 // b6 513115084Smarcel mov b7=r15 514115084Smarcel ;; 515115084Smarcel} 516115084Smarcel{ .mmi 517115084Smarcel ld8.fill r31=[r3],-16 // r31 518115084Smarcel ld8.fill r30=[r2],-16 // r30 519115084Smarcel mov b6=r8 520115084Smarcel ;; 521115084Smarcel} 522115084Smarcel 523115084Smarcel ld8.fill r29=[r3],-16 // r29 524115084Smarcel ld8.fill r28=[r2],-16 // r28 525115084Smarcel ;; 526115084Smarcel ld8.fill r27=[r3],-16 // r27 527115084Smarcel ld8.fill r26=[r2],-16 // r26 528115084Smarcel ;; 529115084Smarcel ld8.fill r25=[r3],-16 // r25 530115084Smarcel ld8.fill r24=[r2],-16 // r24 531115084Smarcel ;; 532115084Smarcel ld8.fill r23=[r3],-16 // r23 533115084Smarcel ld8.fill r22=[r2],-16 // r22 534115084Smarcel ;; 535115084Smarcel ld8.fill r21=[r3],-16 // r21 536115084Smarcel ld8.fill r20=[r2],-16 // r20 537115084Smarcel ;; 538115084Smarcel ld8.fill r19=[r3],-16 // r19 539115084Smarcel ld8.fill r18=[r2],-16 // r18 540115084Smarcel ;; 541115084Smarcel 542115084Smarcel{ .mmb 543115084Smarcel ld8.fill r17=[r3],-16 // r17 544115084Smarcel ld8.fill r16=[r2],-16 // r16 545115084Smarcel bsw.0 546115084Smarcel ;; 547115084Smarcel} 548223700Smarcel{ .mii 549223700Smarcel ld8 r16=[r9] // tf_length 550223700Smarcel add r31=16,r9 551223700Smarcel add r30=24,r9 552223700Smarcel} 553115084Smarcel{ .mmi 554115084Smarcel ld8.fill r15=[r3],-16 // r15 555115084Smarcel ld8.fill r14=[r2],-16 // r14 556223700Smarcel nop 0 557115084Smarcel ;; 558115084Smarcel} 559115084Smarcel{ .mmi 560115084Smarcel ld8.fill r11=[r3],-16 // r11 561223700Smarcel ld8.fill r10=[r2],-16 // r10 562223700Smarcel add r16=r16,sp // ar.k7 563115084Smarcel ;; 564115084Smarcel} 565115084Smarcel{ .mmi 566115084Smarcel ld8.fill r9=[r3],-16 // r9 567223700Smarcel ld8.fill r8=[r2],-16 // r8 568223700Smarcel nop 0 569115084Smarcel ;; 570115084Smarcel} 571115084Smarcel{ .mmi 572115084Smarcel ld8.fill r3=[r3] // r3 573115084Smarcel ld8.fill r2=[r2] // r2 574115084Smarcel nop 0 575115084Smarcel ;; 576223700Smarcel} 577223700Smarcel 578115084Smarcel ld8.fill sp=[r31],16 // sp 579223700Smarcel ld8 r17=[r30],16 // unat 580115084Smarcel ;; 581115084Smarcel ld8 r29=[r31],16 // rp 582223700Smarcel ld8 r18=[r30],16 // pr 583115084Smarcel ;; 584115084Smarcel ld8 r28=[r31],16 // pfs 585223700Smarcel ld8 r20=[r30],24 // bspstore 586115084Smarcel mov rp=r29 587115084Smarcel ;; 588115084Smarcel ld8 r21=[r31],24 // rnat 589115084Smarcel mov ar.pfs=r28 590115084Smarcel ;; 591199566Smarcel ld8.fill r26=[r30],16 // tp 592115084Smarcel ld8 r22=[r31],16 // rsc 593115084Smarcel ;; 594223700Smarcel 595115084Smarcel{ .mmi 596115084Smarcel ld8 r23=[r30],16 // fpsr 597115084Smarcel ld8 r24=[r31],16 // psr 598115084Smarcel extr.u r28=r20,61,3 599115084Smarcel ;; 600115084Smarcel} 601115084Smarcel{ .mmi 602115084Smarcel ld8.fill r1=[r30],16 // gp 603199566Smarcel ld8 r27=[r31],16 // ndirty 604221271Smarcel cmp.le p14,p15=IA64_VM_MINKERN_REGION,r28 605115084Smarcel ;; 606115084Smarcel} 607204184Smarcel{ .mmi 608199566Smarcel ld8 r25=[r30] // cfm 609115084Smarcel ld8 r19=[r31] // ip 610115274Smarcel nop 0 611115084Smarcel ;; 612115084Smarcel} 613199566Smarcel{ .mii 614115084Smarcel // Switch register stack 615115084Smarcel alloc r30=ar.pfs,0,0,0,0 // discard current frame 616199566Smarcel shl r31=r27,16 // value for ar.rsc 617199566Smarcel(p15) mov r13=r26 618115084Smarcel ;; 619115084Smarcel} 620115084Smarcel // The loadrs can fault if the backing store is not currently 621115084Smarcel // mapped. We assured forward progress by getting everything we 622115084Smarcel // need from the trapframe so that we don't care if the CPU 623115084Smarcel // purges that translation when it needs to insert a new one for 624115084Smarcel // the backing store. 625115084Smarcel{ .mmi 626115084Smarcel mov ar.rsc=r31 // setup for loadrs 627115291Smarcel mov ar.k7=r16 628199566Smarcel addl r29=NTLBRT_RESTORE,r0 // 22-bit restart token 629115084Smarcel ;; 630115084Smarcel} 631223700Smarcel 632223700Smarcel ssm psr.dt 633223700Smarcel ;; 634223700Smarcel srlz.d 635223700Smarcel 636115084Smarcelexception_restore_restart: 637115084Smarcel{ .mmi 638115084Smarcel mov r30=ar.bspstore 639115084Smarcel ;; 640115084Smarcel loadrs // load user regs 641221893Smarcel mov r29=0 // Clobber restart token 642115084Smarcel ;; 643115084Smarcel} 644115084Smarcel{ .mmi 645118563Smarcel mov r31=ar.bspstore 646115084Smarcel ;; 647115084Smarcel mov ar.bspstore=r20 648118563Smarcel dep r31=0,r31,0,13 // 8KB aligned 649115084Smarcel ;; 650115084Smarcel} 651204184Smarcel{ .mmi 652115291Smarcel mov ar.k6=r31 653115084Smarcel mov ar.rnat=r21 654115084Smarcel nop 0 655115084Smarcel ;; 656115084Smarcel} 657204184Smarcel{ .mmi 658115084Smarcel mov ar.unat=r17 659115084Smarcel mov cr.iip=r19 660115084Smarcel nop 0 661115084Smarcel} 662115084Smarcel{ .mmi 663115084Smarcel mov cr.ipsr=r24 664199566Smarcel mov cr.ifs=r25 665171666Smarcel mov pr=r18,0x1ffff 666115084Smarcel ;; 667115084Smarcel} 668115084Smarcel{ .mmb 669115084Smarcel mov ar.rsc=r22 670115084Smarcel mov ar.fpsr=r23 671115084Smarcel rfi 672115084Smarcel ;; 673115084Smarcel} 674115084SmarcelEND(exception_restore) 675115084Smarcel 676115084Smarcel/* 67766458Sdfr * Call exception_save_regs to preserve the interrupted state in a 67867020Sdfr * trapframe. Note that we don't use a call instruction because we 67967020Sdfr * must be careful not to lose track of the RSE state. We then call 68067020Sdfr * trap() with the value of _n_ as an argument to handle the 68167020Sdfr * exception. We arrange for trap() to return to exception_restore 68267020Sdfr * which will restore the interrupted state before executing an rfi to 68367020Sdfr * resume it. 68466458Sdfr */ 685135783Smarcel#define CALL(_func_, _n_, _ifa_) \ 686115084Smarcel{ .mib ; \ 687115084Smarcel mov r17=_ifa_ ; \ 688115084Smarcel mov r16=ip ; \ 689171739Smarcel br.sptk exception_save ;; \ 690115084Smarcel} ; \ 691115084Smarcel{ .mmi ; \ 692171739Smarcel alloc r15=ar.pfs,0,0,2,0 ;; \ 693171739Smarcel(p11) ssm psr.i ; \ 694115084Smarcel mov out0=_n_ ;; \ 695115084Smarcel} ; \ 696171739Smarcel{ .mib ; \ 697171739Smarcel(p11) srlz.d ; \ 698115084Smarcel add out1=16,sp ; \ 699171739Smarcel br.call.sptk rp=_func_ ;; \ 700115084Smarcel} ; \ 701204184Smarcel{ .mib ; \ 702115084Smarcel nop 0 ; \ 703115084Smarcel nop 0 ; \ 704171739Smarcel br.sptk exception_restore ;; \ 705115084Smarcel} 706105499Smarcel 707105499Smarcel#define IVT_ENTRY(name, offset) \ 708105499Smarcel .org ia64_vector_table + offset; \ 709105499Smarcel .global ivt_##name; \ 710105499Smarcel .proc ivt_##name; \ 71185682Sdfr .prologue; \ 712105499Smarcel .unwabi @svr4, 'I'; \ 713105499Smarcel .save rp, r0; \ 71485682Sdfr .body; \ 715171665Smarcelivt_##name: \ 716171665Smarcel XTRACE(offset) 717105499Smarcel 718105499Smarcel#define IVT_END(name) \ 719117436Smarcel .endp ivt_##name 720105499Smarcel 721205014Snwhitehorn#ifdef COMPAT_FREEBSD32 722135783Smarcel#define IA32_TRAP ia32_trap 723135783Smarcel#else 724135783Smarcel#define IA32_TRAP trap 725135783Smarcel#endif 726135783Smarcel 72766458Sdfr/* 72866458Sdfr * The IA64 Interrupt Vector Table (IVT) contains 20 slots with 64 72966458Sdfr * bundles per vector and 48 slots with 16 bundles per vector. 73066458Sdfr */ 73166458Sdfr 732219758Smarcel .section .ivt, "ax" 73366458Sdfr 73466458Sdfr .align 32768 73566458Sdfr .global ia64_vector_table 736105499Smarcel .size ia64_vector_table, 32768 73766458Sdfria64_vector_table: 73866458Sdfr 739105499SmarcelIVT_ENTRY(VHPT_Translation, 0x0000) 740135783Smarcel CALL(trap, 0, cr.ifa) 741105499SmarcelIVT_END(VHPT_Translation) 74266458Sdfr 743105499SmarcelIVT_ENTRY(Instruction_TLB, 0x0400) 74466458Sdfr mov r16=cr.ifa 74566458Sdfr mov r17=pr 74666458Sdfr ;; 74766458Sdfr thash r18=r16 74866458Sdfr ttag r19=r16 74966458Sdfr ;; 75067020Sdfr add r21=16,r18 // tag 75166458Sdfr add r20=24,r18 // collision chain 75266458Sdfr ;; 75367020Sdfr ld8 r21=[r21] // check VHPT tag 754148807Smarcel ld8 r20=[r20] // bucket head 75567020Sdfr ;; 756115084Smarcel cmp.ne p15,p0=r21,r19 757115084Smarcel(p15) br.dpnt.few 1f 75867020Sdfr ;; 75967020Sdfr ld8 r21=[r18] // read pte 76067020Sdfr ;; 76167020Sdfr itc.i r21 // insert pte 762171666Smarcel mov pr=r17,0x1ffff 763115179Smarcel ;; 76467020Sdfr rfi // done 76567020Sdfr ;; 766171666Smarcel1: rsm psr.dt // turn off data translations 767171666Smarcel dep r20=0,r20,61,3 // convert vhpt ptr to physical 76866458Sdfr ;; 76966458Sdfr srlz.d // serialize 770171666Smarcel ld8 r20=[r20] // first entry 77166458Sdfr ;; 772115084Smarcel2: cmp.eq p15,p0=r0,r20 // done? 773115084Smarcel(p15) br.cond.spnt.few 9f // bail if done 77466458Sdfr ;; 77566458Sdfr add r21=16,r20 // tag location 77666458Sdfr ;; 77766458Sdfr ld8 r21=[r21] // read tag 77866458Sdfr ;; 779115084Smarcel cmp.ne p15,p0=r21,r19 // compare tags 780115084Smarcel(p15) br.cond.sptk.few 3f // if not, read next in chain 78166458Sdfr ;; 782172692Smarcel ld8 r21=[r20] // read pte 783172692Smarcel mov r22=PTE_ACCESSED 784172692Smarcel ;; 785172692Smarcel or r21=r21,r22 786172692Smarcel ;; 787172692Smarcel st8 [r20]=r21,8 78866458Sdfr ;; 78966458Sdfr ld8 r22=[r20] // read rest of pte 79066458Sdfr ;; 79166458Sdfr dep r18=0,r18,61,3 // convert vhpt ptr to physical 79266458Sdfr ;; 79366458Sdfr add r20=16,r18 // address of tag 79466458Sdfr ;; 79566458Sdfr ld8.acq r23=[r20] // read old tag 79666458Sdfr ;; 79786951Sdfr dep r23=-1,r23,63,1 // set ti bit 79866458Sdfr ;; 79966458Sdfr st8.rel [r20]=r23 // store old tag + ti 80066458Sdfr ;; 80166458Sdfr mf // make sure everyone sees 80266458Sdfr ;; 80366458Sdfr st8 [r18]=r21,8 // store pte 80466458Sdfr ;; 80566458Sdfr st8 [r18]=r22,8 80666458Sdfr ;; 80766458Sdfr st8.rel [r18]=r19 // store new tag 808115179Smarcel ;; 809115179Smarcel itc.i r21 // and place in TLB 810171666Smarcel ssm psr.dt 81166458Sdfr ;; 812171666Smarcel srlz.d 81366458Sdfr mov pr=r17,0x1ffff // restore predicates 81486951Sdfr rfi 815171666Smarcel ;; 81667020Sdfr3: add r20=24,r20 // next in chain 81766458Sdfr ;; 81866458Sdfr ld8 r20=[r20] // read chain 819219758Smarcel br.sptk 2b // loop 82067020Sdfr ;; 821171666Smarcel9: ssm psr.dt 822171666Smarcel mov pr=r17,0x1ffff // restore predicates 823171666Smarcel ;; 82467020Sdfr srlz.d 82567020Sdfr ;; 826135783Smarcel CALL(trap, 20, cr.ifa) // Page Not Present trap 827105499SmarcelIVT_END(Instruction_TLB) 82866458Sdfr 829105499SmarcelIVT_ENTRY(Data_TLB, 0x0800) 83066458Sdfr mov r16=cr.ifa 83166458Sdfr mov r17=pr 83266458Sdfr ;; 83366458Sdfr thash r18=r16 83466458Sdfr ttag r19=r16 83566458Sdfr ;; 83667020Sdfr add r21=16,r18 // tag 83766458Sdfr add r20=24,r18 // collision chain 83866458Sdfr ;; 83967020Sdfr ld8 r21=[r21] // check VHPT tag 840148807Smarcel ld8 r20=[r20] // bucket head 84167020Sdfr ;; 842115084Smarcel cmp.ne p15,p0=r21,r19 843115084Smarcel(p15) br.dpnt.few 1f 84467020Sdfr ;; 84567020Sdfr ld8 r21=[r18] // read pte 84667020Sdfr ;; 84767020Sdfr itc.d r21 // insert pte 848171666Smarcel mov pr=r17,0x1ffff 849115179Smarcel ;; 85067020Sdfr rfi // done 85167020Sdfr ;; 852171666Smarcel1: rsm psr.dt // turn off data translations 853171666Smarcel dep r20=0,r20,61,3 // convert vhpt ptr to physical 85466458Sdfr ;; 85566458Sdfr srlz.d // serialize 856171666Smarcel ld8 r20=[r20] // first entry 85766458Sdfr ;; 858115084Smarcel2: cmp.eq p15,p0=r0,r20 // done? 859115084Smarcel(p15) br.cond.spnt.few 9f // bail if done 86066458Sdfr ;; 86166458Sdfr add r21=16,r20 // tag location 86266458Sdfr ;; 86366458Sdfr ld8 r21=[r21] // read tag 86466458Sdfr ;; 865115084Smarcel cmp.ne p15,p0=r21,r19 // compare tags 866115084Smarcel(p15) br.cond.sptk.few 3f // if not, read next in chain 86766458Sdfr ;; 868172692Smarcel ld8 r21=[r20] // read pte 869172692Smarcel mov r22=PTE_ACCESSED 870172692Smarcel ;; 871172692Smarcel or r21=r21,r22 872172692Smarcel ;; 873172692Smarcel st8 [r20]=r21,8 87466458Sdfr ;; 87566458Sdfr ld8 r22=[r20] // read rest of pte 87666458Sdfr ;; 87766458Sdfr dep r18=0,r18,61,3 // convert vhpt ptr to physical 87866458Sdfr ;; 87966458Sdfr add r20=16,r18 // address of tag 88066458Sdfr ;; 88166458Sdfr ld8.acq r23=[r20] // read old tag 88266458Sdfr ;; 88386951Sdfr dep r23=-1,r23,63,1 // set ti bit 88466458Sdfr ;; 88566458Sdfr st8.rel [r20]=r23 // store old tag + ti 88666458Sdfr ;; 88766458Sdfr mf // make sure everyone sees 88866458Sdfr ;; 88966458Sdfr st8 [r18]=r21,8 // store pte 89066458Sdfr ;; 89166458Sdfr st8 [r18]=r22,8 89266458Sdfr ;; 89366458Sdfr st8.rel [r18]=r19 // store new tag 894115179Smarcel ;; 895115179Smarcel itc.d r21 // and place in TLB 896171666Smarcel ssm psr.dt 89766458Sdfr ;; 898171666Smarcel srlz.d 89966458Sdfr mov pr=r17,0x1ffff // restore predicates 90086951Sdfr rfi 901171666Smarcel ;; 90267020Sdfr3: add r20=24,r20 // next in chain 90366458Sdfr ;; 90466458Sdfr ld8 r20=[r20] // read chain 905219758Smarcel br.sptk 2b // loop 90667020Sdfr ;; 907171666Smarcel9: ssm psr.dt 908171666Smarcel mov pr=r17,0x1ffff // restore predicates 909171666Smarcel ;; 91067020Sdfr srlz.d 91167020Sdfr ;; 912135783Smarcel CALL(trap, 20, cr.ifa) // Page Not Present trap 913105499SmarcelIVT_END(Data_TLB) 91466458Sdfr 915105499SmarcelIVT_ENTRY(Alternate_Instruction_TLB, 0x0c00) 91666458Sdfr mov r16=cr.ifa // where did it happen 91766458Sdfr mov r18=pr // save predicates 91866458Sdfr ;; 91966458Sdfr extr.u r17=r16,61,3 // get region number 920219758Smarcel mov r19=PTE_PRESENT+PTE_ACCESSED+PTE_DIRTY+PTE_PL_KERN+PTE_AR_RWX 92166458Sdfr ;; 922221271Smarcel cmp.eq p13,p0=IA64_PBVM_RR,r17 // RR4? 923219758Smarcel(p13) br.cond.sptk.few 4f 924219758Smarcel ;; 925115084Smarcel cmp.ge p13,p0=5,r17 // RR0-RR5? 926219758Smarcel cmp.eq p14,p15=7,r17 // RR7? 927219758Smarcel(p13) br.cond.spnt.few 9f 92866458Sdfr ;; 929219758Smarcel(p14) add r19=PTE_MA_WB,r19 930219758Smarcel(p15) add r19=PTE_MA_UC,r19 931219758Smarcel dep r17=0,r16,50,14 // clear bits above PPN 93266458Sdfr ;; 933219758Smarcel1: dep r16=r19,r17,0,12 // put pte bits in 0..11 93466458Sdfr ;; 93566458Sdfr itc.i r16 93666458Sdfr mov pr=r18,0x1ffff // restore predicates 93766458Sdfr ;; 93866458Sdfr rfi 939171666Smarcel ;; 940219758Smarcel4: 941219758Smarcel add r19=PTE_MA_WB,r19 942219758Smarcel movl r17=IA64_PBVM_BASE 943219758Smarcel ;; 944219758Smarcel sub r17=r16,r17 945219758Smarcel movl r16=IA64_PBVM_PGTBL 946219758Smarcel ;; 947219758Smarcel extr.u r17=r17,IA64_PBVM_PAGE_SHIFT,61-IA64_PBVM_PAGE_SHIFT 948219758Smarcel ;; 949219758Smarcel shladd r16=r17,3,r16 950219758Smarcel ;; 951219758Smarcel ld8 r17=[r16] 952219758Smarcel br.sptk 1b 953219758Smarcel ;; 95486290Smarcel9: mov pr=r18,0x1ffff // restore predicates 955135783Smarcel CALL(trap, 3, cr.ifa) 956105499SmarcelIVT_END(Alternate_Instruction_TLB) 95766458Sdfr 958105499SmarcelIVT_ENTRY(Alternate_Data_TLB, 0x1000) 95966458Sdfr mov r16=cr.ifa // where did it happen 96066458Sdfr mov r18=pr // save predicates 96166458Sdfr ;; 96266458Sdfr extr.u r17=r16,61,3 // get region number 963219758Smarcel mov r19=PTE_PRESENT+PTE_ACCESSED+PTE_DIRTY+PTE_PL_KERN+PTE_AR_RWX 96466458Sdfr ;; 965221271Smarcel cmp.eq p13,p0=IA64_PBVM_RR,r17 // RR4? 966219758Smarcel(p13) br.cond.sptk.few 4f 967219758Smarcel ;; 968115084Smarcel cmp.ge p13,p0=5,r17 // RR0-RR5? 969219758Smarcel cmp.eq p14,p15=7,r17 // RR7? 970219758Smarcel(p13) br.cond.spnt.few 9f 97166458Sdfr ;; 972219758Smarcel(p14) add r19=PTE_MA_WB,r19 973219758Smarcel(p15) add r19=PTE_MA_UC,r19 974219758Smarcel dep r17=0,r16,50,14 // clear bits above PPN 97566458Sdfr ;; 976219758Smarcel1: dep r16=r19,r17,0,12 // put pte bits in 0..11 97766458Sdfr ;; 97866458Sdfr itc.d r16 97966458Sdfr mov pr=r18,0x1ffff // restore predicates 98066458Sdfr ;; 98166458Sdfr rfi 982171666Smarcel ;; 983219758Smarcel4: 984219758Smarcel add r19=PTE_MA_WB,r19 985219758Smarcel movl r17=IA64_PBVM_BASE 986219758Smarcel ;; 987219758Smarcel sub r17=r16,r17 988219758Smarcel movl r16=IA64_PBVM_PGTBL 989219758Smarcel ;; 990219758Smarcel extr.u r17=r17,IA64_PBVM_PAGE_SHIFT,61-IA64_PBVM_PAGE_SHIFT 991219758Smarcel ;; 992219758Smarcel shladd r16=r17,3,r16 993219758Smarcel ;; 994219758Smarcel ld8 r17=[r16] 995219758Smarcel br.sptk 1b 996219758Smarcel ;; 99786290Smarcel9: mov pr=r18,0x1ffff // restore predicates 998135783Smarcel CALL(trap, 4, cr.ifa) 999105499SmarcelIVT_END(Alternate_Data_TLB) 100066458Sdfr 1001105499SmarcelIVT_ENTRY(Data_Nested_TLB, 0x1400) 1002115084Smarcel // See exception_save_restart and exception_restore_restart for the 1003115084Smarcel // contexts that may cause a data nested TLB. We can only use the 1004115084Smarcel // banked general registers and predicates, but don't use: 1005115084Smarcel // p14 & p15 - Set in exception save 1006115084Smarcel // r16 & r17 - Arguments to exception save 1007115084Smarcel // r30 - Faulting address (modulo page size) 1008115084Smarcel // We assume r30 has the virtual addresses that relate to the data 1009115084Smarcel // nested TLB fault. The address does not have to be exact, as long 1010115084Smarcel // as it's in the same page. We use physical addressing to avoid 1011115084Smarcel // double nested faults. Since all virtual addresses we encounter 1012115084Smarcel // here are direct mapped region 7 addresses, we have no problem 1013115084Smarcel // constructing physical addresses. 1014221271Smarcel 1015223700Smarcel{ .mmi 1016223700Smarcel mov cr.ifa=r30 1017223700Smarcel mov r26=rr[r30] 1018223700Smarcel extr.u r27=r30,61,3 1019223700Smarcel ;; 1020223700Smarcel} 1021223700Smarcel{ .mii 1022221271Smarcel nop 0 1023223700Smarcel dep r26=0,r26,0,2 1024223700Smarcel cmp.eq p12,p13=7,r27 1025115084Smarcel ;; 1026115084Smarcel} 1027115084Smarcel{ .mii 1028223700Smarcel mov cr.itir=r26 1029223700Smarcel(p12) dep r28=0,r30,61,3 1030223700Smarcel(p13) extr.u r28=r30,3*PAGE_SHIFT-8, PAGE_SHIFT-3 // dir L0 index 1031115084Smarcel ;; 1032221271Smarcel} 1033223700Smarcel{ .mlx 1034223700Smarcel(p12) add r28=PTE_PRESENT+PTE_ACCESSED+PTE_DIRTY+PTE_PL_KERN+PTE_AR_RWX+PTE_MA_WB,r28 1035223700Smarcel(p13) movl r27=ia64_kptdir 1036223700Smarcel ;; 1037223700Smarcel} 1038223700Smarcel{ .mib 1039223700Smarcel(p13) ld8 r27=[r27] 1040223700Smarcel(p13) extr.u r26=r30,2*PAGE_SHIFT-5, PAGE_SHIFT-3 // dir L1 index 1041223700Smarcel(p12) br.cond.spnt.few 1f 1042223700Smarcel ;; 1043223700Smarcel} 1044221271Smarcel{ .mmi 1045221271Smarcel rsm psr.dt 1046221271Smarcel ;; 1047221271Smarcel srlz.d 1048169760Smarcel dep r27=0,r27,61,3 1049169760Smarcel ;; 1050115084Smarcel} 1051115084Smarcel{ .mmi 1052169760Smarcel shladd r27=r28,3,r27 1053115084Smarcel ;; 1054169760Smarcel ld8 r27=[r27] // dir L1 page 1055169760Smarcel extr.u r28=r30,PAGE_SHIFT,PAGE_SHIFT-5 // pte index 1056115084Smarcel ;; 1057115084Smarcel} 1058223700Smarcel{ .mii 1059199566Smarcel shladd r27=r26,3,r27 1060223700Smarcel shl r28=r28,5 1061169760Smarcel ;; 1062169760Smarcel dep r27=0,r27,61,3 1063115084Smarcel ;; 1064115084Smarcel} 1065169760Smarcel ld8 r27=[r27] // pte page 1066115084Smarcel ;; 1067169760Smarcel add r27=r28,r27 1068169760Smarcel ;; 1069115084Smarcel dep r27=0,r27,61,3 1070115084Smarcel ;; 1071223700Smarcel ld8 r28=[r27] // pte 1072115084Smarcel ;; 1073135590Smarcel or r28=PTE_DIRTY+PTE_ACCESSED,r28 1074115084Smarcel ;; 1075115084Smarcel st8 [r27]=r28 1076115084Smarcel ;; 1077223700Smarcel ssm psr.dt 1078223700Smarcel ;; 1079223700Smarcel1: 1080115084Smarcel{ .mmi 1081115084Smarcel itc.d r28 1082115084Smarcel ;; 1083223700Smarcel addl r26=NTLBRT_SAVE,r0 1084223700Smarcel addl r27=NTLBRT_RESTORE,r0 1085115084Smarcel ;; 1086115084Smarcel} 1087223700Smarcel{ .mmi 1088115084Smarcel srlz.d 1089223700Smarcel cmp.eq p12,p0=r29,r26 1090199566Smarcel cmp.eq p13,p0=r29,r27 1091199566Smarcel ;; 1092199566Smarcel} 1093223700Smarcel{ .mbb 1094199566Smarcel nop 0 1095223700Smarcel(p12) br.cond.sptk.few exception_save_restart 1096219758Smarcel(p13) br.cond.sptk.few exception_restore_restart 1097115084Smarcel ;; 1098115084Smarcel} 1099223700Smarcel 1100199566Smarcel{ .mlx 1101199566Smarcel mov r26=ar.bsp 1102221893Smarcel movl r29=kstack 1103199566Smarcel ;; 1104199566Smarcel} 1105221893Smarcel{ .mlx 1106199566Smarcel mov r28=sp 1107221893Smarcel movl r27=kstack_top 1108199566Smarcel ;; 1109199566Smarcel} 1110199566Smarcel{ .mmi 1111221893Smarcel add sp=-16,r27 1112199566Smarcel ;; 1113199566Smarcel mov r27=ar.bspstore 1114199566Smarcel nop 0 1115199566Smarcel ;; 1116199566Smarcel} 1117221893Smarcel mov ar.rsc=0 1118221893Smarcel dep r29=r27,r29,0,9 1119221893Smarcel ;; 1120221893Smarcel mov ar.bspstore=r29 1121221893Smarcel ;; 1122199566Smarcel CALL(trap, 5, r30) 1123105499SmarcelIVT_END(Data_Nested_TLB) 112466458Sdfr 1125105499SmarcelIVT_ENTRY(Instruction_Key_Miss, 0x1800) 1126135783Smarcel CALL(trap, 6, cr.ifa) 1127105499SmarcelIVT_END(Instruction_Key_Miss) 1128105499Smarcel 1129105499SmarcelIVT_ENTRY(Data_Key_Miss, 0x1c00) 1130135783Smarcel CALL(trap, 7, cr.ifa) 1131105499SmarcelIVT_END(Data_Key_Miss) 113266458Sdfr 1133105499SmarcelIVT_ENTRY(Dirty_Bit, 0x2000) 113466463Sdfr mov r16=cr.ifa 113566463Sdfr mov r17=pr 113666463Sdfr ;; 113766463Sdfr thash r18=r16 1138115179Smarcel ;; 113966463Sdfr ttag r19=r16 114066463Sdfr add r20=24,r18 // collision chain 114166463Sdfr ;; 1142148807Smarcel ld8 r20=[r20] // bucket head 1143148807Smarcel ;; 114466463Sdfr rsm psr.dt // turn off data translations 1145171666Smarcel dep r20=0,r20,61,3 // convert vhpt ptr to physical 114666463Sdfr ;; 114766463Sdfr srlz.d // serialize 1148171666Smarcel ld8 r20=[r20] // first entry 114966463Sdfr ;; 1150115084Smarcel1: cmp.eq p15,p0=r0,r20 // done? 1151115084Smarcel(p15) br.cond.spnt.few 9f // bail if done 115266463Sdfr ;; 115366463Sdfr add r21=16,r20 // tag location 115466463Sdfr ;; 115566463Sdfr ld8 r21=[r21] // read tag 115666463Sdfr ;; 1157115084Smarcel cmp.ne p15,p0=r21,r19 // compare tags 1158115084Smarcel(p15) br.cond.sptk.few 2f // if not, read next in chain 115966463Sdfr ;; 116066463Sdfr ld8 r21=[r20] // read pte 1161135590Smarcel mov r22=PTE_DIRTY+PTE_ACCESSED 116266463Sdfr ;; 1163113160Smarcel or r21=r22,r21 // set dirty & access bit 116466463Sdfr ;; 1165115179Smarcel st8 [r20]=r21,8 // store back 116666463Sdfr ;; 116766463Sdfr ld8 r22=[r20] // read rest of pte 116866463Sdfr ;; 116966463Sdfr dep r18=0,r18,61,3 // convert vhpt ptr to physical 117066463Sdfr ;; 117166463Sdfr add r20=16,r18 // address of tag 117266463Sdfr ;; 117366463Sdfr ld8.acq r23=[r20] // read old tag 117466463Sdfr ;; 117586951Sdfr dep r23=-1,r23,63,1 // set ti bit 117666463Sdfr ;; 117766463Sdfr st8.rel [r20]=r23 // store old tag + ti 117866463Sdfr ;; 117966463Sdfr mf // make sure everyone sees 118066463Sdfr ;; 118166463Sdfr st8 [r18]=r21,8 // store pte 118266463Sdfr ;; 118366463Sdfr st8 [r18]=r22,8 118466463Sdfr ;; 118566463Sdfr st8.rel [r18]=r19 // store new tag 1186115179Smarcel ;; 1187115179Smarcel itc.d r21 // and place in TLB 1188171666Smarcel ssm psr.dt 118966463Sdfr ;; 1190171666Smarcel srlz.d 119166463Sdfr mov pr=r17,0x1ffff // restore predicates 119286951Sdfr rfi 1193171666Smarcel ;; 119466463Sdfr2: add r20=24,r20 // next in chain 119566463Sdfr ;; 119666463Sdfr ld8 r20=[r20] // read chain 1197219758Smarcel br.sptk 1b // loop 1198171666Smarcel ;; 1199171666Smarcel9: ssm psr.dt 1200171666Smarcel mov pr=r17,0x1ffff // restore predicates 1201171666Smarcel ;; 1202171666Smarcel srlz.d 1203171666Smarcel ;; 1204135783Smarcel CALL(trap, 8, cr.ifa) // die horribly 1205105499SmarcelIVT_END(Dirty_Bit) 120666458Sdfr 1207105499SmarcelIVT_ENTRY(Instruction_Access_Bit, 0x2400) 120866463Sdfr mov r16=cr.ifa 120966463Sdfr mov r17=pr 121066463Sdfr ;; 121166463Sdfr thash r18=r16 1212115179Smarcel ;; 121366463Sdfr ttag r19=r16 121466463Sdfr add r20=24,r18 // collision chain 121566463Sdfr ;; 1216148807Smarcel ld8 r20=[r20] // bucket head 1217148807Smarcel ;; 121866463Sdfr rsm psr.dt // turn off data translations 1219171666Smarcel dep r20=0,r20,61,3 // convert vhpt ptr to physical 122066463Sdfr ;; 122166463Sdfr srlz.d // serialize 1222171666Smarcel ld8 r20=[r20] // first entry 122366463Sdfr ;; 1224115084Smarcel1: cmp.eq p15,p0=r0,r20 // done? 1225115084Smarcel(p15) br.cond.spnt.few 9f // bail if done 122666463Sdfr ;; 122766463Sdfr add r21=16,r20 // tag location 122866463Sdfr ;; 122966463Sdfr ld8 r21=[r21] // read tag 123066463Sdfr ;; 1231115084Smarcel cmp.ne p15,p0=r21,r19 // compare tags 1232115084Smarcel(p15) br.cond.sptk.few 2f // if not, read next in chain 123366463Sdfr ;; 123466463Sdfr ld8 r21=[r20] // read pte 1235135590Smarcel mov r22=PTE_ACCESSED 123666463Sdfr ;; 123766463Sdfr or r21=r22,r21 // set accessed bit 123866463Sdfr ;; 1239115179Smarcel st8 [r20]=r21,8 // store back 1240115179Smarcel ;; 124166463Sdfr ld8 r22=[r20] // read rest of pte 124266463Sdfr ;; 124366463Sdfr dep r18=0,r18,61,3 // convert vhpt ptr to physical 124466463Sdfr ;; 124566463Sdfr add r20=16,r18 // address of tag 124666463Sdfr ;; 124766463Sdfr ld8.acq r23=[r20] // read old tag 124866463Sdfr ;; 124986951Sdfr dep r23=-1,r23,63,1 // set ti bit 125066463Sdfr ;; 125166463Sdfr st8.rel [r20]=r23 // store old tag + ti 125266463Sdfr ;; 125366463Sdfr mf // make sure everyone sees 125466463Sdfr ;; 125566463Sdfr st8 [r18]=r21,8 // store pte 125666463Sdfr ;; 125766463Sdfr st8 [r18]=r22,8 125866463Sdfr ;; 125966463Sdfr st8.rel [r18]=r19 // store new tag 1260115179Smarcel ;; 1261115179Smarcel itc.i r21 // and place in TLB 1262171666Smarcel ssm psr.dt 126366463Sdfr ;; 1264171666Smarcel srlz.d 126566463Sdfr mov pr=r17,0x1ffff // restore predicates 126666463Sdfr rfi // walker will retry the access 1267171666Smarcel ;; 126866463Sdfr2: add r20=24,r20 // next in chain 126966463Sdfr ;; 127066463Sdfr ld8 r20=[r20] // read chain 1271219758Smarcel br.sptk 1b // loop 1272171666Smarcel ;; 1273171666Smarcel9: ssm psr.dt 1274171666Smarcel mov pr=r17,0x1ffff // restore predicates 1275171666Smarcel ;; 1276171666Smarcel srlz.d 1277171666Smarcel ;; 1278135783Smarcel CALL(trap, 9, cr.ifa) 1279105499SmarcelIVT_END(Instruction_Access_Bit) 128066458Sdfr 1281105499SmarcelIVT_ENTRY(Data_Access_Bit, 0x2800) 128266463Sdfr mov r16=cr.ifa 128366463Sdfr mov r17=pr 128466463Sdfr ;; 128566463Sdfr thash r18=r16 1286115179Smarcel ;; 128766463Sdfr ttag r19=r16 1288115179Smarcel add r20=24,r18 // collision chain 128966463Sdfr ;; 1290148807Smarcel ld8 r20=[r20] // bucket head 1291148807Smarcel ;; 129266463Sdfr rsm psr.dt // turn off data translations 1293171666Smarcel dep r20=0,r20,61,3 // convert vhpt ptr to physical 129466463Sdfr ;; 129566463Sdfr srlz.d // serialize 1296171666Smarcel ld8 r20=[r20] // first entry 129766463Sdfr ;; 1298115084Smarcel1: cmp.eq p15,p0=r0,r20 // done? 1299115084Smarcel(p15) br.cond.spnt.few 9f // bail if done 130066463Sdfr ;; 130166463Sdfr add r21=16,r20 // tag location 130266463Sdfr ;; 130366463Sdfr ld8 r21=[r21] // read tag 130466463Sdfr ;; 1305115084Smarcel cmp.ne p15,p0=r21,r19 // compare tags 1306115084Smarcel(p15) br.cond.sptk.few 2f // if not, read next in chain 130766463Sdfr ;; 130866463Sdfr ld8 r21=[r20] // read pte 1309135590Smarcel mov r22=PTE_ACCESSED 131066463Sdfr ;; 131166463Sdfr or r21=r22,r21 // set accessed bit 131266463Sdfr ;; 1313115179Smarcel st8 [r20]=r21,8 // store back 131466463Sdfr ;; 131566463Sdfr ld8 r22=[r20] // read rest of pte 131666463Sdfr ;; 131766463Sdfr dep r18=0,r18,61,3 // convert vhpt ptr to physical 131866463Sdfr ;; 131966463Sdfr add r20=16,r18 // address of tag 132066463Sdfr ;; 132166463Sdfr ld8.acq r23=[r20] // read old tag 132266463Sdfr ;; 132386951Sdfr dep r23=-1,r23,63,1 // set ti bit 132466463Sdfr ;; 132566463Sdfr st8.rel [r20]=r23 // store old tag + ti 132666463Sdfr ;; 132766463Sdfr mf // make sure everyone sees 132866463Sdfr ;; 132966463Sdfr st8 [r18]=r21,8 // store pte 133066463Sdfr ;; 133166463Sdfr st8 [r18]=r22,8 133266463Sdfr ;; 133366463Sdfr st8.rel [r18]=r19 // store new tag 1334115179Smarcel ;; 1335115179Smarcel itc.d r21 // and place in TLB 1336171666Smarcel ssm psr.dt 133766463Sdfr ;; 1338171666Smarcel srlz.d 133966463Sdfr mov pr=r17,0x1ffff // restore predicates 134066463Sdfr rfi // walker will retry the access 1341171666Smarcel ;; 134266463Sdfr2: add r20=24,r20 // next in chain 134366463Sdfr ;; 134466463Sdfr ld8 r20=[r20] // read chain 1345219758Smarcel br.sptk 1b // loop 1346171666Smarcel ;; 1347171666Smarcel9: ssm psr.dt 1348171666Smarcel mov pr=r17,0x1ffff // restore predicates 1349171666Smarcel ;; 1350171666Smarcel srlz.d 1351171666Smarcel ;; 1352135783Smarcel CALL(trap, 10, cr.ifa) 1353105499SmarcelIVT_END(Data_Access_Bit) 135466458Sdfr 1355105499SmarcelIVT_ENTRY(Break_Instruction, 0x2c00) 1356115084Smarcel{ .mib 1357115084Smarcel mov r17=cr.iim 1358115084Smarcel mov r16=ip 1359115084Smarcel br.sptk exception_save 136067199Sdfr ;; 1361115084Smarcel} 1362115084Smarcel{ .mmi 1363115084Smarcel alloc r15=ar.pfs,0,0,2,0 1364115344Smarcel ;; 1365171739Smarcel(p11) ssm psr.i 1366115084Smarcel mov out0=11 1367115084Smarcel ;; 1368115084Smarcel} 1369171739Smarcel{ .mmi 1370171739Smarcel flushrs 1371171739Smarcel ;; 1372171739Smarcel(p11) srlz.d 1373115084Smarcel add out1=16,sp 1374171739Smarcel} 1375204184Smarcel{ .mib 1376171739Smarcel nop 0 1377171739Smarcel nop 0 1378115084Smarcel br.call.sptk rp=trap 1379115084Smarcel ;; 1380115084Smarcel} 1381204184Smarcel{ .mib 1382115084Smarcel nop 0 1383115084Smarcel nop 0 1384115084Smarcel br.sptk exception_restore 1385115084Smarcel ;; 1386115084Smarcel} 1387105499SmarcelIVT_END(Break_Instruction) 138866458Sdfr 1389105499SmarcelIVT_ENTRY(External_Interrupt, 0x3000) 1390115084Smarcel{ .mib 1391205433Smarcel mov r17=ar.itc // Put the ITC in the trapframe. 1392115084Smarcel mov r16=ip 1393115084Smarcel br.sptk exception_save 1394115084Smarcel ;; 1395115084Smarcel} 1396204184Smarcel{ .mmi 1397171739Smarcel alloc r15=ar.pfs,0,0,1,0 1398118402Smarcel nop 0 1399171739Smarcel nop 0 140067032Sdfr ;; 1401118402Smarcel} 1402204184Smarcel{ .mib 1403171739Smarcel add out0=16,sp 1404118402Smarcel nop 0 1405205234Smarcel br.call.sptk rp=ia64_handle_intr 1406115084Smarcel ;; 1407118402Smarcel} 1408204184Smarcel{ .mib 1409118402Smarcel nop 0 1410118402Smarcel nop 0 1411118402Smarcel br.sptk exception_restore 1412118402Smarcel ;; 1413118402Smarcel} 1414105499SmarcelIVT_END(External_Interrupt) 141567032Sdfr 1416105499SmarcelIVT_ENTRY(Reserved_3400, 0x3400) 1417135783Smarcel CALL(trap, 13, cr.ifa) 1418105499SmarcelIVT_END(Reserved_3400) 141966458Sdfr 1420105499SmarcelIVT_ENTRY(Reserved_3800, 0x3800) 1421135783Smarcel CALL(trap, 14, cr.ifa) 1422105499SmarcelIVT_END(Reserved_3800) 142366458Sdfr 1424105499SmarcelIVT_ENTRY(Reserved_3c00, 0x3c00) 1425135783Smarcel CALL(trap, 15, cr.ifa) 1426105499SmarcelIVT_END(Reserved_3c00) 142766458Sdfr 1428105499SmarcelIVT_ENTRY(Reserved_4000, 0x4000) 1429135783Smarcel CALL(trap, 16, cr.ifa) 1430105499SmarcelIVT_END(Reserved_4000) 143166458Sdfr 1432105499SmarcelIVT_ENTRY(Reserved_4400, 0x4400) 1433135783Smarcel CALL(trap, 17, cr.ifa) 1434105499SmarcelIVT_END(Reserved_4400) 143566458Sdfr 1436105499SmarcelIVT_ENTRY(Reserved_4800, 0x4800) 1437135783Smarcel CALL(trap, 18, cr.ifa) 1438105499SmarcelIVT_END(Reserved_4800) 143966458Sdfr 1440105499SmarcelIVT_ENTRY(Reserved_4c00, 0x4c00) 1441135783Smarcel CALL(trap, 19, cr.ifa) 1442105499SmarcelIVT_END(Reserved_4c00) 144366458Sdfr 1444105499SmarcelIVT_ENTRY(Page_Not_Present, 0x5000) 1445135783Smarcel CALL(trap, 20, cr.ifa) 1446105499SmarcelIVT_END(Page_Not_Present) 144766458Sdfr 1448105499SmarcelIVT_ENTRY(Key_Permission, 0x5100) 1449135783Smarcel CALL(trap, 21, cr.ifa) 1450105499SmarcelIVT_END(Key_Permission) 145166458Sdfr 1452105499SmarcelIVT_ENTRY(Instruction_Access_Rights, 0x5200) 1453135783Smarcel CALL(trap, 22, cr.ifa) 1454105499SmarcelIVT_END(Instruction_Access_Rights) 145566458Sdfr 1456105499SmarcelIVT_ENTRY(Data_Access_Rights, 0x5300) 1457135783Smarcel CALL(trap, 23, cr.ifa) 1458105499SmarcelIVT_END(Data_Access_Rights) 145966458Sdfr 1460105499SmarcelIVT_ENTRY(General_Exception, 0x5400) 1461135783Smarcel CALL(trap, 24, cr.ifa) 1462105499SmarcelIVT_END(General_Exception) 146366458Sdfr 1464105499SmarcelIVT_ENTRY(Disabled_FP_Register, 0x5500) 1465135783Smarcel CALL(trap, 25, cr.ifa) 1466105499SmarcelIVT_END(Disabled_FP_Register) 146766458Sdfr 1468105499SmarcelIVT_ENTRY(NaT_Consumption, 0x5600) 1469135783Smarcel CALL(trap, 26, cr.ifa) 1470105499SmarcelIVT_END(NaT_Consumption) 147166458Sdfr 1472105499SmarcelIVT_ENTRY(Speculation, 0x5700) 1473135783Smarcel CALL(trap, 27, cr.iim) 1474105499SmarcelIVT_END(Speculation) 147566458Sdfr 1476105499SmarcelIVT_ENTRY(Reserved_5800, 0x5800) 1477135783Smarcel CALL(trap, 28, cr.ifa) 1478105499SmarcelIVT_END(Reserved_5800) 147966458Sdfr 1480105499SmarcelIVT_ENTRY(Debug, 0x5900) 1481135783Smarcel CALL(trap, 29, cr.ifa) 1482105499SmarcelIVT_END(Debug) 148366458Sdfr 1484105499SmarcelIVT_ENTRY(Unaligned_Reference, 0x5a00) 1485135783Smarcel CALL(trap, 30, cr.ifa) 1486105499SmarcelIVT_END(Unaligned_Reference) 148766458Sdfr 1488105499SmarcelIVT_ENTRY(Unsupported_Data_Reference, 0x5b00) 1489135783Smarcel CALL(trap, 31, cr.ifa) 1490105499SmarcelIVT_END(Unsupported_Data_Reference) 149166458Sdfr 1492105499SmarcelIVT_ENTRY(Floating_Point_Fault, 0x5c00) 1493135783Smarcel CALL(trap, 32, cr.ifa) 1494105499SmarcelIVT_END(Floating_Point_Fault) 149566458Sdfr 1496105499SmarcelIVT_ENTRY(Floating_Point_Trap, 0x5d00) 1497135783Smarcel CALL(trap, 33, cr.ifa) 1498105499SmarcelIVT_END(Floating_Point_Trap) 149966458Sdfr 1500105499SmarcelIVT_ENTRY(Lower_Privilege_Transfer_Trap, 0x5e00) 1501135783Smarcel CALL(trap, 34, cr.ifa) 1502105499SmarcelIVT_END(Lower_Privilege_Transfer_Trap) 150366458Sdfr 1504105499SmarcelIVT_ENTRY(Taken_Branch_Trap, 0x5f00) 1505135783Smarcel CALL(trap, 35, cr.ifa) 1506105499SmarcelIVT_END(Taken_Branch_Trap) 150766458Sdfr 1508105499SmarcelIVT_ENTRY(Single_Step_Trap, 0x6000) 1509135783Smarcel CALL(trap, 36, cr.ifa) 1510105499SmarcelIVT_END(Single_Step_Trap) 151166458Sdfr 1512105499SmarcelIVT_ENTRY(Reserved_6100, 0x6100) 1513135783Smarcel CALL(trap, 37, cr.ifa) 1514105499SmarcelIVT_END(Reserved_6100) 151566458Sdfr 1516105499SmarcelIVT_ENTRY(Reserved_6200, 0x6200) 1517135783Smarcel CALL(trap, 38, cr.ifa) 1518105499SmarcelIVT_END(Reserved_6200) 151966458Sdfr 1520105499SmarcelIVT_ENTRY(Reserved_6300, 0x6300) 1521135783Smarcel CALL(trap, 39, cr.ifa) 1522105499SmarcelIVT_END(Reserved_6300) 152366458Sdfr 1524105499SmarcelIVT_ENTRY(Reserved_6400, 0x6400) 1525135783Smarcel CALL(trap, 40, cr.ifa) 1526105499SmarcelIVT_END(Reserved_6400) 152766458Sdfr 1528105499SmarcelIVT_ENTRY(Reserved_6500, 0x6500) 1529135783Smarcel CALL(trap, 41, cr.ifa) 1530105499SmarcelIVT_END(Reserved_6500) 153166458Sdfr 1532105499SmarcelIVT_ENTRY(Reserved_6600, 0x6600) 1533135783Smarcel CALL(trap, 42, cr.ifa) 1534105499SmarcelIVT_END(Reserved_6600) 153566458Sdfr 1536105499SmarcelIVT_ENTRY(Reserved_6700, 0x6700) 1537135783Smarcel CALL(trap, 43, cr.ifa) 1538105499SmarcelIVT_END(Reserved_6700) 153966458Sdfr 1540105499SmarcelIVT_ENTRY(Reserved_6800, 0x6800) 1541135783Smarcel CALL(trap, 44, cr.ifa) 1542105499SmarcelIVT_END(Reserved_6800) 154366458Sdfr 1544105499SmarcelIVT_ENTRY(IA_32_Exception, 0x6900) 1545135783Smarcel CALL(IA32_TRAP, 45, cr.ifa) 1546105499SmarcelIVT_END(IA_32_Exception) 154766458Sdfr 1548105499SmarcelIVT_ENTRY(IA_32_Intercept, 0x6a00) 1549135783Smarcel CALL(IA32_TRAP, 46, cr.iim) 1550105499SmarcelIVT_END(IA_32_Intercept) 155166458Sdfr 1552105499SmarcelIVT_ENTRY(IA_32_Interrupt, 0x6b00) 1553135783Smarcel CALL(IA32_TRAP, 47, cr.ifa) 1554105499SmarcelIVT_END(IA_32_Interrupt) 155566458Sdfr 1556105499SmarcelIVT_ENTRY(Reserved_6c00, 0x6c00) 1557135783Smarcel CALL(trap, 48, cr.ifa) 1558105499SmarcelIVT_END(Reserved_6c00) 155966458Sdfr 1560105499SmarcelIVT_ENTRY(Reserved_6d00, 0x6d00) 1561135783Smarcel CALL(trap, 49, cr.ifa) 1562105499SmarcelIVT_END(Reserved_6d00) 156366458Sdfr 1564105499SmarcelIVT_ENTRY(Reserved_6e00, 0x6e00) 1565135783Smarcel CALL(trap, 50, cr.ifa) 1566105499SmarcelIVT_END(Reserved_6e00) 156766458Sdfr 1568105499SmarcelIVT_ENTRY(Reserved_6f00, 0x6f00) 1569135783Smarcel CALL(trap, 51, cr.ifa) 1570105499SmarcelIVT_END(Reserved_6f00) 157166458Sdfr 1572105499SmarcelIVT_ENTRY(Reserved_7000, 0x7000) 1573135783Smarcel CALL(trap, 52, cr.ifa) 1574105499SmarcelIVT_END(Reserved_7000) 157566458Sdfr 1576105499SmarcelIVT_ENTRY(Reserved_7100, 0x7100) 1577135783Smarcel CALL(trap, 53, cr.ifa) 1578105499SmarcelIVT_END(Reserved_7100) 157966458Sdfr 1580105499SmarcelIVT_ENTRY(Reserved_7200, 0x7200) 1581135783Smarcel CALL(trap, 54, cr.ifa) 1582105499SmarcelIVT_END(Reserved_7200) 158366458Sdfr 1584105499SmarcelIVT_ENTRY(Reserved_7300, 0x7300) 1585135783Smarcel CALL(trap, 55, cr.ifa) 1586105499SmarcelIVT_END(Reserved_7300) 158766458Sdfr 1588105499SmarcelIVT_ENTRY(Reserved_7400, 0x7400) 1589135783Smarcel CALL(trap, 56, cr.ifa) 1590105499SmarcelIVT_END(Reserved_7400) 159166458Sdfr 1592105499SmarcelIVT_ENTRY(Reserved_7500, 0x7500) 1593135783Smarcel CALL(trap, 57, cr.ifa) 1594105499SmarcelIVT_END(Reserved_7500) 159566458Sdfr 1596105499SmarcelIVT_ENTRY(Reserved_7600, 0x7600) 1597135783Smarcel CALL(trap, 58, cr.ifa) 1598105499SmarcelIVT_END(Reserved_7600) 159966458Sdfr 1600105499SmarcelIVT_ENTRY(Reserved_7700, 0x7700) 1601135783Smarcel CALL(trap, 59, cr.ifa) 1602105499SmarcelIVT_END(Reserved_7700) 160366458Sdfr 1604105499SmarcelIVT_ENTRY(Reserved_7800, 0x7800) 1605135783Smarcel CALL(trap, 60, cr.ifa) 1606105499SmarcelIVT_END(Reserved_7800) 160766458Sdfr 1608105499SmarcelIVT_ENTRY(Reserved_7900, 0x7900) 1609135783Smarcel CALL(trap, 61, cr.ifa) 1610105499SmarcelIVT_END(Reserved_7900) 161166458Sdfr 1612105499SmarcelIVT_ENTRY(Reserved_7a00, 0x7a00) 1613135783Smarcel CALL(trap, 62, cr.ifa) 1614105499SmarcelIVT_END(Reserved_7a00) 161566458Sdfr 1616105499SmarcelIVT_ENTRY(Reserved_7b00, 0x7b00) 1617135783Smarcel CALL(trap, 63, cr.ifa) 1618105499SmarcelIVT_END(Reserved_7b00) 161966458Sdfr 1620105499SmarcelIVT_ENTRY(Reserved_7c00, 0x7c00) 1621135783Smarcel CALL(trap, 64, cr.ifa) 1622105499SmarcelIVT_END(Reserved_7c00) 162366458Sdfr 1624105499SmarcelIVT_ENTRY(Reserved_7d00, 0x7d00) 1625135783Smarcel CALL(trap, 65, cr.ifa) 1626105499SmarcelIVT_END(Reserved_7d00) 162766458Sdfr 1628105499SmarcelIVT_ENTRY(Reserved_7e00, 0x7e00) 1629135783Smarcel CALL(trap, 66, cr.ifa) 1630105499SmarcelIVT_END(Reserved_7e00) 163166458Sdfr 1632105499SmarcelIVT_ENTRY(Reserved_7f00, 0x7f00) 1633135783Smarcel CALL(trap, 67, cr.ifa) 1634105499SmarcelIVT_END(Reserved_7f00) 1635