pmap.c revision 240151
1181641Skmacy/*- 2181641Skmacy * Copyright (c) 1991 Regents of the University of California. 3181641Skmacy * All rights reserved. 4181641Skmacy * Copyright (c) 1994 John S. Dyson 5181641Skmacy * All rights reserved. 6181641Skmacy * Copyright (c) 1994 David Greenman 7181641Skmacy * All rights reserved. 8181641Skmacy * Copyright (c) 2005 Alan L. Cox <alc@cs.rice.edu> 9181641Skmacy * All rights reserved. 10181641Skmacy * 11181641Skmacy * This code is derived from software contributed to Berkeley by 12181641Skmacy * the Systems Programming Group of the University of Utah Computer 13181641Skmacy * Science Department and William Jolitz of UUNET Technologies Inc. 14181641Skmacy * 15181641Skmacy * Redistribution and use in source and binary forms, with or without 16181641Skmacy * modification, are permitted provided that the following conditions 17181641Skmacy * are met: 18181641Skmacy * 1. Redistributions of source code must retain the above copyright 19181641Skmacy * notice, this list of conditions and the following disclaimer. 20181641Skmacy * 2. Redistributions in binary form must reproduce the above copyright 21181641Skmacy * notice, this list of conditions and the following disclaimer in the 22181641Skmacy * documentation and/or other materials provided with the distribution. 23181641Skmacy * 3. All advertising materials mentioning features or use of this software 24181641Skmacy * must display the following acknowledgement: 25181641Skmacy * This product includes software developed by the University of 26181641Skmacy * California, Berkeley and its contributors. 27181641Skmacy * 4. Neither the name of the University nor the names of its contributors 28181641Skmacy * may be used to endorse or promote products derived from this software 29181641Skmacy * without specific prior written permission. 30181641Skmacy * 31181641Skmacy * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 32181641Skmacy * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 33181641Skmacy * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 34181641Skmacy * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 35181641Skmacy * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 36181641Skmacy * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 37181641Skmacy * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 38181641Skmacy * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 39181641Skmacy * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 40181641Skmacy * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 41181641Skmacy * SUCH DAMAGE. 42181641Skmacy * 43181641Skmacy * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91 44181641Skmacy */ 45181641Skmacy/*- 46181641Skmacy * Copyright (c) 2003 Networks Associates Technology, Inc. 47181641Skmacy * All rights reserved. 48181641Skmacy * 49181641Skmacy * This software was developed for the FreeBSD Project by Jake Burkholder, 50181641Skmacy * Safeport Network Services, and Network Associates Laboratories, the 51181641Skmacy * Security Research Division of Network Associates, Inc. under 52181641Skmacy * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA 53181641Skmacy * CHATS research program. 54181641Skmacy * 55181641Skmacy * Redistribution and use in source and binary forms, with or without 56181641Skmacy * modification, are permitted provided that the following conditions 57181641Skmacy * are met: 58181641Skmacy * 1. Redistributions of source code must retain the above copyright 59181641Skmacy * notice, this list of conditions and the following disclaimer. 60181641Skmacy * 2. Redistributions in binary form must reproduce the above copyright 61181641Skmacy * notice, this list of conditions and the following disclaimer in the 62181641Skmacy * documentation and/or other materials provided with the distribution. 63181641Skmacy * 64181641Skmacy * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 65181641Skmacy * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 66181641Skmacy * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 67181641Skmacy * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 68181641Skmacy * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 69181641Skmacy * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 70181641Skmacy * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 71181641Skmacy * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 72181641Skmacy * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 73181641Skmacy * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 74181641Skmacy * SUCH DAMAGE. 75181641Skmacy */ 76181641Skmacy 77181641Skmacy#include <sys/cdefs.h> 78181641Skmacy__FBSDID("$FreeBSD: stable/9/sys/i386/xen/pmap.c 240151 2012-09-05 20:40:11Z kib $"); 79181641Skmacy 80181641Skmacy/* 81181641Skmacy * Manages physical address maps. 82181641Skmacy * 83181641Skmacy * In addition to hardware address maps, this 84181641Skmacy * module is called upon to provide software-use-only 85181641Skmacy * maps which may or may not be stored in the same 86181641Skmacy * form as hardware maps. These pseudo-maps are 87181641Skmacy * used to store intermediate results from copy 88181641Skmacy * operations to and from address spaces. 89181641Skmacy * 90181641Skmacy * Since the information managed by this module is 91181641Skmacy * also stored by the logical address mapping module, 92181641Skmacy * this module may throw away valid virtual-to-physical 93181641Skmacy * mappings at almost any time. However, invalidations 94181641Skmacy * of virtual-to-physical mappings must be done as 95181641Skmacy * requested. 96181641Skmacy * 97181641Skmacy * In order to cope with hardware architectures which 98181641Skmacy * make virtual-to-physical map invalidates expensive, 99181641Skmacy * this module may delay invalidate or reduced protection 100181641Skmacy * operations until such time as they are actually 101181641Skmacy * necessary. This module is given full information as 102181641Skmacy * to which processors are currently using which maps, 103181641Skmacy * and to when physical maps must be made correct. 104181641Skmacy */ 105181641Skmacy 106181641Skmacy#include "opt_cpu.h" 107181641Skmacy#include "opt_pmap.h" 108181641Skmacy#include "opt_smp.h" 109181641Skmacy#include "opt_xbox.h" 110181641Skmacy 111181641Skmacy#include <sys/param.h> 112181641Skmacy#include <sys/systm.h> 113181641Skmacy#include <sys/kernel.h> 114181641Skmacy#include <sys/ktr.h> 115181641Skmacy#include <sys/lock.h> 116181641Skmacy#include <sys/malloc.h> 117181641Skmacy#include <sys/mman.h> 118181641Skmacy#include <sys/msgbuf.h> 119181641Skmacy#include <sys/mutex.h> 120181641Skmacy#include <sys/proc.h> 121195949Skib#include <sys/sf_buf.h> 122181641Skmacy#include <sys/sx.h> 123181641Skmacy#include <sys/vmmeter.h> 124181641Skmacy#include <sys/sched.h> 125181641Skmacy#include <sys/sysctl.h> 126181641Skmacy#ifdef SMP 127181641Skmacy#include <sys/smp.h> 128230435Salc#else 129230435Salc#include <sys/cpuset.h> 130181641Skmacy#endif 131181641Skmacy 132181641Skmacy#include <vm/vm.h> 133181641Skmacy#include <vm/vm_param.h> 134181641Skmacy#include <vm/vm_kern.h> 135181641Skmacy#include <vm/vm_page.h> 136181641Skmacy#include <vm/vm_map.h> 137181641Skmacy#include <vm/vm_object.h> 138181641Skmacy#include <vm/vm_extern.h> 139181641Skmacy#include <vm/vm_pageout.h> 140181641Skmacy#include <vm/vm_pager.h> 141181641Skmacy#include <vm/uma.h> 142181641Skmacy 143181641Skmacy#include <machine/cpu.h> 144181641Skmacy#include <machine/cputypes.h> 145181641Skmacy#include <machine/md_var.h> 146181641Skmacy#include <machine/pcb.h> 147181641Skmacy#include <machine/specialreg.h> 148181641Skmacy#ifdef SMP 149181641Skmacy#include <machine/smp.h> 150181641Skmacy#endif 151181641Skmacy 152181641Skmacy#ifdef XBOX 153181641Skmacy#include <machine/xbox.h> 154181641Skmacy#endif 155181641Skmacy 156181641Skmacy#include <xen/interface/xen.h> 157186557Skmacy#include <xen/hypervisor.h> 158181641Skmacy#include <machine/xen/hypercall.h> 159181641Skmacy#include <machine/xen/xenvar.h> 160181641Skmacy#include <machine/xen/xenfunc.h> 161181641Skmacy 162181641Skmacy#if !defined(CPU_DISABLE_SSE) && defined(I686_CPU) 163181641Skmacy#define CPU_ENABLE_SSE 164181641Skmacy#endif 165181641Skmacy 166181641Skmacy#ifndef PMAP_SHPGPERPROC 167181641Skmacy#define PMAP_SHPGPERPROC 200 168181641Skmacy#endif 169181641Skmacy 170208651Salc#define DIAGNOSTIC 171181641Skmacy 172208651Salc#if !defined(DIAGNOSTIC) 173204041Sed#ifdef __GNUC_GNU_INLINE__ 174208651Salc#define PMAP_INLINE __attribute__((__gnu_inline__)) inline 175204041Sed#else 176202628Sed#define PMAP_INLINE extern inline 177204041Sed#endif 178181641Skmacy#else 179181641Skmacy#define PMAP_INLINE 180181641Skmacy#endif 181181641Skmacy 182181641Skmacy#define PV_STATS 183181641Skmacy#ifdef PV_STATS 184181641Skmacy#define PV_STAT(x) do { x ; } while (0) 185181641Skmacy#else 186181641Skmacy#define PV_STAT(x) do { } while (0) 187181641Skmacy#endif 188181641Skmacy 189181641Skmacy/* 190181641Skmacy * Get PDEs and PTEs for user/kernel address space 191181641Skmacy */ 192181641Skmacy#define pmap_pde(m, v) (&((m)->pm_pdir[(vm_offset_t)(v) >> PDRSHIFT])) 193181641Skmacy#define pdir_pde(m, v) (m[(vm_offset_t)(v) >> PDRSHIFT]) 194181641Skmacy 195181641Skmacy#define pmap_pde_v(pte) ((*(int *)pte & PG_V) != 0) 196181641Skmacy#define pmap_pte_w(pte) ((*(int *)pte & PG_W) != 0) 197181641Skmacy#define pmap_pte_m(pte) ((*(int *)pte & PG_M) != 0) 198181641Skmacy#define pmap_pte_u(pte) ((*(int *)pte & PG_A) != 0) 199181641Skmacy#define pmap_pte_v(pte) ((*(int *)pte & PG_V) != 0) 200181641Skmacy 201181641Skmacy#define pmap_pte_set_prot(pte, v) ((*(int *)pte &= ~PG_PROT), (*(int *)pte |= (v))) 202181641Skmacy 203216960Scperciva#define HAMFISTED_LOCKING 204216960Scperciva#ifdef HAMFISTED_LOCKING 205216960Scpercivastatic struct mtx createdelete_lock; 206216960Scperciva#endif 207216960Scperciva 208181641Skmacystruct pmap kernel_pmap_store; 209181641SkmacyLIST_HEAD(pmaplist, pmap); 210181641Skmacystatic struct pmaplist allpmaps; 211181641Skmacystatic struct mtx allpmaps_lock; 212181641Skmacy 213181641Skmacyvm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */ 214181641Skmacyvm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */ 215181641Skmacyint pgeflag = 0; /* PG_G or-in */ 216181641Skmacyint pseflag = 0; /* PG_PS or-in */ 217181641Skmacy 218182902Skmacyint nkpt; 219181641Skmacyvm_offset_t kernel_vm_end; 220181641Skmacyextern u_int32_t KERNend; 221181641Skmacy 222181641Skmacy#ifdef PAE 223181641Skmacypt_entry_t pg_nx; 224181641Skmacy#endif 225181641Skmacy 226230435Salcstatic SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD, 0, "VM/pmap parameters"); 227230435Salc 228196726Sadrianstatic int pat_works; /* Is page attribute table sane? */ 229196726Sadrian 230181641Skmacy/* 231181641Skmacy * Data for the pv entry allocation mechanism 232181641Skmacy */ 233237950Salcstatic TAILQ_HEAD(pch, pv_chunk) pv_chunks = TAILQ_HEAD_INITIALIZER(pv_chunks); 234181641Skmacystatic int pv_entry_count = 0, pv_entry_max = 0, pv_entry_high_water = 0; 235181641Skmacystatic int shpgperproc = PMAP_SHPGPERPROC; 236181641Skmacy 237181641Skmacystruct pv_chunk *pv_chunkbase; /* KVA block for pv_chunks */ 238181641Skmacyint pv_maxchunks; /* How many chunks we have KVA for */ 239181641Skmacyvm_offset_t pv_vafree; /* freelist stored in the PTE */ 240181641Skmacy 241181641Skmacy/* 242181641Skmacy * All those kernel PT submaps that BSD is so fond of 243181641Skmacy */ 244181641Skmacystruct sysmaps { 245181641Skmacy struct mtx lock; 246181641Skmacy pt_entry_t *CMAP1; 247181641Skmacy pt_entry_t *CMAP2; 248181641Skmacy caddr_t CADDR1; 249181641Skmacy caddr_t CADDR2; 250181641Skmacy}; 251181641Skmacystatic struct sysmaps sysmaps_pcpu[MAXCPU]; 252181641Skmacystatic pt_entry_t *CMAP3; 253204160Skmacycaddr_t ptvmmap = 0; 254181641Skmacystatic caddr_t CADDR3; 255181641Skmacystruct msgbuf *msgbufp = 0; 256181641Skmacy 257181641Skmacy/* 258181641Skmacy * Crashdump maps. 259181641Skmacy */ 260181641Skmacystatic caddr_t crashdumpmap; 261181641Skmacy 262181641Skmacystatic pt_entry_t *PMAP1 = 0, *PMAP2; 263181641Skmacystatic pt_entry_t *PADDR1 = 0, *PADDR2; 264181641Skmacy#ifdef SMP 265181641Skmacystatic int PMAP1cpu; 266181641Skmacystatic int PMAP1changedcpu; 267181641SkmacySYSCTL_INT(_debug, OID_AUTO, PMAP1changedcpu, CTLFLAG_RD, 268181641Skmacy &PMAP1changedcpu, 0, 269181641Skmacy "Number of times pmap_pte_quick changed CPU with same PMAP1"); 270181641Skmacy#endif 271181641Skmacystatic int PMAP1changed; 272181641SkmacySYSCTL_INT(_debug, OID_AUTO, PMAP1changed, CTLFLAG_RD, 273181641Skmacy &PMAP1changed, 0, 274181641Skmacy "Number of times pmap_pte_quick changed PMAP1"); 275181641Skmacystatic int PMAP1unchanged; 276181641SkmacySYSCTL_INT(_debug, OID_AUTO, PMAP1unchanged, CTLFLAG_RD, 277181641Skmacy &PMAP1unchanged, 0, 278181641Skmacy "Number of times pmap_pte_quick didn't change PMAP1"); 279181641Skmacystatic struct mtx PMAP2mutex; 280181641Skmacy 281237950Salcstatic void free_pv_chunk(struct pv_chunk *pc); 282181641Skmacystatic void free_pv_entry(pmap_t pmap, pv_entry_t pv); 283237950Salcstatic pv_entry_t get_pv_entry(pmap_t pmap, boolean_t try); 284208651Salcstatic void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va); 285208651Salcstatic pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, 286208651Salc vm_offset_t va); 287181641Skmacy 288181641Skmacystatic vm_page_t pmap_enter_quick_locked(multicall_entry_t **mcl, int *count, pmap_t pmap, vm_offset_t va, 289181641Skmacy vm_page_t m, vm_prot_t prot, vm_page_t mpte); 290230435Salcstatic void pmap_flush_page(vm_page_t m); 291230435Salcstatic void pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode); 292181641Skmacystatic int pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t sva, 293181641Skmacy vm_page_t *free); 294181641Skmacystatic void pmap_remove_page(struct pmap *pmap, vm_offset_t va, 295181641Skmacy vm_page_t *free); 296181641Skmacystatic void pmap_remove_entry(struct pmap *pmap, vm_page_t m, 297181641Skmacy vm_offset_t va); 298181641Skmacystatic boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, 299181641Skmacy vm_page_t m); 300181641Skmacy 301181641Skmacystatic vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va, int flags); 302181641Skmacy 303230435Salcstatic vm_page_t _pmap_allocpte(pmap_t pmap, u_int ptepindex, int flags); 304240151Skibstatic void _pmap_unwire_ptp(pmap_t pmap, vm_page_t m, vm_page_t *free); 305181641Skmacystatic pt_entry_t *pmap_pte_quick(pmap_t pmap, vm_offset_t va); 306181641Skmacystatic void pmap_pte_release(pt_entry_t *pte); 307181641Skmacystatic int pmap_unuse_pt(pmap_t, vm_offset_t, vm_page_t *); 308181641Skmacystatic boolean_t pmap_is_prefaultable_locked(pmap_t pmap, vm_offset_t addr); 309181641Skmacy 310196725Sadrianstatic __inline void pagezero(void *page); 311181747Skmacy 312181641SkmacyCTASSERT(1 << PDESHIFT == sizeof(pd_entry_t)); 313181641SkmacyCTASSERT(1 << PTESHIFT == sizeof(pt_entry_t)); 314181641Skmacy 315181641Skmacy/* 316181641Skmacy * If you get an error here, then you set KVA_PAGES wrong! See the 317181641Skmacy * description of KVA_PAGES in sys/i386/include/pmap.h. It must be 318181641Skmacy * multiple of 4 for a normal kernel, or a multiple of 8 for a PAE. 319181641Skmacy */ 320181641SkmacyCTASSERT(KERNBASE % (1 << 24) == 0); 321181641Skmacy 322181641Skmacyvoid 323181641Skmacypd_set(struct pmap *pmap, int ptepindex, vm_paddr_t val, int type) 324181641Skmacy{ 325181641Skmacy vm_paddr_t pdir_ma = vtomach(&pmap->pm_pdir[ptepindex]); 326181641Skmacy 327181641Skmacy switch (type) { 328181641Skmacy case SH_PD_SET_VA: 329181641Skmacy#if 0 330181641Skmacy xen_queue_pt_update(shadow_pdir_ma, 331181641Skmacy xpmap_ptom(val & ~(PG_RW))); 332181641Skmacy#endif 333181641Skmacy xen_queue_pt_update(pdir_ma, 334181641Skmacy xpmap_ptom(val)); 335181641Skmacy break; 336181641Skmacy case SH_PD_SET_VA_MA: 337181641Skmacy#if 0 338181641Skmacy xen_queue_pt_update(shadow_pdir_ma, 339181641Skmacy val & ~(PG_RW)); 340181641Skmacy#endif 341181641Skmacy xen_queue_pt_update(pdir_ma, val); 342181641Skmacy break; 343181641Skmacy case SH_PD_SET_VA_CLEAR: 344181641Skmacy#if 0 345181641Skmacy xen_queue_pt_update(shadow_pdir_ma, 0); 346181641Skmacy#endif 347181641Skmacy xen_queue_pt_update(pdir_ma, 0); 348181641Skmacy break; 349181641Skmacy } 350181641Skmacy} 351181641Skmacy 352181641Skmacy/* 353181641Skmacy * Bootstrap the system enough to run with virtual memory. 354181641Skmacy * 355181641Skmacy * On the i386 this is called after mapping has already been enabled 356181641Skmacy * and just syncs the pmap module with what has already been done. 357181641Skmacy * [We can't call it easily with mapping off since the kernel is not 358181641Skmacy * mapped with PA == VA, hence we would have to relocate every address 359181641Skmacy * from the linked base (virtual) address "KERNBASE" to the actual 360181641Skmacy * (physical) address starting relative to 0] 361181641Skmacy */ 362181641Skmacyvoid 363181641Skmacypmap_bootstrap(vm_paddr_t firstaddr) 364181641Skmacy{ 365181641Skmacy vm_offset_t va; 366181641Skmacy pt_entry_t *pte, *unused; 367181641Skmacy struct sysmaps *sysmaps; 368181641Skmacy int i; 369181641Skmacy 370181641Skmacy /* 371230435Salc * Initialize the first available kernel virtual address. However, 372230435Salc * using "firstaddr" may waste a few pages of the kernel virtual 373230435Salc * address space, because locore may not have mapped every physical 374230435Salc * page that it allocated. Preferably, locore would provide a first 375230435Salc * unused virtual address in addition to "firstaddr". 376181641Skmacy */ 377181641Skmacy virtual_avail = (vm_offset_t) KERNBASE + firstaddr; 378181641Skmacy 379181641Skmacy virtual_end = VM_MAX_KERNEL_ADDRESS; 380181641Skmacy 381181641Skmacy /* 382181641Skmacy * Initialize the kernel pmap (which is statically allocated). 383181641Skmacy */ 384181641Skmacy PMAP_LOCK_INIT(kernel_pmap); 385181641Skmacy kernel_pmap->pm_pdir = (pd_entry_t *) (KERNBASE + (u_int)IdlePTD); 386181641Skmacy#ifdef PAE 387181641Skmacy kernel_pmap->pm_pdpt = (pdpt_entry_t *) (KERNBASE + (u_int)IdlePDPT); 388181641Skmacy#endif 389222813Sattilio CPU_FILL(&kernel_pmap->pm_active); /* don't allow deactivation */ 390181641Skmacy TAILQ_INIT(&kernel_pmap->pm_pvchunk); 391181641Skmacy LIST_INIT(&allpmaps); 392181641Skmacy mtx_init(&allpmaps_lock, "allpmaps", NULL, MTX_SPIN); 393181641Skmacy mtx_lock_spin(&allpmaps_lock); 394181641Skmacy LIST_INSERT_HEAD(&allpmaps, kernel_pmap, pm_list); 395181641Skmacy mtx_unlock_spin(&allpmaps_lock); 396183342Skmacy if (nkpt == 0) 397183342Skmacy nkpt = NKPT; 398181641Skmacy 399181641Skmacy /* 400181641Skmacy * Reserve some special page table entries/VA space for temporary 401181641Skmacy * mapping of pages. 402181641Skmacy */ 403181641Skmacy#define SYSMAP(c, p, v, n) \ 404181641Skmacy v = (c)va; va += ((n)*PAGE_SIZE); p = pte; pte += (n); 405181641Skmacy 406181641Skmacy va = virtual_avail; 407181641Skmacy pte = vtopte(va); 408181641Skmacy 409181641Skmacy /* 410181641Skmacy * CMAP1/CMAP2 are used for zeroing and copying pages. 411181641Skmacy * CMAP3 is used for the idle process page zeroing. 412181641Skmacy */ 413181641Skmacy for (i = 0; i < MAXCPU; i++) { 414181641Skmacy sysmaps = &sysmaps_pcpu[i]; 415181641Skmacy mtx_init(&sysmaps->lock, "SYSMAPS", NULL, MTX_DEF); 416181641Skmacy SYSMAP(caddr_t, sysmaps->CMAP1, sysmaps->CADDR1, 1) 417181641Skmacy SYSMAP(caddr_t, sysmaps->CMAP2, sysmaps->CADDR2, 1) 418204160Skmacy PT_SET_MA(sysmaps->CADDR1, 0); 419204160Skmacy PT_SET_MA(sysmaps->CADDR2, 0); 420181641Skmacy } 421181641Skmacy SYSMAP(caddr_t, CMAP3, CADDR3, 1) 422181641Skmacy PT_SET_MA(CADDR3, 0); 423181641Skmacy 424181641Skmacy /* 425181641Skmacy * Crashdump maps. 426181641Skmacy */ 427181641Skmacy SYSMAP(caddr_t, unused, crashdumpmap, MAXDUMPPGS) 428181641Skmacy 429181641Skmacy /* 430181641Skmacy * ptvmmap is used for reading arbitrary physical pages via /dev/mem. 431181641Skmacy */ 432181641Skmacy SYSMAP(caddr_t, unused, ptvmmap, 1) 433181641Skmacy 434181641Skmacy /* 435181641Skmacy * msgbufp is used to map the system message buffer. 436181641Skmacy */ 437217688Spluknet SYSMAP(struct msgbuf *, unused, msgbufp, atop(round_page(msgbufsize))) 438181641Skmacy 439181641Skmacy /* 440181641Skmacy * ptemap is used for pmap_pte_quick 441181641Skmacy */ 442230435Salc SYSMAP(pt_entry_t *, PMAP1, PADDR1, 1) 443230435Salc SYSMAP(pt_entry_t *, PMAP2, PADDR2, 1) 444181641Skmacy 445181641Skmacy mtx_init(&PMAP2mutex, "PMAP2", NULL, MTX_DEF); 446181641Skmacy 447181641Skmacy virtual_avail = va; 448181641Skmacy 449181641Skmacy /* 450181641Skmacy * Leave in place an identity mapping (virt == phys) for the low 1 MB 451181641Skmacy * physical memory region that is used by the ACPI wakeup code. This 452181641Skmacy * mapping must not have PG_G set. 453181641Skmacy */ 454181641Skmacy#ifndef XEN 455181641Skmacy /* 456181641Skmacy * leave here deliberately to show that this is not supported 457181641Skmacy */ 458181641Skmacy#ifdef XBOX 459181641Skmacy /* FIXME: This is gross, but needed for the XBOX. Since we are in such 460181641Skmacy * an early stadium, we cannot yet neatly map video memory ... :-( 461181641Skmacy * Better fixes are very welcome! */ 462181641Skmacy if (!arch_i386_is_xbox) 463181641Skmacy#endif 464181641Skmacy for (i = 1; i < NKPT; i++) 465181641Skmacy PTD[i] = 0; 466181641Skmacy 467181641Skmacy /* Initialize the PAT MSR if present. */ 468181641Skmacy pmap_init_pat(); 469181641Skmacy 470181641Skmacy /* Turn on PG_G on kernel page(s) */ 471181641Skmacy pmap_set_pg(); 472181641Skmacy#endif 473216960Scperciva 474216960Scperciva#ifdef HAMFISTED_LOCKING 475216960Scperciva mtx_init(&createdelete_lock, "pmap create/delete", NULL, MTX_DEF); 476216960Scperciva#endif 477181641Skmacy} 478181641Skmacy 479181641Skmacy/* 480181641Skmacy * Setup the PAT MSR. 481181641Skmacy */ 482181641Skmacyvoid 483181641Skmacypmap_init_pat(void) 484181641Skmacy{ 485181641Skmacy uint64_t pat_msr; 486181641Skmacy 487181641Skmacy /* Bail if this CPU doesn't implement PAT. */ 488181641Skmacy if (!(cpu_feature & CPUID_PAT)) 489181641Skmacy return; 490181641Skmacy 491196726Sadrian if (cpu_vendor_id != CPU_VENDOR_INTEL || 492197070Sjkim (CPUID_TO_FAMILY(cpu_id) == 6 && CPUID_TO_MODEL(cpu_id) >= 0xe)) { 493196726Sadrian /* 494196726Sadrian * Leave the indices 0-3 at the default of WB, WT, UC, and UC-. 495196726Sadrian * Program 4 and 5 as WP and WC. 496196726Sadrian * Leave 6 and 7 as UC and UC-. 497196726Sadrian */ 498196726Sadrian pat_msr = rdmsr(MSR_PAT); 499196726Sadrian pat_msr &= ~(PAT_MASK(4) | PAT_MASK(5)); 500196726Sadrian pat_msr |= PAT_VALUE(4, PAT_WRITE_PROTECTED) | 501196726Sadrian PAT_VALUE(5, PAT_WRITE_COMBINING); 502196726Sadrian pat_works = 1; 503196726Sadrian } else { 504196726Sadrian /* 505196726Sadrian * Due to some Intel errata, we can only safely use the lower 4 506196726Sadrian * PAT entries. Thus, just replace PAT Index 2 with WC instead 507196726Sadrian * of UC-. 508196726Sadrian * 509196726Sadrian * Intel Pentium III Processor Specification Update 510196726Sadrian * Errata E.27 (Upper Four PAT Entries Not Usable With Mode B 511196726Sadrian * or Mode C Paging) 512196726Sadrian * 513196726Sadrian * Intel Pentium IV Processor Specification Update 514196726Sadrian * Errata N46 (PAT Index MSB May Be Calculated Incorrectly) 515196726Sadrian */ 516196726Sadrian pat_msr = rdmsr(MSR_PAT); 517196726Sadrian pat_msr &= ~PAT_MASK(2); 518196726Sadrian pat_msr |= PAT_VALUE(2, PAT_WRITE_COMBINING); 519196726Sadrian pat_works = 0; 520196726Sadrian } 521181641Skmacy wrmsr(MSR_PAT, pat_msr); 522181641Skmacy} 523181641Skmacy 524181641Skmacy/* 525181641Skmacy * Initialize a vm_page's machine-dependent fields. 526181641Skmacy */ 527181641Skmacyvoid 528181641Skmacypmap_page_init(vm_page_t m) 529181641Skmacy{ 530181641Skmacy 531181641Skmacy TAILQ_INIT(&m->md.pv_list); 532195649Salc m->md.pat_mode = PAT_WRITE_BACK; 533181641Skmacy} 534181641Skmacy 535181641Skmacy/* 536181641Skmacy * ABuse the pte nodes for unmapped kva to thread a kva freelist through. 537181641Skmacy * Requirements: 538181641Skmacy * - Must deal with pages in order to ensure that none of the PG_* bits 539181641Skmacy * are ever set, PG_V in particular. 540181641Skmacy * - Assumes we can write to ptes without pte_store() atomic ops, even 541181641Skmacy * on PAE systems. This should be ok. 542181641Skmacy * - Assumes nothing will ever test these addresses for 0 to indicate 543181641Skmacy * no mapping instead of correctly checking PG_V. 544181641Skmacy * - Assumes a vm_offset_t will fit in a pte (true for i386). 545181641Skmacy * Because PG_V is never set, there can be no mappings to invalidate. 546181641Skmacy */ 547181641Skmacystatic int ptelist_count = 0; 548181641Skmacystatic vm_offset_t 549181641Skmacypmap_ptelist_alloc(vm_offset_t *head) 550181641Skmacy{ 551181641Skmacy vm_offset_t va; 552181641Skmacy vm_offset_t *phead = (vm_offset_t *)*head; 553181641Skmacy 554181641Skmacy if (ptelist_count == 0) { 555181641Skmacy printf("out of memory!!!!!!\n"); 556181641Skmacy return (0); /* Out of memory */ 557181641Skmacy } 558181641Skmacy ptelist_count--; 559181641Skmacy va = phead[ptelist_count]; 560181641Skmacy return (va); 561181641Skmacy} 562181641Skmacy 563181641Skmacystatic void 564181641Skmacypmap_ptelist_free(vm_offset_t *head, vm_offset_t va) 565181641Skmacy{ 566181641Skmacy vm_offset_t *phead = (vm_offset_t *)*head; 567181641Skmacy 568181641Skmacy phead[ptelist_count++] = va; 569181641Skmacy} 570181641Skmacy 571181641Skmacystatic void 572181641Skmacypmap_ptelist_init(vm_offset_t *head, void *base, int npages) 573181641Skmacy{ 574181641Skmacy int i, nstackpages; 575181641Skmacy vm_offset_t va; 576181641Skmacy vm_page_t m; 577181641Skmacy 578181641Skmacy nstackpages = (npages + PAGE_SIZE/sizeof(vm_offset_t) - 1)/ (PAGE_SIZE/sizeof(vm_offset_t)); 579181641Skmacy for (i = 0; i < nstackpages; i++) { 580181641Skmacy va = (vm_offset_t)base + i * PAGE_SIZE; 581181641Skmacy m = vm_page_alloc(NULL, i, 582181641Skmacy VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | 583181641Skmacy VM_ALLOC_ZERO); 584181641Skmacy pmap_qenter(va, &m, 1); 585181641Skmacy } 586181641Skmacy 587181641Skmacy *head = (vm_offset_t)base; 588181641Skmacy for (i = npages - 1; i >= nstackpages; i--) { 589181641Skmacy va = (vm_offset_t)base + i * PAGE_SIZE; 590181641Skmacy pmap_ptelist_free(head, va); 591181641Skmacy } 592181641Skmacy} 593181641Skmacy 594181641Skmacy 595181641Skmacy/* 596181641Skmacy * Initialize the pmap module. 597181641Skmacy * Called by vm_init, to initialize any structures that the pmap 598181641Skmacy * system needs to map virtual memory. 599181641Skmacy */ 600181641Skmacyvoid 601181641Skmacypmap_init(void) 602181641Skmacy{ 603181641Skmacy 604181641Skmacy /* 605181641Skmacy * Initialize the address space (zone) for the pv entries. Set a 606181641Skmacy * high water mark so that the system can recover from excessive 607181641Skmacy * numbers of pv entries. 608181641Skmacy */ 609181641Skmacy TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc); 610181641Skmacy pv_entry_max = shpgperproc * maxproc + cnt.v_page_count; 611181641Skmacy TUNABLE_INT_FETCH("vm.pmap.pv_entries", &pv_entry_max); 612181641Skmacy pv_entry_max = roundup(pv_entry_max, _NPCPV); 613181641Skmacy pv_entry_high_water = 9 * (pv_entry_max / 10); 614181641Skmacy 615181641Skmacy pv_maxchunks = MAX(pv_entry_max / _NPCPV, maxproc); 616181641Skmacy pv_chunkbase = (struct pv_chunk *)kmem_alloc_nofault(kernel_map, 617181641Skmacy PAGE_SIZE * pv_maxchunks); 618181641Skmacy if (pv_chunkbase == NULL) 619181641Skmacy panic("pmap_init: not enough kvm for pv chunks"); 620181641Skmacy pmap_ptelist_init(&pv_vafree, pv_chunkbase, pv_maxchunks); 621181641Skmacy} 622181641Skmacy 623181641Skmacy 624230435SalcSYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_max, CTLFLAG_RD, &pv_entry_max, 0, 625230435Salc "Max number of PV entries"); 626230435SalcSYSCTL_INT(_vm_pmap, OID_AUTO, shpgperproc, CTLFLAG_RD, &shpgperproc, 0, 627230435Salc "Page share factor per proc"); 628230435Salc 629230435Salcstatic SYSCTL_NODE(_vm_pmap, OID_AUTO, pde, CTLFLAG_RD, 0, 630230435Salc "2/4MB page mapping counters"); 631230435Salc 632230435Salcstatic u_long pmap_pde_mappings; 633230435SalcSYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, mappings, CTLFLAG_RD, 634230435Salc &pmap_pde_mappings, 0, "2/4MB page mappings"); 635230435Salc 636181641Skmacy/*************************************************** 637181641Skmacy * Low level helper routines..... 638181641Skmacy ***************************************************/ 639181641Skmacy 640181641Skmacy/* 641181641Skmacy * Determine the appropriate bits to set in a PTE or PDE for a specified 642181641Skmacy * caching mode. 643181641Skmacy */ 644195949Skibint 645181641Skmacypmap_cache_bits(int mode, boolean_t is_pde) 646181641Skmacy{ 647181641Skmacy int pat_flag, pat_index, cache_bits; 648181641Skmacy 649181641Skmacy /* The PAT bit is different for PTE's and PDE's. */ 650181641Skmacy pat_flag = is_pde ? PG_PDE_PAT : PG_PTE_PAT; 651181641Skmacy 652181641Skmacy /* If we don't support PAT, map extended modes to older ones. */ 653181641Skmacy if (!(cpu_feature & CPUID_PAT)) { 654181641Skmacy switch (mode) { 655181641Skmacy case PAT_UNCACHEABLE: 656181641Skmacy case PAT_WRITE_THROUGH: 657181641Skmacy case PAT_WRITE_BACK: 658181641Skmacy break; 659181641Skmacy case PAT_UNCACHED: 660181641Skmacy case PAT_WRITE_COMBINING: 661181641Skmacy case PAT_WRITE_PROTECTED: 662181641Skmacy mode = PAT_UNCACHEABLE; 663181641Skmacy break; 664181641Skmacy } 665181641Skmacy } 666181641Skmacy 667181641Skmacy /* Map the caching mode to a PAT index. */ 668196726Sadrian if (pat_works) { 669196726Sadrian switch (mode) { 670196726Sadrian case PAT_UNCACHEABLE: 671196726Sadrian pat_index = 3; 672196726Sadrian break; 673196726Sadrian case PAT_WRITE_THROUGH: 674196726Sadrian pat_index = 1; 675196726Sadrian break; 676196726Sadrian case PAT_WRITE_BACK: 677196726Sadrian pat_index = 0; 678196726Sadrian break; 679196726Sadrian case PAT_UNCACHED: 680196726Sadrian pat_index = 2; 681196726Sadrian break; 682196726Sadrian case PAT_WRITE_COMBINING: 683196726Sadrian pat_index = 5; 684196726Sadrian break; 685196726Sadrian case PAT_WRITE_PROTECTED: 686196726Sadrian pat_index = 4; 687196726Sadrian break; 688196726Sadrian default: 689196726Sadrian panic("Unknown caching mode %d\n", mode); 690196726Sadrian } 691196726Sadrian } else { 692196726Sadrian switch (mode) { 693196726Sadrian case PAT_UNCACHED: 694196726Sadrian case PAT_UNCACHEABLE: 695196726Sadrian case PAT_WRITE_PROTECTED: 696196726Sadrian pat_index = 3; 697196726Sadrian break; 698196726Sadrian case PAT_WRITE_THROUGH: 699196726Sadrian pat_index = 1; 700196726Sadrian break; 701196726Sadrian case PAT_WRITE_BACK: 702196726Sadrian pat_index = 0; 703196726Sadrian break; 704196726Sadrian case PAT_WRITE_COMBINING: 705196726Sadrian pat_index = 2; 706196726Sadrian break; 707196726Sadrian default: 708196726Sadrian panic("Unknown caching mode %d\n", mode); 709196726Sadrian } 710181641Skmacy } 711181641Skmacy 712181641Skmacy /* Map the 3-bit index value into the PAT, PCD, and PWT bits. */ 713181641Skmacy cache_bits = 0; 714181641Skmacy if (pat_index & 0x4) 715181641Skmacy cache_bits |= pat_flag; 716181641Skmacy if (pat_index & 0x2) 717181641Skmacy cache_bits |= PG_NC_PCD; 718181641Skmacy if (pat_index & 0x1) 719181641Skmacy cache_bits |= PG_NC_PWT; 720181641Skmacy return (cache_bits); 721181641Skmacy} 722181641Skmacy#ifdef SMP 723181641Skmacy/* 724181641Skmacy * For SMP, these functions have to use the IPI mechanism for coherence. 725181641Skmacy * 726181641Skmacy * N.B.: Before calling any of the following TLB invalidation functions, 727181641Skmacy * the calling processor must ensure that all stores updating a non- 728181641Skmacy * kernel page table are globally performed. Otherwise, another 729181641Skmacy * processor could cache an old, pre-update entry without being 730181641Skmacy * invalidated. This can happen one of two ways: (1) The pmap becomes 731181641Skmacy * active on another processor after its pm_active field is checked by 732181641Skmacy * one of the following functions but before a store updating the page 733181641Skmacy * table is globally performed. (2) The pmap becomes active on another 734181641Skmacy * processor before its pm_active field is checked but due to 735181641Skmacy * speculative loads one of the following functions stills reads the 736181641Skmacy * pmap as inactive on the other processor. 737181641Skmacy * 738181641Skmacy * The kernel page table is exempt because its pm_active field is 739181641Skmacy * immutable. The kernel page table is always active on every 740181641Skmacy * processor. 741181641Skmacy */ 742181641Skmacyvoid 743181641Skmacypmap_invalidate_page(pmap_t pmap, vm_offset_t va) 744181641Skmacy{ 745223758Sattilio cpuset_t other_cpus; 746223758Sattilio u_int cpuid; 747181641Skmacy 748181641Skmacy CTR2(KTR_PMAP, "pmap_invalidate_page: pmap=%p va=0x%x", 749181641Skmacy pmap, va); 750181641Skmacy 751181641Skmacy sched_pin(); 752222813Sattilio if (pmap == kernel_pmap || !CPU_CMP(&pmap->pm_active, &all_cpus)) { 753181641Skmacy invlpg(va); 754181641Skmacy smp_invlpg(va); 755181641Skmacy } else { 756223758Sattilio cpuid = PCPU_GET(cpuid); 757223758Sattilio other_cpus = all_cpus; 758223758Sattilio CPU_CLR(cpuid, &other_cpus); 759223758Sattilio if (CPU_ISSET(cpuid, &pmap->pm_active)) 760181641Skmacy invlpg(va); 761222813Sattilio CPU_AND(&other_cpus, &pmap->pm_active); 762222813Sattilio if (!CPU_EMPTY(&other_cpus)) 763222813Sattilio smp_masked_invlpg(other_cpus, va); 764181641Skmacy } 765181641Skmacy sched_unpin(); 766181641Skmacy PT_UPDATES_FLUSH(); 767181641Skmacy} 768181641Skmacy 769181641Skmacyvoid 770181641Skmacypmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 771181641Skmacy{ 772223758Sattilio cpuset_t other_cpus; 773181641Skmacy vm_offset_t addr; 774223758Sattilio u_int cpuid; 775181641Skmacy 776181641Skmacy CTR3(KTR_PMAP, "pmap_invalidate_page: pmap=%p eva=0x%x sva=0x%x", 777181641Skmacy pmap, sva, eva); 778181641Skmacy 779181641Skmacy sched_pin(); 780222813Sattilio if (pmap == kernel_pmap || !CPU_CMP(&pmap->pm_active, &all_cpus)) { 781181641Skmacy for (addr = sva; addr < eva; addr += PAGE_SIZE) 782181641Skmacy invlpg(addr); 783181641Skmacy smp_invlpg_range(sva, eva); 784181641Skmacy } else { 785223758Sattilio cpuid = PCPU_GET(cpuid); 786223758Sattilio other_cpus = all_cpus; 787223758Sattilio CPU_CLR(cpuid, &other_cpus); 788223758Sattilio if (CPU_ISSET(cpuid, &pmap->pm_active)) 789181641Skmacy for (addr = sva; addr < eva; addr += PAGE_SIZE) 790181641Skmacy invlpg(addr); 791222813Sattilio CPU_AND(&other_cpus, &pmap->pm_active); 792222813Sattilio if (!CPU_EMPTY(&other_cpus)) 793222813Sattilio smp_masked_invlpg_range(other_cpus, sva, eva); 794181641Skmacy } 795181641Skmacy sched_unpin(); 796181641Skmacy PT_UPDATES_FLUSH(); 797181641Skmacy} 798181641Skmacy 799181641Skmacyvoid 800181641Skmacypmap_invalidate_all(pmap_t pmap) 801181641Skmacy{ 802223758Sattilio cpuset_t other_cpus; 803223758Sattilio u_int cpuid; 804181641Skmacy 805181641Skmacy CTR1(KTR_PMAP, "pmap_invalidate_page: pmap=%p", pmap); 806181641Skmacy 807181641Skmacy sched_pin(); 808222813Sattilio if (pmap == kernel_pmap || !CPU_CMP(&pmap->pm_active, &all_cpus)) { 809181641Skmacy invltlb(); 810181641Skmacy smp_invltlb(); 811181641Skmacy } else { 812223758Sattilio cpuid = PCPU_GET(cpuid); 813223758Sattilio other_cpus = all_cpus; 814223758Sattilio CPU_CLR(cpuid, &other_cpus); 815223758Sattilio if (CPU_ISSET(cpuid, &pmap->pm_active)) 816181641Skmacy invltlb(); 817222813Sattilio CPU_AND(&other_cpus, &pmap->pm_active); 818222813Sattilio if (!CPU_EMPTY(&other_cpus)) 819222813Sattilio smp_masked_invltlb(other_cpus); 820181641Skmacy } 821181641Skmacy sched_unpin(); 822181641Skmacy} 823181641Skmacy 824181641Skmacyvoid 825181641Skmacypmap_invalidate_cache(void) 826181641Skmacy{ 827181641Skmacy 828181641Skmacy sched_pin(); 829181641Skmacy wbinvd(); 830181641Skmacy smp_cache_flush(); 831181641Skmacy sched_unpin(); 832181641Skmacy} 833181641Skmacy#else /* !SMP */ 834181641Skmacy/* 835181641Skmacy * Normal, non-SMP, 486+ invalidation functions. 836181641Skmacy * We inline these within pmap.c for speed. 837181641Skmacy */ 838181641SkmacyPMAP_INLINE void 839181641Skmacypmap_invalidate_page(pmap_t pmap, vm_offset_t va) 840181641Skmacy{ 841181641Skmacy CTR2(KTR_PMAP, "pmap_invalidate_page: pmap=%p va=0x%x", 842181641Skmacy pmap, va); 843181641Skmacy 844222813Sattilio if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active)) 845181641Skmacy invlpg(va); 846181641Skmacy PT_UPDATES_FLUSH(); 847181641Skmacy} 848181641Skmacy 849181641SkmacyPMAP_INLINE void 850181641Skmacypmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 851181641Skmacy{ 852181641Skmacy vm_offset_t addr; 853181641Skmacy 854181641Skmacy if (eva - sva > PAGE_SIZE) 855181641Skmacy CTR3(KTR_PMAP, "pmap_invalidate_range: pmap=%p sva=0x%x eva=0x%x", 856181641Skmacy pmap, sva, eva); 857181641Skmacy 858222813Sattilio if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active)) 859181641Skmacy for (addr = sva; addr < eva; addr += PAGE_SIZE) 860181641Skmacy invlpg(addr); 861181641Skmacy PT_UPDATES_FLUSH(); 862181641Skmacy} 863181641Skmacy 864181641SkmacyPMAP_INLINE void 865181641Skmacypmap_invalidate_all(pmap_t pmap) 866181641Skmacy{ 867181641Skmacy 868181641Skmacy CTR1(KTR_PMAP, "pmap_invalidate_all: pmap=%p", pmap); 869181641Skmacy 870222813Sattilio if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active)) 871181641Skmacy invltlb(); 872181641Skmacy} 873181641Skmacy 874181641SkmacyPMAP_INLINE void 875181641Skmacypmap_invalidate_cache(void) 876181641Skmacy{ 877181641Skmacy 878181641Skmacy wbinvd(); 879181641Skmacy} 880181641Skmacy#endif /* !SMP */ 881181641Skmacy 882230435Salc#define PMAP_CLFLUSH_THRESHOLD (2 * 1024 * 1024) 883230435Salc 884195949Skibvoid 885195949Skibpmap_invalidate_cache_range(vm_offset_t sva, vm_offset_t eva) 886195949Skib{ 887195949Skib 888195949Skib KASSERT((sva & PAGE_MASK) == 0, 889195949Skib ("pmap_invalidate_cache_range: sva not page-aligned")); 890195949Skib KASSERT((eva & PAGE_MASK) == 0, 891195949Skib ("pmap_invalidate_cache_range: eva not page-aligned")); 892195949Skib 893195949Skib if (cpu_feature & CPUID_SS) 894195949Skib ; /* If "Self Snoop" is supported, do nothing. */ 895230435Salc else if ((cpu_feature & CPUID_CLFSH) != 0 && 896230435Salc eva - sva < PMAP_CLFLUSH_THRESHOLD) { 897195949Skib 898195949Skib /* 899195949Skib * Otherwise, do per-cache line flush. Use the mfence 900195949Skib * instruction to insure that previous stores are 901195949Skib * included in the write-back. The processor 902195949Skib * propagates flush to other processors in the cache 903195949Skib * coherence domain. 904195949Skib */ 905195949Skib mfence(); 906197046Skib for (; sva < eva; sva += cpu_clflush_line_size) 907197046Skib clflush(sva); 908195949Skib mfence(); 909195949Skib } else { 910195949Skib 911195949Skib /* 912195949Skib * No targeted cache flush methods are supported by CPU, 913230435Salc * or the supplied range is bigger than 2MB. 914230435Salc * Globally invalidate cache. 915195949Skib */ 916195949Skib pmap_invalidate_cache(); 917195949Skib } 918195949Skib} 919195949Skib 920230435Salcvoid 921230435Salcpmap_invalidate_cache_pages(vm_page_t *pages, int count) 922230435Salc{ 923230435Salc int i; 924230435Salc 925230435Salc if (count >= PMAP_CLFLUSH_THRESHOLD / PAGE_SIZE || 926230435Salc (cpu_feature & CPUID_CLFSH) == 0) { 927230435Salc pmap_invalidate_cache(); 928230435Salc } else { 929230435Salc for (i = 0; i < count; i++) 930230435Salc pmap_flush_page(pages[i]); 931230435Salc } 932230435Salc} 933230435Salc 934181641Skmacy/* 935181641Skmacy * Are we current address space or kernel? N.B. We return FALSE when 936181641Skmacy * a pmap's page table is in use because a kernel thread is borrowing 937181641Skmacy * it. The borrowed page table can change spontaneously, making any 938181641Skmacy * dependence on its continued use subject to a race condition. 939181641Skmacy */ 940181641Skmacystatic __inline int 941181641Skmacypmap_is_current(pmap_t pmap) 942181641Skmacy{ 943181641Skmacy 944181641Skmacy return (pmap == kernel_pmap || 945181641Skmacy (pmap == vmspace_pmap(curthread->td_proc->p_vmspace) && 946230435Salc (pmap->pm_pdir[PTDPTDI] & PG_FRAME) == (PTDpde[0] & PG_FRAME))); 947181641Skmacy} 948181641Skmacy 949181641Skmacy/* 950181641Skmacy * If the given pmap is not the current or kernel pmap, the returned pte must 951181641Skmacy * be released by passing it to pmap_pte_release(). 952181641Skmacy */ 953181641Skmacypt_entry_t * 954181641Skmacypmap_pte(pmap_t pmap, vm_offset_t va) 955181641Skmacy{ 956181641Skmacy pd_entry_t newpf; 957181641Skmacy pd_entry_t *pde; 958181641Skmacy 959181641Skmacy pde = pmap_pde(pmap, va); 960181641Skmacy if (*pde & PG_PS) 961181641Skmacy return (pde); 962181641Skmacy if (*pde != 0) { 963181641Skmacy /* are we current address space or kernel? */ 964181641Skmacy if (pmap_is_current(pmap)) 965181641Skmacy return (vtopte(va)); 966181641Skmacy mtx_lock(&PMAP2mutex); 967181641Skmacy newpf = *pde & PG_FRAME; 968181641Skmacy if ((*PMAP2 & PG_FRAME) != newpf) { 969204160Skmacy vm_page_lock_queues(); 970181641Skmacy PT_SET_MA(PADDR2, newpf | PG_V | PG_A | PG_M); 971204160Skmacy vm_page_unlock_queues(); 972181641Skmacy CTR3(KTR_PMAP, "pmap_pte: pmap=%p va=0x%x newpte=0x%08x", 973181641Skmacy pmap, va, (*PMAP2 & 0xffffffff)); 974181641Skmacy } 975181641Skmacy return (PADDR2 + (i386_btop(va) & (NPTEPG - 1))); 976181641Skmacy } 977230435Salc return (NULL); 978181641Skmacy} 979181641Skmacy 980181641Skmacy/* 981181641Skmacy * Releases a pte that was obtained from pmap_pte(). Be prepared for the pte 982181641Skmacy * being NULL. 983181641Skmacy */ 984181641Skmacystatic __inline void 985181641Skmacypmap_pte_release(pt_entry_t *pte) 986181641Skmacy{ 987181641Skmacy 988181641Skmacy if ((pt_entry_t *)((vm_offset_t)pte & ~PAGE_MASK) == PADDR2) { 989181641Skmacy CTR1(KTR_PMAP, "pmap_pte_release: pte=0x%jx", 990181641Skmacy *PMAP2); 991216703Scperciva vm_page_lock_queues(); 992181641Skmacy PT_SET_VA(PMAP2, 0, TRUE); 993216703Scperciva vm_page_unlock_queues(); 994181641Skmacy mtx_unlock(&PMAP2mutex); 995181641Skmacy } 996181641Skmacy} 997181641Skmacy 998181641Skmacystatic __inline void 999181641Skmacyinvlcaddr(void *caddr) 1000181641Skmacy{ 1001181641Skmacy 1002181641Skmacy invlpg((u_int)caddr); 1003181641Skmacy PT_UPDATES_FLUSH(); 1004181641Skmacy} 1005181641Skmacy 1006181641Skmacy/* 1007181641Skmacy * Super fast pmap_pte routine best used when scanning 1008181641Skmacy * the pv lists. This eliminates many coarse-grained 1009181641Skmacy * invltlb calls. Note that many of the pv list 1010181641Skmacy * scans are across different pmaps. It is very wasteful 1011181641Skmacy * to do an entire invltlb for checking a single mapping. 1012181641Skmacy * 1013181641Skmacy * If the given pmap is not the current pmap, vm_page_queue_mtx 1014181641Skmacy * must be held and curthread pinned to a CPU. 1015181641Skmacy */ 1016181641Skmacystatic pt_entry_t * 1017181641Skmacypmap_pte_quick(pmap_t pmap, vm_offset_t va) 1018181641Skmacy{ 1019181641Skmacy pd_entry_t newpf; 1020181641Skmacy pd_entry_t *pde; 1021181641Skmacy 1022181641Skmacy pde = pmap_pde(pmap, va); 1023181641Skmacy if (*pde & PG_PS) 1024181641Skmacy return (pde); 1025181641Skmacy if (*pde != 0) { 1026181641Skmacy /* are we current address space or kernel? */ 1027181641Skmacy if (pmap_is_current(pmap)) 1028181641Skmacy return (vtopte(va)); 1029181641Skmacy mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1030181641Skmacy KASSERT(curthread->td_pinned > 0, ("curthread not pinned")); 1031181641Skmacy newpf = *pde & PG_FRAME; 1032181641Skmacy if ((*PMAP1 & PG_FRAME) != newpf) { 1033181641Skmacy PT_SET_MA(PADDR1, newpf | PG_V | PG_A | PG_M); 1034181641Skmacy CTR3(KTR_PMAP, "pmap_pte_quick: pmap=%p va=0x%x newpte=0x%08x", 1035181641Skmacy pmap, va, (u_long)*PMAP1); 1036181641Skmacy 1037181641Skmacy#ifdef SMP 1038181641Skmacy PMAP1cpu = PCPU_GET(cpuid); 1039181641Skmacy#endif 1040181641Skmacy PMAP1changed++; 1041181641Skmacy } else 1042181641Skmacy#ifdef SMP 1043181641Skmacy if (PMAP1cpu != PCPU_GET(cpuid)) { 1044181641Skmacy PMAP1cpu = PCPU_GET(cpuid); 1045181641Skmacy invlcaddr(PADDR1); 1046181641Skmacy PMAP1changedcpu++; 1047181641Skmacy } else 1048181641Skmacy#endif 1049181641Skmacy PMAP1unchanged++; 1050181641Skmacy return (PADDR1 + (i386_btop(va) & (NPTEPG - 1))); 1051181641Skmacy } 1052181641Skmacy return (0); 1053181641Skmacy} 1054181641Skmacy 1055181641Skmacy/* 1056181641Skmacy * Routine: pmap_extract 1057181641Skmacy * Function: 1058181641Skmacy * Extract the physical page address associated 1059181641Skmacy * with the given map/virtual_address pair. 1060181641Skmacy */ 1061181641Skmacyvm_paddr_t 1062181641Skmacypmap_extract(pmap_t pmap, vm_offset_t va) 1063181641Skmacy{ 1064181641Skmacy vm_paddr_t rtval; 1065181641Skmacy pt_entry_t *pte; 1066181641Skmacy pd_entry_t pde; 1067181641Skmacy pt_entry_t pteval; 1068230435Salc 1069181641Skmacy rtval = 0; 1070181641Skmacy PMAP_LOCK(pmap); 1071181641Skmacy pde = pmap->pm_pdir[va >> PDRSHIFT]; 1072181641Skmacy if (pde != 0) { 1073181641Skmacy if ((pde & PG_PS) != 0) { 1074181641Skmacy rtval = xpmap_mtop(pde & PG_PS_FRAME) | (va & PDRMASK); 1075181641Skmacy PMAP_UNLOCK(pmap); 1076181641Skmacy return rtval; 1077181641Skmacy } 1078181641Skmacy pte = pmap_pte(pmap, va); 1079181641Skmacy pteval = *pte ? xpmap_mtop(*pte) : 0; 1080181641Skmacy rtval = (pteval & PG_FRAME) | (va & PAGE_MASK); 1081181641Skmacy pmap_pte_release(pte); 1082181641Skmacy } 1083181641Skmacy PMAP_UNLOCK(pmap); 1084181641Skmacy return (rtval); 1085181641Skmacy} 1086181641Skmacy 1087181641Skmacy/* 1088181641Skmacy * Routine: pmap_extract_ma 1089181641Skmacy * Function: 1090181641Skmacy * Like pmap_extract, but returns machine address 1091181641Skmacy */ 1092181641Skmacyvm_paddr_t 1093181641Skmacypmap_extract_ma(pmap_t pmap, vm_offset_t va) 1094181641Skmacy{ 1095181641Skmacy vm_paddr_t rtval; 1096181641Skmacy pt_entry_t *pte; 1097181641Skmacy pd_entry_t pde; 1098181641Skmacy 1099181641Skmacy rtval = 0; 1100181641Skmacy PMAP_LOCK(pmap); 1101181641Skmacy pde = pmap->pm_pdir[va >> PDRSHIFT]; 1102181641Skmacy if (pde != 0) { 1103181641Skmacy if ((pde & PG_PS) != 0) { 1104181641Skmacy rtval = (pde & ~PDRMASK) | (va & PDRMASK); 1105181641Skmacy PMAP_UNLOCK(pmap); 1106181641Skmacy return rtval; 1107181641Skmacy } 1108181641Skmacy pte = pmap_pte(pmap, va); 1109181641Skmacy rtval = (*pte & PG_FRAME) | (va & PAGE_MASK); 1110181641Skmacy pmap_pte_release(pte); 1111181641Skmacy } 1112181641Skmacy PMAP_UNLOCK(pmap); 1113181641Skmacy return (rtval); 1114181641Skmacy} 1115181641Skmacy 1116181641Skmacy/* 1117181641Skmacy * Routine: pmap_extract_and_hold 1118181641Skmacy * Function: 1119181641Skmacy * Atomically extract and hold the physical page 1120181641Skmacy * with the given pmap and virtual address pair 1121181641Skmacy * if that mapping permits the given protection. 1122181641Skmacy */ 1123181641Skmacyvm_page_t 1124181641Skmacypmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot) 1125181641Skmacy{ 1126181641Skmacy pd_entry_t pde; 1127230435Salc pt_entry_t pte, *ptep; 1128181641Skmacy vm_page_t m; 1129207410Skmacy vm_paddr_t pa; 1130181641Skmacy 1131207410Skmacy pa = 0; 1132181641Skmacy m = NULL; 1133181641Skmacy PMAP_LOCK(pmap); 1134207410Skmacyretry: 1135181641Skmacy pde = PT_GET(pmap_pde(pmap, va)); 1136181641Skmacy if (pde != 0) { 1137181641Skmacy if (pde & PG_PS) { 1138181641Skmacy if ((pde & PG_RW) || (prot & VM_PROT_WRITE) == 0) { 1139230435Salc if (vm_page_pa_tryrelock(pmap, (pde & 1140230435Salc PG_PS_FRAME) | (va & PDRMASK), &pa)) 1141207410Skmacy goto retry; 1142181641Skmacy m = PHYS_TO_VM_PAGE((pde & PG_PS_FRAME) | 1143181641Skmacy (va & PDRMASK)); 1144181641Skmacy vm_page_hold(m); 1145181641Skmacy } 1146181641Skmacy } else { 1147230435Salc ptep = pmap_pte(pmap, va); 1148230435Salc pte = PT_GET(ptep); 1149230435Salc pmap_pte_release(ptep); 1150230435Salc if (pte != 0 && 1151181641Skmacy ((pte & PG_RW) || (prot & VM_PROT_WRITE) == 0)) { 1152230435Salc if (vm_page_pa_tryrelock(pmap, pte & PG_FRAME, 1153230435Salc &pa)) 1154207410Skmacy goto retry; 1155181641Skmacy m = PHYS_TO_VM_PAGE(pte & PG_FRAME); 1156181641Skmacy vm_page_hold(m); 1157181641Skmacy } 1158181641Skmacy } 1159181641Skmacy } 1160207410Skmacy PA_UNLOCK_COND(pa); 1161181641Skmacy PMAP_UNLOCK(pmap); 1162181641Skmacy return (m); 1163181641Skmacy} 1164181641Skmacy 1165181641Skmacy/*************************************************** 1166181641Skmacy * Low level mapping routines..... 1167181641Skmacy ***************************************************/ 1168181641Skmacy 1169181641Skmacy/* 1170181641Skmacy * Add a wired page to the kva. 1171181641Skmacy * Note: not SMP coherent. 1172230435Salc * 1173230435Salc * This function may be used before pmap_bootstrap() is called. 1174181641Skmacy */ 1175181747Skmacyvoid 1176181641Skmacypmap_kenter(vm_offset_t va, vm_paddr_t pa) 1177181641Skmacy{ 1178230435Salc 1179181641Skmacy PT_SET_MA(va, xpmap_ptom(pa)| PG_RW | PG_V | pgeflag); 1180181641Skmacy} 1181181641Skmacy 1182181747Skmacyvoid 1183181641Skmacypmap_kenter_ma(vm_offset_t va, vm_paddr_t ma) 1184181641Skmacy{ 1185181641Skmacy pt_entry_t *pte; 1186181641Skmacy 1187181641Skmacy pte = vtopte(va); 1188181641Skmacy pte_store_ma(pte, ma | PG_RW | PG_V | pgeflag); 1189181641Skmacy} 1190181641Skmacy 1191230435Salcstatic __inline void 1192181641Skmacypmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode) 1193181641Skmacy{ 1194230435Salc 1195181641Skmacy PT_SET_MA(va, pa | PG_RW | PG_V | pgeflag | pmap_cache_bits(mode, 0)); 1196181641Skmacy} 1197181641Skmacy 1198181641Skmacy/* 1199181641Skmacy * Remove a page from the kernel pagetables. 1200181641Skmacy * Note: not SMP coherent. 1201230435Salc * 1202230435Salc * This function may be used before pmap_bootstrap() is called. 1203181641Skmacy */ 1204181641SkmacyPMAP_INLINE void 1205181641Skmacypmap_kremove(vm_offset_t va) 1206181641Skmacy{ 1207181641Skmacy pt_entry_t *pte; 1208181641Skmacy 1209181641Skmacy pte = vtopte(va); 1210181641Skmacy PT_CLEAR_VA(pte, FALSE); 1211181641Skmacy} 1212181641Skmacy 1213181641Skmacy/* 1214181641Skmacy * Used to map a range of physical addresses into kernel 1215181641Skmacy * virtual address space. 1216181641Skmacy * 1217181641Skmacy * The value passed in '*virt' is a suggested virtual address for 1218181641Skmacy * the mapping. Architectures which can support a direct-mapped 1219181641Skmacy * physical to virtual region can return the appropriate address 1220181641Skmacy * within that region, leaving '*virt' unchanged. Other 1221181641Skmacy * architectures should map the pages starting at '*virt' and 1222181641Skmacy * update '*virt' with the first usable address after the mapped 1223181641Skmacy * region. 1224181641Skmacy */ 1225181641Skmacyvm_offset_t 1226181641Skmacypmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot) 1227181641Skmacy{ 1228181641Skmacy vm_offset_t va, sva; 1229181641Skmacy 1230181641Skmacy va = sva = *virt; 1231181641Skmacy CTR4(KTR_PMAP, "pmap_map: va=0x%x start=0x%jx end=0x%jx prot=0x%x", 1232181641Skmacy va, start, end, prot); 1233181641Skmacy while (start < end) { 1234181641Skmacy pmap_kenter(va, start); 1235181641Skmacy va += PAGE_SIZE; 1236181641Skmacy start += PAGE_SIZE; 1237181641Skmacy } 1238181641Skmacy pmap_invalidate_range(kernel_pmap, sva, va); 1239181641Skmacy *virt = va; 1240181641Skmacy return (sva); 1241181641Skmacy} 1242181641Skmacy 1243181641Skmacy 1244181641Skmacy/* 1245181641Skmacy * Add a list of wired pages to the kva 1246181641Skmacy * this routine is only used for temporary 1247181641Skmacy * kernel mappings that do not need to have 1248181641Skmacy * page modification or references recorded. 1249181641Skmacy * Note that old mappings are simply written 1250181641Skmacy * over. The page *must* be wired. 1251181641Skmacy * Note: SMP coherent. Uses a ranged shootdown IPI. 1252181641Skmacy */ 1253181641Skmacyvoid 1254181641Skmacypmap_qenter(vm_offset_t sva, vm_page_t *ma, int count) 1255181641Skmacy{ 1256181641Skmacy pt_entry_t *endpte, *pte; 1257181641Skmacy vm_paddr_t pa; 1258181641Skmacy vm_offset_t va = sva; 1259181641Skmacy int mclcount = 0; 1260181641Skmacy multicall_entry_t mcl[16]; 1261181641Skmacy multicall_entry_t *mclp = mcl; 1262181641Skmacy int error; 1263181641Skmacy 1264181641Skmacy CTR2(KTR_PMAP, "pmap_qenter:sva=0x%x count=%d", va, count); 1265181641Skmacy pte = vtopte(sva); 1266181641Skmacy endpte = pte + count; 1267181641Skmacy while (pte < endpte) { 1268215587Scperciva pa = VM_PAGE_TO_MACH(*ma) | pgeflag | PG_RW | PG_V | PG_M | PG_A; 1269181641Skmacy 1270181641Skmacy mclp->op = __HYPERVISOR_update_va_mapping; 1271181641Skmacy mclp->args[0] = va; 1272181641Skmacy mclp->args[1] = (uint32_t)(pa & 0xffffffff); 1273181641Skmacy mclp->args[2] = (uint32_t)(pa >> 32); 1274181641Skmacy mclp->args[3] = (*pte & PG_V) ? UVMF_INVLPG|UVMF_ALL : 0; 1275181641Skmacy 1276181641Skmacy va += PAGE_SIZE; 1277181641Skmacy pte++; 1278181641Skmacy ma++; 1279181641Skmacy mclp++; 1280181641Skmacy mclcount++; 1281181641Skmacy if (mclcount == 16) { 1282181641Skmacy error = HYPERVISOR_multicall(mcl, mclcount); 1283181641Skmacy mclp = mcl; 1284181641Skmacy mclcount = 0; 1285181641Skmacy KASSERT(error == 0, ("bad multicall %d", error)); 1286181641Skmacy } 1287181641Skmacy } 1288181641Skmacy if (mclcount) { 1289181641Skmacy error = HYPERVISOR_multicall(mcl, mclcount); 1290181641Skmacy KASSERT(error == 0, ("bad multicall %d", error)); 1291181641Skmacy } 1292181641Skmacy 1293181641Skmacy#ifdef INVARIANTS 1294181641Skmacy for (pte = vtopte(sva), mclcount = 0; mclcount < count; mclcount++, pte++) 1295181641Skmacy KASSERT(*pte, ("pte not set for va=0x%x", sva + mclcount*PAGE_SIZE)); 1296181641Skmacy#endif 1297181641Skmacy} 1298181641Skmacy 1299181641Skmacy/* 1300181641Skmacy * This routine tears out page mappings from the 1301181641Skmacy * kernel -- it is meant only for temporary mappings. 1302181641Skmacy * Note: SMP coherent. Uses a ranged shootdown IPI. 1303181641Skmacy */ 1304181641Skmacyvoid 1305181641Skmacypmap_qremove(vm_offset_t sva, int count) 1306181641Skmacy{ 1307181641Skmacy vm_offset_t va; 1308181641Skmacy 1309181641Skmacy CTR2(KTR_PMAP, "pmap_qremove: sva=0x%x count=%d", sva, count); 1310181641Skmacy va = sva; 1311181641Skmacy vm_page_lock_queues(); 1312181641Skmacy critical_enter(); 1313181641Skmacy while (count-- > 0) { 1314181641Skmacy pmap_kremove(va); 1315181641Skmacy va += PAGE_SIZE; 1316181641Skmacy } 1317215844Scperciva PT_UPDATES_FLUSH(); 1318181641Skmacy pmap_invalidate_range(kernel_pmap, sva, va); 1319181641Skmacy critical_exit(); 1320181641Skmacy vm_page_unlock_queues(); 1321181641Skmacy} 1322181641Skmacy 1323181641Skmacy/*************************************************** 1324181641Skmacy * Page table page management routines..... 1325181641Skmacy ***************************************************/ 1326181641Skmacystatic __inline void 1327181641Skmacypmap_free_zero_pages(vm_page_t free) 1328181641Skmacy{ 1329181641Skmacy vm_page_t m; 1330181641Skmacy 1331181641Skmacy while (free != NULL) { 1332181641Skmacy m = free; 1333181641Skmacy free = m->right; 1334181641Skmacy vm_page_free_zero(m); 1335181641Skmacy } 1336181641Skmacy} 1337181641Skmacy 1338181641Skmacy/* 1339240151Skib * Decrements a page table page's wire count, which is used to record the 1340240151Skib * number of valid page table entries within the page. If the wire count 1341240151Skib * drops to zero, then the page table page is unmapped. Returns TRUE if the 1342240151Skib * page table page was unmapped and FALSE otherwise. 1343181641Skmacy */ 1344240151Skibstatic inline boolean_t 1345240151Skibpmap_unwire_ptp(pmap_t pmap, vm_page_t m, vm_page_t *free) 1346181641Skmacy{ 1347181641Skmacy 1348181641Skmacy --m->wire_count; 1349240151Skib if (m->wire_count == 0) { 1350240151Skib _pmap_unwire_ptp(pmap, m, free); 1351240151Skib return (TRUE); 1352240151Skib } else 1353240151Skib return (FALSE); 1354181641Skmacy} 1355181641Skmacy 1356240151Skibstatic void 1357240151Skib_pmap_unwire_ptp(pmap_t pmap, vm_page_t m, vm_page_t *free) 1358181641Skmacy{ 1359181641Skmacy vm_offset_t pteva; 1360181641Skmacy 1361181641Skmacy PT_UPDATES_FLUSH(); 1362181641Skmacy /* 1363181641Skmacy * unmap the page table page 1364181641Skmacy */ 1365181641Skmacy xen_pt_unpin(pmap->pm_pdir[m->pindex]); 1366181641Skmacy /* 1367181641Skmacy * page *might* contain residual mapping :-/ 1368181641Skmacy */ 1369181641Skmacy PD_CLEAR_VA(pmap, m->pindex, TRUE); 1370181641Skmacy pmap_zero_page(m); 1371181641Skmacy --pmap->pm_stats.resident_count; 1372181641Skmacy 1373181641Skmacy /* 1374181641Skmacy * This is a release store so that the ordinary store unmapping 1375181641Skmacy * the page table page is globally performed before TLB shoot- 1376181641Skmacy * down is begun. 1377181641Skmacy */ 1378181641Skmacy atomic_subtract_rel_int(&cnt.v_wire_count, 1); 1379181641Skmacy 1380181641Skmacy /* 1381181641Skmacy * Do an invltlb to make the invalidated mapping 1382181641Skmacy * take effect immediately. 1383181641Skmacy */ 1384181641Skmacy pteva = VM_MAXUSER_ADDRESS + i386_ptob(m->pindex); 1385181641Skmacy pmap_invalidate_page(pmap, pteva); 1386181641Skmacy 1387181641Skmacy /* 1388181641Skmacy * Put page on a list so that it is released after 1389181641Skmacy * *ALL* TLB shootdown is done 1390181641Skmacy */ 1391181641Skmacy m->right = *free; 1392181641Skmacy *free = m; 1393181641Skmacy} 1394181641Skmacy 1395181641Skmacy/* 1396181641Skmacy * After removing a page table entry, this routine is used to 1397181641Skmacy * conditionally free the page, and manage the hold/wire counts. 1398181641Skmacy */ 1399181641Skmacystatic int 1400181641Skmacypmap_unuse_pt(pmap_t pmap, vm_offset_t va, vm_page_t *free) 1401181641Skmacy{ 1402181641Skmacy pd_entry_t ptepde; 1403181641Skmacy vm_page_t mpte; 1404181641Skmacy 1405181641Skmacy if (va >= VM_MAXUSER_ADDRESS) 1406230435Salc return (0); 1407181641Skmacy ptepde = PT_GET(pmap_pde(pmap, va)); 1408181641Skmacy mpte = PHYS_TO_VM_PAGE(ptepde & PG_FRAME); 1409240151Skib return (pmap_unwire_ptp(pmap, mpte, free)); 1410181641Skmacy} 1411181641Skmacy 1412230435Salc/* 1413230435Salc * Initialize the pmap for the swapper process. 1414230435Salc */ 1415181641Skmacyvoid 1416181641Skmacypmap_pinit0(pmap_t pmap) 1417181641Skmacy{ 1418181641Skmacy 1419181641Skmacy PMAP_LOCK_INIT(pmap); 1420230435Salc /* 1421230435Salc * Since the page table directory is shared with the kernel pmap, 1422230435Salc * which is already included in the list "allpmaps", this pmap does 1423230435Salc * not need to be inserted into that list. 1424230435Salc */ 1425181641Skmacy pmap->pm_pdir = (pd_entry_t *)(KERNBASE + (vm_offset_t)IdlePTD); 1426181641Skmacy#ifdef PAE 1427181641Skmacy pmap->pm_pdpt = (pdpt_entry_t *)(KERNBASE + (vm_offset_t)IdlePDPT); 1428181641Skmacy#endif 1429222813Sattilio CPU_ZERO(&pmap->pm_active); 1430181641Skmacy PCPU_SET(curpmap, pmap); 1431181641Skmacy TAILQ_INIT(&pmap->pm_pvchunk); 1432181641Skmacy bzero(&pmap->pm_stats, sizeof pmap->pm_stats); 1433181641Skmacy} 1434181641Skmacy 1435181641Skmacy/* 1436181641Skmacy * Initialize a preallocated and zeroed pmap structure, 1437181641Skmacy * such as one in a vmspace structure. 1438181641Skmacy */ 1439181641Skmacyint 1440181641Skmacypmap_pinit(pmap_t pmap) 1441181641Skmacy{ 1442181641Skmacy vm_page_t m, ptdpg[NPGPTD + 1]; 1443181641Skmacy int npgptd = NPGPTD + 1; 1444181641Skmacy int i; 1445181641Skmacy 1446216960Scperciva#ifdef HAMFISTED_LOCKING 1447216960Scperciva mtx_lock(&createdelete_lock); 1448216960Scperciva#endif 1449216960Scperciva 1450181641Skmacy PMAP_LOCK_INIT(pmap); 1451181641Skmacy 1452181641Skmacy /* 1453181641Skmacy * No need to allocate page table space yet but we do need a valid 1454181641Skmacy * page directory table. 1455181641Skmacy */ 1456181641Skmacy if (pmap->pm_pdir == NULL) { 1457181641Skmacy pmap->pm_pdir = (pd_entry_t *)kmem_alloc_nofault(kernel_map, 1458181641Skmacy NBPTD); 1459181641Skmacy if (pmap->pm_pdir == NULL) { 1460181641Skmacy PMAP_LOCK_DESTROY(pmap); 1461216960Scperciva#ifdef HAMFISTED_LOCKING 1462216960Scperciva mtx_unlock(&createdelete_lock); 1463216960Scperciva#endif 1464181641Skmacy return (0); 1465181641Skmacy } 1466215593Scperciva#ifdef PAE 1467181641Skmacy pmap->pm_pdpt = (pd_entry_t *)kmem_alloc_nofault(kernel_map, 1); 1468181641Skmacy#endif 1469181641Skmacy } 1470181641Skmacy 1471181641Skmacy /* 1472181641Skmacy * allocate the page directory page(s) 1473181641Skmacy */ 1474181641Skmacy for (i = 0; i < npgptd;) { 1475237949Salc m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ | 1476237949Salc VM_ALLOC_WIRED | VM_ALLOC_ZERO); 1477181641Skmacy if (m == NULL) 1478181641Skmacy VM_WAIT; 1479181641Skmacy else { 1480181641Skmacy ptdpg[i++] = m; 1481181641Skmacy } 1482181641Skmacy } 1483230435Salc 1484181641Skmacy pmap_qenter((vm_offset_t)pmap->pm_pdir, ptdpg, NPGPTD); 1485230435Salc 1486230435Salc for (i = 0; i < NPGPTD; i++) 1487181641Skmacy if ((ptdpg[i]->flags & PG_ZERO) == 0) 1488230435Salc pagezero(pmap->pm_pdir + (i * NPDEPG)); 1489181641Skmacy 1490181641Skmacy mtx_lock_spin(&allpmaps_lock); 1491181641Skmacy LIST_INSERT_HEAD(&allpmaps, pmap, pm_list); 1492230435Salc /* Copy the kernel page table directory entries. */ 1493230435Salc bcopy(PTD + KPTDI, pmap->pm_pdir + KPTDI, nkpt * sizeof(pd_entry_t)); 1494181641Skmacy mtx_unlock_spin(&allpmaps_lock); 1495181641Skmacy 1496181641Skmacy#ifdef PAE 1497181641Skmacy pmap_qenter((vm_offset_t)pmap->pm_pdpt, &ptdpg[NPGPTD], 1); 1498181641Skmacy if ((ptdpg[NPGPTD]->flags & PG_ZERO) == 0) 1499181641Skmacy bzero(pmap->pm_pdpt, PAGE_SIZE); 1500181641Skmacy for (i = 0; i < NPGPTD; i++) { 1501181641Skmacy vm_paddr_t ma; 1502181641Skmacy 1503215587Scperciva ma = VM_PAGE_TO_MACH(ptdpg[i]); 1504181641Skmacy pmap->pm_pdpt[i] = ma | PG_V; 1505181641Skmacy 1506181641Skmacy } 1507181641Skmacy#endif 1508181641Skmacy for (i = 0; i < NPGPTD; i++) { 1509181641Skmacy pt_entry_t *pd; 1510181641Skmacy vm_paddr_t ma; 1511181641Skmacy 1512215587Scperciva ma = VM_PAGE_TO_MACH(ptdpg[i]); 1513181641Skmacy pd = pmap->pm_pdir + (i * NPDEPG); 1514181641Skmacy PT_SET_MA(pd, *vtopte((vm_offset_t)pd) & ~(PG_M|PG_A|PG_U|PG_RW)); 1515181641Skmacy#if 0 1516181641Skmacy xen_pgd_pin(ma); 1517181641Skmacy#endif 1518181641Skmacy } 1519181641Skmacy 1520181641Skmacy#ifdef PAE 1521181641Skmacy PT_SET_MA(pmap->pm_pdpt, *vtopte((vm_offset_t)pmap->pm_pdpt) & ~PG_RW); 1522181641Skmacy#endif 1523181641Skmacy vm_page_lock_queues(); 1524181641Skmacy xen_flush_queue(); 1525215587Scperciva xen_pgdpt_pin(VM_PAGE_TO_MACH(ptdpg[NPGPTD])); 1526181641Skmacy for (i = 0; i < NPGPTD; i++) { 1527215587Scperciva vm_paddr_t ma = VM_PAGE_TO_MACH(ptdpg[i]); 1528181641Skmacy PT_SET_VA_MA(&pmap->pm_pdir[PTDPTDI + i], ma | PG_V | PG_A, FALSE); 1529181641Skmacy } 1530181641Skmacy xen_flush_queue(); 1531181641Skmacy vm_page_unlock_queues(); 1532222813Sattilio CPU_ZERO(&pmap->pm_active); 1533181641Skmacy TAILQ_INIT(&pmap->pm_pvchunk); 1534181641Skmacy bzero(&pmap->pm_stats, sizeof pmap->pm_stats); 1535181641Skmacy 1536216960Scperciva#ifdef HAMFISTED_LOCKING 1537216960Scperciva mtx_unlock(&createdelete_lock); 1538216960Scperciva#endif 1539181641Skmacy return (1); 1540181641Skmacy} 1541181641Skmacy 1542181641Skmacy/* 1543181641Skmacy * this routine is called if the page table page is not 1544181641Skmacy * mapped correctly. 1545181641Skmacy */ 1546181641Skmacystatic vm_page_t 1547230435Salc_pmap_allocpte(pmap_t pmap, u_int ptepindex, int flags) 1548181641Skmacy{ 1549181641Skmacy vm_paddr_t ptema; 1550181641Skmacy vm_page_t m; 1551181641Skmacy 1552181641Skmacy KASSERT((flags & (M_NOWAIT | M_WAITOK)) == M_NOWAIT || 1553181641Skmacy (flags & (M_NOWAIT | M_WAITOK)) == M_WAITOK, 1554181641Skmacy ("_pmap_allocpte: flags is neither M_NOWAIT nor M_WAITOK")); 1555181641Skmacy 1556181641Skmacy /* 1557181641Skmacy * Allocate a page table page. 1558181641Skmacy */ 1559181641Skmacy if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ | 1560181641Skmacy VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) { 1561181641Skmacy if (flags & M_WAITOK) { 1562181641Skmacy PMAP_UNLOCK(pmap); 1563181641Skmacy vm_page_unlock_queues(); 1564181641Skmacy VM_WAIT; 1565181641Skmacy vm_page_lock_queues(); 1566181641Skmacy PMAP_LOCK(pmap); 1567181641Skmacy } 1568181641Skmacy 1569181641Skmacy /* 1570181641Skmacy * Indicate the need to retry. While waiting, the page table 1571181641Skmacy * page may have been allocated. 1572181641Skmacy */ 1573181641Skmacy return (NULL); 1574181641Skmacy } 1575181641Skmacy if ((m->flags & PG_ZERO) == 0) 1576181641Skmacy pmap_zero_page(m); 1577181641Skmacy 1578181641Skmacy /* 1579181641Skmacy * Map the pagetable page into the process address space, if 1580181641Skmacy * it isn't already there. 1581181641Skmacy */ 1582230435Salc 1583181641Skmacy pmap->pm_stats.resident_count++; 1584181641Skmacy 1585215587Scperciva ptema = VM_PAGE_TO_MACH(m); 1586181641Skmacy xen_pt_pin(ptema); 1587181641Skmacy PT_SET_VA_MA(&pmap->pm_pdir[ptepindex], 1588181641Skmacy (ptema | PG_U | PG_RW | PG_V | PG_A | PG_M), TRUE); 1589181641Skmacy 1590181641Skmacy KASSERT(pmap->pm_pdir[ptepindex], 1591181641Skmacy ("_pmap_allocpte: ptepindex=%d did not get mapped", ptepindex)); 1592181641Skmacy return (m); 1593181641Skmacy} 1594181641Skmacy 1595181641Skmacystatic vm_page_t 1596181641Skmacypmap_allocpte(pmap_t pmap, vm_offset_t va, int flags) 1597181641Skmacy{ 1598230435Salc u_int ptepindex; 1599181641Skmacy pd_entry_t ptema; 1600181641Skmacy vm_page_t m; 1601181641Skmacy 1602181641Skmacy KASSERT((flags & (M_NOWAIT | M_WAITOK)) == M_NOWAIT || 1603181641Skmacy (flags & (M_NOWAIT | M_WAITOK)) == M_WAITOK, 1604181641Skmacy ("pmap_allocpte: flags is neither M_NOWAIT nor M_WAITOK")); 1605181641Skmacy 1606181641Skmacy /* 1607181641Skmacy * Calculate pagetable page index 1608181641Skmacy */ 1609181641Skmacy ptepindex = va >> PDRSHIFT; 1610181641Skmacyretry: 1611181641Skmacy /* 1612181641Skmacy * Get the page directory entry 1613181641Skmacy */ 1614181641Skmacy ptema = pmap->pm_pdir[ptepindex]; 1615181641Skmacy 1616181641Skmacy /* 1617181641Skmacy * This supports switching from a 4MB page to a 1618181641Skmacy * normal 4K page. 1619181641Skmacy */ 1620181641Skmacy if (ptema & PG_PS) { 1621181641Skmacy /* 1622181641Skmacy * XXX 1623181641Skmacy */ 1624181641Skmacy pmap->pm_pdir[ptepindex] = 0; 1625181641Skmacy ptema = 0; 1626181641Skmacy pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE; 1627181641Skmacy pmap_invalidate_all(kernel_pmap); 1628181641Skmacy } 1629181641Skmacy 1630181641Skmacy /* 1631181641Skmacy * If the page table page is mapped, we just increment the 1632181641Skmacy * hold count, and activate it. 1633181641Skmacy */ 1634181641Skmacy if (ptema & PG_V) { 1635181641Skmacy m = PHYS_TO_VM_PAGE(xpmap_mtop(ptema) & PG_FRAME); 1636181641Skmacy m->wire_count++; 1637181641Skmacy } else { 1638181641Skmacy /* 1639181641Skmacy * Here if the pte page isn't mapped, or if it has 1640181641Skmacy * been deallocated. 1641181641Skmacy */ 1642181641Skmacy CTR3(KTR_PMAP, "pmap_allocpte: pmap=%p va=0x%08x flags=0x%x", 1643181641Skmacy pmap, va, flags); 1644181641Skmacy m = _pmap_allocpte(pmap, ptepindex, flags); 1645181641Skmacy if (m == NULL && (flags & M_WAITOK)) 1646181641Skmacy goto retry; 1647181641Skmacy 1648181641Skmacy KASSERT(pmap->pm_pdir[ptepindex], ("ptepindex=%d did not get mapped", ptepindex)); 1649181641Skmacy } 1650181641Skmacy return (m); 1651181641Skmacy} 1652181641Skmacy 1653181641Skmacy 1654181641Skmacy/*************************************************** 1655181641Skmacy* Pmap allocation/deallocation routines. 1656181641Skmacy ***************************************************/ 1657181641Skmacy 1658181641Skmacy#ifdef SMP 1659181641Skmacy/* 1660181641Skmacy * Deal with a SMP shootdown of other users of the pmap that we are 1661181641Skmacy * trying to dispose of. This can be a bit hairy. 1662181641Skmacy */ 1663222813Sattiliostatic cpuset_t *lazymask; 1664181641Skmacystatic u_int lazyptd; 1665181641Skmacystatic volatile u_int lazywait; 1666181641Skmacy 1667181641Skmacyvoid pmap_lazyfix_action(void); 1668181641Skmacy 1669181641Skmacyvoid 1670181641Skmacypmap_lazyfix_action(void) 1671181641Skmacy{ 1672181641Skmacy 1673181641Skmacy#ifdef COUNT_IPIS 1674181641Skmacy (*ipi_lazypmap_counts[PCPU_GET(cpuid)])++; 1675181641Skmacy#endif 1676181641Skmacy if (rcr3() == lazyptd) 1677181641Skmacy load_cr3(PCPU_GET(curpcb)->pcb_cr3); 1678222813Sattilio CPU_CLR_ATOMIC(PCPU_GET(cpuid), lazymask); 1679181641Skmacy atomic_store_rel_int(&lazywait, 1); 1680181641Skmacy} 1681181641Skmacy 1682181641Skmacystatic void 1683223758Sattiliopmap_lazyfix_self(u_int cpuid) 1684181641Skmacy{ 1685181641Skmacy 1686181641Skmacy if (rcr3() == lazyptd) 1687181641Skmacy load_cr3(PCPU_GET(curpcb)->pcb_cr3); 1688223758Sattilio CPU_CLR_ATOMIC(cpuid, lazymask); 1689181641Skmacy} 1690181641Skmacy 1691181641Skmacy 1692181641Skmacystatic void 1693181641Skmacypmap_lazyfix(pmap_t pmap) 1694181641Skmacy{ 1695222813Sattilio cpuset_t mymask, mask; 1696223758Sattilio u_int cpuid, spins; 1697222813Sattilio int lsb; 1698181641Skmacy 1699222813Sattilio mask = pmap->pm_active; 1700222813Sattilio while (!CPU_EMPTY(&mask)) { 1701181641Skmacy spins = 50000000; 1702222813Sattilio 1703222813Sattilio /* Find least significant set bit. */ 1704222813Sattilio lsb = cpusetobj_ffs(&mask); 1705222813Sattilio MPASS(lsb != 0); 1706222813Sattilio lsb--; 1707222813Sattilio CPU_SETOF(lsb, &mask); 1708181641Skmacy mtx_lock_spin(&smp_ipi_mtx); 1709181641Skmacy#ifdef PAE 1710181641Skmacy lazyptd = vtophys(pmap->pm_pdpt); 1711181641Skmacy#else 1712181641Skmacy lazyptd = vtophys(pmap->pm_pdir); 1713181641Skmacy#endif 1714223758Sattilio cpuid = PCPU_GET(cpuid); 1715223758Sattilio 1716223758Sattilio /* Use a cpuset just for having an easy check. */ 1717223758Sattilio CPU_SETOF(cpuid, &mymask); 1718222813Sattilio if (!CPU_CMP(&mask, &mymask)) { 1719181641Skmacy lazymask = &pmap->pm_active; 1720223758Sattilio pmap_lazyfix_self(cpuid); 1721181641Skmacy } else { 1722181641Skmacy atomic_store_rel_int((u_int *)&lazymask, 1723181641Skmacy (u_int)&pmap->pm_active); 1724181641Skmacy atomic_store_rel_int(&lazywait, 0); 1725181641Skmacy ipi_selected(mask, IPI_LAZYPMAP); 1726181641Skmacy while (lazywait == 0) { 1727181641Skmacy ia32_pause(); 1728181641Skmacy if (--spins == 0) 1729181641Skmacy break; 1730181641Skmacy } 1731181641Skmacy } 1732181641Skmacy mtx_unlock_spin(&smp_ipi_mtx); 1733181641Skmacy if (spins == 0) 1734181641Skmacy printf("pmap_lazyfix: spun for 50000000\n"); 1735222813Sattilio mask = pmap->pm_active; 1736181641Skmacy } 1737181641Skmacy} 1738181641Skmacy 1739181641Skmacy#else /* SMP */ 1740181641Skmacy 1741181641Skmacy/* 1742181641Skmacy * Cleaning up on uniprocessor is easy. For various reasons, we're 1743181641Skmacy * unlikely to have to even execute this code, including the fact 1744181641Skmacy * that the cleanup is deferred until the parent does a wait(2), which 1745181641Skmacy * means that another userland process has run. 1746181641Skmacy */ 1747181641Skmacystatic void 1748181641Skmacypmap_lazyfix(pmap_t pmap) 1749181641Skmacy{ 1750181641Skmacy u_int cr3; 1751181641Skmacy 1752181641Skmacy cr3 = vtophys(pmap->pm_pdir); 1753181641Skmacy if (cr3 == rcr3()) { 1754181641Skmacy load_cr3(PCPU_GET(curpcb)->pcb_cr3); 1755222813Sattilio CPU_CLR(PCPU_GET(cpuid), &pmap->pm_active); 1756181641Skmacy } 1757181641Skmacy} 1758181641Skmacy#endif /* SMP */ 1759181641Skmacy 1760181641Skmacy/* 1761181641Skmacy * Release any resources held by the given physical map. 1762181641Skmacy * Called when a pmap initialized by pmap_pinit is being released. 1763181641Skmacy * Should only be called if the map contains no valid mappings. 1764181641Skmacy */ 1765181641Skmacyvoid 1766181641Skmacypmap_release(pmap_t pmap) 1767181641Skmacy{ 1768181641Skmacy vm_page_t m, ptdpg[2*NPGPTD+1]; 1769181641Skmacy vm_paddr_t ma; 1770181641Skmacy int i; 1771181641Skmacy#ifdef PAE 1772181641Skmacy int npgptd = NPGPTD + 1; 1773181641Skmacy#else 1774181641Skmacy int npgptd = NPGPTD; 1775181641Skmacy#endif 1776230435Salc 1777181641Skmacy KASSERT(pmap->pm_stats.resident_count == 0, 1778181641Skmacy ("pmap_release: pmap resident count %ld != 0", 1779181641Skmacy pmap->pm_stats.resident_count)); 1780181641Skmacy PT_UPDATES_FLUSH(); 1781181641Skmacy 1782216960Scperciva#ifdef HAMFISTED_LOCKING 1783216960Scperciva mtx_lock(&createdelete_lock); 1784216960Scperciva#endif 1785216960Scperciva 1786181641Skmacy pmap_lazyfix(pmap); 1787181641Skmacy mtx_lock_spin(&allpmaps_lock); 1788181641Skmacy LIST_REMOVE(pmap, pm_list); 1789181641Skmacy mtx_unlock_spin(&allpmaps_lock); 1790181641Skmacy 1791181641Skmacy for (i = 0; i < NPGPTD; i++) 1792181641Skmacy ptdpg[i] = PHYS_TO_VM_PAGE(vtophys(pmap->pm_pdir + (i*NPDEPG)) & PG_FRAME); 1793181641Skmacy pmap_qremove((vm_offset_t)pmap->pm_pdir, NPGPTD); 1794215593Scperciva#ifdef PAE 1795181641Skmacy ptdpg[NPGPTD] = PHYS_TO_VM_PAGE(vtophys(pmap->pm_pdpt)); 1796181641Skmacy#endif 1797181641Skmacy 1798181641Skmacy for (i = 0; i < npgptd; i++) { 1799181641Skmacy m = ptdpg[i]; 1800215587Scperciva ma = VM_PAGE_TO_MACH(m); 1801181641Skmacy /* unpinning L1 and L2 treated the same */ 1802215525Scperciva#if 0 1803181641Skmacy xen_pgd_unpin(ma); 1804215525Scperciva#else 1805215525Scperciva if (i == NPGPTD) 1806215525Scperciva xen_pgd_unpin(ma); 1807215525Scperciva#endif 1808181641Skmacy#ifdef PAE 1809215470Scperciva if (i < NPGPTD) 1810215587Scperciva KASSERT(VM_PAGE_TO_MACH(m) == (pmap->pm_pdpt[i] & PG_FRAME), 1811215470Scperciva ("pmap_release: got wrong ptd page")); 1812181641Skmacy#endif 1813181641Skmacy m->wire_count--; 1814181641Skmacy atomic_subtract_int(&cnt.v_wire_count, 1); 1815181641Skmacy vm_page_free(m); 1816181641Skmacy } 1817215472Scperciva#ifdef PAE 1818215472Scperciva pmap_qremove((vm_offset_t)pmap->pm_pdpt, 1); 1819215472Scperciva#endif 1820181641Skmacy PMAP_LOCK_DESTROY(pmap); 1821216960Scperciva 1822216960Scperciva#ifdef HAMFISTED_LOCKING 1823216960Scperciva mtx_unlock(&createdelete_lock); 1824216960Scperciva#endif 1825181641Skmacy} 1826181641Skmacy 1827181641Skmacystatic int 1828181641Skmacykvm_size(SYSCTL_HANDLER_ARGS) 1829181641Skmacy{ 1830181641Skmacy unsigned long ksize = VM_MAX_KERNEL_ADDRESS - KERNBASE; 1831181641Skmacy 1832230435Salc return (sysctl_handle_long(oidp, &ksize, 0, req)); 1833181641Skmacy} 1834181641SkmacySYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG|CTLFLAG_RD, 1835181641Skmacy 0, 0, kvm_size, "IU", "Size of KVM"); 1836181641Skmacy 1837181641Skmacystatic int 1838181641Skmacykvm_free(SYSCTL_HANDLER_ARGS) 1839181641Skmacy{ 1840181641Skmacy unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end; 1841181641Skmacy 1842230435Salc return (sysctl_handle_long(oidp, &kfree, 0, req)); 1843181641Skmacy} 1844181641SkmacySYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG|CTLFLAG_RD, 1845181641Skmacy 0, 0, kvm_free, "IU", "Amount of KVM free"); 1846181641Skmacy 1847181641Skmacy/* 1848181641Skmacy * grow the number of kernel page table entries, if needed 1849181641Skmacy */ 1850181641Skmacyvoid 1851181641Skmacypmap_growkernel(vm_offset_t addr) 1852181641Skmacy{ 1853181641Skmacy struct pmap *pmap; 1854181641Skmacy vm_paddr_t ptppaddr; 1855181641Skmacy vm_page_t nkpg; 1856181641Skmacy pd_entry_t newpdir; 1857181641Skmacy 1858181641Skmacy mtx_assert(&kernel_map->system_mtx, MA_OWNED); 1859181641Skmacy if (kernel_vm_end == 0) { 1860181641Skmacy kernel_vm_end = KERNBASE; 1861181641Skmacy nkpt = 0; 1862181641Skmacy while (pdir_pde(PTD, kernel_vm_end)) { 1863181641Skmacy kernel_vm_end = (kernel_vm_end + PAGE_SIZE * NPTEPG) & ~(PAGE_SIZE * NPTEPG - 1); 1864181641Skmacy nkpt++; 1865181641Skmacy if (kernel_vm_end - 1 >= kernel_map->max_offset) { 1866181641Skmacy kernel_vm_end = kernel_map->max_offset; 1867181641Skmacy break; 1868181641Skmacy } 1869181641Skmacy } 1870181641Skmacy } 1871230435Salc addr = roundup2(addr, NBPDR); 1872181641Skmacy if (addr - 1 >= kernel_map->max_offset) 1873181641Skmacy addr = kernel_map->max_offset; 1874181641Skmacy while (kernel_vm_end < addr) { 1875181641Skmacy if (pdir_pde(PTD, kernel_vm_end)) { 1876230435Salc kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK; 1877181641Skmacy if (kernel_vm_end - 1 >= kernel_map->max_offset) { 1878181641Skmacy kernel_vm_end = kernel_map->max_offset; 1879181641Skmacy break; 1880181641Skmacy } 1881181641Skmacy continue; 1882181641Skmacy } 1883181641Skmacy 1884230435Salc nkpg = vm_page_alloc(NULL, kernel_vm_end >> PDRSHIFT, 1885230435Salc VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | 1886230435Salc VM_ALLOC_ZERO); 1887230435Salc if (nkpg == NULL) 1888181641Skmacy panic("pmap_growkernel: no memory to grow kernel"); 1889181641Skmacy 1890181641Skmacy nkpt++; 1891181641Skmacy 1892230435Salc if ((nkpg->flags & PG_ZERO) == 0) 1893230435Salc pmap_zero_page(nkpg); 1894181641Skmacy ptppaddr = VM_PAGE_TO_PHYS(nkpg); 1895181641Skmacy newpdir = (pd_entry_t) (ptppaddr | PG_V | PG_RW | PG_A | PG_M); 1896181946Skmacy vm_page_lock_queues(); 1897181641Skmacy PD_SET_VA(kernel_pmap, (kernel_vm_end >> PDRSHIFT), newpdir, TRUE); 1898181641Skmacy mtx_lock_spin(&allpmaps_lock); 1899181641Skmacy LIST_FOREACH(pmap, &allpmaps, pm_list) 1900181641Skmacy PD_SET_VA(pmap, (kernel_vm_end >> PDRSHIFT), newpdir, TRUE); 1901181641Skmacy 1902181641Skmacy mtx_unlock_spin(&allpmaps_lock); 1903181946Skmacy vm_page_unlock_queues(); 1904181946Skmacy 1905230435Salc kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK; 1906181641Skmacy if (kernel_vm_end - 1 >= kernel_map->max_offset) { 1907181641Skmacy kernel_vm_end = kernel_map->max_offset; 1908181641Skmacy break; 1909181641Skmacy } 1910181641Skmacy } 1911181641Skmacy} 1912181641Skmacy 1913181641Skmacy 1914181641Skmacy/*************************************************** 1915181641Skmacy * page management routines. 1916181641Skmacy ***************************************************/ 1917181641Skmacy 1918181641SkmacyCTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE); 1919181641SkmacyCTASSERT(_NPCM == 11); 1920237950SalcCTASSERT(_NPCPV == 336); 1921181641Skmacy 1922181641Skmacystatic __inline struct pv_chunk * 1923181641Skmacypv_to_chunk(pv_entry_t pv) 1924181641Skmacy{ 1925181641Skmacy 1926230435Salc return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK)); 1927181641Skmacy} 1928181641Skmacy 1929181641Skmacy#define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap) 1930181641Skmacy 1931181641Skmacy#define PC_FREE0_9 0xfffffffful /* Free values for index 0 through 9 */ 1932181641Skmacy#define PC_FREE10 0x0000fffful /* Free values for index 10 */ 1933181641Skmacy 1934238005Salcstatic const uint32_t pc_freemask[_NPCM] = { 1935181641Skmacy PC_FREE0_9, PC_FREE0_9, PC_FREE0_9, 1936181641Skmacy PC_FREE0_9, PC_FREE0_9, PC_FREE0_9, 1937181641Skmacy PC_FREE0_9, PC_FREE0_9, PC_FREE0_9, 1938181641Skmacy PC_FREE0_9, PC_FREE10 1939181641Skmacy}; 1940181641Skmacy 1941181641SkmacySYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0, 1942181641Skmacy "Current number of pv entries"); 1943181641Skmacy 1944181641Skmacy#ifdef PV_STATS 1945181641Skmacystatic int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail; 1946181641Skmacy 1947181641SkmacySYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0, 1948181641Skmacy "Current number of pv entry chunks"); 1949181641SkmacySYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0, 1950181641Skmacy "Current number of pv entry chunks allocated"); 1951181641SkmacySYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0, 1952181641Skmacy "Current number of pv entry chunks frees"); 1953181641SkmacySYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0, 1954181641Skmacy "Number of times tried to get a chunk page but failed."); 1955181641Skmacy 1956181641Skmacystatic long pv_entry_frees, pv_entry_allocs; 1957181641Skmacystatic int pv_entry_spare; 1958181641Skmacy 1959181641SkmacySYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0, 1960181641Skmacy "Current number of pv entry frees"); 1961181641SkmacySYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0, 1962181641Skmacy "Current number of pv entry allocs"); 1963181641SkmacySYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0, 1964181641Skmacy "Current number of spare pv entries"); 1965181641Skmacy#endif 1966181641Skmacy 1967181641Skmacy/* 1968181641Skmacy * We are in a serious low memory condition. Resort to 1969181641Skmacy * drastic measures to free some pages so we can allocate 1970237950Salc * another pv entry chunk. 1971181641Skmacy */ 1972237950Salcstatic vm_page_t 1973237950Salcpmap_pv_reclaim(pmap_t locked_pmap) 1974181641Skmacy{ 1975237950Salc struct pch newtail; 1976237950Salc struct pv_chunk *pc; 1977181641Skmacy pmap_t pmap; 1978181641Skmacy pt_entry_t *pte, tpte; 1979237950Salc pv_entry_t pv; 1980181641Skmacy vm_offset_t va; 1981237950Salc vm_page_t free, m, m_pc; 1982238005Salc uint32_t inuse; 1983237950Salc int bit, field, freed; 1984181641Skmacy 1985237950Salc PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED); 1986237950Salc pmap = NULL; 1987237950Salc free = m_pc = NULL; 1988237950Salc TAILQ_INIT(&newtail); 1989181641Skmacy sched_pin(); 1990237950Salc while ((pc = TAILQ_FIRST(&pv_chunks)) != NULL && (pv_vafree == 0 || 1991237950Salc free == NULL)) { 1992237950Salc TAILQ_REMOVE(&pv_chunks, pc, pc_lru); 1993237950Salc if (pmap != pc->pc_pmap) { 1994237950Salc if (pmap != NULL) { 1995237950Salc pmap_invalidate_all(pmap); 1996237950Salc if (pmap != locked_pmap) 1997237950Salc PMAP_UNLOCK(pmap); 1998237950Salc } 1999237950Salc pmap = pc->pc_pmap; 2000181641Skmacy /* Avoid deadlock and lock recursion. */ 2001181641Skmacy if (pmap > locked_pmap) 2002181641Skmacy PMAP_LOCK(pmap); 2003237950Salc else if (pmap != locked_pmap && !PMAP_TRYLOCK(pmap)) { 2004237950Salc pmap = NULL; 2005237950Salc TAILQ_INSERT_TAIL(&newtail, pc, pc_lru); 2006181641Skmacy continue; 2007237950Salc } 2008181641Skmacy } 2009237950Salc 2010237950Salc /* 2011237950Salc * Destroy every non-wired, 4 KB page mapping in the chunk. 2012237950Salc */ 2013237950Salc freed = 0; 2014237950Salc for (field = 0; field < _NPCM; field++) { 2015237950Salc for (inuse = ~pc->pc_map[field] & pc_freemask[field]; 2016237950Salc inuse != 0; inuse &= ~(1UL << bit)) { 2017237950Salc bit = bsfl(inuse); 2018237950Salc pv = &pc->pc_pventry[field * 32 + bit]; 2019237950Salc va = pv->pv_va; 2020237950Salc pte = pmap_pte_quick(pmap, va); 2021237950Salc if ((*pte & PG_W) != 0) 2022237950Salc continue; 2023237950Salc tpte = pte_load_clear(pte); 2024237950Salc if ((tpte & PG_G) != 0) 2025237950Salc pmap_invalidate_page(pmap, va); 2026237950Salc m = PHYS_TO_VM_PAGE(tpte & PG_FRAME); 2027237950Salc if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) 2028237950Salc vm_page_dirty(m); 2029237950Salc if ((tpte & PG_A) != 0) 2030237950Salc vm_page_aflag_set(m, PGA_REFERENCED); 2031237950Salc TAILQ_REMOVE(&m->md.pv_list, pv, pv_list); 2032237950Salc if (TAILQ_EMPTY(&m->md.pv_list)) 2033237950Salc vm_page_aflag_clear(m, PGA_WRITEABLE); 2034238005Salc pc->pc_map[field] |= 1UL << bit; 2035237950Salc pmap_unuse_pt(pmap, va, &free); 2036237950Salc freed++; 2037237950Salc } 2038237950Salc } 2039237950Salc if (freed == 0) { 2040237950Salc TAILQ_INSERT_TAIL(&newtail, pc, pc_lru); 2041237950Salc continue; 2042237950Salc } 2043238005Salc /* Every freed mapping is for a 4 KB page. */ 2044237950Salc pmap->pm_stats.resident_count -= freed; 2045237950Salc PV_STAT(pv_entry_frees += freed); 2046237950Salc PV_STAT(pv_entry_spare += freed); 2047237950Salc pv_entry_count -= freed; 2048237950Salc TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 2049237950Salc for (field = 0; field < _NPCM; field++) 2050237950Salc if (pc->pc_map[field] != pc_freemask[field]) { 2051237950Salc TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, 2052237950Salc pc_list); 2053237950Salc TAILQ_INSERT_TAIL(&newtail, pc, pc_lru); 2054237950Salc 2055237950Salc /* 2056237950Salc * One freed pv entry in locked_pmap is 2057237950Salc * sufficient. 2058237950Salc */ 2059237950Salc if (pmap == locked_pmap) 2060237950Salc goto out; 2061237950Salc break; 2062237950Salc } 2063237950Salc if (field == _NPCM) { 2064237950Salc PV_STAT(pv_entry_spare -= _NPCPV); 2065237950Salc PV_STAT(pc_chunk_count--); 2066237950Salc PV_STAT(pc_chunk_frees++); 2067237950Salc /* Entire chunk is free; return it. */ 2068237950Salc m_pc = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc)); 2069237950Salc pmap_qremove((vm_offset_t)pc, 1); 2070237950Salc pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc); 2071237950Salc break; 2072237950Salc } 2073181641Skmacy } 2074237950Salcout: 2075181641Skmacy sched_unpin(); 2076237950Salc TAILQ_CONCAT(&pv_chunks, &newtail, pc_lru); 2077237950Salc if (pmap != NULL) { 2078237950Salc pmap_invalidate_all(pmap); 2079237950Salc if (pmap != locked_pmap) 2080237950Salc PMAP_UNLOCK(pmap); 2081237950Salc } 2082237950Salc if (m_pc == NULL && pv_vafree != 0 && free != NULL) { 2083237950Salc m_pc = free; 2084237950Salc free = m_pc->right; 2085237950Salc /* Recycle a freed page table page. */ 2086237950Salc m_pc->wire_count = 1; 2087237950Salc atomic_add_int(&cnt.v_wire_count, 1); 2088237950Salc } 2089237950Salc pmap_free_zero_pages(free); 2090237950Salc return (m_pc); 2091181641Skmacy} 2092181641Skmacy 2093181641Skmacy/* 2094181641Skmacy * free the pv_entry back to the free list 2095181641Skmacy */ 2096181641Skmacystatic void 2097181641Skmacyfree_pv_entry(pmap_t pmap, pv_entry_t pv) 2098181641Skmacy{ 2099181641Skmacy struct pv_chunk *pc; 2100181641Skmacy int idx, field, bit; 2101181641Skmacy 2102181641Skmacy mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2103181641Skmacy PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2104181641Skmacy PV_STAT(pv_entry_frees++); 2105181641Skmacy PV_STAT(pv_entry_spare++); 2106181641Skmacy pv_entry_count--; 2107181641Skmacy pc = pv_to_chunk(pv); 2108181641Skmacy idx = pv - &pc->pc_pventry[0]; 2109181641Skmacy field = idx / 32; 2110181641Skmacy bit = idx % 32; 2111181641Skmacy pc->pc_map[field] |= 1ul << bit; 2112181641Skmacy for (idx = 0; idx < _NPCM; idx++) 2113230435Salc if (pc->pc_map[idx] != pc_freemask[idx]) { 2114238005Salc /* 2115238005Salc * 98% of the time, pc is already at the head of the 2116238005Salc * list. If it isn't already, move it to the head. 2117238005Salc */ 2118238005Salc if (__predict_false(TAILQ_FIRST(&pmap->pm_pvchunk) != 2119238005Salc pc)) { 2120238005Salc TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 2121238005Salc TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, 2122238005Salc pc_list); 2123238005Salc } 2124181641Skmacy return; 2125230435Salc } 2126238005Salc TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 2127237950Salc free_pv_chunk(pc); 2128237950Salc} 2129237950Salc 2130237950Salcstatic void 2131237950Salcfree_pv_chunk(struct pv_chunk *pc) 2132237950Salc{ 2133237950Salc vm_page_t m; 2134237950Salc 2135237950Salc TAILQ_REMOVE(&pv_chunks, pc, pc_lru); 2136181641Skmacy PV_STAT(pv_entry_spare -= _NPCPV); 2137181641Skmacy PV_STAT(pc_chunk_count--); 2138181641Skmacy PV_STAT(pc_chunk_frees++); 2139181641Skmacy /* entire chunk is free, return it */ 2140181641Skmacy m = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc)); 2141181641Skmacy pmap_qremove((vm_offset_t)pc, 1); 2142181641Skmacy vm_page_unwire(m, 0); 2143181641Skmacy vm_page_free(m); 2144181641Skmacy pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc); 2145181641Skmacy} 2146181641Skmacy 2147181641Skmacy/* 2148181641Skmacy * get a new pv_entry, allocating a block from the system 2149181641Skmacy * when needed. 2150181641Skmacy */ 2151181641Skmacystatic pv_entry_t 2152237950Salcget_pv_entry(pmap_t pmap, boolean_t try) 2153181641Skmacy{ 2154181641Skmacy static const struct timeval printinterval = { 60, 0 }; 2155181641Skmacy static struct timeval lastprint; 2156181641Skmacy int bit, field; 2157181641Skmacy pv_entry_t pv; 2158181641Skmacy struct pv_chunk *pc; 2159181641Skmacy vm_page_t m; 2160181641Skmacy 2161181641Skmacy PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2162181641Skmacy mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2163181641Skmacy PV_STAT(pv_entry_allocs++); 2164181641Skmacy pv_entry_count++; 2165181641Skmacy if (pv_entry_count > pv_entry_high_water) 2166181641Skmacy if (ratecheck(&lastprint, &printinterval)) 2167181641Skmacy printf("Approaching the limit on PV entries, consider " 2168181641Skmacy "increasing either the vm.pmap.shpgperproc or the " 2169181641Skmacy "vm.pmap.pv_entry_max tunable.\n"); 2170181641Skmacyretry: 2171181641Skmacy pc = TAILQ_FIRST(&pmap->pm_pvchunk); 2172181641Skmacy if (pc != NULL) { 2173181641Skmacy for (field = 0; field < _NPCM; field++) { 2174181641Skmacy if (pc->pc_map[field]) { 2175181641Skmacy bit = bsfl(pc->pc_map[field]); 2176181641Skmacy break; 2177181641Skmacy } 2178181641Skmacy } 2179181641Skmacy if (field < _NPCM) { 2180181641Skmacy pv = &pc->pc_pventry[field * 32 + bit]; 2181181641Skmacy pc->pc_map[field] &= ~(1ul << bit); 2182181641Skmacy /* If this was the last item, move it to tail */ 2183181641Skmacy for (field = 0; field < _NPCM; field++) 2184181641Skmacy if (pc->pc_map[field] != 0) { 2185181641Skmacy PV_STAT(pv_entry_spare--); 2186181641Skmacy return (pv); /* not full, return */ 2187181641Skmacy } 2188181641Skmacy TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 2189181641Skmacy TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list); 2190181641Skmacy PV_STAT(pv_entry_spare--); 2191181641Skmacy return (pv); 2192181641Skmacy } 2193181641Skmacy } 2194181641Skmacy /* 2195181641Skmacy * Access to the ptelist "pv_vafree" is synchronized by the page 2196181641Skmacy * queues lock. If "pv_vafree" is currently non-empty, it will 2197181641Skmacy * remain non-empty until pmap_ptelist_alloc() completes. 2198181641Skmacy */ 2199237950Salc if (pv_vafree == 0 || (m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | 2200181641Skmacy VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) { 2201181641Skmacy if (try) { 2202181641Skmacy pv_entry_count--; 2203181641Skmacy PV_STAT(pc_chunk_tryfail++); 2204181641Skmacy return (NULL); 2205181641Skmacy } 2206237950Salc m = pmap_pv_reclaim(pmap); 2207237950Salc if (m == NULL) 2208237950Salc goto retry; 2209181641Skmacy } 2210181641Skmacy PV_STAT(pc_chunk_count++); 2211181641Skmacy PV_STAT(pc_chunk_allocs++); 2212181641Skmacy pc = (struct pv_chunk *)pmap_ptelist_alloc(&pv_vafree); 2213181641Skmacy pmap_qenter((vm_offset_t)pc, &m, 1); 2214181641Skmacy if ((m->flags & PG_ZERO) == 0) 2215181641Skmacy pagezero(pc); 2216181641Skmacy pc->pc_pmap = pmap; 2217181641Skmacy pc->pc_map[0] = pc_freemask[0] & ~1ul; /* preallocated bit 0 */ 2218181641Skmacy for (field = 1; field < _NPCM; field++) 2219181641Skmacy pc->pc_map[field] = pc_freemask[field]; 2220237950Salc TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru); 2221181641Skmacy pv = &pc->pc_pventry[0]; 2222181641Skmacy TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list); 2223181641Skmacy PV_STAT(pv_entry_spare += _NPCPV - 1); 2224181641Skmacy return (pv); 2225181641Skmacy} 2226181641Skmacy 2227208651Salcstatic __inline pv_entry_t 2228208651Salcpmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va) 2229181641Skmacy{ 2230181641Skmacy pv_entry_t pv; 2231181641Skmacy 2232181641Skmacy mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2233208651Salc TAILQ_FOREACH(pv, &pvh->pv_list, pv_list) { 2234208651Salc if (pmap == PV_PMAP(pv) && va == pv->pv_va) { 2235208651Salc TAILQ_REMOVE(&pvh->pv_list, pv, pv_list); 2236181641Skmacy break; 2237208651Salc } 2238181641Skmacy } 2239208651Salc return (pv); 2240181641Skmacy} 2241181641Skmacy 2242181641Skmacystatic void 2243208651Salcpmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va) 2244181641Skmacy{ 2245181641Skmacy pv_entry_t pv; 2246181641Skmacy 2247208651Salc pv = pmap_pvh_remove(pvh, pmap, va); 2248208651Salc KASSERT(pv != NULL, ("pmap_pvh_free: pv not found")); 2249208651Salc free_pv_entry(pmap, pv); 2250208651Salc} 2251208651Salc 2252208651Salcstatic void 2253208651Salcpmap_remove_entry(pmap_t pmap, vm_page_t m, vm_offset_t va) 2254208651Salc{ 2255208651Salc 2256181641Skmacy mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2257208651Salc pmap_pvh_free(&m->md, pmap, va); 2258208651Salc if (TAILQ_EMPTY(&m->md.pv_list)) 2259225418Skib vm_page_aflag_clear(m, PGA_WRITEABLE); 2260181641Skmacy} 2261181641Skmacy 2262181641Skmacy/* 2263181641Skmacy * Conditionally create a pv entry. 2264181641Skmacy */ 2265181641Skmacystatic boolean_t 2266181641Skmacypmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m) 2267181641Skmacy{ 2268181641Skmacy pv_entry_t pv; 2269181641Skmacy 2270181641Skmacy PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2271181641Skmacy mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2272181641Skmacy if (pv_entry_count < pv_entry_high_water && 2273181641Skmacy (pv = get_pv_entry(pmap, TRUE)) != NULL) { 2274181641Skmacy pv->pv_va = va; 2275181641Skmacy TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list); 2276181641Skmacy return (TRUE); 2277181641Skmacy } else 2278181641Skmacy return (FALSE); 2279181641Skmacy} 2280181641Skmacy 2281181641Skmacy/* 2282181641Skmacy * pmap_remove_pte: do the things to unmap a page in a process 2283181641Skmacy */ 2284181641Skmacystatic int 2285181641Skmacypmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t va, vm_page_t *free) 2286181641Skmacy{ 2287181641Skmacy pt_entry_t oldpte; 2288181641Skmacy vm_page_t m; 2289181641Skmacy 2290181641Skmacy CTR3(KTR_PMAP, "pmap_remove_pte: pmap=%p *ptq=0x%x va=0x%x", 2291181641Skmacy pmap, (u_long)*ptq, va); 2292181641Skmacy 2293181641Skmacy mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2294181641Skmacy PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2295181641Skmacy oldpte = *ptq; 2296181641Skmacy PT_SET_VA_MA(ptq, 0, TRUE); 2297181641Skmacy if (oldpte & PG_W) 2298181641Skmacy pmap->pm_stats.wired_count -= 1; 2299181641Skmacy /* 2300181641Skmacy * Machines that don't support invlpg, also don't support 2301181641Skmacy * PG_G. 2302181641Skmacy */ 2303181641Skmacy if (oldpte & PG_G) 2304181641Skmacy pmap_invalidate_page(kernel_pmap, va); 2305181641Skmacy pmap->pm_stats.resident_count -= 1; 2306216762Scperciva if (oldpte & PG_MANAGED) { 2307181641Skmacy m = PHYS_TO_VM_PAGE(xpmap_mtop(oldpte) & PG_FRAME); 2308208651Salc if ((oldpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) 2309181641Skmacy vm_page_dirty(m); 2310181641Skmacy if (oldpte & PG_A) 2311225418Skib vm_page_aflag_set(m, PGA_REFERENCED); 2312181641Skmacy pmap_remove_entry(pmap, m, va); 2313216762Scperciva } 2314181641Skmacy return (pmap_unuse_pt(pmap, va, free)); 2315181641Skmacy} 2316181641Skmacy 2317181641Skmacy/* 2318181641Skmacy * Remove a single page from a process address space 2319181641Skmacy */ 2320181641Skmacystatic void 2321181641Skmacypmap_remove_page(pmap_t pmap, vm_offset_t va, vm_page_t *free) 2322181641Skmacy{ 2323181641Skmacy pt_entry_t *pte; 2324181641Skmacy 2325181641Skmacy CTR2(KTR_PMAP, "pmap_remove_page: pmap=%p va=0x%x", 2326181641Skmacy pmap, va); 2327181641Skmacy 2328181641Skmacy mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2329181641Skmacy KASSERT(curthread->td_pinned > 0, ("curthread not pinned")); 2330181641Skmacy PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2331181641Skmacy if ((pte = pmap_pte_quick(pmap, va)) == NULL || (*pte & PG_V) == 0) 2332181641Skmacy return; 2333181641Skmacy pmap_remove_pte(pmap, pte, va, free); 2334181641Skmacy pmap_invalidate_page(pmap, va); 2335181641Skmacy if (*PMAP1) 2336181641Skmacy PT_SET_MA(PADDR1, 0); 2337181641Skmacy 2338181641Skmacy} 2339181641Skmacy 2340181641Skmacy/* 2341181641Skmacy * Remove the given range of addresses from the specified map. 2342181641Skmacy * 2343181641Skmacy * It is assumed that the start and end are properly 2344181641Skmacy * rounded to the page size. 2345181641Skmacy */ 2346181641Skmacyvoid 2347181641Skmacypmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 2348181641Skmacy{ 2349181641Skmacy vm_offset_t pdnxt; 2350181641Skmacy pd_entry_t ptpaddr; 2351181641Skmacy pt_entry_t *pte; 2352181641Skmacy vm_page_t free = NULL; 2353181641Skmacy int anyvalid; 2354230435Salc 2355181641Skmacy CTR3(KTR_PMAP, "pmap_remove: pmap=%p sva=0x%x eva=0x%x", 2356181641Skmacy pmap, sva, eva); 2357230435Salc 2358181641Skmacy /* 2359181641Skmacy * Perform an unsynchronized read. This is, however, safe. 2360181641Skmacy */ 2361181641Skmacy if (pmap->pm_stats.resident_count == 0) 2362181641Skmacy return; 2363181641Skmacy 2364181641Skmacy anyvalid = 0; 2365181641Skmacy 2366181641Skmacy vm_page_lock_queues(); 2367181641Skmacy sched_pin(); 2368181641Skmacy PMAP_LOCK(pmap); 2369181641Skmacy 2370181641Skmacy /* 2371181641Skmacy * special handling of removing one page. a very 2372181641Skmacy * common operation and easy to short circuit some 2373181641Skmacy * code. 2374181641Skmacy */ 2375181641Skmacy if ((sva + PAGE_SIZE == eva) && 2376181641Skmacy ((pmap->pm_pdir[(sva >> PDRSHIFT)] & PG_PS) == 0)) { 2377181641Skmacy pmap_remove_page(pmap, sva, &free); 2378181641Skmacy goto out; 2379181641Skmacy } 2380181641Skmacy 2381181641Skmacy for (; sva < eva; sva = pdnxt) { 2382230435Salc u_int pdirindex; 2383181641Skmacy 2384181641Skmacy /* 2385181641Skmacy * Calculate index for next page table. 2386181641Skmacy */ 2387181641Skmacy pdnxt = (sva + NBPDR) & ~PDRMASK; 2388230435Salc if (pdnxt < sva) 2389230435Salc pdnxt = eva; 2390181641Skmacy if (pmap->pm_stats.resident_count == 0) 2391181641Skmacy break; 2392181641Skmacy 2393181641Skmacy pdirindex = sva >> PDRSHIFT; 2394181641Skmacy ptpaddr = pmap->pm_pdir[pdirindex]; 2395181641Skmacy 2396181641Skmacy /* 2397181641Skmacy * Weed out invalid mappings. Note: we assume that the page 2398181641Skmacy * directory table is always allocated, and in kernel virtual. 2399181641Skmacy */ 2400181641Skmacy if (ptpaddr == 0) 2401181641Skmacy continue; 2402181641Skmacy 2403181641Skmacy /* 2404181641Skmacy * Check for large page. 2405181641Skmacy */ 2406181641Skmacy if ((ptpaddr & PG_PS) != 0) { 2407181641Skmacy PD_CLEAR_VA(pmap, pdirindex, TRUE); 2408181641Skmacy pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE; 2409181641Skmacy anyvalid = 1; 2410181641Skmacy continue; 2411181641Skmacy } 2412181641Skmacy 2413181641Skmacy /* 2414181641Skmacy * Limit our scan to either the end of the va represented 2415181641Skmacy * by the current page table page, or to the end of the 2416181641Skmacy * range being removed. 2417181641Skmacy */ 2418181641Skmacy if (pdnxt > eva) 2419181641Skmacy pdnxt = eva; 2420181641Skmacy 2421181641Skmacy for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++, 2422181641Skmacy sva += PAGE_SIZE) { 2423181641Skmacy if ((*pte & PG_V) == 0) 2424181641Skmacy continue; 2425181641Skmacy 2426181641Skmacy /* 2427181641Skmacy * The TLB entry for a PG_G mapping is invalidated 2428181641Skmacy * by pmap_remove_pte(). 2429181641Skmacy */ 2430181641Skmacy if ((*pte & PG_G) == 0) 2431181641Skmacy anyvalid = 1; 2432181641Skmacy if (pmap_remove_pte(pmap, pte, sva, &free)) 2433181641Skmacy break; 2434181641Skmacy } 2435181641Skmacy } 2436181641Skmacy PT_UPDATES_FLUSH(); 2437181641Skmacy if (*PMAP1) 2438181641Skmacy PT_SET_VA_MA(PMAP1, 0, TRUE); 2439181641Skmacyout: 2440181641Skmacy if (anyvalid) 2441181641Skmacy pmap_invalidate_all(pmap); 2442181641Skmacy sched_unpin(); 2443181641Skmacy vm_page_unlock_queues(); 2444181641Skmacy PMAP_UNLOCK(pmap); 2445181641Skmacy pmap_free_zero_pages(free); 2446181641Skmacy} 2447181641Skmacy 2448181641Skmacy/* 2449181641Skmacy * Routine: pmap_remove_all 2450181641Skmacy * Function: 2451181641Skmacy * Removes this physical page from 2452181641Skmacy * all physical maps in which it resides. 2453181641Skmacy * Reflects back modify bits to the pager. 2454181641Skmacy * 2455181641Skmacy * Notes: 2456181641Skmacy * Original versions of this routine were very 2457181641Skmacy * inefficient because they iteratively called 2458181641Skmacy * pmap_remove (slow...) 2459181641Skmacy */ 2460181641Skmacy 2461181641Skmacyvoid 2462181641Skmacypmap_remove_all(vm_page_t m) 2463181641Skmacy{ 2464181641Skmacy pv_entry_t pv; 2465181641Skmacy pmap_t pmap; 2466181641Skmacy pt_entry_t *pte, tpte; 2467181641Skmacy vm_page_t free; 2468181641Skmacy 2469224746Skib KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2470223677Salc ("pmap_remove_all: page %p is not managed", m)); 2471208651Salc free = NULL; 2472207796Salc vm_page_lock_queues(); 2473181641Skmacy sched_pin(); 2474181641Skmacy while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) { 2475181641Skmacy pmap = PV_PMAP(pv); 2476181641Skmacy PMAP_LOCK(pmap); 2477181641Skmacy pmap->pm_stats.resident_count--; 2478181641Skmacy pte = pmap_pte_quick(pmap, pv->pv_va); 2479181641Skmacy tpte = *pte; 2480181641Skmacy PT_SET_VA_MA(pte, 0, TRUE); 2481181641Skmacy if (tpte & PG_W) 2482181641Skmacy pmap->pm_stats.wired_count--; 2483181641Skmacy if (tpte & PG_A) 2484225418Skib vm_page_aflag_set(m, PGA_REFERENCED); 2485181641Skmacy 2486181641Skmacy /* 2487181641Skmacy * Update the vm_page_t clean and reference bits. 2488181641Skmacy */ 2489208651Salc if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) 2490181641Skmacy vm_page_dirty(m); 2491181641Skmacy pmap_unuse_pt(pmap, pv->pv_va, &free); 2492181641Skmacy pmap_invalidate_page(pmap, pv->pv_va); 2493181641Skmacy TAILQ_REMOVE(&m->md.pv_list, pv, pv_list); 2494181641Skmacy free_pv_entry(pmap, pv); 2495181641Skmacy PMAP_UNLOCK(pmap); 2496181641Skmacy } 2497225418Skib vm_page_aflag_clear(m, PGA_WRITEABLE); 2498181641Skmacy PT_UPDATES_FLUSH(); 2499181641Skmacy if (*PMAP1) 2500181641Skmacy PT_SET_MA(PADDR1, 0); 2501181641Skmacy sched_unpin(); 2502207796Salc vm_page_unlock_queues(); 2503208651Salc pmap_free_zero_pages(free); 2504181641Skmacy} 2505181641Skmacy 2506181641Skmacy/* 2507181641Skmacy * Set the physical protection on the 2508181641Skmacy * specified range of this map as requested. 2509181641Skmacy */ 2510181641Skmacyvoid 2511181641Skmacypmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot) 2512181641Skmacy{ 2513181641Skmacy vm_offset_t pdnxt; 2514181641Skmacy pd_entry_t ptpaddr; 2515181641Skmacy pt_entry_t *pte; 2516181641Skmacy int anychanged; 2517181641Skmacy 2518181641Skmacy CTR4(KTR_PMAP, "pmap_protect: pmap=%p sva=0x%x eva=0x%x prot=0x%x", 2519181641Skmacy pmap, sva, eva, prot); 2520181641Skmacy 2521181641Skmacy if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 2522181641Skmacy pmap_remove(pmap, sva, eva); 2523181641Skmacy return; 2524181641Skmacy } 2525181641Skmacy 2526181641Skmacy#ifdef PAE 2527181641Skmacy if ((prot & (VM_PROT_WRITE|VM_PROT_EXECUTE)) == 2528181641Skmacy (VM_PROT_WRITE|VM_PROT_EXECUTE)) 2529181641Skmacy return; 2530181641Skmacy#else 2531181641Skmacy if (prot & VM_PROT_WRITE) 2532181641Skmacy return; 2533181641Skmacy#endif 2534181641Skmacy 2535181641Skmacy anychanged = 0; 2536181641Skmacy 2537181641Skmacy vm_page_lock_queues(); 2538181641Skmacy sched_pin(); 2539181641Skmacy PMAP_LOCK(pmap); 2540181641Skmacy for (; sva < eva; sva = pdnxt) { 2541181641Skmacy pt_entry_t obits, pbits; 2542230435Salc u_int pdirindex; 2543181641Skmacy 2544181641Skmacy pdnxt = (sva + NBPDR) & ~PDRMASK; 2545230435Salc if (pdnxt < sva) 2546230435Salc pdnxt = eva; 2547181641Skmacy 2548181641Skmacy pdirindex = sva >> PDRSHIFT; 2549181641Skmacy ptpaddr = pmap->pm_pdir[pdirindex]; 2550181641Skmacy 2551181641Skmacy /* 2552181641Skmacy * Weed out invalid mappings. Note: we assume that the page 2553181641Skmacy * directory table is always allocated, and in kernel virtual. 2554181641Skmacy */ 2555181641Skmacy if (ptpaddr == 0) 2556181641Skmacy continue; 2557181641Skmacy 2558181641Skmacy /* 2559181641Skmacy * Check for large page. 2560181641Skmacy */ 2561181641Skmacy if ((ptpaddr & PG_PS) != 0) { 2562181641Skmacy if ((prot & VM_PROT_WRITE) == 0) 2563181641Skmacy pmap->pm_pdir[pdirindex] &= ~(PG_M|PG_RW); 2564181641Skmacy#ifdef PAE 2565181641Skmacy if ((prot & VM_PROT_EXECUTE) == 0) 2566181641Skmacy pmap->pm_pdir[pdirindex] |= pg_nx; 2567181641Skmacy#endif 2568181641Skmacy anychanged = 1; 2569181641Skmacy continue; 2570181641Skmacy } 2571181641Skmacy 2572181641Skmacy if (pdnxt > eva) 2573181641Skmacy pdnxt = eva; 2574181641Skmacy 2575181641Skmacy for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++, 2576181641Skmacy sva += PAGE_SIZE) { 2577181641Skmacy vm_page_t m; 2578181641Skmacy 2579181641Skmacyretry: 2580181641Skmacy /* 2581181641Skmacy * Regardless of whether a pte is 32 or 64 bits in 2582181641Skmacy * size, PG_RW, PG_A, and PG_M are among the least 2583181641Skmacy * significant 32 bits. 2584181641Skmacy */ 2585181641Skmacy obits = pbits = *pte; 2586181641Skmacy if ((pbits & PG_V) == 0) 2587181641Skmacy continue; 2588207262Salc 2589207262Salc if ((prot & VM_PROT_WRITE) == 0) { 2590207262Salc if ((pbits & (PG_MANAGED | PG_M | PG_RW)) == 2591207262Salc (PG_MANAGED | PG_M | PG_RW)) { 2592207262Salc m = PHYS_TO_VM_PAGE(xpmap_mtop(pbits) & 2593207262Salc PG_FRAME); 2594181641Skmacy vm_page_dirty(m); 2595181641Skmacy } 2596207262Salc pbits &= ~(PG_RW | PG_M); 2597181641Skmacy } 2598181641Skmacy#ifdef PAE 2599181641Skmacy if ((prot & VM_PROT_EXECUTE) == 0) 2600181641Skmacy pbits |= pg_nx; 2601181641Skmacy#endif 2602181641Skmacy 2603181641Skmacy if (pbits != obits) { 2604181641Skmacy obits = *pte; 2605181641Skmacy PT_SET_VA_MA(pte, pbits, TRUE); 2606181641Skmacy if (*pte != pbits) 2607181641Skmacy goto retry; 2608181641Skmacy if (obits & PG_G) 2609181641Skmacy pmap_invalidate_page(pmap, sva); 2610181641Skmacy else 2611181641Skmacy anychanged = 1; 2612181641Skmacy } 2613181641Skmacy } 2614181641Skmacy } 2615181641Skmacy PT_UPDATES_FLUSH(); 2616181641Skmacy if (*PMAP1) 2617181641Skmacy PT_SET_VA_MA(PMAP1, 0, TRUE); 2618181641Skmacy if (anychanged) 2619181641Skmacy pmap_invalidate_all(pmap); 2620181641Skmacy sched_unpin(); 2621181641Skmacy vm_page_unlock_queues(); 2622181641Skmacy PMAP_UNLOCK(pmap); 2623181641Skmacy} 2624181641Skmacy 2625181641Skmacy/* 2626181641Skmacy * Insert the given physical page (p) at 2627181641Skmacy * the specified virtual address (v) in the 2628181641Skmacy * target physical map with the protection requested. 2629181641Skmacy * 2630181641Skmacy * If specified, the page will be wired down, meaning 2631181641Skmacy * that the related pte can not be reclaimed. 2632181641Skmacy * 2633181641Skmacy * NB: This is the only routine which MAY NOT lazy-evaluate 2634181641Skmacy * or lose information. That is, this routine must actually 2635181641Skmacy * insert this page into the given map NOW. 2636181641Skmacy */ 2637181641Skmacyvoid 2638181641Skmacypmap_enter(pmap_t pmap, vm_offset_t va, vm_prot_t access, vm_page_t m, 2639181641Skmacy vm_prot_t prot, boolean_t wired) 2640181641Skmacy{ 2641181641Skmacy pd_entry_t *pde; 2642181641Skmacy pt_entry_t *pte; 2643208651Salc pt_entry_t newpte, origpte; 2644208651Salc pv_entry_t pv; 2645208651Salc vm_paddr_t opa, pa; 2646181641Skmacy vm_page_t mpte, om; 2647181641Skmacy boolean_t invlva; 2648181641Skmacy 2649181641Skmacy CTR6(KTR_PMAP, "pmap_enter: pmap=%08p va=0x%08x access=0x%x ma=0x%08x prot=0x%x wired=%d", 2650215587Scperciva pmap, va, access, VM_PAGE_TO_MACH(m), prot, wired); 2651181641Skmacy va = trunc_page(va); 2652208651Salc KASSERT(va <= VM_MAX_KERNEL_ADDRESS, ("pmap_enter: toobig")); 2653208651Salc KASSERT(va < UPT_MIN_ADDRESS || va >= UPT_MAX_ADDRESS, 2654208175Salc ("pmap_enter: invalid to pmap_enter page table pages (va: 0x%x)", 2655208175Salc va)); 2656230435Salc KASSERT((m->oflags & (VPO_UNMANAGED | VPO_BUSY)) != 0 || 2657230435Salc VM_OBJECT_LOCKED(m->object), 2658208175Salc ("pmap_enter: page %p is not busy", m)); 2659181641Skmacy 2660181641Skmacy mpte = NULL; 2661181641Skmacy 2662181641Skmacy vm_page_lock_queues(); 2663181641Skmacy PMAP_LOCK(pmap); 2664181641Skmacy sched_pin(); 2665181641Skmacy 2666181641Skmacy /* 2667181641Skmacy * In the case that a page table page is not 2668181641Skmacy * resident, we are creating it here. 2669181641Skmacy */ 2670181641Skmacy if (va < VM_MAXUSER_ADDRESS) { 2671181641Skmacy mpte = pmap_allocpte(pmap, va, M_WAITOK); 2672181641Skmacy } 2673181641Skmacy 2674181641Skmacy pde = pmap_pde(pmap, va); 2675181641Skmacy if ((*pde & PG_PS) != 0) 2676181641Skmacy panic("pmap_enter: attempted pmap_enter on 4MB page"); 2677181641Skmacy pte = pmap_pte_quick(pmap, va); 2678181641Skmacy 2679181641Skmacy /* 2680181641Skmacy * Page Directory table entry not valid, we need a new PT page 2681181641Skmacy */ 2682181641Skmacy if (pte == NULL) { 2683208651Salc panic("pmap_enter: invalid page directory pdir=%#jx, va=%#x", 2684181641Skmacy (uintmax_t)pmap->pm_pdir[va >> PDRSHIFT], va); 2685181641Skmacy } 2686181641Skmacy 2687181641Skmacy pa = VM_PAGE_TO_PHYS(m); 2688181641Skmacy om = NULL; 2689181641Skmacy opa = origpte = 0; 2690181641Skmacy 2691181641Skmacy#if 0 2692181641Skmacy KASSERT((*pte & PG_V) || (*pte == 0), ("address set but not valid pte=%p *pte=0x%016jx", 2693181641Skmacy pte, *pte)); 2694181641Skmacy#endif 2695181641Skmacy origpte = *pte; 2696181641Skmacy if (origpte) 2697181641Skmacy origpte = xpmap_mtop(origpte); 2698181641Skmacy opa = origpte & PG_FRAME; 2699181641Skmacy 2700181641Skmacy /* 2701181641Skmacy * Mapping has not changed, must be protection or wiring change. 2702181641Skmacy */ 2703181641Skmacy if (origpte && (opa == pa)) { 2704181641Skmacy /* 2705181641Skmacy * Wiring change, just update stats. We don't worry about 2706181641Skmacy * wiring PT pages as they remain resident as long as there 2707181641Skmacy * are valid mappings in them. Hence, if a user page is wired, 2708181641Skmacy * the PT page will be also. 2709181641Skmacy */ 2710181641Skmacy if (wired && ((origpte & PG_W) == 0)) 2711181641Skmacy pmap->pm_stats.wired_count++; 2712181641Skmacy else if (!wired && (origpte & PG_W)) 2713181641Skmacy pmap->pm_stats.wired_count--; 2714181641Skmacy 2715181641Skmacy /* 2716181641Skmacy * Remove extra pte reference 2717181641Skmacy */ 2718181641Skmacy if (mpte) 2719181641Skmacy mpte->wire_count--; 2720181641Skmacy 2721181641Skmacy if (origpte & PG_MANAGED) { 2722181641Skmacy om = m; 2723181641Skmacy pa |= PG_MANAGED; 2724181641Skmacy } 2725181641Skmacy goto validate; 2726181641Skmacy } 2727208651Salc 2728208651Salc pv = NULL; 2729208651Salc 2730181641Skmacy /* 2731181641Skmacy * Mapping has changed, invalidate old range and fall through to 2732181641Skmacy * handle validating new mapping. 2733181641Skmacy */ 2734181641Skmacy if (opa) { 2735181641Skmacy if (origpte & PG_W) 2736181641Skmacy pmap->pm_stats.wired_count--; 2737181641Skmacy if (origpte & PG_MANAGED) { 2738181641Skmacy om = PHYS_TO_VM_PAGE(opa); 2739208651Salc pv = pmap_pvh_remove(&om->md, pmap, va); 2740181641Skmacy } else if (va < VM_MAXUSER_ADDRESS) 2741181641Skmacy printf("va=0x%x is unmanaged :-( \n", va); 2742181641Skmacy 2743181641Skmacy if (mpte != NULL) { 2744181641Skmacy mpte->wire_count--; 2745181641Skmacy KASSERT(mpte->wire_count > 0, 2746181641Skmacy ("pmap_enter: missing reference to page table page," 2747181641Skmacy " va: 0x%x", va)); 2748181641Skmacy } 2749181641Skmacy } else 2750181641Skmacy pmap->pm_stats.resident_count++; 2751181641Skmacy 2752181641Skmacy /* 2753181641Skmacy * Enter on the PV list if part of our managed memory. 2754181641Skmacy */ 2755224746Skib if ((m->oflags & VPO_UNMANAGED) == 0) { 2756181641Skmacy KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva, 2757181641Skmacy ("pmap_enter: managed mapping within the clean submap")); 2758208651Salc if (pv == NULL) 2759208651Salc pv = get_pv_entry(pmap, FALSE); 2760208651Salc pv->pv_va = va; 2761208651Salc TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list); 2762181641Skmacy pa |= PG_MANAGED; 2763208651Salc } else if (pv != NULL) 2764208651Salc free_pv_entry(pmap, pv); 2765181641Skmacy 2766181641Skmacy /* 2767181641Skmacy * Increment counters 2768181641Skmacy */ 2769181641Skmacy if (wired) 2770181641Skmacy pmap->pm_stats.wired_count++; 2771181641Skmacy 2772181641Skmacyvalidate: 2773181641Skmacy /* 2774181641Skmacy * Now validate mapping with desired protection/wiring. 2775181641Skmacy */ 2776181641Skmacy newpte = (pt_entry_t)(pa | PG_V); 2777181641Skmacy if ((prot & VM_PROT_WRITE) != 0) { 2778181641Skmacy newpte |= PG_RW; 2779208651Salc if ((newpte & PG_MANAGED) != 0) 2780225418Skib vm_page_aflag_set(m, PGA_WRITEABLE); 2781181641Skmacy } 2782181641Skmacy#ifdef PAE 2783181641Skmacy if ((prot & VM_PROT_EXECUTE) == 0) 2784181641Skmacy newpte |= pg_nx; 2785181641Skmacy#endif 2786181641Skmacy if (wired) 2787181641Skmacy newpte |= PG_W; 2788181641Skmacy if (va < VM_MAXUSER_ADDRESS) 2789181641Skmacy newpte |= PG_U; 2790181641Skmacy if (pmap == kernel_pmap) 2791181641Skmacy newpte |= pgeflag; 2792181641Skmacy 2793181641Skmacy critical_enter(); 2794181641Skmacy /* 2795181641Skmacy * if the mapping or permission bits are different, we need 2796181641Skmacy * to update the pte. 2797181641Skmacy */ 2798181641Skmacy if ((origpte & ~(PG_M|PG_A)) != newpte) { 2799181641Skmacy if (origpte) { 2800181641Skmacy invlva = FALSE; 2801181641Skmacy origpte = *pte; 2802181641Skmacy PT_SET_VA(pte, newpte | PG_A, FALSE); 2803181641Skmacy if (origpte & PG_A) { 2804181641Skmacy if (origpte & PG_MANAGED) 2805225418Skib vm_page_aflag_set(om, PGA_REFERENCED); 2806181641Skmacy if (opa != VM_PAGE_TO_PHYS(m)) 2807181641Skmacy invlva = TRUE; 2808181641Skmacy#ifdef PAE 2809181641Skmacy if ((origpte & PG_NX) == 0 && 2810181641Skmacy (newpte & PG_NX) != 0) 2811181641Skmacy invlva = TRUE; 2812181641Skmacy#endif 2813181641Skmacy } 2814208651Salc if ((origpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) { 2815181641Skmacy if ((origpte & PG_MANAGED) != 0) 2816181641Skmacy vm_page_dirty(om); 2817181641Skmacy if ((prot & VM_PROT_WRITE) == 0) 2818181641Skmacy invlva = TRUE; 2819181641Skmacy } 2820208651Salc if ((origpte & PG_MANAGED) != 0 && 2821208651Salc TAILQ_EMPTY(&om->md.pv_list)) 2822225418Skib vm_page_aflag_clear(om, PGA_WRITEABLE); 2823181641Skmacy if (invlva) 2824181641Skmacy pmap_invalidate_page(pmap, va); 2825181641Skmacy } else{ 2826181641Skmacy PT_SET_VA(pte, newpte | PG_A, FALSE); 2827181641Skmacy } 2828181641Skmacy 2829181641Skmacy } 2830181641Skmacy PT_UPDATES_FLUSH(); 2831181641Skmacy critical_exit(); 2832181641Skmacy if (*PMAP1) 2833181641Skmacy PT_SET_VA_MA(PMAP1, 0, TRUE); 2834181641Skmacy sched_unpin(); 2835181641Skmacy vm_page_unlock_queues(); 2836181641Skmacy PMAP_UNLOCK(pmap); 2837181641Skmacy} 2838181641Skmacy 2839181641Skmacy/* 2840181641Skmacy * Maps a sequence of resident pages belonging to the same object. 2841181641Skmacy * The sequence begins with the given page m_start. This page is 2842181641Skmacy * mapped at the given virtual address start. Each subsequent page is 2843181641Skmacy * mapped at a virtual address that is offset from start by the same 2844181641Skmacy * amount as the page is offset from m_start within the object. The 2845181641Skmacy * last page in the sequence is the page with the largest offset from 2846181641Skmacy * m_start that can be mapped at a virtual address less than the given 2847181641Skmacy * virtual address end. Not every virtual page between start and end 2848181641Skmacy * is mapped; only those for which a resident page exists with the 2849181641Skmacy * corresponding offset from m_start are mapped. 2850181641Skmacy */ 2851181641Skmacyvoid 2852181641Skmacypmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end, 2853181641Skmacy vm_page_t m_start, vm_prot_t prot) 2854181641Skmacy{ 2855181641Skmacy vm_page_t m, mpte; 2856181641Skmacy vm_pindex_t diff, psize; 2857181641Skmacy multicall_entry_t mcl[16]; 2858181641Skmacy multicall_entry_t *mclp = mcl; 2859181641Skmacy int error, count = 0; 2860230435Salc 2861181641Skmacy VM_OBJECT_LOCK_ASSERT(m_start->object, MA_OWNED); 2862181641Skmacy psize = atop(end - start); 2863181641Skmacy mpte = NULL; 2864181641Skmacy m = m_start; 2865208574Salc vm_page_lock_queues(); 2866181641Skmacy PMAP_LOCK(pmap); 2867181641Skmacy while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 2868181641Skmacy mpte = pmap_enter_quick_locked(&mclp, &count, pmap, start + ptoa(diff), m, 2869181641Skmacy prot, mpte); 2870181641Skmacy m = TAILQ_NEXT(m, listq); 2871181641Skmacy if (count == 16) { 2872181641Skmacy error = HYPERVISOR_multicall(mcl, count); 2873181641Skmacy KASSERT(error == 0, ("bad multicall %d", error)); 2874181641Skmacy mclp = mcl; 2875181641Skmacy count = 0; 2876181641Skmacy } 2877181641Skmacy } 2878181641Skmacy if (count) { 2879181641Skmacy error = HYPERVISOR_multicall(mcl, count); 2880181641Skmacy KASSERT(error == 0, ("bad multicall %d", error)); 2881181641Skmacy } 2882208574Salc vm_page_unlock_queues(); 2883181641Skmacy PMAP_UNLOCK(pmap); 2884181641Skmacy} 2885181641Skmacy 2886181641Skmacy/* 2887181641Skmacy * this code makes some *MAJOR* assumptions: 2888181641Skmacy * 1. Current pmap & pmap exists. 2889181641Skmacy * 2. Not wired. 2890181641Skmacy * 3. Read access. 2891181641Skmacy * 4. No page table pages. 2892181641Skmacy * but is *MUCH* faster than pmap_enter... 2893181641Skmacy */ 2894181641Skmacy 2895181641Skmacyvoid 2896181641Skmacypmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot) 2897181641Skmacy{ 2898181641Skmacy multicall_entry_t mcl, *mclp; 2899181641Skmacy int count = 0; 2900181641Skmacy mclp = &mcl; 2901230435Salc 2902181641Skmacy CTR4(KTR_PMAP, "pmap_enter_quick: pmap=%p va=0x%x m=%p prot=0x%x", 2903181641Skmacy pmap, va, m, prot); 2904181641Skmacy 2905207796Salc vm_page_lock_queues(); 2906181641Skmacy PMAP_LOCK(pmap); 2907207796Salc (void)pmap_enter_quick_locked(&mclp, &count, pmap, va, m, prot, NULL); 2908181641Skmacy if (count) 2909181641Skmacy HYPERVISOR_multicall(&mcl, count); 2910207796Salc vm_page_unlock_queues(); 2911181641Skmacy PMAP_UNLOCK(pmap); 2912181641Skmacy} 2913181641Skmacy 2914181747Skmacy#ifdef notyet 2915181641Skmacyvoid 2916181641Skmacypmap_enter_quick_range(pmap_t pmap, vm_offset_t *addrs, vm_page_t *pages, vm_prot_t *prots, int count) 2917181641Skmacy{ 2918181641Skmacy int i, error, index = 0; 2919181641Skmacy multicall_entry_t mcl[16]; 2920181641Skmacy multicall_entry_t *mclp = mcl; 2921181641Skmacy 2922181641Skmacy PMAP_LOCK(pmap); 2923181641Skmacy for (i = 0; i < count; i++, addrs++, pages++, prots++) { 2924181641Skmacy if (!pmap_is_prefaultable_locked(pmap, *addrs)) 2925181641Skmacy continue; 2926181641Skmacy 2927181641Skmacy (void) pmap_enter_quick_locked(&mclp, &index, pmap, *addrs, *pages, *prots, NULL); 2928181641Skmacy if (index == 16) { 2929181641Skmacy error = HYPERVISOR_multicall(mcl, index); 2930181641Skmacy mclp = mcl; 2931181641Skmacy index = 0; 2932181641Skmacy KASSERT(error == 0, ("bad multicall %d", error)); 2933181641Skmacy } 2934181641Skmacy } 2935181641Skmacy if (index) { 2936181641Skmacy error = HYPERVISOR_multicall(mcl, index); 2937181641Skmacy KASSERT(error == 0, ("bad multicall %d", error)); 2938181641Skmacy } 2939181641Skmacy 2940181641Skmacy PMAP_UNLOCK(pmap); 2941181641Skmacy} 2942181747Skmacy#endif 2943181641Skmacy 2944181641Skmacystatic vm_page_t 2945181641Skmacypmap_enter_quick_locked(multicall_entry_t **mclpp, int *count, pmap_t pmap, vm_offset_t va, vm_page_t m, 2946181641Skmacy vm_prot_t prot, vm_page_t mpte) 2947181641Skmacy{ 2948181641Skmacy pt_entry_t *pte; 2949181641Skmacy vm_paddr_t pa; 2950181641Skmacy vm_page_t free; 2951181641Skmacy multicall_entry_t *mcl = *mclpp; 2952230435Salc 2953181641Skmacy KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva || 2954224746Skib (m->oflags & VPO_UNMANAGED) != 0, 2955181641Skmacy ("pmap_enter_quick_locked: managed mapping within the clean submap")); 2956181641Skmacy mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2957181641Skmacy PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2958181641Skmacy 2959181641Skmacy /* 2960181641Skmacy * In the case that a page table page is not 2961181641Skmacy * resident, we are creating it here. 2962181641Skmacy */ 2963181641Skmacy if (va < VM_MAXUSER_ADDRESS) { 2964230435Salc u_int ptepindex; 2965181641Skmacy pd_entry_t ptema; 2966181641Skmacy 2967181641Skmacy /* 2968181641Skmacy * Calculate pagetable page index 2969181641Skmacy */ 2970181641Skmacy ptepindex = va >> PDRSHIFT; 2971181641Skmacy if (mpte && (mpte->pindex == ptepindex)) { 2972181641Skmacy mpte->wire_count++; 2973181641Skmacy } else { 2974181641Skmacy /* 2975181641Skmacy * Get the page directory entry 2976181641Skmacy */ 2977181641Skmacy ptema = pmap->pm_pdir[ptepindex]; 2978181641Skmacy 2979181641Skmacy /* 2980181641Skmacy * If the page table page is mapped, we just increment 2981181641Skmacy * the hold count, and activate it. 2982181641Skmacy */ 2983181641Skmacy if (ptema & PG_V) { 2984181641Skmacy if (ptema & PG_PS) 2985181641Skmacy panic("pmap_enter_quick: unexpected mapping into 4MB page"); 2986181641Skmacy mpte = PHYS_TO_VM_PAGE(xpmap_mtop(ptema) & PG_FRAME); 2987181641Skmacy mpte->wire_count++; 2988181641Skmacy } else { 2989181641Skmacy mpte = _pmap_allocpte(pmap, ptepindex, 2990181641Skmacy M_NOWAIT); 2991181641Skmacy if (mpte == NULL) 2992181641Skmacy return (mpte); 2993181641Skmacy } 2994181641Skmacy } 2995181641Skmacy } else { 2996181641Skmacy mpte = NULL; 2997181641Skmacy } 2998181641Skmacy 2999181641Skmacy /* 3000181641Skmacy * This call to vtopte makes the assumption that we are 3001181641Skmacy * entering the page into the current pmap. In order to support 3002181641Skmacy * quick entry into any pmap, one would likely use pmap_pte_quick. 3003181641Skmacy * But that isn't as quick as vtopte. 3004181641Skmacy */ 3005181641Skmacy KASSERT(pmap_is_current(pmap), ("entering pages in non-current pmap")); 3006181641Skmacy pte = vtopte(va); 3007181641Skmacy if (*pte & PG_V) { 3008181641Skmacy if (mpte != NULL) { 3009181641Skmacy mpte->wire_count--; 3010181641Skmacy mpte = NULL; 3011181641Skmacy } 3012181641Skmacy return (mpte); 3013181641Skmacy } 3014181641Skmacy 3015181641Skmacy /* 3016181641Skmacy * Enter on the PV list if part of our managed memory. 3017181641Skmacy */ 3018224746Skib if ((m->oflags & VPO_UNMANAGED) == 0 && 3019181641Skmacy !pmap_try_insert_pv_entry(pmap, va, m)) { 3020181641Skmacy if (mpte != NULL) { 3021181641Skmacy free = NULL; 3022240151Skib if (pmap_unwire_ptp(pmap, mpte, &free)) { 3023181641Skmacy pmap_invalidate_page(pmap, va); 3024181641Skmacy pmap_free_zero_pages(free); 3025181641Skmacy } 3026181641Skmacy 3027181641Skmacy mpte = NULL; 3028181641Skmacy } 3029181641Skmacy return (mpte); 3030181641Skmacy } 3031181641Skmacy 3032181641Skmacy /* 3033181641Skmacy * Increment counters 3034181641Skmacy */ 3035181641Skmacy pmap->pm_stats.resident_count++; 3036181641Skmacy 3037181641Skmacy pa = VM_PAGE_TO_PHYS(m); 3038181641Skmacy#ifdef PAE 3039181641Skmacy if ((prot & VM_PROT_EXECUTE) == 0) 3040181641Skmacy pa |= pg_nx; 3041181641Skmacy#endif 3042181641Skmacy 3043181641Skmacy#if 0 3044181641Skmacy /* 3045181641Skmacy * Now validate mapping with RO protection 3046181641Skmacy */ 3047224746Skib if ((m->oflags & VPO_UNMANAGED) != 0) 3048181641Skmacy pte_store(pte, pa | PG_V | PG_U); 3049181641Skmacy else 3050181641Skmacy pte_store(pte, pa | PG_V | PG_U | PG_MANAGED); 3051181641Skmacy#else 3052181641Skmacy /* 3053181641Skmacy * Now validate mapping with RO protection 3054181641Skmacy */ 3055224746Skib if ((m->oflags & VPO_UNMANAGED) != 0) 3056181641Skmacy pa = xpmap_ptom(pa | PG_V | PG_U); 3057181641Skmacy else 3058181641Skmacy pa = xpmap_ptom(pa | PG_V | PG_U | PG_MANAGED); 3059181641Skmacy 3060181641Skmacy mcl->op = __HYPERVISOR_update_va_mapping; 3061181641Skmacy mcl->args[0] = va; 3062181641Skmacy mcl->args[1] = (uint32_t)(pa & 0xffffffff); 3063181641Skmacy mcl->args[2] = (uint32_t)(pa >> 32); 3064181641Skmacy mcl->args[3] = 0; 3065181641Skmacy *mclpp = mcl + 1; 3066181641Skmacy *count = *count + 1; 3067181641Skmacy#endif 3068230435Salc return (mpte); 3069181641Skmacy} 3070181641Skmacy 3071181641Skmacy/* 3072181641Skmacy * Make a temporary mapping for a physical address. This is only intended 3073181641Skmacy * to be used for panic dumps. 3074181641Skmacy */ 3075181641Skmacyvoid * 3076181641Skmacypmap_kenter_temporary(vm_paddr_t pa, int i) 3077181641Skmacy{ 3078181641Skmacy vm_offset_t va; 3079200346Skmacy vm_paddr_t ma = xpmap_ptom(pa); 3080181641Skmacy 3081181641Skmacy va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE); 3082200346Skmacy PT_SET_MA(va, (ma & ~PAGE_MASK) | PG_V | pgeflag); 3083181641Skmacy invlpg(va); 3084181641Skmacy return ((void *)crashdumpmap); 3085181641Skmacy} 3086181641Skmacy 3087181641Skmacy/* 3088181641Skmacy * This code maps large physical mmap regions into the 3089181641Skmacy * processor address space. Note that some shortcuts 3090181641Skmacy * are taken, but the code works. 3091181641Skmacy */ 3092181641Skmacyvoid 3093230435Salcpmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object, 3094230435Salc vm_pindex_t pindex, vm_size_t size) 3095181641Skmacy{ 3096207419Skmacy pd_entry_t *pde; 3097207419Skmacy vm_paddr_t pa, ptepa; 3098181641Skmacy vm_page_t p; 3099207419Skmacy int pat_mode; 3100181641Skmacy 3101181641Skmacy VM_OBJECT_LOCK_ASSERT(object, MA_OWNED); 3102195840Sjhb KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG, 3103181641Skmacy ("pmap_object_init_pt: non-device object")); 3104181641Skmacy if (pseflag && 3105207419Skmacy (addr & (NBPDR - 1)) == 0 && (size & (NBPDR - 1)) == 0) { 3106207419Skmacy if (!vm_object_populate(object, pindex, pindex + atop(size))) 3107207419Skmacy return; 3108181641Skmacy p = vm_page_lookup(object, pindex); 3109207419Skmacy KASSERT(p->valid == VM_PAGE_BITS_ALL, 3110207419Skmacy ("pmap_object_init_pt: invalid page %p", p)); 3111207419Skmacy pat_mode = p->md.pat_mode; 3112230435Salc 3113207419Skmacy /* 3114207419Skmacy * Abort the mapping if the first page is not physically 3115207419Skmacy * aligned to a 2/4MB page boundary. 3116207419Skmacy */ 3117181641Skmacy ptepa = VM_PAGE_TO_PHYS(p); 3118181641Skmacy if (ptepa & (NBPDR - 1)) 3119181641Skmacy return; 3120230435Salc 3121207419Skmacy /* 3122207419Skmacy * Skip the first page. Abort the mapping if the rest of 3123207419Skmacy * the pages are not physically contiguous or have differing 3124207419Skmacy * memory attributes. 3125207419Skmacy */ 3126207419Skmacy p = TAILQ_NEXT(p, listq); 3127207419Skmacy for (pa = ptepa + PAGE_SIZE; pa < ptepa + size; 3128207419Skmacy pa += PAGE_SIZE) { 3129207419Skmacy KASSERT(p->valid == VM_PAGE_BITS_ALL, 3130207419Skmacy ("pmap_object_init_pt: invalid page %p", p)); 3131207419Skmacy if (pa != VM_PAGE_TO_PHYS(p) || 3132207419Skmacy pat_mode != p->md.pat_mode) 3133207419Skmacy return; 3134207419Skmacy p = TAILQ_NEXT(p, listq); 3135207419Skmacy } 3136230435Salc 3137230435Salc /* 3138230435Salc * Map using 2/4MB pages. Since "ptepa" is 2/4M aligned and 3139230435Salc * "size" is a multiple of 2/4M, adding the PAT setting to 3140230435Salc * "pa" will not affect the termination of this loop. 3141230435Salc */ 3142181641Skmacy PMAP_LOCK(pmap); 3143207419Skmacy for (pa = ptepa | pmap_cache_bits(pat_mode, 1); pa < ptepa + 3144207419Skmacy size; pa += NBPDR) { 3145207419Skmacy pde = pmap_pde(pmap, addr); 3146207419Skmacy if (*pde == 0) { 3147207419Skmacy pde_store(pde, pa | PG_PS | PG_M | PG_A | 3148207419Skmacy PG_U | PG_RW | PG_V); 3149207419Skmacy pmap->pm_stats.resident_count += NBPDR / 3150207419Skmacy PAGE_SIZE; 3151207419Skmacy pmap_pde_mappings++; 3152207419Skmacy } 3153207419Skmacy /* Else continue on if the PDE is already valid. */ 3154207419Skmacy addr += NBPDR; 3155181641Skmacy } 3156181641Skmacy PMAP_UNLOCK(pmap); 3157181641Skmacy } 3158181641Skmacy} 3159181641Skmacy 3160181641Skmacy/* 3161181641Skmacy * Routine: pmap_change_wiring 3162181641Skmacy * Function: Change the wiring attribute for a map/virtual-address 3163181641Skmacy * pair. 3164181641Skmacy * In/out conditions: 3165181641Skmacy * The mapping must already exist in the pmap. 3166181641Skmacy */ 3167181641Skmacyvoid 3168181641Skmacypmap_change_wiring(pmap_t pmap, vm_offset_t va, boolean_t wired) 3169181641Skmacy{ 3170181641Skmacy pt_entry_t *pte; 3171181641Skmacy 3172181641Skmacy vm_page_lock_queues(); 3173181641Skmacy PMAP_LOCK(pmap); 3174181641Skmacy pte = pmap_pte(pmap, va); 3175181641Skmacy 3176181641Skmacy if (wired && !pmap_pte_w(pte)) { 3177181641Skmacy PT_SET_VA_MA((pte), *(pte) | PG_W, TRUE); 3178181641Skmacy pmap->pm_stats.wired_count++; 3179181641Skmacy } else if (!wired && pmap_pte_w(pte)) { 3180181641Skmacy PT_SET_VA_MA((pte), *(pte) & ~PG_W, TRUE); 3181181641Skmacy pmap->pm_stats.wired_count--; 3182181641Skmacy } 3183181641Skmacy 3184181641Skmacy /* 3185181641Skmacy * Wiring is not a hardware characteristic so there is no need to 3186181641Skmacy * invalidate TLB. 3187181641Skmacy */ 3188181641Skmacy pmap_pte_release(pte); 3189181641Skmacy PMAP_UNLOCK(pmap); 3190181641Skmacy vm_page_unlock_queues(); 3191181641Skmacy} 3192181641Skmacy 3193181641Skmacy 3194181641Skmacy 3195181641Skmacy/* 3196181641Skmacy * Copy the range specified by src_addr/len 3197181641Skmacy * from the source map to the range dst_addr/len 3198181641Skmacy * in the destination map. 3199181641Skmacy * 3200181641Skmacy * This routine is only advisory and need not do anything. 3201181641Skmacy */ 3202181641Skmacy 3203181641Skmacyvoid 3204181641Skmacypmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len, 3205230435Salc vm_offset_t src_addr) 3206181641Skmacy{ 3207181641Skmacy vm_page_t free; 3208181641Skmacy vm_offset_t addr; 3209181641Skmacy vm_offset_t end_addr = src_addr + len; 3210181641Skmacy vm_offset_t pdnxt; 3211181641Skmacy 3212181641Skmacy if (dst_addr != src_addr) 3213181641Skmacy return; 3214181641Skmacy 3215181641Skmacy if (!pmap_is_current(src_pmap)) { 3216181641Skmacy CTR2(KTR_PMAP, 3217181641Skmacy "pmap_copy, skipping: pdir[PTDPTDI]=0x%jx PTDpde[0]=0x%jx", 3218181641Skmacy (src_pmap->pm_pdir[PTDPTDI] & PG_FRAME), (PTDpde[0] & PG_FRAME)); 3219181641Skmacy 3220181641Skmacy return; 3221181641Skmacy } 3222181641Skmacy CTR5(KTR_PMAP, "pmap_copy: dst_pmap=%p src_pmap=%p dst_addr=0x%x len=%d src_addr=0x%x", 3223181641Skmacy dst_pmap, src_pmap, dst_addr, len, src_addr); 3224181641Skmacy 3225216960Scperciva#ifdef HAMFISTED_LOCKING 3226216960Scperciva mtx_lock(&createdelete_lock); 3227216960Scperciva#endif 3228216960Scperciva 3229181641Skmacy vm_page_lock_queues(); 3230181641Skmacy if (dst_pmap < src_pmap) { 3231181641Skmacy PMAP_LOCK(dst_pmap); 3232181641Skmacy PMAP_LOCK(src_pmap); 3233181641Skmacy } else { 3234181641Skmacy PMAP_LOCK(src_pmap); 3235181641Skmacy PMAP_LOCK(dst_pmap); 3236181641Skmacy } 3237181641Skmacy sched_pin(); 3238181641Skmacy for (addr = src_addr; addr < end_addr; addr = pdnxt) { 3239181641Skmacy pt_entry_t *src_pte, *dst_pte; 3240181641Skmacy vm_page_t dstmpte, srcmpte; 3241181641Skmacy pd_entry_t srcptepaddr; 3242230435Salc u_int ptepindex; 3243181641Skmacy 3244208651Salc KASSERT(addr < UPT_MIN_ADDRESS, 3245208651Salc ("pmap_copy: invalid to pmap_copy page tables")); 3246181641Skmacy 3247181641Skmacy pdnxt = (addr + NBPDR) & ~PDRMASK; 3248230435Salc if (pdnxt < addr) 3249230435Salc pdnxt = end_addr; 3250181641Skmacy ptepindex = addr >> PDRSHIFT; 3251181641Skmacy 3252181641Skmacy srcptepaddr = PT_GET(&src_pmap->pm_pdir[ptepindex]); 3253181641Skmacy if (srcptepaddr == 0) 3254181641Skmacy continue; 3255181641Skmacy 3256181641Skmacy if (srcptepaddr & PG_PS) { 3257181641Skmacy if (dst_pmap->pm_pdir[ptepindex] == 0) { 3258181641Skmacy PD_SET_VA(dst_pmap, ptepindex, srcptepaddr & ~PG_W, TRUE); 3259181641Skmacy dst_pmap->pm_stats.resident_count += 3260181641Skmacy NBPDR / PAGE_SIZE; 3261181641Skmacy } 3262181641Skmacy continue; 3263181641Skmacy } 3264181641Skmacy 3265181641Skmacy srcmpte = PHYS_TO_VM_PAGE(srcptepaddr & PG_FRAME); 3266208651Salc KASSERT(srcmpte->wire_count > 0, 3267208651Salc ("pmap_copy: source page table page is unused")); 3268181641Skmacy 3269181641Skmacy if (pdnxt > end_addr) 3270181641Skmacy pdnxt = end_addr; 3271181641Skmacy 3272181641Skmacy src_pte = vtopte(addr); 3273181641Skmacy while (addr < pdnxt) { 3274181641Skmacy pt_entry_t ptetemp; 3275181641Skmacy ptetemp = *src_pte; 3276181641Skmacy /* 3277181641Skmacy * we only virtual copy managed pages 3278181641Skmacy */ 3279181641Skmacy if ((ptetemp & PG_MANAGED) != 0) { 3280181641Skmacy dstmpte = pmap_allocpte(dst_pmap, addr, 3281181641Skmacy M_NOWAIT); 3282181641Skmacy if (dstmpte == NULL) 3283230435Salc goto out; 3284181641Skmacy dst_pte = pmap_pte_quick(dst_pmap, addr); 3285181641Skmacy if (*dst_pte == 0 && 3286181641Skmacy pmap_try_insert_pv_entry(dst_pmap, addr, 3287181641Skmacy PHYS_TO_VM_PAGE(xpmap_mtop(ptetemp) & PG_FRAME))) { 3288181641Skmacy /* 3289181641Skmacy * Clear the wired, modified, and 3290181641Skmacy * accessed (referenced) bits 3291181641Skmacy * during the copy. 3292181641Skmacy */ 3293181641Skmacy KASSERT(ptetemp != 0, ("src_pte not set")); 3294181641Skmacy PT_SET_VA_MA(dst_pte, ptetemp & ~(PG_W | PG_M | PG_A), TRUE /* XXX debug */); 3295181641Skmacy KASSERT(*dst_pte == (ptetemp & ~(PG_W | PG_M | PG_A)), 3296181641Skmacy ("no pmap copy expected: 0x%jx saw: 0x%jx", 3297181641Skmacy ptetemp & ~(PG_W | PG_M | PG_A), *dst_pte)); 3298181641Skmacy dst_pmap->pm_stats.resident_count++; 3299181641Skmacy } else { 3300181641Skmacy free = NULL; 3301240151Skib if (pmap_unwire_ptp(dst_pmap, dstmpte, 3302240151Skib &free)) { 3303181641Skmacy pmap_invalidate_page(dst_pmap, 3304181641Skmacy addr); 3305181641Skmacy pmap_free_zero_pages(free); 3306181641Skmacy } 3307230435Salc goto out; 3308181641Skmacy } 3309181641Skmacy if (dstmpte->wire_count >= srcmpte->wire_count) 3310181641Skmacy break; 3311181641Skmacy } 3312181641Skmacy addr += PAGE_SIZE; 3313181641Skmacy src_pte++; 3314181641Skmacy } 3315181641Skmacy } 3316230435Salcout: 3317181641Skmacy PT_UPDATES_FLUSH(); 3318181641Skmacy sched_unpin(); 3319181641Skmacy vm_page_unlock_queues(); 3320181641Skmacy PMAP_UNLOCK(src_pmap); 3321181641Skmacy PMAP_UNLOCK(dst_pmap); 3322216960Scperciva 3323216960Scperciva#ifdef HAMFISTED_LOCKING 3324216960Scperciva mtx_unlock(&createdelete_lock); 3325216960Scperciva#endif 3326181641Skmacy} 3327181641Skmacy 3328196723Sadrianstatic __inline void 3329196723Sadrianpagezero(void *page) 3330196723Sadrian{ 3331196723Sadrian#if defined(I686_CPU) 3332196723Sadrian if (cpu_class == CPUCLASS_686) { 3333196723Sadrian#if defined(CPU_ENABLE_SSE) 3334196723Sadrian if (cpu_feature & CPUID_SSE2) 3335196723Sadrian sse2_pagezero(page); 3336196723Sadrian else 3337196723Sadrian#endif 3338196723Sadrian i686_pagezero(page); 3339196723Sadrian } else 3340196723Sadrian#endif 3341196723Sadrian bzero(page, PAGE_SIZE); 3342196723Sadrian} 3343196723Sadrian 3344181641Skmacy/* 3345181641Skmacy * pmap_zero_page zeros the specified hardware page by mapping 3346181641Skmacy * the page into KVM and using bzero to clear its contents. 3347181641Skmacy */ 3348181641Skmacyvoid 3349181641Skmacypmap_zero_page(vm_page_t m) 3350181641Skmacy{ 3351181641Skmacy struct sysmaps *sysmaps; 3352181641Skmacy 3353181641Skmacy sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)]; 3354181641Skmacy mtx_lock(&sysmaps->lock); 3355181641Skmacy if (*sysmaps->CMAP2) 3356181641Skmacy panic("pmap_zero_page: CMAP2 busy"); 3357181641Skmacy sched_pin(); 3358215587Scperciva PT_SET_MA(sysmaps->CADDR2, PG_V | PG_RW | VM_PAGE_TO_MACH(m) | PG_A | PG_M); 3359181641Skmacy pagezero(sysmaps->CADDR2); 3360181641Skmacy PT_SET_MA(sysmaps->CADDR2, 0); 3361181641Skmacy sched_unpin(); 3362181641Skmacy mtx_unlock(&sysmaps->lock); 3363181641Skmacy} 3364181641Skmacy 3365181641Skmacy/* 3366181641Skmacy * pmap_zero_page_area zeros the specified hardware page by mapping 3367181641Skmacy * the page into KVM and using bzero to clear its contents. 3368181641Skmacy * 3369181641Skmacy * off and size may not cover an area beyond a single hardware page. 3370181641Skmacy */ 3371181641Skmacyvoid 3372181641Skmacypmap_zero_page_area(vm_page_t m, int off, int size) 3373181641Skmacy{ 3374181641Skmacy struct sysmaps *sysmaps; 3375181641Skmacy 3376181641Skmacy sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)]; 3377181641Skmacy mtx_lock(&sysmaps->lock); 3378181641Skmacy if (*sysmaps->CMAP2) 3379230435Salc panic("pmap_zero_page_area: CMAP2 busy"); 3380181641Skmacy sched_pin(); 3381215587Scperciva PT_SET_MA(sysmaps->CADDR2, PG_V | PG_RW | VM_PAGE_TO_MACH(m) | PG_A | PG_M); 3382181641Skmacy 3383181641Skmacy if (off == 0 && size == PAGE_SIZE) 3384181641Skmacy pagezero(sysmaps->CADDR2); 3385181641Skmacy else 3386181641Skmacy bzero((char *)sysmaps->CADDR2 + off, size); 3387181641Skmacy PT_SET_MA(sysmaps->CADDR2, 0); 3388181641Skmacy sched_unpin(); 3389181641Skmacy mtx_unlock(&sysmaps->lock); 3390181641Skmacy} 3391181641Skmacy 3392181641Skmacy/* 3393181641Skmacy * pmap_zero_page_idle zeros the specified hardware page by mapping 3394181641Skmacy * the page into KVM and using bzero to clear its contents. This 3395181641Skmacy * is intended to be called from the vm_pagezero process only and 3396181641Skmacy * outside of Giant. 3397181641Skmacy */ 3398181641Skmacyvoid 3399181641Skmacypmap_zero_page_idle(vm_page_t m) 3400181641Skmacy{ 3401181641Skmacy 3402181641Skmacy if (*CMAP3) 3403230435Salc panic("pmap_zero_page_idle: CMAP3 busy"); 3404181641Skmacy sched_pin(); 3405215587Scperciva PT_SET_MA(CADDR3, PG_V | PG_RW | VM_PAGE_TO_MACH(m) | PG_A | PG_M); 3406181641Skmacy pagezero(CADDR3); 3407181641Skmacy PT_SET_MA(CADDR3, 0); 3408181641Skmacy sched_unpin(); 3409181641Skmacy} 3410181641Skmacy 3411181641Skmacy/* 3412181641Skmacy * pmap_copy_page copies the specified (machine independent) 3413181641Skmacy * page by mapping the page into virtual memory and using 3414181641Skmacy * bcopy to copy the page, one machine dependent page at a 3415181641Skmacy * time. 3416181641Skmacy */ 3417181641Skmacyvoid 3418181641Skmacypmap_copy_page(vm_page_t src, vm_page_t dst) 3419181641Skmacy{ 3420181641Skmacy struct sysmaps *sysmaps; 3421181641Skmacy 3422181641Skmacy sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)]; 3423181641Skmacy mtx_lock(&sysmaps->lock); 3424181641Skmacy if (*sysmaps->CMAP1) 3425181641Skmacy panic("pmap_copy_page: CMAP1 busy"); 3426181641Skmacy if (*sysmaps->CMAP2) 3427181641Skmacy panic("pmap_copy_page: CMAP2 busy"); 3428181641Skmacy sched_pin(); 3429215587Scperciva PT_SET_MA(sysmaps->CADDR1, PG_V | VM_PAGE_TO_MACH(src) | PG_A); 3430215587Scperciva PT_SET_MA(sysmaps->CADDR2, PG_V | PG_RW | VM_PAGE_TO_MACH(dst) | PG_A | PG_M); 3431181641Skmacy bcopy(sysmaps->CADDR1, sysmaps->CADDR2, PAGE_SIZE); 3432181641Skmacy PT_SET_MA(sysmaps->CADDR1, 0); 3433181641Skmacy PT_SET_MA(sysmaps->CADDR2, 0); 3434181641Skmacy sched_unpin(); 3435181641Skmacy mtx_unlock(&sysmaps->lock); 3436181641Skmacy} 3437181641Skmacy 3438181641Skmacy/* 3439181641Skmacy * Returns true if the pmap's pv is one of the first 3440181641Skmacy * 16 pvs linked to from this page. This count may 3441181641Skmacy * be changed upwards or downwards in the future; it 3442181641Skmacy * is only necessary that true be returned for a small 3443181641Skmacy * subset of pmaps for proper page aging. 3444181641Skmacy */ 3445181641Skmacyboolean_t 3446181641Skmacypmap_page_exists_quick(pmap_t pmap, vm_page_t m) 3447181641Skmacy{ 3448181641Skmacy pv_entry_t pv; 3449181641Skmacy int loops = 0; 3450208990Salc boolean_t rv; 3451181641Skmacy 3452224746Skib KASSERT((m->oflags & VPO_UNMANAGED) == 0, 3453208990Salc ("pmap_page_exists_quick: page %p is not managed", m)); 3454208990Salc rv = FALSE; 3455208990Salc vm_page_lock_queues(); 3456181641Skmacy TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 3457181641Skmacy if (PV_PMAP(pv) == pmap) { 3458208990Salc rv = TRUE; 3459208990Salc break; 3460181641Skmacy } 3461181641Skmacy loops++; 3462181641Skmacy if (loops >= 16) 3463181641Skmacy break; 3464181641Skmacy } 3465208990Salc vm_page_unlock_queues(); 3466208990Salc return (rv); 3467181641Skmacy} 3468181641Skmacy 3469181641Skmacy/* 3470181641Skmacy * pmap_page_wired_mappings: 3471181641Skmacy * 3472181641Skmacy * Return the number of managed mappings to the given physical page 3473181641Skmacy * that are wired. 3474181641Skmacy */ 3475181641Skmacyint 3476181641Skmacypmap_page_wired_mappings(vm_page_t m) 3477181641Skmacy{ 3478181641Skmacy pv_entry_t pv; 3479181641Skmacy pt_entry_t *pte; 3480181641Skmacy pmap_t pmap; 3481181641Skmacy int count; 3482181641Skmacy 3483181641Skmacy count = 0; 3484224746Skib if ((m->oflags & VPO_UNMANAGED) != 0) 3485181641Skmacy return (count); 3486207796Salc vm_page_lock_queues(); 3487181641Skmacy sched_pin(); 3488181641Skmacy TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 3489181641Skmacy pmap = PV_PMAP(pv); 3490181641Skmacy PMAP_LOCK(pmap); 3491181641Skmacy pte = pmap_pte_quick(pmap, pv->pv_va); 3492181641Skmacy if ((*pte & PG_W) != 0) 3493181641Skmacy count++; 3494181641Skmacy PMAP_UNLOCK(pmap); 3495181641Skmacy } 3496181641Skmacy sched_unpin(); 3497207796Salc vm_page_unlock_queues(); 3498181641Skmacy return (count); 3499181641Skmacy} 3500181641Skmacy 3501181641Skmacy/* 3502230431Salc * Returns TRUE if the given page is mapped. Otherwise, returns FALSE. 3503181747Skmacy */ 3504181747Skmacyboolean_t 3505181747Skmacypmap_page_is_mapped(vm_page_t m) 3506181747Skmacy{ 3507181747Skmacy 3508224746Skib if ((m->oflags & VPO_UNMANAGED) != 0) 3509181747Skmacy return (FALSE); 3510230431Salc return (!TAILQ_EMPTY(&m->md.pv_list)); 3511181747Skmacy} 3512181747Skmacy 3513181747Skmacy/* 3514181641Skmacy * Remove all pages from specified address space 3515181641Skmacy * this aids process exit speeds. Also, this code 3516181641Skmacy * is special cased for current process only, but 3517181641Skmacy * can have the more generic (and slightly slower) 3518181641Skmacy * mode enabled. This is much faster than pmap_remove 3519181641Skmacy * in the case of running down an entire address space. 3520181641Skmacy */ 3521181641Skmacyvoid 3522181641Skmacypmap_remove_pages(pmap_t pmap) 3523181641Skmacy{ 3524181641Skmacy pt_entry_t *pte, tpte; 3525181641Skmacy vm_page_t m, free = NULL; 3526181641Skmacy pv_entry_t pv; 3527181641Skmacy struct pv_chunk *pc, *npc; 3528181641Skmacy int field, idx; 3529181641Skmacy int32_t bit; 3530181641Skmacy uint32_t inuse, bitmask; 3531181641Skmacy int allfree; 3532181641Skmacy 3533181641Skmacy CTR1(KTR_PMAP, "pmap_remove_pages: pmap=%p", pmap); 3534181641Skmacy 3535181641Skmacy if (pmap != vmspace_pmap(curthread->td_proc->p_vmspace)) { 3536181641Skmacy printf("warning: pmap_remove_pages called with non-current pmap\n"); 3537181641Skmacy return; 3538181641Skmacy } 3539181641Skmacy vm_page_lock_queues(); 3540181641Skmacy KASSERT(pmap_is_current(pmap), ("removing pages from non-current pmap")); 3541181641Skmacy PMAP_LOCK(pmap); 3542181641Skmacy sched_pin(); 3543181641Skmacy TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) { 3544181641Skmacy allfree = 1; 3545181641Skmacy for (field = 0; field < _NPCM; field++) { 3546238005Salc inuse = ~pc->pc_map[field] & pc_freemask[field]; 3547181641Skmacy while (inuse != 0) { 3548181641Skmacy bit = bsfl(inuse); 3549181641Skmacy bitmask = 1UL << bit; 3550181641Skmacy idx = field * 32 + bit; 3551181641Skmacy pv = &pc->pc_pventry[idx]; 3552181641Skmacy inuse &= ~bitmask; 3553181641Skmacy 3554181641Skmacy pte = vtopte(pv->pv_va); 3555181641Skmacy tpte = *pte ? xpmap_mtop(*pte) : 0; 3556181641Skmacy 3557181641Skmacy if (tpte == 0) { 3558181641Skmacy printf( 3559181641Skmacy "TPTE at %p IS ZERO @ VA %08x\n", 3560181641Skmacy pte, pv->pv_va); 3561181641Skmacy panic("bad pte"); 3562181641Skmacy } 3563181641Skmacy 3564181641Skmacy/* 3565181641Skmacy * We cannot remove wired pages from a process' mapping at this time 3566181641Skmacy */ 3567181641Skmacy if (tpte & PG_W) { 3568181641Skmacy allfree = 0; 3569181641Skmacy continue; 3570181641Skmacy } 3571181641Skmacy 3572181641Skmacy m = PHYS_TO_VM_PAGE(tpte & PG_FRAME); 3573181641Skmacy KASSERT(m->phys_addr == (tpte & PG_FRAME), 3574181641Skmacy ("vm_page_t %p phys_addr mismatch %016jx %016jx", 3575181641Skmacy m, (uintmax_t)m->phys_addr, 3576181641Skmacy (uintmax_t)tpte)); 3577181641Skmacy 3578181641Skmacy KASSERT(m < &vm_page_array[vm_page_array_size], 3579181641Skmacy ("pmap_remove_pages: bad tpte %#jx", 3580181641Skmacy (uintmax_t)tpte)); 3581181641Skmacy 3582181641Skmacy 3583181641Skmacy PT_CLEAR_VA(pte, FALSE); 3584181641Skmacy 3585181641Skmacy /* 3586181641Skmacy * Update the vm_page_t clean/reference bits. 3587181641Skmacy */ 3588181641Skmacy if (tpte & PG_M) 3589181641Skmacy vm_page_dirty(m); 3590181641Skmacy 3591181641Skmacy TAILQ_REMOVE(&m->md.pv_list, pv, pv_list); 3592181641Skmacy if (TAILQ_EMPTY(&m->md.pv_list)) 3593225418Skib vm_page_aflag_clear(m, PGA_WRITEABLE); 3594181641Skmacy 3595181641Skmacy pmap_unuse_pt(pmap, pv->pv_va, &free); 3596181641Skmacy 3597181641Skmacy /* Mark free */ 3598181641Skmacy PV_STAT(pv_entry_frees++); 3599181641Skmacy PV_STAT(pv_entry_spare++); 3600181641Skmacy pv_entry_count--; 3601181641Skmacy pc->pc_map[field] |= bitmask; 3602181641Skmacy pmap->pm_stats.resident_count--; 3603181641Skmacy } 3604181641Skmacy } 3605181641Skmacy PT_UPDATES_FLUSH(); 3606181641Skmacy if (allfree) { 3607181641Skmacy TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 3608237950Salc free_pv_chunk(pc); 3609181641Skmacy } 3610181641Skmacy } 3611181641Skmacy PT_UPDATES_FLUSH(); 3612181641Skmacy if (*PMAP1) 3613181641Skmacy PT_SET_MA(PADDR1, 0); 3614181641Skmacy 3615181641Skmacy sched_unpin(); 3616181641Skmacy pmap_invalidate_all(pmap); 3617181641Skmacy vm_page_unlock_queues(); 3618181641Skmacy PMAP_UNLOCK(pmap); 3619181641Skmacy pmap_free_zero_pages(free); 3620181641Skmacy} 3621181641Skmacy 3622181641Skmacy/* 3623181641Skmacy * pmap_is_modified: 3624181641Skmacy * 3625181641Skmacy * Return whether or not the specified physical page was modified 3626181641Skmacy * in any physical maps. 3627181641Skmacy */ 3628181641Skmacyboolean_t 3629181641Skmacypmap_is_modified(vm_page_t m) 3630181641Skmacy{ 3631181641Skmacy pv_entry_t pv; 3632181641Skmacy pt_entry_t *pte; 3633181641Skmacy pmap_t pmap; 3634181641Skmacy boolean_t rv; 3635181641Skmacy 3636224746Skib KASSERT((m->oflags & VPO_UNMANAGED) == 0, 3637208504Salc ("pmap_is_modified: page %p is not managed", m)); 3638181641Skmacy rv = FALSE; 3639208504Salc 3640208504Salc /* 3641225418Skib * If the page is not VPO_BUSY, then PGA_WRITEABLE cannot be 3642225418Skib * concurrently set while the object is locked. Thus, if PGA_WRITEABLE 3643208504Salc * is clear, no PTEs can have PG_M set. 3644208504Salc */ 3645208504Salc VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 3646208504Salc if ((m->oflags & VPO_BUSY) == 0 && 3647225418Skib (m->aflags & PGA_WRITEABLE) == 0) 3648181641Skmacy return (rv); 3649208504Salc vm_page_lock_queues(); 3650181641Skmacy sched_pin(); 3651181641Skmacy TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 3652181641Skmacy pmap = PV_PMAP(pv); 3653181641Skmacy PMAP_LOCK(pmap); 3654181641Skmacy pte = pmap_pte_quick(pmap, pv->pv_va); 3655181641Skmacy rv = (*pte & PG_M) != 0; 3656181641Skmacy PMAP_UNLOCK(pmap); 3657181641Skmacy if (rv) 3658181641Skmacy break; 3659181641Skmacy } 3660181641Skmacy if (*PMAP1) 3661181641Skmacy PT_SET_MA(PADDR1, 0); 3662181641Skmacy sched_unpin(); 3663208504Salc vm_page_unlock_queues(); 3664181641Skmacy return (rv); 3665181641Skmacy} 3666181641Skmacy 3667181641Skmacy/* 3668181641Skmacy * pmap_is_prefaultable: 3669181641Skmacy * 3670181641Skmacy * Return whether or not the specified virtual address is elgible 3671181641Skmacy * for prefault. 3672181641Skmacy */ 3673181641Skmacystatic boolean_t 3674181641Skmacypmap_is_prefaultable_locked(pmap_t pmap, vm_offset_t addr) 3675181641Skmacy{ 3676181641Skmacy pt_entry_t *pte; 3677181641Skmacy boolean_t rv = FALSE; 3678181641Skmacy 3679181641Skmacy return (rv); 3680181641Skmacy 3681181641Skmacy if (pmap_is_current(pmap) && *pmap_pde(pmap, addr)) { 3682181641Skmacy pte = vtopte(addr); 3683181641Skmacy rv = (*pte == 0); 3684181641Skmacy } 3685181641Skmacy return (rv); 3686181641Skmacy} 3687181641Skmacy 3688181641Skmacyboolean_t 3689181641Skmacypmap_is_prefaultable(pmap_t pmap, vm_offset_t addr) 3690181641Skmacy{ 3691181641Skmacy boolean_t rv; 3692181641Skmacy 3693181641Skmacy PMAP_LOCK(pmap); 3694181641Skmacy rv = pmap_is_prefaultable_locked(pmap, addr); 3695181641Skmacy PMAP_UNLOCK(pmap); 3696181641Skmacy return (rv); 3697181641Skmacy} 3698181641Skmacy 3699207155Salcboolean_t 3700207155Salcpmap_is_referenced(vm_page_t m) 3701207155Salc{ 3702207155Salc pv_entry_t pv; 3703207155Salc pt_entry_t *pte; 3704207155Salc pmap_t pmap; 3705207155Salc boolean_t rv; 3706207155Salc 3707224746Skib KASSERT((m->oflags & VPO_UNMANAGED) == 0, 3708208574Salc ("pmap_is_referenced: page %p is not managed", m)); 3709207155Salc rv = FALSE; 3710208574Salc vm_page_lock_queues(); 3711207155Salc sched_pin(); 3712207155Salc TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 3713207155Salc pmap = PV_PMAP(pv); 3714207155Salc PMAP_LOCK(pmap); 3715207155Salc pte = pmap_pte_quick(pmap, pv->pv_va); 3716207155Salc rv = (*pte & (PG_A | PG_V)) == (PG_A | PG_V); 3717207155Salc PMAP_UNLOCK(pmap); 3718207155Salc if (rv) 3719207155Salc break; 3720207155Salc } 3721207155Salc if (*PMAP1) 3722207155Salc PT_SET_MA(PADDR1, 0); 3723207155Salc sched_unpin(); 3724208574Salc vm_page_unlock_queues(); 3725207155Salc return (rv); 3726207155Salc} 3727207155Salc 3728181641Skmacyvoid 3729181641Skmacypmap_map_readonly(pmap_t pmap, vm_offset_t va, int len) 3730181641Skmacy{ 3731181641Skmacy int i, npages = round_page(len) >> PAGE_SHIFT; 3732181641Skmacy for (i = 0; i < npages; i++) { 3733181641Skmacy pt_entry_t *pte; 3734181641Skmacy pte = pmap_pte(pmap, (vm_offset_t)(va + i*PAGE_SIZE)); 3735216843Scperciva vm_page_lock_queues(); 3736181641Skmacy pte_store(pte, xpmap_mtop(*pte & ~(PG_RW|PG_M))); 3737216843Scperciva vm_page_unlock_queues(); 3738181641Skmacy PMAP_MARK_PRIV(xpmap_mtop(*pte)); 3739181641Skmacy pmap_pte_release(pte); 3740181641Skmacy } 3741181641Skmacy} 3742181641Skmacy 3743181641Skmacyvoid 3744181641Skmacypmap_map_readwrite(pmap_t pmap, vm_offset_t va, int len) 3745181641Skmacy{ 3746181641Skmacy int i, npages = round_page(len) >> PAGE_SHIFT; 3747181641Skmacy for (i = 0; i < npages; i++) { 3748181641Skmacy pt_entry_t *pte; 3749181641Skmacy pte = pmap_pte(pmap, (vm_offset_t)(va + i*PAGE_SIZE)); 3750181641Skmacy PMAP_MARK_UNPRIV(xpmap_mtop(*pte)); 3751216843Scperciva vm_page_lock_queues(); 3752181641Skmacy pte_store(pte, xpmap_mtop(*pte) | (PG_RW|PG_M)); 3753216843Scperciva vm_page_unlock_queues(); 3754181641Skmacy pmap_pte_release(pte); 3755181641Skmacy } 3756181641Skmacy} 3757181641Skmacy 3758181641Skmacy/* 3759181641Skmacy * Clear the write and modified bits in each of the given page's mappings. 3760181641Skmacy */ 3761181641Skmacyvoid 3762181641Skmacypmap_remove_write(vm_page_t m) 3763181641Skmacy{ 3764181641Skmacy pv_entry_t pv; 3765181641Skmacy pmap_t pmap; 3766181641Skmacy pt_entry_t oldpte, *pte; 3767181641Skmacy 3768224746Skib KASSERT((m->oflags & VPO_UNMANAGED) == 0, 3769208175Salc ("pmap_remove_write: page %p is not managed", m)); 3770208175Salc 3771208175Salc /* 3772225418Skib * If the page is not VPO_BUSY, then PGA_WRITEABLE cannot be set by 3773225418Skib * another thread while the object is locked. Thus, if PGA_WRITEABLE 3774208175Salc * is clear, no page table entries need updating. 3775208175Salc */ 3776208175Salc VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 3777208175Salc if ((m->oflags & VPO_BUSY) == 0 && 3778225418Skib (m->aflags & PGA_WRITEABLE) == 0) 3779181641Skmacy return; 3780207796Salc vm_page_lock_queues(); 3781181641Skmacy sched_pin(); 3782181641Skmacy TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 3783181641Skmacy pmap = PV_PMAP(pv); 3784181641Skmacy PMAP_LOCK(pmap); 3785181641Skmacy pte = pmap_pte_quick(pmap, pv->pv_va); 3786181641Skmacyretry: 3787181641Skmacy oldpte = *pte; 3788181641Skmacy if ((oldpte & PG_RW) != 0) { 3789188341Skmacy vm_paddr_t newpte = oldpte & ~(PG_RW | PG_M); 3790188341Skmacy 3791181641Skmacy /* 3792181641Skmacy * Regardless of whether a pte is 32 or 64 bits 3793181641Skmacy * in size, PG_RW and PG_M are among the least 3794181641Skmacy * significant 32 bits. 3795181641Skmacy */ 3796188341Skmacy PT_SET_VA_MA(pte, newpte, TRUE); 3797188341Skmacy if (*pte != newpte) 3798181641Skmacy goto retry; 3799188341Skmacy 3800181641Skmacy if ((oldpte & PG_M) != 0) 3801181641Skmacy vm_page_dirty(m); 3802181641Skmacy pmap_invalidate_page(pmap, pv->pv_va); 3803181641Skmacy } 3804181641Skmacy PMAP_UNLOCK(pmap); 3805181641Skmacy } 3806225418Skib vm_page_aflag_clear(m, PGA_WRITEABLE); 3807181641Skmacy PT_UPDATES_FLUSH(); 3808181641Skmacy if (*PMAP1) 3809181641Skmacy PT_SET_MA(PADDR1, 0); 3810181641Skmacy sched_unpin(); 3811207796Salc vm_page_unlock_queues(); 3812181641Skmacy} 3813181641Skmacy 3814181641Skmacy/* 3815181641Skmacy * pmap_ts_referenced: 3816181641Skmacy * 3817181641Skmacy * Return a count of reference bits for a page, clearing those bits. 3818181641Skmacy * It is not necessary for every reference bit to be cleared, but it 3819181641Skmacy * is necessary that 0 only be returned when there are truly no 3820181641Skmacy * reference bits set. 3821181641Skmacy * 3822181641Skmacy * XXX: The exact number of bits to check and clear is a matter that 3823181641Skmacy * should be tested and standardized at some point in the future for 3824181641Skmacy * optimal aging of shared pages. 3825181641Skmacy */ 3826181641Skmacyint 3827181641Skmacypmap_ts_referenced(vm_page_t m) 3828181641Skmacy{ 3829181641Skmacy pv_entry_t pv, pvf, pvn; 3830181641Skmacy pmap_t pmap; 3831181641Skmacy pt_entry_t *pte; 3832181641Skmacy int rtval = 0; 3833181641Skmacy 3834224746Skib KASSERT((m->oflags & VPO_UNMANAGED) == 0, 3835208990Salc ("pmap_ts_referenced: page %p is not managed", m)); 3836208990Salc vm_page_lock_queues(); 3837181641Skmacy sched_pin(); 3838181641Skmacy if ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) { 3839181641Skmacy pvf = pv; 3840181641Skmacy do { 3841181641Skmacy pvn = TAILQ_NEXT(pv, pv_list); 3842181641Skmacy TAILQ_REMOVE(&m->md.pv_list, pv, pv_list); 3843181641Skmacy TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list); 3844181641Skmacy pmap = PV_PMAP(pv); 3845181641Skmacy PMAP_LOCK(pmap); 3846181641Skmacy pte = pmap_pte_quick(pmap, pv->pv_va); 3847181641Skmacy if ((*pte & PG_A) != 0) { 3848181641Skmacy PT_SET_VA_MA(pte, *pte & ~PG_A, FALSE); 3849181641Skmacy pmap_invalidate_page(pmap, pv->pv_va); 3850181641Skmacy rtval++; 3851181641Skmacy if (rtval > 4) 3852181641Skmacy pvn = NULL; 3853181641Skmacy } 3854181641Skmacy PMAP_UNLOCK(pmap); 3855181641Skmacy } while ((pv = pvn) != NULL && pv != pvf); 3856181641Skmacy } 3857181641Skmacy PT_UPDATES_FLUSH(); 3858181641Skmacy if (*PMAP1) 3859181641Skmacy PT_SET_MA(PADDR1, 0); 3860181641Skmacy sched_unpin(); 3861208990Salc vm_page_unlock_queues(); 3862181641Skmacy return (rtval); 3863181641Skmacy} 3864181641Skmacy 3865181641Skmacy/* 3866181641Skmacy * Clear the modify bits on the specified physical page. 3867181641Skmacy */ 3868181641Skmacyvoid 3869181641Skmacypmap_clear_modify(vm_page_t m) 3870181641Skmacy{ 3871181641Skmacy pv_entry_t pv; 3872181641Skmacy pmap_t pmap; 3873181641Skmacy pt_entry_t *pte; 3874181641Skmacy 3875224746Skib KASSERT((m->oflags & VPO_UNMANAGED) == 0, 3876208504Salc ("pmap_clear_modify: page %p is not managed", m)); 3877208504Salc VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 3878208504Salc KASSERT((m->oflags & VPO_BUSY) == 0, 3879208504Salc ("pmap_clear_modify: page %p is busy", m)); 3880208504Salc 3881208504Salc /* 3882225418Skib * If the page is not PGA_WRITEABLE, then no PTEs can have PG_M set. 3883208504Salc * If the object containing the page is locked and the page is not 3884225418Skib * VPO_BUSY, then PGA_WRITEABLE cannot be concurrently set. 3885208504Salc */ 3886225418Skib if ((m->aflags & PGA_WRITEABLE) == 0) 3887181641Skmacy return; 3888208504Salc vm_page_lock_queues(); 3889181641Skmacy sched_pin(); 3890181641Skmacy TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 3891181641Skmacy pmap = PV_PMAP(pv); 3892181641Skmacy PMAP_LOCK(pmap); 3893181641Skmacy pte = pmap_pte_quick(pmap, pv->pv_va); 3894230435Salc if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) { 3895181641Skmacy /* 3896181641Skmacy * Regardless of whether a pte is 32 or 64 bits 3897181641Skmacy * in size, PG_M is among the least significant 3898181641Skmacy * 32 bits. 3899181641Skmacy */ 3900181641Skmacy PT_SET_VA_MA(pte, *pte & ~PG_M, FALSE); 3901181641Skmacy pmap_invalidate_page(pmap, pv->pv_va); 3902181641Skmacy } 3903181641Skmacy PMAP_UNLOCK(pmap); 3904181641Skmacy } 3905181641Skmacy sched_unpin(); 3906208504Salc vm_page_unlock_queues(); 3907181641Skmacy} 3908181641Skmacy 3909181641Skmacy/* 3910181641Skmacy * pmap_clear_reference: 3911181641Skmacy * 3912181641Skmacy * Clear the reference bit on the specified physical page. 3913181641Skmacy */ 3914181641Skmacyvoid 3915181641Skmacypmap_clear_reference(vm_page_t m) 3916181641Skmacy{ 3917181641Skmacy pv_entry_t pv; 3918181641Skmacy pmap_t pmap; 3919181641Skmacy pt_entry_t *pte; 3920181641Skmacy 3921224746Skib KASSERT((m->oflags & VPO_UNMANAGED) == 0, 3922208504Salc ("pmap_clear_reference: page %p is not managed", m)); 3923208504Salc vm_page_lock_queues(); 3924181641Skmacy sched_pin(); 3925181641Skmacy TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 3926181641Skmacy pmap = PV_PMAP(pv); 3927181641Skmacy PMAP_LOCK(pmap); 3928181641Skmacy pte = pmap_pte_quick(pmap, pv->pv_va); 3929181641Skmacy if ((*pte & PG_A) != 0) { 3930181641Skmacy /* 3931181641Skmacy * Regardless of whether a pte is 32 or 64 bits 3932181641Skmacy * in size, PG_A is among the least significant 3933181641Skmacy * 32 bits. 3934181641Skmacy */ 3935181641Skmacy PT_SET_VA_MA(pte, *pte & ~PG_A, FALSE); 3936181641Skmacy pmap_invalidate_page(pmap, pv->pv_va); 3937181641Skmacy } 3938181641Skmacy PMAP_UNLOCK(pmap); 3939181641Skmacy } 3940181641Skmacy sched_unpin(); 3941208504Salc vm_page_unlock_queues(); 3942181641Skmacy} 3943181641Skmacy 3944181641Skmacy/* 3945181641Skmacy * Miscellaneous support routines follow 3946181641Skmacy */ 3947181641Skmacy 3948181641Skmacy/* 3949181641Skmacy * Map a set of physical memory pages into the kernel virtual 3950181641Skmacy * address space. Return a pointer to where it is mapped. This 3951181641Skmacy * routine is intended to be used for mapping device memory, 3952181641Skmacy * NOT real memory. 3953181641Skmacy */ 3954181641Skmacyvoid * 3955181641Skmacypmap_mapdev_attr(vm_paddr_t pa, vm_size_t size, int mode) 3956181641Skmacy{ 3957195949Skib vm_offset_t va, offset; 3958195949Skib vm_size_t tmpsize; 3959181641Skmacy 3960181641Skmacy offset = pa & PAGE_MASK; 3961181641Skmacy size = roundup(offset + size, PAGE_SIZE); 3962181641Skmacy pa = pa & PG_FRAME; 3963181641Skmacy 3964181641Skmacy if (pa < KERNLOAD && pa + size <= KERNLOAD) 3965181641Skmacy va = KERNBASE + pa; 3966181641Skmacy else 3967181641Skmacy va = kmem_alloc_nofault(kernel_map, size); 3968181641Skmacy if (!va) 3969181641Skmacy panic("pmap_mapdev: Couldn't alloc kernel virtual memory"); 3970181641Skmacy 3971195949Skib for (tmpsize = 0; tmpsize < size; tmpsize += PAGE_SIZE) 3972195949Skib pmap_kenter_attr(va + tmpsize, pa + tmpsize, mode); 3973195949Skib pmap_invalidate_range(kernel_pmap, va, va + tmpsize); 3974195949Skib pmap_invalidate_cache_range(va, va + size); 3975181641Skmacy return ((void *)(va + offset)); 3976181641Skmacy} 3977181641Skmacy 3978181641Skmacyvoid * 3979181641Skmacypmap_mapdev(vm_paddr_t pa, vm_size_t size) 3980181641Skmacy{ 3981181641Skmacy 3982181641Skmacy return (pmap_mapdev_attr(pa, size, PAT_UNCACHEABLE)); 3983181641Skmacy} 3984181641Skmacy 3985181641Skmacyvoid * 3986181641Skmacypmap_mapbios(vm_paddr_t pa, vm_size_t size) 3987181641Skmacy{ 3988181641Skmacy 3989181641Skmacy return (pmap_mapdev_attr(pa, size, PAT_WRITE_BACK)); 3990181641Skmacy} 3991181641Skmacy 3992181641Skmacyvoid 3993181641Skmacypmap_unmapdev(vm_offset_t va, vm_size_t size) 3994181641Skmacy{ 3995181641Skmacy vm_offset_t base, offset, tmpva; 3996181641Skmacy 3997181641Skmacy if (va >= KERNBASE && va + size <= KERNBASE + KERNLOAD) 3998181641Skmacy return; 3999181641Skmacy base = trunc_page(va); 4000181641Skmacy offset = va & PAGE_MASK; 4001181641Skmacy size = roundup(offset + size, PAGE_SIZE); 4002181641Skmacy critical_enter(); 4003181641Skmacy for (tmpva = base; tmpva < (base + size); tmpva += PAGE_SIZE) 4004181641Skmacy pmap_kremove(tmpva); 4005181641Skmacy pmap_invalidate_range(kernel_pmap, va, tmpva); 4006181641Skmacy critical_exit(); 4007181641Skmacy kmem_free(kernel_map, base, size); 4008181641Skmacy} 4009181641Skmacy 4010195774Salc/* 4011195774Salc * Sets the memory attribute for the specified page. 4012195774Salc */ 4013195774Salcvoid 4014195774Salcpmap_page_set_memattr(vm_page_t m, vm_memattr_t ma) 4015195774Salc{ 4016195774Salc 4017195774Salc m->md.pat_mode = ma; 4018195949Skib if ((m->flags & PG_FICTITIOUS) != 0) 4019195949Skib return; 4020195774Salc 4021195774Salc /* 4022195774Salc * If "m" is a normal page, flush it from the cache. 4023195949Skib * See pmap_invalidate_cache_range(). 4024195949Skib * 4025195949Skib * First, try to find an existing mapping of the page by sf 4026195949Skib * buffer. sf_buf_invalidate_cache() modifies mapping and 4027195949Skib * flushes the cache. 4028195774Salc */ 4029195949Skib if (sf_buf_invalidate_cache(m)) 4030195949Skib return; 4031195949Skib 4032195949Skib /* 4033195949Skib * If page is not mapped by sf buffer, but CPU does not 4034195949Skib * support self snoop, map the page transient and do 4035195949Skib * invalidation. In the worst case, whole cache is flushed by 4036195949Skib * pmap_invalidate_cache_range(). 4037195949Skib */ 4038230435Salc if ((cpu_feature & CPUID_SS) == 0) 4039230435Salc pmap_flush_page(m); 4040230435Salc} 4041230435Salc 4042230435Salcstatic void 4043230435Salcpmap_flush_page(vm_page_t m) 4044230435Salc{ 4045230435Salc struct sysmaps *sysmaps; 4046230435Salc vm_offset_t sva, eva; 4047230435Salc 4048230435Salc if ((cpu_feature & CPUID_CLFSH) != 0) { 4049195949Skib sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)]; 4050195949Skib mtx_lock(&sysmaps->lock); 4051195949Skib if (*sysmaps->CMAP2) 4052230435Salc panic("pmap_flush_page: CMAP2 busy"); 4053195949Skib sched_pin(); 4054195949Skib PT_SET_MA(sysmaps->CADDR2, PG_V | PG_RW | 4055215587Scperciva VM_PAGE_TO_MACH(m) | PG_A | PG_M | 4056195949Skib pmap_cache_bits(m->md.pat_mode, 0)); 4057195949Skib invlcaddr(sysmaps->CADDR2); 4058195949Skib sva = (vm_offset_t)sysmaps->CADDR2; 4059195949Skib eva = sva + PAGE_SIZE; 4060230435Salc 4061230435Salc /* 4062230435Salc * Use mfence despite the ordering implied by 4063230435Salc * mtx_{un,}lock() because clflush is not guaranteed 4064230435Salc * to be ordered by any other instruction. 4065230435Salc */ 4066230435Salc mfence(); 4067230435Salc for (; sva < eva; sva += cpu_clflush_line_size) 4068230435Salc clflush(sva); 4069230435Salc mfence(); 4070195949Skib PT_SET_MA(sysmaps->CADDR2, 0); 4071195949Skib sched_unpin(); 4072195949Skib mtx_unlock(&sysmaps->lock); 4073230435Salc } else 4074230435Salc pmap_invalidate_cache(); 4075195774Salc} 4076195774Salc 4077230435Salc/* 4078230435Salc * Changes the specified virtual address range's memory type to that given by 4079230435Salc * the parameter "mode". The specified virtual address range must be 4080230435Salc * completely contained within either the kernel map. 4081230435Salc * 4082230435Salc * Returns zero if the change completed successfully, and either EINVAL or 4083230435Salc * ENOMEM if the change failed. Specifically, EINVAL is returned if some part 4084230435Salc * of the virtual address range was not mapped, and ENOMEM is returned if 4085230435Salc * there was insufficient memory available to complete the change. 4086230435Salc */ 4087181641Skmacyint 4088230435Salcpmap_change_attr(vm_offset_t va, vm_size_t size, int mode) 4089181641Skmacy{ 4090181641Skmacy vm_offset_t base, offset, tmpva; 4091181641Skmacy pt_entry_t *pte; 4092181641Skmacy u_int opte, npte; 4093181641Skmacy pd_entry_t *pde; 4094195949Skib boolean_t changed; 4095181641Skmacy 4096181641Skmacy base = trunc_page(va); 4097181641Skmacy offset = va & PAGE_MASK; 4098181641Skmacy size = roundup(offset + size, PAGE_SIZE); 4099181641Skmacy 4100181641Skmacy /* Only supported on kernel virtual addresses. */ 4101181641Skmacy if (base <= VM_MAXUSER_ADDRESS) 4102181641Skmacy return (EINVAL); 4103181641Skmacy 4104181641Skmacy /* 4MB pages and pages that aren't mapped aren't supported. */ 4105181641Skmacy for (tmpva = base; tmpva < (base + size); tmpva += PAGE_SIZE) { 4106181641Skmacy pde = pmap_pde(kernel_pmap, tmpva); 4107181641Skmacy if (*pde & PG_PS) 4108181641Skmacy return (EINVAL); 4109181641Skmacy if ((*pde & PG_V) == 0) 4110181641Skmacy return (EINVAL); 4111181641Skmacy pte = vtopte(va); 4112181641Skmacy if ((*pte & PG_V) == 0) 4113181641Skmacy return (EINVAL); 4114181641Skmacy } 4115181641Skmacy 4116195949Skib changed = FALSE; 4117195949Skib 4118181641Skmacy /* 4119181641Skmacy * Ok, all the pages exist and are 4k, so run through them updating 4120181641Skmacy * their cache mode. 4121181641Skmacy */ 4122181641Skmacy for (tmpva = base; size > 0; ) { 4123181641Skmacy pte = vtopte(tmpva); 4124181641Skmacy 4125181641Skmacy /* 4126181641Skmacy * The cache mode bits are all in the low 32-bits of the 4127181641Skmacy * PTE, so we can just spin on updating the low 32-bits. 4128181641Skmacy */ 4129181641Skmacy do { 4130181641Skmacy opte = *(u_int *)pte; 4131181641Skmacy npte = opte & ~(PG_PTE_PAT | PG_NC_PCD | PG_NC_PWT); 4132181641Skmacy npte |= pmap_cache_bits(mode, 0); 4133181641Skmacy PT_SET_VA_MA(pte, npte, TRUE); 4134181641Skmacy } while (npte != opte && (*pte != npte)); 4135195949Skib if (npte != opte) 4136195949Skib changed = TRUE; 4137181641Skmacy tmpva += PAGE_SIZE; 4138181641Skmacy size -= PAGE_SIZE; 4139181641Skmacy } 4140181641Skmacy 4141181641Skmacy /* 4142230435Salc * Flush CPU caches to make sure any data isn't cached that 4143230435Salc * shouldn't be, etc. 4144181641Skmacy */ 4145195949Skib if (changed) { 4146195949Skib pmap_invalidate_range(kernel_pmap, base, tmpva); 4147195949Skib pmap_invalidate_cache_range(base, tmpva); 4148195949Skib } 4149181641Skmacy return (0); 4150181641Skmacy} 4151181641Skmacy 4152181641Skmacy/* 4153181641Skmacy * perform the pmap work for mincore 4154181641Skmacy */ 4155181641Skmacyint 4156208504Salcpmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa) 4157181641Skmacy{ 4158181641Skmacy pt_entry_t *ptep, pte; 4159208504Salc vm_paddr_t pa; 4160208504Salc int val; 4161230435Salc 4162181641Skmacy PMAP_LOCK(pmap); 4163208504Salcretry: 4164181641Skmacy ptep = pmap_pte(pmap, addr); 4165181641Skmacy pte = (ptep != NULL) ? PT_GET(ptep) : 0; 4166181641Skmacy pmap_pte_release(ptep); 4167208504Salc val = 0; 4168208504Salc if ((pte & PG_V) != 0) { 4169208504Salc val |= MINCORE_INCORE; 4170208504Salc if ((pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) 4171208504Salc val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER; 4172208504Salc if ((pte & PG_A) != 0) 4173208504Salc val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER; 4174208504Salc } 4175208504Salc if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) != 4176208504Salc (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) && 4177208504Salc (pte & (PG_MANAGED | PG_V)) == (PG_MANAGED | PG_V)) { 4178208504Salc pa = pte & PG_FRAME; 4179208504Salc /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */ 4180208504Salc if (vm_page_pa_tryrelock(pmap, pa, locked_pa)) 4181208504Salc goto retry; 4182208504Salc } else 4183208504Salc PA_UNLOCK_COND(*locked_pa); 4184181641Skmacy PMAP_UNLOCK(pmap); 4185208504Salc return (val); 4186181641Skmacy} 4187181641Skmacy 4188181641Skmacyvoid 4189181641Skmacypmap_activate(struct thread *td) 4190181641Skmacy{ 4191181641Skmacy pmap_t pmap, oldpmap; 4192223758Sattilio u_int cpuid; 4193181641Skmacy u_int32_t cr3; 4194181641Skmacy 4195181641Skmacy critical_enter(); 4196181641Skmacy pmap = vmspace_pmap(td->td_proc->p_vmspace); 4197181641Skmacy oldpmap = PCPU_GET(curpmap); 4198223758Sattilio cpuid = PCPU_GET(cpuid); 4199181641Skmacy#if defined(SMP) 4200223758Sattilio CPU_CLR_ATOMIC(cpuid, &oldpmap->pm_active); 4201223758Sattilio CPU_SET_ATOMIC(cpuid, &pmap->pm_active); 4202181641Skmacy#else 4203223758Sattilio CPU_CLR(cpuid, &oldpmap->pm_active); 4204223758Sattilio CPU_SET(cpuid, &pmap->pm_active); 4205181641Skmacy#endif 4206181641Skmacy#ifdef PAE 4207181641Skmacy cr3 = vtophys(pmap->pm_pdpt); 4208181641Skmacy#else 4209181641Skmacy cr3 = vtophys(pmap->pm_pdir); 4210181641Skmacy#endif 4211181641Skmacy /* 4212181641Skmacy * pmap_activate is for the current thread on the current cpu 4213181641Skmacy */ 4214181641Skmacy td->td_pcb->pcb_cr3 = cr3; 4215181641Skmacy PT_UPDATES_FLUSH(); 4216181641Skmacy load_cr3(cr3); 4217181641Skmacy PCPU_SET(curpmap, pmap); 4218181641Skmacy critical_exit(); 4219181641Skmacy} 4220181641Skmacy 4221198341Smarcelvoid 4222198341Smarcelpmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz) 4223198341Smarcel{ 4224198341Smarcel} 4225198341Smarcel 4226181747Skmacy/* 4227181747Skmacy * Increase the starting virtual address of the given mapping if a 4228181747Skmacy * different alignment might result in more superpage mappings. 4229181747Skmacy */ 4230181747Skmacyvoid 4231181747Skmacypmap_align_superpage(vm_object_t object, vm_ooffset_t offset, 4232181747Skmacy vm_offset_t *addr, vm_size_t size) 4233181641Skmacy{ 4234181747Skmacy vm_offset_t superpage_offset; 4235181641Skmacy 4236181747Skmacy if (size < NBPDR) 4237181747Skmacy return; 4238181747Skmacy if (object != NULL && (object->flags & OBJ_COLORED) != 0) 4239181747Skmacy offset += ptoa(object->pg_color); 4240181747Skmacy superpage_offset = offset & PDRMASK; 4241181747Skmacy if (size - ((NBPDR - superpage_offset) & PDRMASK) < NBPDR || 4242181747Skmacy (*addr & PDRMASK) == superpage_offset) 4243181747Skmacy return; 4244181747Skmacy if ((*addr & PDRMASK) < superpage_offset) 4245181747Skmacy *addr = (*addr & ~PDRMASK) + superpage_offset; 4246181747Skmacy else 4247181747Skmacy *addr = ((*addr + PDRMASK) & ~PDRMASK) + superpage_offset; 4248181641Skmacy} 4249181641Skmacy 4250190627Sdfrvoid 4251190627Sdfrpmap_suspend() 4252190627Sdfr{ 4253190627Sdfr pmap_t pmap; 4254190627Sdfr int i, pdir, offset; 4255190627Sdfr vm_paddr_t pdirma; 4256190627Sdfr mmu_update_t mu[4]; 4257190627Sdfr 4258190627Sdfr /* 4259190627Sdfr * We need to remove the recursive mapping structure from all 4260190627Sdfr * our pmaps so that Xen doesn't get confused when it restores 4261190627Sdfr * the page tables. The recursive map lives at page directory 4262190627Sdfr * index PTDPTDI. We assume that the suspend code has stopped 4263190627Sdfr * the other vcpus (if any). 4264190627Sdfr */ 4265190627Sdfr LIST_FOREACH(pmap, &allpmaps, pm_list) { 4266190627Sdfr for (i = 0; i < 4; i++) { 4267190627Sdfr /* 4268190627Sdfr * Figure out which page directory (L2) page 4269190627Sdfr * contains this bit of the recursive map and 4270190627Sdfr * the offset within that page of the map 4271190627Sdfr * entry 4272190627Sdfr */ 4273190627Sdfr pdir = (PTDPTDI + i) / NPDEPG; 4274190627Sdfr offset = (PTDPTDI + i) % NPDEPG; 4275190627Sdfr pdirma = pmap->pm_pdpt[pdir] & PG_FRAME; 4276190627Sdfr mu[i].ptr = pdirma + offset * sizeof(pd_entry_t); 4277190627Sdfr mu[i].val = 0; 4278190627Sdfr } 4279190627Sdfr HYPERVISOR_mmu_update(mu, 4, NULL, DOMID_SELF); 4280190627Sdfr } 4281190627Sdfr} 4282190627Sdfr 4283190627Sdfrvoid 4284190627Sdfrpmap_resume() 4285190627Sdfr{ 4286190627Sdfr pmap_t pmap; 4287190627Sdfr int i, pdir, offset; 4288190627Sdfr vm_paddr_t pdirma; 4289190627Sdfr mmu_update_t mu[4]; 4290190627Sdfr 4291190627Sdfr /* 4292190627Sdfr * Restore the recursive map that we removed on suspend. 4293190627Sdfr */ 4294190627Sdfr LIST_FOREACH(pmap, &allpmaps, pm_list) { 4295190627Sdfr for (i = 0; i < 4; i++) { 4296190627Sdfr /* 4297190627Sdfr * Figure out which page directory (L2) page 4298190627Sdfr * contains this bit of the recursive map and 4299190627Sdfr * the offset within that page of the map 4300190627Sdfr * entry 4301190627Sdfr */ 4302190627Sdfr pdir = (PTDPTDI + i) / NPDEPG; 4303190627Sdfr offset = (PTDPTDI + i) % NPDEPG; 4304190627Sdfr pdirma = pmap->pm_pdpt[pdir] & PG_FRAME; 4305190627Sdfr mu[i].ptr = pdirma + offset * sizeof(pd_entry_t); 4306190627Sdfr mu[i].val = (pmap->pm_pdpt[i] & PG_FRAME) | PG_V; 4307190627Sdfr } 4308190627Sdfr HYPERVISOR_mmu_update(mu, 4, NULL, DOMID_SELF); 4309190627Sdfr } 4310190627Sdfr} 4311190627Sdfr 4312181641Skmacy#if defined(PMAP_DEBUG) 4313181641Skmacypmap_pid_dump(int pid) 4314181641Skmacy{ 4315181641Skmacy pmap_t pmap; 4316181641Skmacy struct proc *p; 4317181641Skmacy int npte = 0; 4318181641Skmacy int index; 4319181641Skmacy 4320181641Skmacy sx_slock(&allproc_lock); 4321181641Skmacy FOREACH_PROC_IN_SYSTEM(p) { 4322181641Skmacy if (p->p_pid != pid) 4323181641Skmacy continue; 4324181641Skmacy 4325181641Skmacy if (p->p_vmspace) { 4326181641Skmacy int i,j; 4327181641Skmacy index = 0; 4328181641Skmacy pmap = vmspace_pmap(p->p_vmspace); 4329181641Skmacy for (i = 0; i < NPDEPTD; i++) { 4330181641Skmacy pd_entry_t *pde; 4331181641Skmacy pt_entry_t *pte; 4332181641Skmacy vm_offset_t base = i << PDRSHIFT; 4333181641Skmacy 4334181641Skmacy pde = &pmap->pm_pdir[i]; 4335181641Skmacy if (pde && pmap_pde_v(pde)) { 4336181641Skmacy for (j = 0; j < NPTEPG; j++) { 4337181641Skmacy vm_offset_t va = base + (j << PAGE_SHIFT); 4338181641Skmacy if (va >= (vm_offset_t) VM_MIN_KERNEL_ADDRESS) { 4339181641Skmacy if (index) { 4340181641Skmacy index = 0; 4341181641Skmacy printf("\n"); 4342181641Skmacy } 4343181641Skmacy sx_sunlock(&allproc_lock); 4344230435Salc return (npte); 4345181641Skmacy } 4346181641Skmacy pte = pmap_pte(pmap, va); 4347181641Skmacy if (pte && pmap_pte_v(pte)) { 4348181641Skmacy pt_entry_t pa; 4349181641Skmacy vm_page_t m; 4350181641Skmacy pa = PT_GET(pte); 4351181641Skmacy m = PHYS_TO_VM_PAGE(pa & PG_FRAME); 4352181641Skmacy printf("va: 0x%x, pt: 0x%x, h: %d, w: %d, f: 0x%x", 4353181641Skmacy va, pa, m->hold_count, m->wire_count, m->flags); 4354181641Skmacy npte++; 4355181641Skmacy index++; 4356181641Skmacy if (index >= 2) { 4357181641Skmacy index = 0; 4358181641Skmacy printf("\n"); 4359181641Skmacy } else { 4360181641Skmacy printf(" "); 4361181641Skmacy } 4362181641Skmacy } 4363181641Skmacy } 4364181641Skmacy } 4365181641Skmacy } 4366181641Skmacy } 4367181641Skmacy } 4368181641Skmacy sx_sunlock(&allproc_lock); 4369230435Salc return (npte); 4370181641Skmacy} 4371181641Skmacy#endif 4372181641Skmacy 4373181641Skmacy#if defined(DEBUG) 4374181641Skmacy 4375181641Skmacystatic void pads(pmap_t pm); 4376181641Skmacyvoid pmap_pvdump(vm_paddr_t pa); 4377181641Skmacy 4378181641Skmacy/* print address space of pmap*/ 4379181641Skmacystatic void 4380181641Skmacypads(pmap_t pm) 4381181641Skmacy{ 4382181641Skmacy int i, j; 4383181641Skmacy vm_paddr_t va; 4384181641Skmacy pt_entry_t *ptep; 4385181641Skmacy 4386181641Skmacy if (pm == kernel_pmap) 4387181641Skmacy return; 4388181641Skmacy for (i = 0; i < NPDEPTD; i++) 4389181641Skmacy if (pm->pm_pdir[i]) 4390181641Skmacy for (j = 0; j < NPTEPG; j++) { 4391181641Skmacy va = (i << PDRSHIFT) + (j << PAGE_SHIFT); 4392181641Skmacy if (pm == kernel_pmap && va < KERNBASE) 4393181641Skmacy continue; 4394181641Skmacy if (pm != kernel_pmap && va > UPT_MAX_ADDRESS) 4395181641Skmacy continue; 4396181641Skmacy ptep = pmap_pte(pm, va); 4397181641Skmacy if (pmap_pte_v(ptep)) 4398181641Skmacy printf("%x:%x ", va, *ptep); 4399181641Skmacy }; 4400181641Skmacy 4401181641Skmacy} 4402181641Skmacy 4403181641Skmacyvoid 4404181641Skmacypmap_pvdump(vm_paddr_t pa) 4405181641Skmacy{ 4406181641Skmacy pv_entry_t pv; 4407181641Skmacy pmap_t pmap; 4408181641Skmacy vm_page_t m; 4409181641Skmacy 4410181641Skmacy printf("pa %x", pa); 4411181641Skmacy m = PHYS_TO_VM_PAGE(pa); 4412181641Skmacy TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 4413181641Skmacy pmap = PV_PMAP(pv); 4414181641Skmacy printf(" -> pmap %p, va %x", (void *)pmap, pv->pv_va); 4415181641Skmacy pads(pmap); 4416181641Skmacy } 4417181641Skmacy printf(" "); 4418181641Skmacy} 4419181641Skmacy#endif 4420