pmap.c revision 207410
1/*- 2 * Copyright (c) 1991 Regents of the University of California. 3 * All rights reserved. 4 * Copyright (c) 1994 John S. Dyson 5 * All rights reserved. 6 * Copyright (c) 1994 David Greenman 7 * All rights reserved. 8 * Copyright (c) 2005 Alan L. Cox <alc@cs.rice.edu> 9 * All rights reserved. 10 * 11 * This code is derived from software contributed to Berkeley by 12 * the Systems Programming Group of the University of Utah Computer 13 * Science Department and William Jolitz of UUNET Technologies Inc. 14 * 15 * Redistribution and use in source and binary forms, with or without 16 * modification, are permitted provided that the following conditions 17 * are met: 18 * 1. Redistributions of source code must retain the above copyright 19 * notice, this list of conditions and the following disclaimer. 20 * 2. Redistributions in binary form must reproduce the above copyright 21 * notice, this list of conditions and the following disclaimer in the 22 * documentation and/or other materials provided with the distribution. 23 * 3. All advertising materials mentioning features or use of this software 24 * must display the following acknowledgement: 25 * This product includes software developed by the University of 26 * California, Berkeley and its contributors. 27 * 4. Neither the name of the University nor the names of its contributors 28 * may be used to endorse or promote products derived from this software 29 * without specific prior written permission. 30 * 31 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 32 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 33 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 34 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 35 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 36 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 37 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 38 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 39 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 40 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 41 * SUCH DAMAGE. 42 * 43 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91 44 */ 45/*- 46 * Copyright (c) 2003 Networks Associates Technology, Inc. 47 * All rights reserved. 48 * 49 * This software was developed for the FreeBSD Project by Jake Burkholder, 50 * Safeport Network Services, and Network Associates Laboratories, the 51 * Security Research Division of Network Associates, Inc. under 52 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA 53 * CHATS research program. 54 * 55 * Redistribution and use in source and binary forms, with or without 56 * modification, are permitted provided that the following conditions 57 * are met: 58 * 1. Redistributions of source code must retain the above copyright 59 * notice, this list of conditions and the following disclaimer. 60 * 2. Redistributions in binary form must reproduce the above copyright 61 * notice, this list of conditions and the following disclaimer in the 62 * documentation and/or other materials provided with the distribution. 63 * 64 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 65 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 66 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 67 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 68 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 69 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 70 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 71 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 72 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 73 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 74 * SUCH DAMAGE. 75 */ 76 77#include <sys/cdefs.h> 78__FBSDID("$FreeBSD: head/sys/i386/xen/pmap.c 207410 2010-04-30 00:46:43Z kmacy $"); 79 80/* 81 * Manages physical address maps. 82 * 83 * In addition to hardware address maps, this 84 * module is called upon to provide software-use-only 85 * maps which may or may not be stored in the same 86 * form as hardware maps. These pseudo-maps are 87 * used to store intermediate results from copy 88 * operations to and from address spaces. 89 * 90 * Since the information managed by this module is 91 * also stored by the logical address mapping module, 92 * this module may throw away valid virtual-to-physical 93 * mappings at almost any time. However, invalidations 94 * of virtual-to-physical mappings must be done as 95 * requested. 96 * 97 * In order to cope with hardware architectures which 98 * make virtual-to-physical map invalidates expensive, 99 * this module may delay invalidate or reduced protection 100 * operations until such time as they are actually 101 * necessary. This module is given full information as 102 * to which processors are currently using which maps, 103 * and to when physical maps must be made correct. 104 */ 105 106#define PMAP_DIAGNOSTIC 107 108#include "opt_cpu.h" 109#include "opt_pmap.h" 110#include "opt_msgbuf.h" 111#include "opt_smp.h" 112#include "opt_xbox.h" 113 114#include <sys/param.h> 115#include <sys/systm.h> 116#include <sys/kernel.h> 117#include <sys/ktr.h> 118#include <sys/lock.h> 119#include <sys/malloc.h> 120#include <sys/mman.h> 121#include <sys/msgbuf.h> 122#include <sys/mutex.h> 123#include <sys/proc.h> 124#include <sys/sf_buf.h> 125#include <sys/sx.h> 126#include <sys/vmmeter.h> 127#include <sys/sched.h> 128#include <sys/sysctl.h> 129#ifdef SMP 130#include <sys/smp.h> 131#endif 132 133#include <vm/vm.h> 134#include <vm/vm_param.h> 135#include <vm/vm_kern.h> 136#include <vm/vm_page.h> 137#include <vm/vm_map.h> 138#include <vm/vm_object.h> 139#include <vm/vm_extern.h> 140#include <vm/vm_pageout.h> 141#include <vm/vm_pager.h> 142#include <vm/uma.h> 143 144#include <machine/cpu.h> 145#include <machine/cputypes.h> 146#include <machine/md_var.h> 147#include <machine/pcb.h> 148#include <machine/specialreg.h> 149#ifdef SMP 150#include <machine/smp.h> 151#endif 152 153#ifdef XBOX 154#include <machine/xbox.h> 155#endif 156 157#include <xen/interface/xen.h> 158#include <xen/hypervisor.h> 159#include <machine/xen/hypercall.h> 160#include <machine/xen/xenvar.h> 161#include <machine/xen/xenfunc.h> 162 163#if !defined(CPU_DISABLE_SSE) && defined(I686_CPU) 164#define CPU_ENABLE_SSE 165#endif 166 167#ifndef PMAP_SHPGPERPROC 168#define PMAP_SHPGPERPROC 200 169#endif 170 171#if defined(DIAGNOSTIC) 172#define PMAP_DIAGNOSTIC 173#endif 174 175#if !defined(PMAP_DIAGNOSTIC) 176#ifdef __GNUC_GNU_INLINE__ 177#define PMAP_INLINE inline 178#else 179#define PMAP_INLINE extern inline 180#endif 181#else 182#define PMAP_INLINE 183#endif 184 185#define PV_STATS 186#ifdef PV_STATS 187#define PV_STAT(x) do { x ; } while (0) 188#else 189#define PV_STAT(x) do { } while (0) 190#endif 191 192#define pa_index(pa) ((pa) >> PDRSHIFT) 193#define pa_to_pvh(pa) (&pv_table[pa_index(pa)]) 194 195/* 196 * Get PDEs and PTEs for user/kernel address space 197 */ 198#define pmap_pde(m, v) (&((m)->pm_pdir[(vm_offset_t)(v) >> PDRSHIFT])) 199#define pdir_pde(m, v) (m[(vm_offset_t)(v) >> PDRSHIFT]) 200 201#define pmap_pde_v(pte) ((*(int *)pte & PG_V) != 0) 202#define pmap_pte_w(pte) ((*(int *)pte & PG_W) != 0) 203#define pmap_pte_m(pte) ((*(int *)pte & PG_M) != 0) 204#define pmap_pte_u(pte) ((*(int *)pte & PG_A) != 0) 205#define pmap_pte_v(pte) ((*(int *)pte & PG_V) != 0) 206 207#define pmap_pte_set_prot(pte, v) ((*(int *)pte &= ~PG_PROT), (*(int *)pte |= (v))) 208 209struct pmap kernel_pmap_store; 210LIST_HEAD(pmaplist, pmap); 211static struct pmaplist allpmaps; 212static struct mtx allpmaps_lock; 213 214vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */ 215vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */ 216int pgeflag = 0; /* PG_G or-in */ 217int pseflag = 0; /* PG_PS or-in */ 218 219int nkpt; 220vm_offset_t kernel_vm_end; 221extern u_int32_t KERNend; 222 223#ifdef PAE 224pt_entry_t pg_nx; 225#if !defined(XEN) 226static uma_zone_t pdptzone; 227#endif 228#endif 229 230static int pat_works; /* Is page attribute table sane? */ 231 232/* 233 * Data for the pv entry allocation mechanism 234 */ 235static int pv_entry_count = 0, pv_entry_max = 0, pv_entry_high_water = 0; 236static struct md_page *pv_table; 237static int shpgperproc = PMAP_SHPGPERPROC; 238 239struct pv_chunk *pv_chunkbase; /* KVA block for pv_chunks */ 240int pv_maxchunks; /* How many chunks we have KVA for */ 241vm_offset_t pv_vafree; /* freelist stored in the PTE */ 242 243/* 244 * All those kernel PT submaps that BSD is so fond of 245 */ 246struct sysmaps { 247 struct mtx lock; 248 pt_entry_t *CMAP1; 249 pt_entry_t *CMAP2; 250 caddr_t CADDR1; 251 caddr_t CADDR2; 252}; 253static struct sysmaps sysmaps_pcpu[MAXCPU]; 254static pt_entry_t *CMAP3; 255caddr_t ptvmmap = 0; 256static caddr_t CADDR3; 257struct msgbuf *msgbufp = 0; 258 259/* 260 * Crashdump maps. 261 */ 262static caddr_t crashdumpmap; 263 264static pt_entry_t *PMAP1 = 0, *PMAP2; 265static pt_entry_t *PADDR1 = 0, *PADDR2; 266#ifdef SMP 267static int PMAP1cpu; 268static int PMAP1changedcpu; 269SYSCTL_INT(_debug, OID_AUTO, PMAP1changedcpu, CTLFLAG_RD, 270 &PMAP1changedcpu, 0, 271 "Number of times pmap_pte_quick changed CPU with same PMAP1"); 272#endif 273static int PMAP1changed; 274SYSCTL_INT(_debug, OID_AUTO, PMAP1changed, CTLFLAG_RD, 275 &PMAP1changed, 0, 276 "Number of times pmap_pte_quick changed PMAP1"); 277static int PMAP1unchanged; 278SYSCTL_INT(_debug, OID_AUTO, PMAP1unchanged, CTLFLAG_RD, 279 &PMAP1unchanged, 0, 280 "Number of times pmap_pte_quick didn't change PMAP1"); 281static struct mtx PMAP2mutex; 282 283SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD, 0, "VM/pmap parameters"); 284static int pg_ps_enabled; 285SYSCTL_INT(_vm_pmap, OID_AUTO, pg_ps_enabled, CTLFLAG_RDTUN, &pg_ps_enabled, 0, 286 "Are large page mappings enabled?"); 287 288SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_max, CTLFLAG_RD, &pv_entry_max, 0, 289 "Max number of PV entries"); 290SYSCTL_INT(_vm_pmap, OID_AUTO, shpgperproc, CTLFLAG_RD, &shpgperproc, 0, 291 "Page share factor per proc"); 292 293static void free_pv_entry(pmap_t pmap, pv_entry_t pv); 294static pv_entry_t get_pv_entry(pmap_t locked_pmap, int try); 295 296static vm_page_t pmap_enter_quick_locked(multicall_entry_t **mcl, int *count, pmap_t pmap, vm_offset_t va, 297 vm_page_t m, vm_prot_t prot, vm_page_t mpte); 298static int pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t sva, 299 vm_page_t *free); 300static void pmap_remove_page(struct pmap *pmap, vm_offset_t va, 301 vm_page_t *free); 302static void pmap_remove_entry(struct pmap *pmap, vm_page_t m, 303 vm_offset_t va); 304static void pmap_insert_entry(pmap_t pmap, vm_offset_t va, vm_page_t m); 305static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, 306 vm_page_t m); 307 308static vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va, int flags); 309 310static vm_page_t _pmap_allocpte(pmap_t pmap, unsigned ptepindex, int flags); 311static int _pmap_unwire_pte_hold(pmap_t pmap, vm_page_t m, vm_page_t *free); 312static pt_entry_t *pmap_pte_quick(pmap_t pmap, vm_offset_t va); 313static void pmap_pte_release(pt_entry_t *pte); 314static int pmap_unuse_pt(pmap_t, vm_offset_t, vm_page_t *); 315static vm_offset_t pmap_kmem_choose(vm_offset_t addr); 316static boolean_t pmap_is_prefaultable_locked(pmap_t pmap, vm_offset_t addr); 317static void pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode); 318 319static __inline void pagezero(void *page); 320 321#if defined(PAE) && !defined(XEN) 322static void *pmap_pdpt_allocf(uma_zone_t zone, int bytes, u_int8_t *flags, int wait); 323#endif 324#ifndef XEN 325static void pmap_set_pg(void); 326#endif 327 328CTASSERT(1 << PDESHIFT == sizeof(pd_entry_t)); 329CTASSERT(1 << PTESHIFT == sizeof(pt_entry_t)); 330 331/* 332 * If you get an error here, then you set KVA_PAGES wrong! See the 333 * description of KVA_PAGES in sys/i386/include/pmap.h. It must be 334 * multiple of 4 for a normal kernel, or a multiple of 8 for a PAE. 335 */ 336CTASSERT(KERNBASE % (1 << 24) == 0); 337 338 339 340void 341pd_set(struct pmap *pmap, int ptepindex, vm_paddr_t val, int type) 342{ 343 vm_paddr_t pdir_ma = vtomach(&pmap->pm_pdir[ptepindex]); 344 345 switch (type) { 346 case SH_PD_SET_VA: 347#if 0 348 xen_queue_pt_update(shadow_pdir_ma, 349 xpmap_ptom(val & ~(PG_RW))); 350#endif 351 xen_queue_pt_update(pdir_ma, 352 xpmap_ptom(val)); 353 break; 354 case SH_PD_SET_VA_MA: 355#if 0 356 xen_queue_pt_update(shadow_pdir_ma, 357 val & ~(PG_RW)); 358#endif 359 xen_queue_pt_update(pdir_ma, val); 360 break; 361 case SH_PD_SET_VA_CLEAR: 362#if 0 363 xen_queue_pt_update(shadow_pdir_ma, 0); 364#endif 365 xen_queue_pt_update(pdir_ma, 0); 366 break; 367 } 368} 369 370/* 371 * Move the kernel virtual free pointer to the next 372 * 4MB. This is used to help improve performance 373 * by using a large (4MB) page for much of the kernel 374 * (.text, .data, .bss) 375 */ 376static vm_offset_t 377pmap_kmem_choose(vm_offset_t addr) 378{ 379 vm_offset_t newaddr = addr; 380 381#ifndef DISABLE_PSE 382 if (cpu_feature & CPUID_PSE) 383 newaddr = (addr + PDRMASK) & ~PDRMASK; 384#endif 385 return newaddr; 386} 387 388/* 389 * Bootstrap the system enough to run with virtual memory. 390 * 391 * On the i386 this is called after mapping has already been enabled 392 * and just syncs the pmap module with what has already been done. 393 * [We can't call it easily with mapping off since the kernel is not 394 * mapped with PA == VA, hence we would have to relocate every address 395 * from the linked base (virtual) address "KERNBASE" to the actual 396 * (physical) address starting relative to 0] 397 */ 398void 399pmap_bootstrap(vm_paddr_t firstaddr) 400{ 401 vm_offset_t va; 402 pt_entry_t *pte, *unused; 403 struct sysmaps *sysmaps; 404 int i; 405 406 /* 407 * XXX The calculation of virtual_avail is wrong. It's NKPT*PAGE_SIZE too 408 * large. It should instead be correctly calculated in locore.s and 409 * not based on 'first' (which is a physical address, not a virtual 410 * address, for the start of unused physical memory). The kernel 411 * page tables are NOT double mapped and thus should not be included 412 * in this calculation. 413 */ 414 virtual_avail = (vm_offset_t) KERNBASE + firstaddr; 415 virtual_avail = pmap_kmem_choose(virtual_avail); 416 417 virtual_end = VM_MAX_KERNEL_ADDRESS; 418 419 /* 420 * Initialize the kernel pmap (which is statically allocated). 421 */ 422 PMAP_LOCK_INIT(kernel_pmap); 423 kernel_pmap->pm_pdir = (pd_entry_t *) (KERNBASE + (u_int)IdlePTD); 424#ifdef PAE 425 kernel_pmap->pm_pdpt = (pdpt_entry_t *) (KERNBASE + (u_int)IdlePDPT); 426#endif 427 kernel_pmap->pm_active = -1; /* don't allow deactivation */ 428 TAILQ_INIT(&kernel_pmap->pm_pvchunk); 429 LIST_INIT(&allpmaps); 430 mtx_init(&allpmaps_lock, "allpmaps", NULL, MTX_SPIN); 431 mtx_lock_spin(&allpmaps_lock); 432 LIST_INSERT_HEAD(&allpmaps, kernel_pmap, pm_list); 433 mtx_unlock_spin(&allpmaps_lock); 434 if (nkpt == 0) 435 nkpt = NKPT; 436 437 /* 438 * Reserve some special page table entries/VA space for temporary 439 * mapping of pages. 440 */ 441#define SYSMAP(c, p, v, n) \ 442 v = (c)va; va += ((n)*PAGE_SIZE); p = pte; pte += (n); 443 444 va = virtual_avail; 445 pte = vtopte(va); 446 447 /* 448 * CMAP1/CMAP2 are used for zeroing and copying pages. 449 * CMAP3 is used for the idle process page zeroing. 450 */ 451 for (i = 0; i < MAXCPU; i++) { 452 sysmaps = &sysmaps_pcpu[i]; 453 mtx_init(&sysmaps->lock, "SYSMAPS", NULL, MTX_DEF); 454 SYSMAP(caddr_t, sysmaps->CMAP1, sysmaps->CADDR1, 1) 455 SYSMAP(caddr_t, sysmaps->CMAP2, sysmaps->CADDR2, 1) 456 PT_SET_MA(sysmaps->CADDR1, 0); 457 PT_SET_MA(sysmaps->CADDR2, 0); 458 } 459 SYSMAP(caddr_t, CMAP3, CADDR3, 1) 460 PT_SET_MA(CADDR3, 0); 461 462 /* 463 * Crashdump maps. 464 */ 465 SYSMAP(caddr_t, unused, crashdumpmap, MAXDUMPPGS) 466 467 /* 468 * ptvmmap is used for reading arbitrary physical pages via /dev/mem. 469 */ 470 SYSMAP(caddr_t, unused, ptvmmap, 1) 471 472 /* 473 * msgbufp is used to map the system message buffer. 474 */ 475 SYSMAP(struct msgbuf *, unused, msgbufp, atop(round_page(MSGBUF_SIZE))) 476 477 /* 478 * ptemap is used for pmap_pte_quick 479 */ 480 SYSMAP(pt_entry_t *, PMAP1, PADDR1, 1); 481 SYSMAP(pt_entry_t *, PMAP2, PADDR2, 1); 482 483 mtx_init(&PMAP2mutex, "PMAP2", NULL, MTX_DEF); 484 485 virtual_avail = va; 486 487 /* 488 * Leave in place an identity mapping (virt == phys) for the low 1 MB 489 * physical memory region that is used by the ACPI wakeup code. This 490 * mapping must not have PG_G set. 491 */ 492#ifndef XEN 493 /* 494 * leave here deliberately to show that this is not supported 495 */ 496#ifdef XBOX 497 /* FIXME: This is gross, but needed for the XBOX. Since we are in such 498 * an early stadium, we cannot yet neatly map video memory ... :-( 499 * Better fixes are very welcome! */ 500 if (!arch_i386_is_xbox) 501#endif 502 for (i = 1; i < NKPT; i++) 503 PTD[i] = 0; 504 505 /* Initialize the PAT MSR if present. */ 506 pmap_init_pat(); 507 508 /* Turn on PG_G on kernel page(s) */ 509 pmap_set_pg(); 510#endif 511} 512 513/* 514 * Setup the PAT MSR. 515 */ 516void 517pmap_init_pat(void) 518{ 519 uint64_t pat_msr; 520 521 /* Bail if this CPU doesn't implement PAT. */ 522 if (!(cpu_feature & CPUID_PAT)) 523 return; 524 525 if (cpu_vendor_id != CPU_VENDOR_INTEL || 526 (CPUID_TO_FAMILY(cpu_id) == 6 && CPUID_TO_MODEL(cpu_id) >= 0xe)) { 527 /* 528 * Leave the indices 0-3 at the default of WB, WT, UC, and UC-. 529 * Program 4 and 5 as WP and WC. 530 * Leave 6 and 7 as UC and UC-. 531 */ 532 pat_msr = rdmsr(MSR_PAT); 533 pat_msr &= ~(PAT_MASK(4) | PAT_MASK(5)); 534 pat_msr |= PAT_VALUE(4, PAT_WRITE_PROTECTED) | 535 PAT_VALUE(5, PAT_WRITE_COMBINING); 536 pat_works = 1; 537 } else { 538 /* 539 * Due to some Intel errata, we can only safely use the lower 4 540 * PAT entries. Thus, just replace PAT Index 2 with WC instead 541 * of UC-. 542 * 543 * Intel Pentium III Processor Specification Update 544 * Errata E.27 (Upper Four PAT Entries Not Usable With Mode B 545 * or Mode C Paging) 546 * 547 * Intel Pentium IV Processor Specification Update 548 * Errata N46 (PAT Index MSB May Be Calculated Incorrectly) 549 */ 550 pat_msr = rdmsr(MSR_PAT); 551 pat_msr &= ~PAT_MASK(2); 552 pat_msr |= PAT_VALUE(2, PAT_WRITE_COMBINING); 553 pat_works = 0; 554 } 555 wrmsr(MSR_PAT, pat_msr); 556} 557 558#ifndef XEN 559/* 560 * Set PG_G on kernel pages. Only the BSP calls this when SMP is turned on. 561 */ 562static void 563pmap_set_pg(void) 564{ 565 pd_entry_t pdir; 566 pt_entry_t *pte; 567 vm_offset_t va, endva; 568 int i; 569 570 if (pgeflag == 0) 571 return; 572 573 i = KERNLOAD/NBPDR; 574 endva = KERNBASE + KERNend; 575 576 if (pseflag) { 577 va = KERNBASE + KERNLOAD; 578 while (va < endva) { 579 pdir = kernel_pmap->pm_pdir[KPTDI+i]; 580 pdir |= pgeflag; 581 kernel_pmap->pm_pdir[KPTDI+i] = PTD[KPTDI+i] = pdir; 582 invltlb(); /* Play it safe, invltlb() every time */ 583 i++; 584 va += NBPDR; 585 } 586 } else { 587 va = (vm_offset_t)btext; 588 while (va < endva) { 589 pte = vtopte(va); 590 if (*pte & PG_V) 591 *pte |= pgeflag; 592 invltlb(); /* Play it safe, invltlb() every time */ 593 va += PAGE_SIZE; 594 } 595 } 596} 597#endif 598 599/* 600 * Initialize a vm_page's machine-dependent fields. 601 */ 602void 603pmap_page_init(vm_page_t m) 604{ 605 606 TAILQ_INIT(&m->md.pv_list); 607 m->md.pat_mode = PAT_WRITE_BACK; 608} 609 610#if defined(PAE) && !defined(XEN) 611static void * 612pmap_pdpt_allocf(uma_zone_t zone, int bytes, u_int8_t *flags, int wait) 613{ 614 615 /* Inform UMA that this allocator uses kernel_map/object. */ 616 *flags = UMA_SLAB_KERNEL; 617 return ((void *)kmem_alloc_contig(kernel_map, bytes, wait, 0x0ULL, 618 0xffffffffULL, 1, 0, VM_MEMATTR_DEFAULT)); 619} 620#endif 621 622/* 623 * ABuse the pte nodes for unmapped kva to thread a kva freelist through. 624 * Requirements: 625 * - Must deal with pages in order to ensure that none of the PG_* bits 626 * are ever set, PG_V in particular. 627 * - Assumes we can write to ptes without pte_store() atomic ops, even 628 * on PAE systems. This should be ok. 629 * - Assumes nothing will ever test these addresses for 0 to indicate 630 * no mapping instead of correctly checking PG_V. 631 * - Assumes a vm_offset_t will fit in a pte (true for i386). 632 * Because PG_V is never set, there can be no mappings to invalidate. 633 */ 634static int ptelist_count = 0; 635static vm_offset_t 636pmap_ptelist_alloc(vm_offset_t *head) 637{ 638 vm_offset_t va; 639 vm_offset_t *phead = (vm_offset_t *)*head; 640 641 if (ptelist_count == 0) { 642 printf("out of memory!!!!!!\n"); 643 return (0); /* Out of memory */ 644 } 645 ptelist_count--; 646 va = phead[ptelist_count]; 647 return (va); 648} 649 650static void 651pmap_ptelist_free(vm_offset_t *head, vm_offset_t va) 652{ 653 vm_offset_t *phead = (vm_offset_t *)*head; 654 655 phead[ptelist_count++] = va; 656} 657 658static void 659pmap_ptelist_init(vm_offset_t *head, void *base, int npages) 660{ 661 int i, nstackpages; 662 vm_offset_t va; 663 vm_page_t m; 664 665 nstackpages = (npages + PAGE_SIZE/sizeof(vm_offset_t) - 1)/ (PAGE_SIZE/sizeof(vm_offset_t)); 666 for (i = 0; i < nstackpages; i++) { 667 va = (vm_offset_t)base + i * PAGE_SIZE; 668 m = vm_page_alloc(NULL, i, 669 VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | 670 VM_ALLOC_ZERO); 671 pmap_qenter(va, &m, 1); 672 } 673 674 *head = (vm_offset_t)base; 675 for (i = npages - 1; i >= nstackpages; i--) { 676 va = (vm_offset_t)base + i * PAGE_SIZE; 677 pmap_ptelist_free(head, va); 678 } 679} 680 681 682/* 683 * Initialize the pmap module. 684 * Called by vm_init, to initialize any structures that the pmap 685 * system needs to map virtual memory. 686 */ 687void 688pmap_init(void) 689{ 690 vm_page_t mpte; 691 vm_size_t s; 692 int i, pv_npg; 693 694 /* 695 * Initialize the vm page array entries for the kernel pmap's 696 * page table pages. 697 */ 698 for (i = 0; i < nkpt; i++) { 699 mpte = PHYS_TO_VM_PAGE(xpmap_mtop(PTD[i + KPTDI] & PG_FRAME)); 700 KASSERT(mpte >= vm_page_array && 701 mpte < &vm_page_array[vm_page_array_size], 702 ("pmap_init: page table page is out of range")); 703 mpte->pindex = i + KPTDI; 704 mpte->phys_addr = xpmap_mtop(PTD[i + KPTDI] & PG_FRAME); 705 } 706 707 /* 708 * Initialize the address space (zone) for the pv entries. Set a 709 * high water mark so that the system can recover from excessive 710 * numbers of pv entries. 711 */ 712 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc); 713 pv_entry_max = shpgperproc * maxproc + cnt.v_page_count; 714 TUNABLE_INT_FETCH("vm.pmap.pv_entries", &pv_entry_max); 715 pv_entry_max = roundup(pv_entry_max, _NPCPV); 716 pv_entry_high_water = 9 * (pv_entry_max / 10); 717 718 /* 719 * Are large page mappings enabled? 720 */ 721 TUNABLE_INT_FETCH("vm.pmap.pg_ps_enabled", &pg_ps_enabled); 722 723 /* 724 * Calculate the size of the pv head table for superpages. 725 */ 726 for (i = 0; phys_avail[i + 1]; i += 2); 727 pv_npg = round_4mpage(phys_avail[(i - 2) + 1]) / NBPDR; 728 729 /* 730 * Allocate memory for the pv head table for superpages. 731 */ 732 s = (vm_size_t)(pv_npg * sizeof(struct md_page)); 733 s = round_page(s); 734 pv_table = (struct md_page *)kmem_alloc(kernel_map, s); 735 for (i = 0; i < pv_npg; i++) 736 TAILQ_INIT(&pv_table[i].pv_list); 737 738 pv_maxchunks = MAX(pv_entry_max / _NPCPV, maxproc); 739 pv_chunkbase = (struct pv_chunk *)kmem_alloc_nofault(kernel_map, 740 PAGE_SIZE * pv_maxchunks); 741 if (pv_chunkbase == NULL) 742 panic("pmap_init: not enough kvm for pv chunks"); 743 pmap_ptelist_init(&pv_vafree, pv_chunkbase, pv_maxchunks); 744#if defined(PAE) && !defined(XEN) 745 pdptzone = uma_zcreate("PDPT", NPGPTD * sizeof(pdpt_entry_t), NULL, 746 NULL, NULL, NULL, (NPGPTD * sizeof(pdpt_entry_t)) - 1, 747 UMA_ZONE_VM | UMA_ZONE_NOFREE); 748 uma_zone_set_allocf(pdptzone, pmap_pdpt_allocf); 749#endif 750} 751 752 753/*************************************************** 754 * Low level helper routines..... 755 ***************************************************/ 756 757/* 758 * Determine the appropriate bits to set in a PTE or PDE for a specified 759 * caching mode. 760 */ 761int 762pmap_cache_bits(int mode, boolean_t is_pde) 763{ 764 int pat_flag, pat_index, cache_bits; 765 766 /* The PAT bit is different for PTE's and PDE's. */ 767 pat_flag = is_pde ? PG_PDE_PAT : PG_PTE_PAT; 768 769 /* If we don't support PAT, map extended modes to older ones. */ 770 if (!(cpu_feature & CPUID_PAT)) { 771 switch (mode) { 772 case PAT_UNCACHEABLE: 773 case PAT_WRITE_THROUGH: 774 case PAT_WRITE_BACK: 775 break; 776 case PAT_UNCACHED: 777 case PAT_WRITE_COMBINING: 778 case PAT_WRITE_PROTECTED: 779 mode = PAT_UNCACHEABLE; 780 break; 781 } 782 } 783 784 /* Map the caching mode to a PAT index. */ 785 if (pat_works) { 786 switch (mode) { 787 case PAT_UNCACHEABLE: 788 pat_index = 3; 789 break; 790 case PAT_WRITE_THROUGH: 791 pat_index = 1; 792 break; 793 case PAT_WRITE_BACK: 794 pat_index = 0; 795 break; 796 case PAT_UNCACHED: 797 pat_index = 2; 798 break; 799 case PAT_WRITE_COMBINING: 800 pat_index = 5; 801 break; 802 case PAT_WRITE_PROTECTED: 803 pat_index = 4; 804 break; 805 default: 806 panic("Unknown caching mode %d\n", mode); 807 } 808 } else { 809 switch (mode) { 810 case PAT_UNCACHED: 811 case PAT_UNCACHEABLE: 812 case PAT_WRITE_PROTECTED: 813 pat_index = 3; 814 break; 815 case PAT_WRITE_THROUGH: 816 pat_index = 1; 817 break; 818 case PAT_WRITE_BACK: 819 pat_index = 0; 820 break; 821 case PAT_WRITE_COMBINING: 822 pat_index = 2; 823 break; 824 default: 825 panic("Unknown caching mode %d\n", mode); 826 } 827 } 828 829 /* Map the 3-bit index value into the PAT, PCD, and PWT bits. */ 830 cache_bits = 0; 831 if (pat_index & 0x4) 832 cache_bits |= pat_flag; 833 if (pat_index & 0x2) 834 cache_bits |= PG_NC_PCD; 835 if (pat_index & 0x1) 836 cache_bits |= PG_NC_PWT; 837 return (cache_bits); 838} 839#ifdef SMP 840/* 841 * For SMP, these functions have to use the IPI mechanism for coherence. 842 * 843 * N.B.: Before calling any of the following TLB invalidation functions, 844 * the calling processor must ensure that all stores updating a non- 845 * kernel page table are globally performed. Otherwise, another 846 * processor could cache an old, pre-update entry without being 847 * invalidated. This can happen one of two ways: (1) The pmap becomes 848 * active on another processor after its pm_active field is checked by 849 * one of the following functions but before a store updating the page 850 * table is globally performed. (2) The pmap becomes active on another 851 * processor before its pm_active field is checked but due to 852 * speculative loads one of the following functions stills reads the 853 * pmap as inactive on the other processor. 854 * 855 * The kernel page table is exempt because its pm_active field is 856 * immutable. The kernel page table is always active on every 857 * processor. 858 */ 859void 860pmap_invalidate_page(pmap_t pmap, vm_offset_t va) 861{ 862 u_int cpumask; 863 u_int other_cpus; 864 865 CTR2(KTR_PMAP, "pmap_invalidate_page: pmap=%p va=0x%x", 866 pmap, va); 867 868 sched_pin(); 869 if (pmap == kernel_pmap || pmap->pm_active == all_cpus) { 870 invlpg(va); 871 smp_invlpg(va); 872 } else { 873 cpumask = PCPU_GET(cpumask); 874 other_cpus = PCPU_GET(other_cpus); 875 if (pmap->pm_active & cpumask) 876 invlpg(va); 877 if (pmap->pm_active & other_cpus) 878 smp_masked_invlpg(pmap->pm_active & other_cpus, va); 879 } 880 sched_unpin(); 881 PT_UPDATES_FLUSH(); 882} 883 884void 885pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 886{ 887 u_int cpumask; 888 u_int other_cpus; 889 vm_offset_t addr; 890 891 CTR3(KTR_PMAP, "pmap_invalidate_page: pmap=%p eva=0x%x sva=0x%x", 892 pmap, sva, eva); 893 894 sched_pin(); 895 if (pmap == kernel_pmap || pmap->pm_active == all_cpus) { 896 for (addr = sva; addr < eva; addr += PAGE_SIZE) 897 invlpg(addr); 898 smp_invlpg_range(sva, eva); 899 } else { 900 cpumask = PCPU_GET(cpumask); 901 other_cpus = PCPU_GET(other_cpus); 902 if (pmap->pm_active & cpumask) 903 for (addr = sva; addr < eva; addr += PAGE_SIZE) 904 invlpg(addr); 905 if (pmap->pm_active & other_cpus) 906 smp_masked_invlpg_range(pmap->pm_active & other_cpus, 907 sva, eva); 908 } 909 sched_unpin(); 910 PT_UPDATES_FLUSH(); 911} 912 913void 914pmap_invalidate_all(pmap_t pmap) 915{ 916 u_int cpumask; 917 u_int other_cpus; 918 919 CTR1(KTR_PMAP, "pmap_invalidate_page: pmap=%p", pmap); 920 921 sched_pin(); 922 if (pmap == kernel_pmap || pmap->pm_active == all_cpus) { 923 invltlb(); 924 smp_invltlb(); 925 } else { 926 cpumask = PCPU_GET(cpumask); 927 other_cpus = PCPU_GET(other_cpus); 928 if (pmap->pm_active & cpumask) 929 invltlb(); 930 if (pmap->pm_active & other_cpus) 931 smp_masked_invltlb(pmap->pm_active & other_cpus); 932 } 933 sched_unpin(); 934} 935 936void 937pmap_invalidate_cache(void) 938{ 939 940 sched_pin(); 941 wbinvd(); 942 smp_cache_flush(); 943 sched_unpin(); 944} 945#else /* !SMP */ 946/* 947 * Normal, non-SMP, 486+ invalidation functions. 948 * We inline these within pmap.c for speed. 949 */ 950PMAP_INLINE void 951pmap_invalidate_page(pmap_t pmap, vm_offset_t va) 952{ 953 CTR2(KTR_PMAP, "pmap_invalidate_page: pmap=%p va=0x%x", 954 pmap, va); 955 956 if (pmap == kernel_pmap || pmap->pm_active) 957 invlpg(va); 958 PT_UPDATES_FLUSH(); 959} 960 961PMAP_INLINE void 962pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 963{ 964 vm_offset_t addr; 965 966 if (eva - sva > PAGE_SIZE) 967 CTR3(KTR_PMAP, "pmap_invalidate_range: pmap=%p sva=0x%x eva=0x%x", 968 pmap, sva, eva); 969 970 if (pmap == kernel_pmap || pmap->pm_active) 971 for (addr = sva; addr < eva; addr += PAGE_SIZE) 972 invlpg(addr); 973 PT_UPDATES_FLUSH(); 974} 975 976PMAP_INLINE void 977pmap_invalidate_all(pmap_t pmap) 978{ 979 980 CTR1(KTR_PMAP, "pmap_invalidate_all: pmap=%p", pmap); 981 982 if (pmap == kernel_pmap || pmap->pm_active) 983 invltlb(); 984} 985 986PMAP_INLINE void 987pmap_invalidate_cache(void) 988{ 989 990 wbinvd(); 991} 992#endif /* !SMP */ 993 994void 995pmap_invalidate_cache_range(vm_offset_t sva, vm_offset_t eva) 996{ 997 998 KASSERT((sva & PAGE_MASK) == 0, 999 ("pmap_invalidate_cache_range: sva not page-aligned")); 1000 KASSERT((eva & PAGE_MASK) == 0, 1001 ("pmap_invalidate_cache_range: eva not page-aligned")); 1002 1003 if (cpu_feature & CPUID_SS) 1004 ; /* If "Self Snoop" is supported, do nothing. */ 1005 else if (cpu_feature & CPUID_CLFSH) { 1006 1007 /* 1008 * Otherwise, do per-cache line flush. Use the mfence 1009 * instruction to insure that previous stores are 1010 * included in the write-back. The processor 1011 * propagates flush to other processors in the cache 1012 * coherence domain. 1013 */ 1014 mfence(); 1015 for (; sva < eva; sva += cpu_clflush_line_size) 1016 clflush(sva); 1017 mfence(); 1018 } else { 1019 1020 /* 1021 * No targeted cache flush methods are supported by CPU, 1022 * globally invalidate cache as a last resort. 1023 */ 1024 pmap_invalidate_cache(); 1025 } 1026} 1027 1028/* 1029 * Are we current address space or kernel? N.B. We return FALSE when 1030 * a pmap's page table is in use because a kernel thread is borrowing 1031 * it. The borrowed page table can change spontaneously, making any 1032 * dependence on its continued use subject to a race condition. 1033 */ 1034static __inline int 1035pmap_is_current(pmap_t pmap) 1036{ 1037 1038 return (pmap == kernel_pmap || 1039 (pmap == vmspace_pmap(curthread->td_proc->p_vmspace) && 1040 (pmap->pm_pdir[PTDPTDI] & PG_FRAME) == (PTDpde[0] & PG_FRAME))); 1041} 1042 1043/* 1044 * If the given pmap is not the current or kernel pmap, the returned pte must 1045 * be released by passing it to pmap_pte_release(). 1046 */ 1047pt_entry_t * 1048pmap_pte(pmap_t pmap, vm_offset_t va) 1049{ 1050 pd_entry_t newpf; 1051 pd_entry_t *pde; 1052 1053 pde = pmap_pde(pmap, va); 1054 if (*pde & PG_PS) 1055 return (pde); 1056 if (*pde != 0) { 1057 /* are we current address space or kernel? */ 1058 if (pmap_is_current(pmap)) 1059 return (vtopte(va)); 1060 mtx_lock(&PMAP2mutex); 1061 newpf = *pde & PG_FRAME; 1062 if ((*PMAP2 & PG_FRAME) != newpf) { 1063 vm_page_lock_queues(); 1064 PT_SET_MA(PADDR2, newpf | PG_V | PG_A | PG_M); 1065 vm_page_unlock_queues(); 1066 CTR3(KTR_PMAP, "pmap_pte: pmap=%p va=0x%x newpte=0x%08x", 1067 pmap, va, (*PMAP2 & 0xffffffff)); 1068 } 1069 1070 return (PADDR2 + (i386_btop(va) & (NPTEPG - 1))); 1071 } 1072 return (0); 1073} 1074 1075/* 1076 * Releases a pte that was obtained from pmap_pte(). Be prepared for the pte 1077 * being NULL. 1078 */ 1079static __inline void 1080pmap_pte_release(pt_entry_t *pte) 1081{ 1082 1083 if ((pt_entry_t *)((vm_offset_t)pte & ~PAGE_MASK) == PADDR2) { 1084 CTR1(KTR_PMAP, "pmap_pte_release: pte=0x%jx", 1085 *PMAP2); 1086 PT_SET_VA(PMAP2, 0, TRUE); 1087 mtx_unlock(&PMAP2mutex); 1088 } 1089} 1090 1091static __inline void 1092invlcaddr(void *caddr) 1093{ 1094 1095 invlpg((u_int)caddr); 1096 PT_UPDATES_FLUSH(); 1097} 1098 1099/* 1100 * Super fast pmap_pte routine best used when scanning 1101 * the pv lists. This eliminates many coarse-grained 1102 * invltlb calls. Note that many of the pv list 1103 * scans are across different pmaps. It is very wasteful 1104 * to do an entire invltlb for checking a single mapping. 1105 * 1106 * If the given pmap is not the current pmap, vm_page_queue_mtx 1107 * must be held and curthread pinned to a CPU. 1108 */ 1109static pt_entry_t * 1110pmap_pte_quick(pmap_t pmap, vm_offset_t va) 1111{ 1112 pd_entry_t newpf; 1113 pd_entry_t *pde; 1114 1115 pde = pmap_pde(pmap, va); 1116 if (*pde & PG_PS) 1117 return (pde); 1118 if (*pde != 0) { 1119 /* are we current address space or kernel? */ 1120 if (pmap_is_current(pmap)) 1121 return (vtopte(va)); 1122 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1123 KASSERT(curthread->td_pinned > 0, ("curthread not pinned")); 1124 newpf = *pde & PG_FRAME; 1125 if ((*PMAP1 & PG_FRAME) != newpf) { 1126 PT_SET_MA(PADDR1, newpf | PG_V | PG_A | PG_M); 1127 CTR3(KTR_PMAP, "pmap_pte_quick: pmap=%p va=0x%x newpte=0x%08x", 1128 pmap, va, (u_long)*PMAP1); 1129 1130#ifdef SMP 1131 PMAP1cpu = PCPU_GET(cpuid); 1132#endif 1133 PMAP1changed++; 1134 } else 1135#ifdef SMP 1136 if (PMAP1cpu != PCPU_GET(cpuid)) { 1137 PMAP1cpu = PCPU_GET(cpuid); 1138 invlcaddr(PADDR1); 1139 PMAP1changedcpu++; 1140 } else 1141#endif 1142 PMAP1unchanged++; 1143 return (PADDR1 + (i386_btop(va) & (NPTEPG - 1))); 1144 } 1145 return (0); 1146} 1147 1148/* 1149 * Routine: pmap_extract 1150 * Function: 1151 * Extract the physical page address associated 1152 * with the given map/virtual_address pair. 1153 */ 1154vm_paddr_t 1155pmap_extract(pmap_t pmap, vm_offset_t va) 1156{ 1157 vm_paddr_t rtval; 1158 pt_entry_t *pte; 1159 pd_entry_t pde; 1160 pt_entry_t pteval; 1161 1162 rtval = 0; 1163 PMAP_LOCK(pmap); 1164 pde = pmap->pm_pdir[va >> PDRSHIFT]; 1165 if (pde != 0) { 1166 if ((pde & PG_PS) != 0) { 1167 rtval = xpmap_mtop(pde & PG_PS_FRAME) | (va & PDRMASK); 1168 PMAP_UNLOCK(pmap); 1169 return rtval; 1170 } 1171 pte = pmap_pte(pmap, va); 1172 pteval = *pte ? xpmap_mtop(*pte) : 0; 1173 rtval = (pteval & PG_FRAME) | (va & PAGE_MASK); 1174 pmap_pte_release(pte); 1175 } 1176 PMAP_UNLOCK(pmap); 1177 return (rtval); 1178} 1179 1180/* 1181 * Routine: pmap_extract_ma 1182 * Function: 1183 * Like pmap_extract, but returns machine address 1184 */ 1185vm_paddr_t 1186pmap_extract_ma(pmap_t pmap, vm_offset_t va) 1187{ 1188 vm_paddr_t rtval; 1189 pt_entry_t *pte; 1190 pd_entry_t pde; 1191 1192 rtval = 0; 1193 PMAP_LOCK(pmap); 1194 pde = pmap->pm_pdir[va >> PDRSHIFT]; 1195 if (pde != 0) { 1196 if ((pde & PG_PS) != 0) { 1197 rtval = (pde & ~PDRMASK) | (va & PDRMASK); 1198 PMAP_UNLOCK(pmap); 1199 return rtval; 1200 } 1201 pte = pmap_pte(pmap, va); 1202 rtval = (*pte & PG_FRAME) | (va & PAGE_MASK); 1203 pmap_pte_release(pte); 1204 } 1205 PMAP_UNLOCK(pmap); 1206 return (rtval); 1207} 1208 1209/* 1210 * Routine: pmap_extract_and_hold 1211 * Function: 1212 * Atomically extract and hold the physical page 1213 * with the given pmap and virtual address pair 1214 * if that mapping permits the given protection. 1215 */ 1216vm_page_t 1217pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot) 1218{ 1219 pd_entry_t pde; 1220 pt_entry_t pte; 1221 vm_page_t m; 1222 vm_paddr_t pa; 1223 1224 pa = 0; 1225 m = NULL; 1226 PMAP_LOCK(pmap); 1227retry: 1228 pde = PT_GET(pmap_pde(pmap, va)); 1229 if (pde != 0) { 1230 if (pde & PG_PS) { 1231 if ((pde & PG_RW) || (prot & VM_PROT_WRITE) == 0) { 1232 if (vm_page_pa_tryrelock(pmap, (pde & PG_PS_FRAME) | 1233 (va & PDRMASK), &pa)) 1234 goto retry; 1235 m = PHYS_TO_VM_PAGE((pde & PG_PS_FRAME) | 1236 (va & PDRMASK)); 1237 vm_page_hold(m); 1238 } 1239 } else { 1240 sched_pin(); 1241 pte = PT_GET(pmap_pte_quick(pmap, va)); 1242 if (*PMAP1) 1243 PT_SET_MA(PADDR1, 0); 1244 if ((pte & PG_V) && 1245 ((pte & PG_RW) || (prot & VM_PROT_WRITE) == 0)) { 1246 if (vm_page_pa_tryrelock(pmap, pte & PG_FRAME, &pa)) 1247 goto retry; 1248 m = PHYS_TO_VM_PAGE(pte & PG_FRAME); 1249 vm_page_hold(m); 1250 } 1251 sched_unpin(); 1252 } 1253 } 1254 PA_UNLOCK_COND(pa); 1255 PMAP_UNLOCK(pmap); 1256 return (m); 1257} 1258 1259/*************************************************** 1260 * Low level mapping routines..... 1261 ***************************************************/ 1262 1263/* 1264 * Add a wired page to the kva. 1265 * Note: not SMP coherent. 1266 */ 1267void 1268pmap_kenter(vm_offset_t va, vm_paddr_t pa) 1269{ 1270 PT_SET_MA(va, xpmap_ptom(pa)| PG_RW | PG_V | pgeflag); 1271} 1272 1273void 1274pmap_kenter_ma(vm_offset_t va, vm_paddr_t ma) 1275{ 1276 pt_entry_t *pte; 1277 1278 pte = vtopte(va); 1279 pte_store_ma(pte, ma | PG_RW | PG_V | pgeflag); 1280} 1281 1282 1283static __inline void 1284pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode) 1285{ 1286 PT_SET_MA(va, pa | PG_RW | PG_V | pgeflag | pmap_cache_bits(mode, 0)); 1287} 1288 1289/* 1290 * Remove a page from the kernel pagetables. 1291 * Note: not SMP coherent. 1292 */ 1293PMAP_INLINE void 1294pmap_kremove(vm_offset_t va) 1295{ 1296 pt_entry_t *pte; 1297 1298 pte = vtopte(va); 1299 PT_CLEAR_VA(pte, FALSE); 1300} 1301 1302/* 1303 * Used to map a range of physical addresses into kernel 1304 * virtual address space. 1305 * 1306 * The value passed in '*virt' is a suggested virtual address for 1307 * the mapping. Architectures which can support a direct-mapped 1308 * physical to virtual region can return the appropriate address 1309 * within that region, leaving '*virt' unchanged. Other 1310 * architectures should map the pages starting at '*virt' and 1311 * update '*virt' with the first usable address after the mapped 1312 * region. 1313 */ 1314vm_offset_t 1315pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot) 1316{ 1317 vm_offset_t va, sva; 1318 1319 va = sva = *virt; 1320 CTR4(KTR_PMAP, "pmap_map: va=0x%x start=0x%jx end=0x%jx prot=0x%x", 1321 va, start, end, prot); 1322 while (start < end) { 1323 pmap_kenter(va, start); 1324 va += PAGE_SIZE; 1325 start += PAGE_SIZE; 1326 } 1327 pmap_invalidate_range(kernel_pmap, sva, va); 1328 *virt = va; 1329 return (sva); 1330} 1331 1332 1333/* 1334 * Add a list of wired pages to the kva 1335 * this routine is only used for temporary 1336 * kernel mappings that do not need to have 1337 * page modification or references recorded. 1338 * Note that old mappings are simply written 1339 * over. The page *must* be wired. 1340 * Note: SMP coherent. Uses a ranged shootdown IPI. 1341 */ 1342void 1343pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count) 1344{ 1345 pt_entry_t *endpte, *pte; 1346 vm_paddr_t pa; 1347 vm_offset_t va = sva; 1348 int mclcount = 0; 1349 multicall_entry_t mcl[16]; 1350 multicall_entry_t *mclp = mcl; 1351 int error; 1352 1353 CTR2(KTR_PMAP, "pmap_qenter:sva=0x%x count=%d", va, count); 1354 pte = vtopte(sva); 1355 endpte = pte + count; 1356 while (pte < endpte) { 1357 pa = xpmap_ptom(VM_PAGE_TO_PHYS(*ma)) | pgeflag | PG_RW | PG_V | PG_M | PG_A; 1358 1359 mclp->op = __HYPERVISOR_update_va_mapping; 1360 mclp->args[0] = va; 1361 mclp->args[1] = (uint32_t)(pa & 0xffffffff); 1362 mclp->args[2] = (uint32_t)(pa >> 32); 1363 mclp->args[3] = (*pte & PG_V) ? UVMF_INVLPG|UVMF_ALL : 0; 1364 1365 va += PAGE_SIZE; 1366 pte++; 1367 ma++; 1368 mclp++; 1369 mclcount++; 1370 if (mclcount == 16) { 1371 error = HYPERVISOR_multicall(mcl, mclcount); 1372 mclp = mcl; 1373 mclcount = 0; 1374 KASSERT(error == 0, ("bad multicall %d", error)); 1375 } 1376 } 1377 if (mclcount) { 1378 error = HYPERVISOR_multicall(mcl, mclcount); 1379 KASSERT(error == 0, ("bad multicall %d", error)); 1380 } 1381 1382#ifdef INVARIANTS 1383 for (pte = vtopte(sva), mclcount = 0; mclcount < count; mclcount++, pte++) 1384 KASSERT(*pte, ("pte not set for va=0x%x", sva + mclcount*PAGE_SIZE)); 1385#endif 1386} 1387 1388 1389/* 1390 * This routine tears out page mappings from the 1391 * kernel -- it is meant only for temporary mappings. 1392 * Note: SMP coherent. Uses a ranged shootdown IPI. 1393 */ 1394void 1395pmap_qremove(vm_offset_t sva, int count) 1396{ 1397 vm_offset_t va; 1398 1399 CTR2(KTR_PMAP, "pmap_qremove: sva=0x%x count=%d", sva, count); 1400 va = sva; 1401 vm_page_lock_queues(); 1402 critical_enter(); 1403 while (count-- > 0) { 1404 pmap_kremove(va); 1405 va += PAGE_SIZE; 1406 } 1407 pmap_invalidate_range(kernel_pmap, sva, va); 1408 critical_exit(); 1409 vm_page_unlock_queues(); 1410} 1411 1412/*************************************************** 1413 * Page table page management routines..... 1414 ***************************************************/ 1415static __inline void 1416pmap_free_zero_pages(vm_page_t free) 1417{ 1418 vm_page_t m; 1419 1420 while (free != NULL) { 1421 m = free; 1422 free = m->right; 1423 vm_page_free_zero(m); 1424 } 1425} 1426 1427/* 1428 * This routine unholds page table pages, and if the hold count 1429 * drops to zero, then it decrements the wire count. 1430 */ 1431static __inline int 1432pmap_unwire_pte_hold(pmap_t pmap, vm_page_t m, vm_page_t *free) 1433{ 1434 1435 --m->wire_count; 1436 if (m->wire_count == 0) 1437 return _pmap_unwire_pte_hold(pmap, m, free); 1438 else 1439 return 0; 1440} 1441 1442static int 1443_pmap_unwire_pte_hold(pmap_t pmap, vm_page_t m, vm_page_t *free) 1444{ 1445 vm_offset_t pteva; 1446 1447 PT_UPDATES_FLUSH(); 1448 /* 1449 * unmap the page table page 1450 */ 1451 xen_pt_unpin(pmap->pm_pdir[m->pindex]); 1452 /* 1453 * page *might* contain residual mapping :-/ 1454 */ 1455 PD_CLEAR_VA(pmap, m->pindex, TRUE); 1456 pmap_zero_page(m); 1457 --pmap->pm_stats.resident_count; 1458 1459 /* 1460 * This is a release store so that the ordinary store unmapping 1461 * the page table page is globally performed before TLB shoot- 1462 * down is begun. 1463 */ 1464 atomic_subtract_rel_int(&cnt.v_wire_count, 1); 1465 1466 /* 1467 * Do an invltlb to make the invalidated mapping 1468 * take effect immediately. 1469 */ 1470 pteva = VM_MAXUSER_ADDRESS + i386_ptob(m->pindex); 1471 pmap_invalidate_page(pmap, pteva); 1472 1473 /* 1474 * Put page on a list so that it is released after 1475 * *ALL* TLB shootdown is done 1476 */ 1477 m->right = *free; 1478 *free = m; 1479 1480 return 1; 1481} 1482 1483/* 1484 * After removing a page table entry, this routine is used to 1485 * conditionally free the page, and manage the hold/wire counts. 1486 */ 1487static int 1488pmap_unuse_pt(pmap_t pmap, vm_offset_t va, vm_page_t *free) 1489{ 1490 pd_entry_t ptepde; 1491 vm_page_t mpte; 1492 1493 if (va >= VM_MAXUSER_ADDRESS) 1494 return 0; 1495 ptepde = PT_GET(pmap_pde(pmap, va)); 1496 mpte = PHYS_TO_VM_PAGE(ptepde & PG_FRAME); 1497 return pmap_unwire_pte_hold(pmap, mpte, free); 1498} 1499 1500void 1501pmap_pinit0(pmap_t pmap) 1502{ 1503 1504 PMAP_LOCK_INIT(pmap); 1505 pmap->pm_pdir = (pd_entry_t *)(KERNBASE + (vm_offset_t)IdlePTD); 1506#ifdef PAE 1507 pmap->pm_pdpt = (pdpt_entry_t *)(KERNBASE + (vm_offset_t)IdlePDPT); 1508#endif 1509 pmap->pm_active = 0; 1510 PCPU_SET(curpmap, pmap); 1511 TAILQ_INIT(&pmap->pm_pvchunk); 1512 bzero(&pmap->pm_stats, sizeof pmap->pm_stats); 1513 mtx_lock_spin(&allpmaps_lock); 1514 LIST_INSERT_HEAD(&allpmaps, pmap, pm_list); 1515 mtx_unlock_spin(&allpmaps_lock); 1516} 1517 1518/* 1519 * Initialize a preallocated and zeroed pmap structure, 1520 * such as one in a vmspace structure. 1521 */ 1522int 1523pmap_pinit(pmap_t pmap) 1524{ 1525 vm_page_t m, ptdpg[NPGPTD + 1]; 1526 int npgptd = NPGPTD + 1; 1527 static int color; 1528 int i; 1529 1530 PMAP_LOCK_INIT(pmap); 1531 1532 /* 1533 * No need to allocate page table space yet but we do need a valid 1534 * page directory table. 1535 */ 1536 if (pmap->pm_pdir == NULL) { 1537 pmap->pm_pdir = (pd_entry_t *)kmem_alloc_nofault(kernel_map, 1538 NBPTD); 1539 if (pmap->pm_pdir == NULL) { 1540 PMAP_LOCK_DESTROY(pmap); 1541 return (0); 1542 } 1543#if defined(XEN) && defined(PAE) 1544 pmap->pm_pdpt = (pd_entry_t *)kmem_alloc_nofault(kernel_map, 1); 1545#endif 1546 1547#if defined(PAE) && !defined(XEN) 1548 pmap->pm_pdpt = uma_zalloc(pdptzone, M_WAITOK | M_ZERO); 1549 KASSERT(((vm_offset_t)pmap->pm_pdpt & 1550 ((NPGPTD * sizeof(pdpt_entry_t)) - 1)) == 0, 1551 ("pmap_pinit: pdpt misaligned")); 1552 KASSERT(pmap_kextract((vm_offset_t)pmap->pm_pdpt) < (4ULL<<30), 1553 ("pmap_pinit: pdpt above 4g")); 1554#endif 1555 } 1556 1557 /* 1558 * allocate the page directory page(s) 1559 */ 1560 for (i = 0; i < npgptd;) { 1561 m = vm_page_alloc(NULL, color++, 1562 VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | 1563 VM_ALLOC_ZERO); 1564 if (m == NULL) 1565 VM_WAIT; 1566 else { 1567 ptdpg[i++] = m; 1568 } 1569 } 1570 pmap_qenter((vm_offset_t)pmap->pm_pdir, ptdpg, NPGPTD); 1571 for (i = 0; i < NPGPTD; i++) { 1572 if ((ptdpg[i]->flags & PG_ZERO) == 0) 1573 pagezero(&pmap->pm_pdir[i*NPTEPG]); 1574 } 1575 1576 mtx_lock_spin(&allpmaps_lock); 1577 LIST_INSERT_HEAD(&allpmaps, pmap, pm_list); 1578 mtx_unlock_spin(&allpmaps_lock); 1579 /* Wire in kernel global address entries. */ 1580 1581 bcopy(PTD + KPTDI, pmap->pm_pdir + KPTDI, nkpt * sizeof(pd_entry_t)); 1582#ifdef PAE 1583#ifdef XEN 1584 pmap_qenter((vm_offset_t)pmap->pm_pdpt, &ptdpg[NPGPTD], 1); 1585 if ((ptdpg[NPGPTD]->flags & PG_ZERO) == 0) 1586 bzero(pmap->pm_pdpt, PAGE_SIZE); 1587#endif 1588 for (i = 0; i < NPGPTD; i++) { 1589 vm_paddr_t ma; 1590 1591 ma = xpmap_ptom(VM_PAGE_TO_PHYS(ptdpg[i])); 1592 pmap->pm_pdpt[i] = ma | PG_V; 1593 1594 } 1595#endif 1596#ifdef XEN 1597 for (i = 0; i < NPGPTD; i++) { 1598 pt_entry_t *pd; 1599 vm_paddr_t ma; 1600 1601 ma = xpmap_ptom(VM_PAGE_TO_PHYS(ptdpg[i])); 1602 pd = pmap->pm_pdir + (i * NPDEPG); 1603 PT_SET_MA(pd, *vtopte((vm_offset_t)pd) & ~(PG_M|PG_A|PG_U|PG_RW)); 1604#if 0 1605 xen_pgd_pin(ma); 1606#endif 1607 } 1608 1609#ifdef PAE 1610 PT_SET_MA(pmap->pm_pdpt, *vtopte((vm_offset_t)pmap->pm_pdpt) & ~PG_RW); 1611#endif 1612 vm_page_lock_queues(); 1613 xen_flush_queue(); 1614 xen_pgdpt_pin(xpmap_ptom(VM_PAGE_TO_PHYS(ptdpg[NPGPTD]))); 1615 for (i = 0; i < NPGPTD; i++) { 1616 vm_paddr_t ma = xpmap_ptom(VM_PAGE_TO_PHYS(ptdpg[i])); 1617 PT_SET_VA_MA(&pmap->pm_pdir[PTDPTDI + i], ma | PG_V | PG_A, FALSE); 1618 } 1619 xen_flush_queue(); 1620 vm_page_unlock_queues(); 1621#endif 1622 pmap->pm_active = 0; 1623 TAILQ_INIT(&pmap->pm_pvchunk); 1624 bzero(&pmap->pm_stats, sizeof pmap->pm_stats); 1625 1626 return (1); 1627} 1628 1629/* 1630 * this routine is called if the page table page is not 1631 * mapped correctly. 1632 */ 1633static vm_page_t 1634_pmap_allocpte(pmap_t pmap, unsigned int ptepindex, int flags) 1635{ 1636 vm_paddr_t ptema; 1637 vm_page_t m; 1638 1639 KASSERT((flags & (M_NOWAIT | M_WAITOK)) == M_NOWAIT || 1640 (flags & (M_NOWAIT | M_WAITOK)) == M_WAITOK, 1641 ("_pmap_allocpte: flags is neither M_NOWAIT nor M_WAITOK")); 1642 1643 /* 1644 * Allocate a page table page. 1645 */ 1646 if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ | 1647 VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) { 1648 if (flags & M_WAITOK) { 1649 PMAP_UNLOCK(pmap); 1650 vm_page_unlock_queues(); 1651 VM_WAIT; 1652 vm_page_lock_queues(); 1653 PMAP_LOCK(pmap); 1654 } 1655 1656 /* 1657 * Indicate the need to retry. While waiting, the page table 1658 * page may have been allocated. 1659 */ 1660 return (NULL); 1661 } 1662 if ((m->flags & PG_ZERO) == 0) 1663 pmap_zero_page(m); 1664 1665 /* 1666 * Map the pagetable page into the process address space, if 1667 * it isn't already there. 1668 */ 1669 pmap->pm_stats.resident_count++; 1670 1671 ptema = xpmap_ptom(VM_PAGE_TO_PHYS(m)); 1672 xen_pt_pin(ptema); 1673 PT_SET_VA_MA(&pmap->pm_pdir[ptepindex], 1674 (ptema | PG_U | PG_RW | PG_V | PG_A | PG_M), TRUE); 1675 1676 KASSERT(pmap->pm_pdir[ptepindex], 1677 ("_pmap_allocpte: ptepindex=%d did not get mapped", ptepindex)); 1678 return (m); 1679} 1680 1681static vm_page_t 1682pmap_allocpte(pmap_t pmap, vm_offset_t va, int flags) 1683{ 1684 unsigned ptepindex; 1685 pd_entry_t ptema; 1686 vm_page_t m; 1687 1688 KASSERT((flags & (M_NOWAIT | M_WAITOK)) == M_NOWAIT || 1689 (flags & (M_NOWAIT | M_WAITOK)) == M_WAITOK, 1690 ("pmap_allocpte: flags is neither M_NOWAIT nor M_WAITOK")); 1691 1692 /* 1693 * Calculate pagetable page index 1694 */ 1695 ptepindex = va >> PDRSHIFT; 1696retry: 1697 /* 1698 * Get the page directory entry 1699 */ 1700 ptema = pmap->pm_pdir[ptepindex]; 1701 1702 /* 1703 * This supports switching from a 4MB page to a 1704 * normal 4K page. 1705 */ 1706 if (ptema & PG_PS) { 1707 /* 1708 * XXX 1709 */ 1710 pmap->pm_pdir[ptepindex] = 0; 1711 ptema = 0; 1712 pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE; 1713 pmap_invalidate_all(kernel_pmap); 1714 } 1715 1716 /* 1717 * If the page table page is mapped, we just increment the 1718 * hold count, and activate it. 1719 */ 1720 if (ptema & PG_V) { 1721 m = PHYS_TO_VM_PAGE(xpmap_mtop(ptema) & PG_FRAME); 1722 m->wire_count++; 1723 } else { 1724 /* 1725 * Here if the pte page isn't mapped, or if it has 1726 * been deallocated. 1727 */ 1728 CTR3(KTR_PMAP, "pmap_allocpte: pmap=%p va=0x%08x flags=0x%x", 1729 pmap, va, flags); 1730 m = _pmap_allocpte(pmap, ptepindex, flags); 1731 if (m == NULL && (flags & M_WAITOK)) 1732 goto retry; 1733 1734 KASSERT(pmap->pm_pdir[ptepindex], ("ptepindex=%d did not get mapped", ptepindex)); 1735 } 1736 return (m); 1737} 1738 1739 1740/*************************************************** 1741* Pmap allocation/deallocation routines. 1742 ***************************************************/ 1743 1744#ifdef SMP 1745/* 1746 * Deal with a SMP shootdown of other users of the pmap that we are 1747 * trying to dispose of. This can be a bit hairy. 1748 */ 1749static cpumask_t *lazymask; 1750static u_int lazyptd; 1751static volatile u_int lazywait; 1752 1753void pmap_lazyfix_action(void); 1754 1755void 1756pmap_lazyfix_action(void) 1757{ 1758 cpumask_t mymask = PCPU_GET(cpumask); 1759 1760#ifdef COUNT_IPIS 1761 (*ipi_lazypmap_counts[PCPU_GET(cpuid)])++; 1762#endif 1763 if (rcr3() == lazyptd) 1764 load_cr3(PCPU_GET(curpcb)->pcb_cr3); 1765 atomic_clear_int(lazymask, mymask); 1766 atomic_store_rel_int(&lazywait, 1); 1767} 1768 1769static void 1770pmap_lazyfix_self(cpumask_t mymask) 1771{ 1772 1773 if (rcr3() == lazyptd) 1774 load_cr3(PCPU_GET(curpcb)->pcb_cr3); 1775 atomic_clear_int(lazymask, mymask); 1776} 1777 1778 1779static void 1780pmap_lazyfix(pmap_t pmap) 1781{ 1782 cpumask_t mymask, mask; 1783 u_int spins; 1784 1785 while ((mask = pmap->pm_active) != 0) { 1786 spins = 50000000; 1787 mask = mask & -mask; /* Find least significant set bit */ 1788 mtx_lock_spin(&smp_ipi_mtx); 1789#ifdef PAE 1790 lazyptd = vtophys(pmap->pm_pdpt); 1791#else 1792 lazyptd = vtophys(pmap->pm_pdir); 1793#endif 1794 mymask = PCPU_GET(cpumask); 1795 if (mask == mymask) { 1796 lazymask = &pmap->pm_active; 1797 pmap_lazyfix_self(mymask); 1798 } else { 1799 atomic_store_rel_int((u_int *)&lazymask, 1800 (u_int)&pmap->pm_active); 1801 atomic_store_rel_int(&lazywait, 0); 1802 ipi_selected(mask, IPI_LAZYPMAP); 1803 while (lazywait == 0) { 1804 ia32_pause(); 1805 if (--spins == 0) 1806 break; 1807 } 1808 } 1809 mtx_unlock_spin(&smp_ipi_mtx); 1810 if (spins == 0) 1811 printf("pmap_lazyfix: spun for 50000000\n"); 1812 } 1813} 1814 1815#else /* SMP */ 1816 1817/* 1818 * Cleaning up on uniprocessor is easy. For various reasons, we're 1819 * unlikely to have to even execute this code, including the fact 1820 * that the cleanup is deferred until the parent does a wait(2), which 1821 * means that another userland process has run. 1822 */ 1823static void 1824pmap_lazyfix(pmap_t pmap) 1825{ 1826 u_int cr3; 1827 1828 cr3 = vtophys(pmap->pm_pdir); 1829 if (cr3 == rcr3()) { 1830 load_cr3(PCPU_GET(curpcb)->pcb_cr3); 1831 pmap->pm_active &= ~(PCPU_GET(cpumask)); 1832 } 1833} 1834#endif /* SMP */ 1835 1836/* 1837 * Release any resources held by the given physical map. 1838 * Called when a pmap initialized by pmap_pinit is being released. 1839 * Should only be called if the map contains no valid mappings. 1840 */ 1841void 1842pmap_release(pmap_t pmap) 1843{ 1844 vm_page_t m, ptdpg[2*NPGPTD+1]; 1845 vm_paddr_t ma; 1846 int i; 1847#ifdef XEN 1848#ifdef PAE 1849 int npgptd = NPGPTD + 1; 1850#else 1851 int npgptd = NPGPTD; 1852#endif 1853#else 1854 int npgptd = NPGPTD; 1855#endif 1856 KASSERT(pmap->pm_stats.resident_count == 0, 1857 ("pmap_release: pmap resident count %ld != 0", 1858 pmap->pm_stats.resident_count)); 1859 PT_UPDATES_FLUSH(); 1860 1861 pmap_lazyfix(pmap); 1862 mtx_lock_spin(&allpmaps_lock); 1863 LIST_REMOVE(pmap, pm_list); 1864 mtx_unlock_spin(&allpmaps_lock); 1865 1866 for (i = 0; i < NPGPTD; i++) 1867 ptdpg[i] = PHYS_TO_VM_PAGE(vtophys(pmap->pm_pdir + (i*NPDEPG)) & PG_FRAME); 1868 pmap_qremove((vm_offset_t)pmap->pm_pdir, NPGPTD); 1869#if defined(PAE) && defined(XEN) 1870 ptdpg[NPGPTD] = PHYS_TO_VM_PAGE(vtophys(pmap->pm_pdpt)); 1871#endif 1872 1873 for (i = 0; i < npgptd; i++) { 1874 m = ptdpg[i]; 1875 ma = xpmap_ptom(VM_PAGE_TO_PHYS(m)); 1876 /* unpinning L1 and L2 treated the same */ 1877 xen_pgd_unpin(ma); 1878#ifdef PAE 1879 KASSERT(xpmap_ptom(VM_PAGE_TO_PHYS(m)) == (pmap->pm_pdpt[i] & PG_FRAME), 1880 ("pmap_release: got wrong ptd page")); 1881#endif 1882 m->wire_count--; 1883 atomic_subtract_int(&cnt.v_wire_count, 1); 1884 vm_page_free(m); 1885 } 1886 PMAP_LOCK_DESTROY(pmap); 1887} 1888 1889static int 1890kvm_size(SYSCTL_HANDLER_ARGS) 1891{ 1892 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - KERNBASE; 1893 1894 return sysctl_handle_long(oidp, &ksize, 0, req); 1895} 1896SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG|CTLFLAG_RD, 1897 0, 0, kvm_size, "IU", "Size of KVM"); 1898 1899static int 1900kvm_free(SYSCTL_HANDLER_ARGS) 1901{ 1902 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end; 1903 1904 return sysctl_handle_long(oidp, &kfree, 0, req); 1905} 1906SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG|CTLFLAG_RD, 1907 0, 0, kvm_free, "IU", "Amount of KVM free"); 1908 1909/* 1910 * grow the number of kernel page table entries, if needed 1911 */ 1912void 1913pmap_growkernel(vm_offset_t addr) 1914{ 1915 struct pmap *pmap; 1916 vm_paddr_t ptppaddr; 1917 vm_page_t nkpg; 1918 pd_entry_t newpdir; 1919 1920 mtx_assert(&kernel_map->system_mtx, MA_OWNED); 1921 if (kernel_vm_end == 0) { 1922 kernel_vm_end = KERNBASE; 1923 nkpt = 0; 1924 while (pdir_pde(PTD, kernel_vm_end)) { 1925 kernel_vm_end = (kernel_vm_end + PAGE_SIZE * NPTEPG) & ~(PAGE_SIZE * NPTEPG - 1); 1926 nkpt++; 1927 if (kernel_vm_end - 1 >= kernel_map->max_offset) { 1928 kernel_vm_end = kernel_map->max_offset; 1929 break; 1930 } 1931 } 1932 } 1933 addr = roundup2(addr, PAGE_SIZE * NPTEPG); 1934 if (addr - 1 >= kernel_map->max_offset) 1935 addr = kernel_map->max_offset; 1936 while (kernel_vm_end < addr) { 1937 if (pdir_pde(PTD, kernel_vm_end)) { 1938 kernel_vm_end = (kernel_vm_end + PAGE_SIZE * NPTEPG) & ~(PAGE_SIZE * NPTEPG - 1); 1939 if (kernel_vm_end - 1 >= kernel_map->max_offset) { 1940 kernel_vm_end = kernel_map->max_offset; 1941 break; 1942 } 1943 continue; 1944 } 1945 1946 /* 1947 * This index is bogus, but out of the way 1948 */ 1949 nkpg = vm_page_alloc(NULL, nkpt, 1950 VM_ALLOC_NOOBJ | VM_ALLOC_SYSTEM | VM_ALLOC_WIRED); 1951 if (!nkpg) 1952 panic("pmap_growkernel: no memory to grow kernel"); 1953 1954 nkpt++; 1955 1956 pmap_zero_page(nkpg); 1957 ptppaddr = VM_PAGE_TO_PHYS(nkpg); 1958 newpdir = (pd_entry_t) (ptppaddr | PG_V | PG_RW | PG_A | PG_M); 1959 vm_page_lock_queues(); 1960 PD_SET_VA(kernel_pmap, (kernel_vm_end >> PDRSHIFT), newpdir, TRUE); 1961 mtx_lock_spin(&allpmaps_lock); 1962 LIST_FOREACH(pmap, &allpmaps, pm_list) 1963 PD_SET_VA(pmap, (kernel_vm_end >> PDRSHIFT), newpdir, TRUE); 1964 1965 mtx_unlock_spin(&allpmaps_lock); 1966 vm_page_unlock_queues(); 1967 1968 kernel_vm_end = (kernel_vm_end + PAGE_SIZE * NPTEPG) & ~(PAGE_SIZE * NPTEPG - 1); 1969 if (kernel_vm_end - 1 >= kernel_map->max_offset) { 1970 kernel_vm_end = kernel_map->max_offset; 1971 break; 1972 } 1973 } 1974} 1975 1976 1977/*************************************************** 1978 * page management routines. 1979 ***************************************************/ 1980 1981CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE); 1982CTASSERT(_NPCM == 11); 1983 1984static __inline struct pv_chunk * 1985pv_to_chunk(pv_entry_t pv) 1986{ 1987 1988 return (struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK); 1989} 1990 1991#define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap) 1992 1993#define PC_FREE0_9 0xfffffffful /* Free values for index 0 through 9 */ 1994#define PC_FREE10 0x0000fffful /* Free values for index 10 */ 1995 1996static uint32_t pc_freemask[11] = { 1997 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9, 1998 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9, 1999 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9, 2000 PC_FREE0_9, PC_FREE10 2001}; 2002 2003SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0, 2004 "Current number of pv entries"); 2005 2006#ifdef PV_STATS 2007static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail; 2008 2009SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0, 2010 "Current number of pv entry chunks"); 2011SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0, 2012 "Current number of pv entry chunks allocated"); 2013SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0, 2014 "Current number of pv entry chunks frees"); 2015SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0, 2016 "Number of times tried to get a chunk page but failed."); 2017 2018static long pv_entry_frees, pv_entry_allocs; 2019static int pv_entry_spare; 2020 2021SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0, 2022 "Current number of pv entry frees"); 2023SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0, 2024 "Current number of pv entry allocs"); 2025SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0, 2026 "Current number of spare pv entries"); 2027 2028static int pmap_collect_inactive, pmap_collect_active; 2029 2030SYSCTL_INT(_vm_pmap, OID_AUTO, pmap_collect_inactive, CTLFLAG_RD, &pmap_collect_inactive, 0, 2031 "Current number times pmap_collect called on inactive queue"); 2032SYSCTL_INT(_vm_pmap, OID_AUTO, pmap_collect_active, CTLFLAG_RD, &pmap_collect_active, 0, 2033 "Current number times pmap_collect called on active queue"); 2034#endif 2035 2036/* 2037 * We are in a serious low memory condition. Resort to 2038 * drastic measures to free some pages so we can allocate 2039 * another pv entry chunk. This is normally called to 2040 * unmap inactive pages, and if necessary, active pages. 2041 */ 2042static void 2043pmap_collect(pmap_t locked_pmap, struct vpgqueues *vpq) 2044{ 2045 pmap_t pmap; 2046 pt_entry_t *pte, tpte; 2047 pv_entry_t next_pv, pv; 2048 vm_offset_t va; 2049 vm_page_t m, free; 2050 2051 sched_pin(); 2052 TAILQ_FOREACH(m, &vpq->pl, pageq) { 2053 if (m->hold_count || m->busy) 2054 continue; 2055 TAILQ_FOREACH_SAFE(pv, &m->md.pv_list, pv_list, next_pv) { 2056 va = pv->pv_va; 2057 pmap = PV_PMAP(pv); 2058 /* Avoid deadlock and lock recursion. */ 2059 if (pmap > locked_pmap) 2060 PMAP_LOCK(pmap); 2061 else if (pmap != locked_pmap && !PMAP_TRYLOCK(pmap)) 2062 continue; 2063 pmap->pm_stats.resident_count--; 2064 pte = pmap_pte_quick(pmap, va); 2065 tpte = pte_load_clear(pte); 2066 KASSERT((tpte & PG_W) == 0, 2067 ("pmap_collect: wired pte %#jx", (uintmax_t)tpte)); 2068 if (tpte & PG_A) 2069 vm_page_flag_set(m, PG_REFERENCED); 2070 if (tpte & PG_M) { 2071 KASSERT((tpte & PG_RW), 2072 ("pmap_collect: modified page not writable: va: %#x, pte: %#jx", 2073 va, (uintmax_t)tpte)); 2074 vm_page_dirty(m); 2075 } 2076 free = NULL; 2077 pmap_unuse_pt(pmap, va, &free); 2078 pmap_invalidate_page(pmap, va); 2079 pmap_free_zero_pages(free); 2080 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list); 2081 if (TAILQ_EMPTY(&m->md.pv_list)) 2082 vm_page_flag_clear(m, PG_WRITEABLE); 2083 free_pv_entry(pmap, pv); 2084 if (pmap != locked_pmap) 2085 PMAP_UNLOCK(pmap); 2086 } 2087 } 2088 sched_unpin(); 2089} 2090 2091 2092/* 2093 * free the pv_entry back to the free list 2094 */ 2095static void 2096free_pv_entry(pmap_t pmap, pv_entry_t pv) 2097{ 2098 vm_page_t m; 2099 struct pv_chunk *pc; 2100 int idx, field, bit; 2101 2102 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2103 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2104 PV_STAT(pv_entry_frees++); 2105 PV_STAT(pv_entry_spare++); 2106 pv_entry_count--; 2107 pc = pv_to_chunk(pv); 2108 idx = pv - &pc->pc_pventry[0]; 2109 field = idx / 32; 2110 bit = idx % 32; 2111 pc->pc_map[field] |= 1ul << bit; 2112 /* move to head of list */ 2113 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 2114 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list); 2115 for (idx = 0; idx < _NPCM; idx++) 2116 if (pc->pc_map[idx] != pc_freemask[idx]) 2117 return; 2118 PV_STAT(pv_entry_spare -= _NPCPV); 2119 PV_STAT(pc_chunk_count--); 2120 PV_STAT(pc_chunk_frees++); 2121 /* entire chunk is free, return it */ 2122 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 2123 m = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc)); 2124 pmap_qremove((vm_offset_t)pc, 1); 2125 vm_page_unwire(m, 0); 2126 vm_page_free(m); 2127 pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc); 2128} 2129 2130/* 2131 * get a new pv_entry, allocating a block from the system 2132 * when needed. 2133 */ 2134static pv_entry_t 2135get_pv_entry(pmap_t pmap, int try) 2136{ 2137 static const struct timeval printinterval = { 60, 0 }; 2138 static struct timeval lastprint; 2139 static vm_pindex_t colour; 2140 struct vpgqueues *pq; 2141 int bit, field; 2142 pv_entry_t pv; 2143 struct pv_chunk *pc; 2144 vm_page_t m; 2145 2146 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2147 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2148 PV_STAT(pv_entry_allocs++); 2149 pv_entry_count++; 2150 if (pv_entry_count > pv_entry_high_water) 2151 if (ratecheck(&lastprint, &printinterval)) 2152 printf("Approaching the limit on PV entries, consider " 2153 "increasing either the vm.pmap.shpgperproc or the " 2154 "vm.pmap.pv_entry_max tunable.\n"); 2155 pq = NULL; 2156retry: 2157 pc = TAILQ_FIRST(&pmap->pm_pvchunk); 2158 if (pc != NULL) { 2159 for (field = 0; field < _NPCM; field++) { 2160 if (pc->pc_map[field]) { 2161 bit = bsfl(pc->pc_map[field]); 2162 break; 2163 } 2164 } 2165 if (field < _NPCM) { 2166 pv = &pc->pc_pventry[field * 32 + bit]; 2167 pc->pc_map[field] &= ~(1ul << bit); 2168 /* If this was the last item, move it to tail */ 2169 for (field = 0; field < _NPCM; field++) 2170 if (pc->pc_map[field] != 0) { 2171 PV_STAT(pv_entry_spare--); 2172 return (pv); /* not full, return */ 2173 } 2174 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 2175 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list); 2176 PV_STAT(pv_entry_spare--); 2177 return (pv); 2178 } 2179 } 2180 /* 2181 * Access to the ptelist "pv_vafree" is synchronized by the page 2182 * queues lock. If "pv_vafree" is currently non-empty, it will 2183 * remain non-empty until pmap_ptelist_alloc() completes. 2184 */ 2185 if (pv_vafree == 0 || (m = vm_page_alloc(NULL, colour, (pq == 2186 &vm_page_queues[PQ_ACTIVE] ? VM_ALLOC_SYSTEM : VM_ALLOC_NORMAL) | 2187 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) { 2188 if (try) { 2189 pv_entry_count--; 2190 PV_STAT(pc_chunk_tryfail++); 2191 return (NULL); 2192 } 2193 /* 2194 * Reclaim pv entries: At first, destroy mappings to 2195 * inactive pages. After that, if a pv chunk entry 2196 * is still needed, destroy mappings to active pages. 2197 */ 2198 if (pq == NULL) { 2199 PV_STAT(pmap_collect_inactive++); 2200 pq = &vm_page_queues[PQ_INACTIVE]; 2201 } else if (pq == &vm_page_queues[PQ_INACTIVE]) { 2202 PV_STAT(pmap_collect_active++); 2203 pq = &vm_page_queues[PQ_ACTIVE]; 2204 } else 2205 panic("get_pv_entry: increase vm.pmap.shpgperproc"); 2206 pmap_collect(pmap, pq); 2207 goto retry; 2208 } 2209 PV_STAT(pc_chunk_count++); 2210 PV_STAT(pc_chunk_allocs++); 2211 colour++; 2212 pc = (struct pv_chunk *)pmap_ptelist_alloc(&pv_vafree); 2213 pmap_qenter((vm_offset_t)pc, &m, 1); 2214 if ((m->flags & PG_ZERO) == 0) 2215 pagezero(pc); 2216 pc->pc_pmap = pmap; 2217 pc->pc_map[0] = pc_freemask[0] & ~1ul; /* preallocated bit 0 */ 2218 for (field = 1; field < _NPCM; field++) 2219 pc->pc_map[field] = pc_freemask[field]; 2220 pv = &pc->pc_pventry[0]; 2221 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list); 2222 PV_STAT(pv_entry_spare += _NPCPV - 1); 2223 return (pv); 2224} 2225 2226static void 2227pmap_remove_entry(pmap_t pmap, vm_page_t m, vm_offset_t va) 2228{ 2229 pv_entry_t pv; 2230 2231 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2232 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2233 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 2234 if (pmap == PV_PMAP(pv) && va == pv->pv_va) 2235 break; 2236 } 2237 KASSERT(pv != NULL, ("pmap_remove_entry: pv not found")); 2238 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list); 2239 if (TAILQ_EMPTY(&m->md.pv_list)) 2240 vm_page_flag_clear(m, PG_WRITEABLE); 2241 free_pv_entry(pmap, pv); 2242} 2243 2244/* 2245 * Create a pv entry for page at pa for 2246 * (pmap, va). 2247 */ 2248static void 2249pmap_insert_entry(pmap_t pmap, vm_offset_t va, vm_page_t m) 2250{ 2251 pv_entry_t pv; 2252 2253 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2254 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2255 pv = get_pv_entry(pmap, FALSE); 2256 pv->pv_va = va; 2257 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list); 2258} 2259 2260/* 2261 * Conditionally create a pv entry. 2262 */ 2263static boolean_t 2264pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m) 2265{ 2266 pv_entry_t pv; 2267 2268 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2269 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2270 if (pv_entry_count < pv_entry_high_water && 2271 (pv = get_pv_entry(pmap, TRUE)) != NULL) { 2272 pv->pv_va = va; 2273 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list); 2274 return (TRUE); 2275 } else 2276 return (FALSE); 2277} 2278 2279/* 2280 * pmap_remove_pte: do the things to unmap a page in a process 2281 */ 2282static int 2283pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t va, vm_page_t *free) 2284{ 2285 pt_entry_t oldpte; 2286 vm_page_t m; 2287 2288 CTR3(KTR_PMAP, "pmap_remove_pte: pmap=%p *ptq=0x%x va=0x%x", 2289 pmap, (u_long)*ptq, va); 2290 2291 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2292 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2293 oldpte = *ptq; 2294 PT_SET_VA_MA(ptq, 0, TRUE); 2295 if (oldpte & PG_W) 2296 pmap->pm_stats.wired_count -= 1; 2297 /* 2298 * Machines that don't support invlpg, also don't support 2299 * PG_G. 2300 */ 2301 if (oldpte & PG_G) 2302 pmap_invalidate_page(kernel_pmap, va); 2303 pmap->pm_stats.resident_count -= 1; 2304 /* 2305 * XXX This is not strictly correctly, but somewhere along the line 2306 * we are losing the managed bit on some pages. It is unclear to me 2307 * why, but I think the most likely explanation is that xen's writable 2308 * page table implementation doesn't respect the unused bits. 2309 */ 2310 if ((oldpte & PG_MANAGED) || ((oldpte & PG_V) && (va < VM_MAXUSER_ADDRESS)) 2311 ) { 2312 m = PHYS_TO_VM_PAGE(xpmap_mtop(oldpte) & PG_FRAME); 2313 2314 if (!(oldpte & PG_MANAGED)) 2315 printf("va=0x%x is unmanaged :-( pte=0x%llx\n", va, oldpte); 2316 2317 if (oldpte & PG_M) { 2318 KASSERT((oldpte & PG_RW), 2319 ("pmap_remove_pte: modified page not writable: va: %#x, pte: %#jx", 2320 va, (uintmax_t)oldpte)); 2321 vm_page_dirty(m); 2322 } 2323 if (oldpte & PG_A) 2324 vm_page_flag_set(m, PG_REFERENCED); 2325 pmap_remove_entry(pmap, m, va); 2326 } else if ((va < VM_MAXUSER_ADDRESS) && (oldpte & PG_V)) 2327 printf("va=0x%x is unmanaged :-( pte=0x%llx\n", va, oldpte); 2328 2329 return (pmap_unuse_pt(pmap, va, free)); 2330} 2331 2332/* 2333 * Remove a single page from a process address space 2334 */ 2335static void 2336pmap_remove_page(pmap_t pmap, vm_offset_t va, vm_page_t *free) 2337{ 2338 pt_entry_t *pte; 2339 2340 CTR2(KTR_PMAP, "pmap_remove_page: pmap=%p va=0x%x", 2341 pmap, va); 2342 2343 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2344 KASSERT(curthread->td_pinned > 0, ("curthread not pinned")); 2345 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2346 if ((pte = pmap_pte_quick(pmap, va)) == NULL || (*pte & PG_V) == 0) 2347 return; 2348 pmap_remove_pte(pmap, pte, va, free); 2349 pmap_invalidate_page(pmap, va); 2350 if (*PMAP1) 2351 PT_SET_MA(PADDR1, 0); 2352 2353} 2354 2355/* 2356 * Remove the given range of addresses from the specified map. 2357 * 2358 * It is assumed that the start and end are properly 2359 * rounded to the page size. 2360 */ 2361void 2362pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 2363{ 2364 vm_offset_t pdnxt; 2365 pd_entry_t ptpaddr; 2366 pt_entry_t *pte; 2367 vm_page_t free = NULL; 2368 int anyvalid; 2369 2370 CTR3(KTR_PMAP, "pmap_remove: pmap=%p sva=0x%x eva=0x%x", 2371 pmap, sva, eva); 2372 2373 /* 2374 * Perform an unsynchronized read. This is, however, safe. 2375 */ 2376 if (pmap->pm_stats.resident_count == 0) 2377 return; 2378 2379 anyvalid = 0; 2380 2381 vm_page_lock_queues(); 2382 sched_pin(); 2383 PMAP_LOCK(pmap); 2384 2385 /* 2386 * special handling of removing one page. a very 2387 * common operation and easy to short circuit some 2388 * code. 2389 */ 2390 if ((sva + PAGE_SIZE == eva) && 2391 ((pmap->pm_pdir[(sva >> PDRSHIFT)] & PG_PS) == 0)) { 2392 pmap_remove_page(pmap, sva, &free); 2393 goto out; 2394 } 2395 2396 for (; sva < eva; sva = pdnxt) { 2397 unsigned pdirindex; 2398 2399 /* 2400 * Calculate index for next page table. 2401 */ 2402 pdnxt = (sva + NBPDR) & ~PDRMASK; 2403 if (pmap->pm_stats.resident_count == 0) 2404 break; 2405 2406 pdirindex = sva >> PDRSHIFT; 2407 ptpaddr = pmap->pm_pdir[pdirindex]; 2408 2409 /* 2410 * Weed out invalid mappings. Note: we assume that the page 2411 * directory table is always allocated, and in kernel virtual. 2412 */ 2413 if (ptpaddr == 0) 2414 continue; 2415 2416 /* 2417 * Check for large page. 2418 */ 2419 if ((ptpaddr & PG_PS) != 0) { 2420 PD_CLEAR_VA(pmap, pdirindex, TRUE); 2421 pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE; 2422 anyvalid = 1; 2423 continue; 2424 } 2425 2426 /* 2427 * Limit our scan to either the end of the va represented 2428 * by the current page table page, or to the end of the 2429 * range being removed. 2430 */ 2431 if (pdnxt > eva) 2432 pdnxt = eva; 2433 2434 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++, 2435 sva += PAGE_SIZE) { 2436 if ((*pte & PG_V) == 0) 2437 continue; 2438 2439 /* 2440 * The TLB entry for a PG_G mapping is invalidated 2441 * by pmap_remove_pte(). 2442 */ 2443 if ((*pte & PG_G) == 0) 2444 anyvalid = 1; 2445 if (pmap_remove_pte(pmap, pte, sva, &free)) 2446 break; 2447 } 2448 } 2449 PT_UPDATES_FLUSH(); 2450 if (*PMAP1) 2451 PT_SET_VA_MA(PMAP1, 0, TRUE); 2452out: 2453 if (anyvalid) 2454 pmap_invalidate_all(pmap); 2455 sched_unpin(); 2456 vm_page_unlock_queues(); 2457 PMAP_UNLOCK(pmap); 2458 pmap_free_zero_pages(free); 2459} 2460 2461/* 2462 * Routine: pmap_remove_all 2463 * Function: 2464 * Removes this physical page from 2465 * all physical maps in which it resides. 2466 * Reflects back modify bits to the pager. 2467 * 2468 * Notes: 2469 * Original versions of this routine were very 2470 * inefficient because they iteratively called 2471 * pmap_remove (slow...) 2472 */ 2473 2474void 2475pmap_remove_all(vm_page_t m) 2476{ 2477 pv_entry_t pv; 2478 pmap_t pmap; 2479 pt_entry_t *pte, tpte; 2480 vm_page_t free; 2481 2482#if defined(PMAP_DIAGNOSTIC) 2483 /* 2484 * XXX This makes pmap_remove_all() illegal for non-managed pages! 2485 */ 2486 if (m->flags & PG_FICTITIOUS) { 2487 panic("pmap_remove_all: illegal for unmanaged page, va: 0x%jx", 2488 VM_PAGE_TO_PHYS(m) & 0xffffffff); 2489 } 2490#endif 2491 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2492 sched_pin(); 2493 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) { 2494 pmap = PV_PMAP(pv); 2495 PMAP_LOCK(pmap); 2496 pmap->pm_stats.resident_count--; 2497 pte = pmap_pte_quick(pmap, pv->pv_va); 2498 2499 tpte = *pte; 2500 PT_SET_VA_MA(pte, 0, TRUE); 2501 if (tpte & PG_W) 2502 pmap->pm_stats.wired_count--; 2503 if (tpte & PG_A) 2504 vm_page_flag_set(m, PG_REFERENCED); 2505 2506 /* 2507 * Update the vm_page_t clean and reference bits. 2508 */ 2509 if (tpte & PG_M) { 2510 KASSERT((tpte & PG_RW), 2511 ("pmap_remove_all: modified page not writable: va: %#x, pte: %#jx", 2512 pv->pv_va, (uintmax_t)tpte)); 2513 vm_page_dirty(m); 2514 } 2515 free = NULL; 2516 pmap_unuse_pt(pmap, pv->pv_va, &free); 2517 pmap_invalidate_page(pmap, pv->pv_va); 2518 pmap_free_zero_pages(free); 2519 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list); 2520 free_pv_entry(pmap, pv); 2521 PMAP_UNLOCK(pmap); 2522 } 2523 vm_page_flag_clear(m, PG_WRITEABLE); 2524 PT_UPDATES_FLUSH(); 2525 if (*PMAP1) 2526 PT_SET_MA(PADDR1, 0); 2527 sched_unpin(); 2528} 2529 2530/* 2531 * Set the physical protection on the 2532 * specified range of this map as requested. 2533 */ 2534void 2535pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot) 2536{ 2537 vm_offset_t pdnxt; 2538 pd_entry_t ptpaddr; 2539 pt_entry_t *pte; 2540 int anychanged; 2541 2542 CTR4(KTR_PMAP, "pmap_protect: pmap=%p sva=0x%x eva=0x%x prot=0x%x", 2543 pmap, sva, eva, prot); 2544 2545 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 2546 pmap_remove(pmap, sva, eva); 2547 return; 2548 } 2549 2550#ifdef PAE 2551 if ((prot & (VM_PROT_WRITE|VM_PROT_EXECUTE)) == 2552 (VM_PROT_WRITE|VM_PROT_EXECUTE)) 2553 return; 2554#else 2555 if (prot & VM_PROT_WRITE) 2556 return; 2557#endif 2558 2559 anychanged = 0; 2560 2561 vm_page_lock_queues(); 2562 sched_pin(); 2563 PMAP_LOCK(pmap); 2564 for (; sva < eva; sva = pdnxt) { 2565 pt_entry_t obits, pbits; 2566 unsigned pdirindex; 2567 2568 pdnxt = (sva + NBPDR) & ~PDRMASK; 2569 2570 pdirindex = sva >> PDRSHIFT; 2571 ptpaddr = pmap->pm_pdir[pdirindex]; 2572 2573 /* 2574 * Weed out invalid mappings. Note: we assume that the page 2575 * directory table is always allocated, and in kernel virtual. 2576 */ 2577 if (ptpaddr == 0) 2578 continue; 2579 2580 /* 2581 * Check for large page. 2582 */ 2583 if ((ptpaddr & PG_PS) != 0) { 2584 if ((prot & VM_PROT_WRITE) == 0) 2585 pmap->pm_pdir[pdirindex] &= ~(PG_M|PG_RW); 2586#ifdef PAE 2587 if ((prot & VM_PROT_EXECUTE) == 0) 2588 pmap->pm_pdir[pdirindex] |= pg_nx; 2589#endif 2590 anychanged = 1; 2591 continue; 2592 } 2593 2594 if (pdnxt > eva) 2595 pdnxt = eva; 2596 2597 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++, 2598 sva += PAGE_SIZE) { 2599 vm_page_t m; 2600 2601retry: 2602 /* 2603 * Regardless of whether a pte is 32 or 64 bits in 2604 * size, PG_RW, PG_A, and PG_M are among the least 2605 * significant 32 bits. 2606 */ 2607 obits = pbits = *pte; 2608 if ((pbits & PG_V) == 0) 2609 continue; 2610 2611 if ((prot & VM_PROT_WRITE) == 0) { 2612 if ((pbits & (PG_MANAGED | PG_M | PG_RW)) == 2613 (PG_MANAGED | PG_M | PG_RW)) { 2614 m = PHYS_TO_VM_PAGE(xpmap_mtop(pbits) & 2615 PG_FRAME); 2616 vm_page_dirty(m); 2617 } 2618 pbits &= ~(PG_RW | PG_M); 2619 } 2620#ifdef PAE 2621 if ((prot & VM_PROT_EXECUTE) == 0) 2622 pbits |= pg_nx; 2623#endif 2624 2625 if (pbits != obits) { 2626#ifdef XEN 2627 obits = *pte; 2628 PT_SET_VA_MA(pte, pbits, TRUE); 2629 if (*pte != pbits) 2630 goto retry; 2631#else 2632#ifdef PAE 2633 if (!atomic_cmpset_64(pte, obits, pbits)) 2634 goto retry; 2635#else 2636 if (!atomic_cmpset_int((u_int *)pte, obits, 2637 pbits)) 2638 goto retry; 2639#endif 2640#endif 2641 if (obits & PG_G) 2642 pmap_invalidate_page(pmap, sva); 2643 else 2644 anychanged = 1; 2645 } 2646 } 2647 } 2648 PT_UPDATES_FLUSH(); 2649 if (*PMAP1) 2650 PT_SET_VA_MA(PMAP1, 0, TRUE); 2651 if (anychanged) 2652 pmap_invalidate_all(pmap); 2653 sched_unpin(); 2654 vm_page_unlock_queues(); 2655 PMAP_UNLOCK(pmap); 2656} 2657 2658/* 2659 * Insert the given physical page (p) at 2660 * the specified virtual address (v) in the 2661 * target physical map with the protection requested. 2662 * 2663 * If specified, the page will be wired down, meaning 2664 * that the related pte can not be reclaimed. 2665 * 2666 * NB: This is the only routine which MAY NOT lazy-evaluate 2667 * or lose information. That is, this routine must actually 2668 * insert this page into the given map NOW. 2669 */ 2670void 2671pmap_enter(pmap_t pmap, vm_offset_t va, vm_prot_t access, vm_page_t m, 2672 vm_prot_t prot, boolean_t wired) 2673{ 2674 vm_paddr_t pa; 2675 pd_entry_t *pde; 2676 pt_entry_t *pte; 2677 vm_paddr_t opa; 2678 pt_entry_t origpte, newpte; 2679 vm_page_t mpte, om; 2680 boolean_t invlva; 2681 2682 CTR6(KTR_PMAP, "pmap_enter: pmap=%08p va=0x%08x access=0x%x ma=0x%08x prot=0x%x wired=%d", 2683 pmap, va, access, xpmap_ptom(VM_PAGE_TO_PHYS(m)), prot, wired); 2684 va = trunc_page(va); 2685#ifdef PMAP_DIAGNOSTIC 2686 if (va > VM_MAX_KERNEL_ADDRESS) 2687 panic("pmap_enter: toobig"); 2688 if ((va >= UPT_MIN_ADDRESS) && (va < UPT_MAX_ADDRESS)) 2689 panic("pmap_enter: invalid to pmap_enter page table pages (va: 0x%x)", va); 2690#endif 2691 2692 mpte = NULL; 2693 2694 vm_page_lock_queues(); 2695 PMAP_LOCK(pmap); 2696 sched_pin(); 2697 2698 /* 2699 * In the case that a page table page is not 2700 * resident, we are creating it here. 2701 */ 2702 if (va < VM_MAXUSER_ADDRESS) { 2703 mpte = pmap_allocpte(pmap, va, M_WAITOK); 2704 } 2705#if 0 && defined(PMAP_DIAGNOSTIC) 2706 else { 2707 pd_entry_t *pdeaddr = pmap_pde(pmap, va); 2708 origpte = *pdeaddr; 2709 if ((origpte & PG_V) == 0) { 2710 panic("pmap_enter: invalid kernel page table page, pdir=%p, pde=%p, va=%p\n", 2711 pmap->pm_pdir[PTDPTDI], origpte, va); 2712 } 2713 } 2714#endif 2715 2716 pde = pmap_pde(pmap, va); 2717 if ((*pde & PG_PS) != 0) 2718 panic("pmap_enter: attempted pmap_enter on 4MB page"); 2719 pte = pmap_pte_quick(pmap, va); 2720 2721 /* 2722 * Page Directory table entry not valid, we need a new PT page 2723 */ 2724 if (pte == NULL) { 2725 panic("pmap_enter: invalid page directory pdir=%#jx, va=%#x\n", 2726 (uintmax_t)pmap->pm_pdir[va >> PDRSHIFT], va); 2727 } 2728 2729 pa = VM_PAGE_TO_PHYS(m); 2730 om = NULL; 2731 opa = origpte = 0; 2732 2733#if 0 2734 KASSERT((*pte & PG_V) || (*pte == 0), ("address set but not valid pte=%p *pte=0x%016jx", 2735 pte, *pte)); 2736#endif 2737 origpte = *pte; 2738 if (origpte) 2739 origpte = xpmap_mtop(origpte); 2740 opa = origpte & PG_FRAME; 2741 2742 /* 2743 * Mapping has not changed, must be protection or wiring change. 2744 */ 2745 if (origpte && (opa == pa)) { 2746 /* 2747 * Wiring change, just update stats. We don't worry about 2748 * wiring PT pages as they remain resident as long as there 2749 * are valid mappings in them. Hence, if a user page is wired, 2750 * the PT page will be also. 2751 */ 2752 if (wired && ((origpte & PG_W) == 0)) 2753 pmap->pm_stats.wired_count++; 2754 else if (!wired && (origpte & PG_W)) 2755 pmap->pm_stats.wired_count--; 2756 2757 /* 2758 * Remove extra pte reference 2759 */ 2760 if (mpte) 2761 mpte->wire_count--; 2762 2763 /* 2764 * We might be turning off write access to the page, 2765 * so we go ahead and sense modify status. 2766 */ 2767 if (origpte & PG_MANAGED) { 2768 om = m; 2769 pa |= PG_MANAGED; 2770 } 2771 goto validate; 2772 } 2773 /* 2774 * Mapping has changed, invalidate old range and fall through to 2775 * handle validating new mapping. 2776 */ 2777 if (opa) { 2778 if (origpte & PG_W) 2779 pmap->pm_stats.wired_count--; 2780 if (origpte & PG_MANAGED) { 2781 om = PHYS_TO_VM_PAGE(opa); 2782 pmap_remove_entry(pmap, om, va); 2783 } else if (va < VM_MAXUSER_ADDRESS) 2784 printf("va=0x%x is unmanaged :-( \n", va); 2785 2786 if (mpte != NULL) { 2787 mpte->wire_count--; 2788 KASSERT(mpte->wire_count > 0, 2789 ("pmap_enter: missing reference to page table page," 2790 " va: 0x%x", va)); 2791 } 2792 } else 2793 pmap->pm_stats.resident_count++; 2794 2795 /* 2796 * Enter on the PV list if part of our managed memory. 2797 */ 2798 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0) { 2799 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva, 2800 ("pmap_enter: managed mapping within the clean submap")); 2801 pmap_insert_entry(pmap, va, m); 2802 pa |= PG_MANAGED; 2803 } 2804 2805 /* 2806 * Increment counters 2807 */ 2808 if (wired) 2809 pmap->pm_stats.wired_count++; 2810 2811validate: 2812 /* 2813 * Now validate mapping with desired protection/wiring. 2814 */ 2815 newpte = (pt_entry_t)(pa | PG_V); 2816 if ((prot & VM_PROT_WRITE) != 0) { 2817 newpte |= PG_RW; 2818 vm_page_flag_set(m, PG_WRITEABLE); 2819 } 2820#ifdef PAE 2821 if ((prot & VM_PROT_EXECUTE) == 0) 2822 newpte |= pg_nx; 2823#endif 2824 if (wired) 2825 newpte |= PG_W; 2826 if (va < VM_MAXUSER_ADDRESS) 2827 newpte |= PG_U; 2828 if (pmap == kernel_pmap) 2829 newpte |= pgeflag; 2830 2831 critical_enter(); 2832 /* 2833 * if the mapping or permission bits are different, we need 2834 * to update the pte. 2835 */ 2836 if ((origpte & ~(PG_M|PG_A)) != newpte) { 2837 if (origpte) { 2838 invlva = FALSE; 2839 origpte = *pte; 2840 PT_SET_VA(pte, newpte | PG_A, FALSE); 2841 if (origpte & PG_A) { 2842 if (origpte & PG_MANAGED) 2843 vm_page_flag_set(om, PG_REFERENCED); 2844 if (opa != VM_PAGE_TO_PHYS(m)) 2845 invlva = TRUE; 2846#ifdef PAE 2847 if ((origpte & PG_NX) == 0 && 2848 (newpte & PG_NX) != 0) 2849 invlva = TRUE; 2850#endif 2851 } 2852 if (origpte & PG_M) { 2853 KASSERT((origpte & PG_RW), 2854 ("pmap_enter: modified page not writable: va: %#x, pte: %#jx", 2855 va, (uintmax_t)origpte)); 2856 if ((origpte & PG_MANAGED) != 0) 2857 vm_page_dirty(om); 2858 if ((prot & VM_PROT_WRITE) == 0) 2859 invlva = TRUE; 2860 } 2861 if (invlva) 2862 pmap_invalidate_page(pmap, va); 2863 } else{ 2864 PT_SET_VA(pte, newpte | PG_A, FALSE); 2865 } 2866 2867 } 2868 PT_UPDATES_FLUSH(); 2869 critical_exit(); 2870 if (*PMAP1) 2871 PT_SET_VA_MA(PMAP1, 0, TRUE); 2872 sched_unpin(); 2873 vm_page_unlock_queues(); 2874 PMAP_UNLOCK(pmap); 2875} 2876 2877/* 2878 * Maps a sequence of resident pages belonging to the same object. 2879 * The sequence begins with the given page m_start. This page is 2880 * mapped at the given virtual address start. Each subsequent page is 2881 * mapped at a virtual address that is offset from start by the same 2882 * amount as the page is offset from m_start within the object. The 2883 * last page in the sequence is the page with the largest offset from 2884 * m_start that can be mapped at a virtual address less than the given 2885 * virtual address end. Not every virtual page between start and end 2886 * is mapped; only those for which a resident page exists with the 2887 * corresponding offset from m_start are mapped. 2888 */ 2889void 2890pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end, 2891 vm_page_t m_start, vm_prot_t prot) 2892{ 2893 vm_page_t m, mpte; 2894 vm_pindex_t diff, psize; 2895 multicall_entry_t mcl[16]; 2896 multicall_entry_t *mclp = mcl; 2897 int error, count = 0; 2898 2899 VM_OBJECT_LOCK_ASSERT(m_start->object, MA_OWNED); 2900 psize = atop(end - start); 2901 2902 mpte = NULL; 2903 m = m_start; 2904 PMAP_LOCK(pmap); 2905 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 2906 mpte = pmap_enter_quick_locked(&mclp, &count, pmap, start + ptoa(diff), m, 2907 prot, mpte); 2908 m = TAILQ_NEXT(m, listq); 2909 if (count == 16) { 2910 error = HYPERVISOR_multicall(mcl, count); 2911 KASSERT(error == 0, ("bad multicall %d", error)); 2912 mclp = mcl; 2913 count = 0; 2914 } 2915 } 2916 if (count) { 2917 error = HYPERVISOR_multicall(mcl, count); 2918 KASSERT(error == 0, ("bad multicall %d", error)); 2919 } 2920 2921 PMAP_UNLOCK(pmap); 2922} 2923 2924/* 2925 * this code makes some *MAJOR* assumptions: 2926 * 1. Current pmap & pmap exists. 2927 * 2. Not wired. 2928 * 3. Read access. 2929 * 4. No page table pages. 2930 * but is *MUCH* faster than pmap_enter... 2931 */ 2932 2933void 2934pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot) 2935{ 2936 multicall_entry_t mcl, *mclp; 2937 int count = 0; 2938 mclp = &mcl; 2939 2940 CTR4(KTR_PMAP, "pmap_enter_quick: pmap=%p va=0x%x m=%p prot=0x%x", 2941 pmap, va, m, prot); 2942 2943 PMAP_LOCK(pmap); 2944 (void) pmap_enter_quick_locked(&mclp, &count, pmap, va, m, prot, NULL); 2945 if (count) 2946 HYPERVISOR_multicall(&mcl, count); 2947 PMAP_UNLOCK(pmap); 2948} 2949 2950#ifdef notyet 2951void 2952pmap_enter_quick_range(pmap_t pmap, vm_offset_t *addrs, vm_page_t *pages, vm_prot_t *prots, int count) 2953{ 2954 int i, error, index = 0; 2955 multicall_entry_t mcl[16]; 2956 multicall_entry_t *mclp = mcl; 2957 2958 PMAP_LOCK(pmap); 2959 for (i = 0; i < count; i++, addrs++, pages++, prots++) { 2960 if (!pmap_is_prefaultable_locked(pmap, *addrs)) 2961 continue; 2962 2963 (void) pmap_enter_quick_locked(&mclp, &index, pmap, *addrs, *pages, *prots, NULL); 2964 if (index == 16) { 2965 error = HYPERVISOR_multicall(mcl, index); 2966 mclp = mcl; 2967 index = 0; 2968 KASSERT(error == 0, ("bad multicall %d", error)); 2969 } 2970 } 2971 if (index) { 2972 error = HYPERVISOR_multicall(mcl, index); 2973 KASSERT(error == 0, ("bad multicall %d", error)); 2974 } 2975 2976 PMAP_UNLOCK(pmap); 2977} 2978#endif 2979 2980static vm_page_t 2981pmap_enter_quick_locked(multicall_entry_t **mclpp, int *count, pmap_t pmap, vm_offset_t va, vm_page_t m, 2982 vm_prot_t prot, vm_page_t mpte) 2983{ 2984 pt_entry_t *pte; 2985 vm_paddr_t pa; 2986 vm_page_t free; 2987 multicall_entry_t *mcl = *mclpp; 2988 2989 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva || 2990 (m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0, 2991 ("pmap_enter_quick_locked: managed mapping within the clean submap")); 2992 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2993 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2994 2995 /* 2996 * In the case that a page table page is not 2997 * resident, we are creating it here. 2998 */ 2999 if (va < VM_MAXUSER_ADDRESS) { 3000 unsigned ptepindex; 3001 pd_entry_t ptema; 3002 3003 /* 3004 * Calculate pagetable page index 3005 */ 3006 ptepindex = va >> PDRSHIFT; 3007 if (mpte && (mpte->pindex == ptepindex)) { 3008 mpte->wire_count++; 3009 } else { 3010 /* 3011 * Get the page directory entry 3012 */ 3013 ptema = pmap->pm_pdir[ptepindex]; 3014 3015 /* 3016 * If the page table page is mapped, we just increment 3017 * the hold count, and activate it. 3018 */ 3019 if (ptema & PG_V) { 3020 if (ptema & PG_PS) 3021 panic("pmap_enter_quick: unexpected mapping into 4MB page"); 3022 mpte = PHYS_TO_VM_PAGE(xpmap_mtop(ptema) & PG_FRAME); 3023 mpte->wire_count++; 3024 } else { 3025 mpte = _pmap_allocpte(pmap, ptepindex, 3026 M_NOWAIT); 3027 if (mpte == NULL) 3028 return (mpte); 3029 } 3030 } 3031 } else { 3032 mpte = NULL; 3033 } 3034 3035 /* 3036 * This call to vtopte makes the assumption that we are 3037 * entering the page into the current pmap. In order to support 3038 * quick entry into any pmap, one would likely use pmap_pte_quick. 3039 * But that isn't as quick as vtopte. 3040 */ 3041 KASSERT(pmap_is_current(pmap), ("entering pages in non-current pmap")); 3042 pte = vtopte(va); 3043 if (*pte & PG_V) { 3044 if (mpte != NULL) { 3045 mpte->wire_count--; 3046 mpte = NULL; 3047 } 3048 return (mpte); 3049 } 3050 3051 /* 3052 * Enter on the PV list if part of our managed memory. 3053 */ 3054 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0 && 3055 !pmap_try_insert_pv_entry(pmap, va, m)) { 3056 if (mpte != NULL) { 3057 free = NULL; 3058 if (pmap_unwire_pte_hold(pmap, mpte, &free)) { 3059 pmap_invalidate_page(pmap, va); 3060 pmap_free_zero_pages(free); 3061 } 3062 3063 mpte = NULL; 3064 } 3065 return (mpte); 3066 } 3067 3068 /* 3069 * Increment counters 3070 */ 3071 pmap->pm_stats.resident_count++; 3072 3073 pa = VM_PAGE_TO_PHYS(m); 3074#ifdef PAE 3075 if ((prot & VM_PROT_EXECUTE) == 0) 3076 pa |= pg_nx; 3077#endif 3078 3079#if 0 3080 /* 3081 * Now validate mapping with RO protection 3082 */ 3083 if (m->flags & (PG_FICTITIOUS|PG_UNMANAGED)) 3084 pte_store(pte, pa | PG_V | PG_U); 3085 else 3086 pte_store(pte, pa | PG_V | PG_U | PG_MANAGED); 3087#else 3088 /* 3089 * Now validate mapping with RO protection 3090 */ 3091 if (m->flags & (PG_FICTITIOUS|PG_UNMANAGED)) 3092 pa = xpmap_ptom(pa | PG_V | PG_U); 3093 else 3094 pa = xpmap_ptom(pa | PG_V | PG_U | PG_MANAGED); 3095 3096 mcl->op = __HYPERVISOR_update_va_mapping; 3097 mcl->args[0] = va; 3098 mcl->args[1] = (uint32_t)(pa & 0xffffffff); 3099 mcl->args[2] = (uint32_t)(pa >> 32); 3100 mcl->args[3] = 0; 3101 *mclpp = mcl + 1; 3102 *count = *count + 1; 3103#endif 3104 return mpte; 3105} 3106 3107/* 3108 * Make a temporary mapping for a physical address. This is only intended 3109 * to be used for panic dumps. 3110 */ 3111void * 3112pmap_kenter_temporary(vm_paddr_t pa, int i) 3113{ 3114 vm_offset_t va; 3115 vm_paddr_t ma = xpmap_ptom(pa); 3116 3117 va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE); 3118 PT_SET_MA(va, (ma & ~PAGE_MASK) | PG_V | pgeflag); 3119 invlpg(va); 3120 return ((void *)crashdumpmap); 3121} 3122 3123/* 3124 * This code maps large physical mmap regions into the 3125 * processor address space. Note that some shortcuts 3126 * are taken, but the code works. 3127 */ 3128void 3129pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, 3130 vm_object_t object, vm_pindex_t pindex, 3131 vm_size_t size) 3132{ 3133 vm_page_t p; 3134 3135 VM_OBJECT_LOCK_ASSERT(object, MA_OWNED); 3136 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG, 3137 ("pmap_object_init_pt: non-device object")); 3138 if (pseflag && 3139 ((addr & (NBPDR - 1)) == 0) && ((size & (NBPDR - 1)) == 0)) { 3140 int i; 3141 vm_page_t m[1]; 3142 unsigned int ptepindex; 3143 int npdes; 3144 pd_entry_t ptepa; 3145 3146 PMAP_LOCK(pmap); 3147 if (pmap->pm_pdir[ptepindex = (addr >> PDRSHIFT)]) 3148 goto out; 3149 PMAP_UNLOCK(pmap); 3150retry: 3151 p = vm_page_lookup(object, pindex); 3152 if (p != NULL) { 3153 if (vm_page_sleep_if_busy(p, FALSE, "init4p")) 3154 goto retry; 3155 } else { 3156 p = vm_page_alloc(object, pindex, VM_ALLOC_NORMAL); 3157 if (p == NULL) 3158 return; 3159 m[0] = p; 3160 3161 if (vm_pager_get_pages(object, m, 1, 0) != VM_PAGER_OK) { 3162 vm_page_lock_queues(); 3163 vm_page_free(p); 3164 vm_page_unlock_queues(); 3165 return; 3166 } 3167 3168 p = vm_page_lookup(object, pindex); 3169 vm_page_wakeup(p); 3170 } 3171 3172 ptepa = VM_PAGE_TO_PHYS(p); 3173 if (ptepa & (NBPDR - 1)) 3174 return; 3175 3176 p->valid = VM_PAGE_BITS_ALL; 3177 3178 PMAP_LOCK(pmap); 3179 pmap->pm_stats.resident_count += size >> PAGE_SHIFT; 3180 npdes = size >> PDRSHIFT; 3181 critical_enter(); 3182 for(i = 0; i < npdes; i++) { 3183 PD_SET_VA(pmap, ptepindex, 3184 ptepa | PG_U | PG_M | PG_RW | PG_V | PG_PS, FALSE); 3185 ptepa += NBPDR; 3186 ptepindex += 1; 3187 } 3188 pmap_invalidate_all(pmap); 3189 critical_exit(); 3190out: 3191 PMAP_UNLOCK(pmap); 3192 } 3193} 3194 3195/* 3196 * Routine: pmap_change_wiring 3197 * Function: Change the wiring attribute for a map/virtual-address 3198 * pair. 3199 * In/out conditions: 3200 * The mapping must already exist in the pmap. 3201 */ 3202void 3203pmap_change_wiring(pmap_t pmap, vm_offset_t va, boolean_t wired) 3204{ 3205 pt_entry_t *pte; 3206 3207 vm_page_lock_queues(); 3208 PMAP_LOCK(pmap); 3209 pte = pmap_pte(pmap, va); 3210 3211 if (wired && !pmap_pte_w(pte)) { 3212 PT_SET_VA_MA((pte), *(pte) | PG_W, TRUE); 3213 pmap->pm_stats.wired_count++; 3214 } else if (!wired && pmap_pte_w(pte)) { 3215 PT_SET_VA_MA((pte), *(pte) & ~PG_W, TRUE); 3216 pmap->pm_stats.wired_count--; 3217 } 3218 3219 /* 3220 * Wiring is not a hardware characteristic so there is no need to 3221 * invalidate TLB. 3222 */ 3223 pmap_pte_release(pte); 3224 PMAP_UNLOCK(pmap); 3225 vm_page_unlock_queues(); 3226} 3227 3228 3229 3230/* 3231 * Copy the range specified by src_addr/len 3232 * from the source map to the range dst_addr/len 3233 * in the destination map. 3234 * 3235 * This routine is only advisory and need not do anything. 3236 */ 3237 3238void 3239pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len, 3240 vm_offset_t src_addr) 3241{ 3242 vm_page_t free; 3243 vm_offset_t addr; 3244 vm_offset_t end_addr = src_addr + len; 3245 vm_offset_t pdnxt; 3246 3247 if (dst_addr != src_addr) 3248 return; 3249 3250 if (!pmap_is_current(src_pmap)) { 3251 CTR2(KTR_PMAP, 3252 "pmap_copy, skipping: pdir[PTDPTDI]=0x%jx PTDpde[0]=0x%jx", 3253 (src_pmap->pm_pdir[PTDPTDI] & PG_FRAME), (PTDpde[0] & PG_FRAME)); 3254 3255 return; 3256 } 3257 CTR5(KTR_PMAP, "pmap_copy: dst_pmap=%p src_pmap=%p dst_addr=0x%x len=%d src_addr=0x%x", 3258 dst_pmap, src_pmap, dst_addr, len, src_addr); 3259 3260 vm_page_lock_queues(); 3261 if (dst_pmap < src_pmap) { 3262 PMAP_LOCK(dst_pmap); 3263 PMAP_LOCK(src_pmap); 3264 } else { 3265 PMAP_LOCK(src_pmap); 3266 PMAP_LOCK(dst_pmap); 3267 } 3268 sched_pin(); 3269 for (addr = src_addr; addr < end_addr; addr = pdnxt) { 3270 pt_entry_t *src_pte, *dst_pte; 3271 vm_page_t dstmpte, srcmpte; 3272 pd_entry_t srcptepaddr; 3273 unsigned ptepindex; 3274 3275 if (addr >= UPT_MIN_ADDRESS) 3276 panic("pmap_copy: invalid to pmap_copy page tables"); 3277 3278 pdnxt = (addr + NBPDR) & ~PDRMASK; 3279 ptepindex = addr >> PDRSHIFT; 3280 3281 srcptepaddr = PT_GET(&src_pmap->pm_pdir[ptepindex]); 3282 if (srcptepaddr == 0) 3283 continue; 3284 3285 if (srcptepaddr & PG_PS) { 3286 if (dst_pmap->pm_pdir[ptepindex] == 0) { 3287 PD_SET_VA(dst_pmap, ptepindex, srcptepaddr & ~PG_W, TRUE); 3288 dst_pmap->pm_stats.resident_count += 3289 NBPDR / PAGE_SIZE; 3290 } 3291 continue; 3292 } 3293 3294 srcmpte = PHYS_TO_VM_PAGE(srcptepaddr & PG_FRAME); 3295 if (srcmpte->wire_count == 0) 3296 panic("pmap_copy: source page table page is unused"); 3297 3298 if (pdnxt > end_addr) 3299 pdnxt = end_addr; 3300 3301 src_pte = vtopte(addr); 3302 while (addr < pdnxt) { 3303 pt_entry_t ptetemp; 3304 ptetemp = *src_pte; 3305 /* 3306 * we only virtual copy managed pages 3307 */ 3308 if ((ptetemp & PG_MANAGED) != 0) { 3309 dstmpte = pmap_allocpte(dst_pmap, addr, 3310 M_NOWAIT); 3311 if (dstmpte == NULL) 3312 break; 3313 dst_pte = pmap_pte_quick(dst_pmap, addr); 3314 if (*dst_pte == 0 && 3315 pmap_try_insert_pv_entry(dst_pmap, addr, 3316 PHYS_TO_VM_PAGE(xpmap_mtop(ptetemp) & PG_FRAME))) { 3317 /* 3318 * Clear the wired, modified, and 3319 * accessed (referenced) bits 3320 * during the copy. 3321 */ 3322 KASSERT(ptetemp != 0, ("src_pte not set")); 3323 PT_SET_VA_MA(dst_pte, ptetemp & ~(PG_W | PG_M | PG_A), TRUE /* XXX debug */); 3324 KASSERT(*dst_pte == (ptetemp & ~(PG_W | PG_M | PG_A)), 3325 ("no pmap copy expected: 0x%jx saw: 0x%jx", 3326 ptetemp & ~(PG_W | PG_M | PG_A), *dst_pte)); 3327 dst_pmap->pm_stats.resident_count++; 3328 } else { 3329 free = NULL; 3330 if (pmap_unwire_pte_hold(dst_pmap, 3331 dstmpte, &free)) { 3332 pmap_invalidate_page(dst_pmap, 3333 addr); 3334 pmap_free_zero_pages(free); 3335 } 3336 } 3337 if (dstmpte->wire_count >= srcmpte->wire_count) 3338 break; 3339 } 3340 addr += PAGE_SIZE; 3341 src_pte++; 3342 } 3343 } 3344 PT_UPDATES_FLUSH(); 3345 sched_unpin(); 3346 vm_page_unlock_queues(); 3347 PMAP_UNLOCK(src_pmap); 3348 PMAP_UNLOCK(dst_pmap); 3349} 3350 3351static __inline void 3352pagezero(void *page) 3353{ 3354#if defined(I686_CPU) 3355 if (cpu_class == CPUCLASS_686) { 3356#if defined(CPU_ENABLE_SSE) 3357 if (cpu_feature & CPUID_SSE2) 3358 sse2_pagezero(page); 3359 else 3360#endif 3361 i686_pagezero(page); 3362 } else 3363#endif 3364 bzero(page, PAGE_SIZE); 3365} 3366 3367/* 3368 * pmap_zero_page zeros the specified hardware page by mapping 3369 * the page into KVM and using bzero to clear its contents. 3370 */ 3371void 3372pmap_zero_page(vm_page_t m) 3373{ 3374 struct sysmaps *sysmaps; 3375 3376 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)]; 3377 mtx_lock(&sysmaps->lock); 3378 if (*sysmaps->CMAP2) 3379 panic("pmap_zero_page: CMAP2 busy"); 3380 sched_pin(); 3381 PT_SET_MA(sysmaps->CADDR2, PG_V | PG_RW | xpmap_ptom(VM_PAGE_TO_PHYS(m)) | PG_A | PG_M); 3382 pagezero(sysmaps->CADDR2); 3383 PT_SET_MA(sysmaps->CADDR2, 0); 3384 sched_unpin(); 3385 mtx_unlock(&sysmaps->lock); 3386} 3387 3388/* 3389 * pmap_zero_page_area zeros the specified hardware page by mapping 3390 * the page into KVM and using bzero to clear its contents. 3391 * 3392 * off and size may not cover an area beyond a single hardware page. 3393 */ 3394void 3395pmap_zero_page_area(vm_page_t m, int off, int size) 3396{ 3397 struct sysmaps *sysmaps; 3398 3399 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)]; 3400 mtx_lock(&sysmaps->lock); 3401 if (*sysmaps->CMAP2) 3402 panic("pmap_zero_page: CMAP2 busy"); 3403 sched_pin(); 3404 PT_SET_MA(sysmaps->CADDR2, PG_V | PG_RW | xpmap_ptom(VM_PAGE_TO_PHYS(m)) | PG_A | PG_M); 3405 3406 if (off == 0 && size == PAGE_SIZE) 3407 pagezero(sysmaps->CADDR2); 3408 else 3409 bzero((char *)sysmaps->CADDR2 + off, size); 3410 PT_SET_MA(sysmaps->CADDR2, 0); 3411 sched_unpin(); 3412 mtx_unlock(&sysmaps->lock); 3413} 3414 3415/* 3416 * pmap_zero_page_idle zeros the specified hardware page by mapping 3417 * the page into KVM and using bzero to clear its contents. This 3418 * is intended to be called from the vm_pagezero process only and 3419 * outside of Giant. 3420 */ 3421void 3422pmap_zero_page_idle(vm_page_t m) 3423{ 3424 3425 if (*CMAP3) 3426 panic("pmap_zero_page: CMAP3 busy"); 3427 sched_pin(); 3428 PT_SET_MA(CADDR3, PG_V | PG_RW | xpmap_ptom(VM_PAGE_TO_PHYS(m)) | PG_A | PG_M); 3429 pagezero(CADDR3); 3430 PT_SET_MA(CADDR3, 0); 3431 sched_unpin(); 3432} 3433 3434/* 3435 * pmap_copy_page copies the specified (machine independent) 3436 * page by mapping the page into virtual memory and using 3437 * bcopy to copy the page, one machine dependent page at a 3438 * time. 3439 */ 3440void 3441pmap_copy_page(vm_page_t src, vm_page_t dst) 3442{ 3443 struct sysmaps *sysmaps; 3444 3445 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)]; 3446 mtx_lock(&sysmaps->lock); 3447 if (*sysmaps->CMAP1) 3448 panic("pmap_copy_page: CMAP1 busy"); 3449 if (*sysmaps->CMAP2) 3450 panic("pmap_copy_page: CMAP2 busy"); 3451 sched_pin(); 3452 PT_SET_MA(sysmaps->CADDR1, PG_V | xpmap_ptom(VM_PAGE_TO_PHYS(src)) | PG_A); 3453 PT_SET_MA(sysmaps->CADDR2, PG_V | PG_RW | xpmap_ptom(VM_PAGE_TO_PHYS(dst)) | PG_A | PG_M); 3454 bcopy(sysmaps->CADDR1, sysmaps->CADDR2, PAGE_SIZE); 3455 PT_SET_MA(sysmaps->CADDR1, 0); 3456 PT_SET_MA(sysmaps->CADDR2, 0); 3457 sched_unpin(); 3458 mtx_unlock(&sysmaps->lock); 3459} 3460 3461/* 3462 * Returns true if the pmap's pv is one of the first 3463 * 16 pvs linked to from this page. This count may 3464 * be changed upwards or downwards in the future; it 3465 * is only necessary that true be returned for a small 3466 * subset of pmaps for proper page aging. 3467 */ 3468boolean_t 3469pmap_page_exists_quick(pmap_t pmap, vm_page_t m) 3470{ 3471 pv_entry_t pv; 3472 int loops = 0; 3473 3474 if (m->flags & PG_FICTITIOUS) 3475 return (FALSE); 3476 3477 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 3478 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 3479 if (PV_PMAP(pv) == pmap) { 3480 return TRUE; 3481 } 3482 loops++; 3483 if (loops >= 16) 3484 break; 3485 } 3486 return (FALSE); 3487} 3488 3489/* 3490 * pmap_page_wired_mappings: 3491 * 3492 * Return the number of managed mappings to the given physical page 3493 * that are wired. 3494 */ 3495int 3496pmap_page_wired_mappings(vm_page_t m) 3497{ 3498 pv_entry_t pv; 3499 pt_entry_t *pte; 3500 pmap_t pmap; 3501 int count; 3502 3503 count = 0; 3504 if ((m->flags & PG_FICTITIOUS) != 0) 3505 return (count); 3506 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 3507 sched_pin(); 3508 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 3509 pmap = PV_PMAP(pv); 3510 PMAP_LOCK(pmap); 3511 pte = pmap_pte_quick(pmap, pv->pv_va); 3512 if ((*pte & PG_W) != 0) 3513 count++; 3514 PMAP_UNLOCK(pmap); 3515 } 3516 sched_unpin(); 3517 return (count); 3518} 3519 3520/* 3521 * Returns TRUE if the given page is mapped individually or as part of 3522 * a 4mpage. Otherwise, returns FALSE. 3523 */ 3524boolean_t 3525pmap_page_is_mapped(vm_page_t m) 3526{ 3527 struct md_page *pvh; 3528 3529 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0) 3530 return (FALSE); 3531 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 3532 if (TAILQ_EMPTY(&m->md.pv_list)) { 3533 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 3534 return (!TAILQ_EMPTY(&pvh->pv_list)); 3535 } else 3536 return (TRUE); 3537} 3538 3539/* 3540 * Remove all pages from specified address space 3541 * this aids process exit speeds. Also, this code 3542 * is special cased for current process only, but 3543 * can have the more generic (and slightly slower) 3544 * mode enabled. This is much faster than pmap_remove 3545 * in the case of running down an entire address space. 3546 */ 3547void 3548pmap_remove_pages(pmap_t pmap) 3549{ 3550 pt_entry_t *pte, tpte; 3551 vm_page_t m, free = NULL; 3552 pv_entry_t pv; 3553 struct pv_chunk *pc, *npc; 3554 int field, idx; 3555 int32_t bit; 3556 uint32_t inuse, bitmask; 3557 int allfree; 3558 3559 CTR1(KTR_PMAP, "pmap_remove_pages: pmap=%p", pmap); 3560 3561 if (pmap != vmspace_pmap(curthread->td_proc->p_vmspace)) { 3562 printf("warning: pmap_remove_pages called with non-current pmap\n"); 3563 return; 3564 } 3565 vm_page_lock_queues(); 3566 KASSERT(pmap_is_current(pmap), ("removing pages from non-current pmap")); 3567 PMAP_LOCK(pmap); 3568 sched_pin(); 3569 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) { 3570 allfree = 1; 3571 for (field = 0; field < _NPCM; field++) { 3572 inuse = (~(pc->pc_map[field])) & pc_freemask[field]; 3573 while (inuse != 0) { 3574 bit = bsfl(inuse); 3575 bitmask = 1UL << bit; 3576 idx = field * 32 + bit; 3577 pv = &pc->pc_pventry[idx]; 3578 inuse &= ~bitmask; 3579 3580 pte = vtopte(pv->pv_va); 3581 tpte = *pte ? xpmap_mtop(*pte) : 0; 3582 3583 if (tpte == 0) { 3584 printf( 3585 "TPTE at %p IS ZERO @ VA %08x\n", 3586 pte, pv->pv_va); 3587 panic("bad pte"); 3588 } 3589 3590/* 3591 * We cannot remove wired pages from a process' mapping at this time 3592 */ 3593 if (tpte & PG_W) { 3594 allfree = 0; 3595 continue; 3596 } 3597 3598 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME); 3599 KASSERT(m->phys_addr == (tpte & PG_FRAME), 3600 ("vm_page_t %p phys_addr mismatch %016jx %016jx", 3601 m, (uintmax_t)m->phys_addr, 3602 (uintmax_t)tpte)); 3603 3604 KASSERT(m < &vm_page_array[vm_page_array_size], 3605 ("pmap_remove_pages: bad tpte %#jx", 3606 (uintmax_t)tpte)); 3607 3608 3609 PT_CLEAR_VA(pte, FALSE); 3610 3611 /* 3612 * Update the vm_page_t clean/reference bits. 3613 */ 3614 if (tpte & PG_M) 3615 vm_page_dirty(m); 3616 3617 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list); 3618 if (TAILQ_EMPTY(&m->md.pv_list)) 3619 vm_page_flag_clear(m, PG_WRITEABLE); 3620 3621 pmap_unuse_pt(pmap, pv->pv_va, &free); 3622 3623 /* Mark free */ 3624 PV_STAT(pv_entry_frees++); 3625 PV_STAT(pv_entry_spare++); 3626 pv_entry_count--; 3627 pc->pc_map[field] |= bitmask; 3628 pmap->pm_stats.resident_count--; 3629 } 3630 } 3631 PT_UPDATES_FLUSH(); 3632 if (allfree) { 3633 PV_STAT(pv_entry_spare -= _NPCPV); 3634 PV_STAT(pc_chunk_count--); 3635 PV_STAT(pc_chunk_frees++); 3636 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 3637 m = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc)); 3638 pmap_qremove((vm_offset_t)pc, 1); 3639 vm_page_unwire(m, 0); 3640 vm_page_free(m); 3641 pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc); 3642 } 3643 } 3644 PT_UPDATES_FLUSH(); 3645 if (*PMAP1) 3646 PT_SET_MA(PADDR1, 0); 3647 3648 sched_unpin(); 3649 pmap_invalidate_all(pmap); 3650 vm_page_unlock_queues(); 3651 PMAP_UNLOCK(pmap); 3652 pmap_free_zero_pages(free); 3653} 3654 3655/* 3656 * pmap_is_modified: 3657 * 3658 * Return whether or not the specified physical page was modified 3659 * in any physical maps. 3660 */ 3661boolean_t 3662pmap_is_modified(vm_page_t m) 3663{ 3664 pv_entry_t pv; 3665 pt_entry_t *pte; 3666 pmap_t pmap; 3667 boolean_t rv; 3668 3669 rv = FALSE; 3670 if (m->flags & PG_FICTITIOUS) 3671 return (rv); 3672 3673 sched_pin(); 3674 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 3675 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 3676 pmap = PV_PMAP(pv); 3677 PMAP_LOCK(pmap); 3678 pte = pmap_pte_quick(pmap, pv->pv_va); 3679 rv = (*pte & PG_M) != 0; 3680 PMAP_UNLOCK(pmap); 3681 if (rv) 3682 break; 3683 } 3684 if (*PMAP1) 3685 PT_SET_MA(PADDR1, 0); 3686 sched_unpin(); 3687 return (rv); 3688} 3689 3690/* 3691 * pmap_is_prefaultable: 3692 * 3693 * Return whether or not the specified virtual address is elgible 3694 * for prefault. 3695 */ 3696static boolean_t 3697pmap_is_prefaultable_locked(pmap_t pmap, vm_offset_t addr) 3698{ 3699 pt_entry_t *pte; 3700 boolean_t rv = FALSE; 3701 3702 return (rv); 3703 3704 if (pmap_is_current(pmap) && *pmap_pde(pmap, addr)) { 3705 pte = vtopte(addr); 3706 rv = (*pte == 0); 3707 } 3708 return (rv); 3709} 3710 3711boolean_t 3712pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr) 3713{ 3714 boolean_t rv; 3715 3716 PMAP_LOCK(pmap); 3717 rv = pmap_is_prefaultable_locked(pmap, addr); 3718 PMAP_UNLOCK(pmap); 3719 return (rv); 3720} 3721 3722boolean_t 3723pmap_is_referenced(vm_page_t m) 3724{ 3725 pv_entry_t pv; 3726 pt_entry_t *pte; 3727 pmap_t pmap; 3728 boolean_t rv; 3729 3730 rv = FALSE; 3731 if (m->flags & PG_FICTITIOUS) 3732 return (rv); 3733 sched_pin(); 3734 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 3735 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 3736 pmap = PV_PMAP(pv); 3737 PMAP_LOCK(pmap); 3738 pte = pmap_pte_quick(pmap, pv->pv_va); 3739 rv = (*pte & (PG_A | PG_V)) == (PG_A | PG_V); 3740 PMAP_UNLOCK(pmap); 3741 if (rv) 3742 break; 3743 } 3744 if (*PMAP1) 3745 PT_SET_MA(PADDR1, 0); 3746 sched_unpin(); 3747 return (rv); 3748} 3749 3750void 3751pmap_map_readonly(pmap_t pmap, vm_offset_t va, int len) 3752{ 3753 int i, npages = round_page(len) >> PAGE_SHIFT; 3754 for (i = 0; i < npages; i++) { 3755 pt_entry_t *pte; 3756 pte = pmap_pte(pmap, (vm_offset_t)(va + i*PAGE_SIZE)); 3757 pte_store(pte, xpmap_mtop(*pte & ~(PG_RW|PG_M))); 3758 PMAP_MARK_PRIV(xpmap_mtop(*pte)); 3759 pmap_pte_release(pte); 3760 } 3761} 3762 3763void 3764pmap_map_readwrite(pmap_t pmap, vm_offset_t va, int len) 3765{ 3766 int i, npages = round_page(len) >> PAGE_SHIFT; 3767 for (i = 0; i < npages; i++) { 3768 pt_entry_t *pte; 3769 pte = pmap_pte(pmap, (vm_offset_t)(va + i*PAGE_SIZE)); 3770 PMAP_MARK_UNPRIV(xpmap_mtop(*pte)); 3771 pte_store(pte, xpmap_mtop(*pte) | (PG_RW|PG_M)); 3772 pmap_pte_release(pte); 3773 } 3774} 3775 3776/* 3777 * Clear the write and modified bits in each of the given page's mappings. 3778 */ 3779void 3780pmap_remove_write(vm_page_t m) 3781{ 3782 pv_entry_t pv; 3783 pmap_t pmap; 3784 pt_entry_t oldpte, *pte; 3785 3786 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 3787 if ((m->flags & PG_FICTITIOUS) != 0 || 3788 (m->flags & PG_WRITEABLE) == 0) 3789 return; 3790 sched_pin(); 3791 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 3792 pmap = PV_PMAP(pv); 3793 PMAP_LOCK(pmap); 3794 pte = pmap_pte_quick(pmap, pv->pv_va); 3795retry: 3796 oldpte = *pte; 3797 if ((oldpte & PG_RW) != 0) { 3798 vm_paddr_t newpte = oldpte & ~(PG_RW | PG_M); 3799 3800 /* 3801 * Regardless of whether a pte is 32 or 64 bits 3802 * in size, PG_RW and PG_M are among the least 3803 * significant 32 bits. 3804 */ 3805 PT_SET_VA_MA(pte, newpte, TRUE); 3806 if (*pte != newpte) 3807 goto retry; 3808 3809 if ((oldpte & PG_M) != 0) 3810 vm_page_dirty(m); 3811 pmap_invalidate_page(pmap, pv->pv_va); 3812 } 3813 PMAP_UNLOCK(pmap); 3814 } 3815 vm_page_flag_clear(m, PG_WRITEABLE); 3816 PT_UPDATES_FLUSH(); 3817 if (*PMAP1) 3818 PT_SET_MA(PADDR1, 0); 3819 sched_unpin(); 3820} 3821 3822/* 3823 * pmap_ts_referenced: 3824 * 3825 * Return a count of reference bits for a page, clearing those bits. 3826 * It is not necessary for every reference bit to be cleared, but it 3827 * is necessary that 0 only be returned when there are truly no 3828 * reference bits set. 3829 * 3830 * XXX: The exact number of bits to check and clear is a matter that 3831 * should be tested and standardized at some point in the future for 3832 * optimal aging of shared pages. 3833 */ 3834int 3835pmap_ts_referenced(vm_page_t m) 3836{ 3837 pv_entry_t pv, pvf, pvn; 3838 pmap_t pmap; 3839 pt_entry_t *pte; 3840 int rtval = 0; 3841 3842 if (m->flags & PG_FICTITIOUS) 3843 return (rtval); 3844 sched_pin(); 3845 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 3846 if ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) { 3847 pvf = pv; 3848 do { 3849 pvn = TAILQ_NEXT(pv, pv_list); 3850 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list); 3851 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list); 3852 pmap = PV_PMAP(pv); 3853 PMAP_LOCK(pmap); 3854 pte = pmap_pte_quick(pmap, pv->pv_va); 3855 if ((*pte & PG_A) != 0) { 3856 PT_SET_VA_MA(pte, *pte & ~PG_A, FALSE); 3857 pmap_invalidate_page(pmap, pv->pv_va); 3858 rtval++; 3859 if (rtval > 4) 3860 pvn = NULL; 3861 } 3862 PMAP_UNLOCK(pmap); 3863 } while ((pv = pvn) != NULL && pv != pvf); 3864 } 3865 PT_UPDATES_FLUSH(); 3866 if (*PMAP1) 3867 PT_SET_MA(PADDR1, 0); 3868 3869 sched_unpin(); 3870 return (rtval); 3871} 3872 3873/* 3874 * Clear the modify bits on the specified physical page. 3875 */ 3876void 3877pmap_clear_modify(vm_page_t m) 3878{ 3879 pv_entry_t pv; 3880 pmap_t pmap; 3881 pt_entry_t *pte; 3882 3883 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 3884 if ((m->flags & PG_FICTITIOUS) != 0) 3885 return; 3886 sched_pin(); 3887 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 3888 pmap = PV_PMAP(pv); 3889 PMAP_LOCK(pmap); 3890 pte = pmap_pte_quick(pmap, pv->pv_va); 3891 if ((*pte & PG_M) != 0) { 3892 /* 3893 * Regardless of whether a pte is 32 or 64 bits 3894 * in size, PG_M is among the least significant 3895 * 32 bits. 3896 */ 3897 PT_SET_VA_MA(pte, *pte & ~PG_M, FALSE); 3898 pmap_invalidate_page(pmap, pv->pv_va); 3899 } 3900 PMAP_UNLOCK(pmap); 3901 } 3902 sched_unpin(); 3903} 3904 3905/* 3906 * pmap_clear_reference: 3907 * 3908 * Clear the reference bit on the specified physical page. 3909 */ 3910void 3911pmap_clear_reference(vm_page_t m) 3912{ 3913 pv_entry_t pv; 3914 pmap_t pmap; 3915 pt_entry_t *pte; 3916 3917 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 3918 if ((m->flags & PG_FICTITIOUS) != 0) 3919 return; 3920 sched_pin(); 3921 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 3922 pmap = PV_PMAP(pv); 3923 PMAP_LOCK(pmap); 3924 pte = pmap_pte_quick(pmap, pv->pv_va); 3925 if ((*pte & PG_A) != 0) { 3926 /* 3927 * Regardless of whether a pte is 32 or 64 bits 3928 * in size, PG_A is among the least significant 3929 * 32 bits. 3930 */ 3931 PT_SET_VA_MA(pte, *pte & ~PG_A, FALSE); 3932 pmap_invalidate_page(pmap, pv->pv_va); 3933 } 3934 PMAP_UNLOCK(pmap); 3935 } 3936 sched_unpin(); 3937} 3938 3939/* 3940 * Miscellaneous support routines follow 3941 */ 3942 3943/* 3944 * Map a set of physical memory pages into the kernel virtual 3945 * address space. Return a pointer to where it is mapped. This 3946 * routine is intended to be used for mapping device memory, 3947 * NOT real memory. 3948 */ 3949void * 3950pmap_mapdev_attr(vm_paddr_t pa, vm_size_t size, int mode) 3951{ 3952 vm_offset_t va, offset; 3953 vm_size_t tmpsize; 3954 3955 offset = pa & PAGE_MASK; 3956 size = roundup(offset + size, PAGE_SIZE); 3957 pa = pa & PG_FRAME; 3958 3959 if (pa < KERNLOAD && pa + size <= KERNLOAD) 3960 va = KERNBASE + pa; 3961 else 3962 va = kmem_alloc_nofault(kernel_map, size); 3963 if (!va) 3964 panic("pmap_mapdev: Couldn't alloc kernel virtual memory"); 3965 3966 for (tmpsize = 0; tmpsize < size; tmpsize += PAGE_SIZE) 3967 pmap_kenter_attr(va + tmpsize, pa + tmpsize, mode); 3968 pmap_invalidate_range(kernel_pmap, va, va + tmpsize); 3969 pmap_invalidate_cache_range(va, va + size); 3970 return ((void *)(va + offset)); 3971} 3972 3973void * 3974pmap_mapdev(vm_paddr_t pa, vm_size_t size) 3975{ 3976 3977 return (pmap_mapdev_attr(pa, size, PAT_UNCACHEABLE)); 3978} 3979 3980void * 3981pmap_mapbios(vm_paddr_t pa, vm_size_t size) 3982{ 3983 3984 return (pmap_mapdev_attr(pa, size, PAT_WRITE_BACK)); 3985} 3986 3987void 3988pmap_unmapdev(vm_offset_t va, vm_size_t size) 3989{ 3990 vm_offset_t base, offset, tmpva; 3991 3992 if (va >= KERNBASE && va + size <= KERNBASE + KERNLOAD) 3993 return; 3994 base = trunc_page(va); 3995 offset = va & PAGE_MASK; 3996 size = roundup(offset + size, PAGE_SIZE); 3997 critical_enter(); 3998 for (tmpva = base; tmpva < (base + size); tmpva += PAGE_SIZE) 3999 pmap_kremove(tmpva); 4000 pmap_invalidate_range(kernel_pmap, va, tmpva); 4001 critical_exit(); 4002 kmem_free(kernel_map, base, size); 4003} 4004 4005/* 4006 * Sets the memory attribute for the specified page. 4007 */ 4008void 4009pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma) 4010{ 4011 struct sysmaps *sysmaps; 4012 vm_offset_t sva, eva; 4013 4014 m->md.pat_mode = ma; 4015 if ((m->flags & PG_FICTITIOUS) != 0) 4016 return; 4017 4018 /* 4019 * If "m" is a normal page, flush it from the cache. 4020 * See pmap_invalidate_cache_range(). 4021 * 4022 * First, try to find an existing mapping of the page by sf 4023 * buffer. sf_buf_invalidate_cache() modifies mapping and 4024 * flushes the cache. 4025 */ 4026 if (sf_buf_invalidate_cache(m)) 4027 return; 4028 4029 /* 4030 * If page is not mapped by sf buffer, but CPU does not 4031 * support self snoop, map the page transient and do 4032 * invalidation. In the worst case, whole cache is flushed by 4033 * pmap_invalidate_cache_range(). 4034 */ 4035 if ((cpu_feature & (CPUID_SS|CPUID_CLFSH)) == CPUID_CLFSH) { 4036 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)]; 4037 mtx_lock(&sysmaps->lock); 4038 if (*sysmaps->CMAP2) 4039 panic("pmap_page_set_memattr: CMAP2 busy"); 4040 sched_pin(); 4041 PT_SET_MA(sysmaps->CADDR2, PG_V | PG_RW | 4042 xpmap_ptom(VM_PAGE_TO_PHYS(m)) | PG_A | PG_M | 4043 pmap_cache_bits(m->md.pat_mode, 0)); 4044 invlcaddr(sysmaps->CADDR2); 4045 sva = (vm_offset_t)sysmaps->CADDR2; 4046 eva = sva + PAGE_SIZE; 4047 } else 4048 sva = eva = 0; /* gcc */ 4049 pmap_invalidate_cache_range(sva, eva); 4050 if (sva != 0) { 4051 PT_SET_MA(sysmaps->CADDR2, 0); 4052 sched_unpin(); 4053 mtx_unlock(&sysmaps->lock); 4054 } 4055} 4056 4057int 4058pmap_change_attr(va, size, mode) 4059 vm_offset_t va; 4060 vm_size_t size; 4061 int mode; 4062{ 4063 vm_offset_t base, offset, tmpva; 4064 pt_entry_t *pte; 4065 u_int opte, npte; 4066 pd_entry_t *pde; 4067 boolean_t changed; 4068 4069 base = trunc_page(va); 4070 offset = va & PAGE_MASK; 4071 size = roundup(offset + size, PAGE_SIZE); 4072 4073 /* Only supported on kernel virtual addresses. */ 4074 if (base <= VM_MAXUSER_ADDRESS) 4075 return (EINVAL); 4076 4077 /* 4MB pages and pages that aren't mapped aren't supported. */ 4078 for (tmpva = base; tmpva < (base + size); tmpva += PAGE_SIZE) { 4079 pde = pmap_pde(kernel_pmap, tmpva); 4080 if (*pde & PG_PS) 4081 return (EINVAL); 4082 if ((*pde & PG_V) == 0) 4083 return (EINVAL); 4084 pte = vtopte(va); 4085 if ((*pte & PG_V) == 0) 4086 return (EINVAL); 4087 } 4088 4089 changed = FALSE; 4090 4091 /* 4092 * Ok, all the pages exist and are 4k, so run through them updating 4093 * their cache mode. 4094 */ 4095 for (tmpva = base; size > 0; ) { 4096 pte = vtopte(tmpva); 4097 4098 /* 4099 * The cache mode bits are all in the low 32-bits of the 4100 * PTE, so we can just spin on updating the low 32-bits. 4101 */ 4102 do { 4103 opte = *(u_int *)pte; 4104 npte = opte & ~(PG_PTE_PAT | PG_NC_PCD | PG_NC_PWT); 4105 npte |= pmap_cache_bits(mode, 0); 4106 PT_SET_VA_MA(pte, npte, TRUE); 4107 } while (npte != opte && (*pte != npte)); 4108 if (npte != opte) 4109 changed = TRUE; 4110 tmpva += PAGE_SIZE; 4111 size -= PAGE_SIZE; 4112 } 4113 4114 /* 4115 * Flush CPU caches to make sure any data isn't cached that shouldn't 4116 * be, etc. 4117 */ 4118 if (changed) { 4119 pmap_invalidate_range(kernel_pmap, base, tmpva); 4120 pmap_invalidate_cache_range(base, tmpva); 4121 } 4122 return (0); 4123} 4124 4125/* 4126 * perform the pmap work for mincore 4127 */ 4128int 4129pmap_mincore(pmap_t pmap, vm_offset_t addr) 4130{ 4131 pt_entry_t *ptep, pte; 4132 vm_page_t m; 4133 int val = 0; 4134 4135 PMAP_LOCK(pmap); 4136 ptep = pmap_pte(pmap, addr); 4137 pte = (ptep != NULL) ? PT_GET(ptep) : 0; 4138 pmap_pte_release(ptep); 4139 PMAP_UNLOCK(pmap); 4140 4141 if (pte != 0) { 4142 vm_paddr_t pa; 4143 4144 val = MINCORE_INCORE; 4145 if ((pte & PG_MANAGED) == 0) 4146 return val; 4147 4148 pa = pte & PG_FRAME; 4149 4150 m = PHYS_TO_VM_PAGE(pa); 4151 4152 /* 4153 * Modified by us 4154 */ 4155 if (pte & PG_M) 4156 val |= MINCORE_MODIFIED|MINCORE_MODIFIED_OTHER; 4157 else { 4158 /* 4159 * Modified by someone else 4160 */ 4161 vm_page_lock_queues(); 4162 if (m->dirty || pmap_is_modified(m)) 4163 val |= MINCORE_MODIFIED_OTHER; 4164 vm_page_unlock_queues(); 4165 } 4166 /* 4167 * Referenced by us 4168 */ 4169 if (pte & PG_A) 4170 val |= MINCORE_REFERENCED|MINCORE_REFERENCED_OTHER; 4171 else { 4172 /* 4173 * Referenced by someone else 4174 */ 4175 vm_page_lock_queues(); 4176 if ((m->flags & PG_REFERENCED) || 4177 pmap_is_referenced(m)) 4178 val |= MINCORE_REFERENCED_OTHER; 4179 vm_page_unlock_queues(); 4180 } 4181 } 4182 return val; 4183} 4184 4185void 4186pmap_activate(struct thread *td) 4187{ 4188 pmap_t pmap, oldpmap; 4189 u_int32_t cr3; 4190 4191 critical_enter(); 4192 pmap = vmspace_pmap(td->td_proc->p_vmspace); 4193 oldpmap = PCPU_GET(curpmap); 4194#if defined(SMP) 4195 atomic_clear_int(&oldpmap->pm_active, PCPU_GET(cpumask)); 4196 atomic_set_int(&pmap->pm_active, PCPU_GET(cpumask)); 4197#else 4198 oldpmap->pm_active &= ~1; 4199 pmap->pm_active |= 1; 4200#endif 4201#ifdef PAE 4202 cr3 = vtophys(pmap->pm_pdpt); 4203#else 4204 cr3 = vtophys(pmap->pm_pdir); 4205#endif 4206 /* 4207 * pmap_activate is for the current thread on the current cpu 4208 */ 4209 td->td_pcb->pcb_cr3 = cr3; 4210 PT_UPDATES_FLUSH(); 4211 load_cr3(cr3); 4212 PCPU_SET(curpmap, pmap); 4213 critical_exit(); 4214} 4215 4216void 4217pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz) 4218{ 4219} 4220 4221/* 4222 * Increase the starting virtual address of the given mapping if a 4223 * different alignment might result in more superpage mappings. 4224 */ 4225void 4226pmap_align_superpage(vm_object_t object, vm_ooffset_t offset, 4227 vm_offset_t *addr, vm_size_t size) 4228{ 4229 vm_offset_t superpage_offset; 4230 4231 if (size < NBPDR) 4232 return; 4233 if (object != NULL && (object->flags & OBJ_COLORED) != 0) 4234 offset += ptoa(object->pg_color); 4235 superpage_offset = offset & PDRMASK; 4236 if (size - ((NBPDR - superpage_offset) & PDRMASK) < NBPDR || 4237 (*addr & PDRMASK) == superpage_offset) 4238 return; 4239 if ((*addr & PDRMASK) < superpage_offset) 4240 *addr = (*addr & ~PDRMASK) + superpage_offset; 4241 else 4242 *addr = ((*addr + PDRMASK) & ~PDRMASK) + superpage_offset; 4243} 4244 4245#ifdef XEN 4246 4247void 4248pmap_suspend() 4249{ 4250 pmap_t pmap; 4251 int i, pdir, offset; 4252 vm_paddr_t pdirma; 4253 mmu_update_t mu[4]; 4254 4255 /* 4256 * We need to remove the recursive mapping structure from all 4257 * our pmaps so that Xen doesn't get confused when it restores 4258 * the page tables. The recursive map lives at page directory 4259 * index PTDPTDI. We assume that the suspend code has stopped 4260 * the other vcpus (if any). 4261 */ 4262 LIST_FOREACH(pmap, &allpmaps, pm_list) { 4263 for (i = 0; i < 4; i++) { 4264 /* 4265 * Figure out which page directory (L2) page 4266 * contains this bit of the recursive map and 4267 * the offset within that page of the map 4268 * entry 4269 */ 4270 pdir = (PTDPTDI + i) / NPDEPG; 4271 offset = (PTDPTDI + i) % NPDEPG; 4272 pdirma = pmap->pm_pdpt[pdir] & PG_FRAME; 4273 mu[i].ptr = pdirma + offset * sizeof(pd_entry_t); 4274 mu[i].val = 0; 4275 } 4276 HYPERVISOR_mmu_update(mu, 4, NULL, DOMID_SELF); 4277 } 4278} 4279 4280void 4281pmap_resume() 4282{ 4283 pmap_t pmap; 4284 int i, pdir, offset; 4285 vm_paddr_t pdirma; 4286 mmu_update_t mu[4]; 4287 4288 /* 4289 * Restore the recursive map that we removed on suspend. 4290 */ 4291 LIST_FOREACH(pmap, &allpmaps, pm_list) { 4292 for (i = 0; i < 4; i++) { 4293 /* 4294 * Figure out which page directory (L2) page 4295 * contains this bit of the recursive map and 4296 * the offset within that page of the map 4297 * entry 4298 */ 4299 pdir = (PTDPTDI + i) / NPDEPG; 4300 offset = (PTDPTDI + i) % NPDEPG; 4301 pdirma = pmap->pm_pdpt[pdir] & PG_FRAME; 4302 mu[i].ptr = pdirma + offset * sizeof(pd_entry_t); 4303 mu[i].val = (pmap->pm_pdpt[i] & PG_FRAME) | PG_V; 4304 } 4305 HYPERVISOR_mmu_update(mu, 4, NULL, DOMID_SELF); 4306 } 4307} 4308 4309#endif 4310 4311#if defined(PMAP_DEBUG) 4312pmap_pid_dump(int pid) 4313{ 4314 pmap_t pmap; 4315 struct proc *p; 4316 int npte = 0; 4317 int index; 4318 4319 sx_slock(&allproc_lock); 4320 FOREACH_PROC_IN_SYSTEM(p) { 4321 if (p->p_pid != pid) 4322 continue; 4323 4324 if (p->p_vmspace) { 4325 int i,j; 4326 index = 0; 4327 pmap = vmspace_pmap(p->p_vmspace); 4328 for (i = 0; i < NPDEPTD; i++) { 4329 pd_entry_t *pde; 4330 pt_entry_t *pte; 4331 vm_offset_t base = i << PDRSHIFT; 4332 4333 pde = &pmap->pm_pdir[i]; 4334 if (pde && pmap_pde_v(pde)) { 4335 for (j = 0; j < NPTEPG; j++) { 4336 vm_offset_t va = base + (j << PAGE_SHIFT); 4337 if (va >= (vm_offset_t) VM_MIN_KERNEL_ADDRESS) { 4338 if (index) { 4339 index = 0; 4340 printf("\n"); 4341 } 4342 sx_sunlock(&allproc_lock); 4343 return npte; 4344 } 4345 pte = pmap_pte(pmap, va); 4346 if (pte && pmap_pte_v(pte)) { 4347 pt_entry_t pa; 4348 vm_page_t m; 4349 pa = PT_GET(pte); 4350 m = PHYS_TO_VM_PAGE(pa & PG_FRAME); 4351 printf("va: 0x%x, pt: 0x%x, h: %d, w: %d, f: 0x%x", 4352 va, pa, m->hold_count, m->wire_count, m->flags); 4353 npte++; 4354 index++; 4355 if (index >= 2) { 4356 index = 0; 4357 printf("\n"); 4358 } else { 4359 printf(" "); 4360 } 4361 } 4362 } 4363 } 4364 } 4365 } 4366 } 4367 sx_sunlock(&allproc_lock); 4368 return npte; 4369} 4370#endif 4371 4372#if defined(DEBUG) 4373 4374static void pads(pmap_t pm); 4375void pmap_pvdump(vm_paddr_t pa); 4376 4377/* print address space of pmap*/ 4378static void 4379pads(pmap_t pm) 4380{ 4381 int i, j; 4382 vm_paddr_t va; 4383 pt_entry_t *ptep; 4384 4385 if (pm == kernel_pmap) 4386 return; 4387 for (i = 0; i < NPDEPTD; i++) 4388 if (pm->pm_pdir[i]) 4389 for (j = 0; j < NPTEPG; j++) { 4390 va = (i << PDRSHIFT) + (j << PAGE_SHIFT); 4391 if (pm == kernel_pmap && va < KERNBASE) 4392 continue; 4393 if (pm != kernel_pmap && va > UPT_MAX_ADDRESS) 4394 continue; 4395 ptep = pmap_pte(pm, va); 4396 if (pmap_pte_v(ptep)) 4397 printf("%x:%x ", va, *ptep); 4398 }; 4399 4400} 4401 4402void 4403pmap_pvdump(vm_paddr_t pa) 4404{ 4405 pv_entry_t pv; 4406 pmap_t pmap; 4407 vm_page_t m; 4408 4409 printf("pa %x", pa); 4410 m = PHYS_TO_VM_PAGE(pa); 4411 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 4412 pmap = PV_PMAP(pv); 4413 printf(" -> pmap %p, va %x", (void *)pmap, pv->pv_va); 4414 pads(pmap); 4415 } 4416 printf(" "); 4417} 4418#endif 4419