1181641Skmacy/*- 2181641Skmacy * Copyright (c) 1991 Regents of the University of California. 3181641Skmacy * All rights reserved. 4181641Skmacy * Copyright (c) 1994 John S. Dyson 5181641Skmacy * All rights reserved. 6181641Skmacy * Copyright (c) 1994 David Greenman 7181641Skmacy * All rights reserved. 8181641Skmacy * Copyright (c) 2005 Alan L. Cox <alc@cs.rice.edu> 9181641Skmacy * All rights reserved. 10181641Skmacy * 11181641Skmacy * This code is derived from software contributed to Berkeley by 12181641Skmacy * the Systems Programming Group of the University of Utah Computer 13181641Skmacy * Science Department and William Jolitz of UUNET Technologies Inc. 14181641Skmacy * 15181641Skmacy * Redistribution and use in source and binary forms, with or without 16181641Skmacy * modification, are permitted provided that the following conditions 17181641Skmacy * are met: 18181641Skmacy * 1. Redistributions of source code must retain the above copyright 19181641Skmacy * notice, this list of conditions and the following disclaimer. 20181641Skmacy * 2. Redistributions in binary form must reproduce the above copyright 21181641Skmacy * notice, this list of conditions and the following disclaimer in the 22181641Skmacy * documentation and/or other materials provided with the distribution. 23181641Skmacy * 3. All advertising materials mentioning features or use of this software 24181641Skmacy * must display the following acknowledgement: 25181641Skmacy * This product includes software developed by the University of 26181641Skmacy * California, Berkeley and its contributors. 27181641Skmacy * 4. Neither the name of the University nor the names of its contributors 28181641Skmacy * may be used to endorse or promote products derived from this software 29181641Skmacy * without specific prior written permission. 30181641Skmacy * 31181641Skmacy * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 32181641Skmacy * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 33181641Skmacy * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 34181641Skmacy * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 35181641Skmacy * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 36181641Skmacy * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 37181641Skmacy * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 38181641Skmacy * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 39181641Skmacy * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 40181641Skmacy * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 41181641Skmacy * SUCH DAMAGE. 42181641Skmacy * 43181641Skmacy * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91 44181641Skmacy */ 45181641Skmacy/*- 46181641Skmacy * Copyright (c) 2003 Networks Associates Technology, Inc. 47181641Skmacy * All rights reserved. 48181641Skmacy * 49181641Skmacy * This software was developed for the FreeBSD Project by Jake Burkholder, 50181641Skmacy * Safeport Network Services, and Network Associates Laboratories, the 51181641Skmacy * Security Research Division of Network Associates, Inc. under 52181641Skmacy * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA 53181641Skmacy * CHATS research program. 54181641Skmacy * 55181641Skmacy * Redistribution and use in source and binary forms, with or without 56181641Skmacy * modification, are permitted provided that the following conditions 57181641Skmacy * are met: 58181641Skmacy * 1. Redistributions of source code must retain the above copyright 59181641Skmacy * notice, this list of conditions and the following disclaimer. 60181641Skmacy * 2. Redistributions in binary form must reproduce the above copyright 61181641Skmacy * notice, this list of conditions and the following disclaimer in the 62181641Skmacy * documentation and/or other materials provided with the distribution. 63181641Skmacy * 64181641Skmacy * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 65181641Skmacy * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 66181641Skmacy * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 67181641Skmacy * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 68181641Skmacy * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 69181641Skmacy * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 70181641Skmacy * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 71181641Skmacy * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 72181641Skmacy * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 73181641Skmacy * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 74181641Skmacy * SUCH DAMAGE. 75181641Skmacy */ 76181641Skmacy 77181641Skmacy#include <sys/cdefs.h> 78181641Skmacy__FBSDID("$FreeBSD$"); 79181641Skmacy 80181641Skmacy/* 81181641Skmacy * Manages physical address maps. 82181641Skmacy * 83181641Skmacy * In addition to hardware address maps, this 84181641Skmacy * module is called upon to provide software-use-only 85181641Skmacy * maps which may or may not be stored in the same 86181641Skmacy * form as hardware maps. These pseudo-maps are 87181641Skmacy * used to store intermediate results from copy 88181641Skmacy * operations to and from address spaces. 89181641Skmacy * 90181641Skmacy * Since the information managed by this module is 91181641Skmacy * also stored by the logical address mapping module, 92181641Skmacy * this module may throw away valid virtual-to-physical 93181641Skmacy * mappings at almost any time. However, invalidations 94181641Skmacy * of virtual-to-physical mappings must be done as 95181641Skmacy * requested. 96181641Skmacy * 97181641Skmacy * In order to cope with hardware architectures which 98181641Skmacy * make virtual-to-physical map invalidates expensive, 99181641Skmacy * this module may delay invalidate or reduced protection 100181641Skmacy * operations until such time as they are actually 101181641Skmacy * necessary. This module is given full information as 102181641Skmacy * to which processors are currently using which maps, 103181641Skmacy * and to when physical maps must be made correct. 104181641Skmacy */ 105181641Skmacy 106181641Skmacy#include "opt_cpu.h" 107181641Skmacy#include "opt_pmap.h" 108181641Skmacy#include "opt_smp.h" 109181641Skmacy#include "opt_xbox.h" 110181641Skmacy 111181641Skmacy#include <sys/param.h> 112181641Skmacy#include <sys/systm.h> 113181641Skmacy#include <sys/kernel.h> 114181641Skmacy#include <sys/ktr.h> 115181641Skmacy#include <sys/lock.h> 116181641Skmacy#include <sys/malloc.h> 117181641Skmacy#include <sys/mman.h> 118181641Skmacy#include <sys/msgbuf.h> 119181641Skmacy#include <sys/mutex.h> 120181641Skmacy#include <sys/proc.h> 121195949Skib#include <sys/sf_buf.h> 122181641Skmacy#include <sys/sx.h> 123181641Skmacy#include <sys/vmmeter.h> 124181641Skmacy#include <sys/sched.h> 125181641Skmacy#include <sys/sysctl.h> 126181641Skmacy#ifdef SMP 127181641Skmacy#include <sys/smp.h> 128230435Salc#else 129230435Salc#include <sys/cpuset.h> 130181641Skmacy#endif 131181641Skmacy 132181641Skmacy#include <vm/vm.h> 133181641Skmacy#include <vm/vm_param.h> 134181641Skmacy#include <vm/vm_kern.h> 135181641Skmacy#include <vm/vm_page.h> 136181641Skmacy#include <vm/vm_map.h> 137181641Skmacy#include <vm/vm_object.h> 138181641Skmacy#include <vm/vm_extern.h> 139181641Skmacy#include <vm/vm_pageout.h> 140181641Skmacy#include <vm/vm_pager.h> 141181641Skmacy#include <vm/uma.h> 142181641Skmacy 143181641Skmacy#include <machine/cpu.h> 144181641Skmacy#include <machine/cputypes.h> 145181641Skmacy#include <machine/md_var.h> 146181641Skmacy#include <machine/pcb.h> 147181641Skmacy#include <machine/specialreg.h> 148181641Skmacy#ifdef SMP 149181641Skmacy#include <machine/smp.h> 150181641Skmacy#endif 151181641Skmacy 152181641Skmacy#ifdef XBOX 153181641Skmacy#include <machine/xbox.h> 154181641Skmacy#endif 155181641Skmacy 156181641Skmacy#include <xen/interface/xen.h> 157186557Skmacy#include <xen/hypervisor.h> 158181641Skmacy#include <machine/xen/hypercall.h> 159181641Skmacy#include <machine/xen/xenvar.h> 160181641Skmacy#include <machine/xen/xenfunc.h> 161181641Skmacy 162181641Skmacy#if !defined(CPU_DISABLE_SSE) && defined(I686_CPU) 163181641Skmacy#define CPU_ENABLE_SSE 164181641Skmacy#endif 165181641Skmacy 166181641Skmacy#ifndef PMAP_SHPGPERPROC 167181641Skmacy#define PMAP_SHPGPERPROC 200 168181641Skmacy#endif 169181641Skmacy 170208651Salc#define DIAGNOSTIC 171181641Skmacy 172208651Salc#if !defined(DIAGNOSTIC) 173204041Sed#ifdef __GNUC_GNU_INLINE__ 174208651Salc#define PMAP_INLINE __attribute__((__gnu_inline__)) inline 175204041Sed#else 176202628Sed#define PMAP_INLINE extern inline 177204041Sed#endif 178181641Skmacy#else 179181641Skmacy#define PMAP_INLINE 180181641Skmacy#endif 181181641Skmacy 182181641Skmacy#define PV_STATS 183181641Skmacy#ifdef PV_STATS 184181641Skmacy#define PV_STAT(x) do { x ; } while (0) 185181641Skmacy#else 186181641Skmacy#define PV_STAT(x) do { } while (0) 187181641Skmacy#endif 188181641Skmacy 189181641Skmacy/* 190181641Skmacy * Get PDEs and PTEs for user/kernel address space 191181641Skmacy */ 192181641Skmacy#define pmap_pde(m, v) (&((m)->pm_pdir[(vm_offset_t)(v) >> PDRSHIFT])) 193181641Skmacy#define pdir_pde(m, v) (m[(vm_offset_t)(v) >> PDRSHIFT]) 194181641Skmacy 195181641Skmacy#define pmap_pde_v(pte) ((*(int *)pte & PG_V) != 0) 196181641Skmacy#define pmap_pte_w(pte) ((*(int *)pte & PG_W) != 0) 197181641Skmacy#define pmap_pte_m(pte) ((*(int *)pte & PG_M) != 0) 198181641Skmacy#define pmap_pte_u(pte) ((*(int *)pte & PG_A) != 0) 199181641Skmacy#define pmap_pte_v(pte) ((*(int *)pte & PG_V) != 0) 200181641Skmacy 201181641Skmacy#define pmap_pte_set_prot(pte, v) ((*(int *)pte &= ~PG_PROT), (*(int *)pte |= (v))) 202181641Skmacy 203216960Scperciva#define HAMFISTED_LOCKING 204216960Scperciva#ifdef HAMFISTED_LOCKING 205216960Scpercivastatic struct mtx createdelete_lock; 206216960Scperciva#endif 207216960Scperciva 208181641Skmacystruct pmap kernel_pmap_store; 209181641SkmacyLIST_HEAD(pmaplist, pmap); 210181641Skmacystatic struct pmaplist allpmaps; 211181641Skmacystatic struct mtx allpmaps_lock; 212181641Skmacy 213181641Skmacyvm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */ 214181641Skmacyvm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */ 215181641Skmacyint pgeflag = 0; /* PG_G or-in */ 216181641Skmacyint pseflag = 0; /* PG_PS or-in */ 217181641Skmacy 218182902Skmacyint nkpt; 219181641Skmacyvm_offset_t kernel_vm_end; 220181641Skmacyextern u_int32_t KERNend; 221181641Skmacy 222181641Skmacy#ifdef PAE 223181641Skmacypt_entry_t pg_nx; 224181641Skmacy#endif 225181641Skmacy 226230435Salcstatic SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD, 0, "VM/pmap parameters"); 227230435Salc 228196726Sadrianstatic int pat_works; /* Is page attribute table sane? */ 229196726Sadrian 230181641Skmacy/* 231181641Skmacy * Data for the pv entry allocation mechanism 232181641Skmacy */ 233237950Salcstatic TAILQ_HEAD(pch, pv_chunk) pv_chunks = TAILQ_HEAD_INITIALIZER(pv_chunks); 234181641Skmacystatic int pv_entry_count = 0, pv_entry_max = 0, pv_entry_high_water = 0; 235181641Skmacystatic int shpgperproc = PMAP_SHPGPERPROC; 236181641Skmacy 237181641Skmacystruct pv_chunk *pv_chunkbase; /* KVA block for pv_chunks */ 238181641Skmacyint pv_maxchunks; /* How many chunks we have KVA for */ 239181641Skmacyvm_offset_t pv_vafree; /* freelist stored in the PTE */ 240181641Skmacy 241181641Skmacy/* 242181641Skmacy * All those kernel PT submaps that BSD is so fond of 243181641Skmacy */ 244181641Skmacystruct sysmaps { 245181641Skmacy struct mtx lock; 246181641Skmacy pt_entry_t *CMAP1; 247181641Skmacy pt_entry_t *CMAP2; 248181641Skmacy caddr_t CADDR1; 249181641Skmacy caddr_t CADDR2; 250181641Skmacy}; 251181641Skmacystatic struct sysmaps sysmaps_pcpu[MAXCPU]; 252181641Skmacystatic pt_entry_t *CMAP3; 253204160Skmacycaddr_t ptvmmap = 0; 254181641Skmacystatic caddr_t CADDR3; 255181641Skmacystruct msgbuf *msgbufp = 0; 256181641Skmacy 257181641Skmacy/* 258181641Skmacy * Crashdump maps. 259181641Skmacy */ 260181641Skmacystatic caddr_t crashdumpmap; 261181641Skmacy 262181641Skmacystatic pt_entry_t *PMAP1 = 0, *PMAP2; 263181641Skmacystatic pt_entry_t *PADDR1 = 0, *PADDR2; 264181641Skmacy#ifdef SMP 265181641Skmacystatic int PMAP1cpu; 266181641Skmacystatic int PMAP1changedcpu; 267181641SkmacySYSCTL_INT(_debug, OID_AUTO, PMAP1changedcpu, CTLFLAG_RD, 268181641Skmacy &PMAP1changedcpu, 0, 269181641Skmacy "Number of times pmap_pte_quick changed CPU with same PMAP1"); 270181641Skmacy#endif 271181641Skmacystatic int PMAP1changed; 272181641SkmacySYSCTL_INT(_debug, OID_AUTO, PMAP1changed, CTLFLAG_RD, 273181641Skmacy &PMAP1changed, 0, 274181641Skmacy "Number of times pmap_pte_quick changed PMAP1"); 275181641Skmacystatic int PMAP1unchanged; 276181641SkmacySYSCTL_INT(_debug, OID_AUTO, PMAP1unchanged, CTLFLAG_RD, 277181641Skmacy &PMAP1unchanged, 0, 278181641Skmacy "Number of times pmap_pte_quick didn't change PMAP1"); 279181641Skmacystatic struct mtx PMAP2mutex; 280181641Skmacy 281237950Salcstatic void free_pv_chunk(struct pv_chunk *pc); 282181641Skmacystatic void free_pv_entry(pmap_t pmap, pv_entry_t pv); 283237950Salcstatic pv_entry_t get_pv_entry(pmap_t pmap, boolean_t try); 284208651Salcstatic void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va); 285208651Salcstatic pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, 286208651Salc vm_offset_t va); 287181641Skmacy 288181641Skmacystatic vm_page_t pmap_enter_quick_locked(multicall_entry_t **mcl, int *count, pmap_t pmap, vm_offset_t va, 289181641Skmacy vm_page_t m, vm_prot_t prot, vm_page_t mpte); 290230435Salcstatic void pmap_flush_page(vm_page_t m); 291230435Salcstatic void pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode); 292181641Skmacystatic int pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t sva, 293181641Skmacy vm_page_t *free); 294181641Skmacystatic void pmap_remove_page(struct pmap *pmap, vm_offset_t va, 295181641Skmacy vm_page_t *free); 296181641Skmacystatic void pmap_remove_entry(struct pmap *pmap, vm_page_t m, 297181641Skmacy vm_offset_t va); 298181641Skmacystatic boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, 299181641Skmacy vm_page_t m); 300181641Skmacy 301181641Skmacystatic vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va, int flags); 302181641Skmacy 303230435Salcstatic vm_page_t _pmap_allocpte(pmap_t pmap, u_int ptepindex, int flags); 304240151Skibstatic void _pmap_unwire_ptp(pmap_t pmap, vm_page_t m, vm_page_t *free); 305181641Skmacystatic pt_entry_t *pmap_pte_quick(pmap_t pmap, vm_offset_t va); 306181641Skmacystatic void pmap_pte_release(pt_entry_t *pte); 307181641Skmacystatic int pmap_unuse_pt(pmap_t, vm_offset_t, vm_page_t *); 308181641Skmacystatic boolean_t pmap_is_prefaultable_locked(pmap_t pmap, vm_offset_t addr); 309181641Skmacy 310196725Sadrianstatic __inline void pagezero(void *page); 311181747Skmacy 312181641SkmacyCTASSERT(1 << PDESHIFT == sizeof(pd_entry_t)); 313181641SkmacyCTASSERT(1 << PTESHIFT == sizeof(pt_entry_t)); 314181641Skmacy 315181641Skmacy/* 316181641Skmacy * If you get an error here, then you set KVA_PAGES wrong! See the 317181641Skmacy * description of KVA_PAGES in sys/i386/include/pmap.h. It must be 318181641Skmacy * multiple of 4 for a normal kernel, or a multiple of 8 for a PAE. 319181641Skmacy */ 320181641SkmacyCTASSERT(KERNBASE % (1 << 24) == 0); 321181641Skmacy 322181641Skmacyvoid 323181641Skmacypd_set(struct pmap *pmap, int ptepindex, vm_paddr_t val, int type) 324181641Skmacy{ 325181641Skmacy vm_paddr_t pdir_ma = vtomach(&pmap->pm_pdir[ptepindex]); 326181641Skmacy 327181641Skmacy switch (type) { 328181641Skmacy case SH_PD_SET_VA: 329181641Skmacy#if 0 330181641Skmacy xen_queue_pt_update(shadow_pdir_ma, 331181641Skmacy xpmap_ptom(val & ~(PG_RW))); 332181641Skmacy#endif 333181641Skmacy xen_queue_pt_update(pdir_ma, 334181641Skmacy xpmap_ptom(val)); 335181641Skmacy break; 336181641Skmacy case SH_PD_SET_VA_MA: 337181641Skmacy#if 0 338181641Skmacy xen_queue_pt_update(shadow_pdir_ma, 339181641Skmacy val & ~(PG_RW)); 340181641Skmacy#endif 341181641Skmacy xen_queue_pt_update(pdir_ma, val); 342181641Skmacy break; 343181641Skmacy case SH_PD_SET_VA_CLEAR: 344181641Skmacy#if 0 345181641Skmacy xen_queue_pt_update(shadow_pdir_ma, 0); 346181641Skmacy#endif 347181641Skmacy xen_queue_pt_update(pdir_ma, 0); 348181641Skmacy break; 349181641Skmacy } 350181641Skmacy} 351181641Skmacy 352181641Skmacy/* 353181641Skmacy * Bootstrap the system enough to run with virtual memory. 354181641Skmacy * 355181641Skmacy * On the i386 this is called after mapping has already been enabled 356181641Skmacy * and just syncs the pmap module with what has already been done. 357181641Skmacy * [We can't call it easily with mapping off since the kernel is not 358181641Skmacy * mapped with PA == VA, hence we would have to relocate every address 359181641Skmacy * from the linked base (virtual) address "KERNBASE" to the actual 360181641Skmacy * (physical) address starting relative to 0] 361181641Skmacy */ 362181641Skmacyvoid 363181641Skmacypmap_bootstrap(vm_paddr_t firstaddr) 364181641Skmacy{ 365181641Skmacy vm_offset_t va; 366181641Skmacy pt_entry_t *pte, *unused; 367181641Skmacy struct sysmaps *sysmaps; 368181641Skmacy int i; 369181641Skmacy 370181641Skmacy /* 371230435Salc * Initialize the first available kernel virtual address. However, 372230435Salc * using "firstaddr" may waste a few pages of the kernel virtual 373230435Salc * address space, because locore may not have mapped every physical 374230435Salc * page that it allocated. Preferably, locore would provide a first 375230435Salc * unused virtual address in addition to "firstaddr". 376181641Skmacy */ 377181641Skmacy virtual_avail = (vm_offset_t) KERNBASE + firstaddr; 378181641Skmacy 379181641Skmacy virtual_end = VM_MAX_KERNEL_ADDRESS; 380181641Skmacy 381181641Skmacy /* 382181641Skmacy * Initialize the kernel pmap (which is statically allocated). 383181641Skmacy */ 384181641Skmacy PMAP_LOCK_INIT(kernel_pmap); 385181641Skmacy kernel_pmap->pm_pdir = (pd_entry_t *) (KERNBASE + (u_int)IdlePTD); 386181641Skmacy#ifdef PAE 387181641Skmacy kernel_pmap->pm_pdpt = (pdpt_entry_t *) (KERNBASE + (u_int)IdlePDPT); 388181641Skmacy#endif 389222813Sattilio CPU_FILL(&kernel_pmap->pm_active); /* don't allow deactivation */ 390181641Skmacy TAILQ_INIT(&kernel_pmap->pm_pvchunk); 391181641Skmacy LIST_INIT(&allpmaps); 392181641Skmacy mtx_init(&allpmaps_lock, "allpmaps", NULL, MTX_SPIN); 393181641Skmacy mtx_lock_spin(&allpmaps_lock); 394181641Skmacy LIST_INSERT_HEAD(&allpmaps, kernel_pmap, pm_list); 395181641Skmacy mtx_unlock_spin(&allpmaps_lock); 396183342Skmacy if (nkpt == 0) 397183342Skmacy nkpt = NKPT; 398181641Skmacy 399181641Skmacy /* 400181641Skmacy * Reserve some special page table entries/VA space for temporary 401181641Skmacy * mapping of pages. 402181641Skmacy */ 403181641Skmacy#define SYSMAP(c, p, v, n) \ 404181641Skmacy v = (c)va; va += ((n)*PAGE_SIZE); p = pte; pte += (n); 405181641Skmacy 406181641Skmacy va = virtual_avail; 407181641Skmacy pte = vtopte(va); 408181641Skmacy 409181641Skmacy /* 410181641Skmacy * CMAP1/CMAP2 are used for zeroing and copying pages. 411181641Skmacy * CMAP3 is used for the idle process page zeroing. 412181641Skmacy */ 413181641Skmacy for (i = 0; i < MAXCPU; i++) { 414181641Skmacy sysmaps = &sysmaps_pcpu[i]; 415181641Skmacy mtx_init(&sysmaps->lock, "SYSMAPS", NULL, MTX_DEF); 416181641Skmacy SYSMAP(caddr_t, sysmaps->CMAP1, sysmaps->CADDR1, 1) 417181641Skmacy SYSMAP(caddr_t, sysmaps->CMAP2, sysmaps->CADDR2, 1) 418204160Skmacy PT_SET_MA(sysmaps->CADDR1, 0); 419204160Skmacy PT_SET_MA(sysmaps->CADDR2, 0); 420181641Skmacy } 421181641Skmacy SYSMAP(caddr_t, CMAP3, CADDR3, 1) 422181641Skmacy PT_SET_MA(CADDR3, 0); 423181641Skmacy 424181641Skmacy /* 425181641Skmacy * Crashdump maps. 426181641Skmacy */ 427181641Skmacy SYSMAP(caddr_t, unused, crashdumpmap, MAXDUMPPGS) 428181641Skmacy 429181641Skmacy /* 430181641Skmacy * ptvmmap is used for reading arbitrary physical pages via /dev/mem. 431181641Skmacy */ 432181641Skmacy SYSMAP(caddr_t, unused, ptvmmap, 1) 433181641Skmacy 434181641Skmacy /* 435181641Skmacy * msgbufp is used to map the system message buffer. 436181641Skmacy */ 437217688Spluknet SYSMAP(struct msgbuf *, unused, msgbufp, atop(round_page(msgbufsize))) 438181641Skmacy 439181641Skmacy /* 440241518Salc * PADDR1 and PADDR2 are used by pmap_pte_quick() and pmap_pte(), 441241518Salc * respectively. 442181641Skmacy */ 443230435Salc SYSMAP(pt_entry_t *, PMAP1, PADDR1, 1) 444230435Salc SYSMAP(pt_entry_t *, PMAP2, PADDR2, 1) 445181641Skmacy 446181641Skmacy mtx_init(&PMAP2mutex, "PMAP2", NULL, MTX_DEF); 447181641Skmacy 448181641Skmacy virtual_avail = va; 449181641Skmacy 450181641Skmacy /* 451181641Skmacy * Leave in place an identity mapping (virt == phys) for the low 1 MB 452181641Skmacy * physical memory region that is used by the ACPI wakeup code. This 453181641Skmacy * mapping must not have PG_G set. 454181641Skmacy */ 455181641Skmacy#ifndef XEN 456181641Skmacy /* 457181641Skmacy * leave here deliberately to show that this is not supported 458181641Skmacy */ 459181641Skmacy#ifdef XBOX 460181641Skmacy /* FIXME: This is gross, but needed for the XBOX. Since we are in such 461181641Skmacy * an early stadium, we cannot yet neatly map video memory ... :-( 462181641Skmacy * Better fixes are very welcome! */ 463181641Skmacy if (!arch_i386_is_xbox) 464181641Skmacy#endif 465181641Skmacy for (i = 1; i < NKPT; i++) 466181641Skmacy PTD[i] = 0; 467181641Skmacy 468181641Skmacy /* Initialize the PAT MSR if present. */ 469181641Skmacy pmap_init_pat(); 470181641Skmacy 471181641Skmacy /* Turn on PG_G on kernel page(s) */ 472181641Skmacy pmap_set_pg(); 473181641Skmacy#endif 474216960Scperciva 475216960Scperciva#ifdef HAMFISTED_LOCKING 476216960Scperciva mtx_init(&createdelete_lock, "pmap create/delete", NULL, MTX_DEF); 477216960Scperciva#endif 478181641Skmacy} 479181641Skmacy 480181641Skmacy/* 481181641Skmacy * Setup the PAT MSR. 482181641Skmacy */ 483181641Skmacyvoid 484181641Skmacypmap_init_pat(void) 485181641Skmacy{ 486181641Skmacy uint64_t pat_msr; 487181641Skmacy 488181641Skmacy /* Bail if this CPU doesn't implement PAT. */ 489181641Skmacy if (!(cpu_feature & CPUID_PAT)) 490181641Skmacy return; 491181641Skmacy 492196726Sadrian if (cpu_vendor_id != CPU_VENDOR_INTEL || 493197070Sjkim (CPUID_TO_FAMILY(cpu_id) == 6 && CPUID_TO_MODEL(cpu_id) >= 0xe)) { 494196726Sadrian /* 495196726Sadrian * Leave the indices 0-3 at the default of WB, WT, UC, and UC-. 496196726Sadrian * Program 4 and 5 as WP and WC. 497196726Sadrian * Leave 6 and 7 as UC and UC-. 498196726Sadrian */ 499196726Sadrian pat_msr = rdmsr(MSR_PAT); 500196726Sadrian pat_msr &= ~(PAT_MASK(4) | PAT_MASK(5)); 501196726Sadrian pat_msr |= PAT_VALUE(4, PAT_WRITE_PROTECTED) | 502196726Sadrian PAT_VALUE(5, PAT_WRITE_COMBINING); 503196726Sadrian pat_works = 1; 504196726Sadrian } else { 505196726Sadrian /* 506196726Sadrian * Due to some Intel errata, we can only safely use the lower 4 507196726Sadrian * PAT entries. Thus, just replace PAT Index 2 with WC instead 508196726Sadrian * of UC-. 509196726Sadrian * 510196726Sadrian * Intel Pentium III Processor Specification Update 511196726Sadrian * Errata E.27 (Upper Four PAT Entries Not Usable With Mode B 512196726Sadrian * or Mode C Paging) 513196726Sadrian * 514196726Sadrian * Intel Pentium IV Processor Specification Update 515196726Sadrian * Errata N46 (PAT Index MSB May Be Calculated Incorrectly) 516196726Sadrian */ 517196726Sadrian pat_msr = rdmsr(MSR_PAT); 518196726Sadrian pat_msr &= ~PAT_MASK(2); 519196726Sadrian pat_msr |= PAT_VALUE(2, PAT_WRITE_COMBINING); 520196726Sadrian pat_works = 0; 521196726Sadrian } 522181641Skmacy wrmsr(MSR_PAT, pat_msr); 523181641Skmacy} 524181641Skmacy 525181641Skmacy/* 526181641Skmacy * Initialize a vm_page's machine-dependent fields. 527181641Skmacy */ 528181641Skmacyvoid 529181641Skmacypmap_page_init(vm_page_t m) 530181641Skmacy{ 531181641Skmacy 532181641Skmacy TAILQ_INIT(&m->md.pv_list); 533195649Salc m->md.pat_mode = PAT_WRITE_BACK; 534181641Skmacy} 535181641Skmacy 536181641Skmacy/* 537181641Skmacy * ABuse the pte nodes for unmapped kva to thread a kva freelist through. 538181641Skmacy * Requirements: 539181641Skmacy * - Must deal with pages in order to ensure that none of the PG_* bits 540181641Skmacy * are ever set, PG_V in particular. 541181641Skmacy * - Assumes we can write to ptes without pte_store() atomic ops, even 542181641Skmacy * on PAE systems. This should be ok. 543181641Skmacy * - Assumes nothing will ever test these addresses for 0 to indicate 544181641Skmacy * no mapping instead of correctly checking PG_V. 545181641Skmacy * - Assumes a vm_offset_t will fit in a pte (true for i386). 546181641Skmacy * Because PG_V is never set, there can be no mappings to invalidate. 547181641Skmacy */ 548181641Skmacystatic int ptelist_count = 0; 549181641Skmacystatic vm_offset_t 550181641Skmacypmap_ptelist_alloc(vm_offset_t *head) 551181641Skmacy{ 552181641Skmacy vm_offset_t va; 553181641Skmacy vm_offset_t *phead = (vm_offset_t *)*head; 554181641Skmacy 555181641Skmacy if (ptelist_count == 0) { 556181641Skmacy printf("out of memory!!!!!!\n"); 557181641Skmacy return (0); /* Out of memory */ 558181641Skmacy } 559181641Skmacy ptelist_count--; 560181641Skmacy va = phead[ptelist_count]; 561181641Skmacy return (va); 562181641Skmacy} 563181641Skmacy 564181641Skmacystatic void 565181641Skmacypmap_ptelist_free(vm_offset_t *head, vm_offset_t va) 566181641Skmacy{ 567181641Skmacy vm_offset_t *phead = (vm_offset_t *)*head; 568181641Skmacy 569181641Skmacy phead[ptelist_count++] = va; 570181641Skmacy} 571181641Skmacy 572181641Skmacystatic void 573181641Skmacypmap_ptelist_init(vm_offset_t *head, void *base, int npages) 574181641Skmacy{ 575181641Skmacy int i, nstackpages; 576181641Skmacy vm_offset_t va; 577181641Skmacy vm_page_t m; 578181641Skmacy 579181641Skmacy nstackpages = (npages + PAGE_SIZE/sizeof(vm_offset_t) - 1)/ (PAGE_SIZE/sizeof(vm_offset_t)); 580181641Skmacy for (i = 0; i < nstackpages; i++) { 581181641Skmacy va = (vm_offset_t)base + i * PAGE_SIZE; 582181641Skmacy m = vm_page_alloc(NULL, i, 583181641Skmacy VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | 584181641Skmacy VM_ALLOC_ZERO); 585181641Skmacy pmap_qenter(va, &m, 1); 586181641Skmacy } 587181641Skmacy 588181641Skmacy *head = (vm_offset_t)base; 589181641Skmacy for (i = npages - 1; i >= nstackpages; i--) { 590181641Skmacy va = (vm_offset_t)base + i * PAGE_SIZE; 591181641Skmacy pmap_ptelist_free(head, va); 592181641Skmacy } 593181641Skmacy} 594181641Skmacy 595181641Skmacy 596181641Skmacy/* 597181641Skmacy * Initialize the pmap module. 598181641Skmacy * Called by vm_init, to initialize any structures that the pmap 599181641Skmacy * system needs to map virtual memory. 600181641Skmacy */ 601181641Skmacyvoid 602181641Skmacypmap_init(void) 603181641Skmacy{ 604181641Skmacy 605181641Skmacy /* 606181641Skmacy * Initialize the address space (zone) for the pv entries. Set a 607181641Skmacy * high water mark so that the system can recover from excessive 608181641Skmacy * numbers of pv entries. 609181641Skmacy */ 610181641Skmacy TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc); 611181641Skmacy pv_entry_max = shpgperproc * maxproc + cnt.v_page_count; 612181641Skmacy TUNABLE_INT_FETCH("vm.pmap.pv_entries", &pv_entry_max); 613181641Skmacy pv_entry_max = roundup(pv_entry_max, _NPCPV); 614181641Skmacy pv_entry_high_water = 9 * (pv_entry_max / 10); 615181641Skmacy 616181641Skmacy pv_maxchunks = MAX(pv_entry_max / _NPCPV, maxproc); 617181641Skmacy pv_chunkbase = (struct pv_chunk *)kmem_alloc_nofault(kernel_map, 618181641Skmacy PAGE_SIZE * pv_maxchunks); 619181641Skmacy if (pv_chunkbase == NULL) 620181641Skmacy panic("pmap_init: not enough kvm for pv chunks"); 621181641Skmacy pmap_ptelist_init(&pv_vafree, pv_chunkbase, pv_maxchunks); 622181641Skmacy} 623181641Skmacy 624181641Skmacy 625230435SalcSYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_max, CTLFLAG_RD, &pv_entry_max, 0, 626230435Salc "Max number of PV entries"); 627230435SalcSYSCTL_INT(_vm_pmap, OID_AUTO, shpgperproc, CTLFLAG_RD, &shpgperproc, 0, 628230435Salc "Page share factor per proc"); 629230435Salc 630230435Salcstatic SYSCTL_NODE(_vm_pmap, OID_AUTO, pde, CTLFLAG_RD, 0, 631230435Salc "2/4MB page mapping counters"); 632230435Salc 633230435Salcstatic u_long pmap_pde_mappings; 634230435SalcSYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, mappings, CTLFLAG_RD, 635230435Salc &pmap_pde_mappings, 0, "2/4MB page mappings"); 636230435Salc 637181641Skmacy/*************************************************** 638181641Skmacy * Low level helper routines..... 639181641Skmacy ***************************************************/ 640181641Skmacy 641181641Skmacy/* 642181641Skmacy * Determine the appropriate bits to set in a PTE or PDE for a specified 643181641Skmacy * caching mode. 644181641Skmacy */ 645195949Skibint 646181641Skmacypmap_cache_bits(int mode, boolean_t is_pde) 647181641Skmacy{ 648181641Skmacy int pat_flag, pat_index, cache_bits; 649181641Skmacy 650181641Skmacy /* The PAT bit is different for PTE's and PDE's. */ 651181641Skmacy pat_flag = is_pde ? PG_PDE_PAT : PG_PTE_PAT; 652181641Skmacy 653181641Skmacy /* If we don't support PAT, map extended modes to older ones. */ 654181641Skmacy if (!(cpu_feature & CPUID_PAT)) { 655181641Skmacy switch (mode) { 656181641Skmacy case PAT_UNCACHEABLE: 657181641Skmacy case PAT_WRITE_THROUGH: 658181641Skmacy case PAT_WRITE_BACK: 659181641Skmacy break; 660181641Skmacy case PAT_UNCACHED: 661181641Skmacy case PAT_WRITE_COMBINING: 662181641Skmacy case PAT_WRITE_PROTECTED: 663181641Skmacy mode = PAT_UNCACHEABLE; 664181641Skmacy break; 665181641Skmacy } 666181641Skmacy } 667181641Skmacy 668181641Skmacy /* Map the caching mode to a PAT index. */ 669196726Sadrian if (pat_works) { 670196726Sadrian switch (mode) { 671196726Sadrian case PAT_UNCACHEABLE: 672196726Sadrian pat_index = 3; 673196726Sadrian break; 674196726Sadrian case PAT_WRITE_THROUGH: 675196726Sadrian pat_index = 1; 676196726Sadrian break; 677196726Sadrian case PAT_WRITE_BACK: 678196726Sadrian pat_index = 0; 679196726Sadrian break; 680196726Sadrian case PAT_UNCACHED: 681196726Sadrian pat_index = 2; 682196726Sadrian break; 683196726Sadrian case PAT_WRITE_COMBINING: 684196726Sadrian pat_index = 5; 685196726Sadrian break; 686196726Sadrian case PAT_WRITE_PROTECTED: 687196726Sadrian pat_index = 4; 688196726Sadrian break; 689196726Sadrian default: 690196726Sadrian panic("Unknown caching mode %d\n", mode); 691196726Sadrian } 692196726Sadrian } else { 693196726Sadrian switch (mode) { 694196726Sadrian case PAT_UNCACHED: 695196726Sadrian case PAT_UNCACHEABLE: 696196726Sadrian case PAT_WRITE_PROTECTED: 697196726Sadrian pat_index = 3; 698196726Sadrian break; 699196726Sadrian case PAT_WRITE_THROUGH: 700196726Sadrian pat_index = 1; 701196726Sadrian break; 702196726Sadrian case PAT_WRITE_BACK: 703196726Sadrian pat_index = 0; 704196726Sadrian break; 705196726Sadrian case PAT_WRITE_COMBINING: 706196726Sadrian pat_index = 2; 707196726Sadrian break; 708196726Sadrian default: 709196726Sadrian panic("Unknown caching mode %d\n", mode); 710196726Sadrian } 711181641Skmacy } 712181641Skmacy 713181641Skmacy /* Map the 3-bit index value into the PAT, PCD, and PWT bits. */ 714181641Skmacy cache_bits = 0; 715181641Skmacy if (pat_index & 0x4) 716181641Skmacy cache_bits |= pat_flag; 717181641Skmacy if (pat_index & 0x2) 718181641Skmacy cache_bits |= PG_NC_PCD; 719181641Skmacy if (pat_index & 0x1) 720181641Skmacy cache_bits |= PG_NC_PWT; 721181641Skmacy return (cache_bits); 722181641Skmacy} 723181641Skmacy#ifdef SMP 724181641Skmacy/* 725181641Skmacy * For SMP, these functions have to use the IPI mechanism for coherence. 726181641Skmacy * 727181641Skmacy * N.B.: Before calling any of the following TLB invalidation functions, 728181641Skmacy * the calling processor must ensure that all stores updating a non- 729181641Skmacy * kernel page table are globally performed. Otherwise, another 730181641Skmacy * processor could cache an old, pre-update entry without being 731181641Skmacy * invalidated. This can happen one of two ways: (1) The pmap becomes 732181641Skmacy * active on another processor after its pm_active field is checked by 733181641Skmacy * one of the following functions but before a store updating the page 734181641Skmacy * table is globally performed. (2) The pmap becomes active on another 735181641Skmacy * processor before its pm_active field is checked but due to 736181641Skmacy * speculative loads one of the following functions stills reads the 737181641Skmacy * pmap as inactive on the other processor. 738181641Skmacy * 739181641Skmacy * The kernel page table is exempt because its pm_active field is 740181641Skmacy * immutable. The kernel page table is always active on every 741181641Skmacy * processor. 742181641Skmacy */ 743181641Skmacyvoid 744181641Skmacypmap_invalidate_page(pmap_t pmap, vm_offset_t va) 745181641Skmacy{ 746223758Sattilio cpuset_t other_cpus; 747223758Sattilio u_int cpuid; 748181641Skmacy 749181641Skmacy CTR2(KTR_PMAP, "pmap_invalidate_page: pmap=%p va=0x%x", 750181641Skmacy pmap, va); 751181641Skmacy 752181641Skmacy sched_pin(); 753222813Sattilio if (pmap == kernel_pmap || !CPU_CMP(&pmap->pm_active, &all_cpus)) { 754181641Skmacy invlpg(va); 755181641Skmacy smp_invlpg(va); 756181641Skmacy } else { 757223758Sattilio cpuid = PCPU_GET(cpuid); 758223758Sattilio other_cpus = all_cpus; 759223758Sattilio CPU_CLR(cpuid, &other_cpus); 760223758Sattilio if (CPU_ISSET(cpuid, &pmap->pm_active)) 761181641Skmacy invlpg(va); 762222813Sattilio CPU_AND(&other_cpus, &pmap->pm_active); 763222813Sattilio if (!CPU_EMPTY(&other_cpus)) 764222813Sattilio smp_masked_invlpg(other_cpus, va); 765181641Skmacy } 766181641Skmacy sched_unpin(); 767181641Skmacy PT_UPDATES_FLUSH(); 768181641Skmacy} 769181641Skmacy 770181641Skmacyvoid 771181641Skmacypmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 772181641Skmacy{ 773223758Sattilio cpuset_t other_cpus; 774181641Skmacy vm_offset_t addr; 775223758Sattilio u_int cpuid; 776181641Skmacy 777181641Skmacy CTR3(KTR_PMAP, "pmap_invalidate_page: pmap=%p eva=0x%x sva=0x%x", 778181641Skmacy pmap, sva, eva); 779181641Skmacy 780181641Skmacy sched_pin(); 781222813Sattilio if (pmap == kernel_pmap || !CPU_CMP(&pmap->pm_active, &all_cpus)) { 782181641Skmacy for (addr = sva; addr < eva; addr += PAGE_SIZE) 783181641Skmacy invlpg(addr); 784181641Skmacy smp_invlpg_range(sva, eva); 785181641Skmacy } else { 786223758Sattilio cpuid = PCPU_GET(cpuid); 787223758Sattilio other_cpus = all_cpus; 788223758Sattilio CPU_CLR(cpuid, &other_cpus); 789223758Sattilio if (CPU_ISSET(cpuid, &pmap->pm_active)) 790181641Skmacy for (addr = sva; addr < eva; addr += PAGE_SIZE) 791181641Skmacy invlpg(addr); 792222813Sattilio CPU_AND(&other_cpus, &pmap->pm_active); 793222813Sattilio if (!CPU_EMPTY(&other_cpus)) 794222813Sattilio smp_masked_invlpg_range(other_cpus, sva, eva); 795181641Skmacy } 796181641Skmacy sched_unpin(); 797181641Skmacy PT_UPDATES_FLUSH(); 798181641Skmacy} 799181641Skmacy 800181641Skmacyvoid 801181641Skmacypmap_invalidate_all(pmap_t pmap) 802181641Skmacy{ 803223758Sattilio cpuset_t other_cpus; 804223758Sattilio u_int cpuid; 805181641Skmacy 806181641Skmacy CTR1(KTR_PMAP, "pmap_invalidate_page: pmap=%p", pmap); 807181641Skmacy 808181641Skmacy sched_pin(); 809222813Sattilio if (pmap == kernel_pmap || !CPU_CMP(&pmap->pm_active, &all_cpus)) { 810181641Skmacy invltlb(); 811181641Skmacy smp_invltlb(); 812181641Skmacy } else { 813223758Sattilio cpuid = PCPU_GET(cpuid); 814223758Sattilio other_cpus = all_cpus; 815223758Sattilio CPU_CLR(cpuid, &other_cpus); 816223758Sattilio if (CPU_ISSET(cpuid, &pmap->pm_active)) 817181641Skmacy invltlb(); 818222813Sattilio CPU_AND(&other_cpus, &pmap->pm_active); 819222813Sattilio if (!CPU_EMPTY(&other_cpus)) 820222813Sattilio smp_masked_invltlb(other_cpus); 821181641Skmacy } 822181641Skmacy sched_unpin(); 823181641Skmacy} 824181641Skmacy 825181641Skmacyvoid 826181641Skmacypmap_invalidate_cache(void) 827181641Skmacy{ 828181641Skmacy 829181641Skmacy sched_pin(); 830181641Skmacy wbinvd(); 831181641Skmacy smp_cache_flush(); 832181641Skmacy sched_unpin(); 833181641Skmacy} 834181641Skmacy#else /* !SMP */ 835181641Skmacy/* 836181641Skmacy * Normal, non-SMP, 486+ invalidation functions. 837181641Skmacy * We inline these within pmap.c for speed. 838181641Skmacy */ 839181641SkmacyPMAP_INLINE void 840181641Skmacypmap_invalidate_page(pmap_t pmap, vm_offset_t va) 841181641Skmacy{ 842181641Skmacy CTR2(KTR_PMAP, "pmap_invalidate_page: pmap=%p va=0x%x", 843181641Skmacy pmap, va); 844181641Skmacy 845222813Sattilio if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active)) 846181641Skmacy invlpg(va); 847181641Skmacy PT_UPDATES_FLUSH(); 848181641Skmacy} 849181641Skmacy 850181641SkmacyPMAP_INLINE void 851181641Skmacypmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 852181641Skmacy{ 853181641Skmacy vm_offset_t addr; 854181641Skmacy 855181641Skmacy if (eva - sva > PAGE_SIZE) 856181641Skmacy CTR3(KTR_PMAP, "pmap_invalidate_range: pmap=%p sva=0x%x eva=0x%x", 857181641Skmacy pmap, sva, eva); 858181641Skmacy 859222813Sattilio if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active)) 860181641Skmacy for (addr = sva; addr < eva; addr += PAGE_SIZE) 861181641Skmacy invlpg(addr); 862181641Skmacy PT_UPDATES_FLUSH(); 863181641Skmacy} 864181641Skmacy 865181641SkmacyPMAP_INLINE void 866181641Skmacypmap_invalidate_all(pmap_t pmap) 867181641Skmacy{ 868181641Skmacy 869181641Skmacy CTR1(KTR_PMAP, "pmap_invalidate_all: pmap=%p", pmap); 870181641Skmacy 871222813Sattilio if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active)) 872181641Skmacy invltlb(); 873181641Skmacy} 874181641Skmacy 875181641SkmacyPMAP_INLINE void 876181641Skmacypmap_invalidate_cache(void) 877181641Skmacy{ 878181641Skmacy 879181641Skmacy wbinvd(); 880181641Skmacy} 881181641Skmacy#endif /* !SMP */ 882181641Skmacy 883230435Salc#define PMAP_CLFLUSH_THRESHOLD (2 * 1024 * 1024) 884230435Salc 885195949Skibvoid 886195949Skibpmap_invalidate_cache_range(vm_offset_t sva, vm_offset_t eva) 887195949Skib{ 888195949Skib 889195949Skib KASSERT((sva & PAGE_MASK) == 0, 890195949Skib ("pmap_invalidate_cache_range: sva not page-aligned")); 891195949Skib KASSERT((eva & PAGE_MASK) == 0, 892195949Skib ("pmap_invalidate_cache_range: eva not page-aligned")); 893195949Skib 894195949Skib if (cpu_feature & CPUID_SS) 895195949Skib ; /* If "Self Snoop" is supported, do nothing. */ 896230435Salc else if ((cpu_feature & CPUID_CLFSH) != 0 && 897230435Salc eva - sva < PMAP_CLFLUSH_THRESHOLD) { 898195949Skib 899195949Skib /* 900195949Skib * Otherwise, do per-cache line flush. Use the mfence 901195949Skib * instruction to insure that previous stores are 902195949Skib * included in the write-back. The processor 903195949Skib * propagates flush to other processors in the cache 904195949Skib * coherence domain. 905195949Skib */ 906195949Skib mfence(); 907197046Skib for (; sva < eva; sva += cpu_clflush_line_size) 908197046Skib clflush(sva); 909195949Skib mfence(); 910195949Skib } else { 911195949Skib 912195949Skib /* 913195949Skib * No targeted cache flush methods are supported by CPU, 914230435Salc * or the supplied range is bigger than 2MB. 915230435Salc * Globally invalidate cache. 916195949Skib */ 917195949Skib pmap_invalidate_cache(); 918195949Skib } 919195949Skib} 920195949Skib 921230435Salcvoid 922230435Salcpmap_invalidate_cache_pages(vm_page_t *pages, int count) 923230435Salc{ 924230435Salc int i; 925230435Salc 926230435Salc if (count >= PMAP_CLFLUSH_THRESHOLD / PAGE_SIZE || 927230435Salc (cpu_feature & CPUID_CLFSH) == 0) { 928230435Salc pmap_invalidate_cache(); 929230435Salc } else { 930230435Salc for (i = 0; i < count; i++) 931230435Salc pmap_flush_page(pages[i]); 932230435Salc } 933230435Salc} 934230435Salc 935181641Skmacy/* 936181641Skmacy * Are we current address space or kernel? N.B. We return FALSE when 937181641Skmacy * a pmap's page table is in use because a kernel thread is borrowing 938181641Skmacy * it. The borrowed page table can change spontaneously, making any 939181641Skmacy * dependence on its continued use subject to a race condition. 940181641Skmacy */ 941181641Skmacystatic __inline int 942181641Skmacypmap_is_current(pmap_t pmap) 943181641Skmacy{ 944181641Skmacy 945181641Skmacy return (pmap == kernel_pmap || 946181641Skmacy (pmap == vmspace_pmap(curthread->td_proc->p_vmspace) && 947230435Salc (pmap->pm_pdir[PTDPTDI] & PG_FRAME) == (PTDpde[0] & PG_FRAME))); 948181641Skmacy} 949181641Skmacy 950181641Skmacy/* 951181641Skmacy * If the given pmap is not the current or kernel pmap, the returned pte must 952181641Skmacy * be released by passing it to pmap_pte_release(). 953181641Skmacy */ 954181641Skmacypt_entry_t * 955181641Skmacypmap_pte(pmap_t pmap, vm_offset_t va) 956181641Skmacy{ 957181641Skmacy pd_entry_t newpf; 958181641Skmacy pd_entry_t *pde; 959181641Skmacy 960181641Skmacy pde = pmap_pde(pmap, va); 961181641Skmacy if (*pde & PG_PS) 962181641Skmacy return (pde); 963181641Skmacy if (*pde != 0) { 964181641Skmacy /* are we current address space or kernel? */ 965181641Skmacy if (pmap_is_current(pmap)) 966181641Skmacy return (vtopte(va)); 967181641Skmacy mtx_lock(&PMAP2mutex); 968181641Skmacy newpf = *pde & PG_FRAME; 969181641Skmacy if ((*PMAP2 & PG_FRAME) != newpf) { 970204160Skmacy vm_page_lock_queues(); 971181641Skmacy PT_SET_MA(PADDR2, newpf | PG_V | PG_A | PG_M); 972204160Skmacy vm_page_unlock_queues(); 973181641Skmacy CTR3(KTR_PMAP, "pmap_pte: pmap=%p va=0x%x newpte=0x%08x", 974181641Skmacy pmap, va, (*PMAP2 & 0xffffffff)); 975181641Skmacy } 976181641Skmacy return (PADDR2 + (i386_btop(va) & (NPTEPG - 1))); 977181641Skmacy } 978230435Salc return (NULL); 979181641Skmacy} 980181641Skmacy 981181641Skmacy/* 982181641Skmacy * Releases a pte that was obtained from pmap_pte(). Be prepared for the pte 983181641Skmacy * being NULL. 984181641Skmacy */ 985181641Skmacystatic __inline void 986181641Skmacypmap_pte_release(pt_entry_t *pte) 987181641Skmacy{ 988181641Skmacy 989181641Skmacy if ((pt_entry_t *)((vm_offset_t)pte & ~PAGE_MASK) == PADDR2) { 990181641Skmacy CTR1(KTR_PMAP, "pmap_pte_release: pte=0x%jx", 991181641Skmacy *PMAP2); 992216703Scperciva vm_page_lock_queues(); 993181641Skmacy PT_SET_VA(PMAP2, 0, TRUE); 994216703Scperciva vm_page_unlock_queues(); 995181641Skmacy mtx_unlock(&PMAP2mutex); 996181641Skmacy } 997181641Skmacy} 998181641Skmacy 999181641Skmacystatic __inline void 1000181641Skmacyinvlcaddr(void *caddr) 1001181641Skmacy{ 1002181641Skmacy 1003181641Skmacy invlpg((u_int)caddr); 1004181641Skmacy PT_UPDATES_FLUSH(); 1005181641Skmacy} 1006181641Skmacy 1007181641Skmacy/* 1008181641Skmacy * Super fast pmap_pte routine best used when scanning 1009181641Skmacy * the pv lists. This eliminates many coarse-grained 1010181641Skmacy * invltlb calls. Note that many of the pv list 1011181641Skmacy * scans are across different pmaps. It is very wasteful 1012181641Skmacy * to do an entire invltlb for checking a single mapping. 1013181641Skmacy * 1014181641Skmacy * If the given pmap is not the current pmap, vm_page_queue_mtx 1015181641Skmacy * must be held and curthread pinned to a CPU. 1016181641Skmacy */ 1017181641Skmacystatic pt_entry_t * 1018181641Skmacypmap_pte_quick(pmap_t pmap, vm_offset_t va) 1019181641Skmacy{ 1020181641Skmacy pd_entry_t newpf; 1021181641Skmacy pd_entry_t *pde; 1022181641Skmacy 1023181641Skmacy pde = pmap_pde(pmap, va); 1024181641Skmacy if (*pde & PG_PS) 1025181641Skmacy return (pde); 1026181641Skmacy if (*pde != 0) { 1027181641Skmacy /* are we current address space or kernel? */ 1028181641Skmacy if (pmap_is_current(pmap)) 1029181641Skmacy return (vtopte(va)); 1030181641Skmacy mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1031181641Skmacy KASSERT(curthread->td_pinned > 0, ("curthread not pinned")); 1032181641Skmacy newpf = *pde & PG_FRAME; 1033181641Skmacy if ((*PMAP1 & PG_FRAME) != newpf) { 1034181641Skmacy PT_SET_MA(PADDR1, newpf | PG_V | PG_A | PG_M); 1035181641Skmacy CTR3(KTR_PMAP, "pmap_pte_quick: pmap=%p va=0x%x newpte=0x%08x", 1036181641Skmacy pmap, va, (u_long)*PMAP1); 1037181641Skmacy 1038181641Skmacy#ifdef SMP 1039181641Skmacy PMAP1cpu = PCPU_GET(cpuid); 1040181641Skmacy#endif 1041181641Skmacy PMAP1changed++; 1042181641Skmacy } else 1043181641Skmacy#ifdef SMP 1044181641Skmacy if (PMAP1cpu != PCPU_GET(cpuid)) { 1045181641Skmacy PMAP1cpu = PCPU_GET(cpuid); 1046181641Skmacy invlcaddr(PADDR1); 1047181641Skmacy PMAP1changedcpu++; 1048181641Skmacy } else 1049181641Skmacy#endif 1050181641Skmacy PMAP1unchanged++; 1051181641Skmacy return (PADDR1 + (i386_btop(va) & (NPTEPG - 1))); 1052181641Skmacy } 1053181641Skmacy return (0); 1054181641Skmacy} 1055181641Skmacy 1056181641Skmacy/* 1057181641Skmacy * Routine: pmap_extract 1058181641Skmacy * Function: 1059181641Skmacy * Extract the physical page address associated 1060181641Skmacy * with the given map/virtual_address pair. 1061181641Skmacy */ 1062181641Skmacyvm_paddr_t 1063181641Skmacypmap_extract(pmap_t pmap, vm_offset_t va) 1064181641Skmacy{ 1065181641Skmacy vm_paddr_t rtval; 1066181641Skmacy pt_entry_t *pte; 1067181641Skmacy pd_entry_t pde; 1068181641Skmacy pt_entry_t pteval; 1069230435Salc 1070181641Skmacy rtval = 0; 1071181641Skmacy PMAP_LOCK(pmap); 1072181641Skmacy pde = pmap->pm_pdir[va >> PDRSHIFT]; 1073181641Skmacy if (pde != 0) { 1074181641Skmacy if ((pde & PG_PS) != 0) { 1075181641Skmacy rtval = xpmap_mtop(pde & PG_PS_FRAME) | (va & PDRMASK); 1076181641Skmacy PMAP_UNLOCK(pmap); 1077181641Skmacy return rtval; 1078181641Skmacy } 1079181641Skmacy pte = pmap_pte(pmap, va); 1080181641Skmacy pteval = *pte ? xpmap_mtop(*pte) : 0; 1081181641Skmacy rtval = (pteval & PG_FRAME) | (va & PAGE_MASK); 1082181641Skmacy pmap_pte_release(pte); 1083181641Skmacy } 1084181641Skmacy PMAP_UNLOCK(pmap); 1085181641Skmacy return (rtval); 1086181641Skmacy} 1087181641Skmacy 1088181641Skmacy/* 1089181641Skmacy * Routine: pmap_extract_ma 1090181641Skmacy * Function: 1091181641Skmacy * Like pmap_extract, but returns machine address 1092181641Skmacy */ 1093181641Skmacyvm_paddr_t 1094181641Skmacypmap_extract_ma(pmap_t pmap, vm_offset_t va) 1095181641Skmacy{ 1096181641Skmacy vm_paddr_t rtval; 1097181641Skmacy pt_entry_t *pte; 1098181641Skmacy pd_entry_t pde; 1099181641Skmacy 1100181641Skmacy rtval = 0; 1101181641Skmacy PMAP_LOCK(pmap); 1102181641Skmacy pde = pmap->pm_pdir[va >> PDRSHIFT]; 1103181641Skmacy if (pde != 0) { 1104181641Skmacy if ((pde & PG_PS) != 0) { 1105181641Skmacy rtval = (pde & ~PDRMASK) | (va & PDRMASK); 1106181641Skmacy PMAP_UNLOCK(pmap); 1107181641Skmacy return rtval; 1108181641Skmacy } 1109181641Skmacy pte = pmap_pte(pmap, va); 1110181641Skmacy rtval = (*pte & PG_FRAME) | (va & PAGE_MASK); 1111181641Skmacy pmap_pte_release(pte); 1112181641Skmacy } 1113181641Skmacy PMAP_UNLOCK(pmap); 1114181641Skmacy return (rtval); 1115181641Skmacy} 1116181641Skmacy 1117181641Skmacy/* 1118181641Skmacy * Routine: pmap_extract_and_hold 1119181641Skmacy * Function: 1120181641Skmacy * Atomically extract and hold the physical page 1121181641Skmacy * with the given pmap and virtual address pair 1122181641Skmacy * if that mapping permits the given protection. 1123181641Skmacy */ 1124181641Skmacyvm_page_t 1125181641Skmacypmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot) 1126181641Skmacy{ 1127181641Skmacy pd_entry_t pde; 1128230435Salc pt_entry_t pte, *ptep; 1129181641Skmacy vm_page_t m; 1130207410Skmacy vm_paddr_t pa; 1131181641Skmacy 1132207410Skmacy pa = 0; 1133181641Skmacy m = NULL; 1134181641Skmacy PMAP_LOCK(pmap); 1135207410Skmacyretry: 1136181641Skmacy pde = PT_GET(pmap_pde(pmap, va)); 1137181641Skmacy if (pde != 0) { 1138181641Skmacy if (pde & PG_PS) { 1139181641Skmacy if ((pde & PG_RW) || (prot & VM_PROT_WRITE) == 0) { 1140230435Salc if (vm_page_pa_tryrelock(pmap, (pde & 1141230435Salc PG_PS_FRAME) | (va & PDRMASK), &pa)) 1142207410Skmacy goto retry; 1143181641Skmacy m = PHYS_TO_VM_PAGE((pde & PG_PS_FRAME) | 1144181641Skmacy (va & PDRMASK)); 1145181641Skmacy vm_page_hold(m); 1146181641Skmacy } 1147181641Skmacy } else { 1148230435Salc ptep = pmap_pte(pmap, va); 1149230435Salc pte = PT_GET(ptep); 1150230435Salc pmap_pte_release(ptep); 1151230435Salc if (pte != 0 && 1152181641Skmacy ((pte & PG_RW) || (prot & VM_PROT_WRITE) == 0)) { 1153230435Salc if (vm_page_pa_tryrelock(pmap, pte & PG_FRAME, 1154230435Salc &pa)) 1155207410Skmacy goto retry; 1156181641Skmacy m = PHYS_TO_VM_PAGE(pte & PG_FRAME); 1157181641Skmacy vm_page_hold(m); 1158181641Skmacy } 1159181641Skmacy } 1160181641Skmacy } 1161207410Skmacy PA_UNLOCK_COND(pa); 1162181641Skmacy PMAP_UNLOCK(pmap); 1163181641Skmacy return (m); 1164181641Skmacy} 1165181641Skmacy 1166181641Skmacy/*************************************************** 1167181641Skmacy * Low level mapping routines..... 1168181641Skmacy ***************************************************/ 1169181641Skmacy 1170181641Skmacy/* 1171181641Skmacy * Add a wired page to the kva. 1172181641Skmacy * Note: not SMP coherent. 1173230435Salc * 1174230435Salc * This function may be used before pmap_bootstrap() is called. 1175181641Skmacy */ 1176181747Skmacyvoid 1177181641Skmacypmap_kenter(vm_offset_t va, vm_paddr_t pa) 1178181641Skmacy{ 1179230435Salc 1180181641Skmacy PT_SET_MA(va, xpmap_ptom(pa)| PG_RW | PG_V | pgeflag); 1181181641Skmacy} 1182181641Skmacy 1183181747Skmacyvoid 1184181641Skmacypmap_kenter_ma(vm_offset_t va, vm_paddr_t ma) 1185181641Skmacy{ 1186181641Skmacy pt_entry_t *pte; 1187181641Skmacy 1188181641Skmacy pte = vtopte(va); 1189181641Skmacy pte_store_ma(pte, ma | PG_RW | PG_V | pgeflag); 1190181641Skmacy} 1191181641Skmacy 1192230435Salcstatic __inline void 1193181641Skmacypmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode) 1194181641Skmacy{ 1195230435Salc 1196181641Skmacy PT_SET_MA(va, pa | PG_RW | PG_V | pgeflag | pmap_cache_bits(mode, 0)); 1197181641Skmacy} 1198181641Skmacy 1199181641Skmacy/* 1200181641Skmacy * Remove a page from the kernel pagetables. 1201181641Skmacy * Note: not SMP coherent. 1202230435Salc * 1203230435Salc * This function may be used before pmap_bootstrap() is called. 1204181641Skmacy */ 1205181641SkmacyPMAP_INLINE void 1206181641Skmacypmap_kremove(vm_offset_t va) 1207181641Skmacy{ 1208181641Skmacy pt_entry_t *pte; 1209181641Skmacy 1210181641Skmacy pte = vtopte(va); 1211181641Skmacy PT_CLEAR_VA(pte, FALSE); 1212181641Skmacy} 1213181641Skmacy 1214181641Skmacy/* 1215181641Skmacy * Used to map a range of physical addresses into kernel 1216181641Skmacy * virtual address space. 1217181641Skmacy * 1218181641Skmacy * The value passed in '*virt' is a suggested virtual address for 1219181641Skmacy * the mapping. Architectures which can support a direct-mapped 1220181641Skmacy * physical to virtual region can return the appropriate address 1221181641Skmacy * within that region, leaving '*virt' unchanged. Other 1222181641Skmacy * architectures should map the pages starting at '*virt' and 1223181641Skmacy * update '*virt' with the first usable address after the mapped 1224181641Skmacy * region. 1225181641Skmacy */ 1226181641Skmacyvm_offset_t 1227181641Skmacypmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot) 1228181641Skmacy{ 1229181641Skmacy vm_offset_t va, sva; 1230181641Skmacy 1231181641Skmacy va = sva = *virt; 1232181641Skmacy CTR4(KTR_PMAP, "pmap_map: va=0x%x start=0x%jx end=0x%jx prot=0x%x", 1233181641Skmacy va, start, end, prot); 1234181641Skmacy while (start < end) { 1235181641Skmacy pmap_kenter(va, start); 1236181641Skmacy va += PAGE_SIZE; 1237181641Skmacy start += PAGE_SIZE; 1238181641Skmacy } 1239181641Skmacy pmap_invalidate_range(kernel_pmap, sva, va); 1240181641Skmacy *virt = va; 1241181641Skmacy return (sva); 1242181641Skmacy} 1243181641Skmacy 1244181641Skmacy 1245181641Skmacy/* 1246181641Skmacy * Add a list of wired pages to the kva 1247181641Skmacy * this routine is only used for temporary 1248181641Skmacy * kernel mappings that do not need to have 1249181641Skmacy * page modification or references recorded. 1250181641Skmacy * Note that old mappings are simply written 1251181641Skmacy * over. The page *must* be wired. 1252181641Skmacy * Note: SMP coherent. Uses a ranged shootdown IPI. 1253181641Skmacy */ 1254181641Skmacyvoid 1255181641Skmacypmap_qenter(vm_offset_t sva, vm_page_t *ma, int count) 1256181641Skmacy{ 1257181641Skmacy pt_entry_t *endpte, *pte; 1258181641Skmacy vm_paddr_t pa; 1259181641Skmacy vm_offset_t va = sva; 1260181641Skmacy int mclcount = 0; 1261181641Skmacy multicall_entry_t mcl[16]; 1262181641Skmacy multicall_entry_t *mclp = mcl; 1263181641Skmacy int error; 1264181641Skmacy 1265181641Skmacy CTR2(KTR_PMAP, "pmap_qenter:sva=0x%x count=%d", va, count); 1266181641Skmacy pte = vtopte(sva); 1267181641Skmacy endpte = pte + count; 1268181641Skmacy while (pte < endpte) { 1269215587Scperciva pa = VM_PAGE_TO_MACH(*ma) | pgeflag | PG_RW | PG_V | PG_M | PG_A; 1270181641Skmacy 1271181641Skmacy mclp->op = __HYPERVISOR_update_va_mapping; 1272181641Skmacy mclp->args[0] = va; 1273181641Skmacy mclp->args[1] = (uint32_t)(pa & 0xffffffff); 1274181641Skmacy mclp->args[2] = (uint32_t)(pa >> 32); 1275181641Skmacy mclp->args[3] = (*pte & PG_V) ? UVMF_INVLPG|UVMF_ALL : 0; 1276181641Skmacy 1277181641Skmacy va += PAGE_SIZE; 1278181641Skmacy pte++; 1279181641Skmacy ma++; 1280181641Skmacy mclp++; 1281181641Skmacy mclcount++; 1282181641Skmacy if (mclcount == 16) { 1283181641Skmacy error = HYPERVISOR_multicall(mcl, mclcount); 1284181641Skmacy mclp = mcl; 1285181641Skmacy mclcount = 0; 1286181641Skmacy KASSERT(error == 0, ("bad multicall %d", error)); 1287181641Skmacy } 1288181641Skmacy } 1289181641Skmacy if (mclcount) { 1290181641Skmacy error = HYPERVISOR_multicall(mcl, mclcount); 1291181641Skmacy KASSERT(error == 0, ("bad multicall %d", error)); 1292181641Skmacy } 1293181641Skmacy 1294181641Skmacy#ifdef INVARIANTS 1295181641Skmacy for (pte = vtopte(sva), mclcount = 0; mclcount < count; mclcount++, pte++) 1296181641Skmacy KASSERT(*pte, ("pte not set for va=0x%x", sva + mclcount*PAGE_SIZE)); 1297181641Skmacy#endif 1298181641Skmacy} 1299181641Skmacy 1300181641Skmacy/* 1301181641Skmacy * This routine tears out page mappings from the 1302181641Skmacy * kernel -- it is meant only for temporary mappings. 1303181641Skmacy * Note: SMP coherent. Uses a ranged shootdown IPI. 1304181641Skmacy */ 1305181641Skmacyvoid 1306181641Skmacypmap_qremove(vm_offset_t sva, int count) 1307181641Skmacy{ 1308181641Skmacy vm_offset_t va; 1309181641Skmacy 1310181641Skmacy CTR2(KTR_PMAP, "pmap_qremove: sva=0x%x count=%d", sva, count); 1311181641Skmacy va = sva; 1312181641Skmacy vm_page_lock_queues(); 1313181641Skmacy critical_enter(); 1314181641Skmacy while (count-- > 0) { 1315181641Skmacy pmap_kremove(va); 1316181641Skmacy va += PAGE_SIZE; 1317181641Skmacy } 1318215844Scperciva PT_UPDATES_FLUSH(); 1319181641Skmacy pmap_invalidate_range(kernel_pmap, sva, va); 1320181641Skmacy critical_exit(); 1321181641Skmacy vm_page_unlock_queues(); 1322181641Skmacy} 1323181641Skmacy 1324181641Skmacy/*************************************************** 1325181641Skmacy * Page table page management routines..... 1326181641Skmacy ***************************************************/ 1327181641Skmacystatic __inline void 1328181641Skmacypmap_free_zero_pages(vm_page_t free) 1329181641Skmacy{ 1330181641Skmacy vm_page_t m; 1331181641Skmacy 1332181641Skmacy while (free != NULL) { 1333181641Skmacy m = free; 1334181641Skmacy free = m->right; 1335181641Skmacy vm_page_free_zero(m); 1336181641Skmacy } 1337181641Skmacy} 1338181641Skmacy 1339181641Skmacy/* 1340240151Skib * Decrements a page table page's wire count, which is used to record the 1341240151Skib * number of valid page table entries within the page. If the wire count 1342240151Skib * drops to zero, then the page table page is unmapped. Returns TRUE if the 1343240151Skib * page table page was unmapped and FALSE otherwise. 1344181641Skmacy */ 1345240151Skibstatic inline boolean_t 1346240151Skibpmap_unwire_ptp(pmap_t pmap, vm_page_t m, vm_page_t *free) 1347181641Skmacy{ 1348181641Skmacy 1349181641Skmacy --m->wire_count; 1350240151Skib if (m->wire_count == 0) { 1351240151Skib _pmap_unwire_ptp(pmap, m, free); 1352240151Skib return (TRUE); 1353240151Skib } else 1354240151Skib return (FALSE); 1355181641Skmacy} 1356181641Skmacy 1357240151Skibstatic void 1358240151Skib_pmap_unwire_ptp(pmap_t pmap, vm_page_t m, vm_page_t *free) 1359181641Skmacy{ 1360181641Skmacy vm_offset_t pteva; 1361181641Skmacy 1362181641Skmacy PT_UPDATES_FLUSH(); 1363181641Skmacy /* 1364181641Skmacy * unmap the page table page 1365181641Skmacy */ 1366181641Skmacy xen_pt_unpin(pmap->pm_pdir[m->pindex]); 1367181641Skmacy /* 1368181641Skmacy * page *might* contain residual mapping :-/ 1369181641Skmacy */ 1370181641Skmacy PD_CLEAR_VA(pmap, m->pindex, TRUE); 1371181641Skmacy pmap_zero_page(m); 1372181641Skmacy --pmap->pm_stats.resident_count; 1373181641Skmacy 1374181641Skmacy /* 1375181641Skmacy * This is a release store so that the ordinary store unmapping 1376181641Skmacy * the page table page is globally performed before TLB shoot- 1377181641Skmacy * down is begun. 1378181641Skmacy */ 1379181641Skmacy atomic_subtract_rel_int(&cnt.v_wire_count, 1); 1380181641Skmacy 1381181641Skmacy /* 1382181641Skmacy * Do an invltlb to make the invalidated mapping 1383181641Skmacy * take effect immediately. 1384181641Skmacy */ 1385181641Skmacy pteva = VM_MAXUSER_ADDRESS + i386_ptob(m->pindex); 1386181641Skmacy pmap_invalidate_page(pmap, pteva); 1387181641Skmacy 1388181641Skmacy /* 1389181641Skmacy * Put page on a list so that it is released after 1390181641Skmacy * *ALL* TLB shootdown is done 1391181641Skmacy */ 1392181641Skmacy m->right = *free; 1393181641Skmacy *free = m; 1394181641Skmacy} 1395181641Skmacy 1396181641Skmacy/* 1397181641Skmacy * After removing a page table entry, this routine is used to 1398181641Skmacy * conditionally free the page, and manage the hold/wire counts. 1399181641Skmacy */ 1400181641Skmacystatic int 1401181641Skmacypmap_unuse_pt(pmap_t pmap, vm_offset_t va, vm_page_t *free) 1402181641Skmacy{ 1403181641Skmacy pd_entry_t ptepde; 1404181641Skmacy vm_page_t mpte; 1405181641Skmacy 1406181641Skmacy if (va >= VM_MAXUSER_ADDRESS) 1407230435Salc return (0); 1408181641Skmacy ptepde = PT_GET(pmap_pde(pmap, va)); 1409181641Skmacy mpte = PHYS_TO_VM_PAGE(ptepde & PG_FRAME); 1410240151Skib return (pmap_unwire_ptp(pmap, mpte, free)); 1411181641Skmacy} 1412181641Skmacy 1413230435Salc/* 1414230435Salc * Initialize the pmap for the swapper process. 1415230435Salc */ 1416181641Skmacyvoid 1417181641Skmacypmap_pinit0(pmap_t pmap) 1418181641Skmacy{ 1419181641Skmacy 1420181641Skmacy PMAP_LOCK_INIT(pmap); 1421230435Salc /* 1422230435Salc * Since the page table directory is shared with the kernel pmap, 1423230435Salc * which is already included in the list "allpmaps", this pmap does 1424230435Salc * not need to be inserted into that list. 1425230435Salc */ 1426181641Skmacy pmap->pm_pdir = (pd_entry_t *)(KERNBASE + (vm_offset_t)IdlePTD); 1427181641Skmacy#ifdef PAE 1428181641Skmacy pmap->pm_pdpt = (pdpt_entry_t *)(KERNBASE + (vm_offset_t)IdlePDPT); 1429181641Skmacy#endif 1430222813Sattilio CPU_ZERO(&pmap->pm_active); 1431181641Skmacy PCPU_SET(curpmap, pmap); 1432181641Skmacy TAILQ_INIT(&pmap->pm_pvchunk); 1433181641Skmacy bzero(&pmap->pm_stats, sizeof pmap->pm_stats); 1434181641Skmacy} 1435181641Skmacy 1436181641Skmacy/* 1437181641Skmacy * Initialize a preallocated and zeroed pmap structure, 1438181641Skmacy * such as one in a vmspace structure. 1439181641Skmacy */ 1440181641Skmacyint 1441181641Skmacypmap_pinit(pmap_t pmap) 1442181641Skmacy{ 1443181641Skmacy vm_page_t m, ptdpg[NPGPTD + 1]; 1444181641Skmacy int npgptd = NPGPTD + 1; 1445181641Skmacy int i; 1446181641Skmacy 1447216960Scperciva#ifdef HAMFISTED_LOCKING 1448216960Scperciva mtx_lock(&createdelete_lock); 1449216960Scperciva#endif 1450216960Scperciva 1451181641Skmacy PMAP_LOCK_INIT(pmap); 1452181641Skmacy 1453181641Skmacy /* 1454181641Skmacy * No need to allocate page table space yet but we do need a valid 1455181641Skmacy * page directory table. 1456181641Skmacy */ 1457181641Skmacy if (pmap->pm_pdir == NULL) { 1458181641Skmacy pmap->pm_pdir = (pd_entry_t *)kmem_alloc_nofault(kernel_map, 1459181641Skmacy NBPTD); 1460181641Skmacy if (pmap->pm_pdir == NULL) { 1461181641Skmacy PMAP_LOCK_DESTROY(pmap); 1462216960Scperciva#ifdef HAMFISTED_LOCKING 1463216960Scperciva mtx_unlock(&createdelete_lock); 1464216960Scperciva#endif 1465181641Skmacy return (0); 1466181641Skmacy } 1467215593Scperciva#ifdef PAE 1468181641Skmacy pmap->pm_pdpt = (pd_entry_t *)kmem_alloc_nofault(kernel_map, 1); 1469181641Skmacy#endif 1470181641Skmacy } 1471181641Skmacy 1472181641Skmacy /* 1473181641Skmacy * allocate the page directory page(s) 1474181641Skmacy */ 1475181641Skmacy for (i = 0; i < npgptd;) { 1476237949Salc m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ | 1477237949Salc VM_ALLOC_WIRED | VM_ALLOC_ZERO); 1478181641Skmacy if (m == NULL) 1479181641Skmacy VM_WAIT; 1480181641Skmacy else { 1481181641Skmacy ptdpg[i++] = m; 1482181641Skmacy } 1483181641Skmacy } 1484230435Salc 1485181641Skmacy pmap_qenter((vm_offset_t)pmap->pm_pdir, ptdpg, NPGPTD); 1486230435Salc 1487230435Salc for (i = 0; i < NPGPTD; i++) 1488181641Skmacy if ((ptdpg[i]->flags & PG_ZERO) == 0) 1489230435Salc pagezero(pmap->pm_pdir + (i * NPDEPG)); 1490181641Skmacy 1491181641Skmacy mtx_lock_spin(&allpmaps_lock); 1492181641Skmacy LIST_INSERT_HEAD(&allpmaps, pmap, pm_list); 1493230435Salc /* Copy the kernel page table directory entries. */ 1494230435Salc bcopy(PTD + KPTDI, pmap->pm_pdir + KPTDI, nkpt * sizeof(pd_entry_t)); 1495181641Skmacy mtx_unlock_spin(&allpmaps_lock); 1496181641Skmacy 1497181641Skmacy#ifdef PAE 1498181641Skmacy pmap_qenter((vm_offset_t)pmap->pm_pdpt, &ptdpg[NPGPTD], 1); 1499181641Skmacy if ((ptdpg[NPGPTD]->flags & PG_ZERO) == 0) 1500181641Skmacy bzero(pmap->pm_pdpt, PAGE_SIZE); 1501181641Skmacy for (i = 0; i < NPGPTD; i++) { 1502181641Skmacy vm_paddr_t ma; 1503181641Skmacy 1504215587Scperciva ma = VM_PAGE_TO_MACH(ptdpg[i]); 1505181641Skmacy pmap->pm_pdpt[i] = ma | PG_V; 1506181641Skmacy 1507181641Skmacy } 1508181641Skmacy#endif 1509181641Skmacy for (i = 0; i < NPGPTD; i++) { 1510181641Skmacy pt_entry_t *pd; 1511181641Skmacy vm_paddr_t ma; 1512181641Skmacy 1513215587Scperciva ma = VM_PAGE_TO_MACH(ptdpg[i]); 1514181641Skmacy pd = pmap->pm_pdir + (i * NPDEPG); 1515181641Skmacy PT_SET_MA(pd, *vtopte((vm_offset_t)pd) & ~(PG_M|PG_A|PG_U|PG_RW)); 1516181641Skmacy#if 0 1517181641Skmacy xen_pgd_pin(ma); 1518181641Skmacy#endif 1519181641Skmacy } 1520181641Skmacy 1521181641Skmacy#ifdef PAE 1522181641Skmacy PT_SET_MA(pmap->pm_pdpt, *vtopte((vm_offset_t)pmap->pm_pdpt) & ~PG_RW); 1523181641Skmacy#endif 1524181641Skmacy vm_page_lock_queues(); 1525181641Skmacy xen_flush_queue(); 1526215587Scperciva xen_pgdpt_pin(VM_PAGE_TO_MACH(ptdpg[NPGPTD])); 1527181641Skmacy for (i = 0; i < NPGPTD; i++) { 1528215587Scperciva vm_paddr_t ma = VM_PAGE_TO_MACH(ptdpg[i]); 1529181641Skmacy PT_SET_VA_MA(&pmap->pm_pdir[PTDPTDI + i], ma | PG_V | PG_A, FALSE); 1530181641Skmacy } 1531181641Skmacy xen_flush_queue(); 1532181641Skmacy vm_page_unlock_queues(); 1533222813Sattilio CPU_ZERO(&pmap->pm_active); 1534181641Skmacy TAILQ_INIT(&pmap->pm_pvchunk); 1535181641Skmacy bzero(&pmap->pm_stats, sizeof pmap->pm_stats); 1536181641Skmacy 1537216960Scperciva#ifdef HAMFISTED_LOCKING 1538216960Scperciva mtx_unlock(&createdelete_lock); 1539216960Scperciva#endif 1540181641Skmacy return (1); 1541181641Skmacy} 1542181641Skmacy 1543181641Skmacy/* 1544181641Skmacy * this routine is called if the page table page is not 1545181641Skmacy * mapped correctly. 1546181641Skmacy */ 1547181641Skmacystatic vm_page_t 1548230435Salc_pmap_allocpte(pmap_t pmap, u_int ptepindex, int flags) 1549181641Skmacy{ 1550181641Skmacy vm_paddr_t ptema; 1551181641Skmacy vm_page_t m; 1552181641Skmacy 1553181641Skmacy KASSERT((flags & (M_NOWAIT | M_WAITOK)) == M_NOWAIT || 1554181641Skmacy (flags & (M_NOWAIT | M_WAITOK)) == M_WAITOK, 1555181641Skmacy ("_pmap_allocpte: flags is neither M_NOWAIT nor M_WAITOK")); 1556181641Skmacy 1557181641Skmacy /* 1558181641Skmacy * Allocate a page table page. 1559181641Skmacy */ 1560181641Skmacy if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ | 1561181641Skmacy VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) { 1562181641Skmacy if (flags & M_WAITOK) { 1563181641Skmacy PMAP_UNLOCK(pmap); 1564181641Skmacy vm_page_unlock_queues(); 1565181641Skmacy VM_WAIT; 1566181641Skmacy vm_page_lock_queues(); 1567181641Skmacy PMAP_LOCK(pmap); 1568181641Skmacy } 1569181641Skmacy 1570181641Skmacy /* 1571181641Skmacy * Indicate the need to retry. While waiting, the page table 1572181641Skmacy * page may have been allocated. 1573181641Skmacy */ 1574181641Skmacy return (NULL); 1575181641Skmacy } 1576181641Skmacy if ((m->flags & PG_ZERO) == 0) 1577181641Skmacy pmap_zero_page(m); 1578181641Skmacy 1579181641Skmacy /* 1580181641Skmacy * Map the pagetable page into the process address space, if 1581181641Skmacy * it isn't already there. 1582181641Skmacy */ 1583230435Salc 1584181641Skmacy pmap->pm_stats.resident_count++; 1585181641Skmacy 1586215587Scperciva ptema = VM_PAGE_TO_MACH(m); 1587181641Skmacy xen_pt_pin(ptema); 1588181641Skmacy PT_SET_VA_MA(&pmap->pm_pdir[ptepindex], 1589181641Skmacy (ptema | PG_U | PG_RW | PG_V | PG_A | PG_M), TRUE); 1590181641Skmacy 1591181641Skmacy KASSERT(pmap->pm_pdir[ptepindex], 1592181641Skmacy ("_pmap_allocpte: ptepindex=%d did not get mapped", ptepindex)); 1593181641Skmacy return (m); 1594181641Skmacy} 1595181641Skmacy 1596181641Skmacystatic vm_page_t 1597181641Skmacypmap_allocpte(pmap_t pmap, vm_offset_t va, int flags) 1598181641Skmacy{ 1599230435Salc u_int ptepindex; 1600181641Skmacy pd_entry_t ptema; 1601181641Skmacy vm_page_t m; 1602181641Skmacy 1603181641Skmacy KASSERT((flags & (M_NOWAIT | M_WAITOK)) == M_NOWAIT || 1604181641Skmacy (flags & (M_NOWAIT | M_WAITOK)) == M_WAITOK, 1605181641Skmacy ("pmap_allocpte: flags is neither M_NOWAIT nor M_WAITOK")); 1606181641Skmacy 1607181641Skmacy /* 1608181641Skmacy * Calculate pagetable page index 1609181641Skmacy */ 1610181641Skmacy ptepindex = va >> PDRSHIFT; 1611181641Skmacyretry: 1612181641Skmacy /* 1613181641Skmacy * Get the page directory entry 1614181641Skmacy */ 1615181641Skmacy ptema = pmap->pm_pdir[ptepindex]; 1616181641Skmacy 1617181641Skmacy /* 1618181641Skmacy * This supports switching from a 4MB page to a 1619181641Skmacy * normal 4K page. 1620181641Skmacy */ 1621181641Skmacy if (ptema & PG_PS) { 1622181641Skmacy /* 1623181641Skmacy * XXX 1624181641Skmacy */ 1625181641Skmacy pmap->pm_pdir[ptepindex] = 0; 1626181641Skmacy ptema = 0; 1627181641Skmacy pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE; 1628181641Skmacy pmap_invalidate_all(kernel_pmap); 1629181641Skmacy } 1630181641Skmacy 1631181641Skmacy /* 1632181641Skmacy * If the page table page is mapped, we just increment the 1633181641Skmacy * hold count, and activate it. 1634181641Skmacy */ 1635181641Skmacy if (ptema & PG_V) { 1636181641Skmacy m = PHYS_TO_VM_PAGE(xpmap_mtop(ptema) & PG_FRAME); 1637181641Skmacy m->wire_count++; 1638181641Skmacy } else { 1639181641Skmacy /* 1640181641Skmacy * Here if the pte page isn't mapped, or if it has 1641181641Skmacy * been deallocated. 1642181641Skmacy */ 1643181641Skmacy CTR3(KTR_PMAP, "pmap_allocpte: pmap=%p va=0x%08x flags=0x%x", 1644181641Skmacy pmap, va, flags); 1645181641Skmacy m = _pmap_allocpte(pmap, ptepindex, flags); 1646181641Skmacy if (m == NULL && (flags & M_WAITOK)) 1647181641Skmacy goto retry; 1648181641Skmacy 1649181641Skmacy KASSERT(pmap->pm_pdir[ptepindex], ("ptepindex=%d did not get mapped", ptepindex)); 1650181641Skmacy } 1651181641Skmacy return (m); 1652181641Skmacy} 1653181641Skmacy 1654181641Skmacy 1655181641Skmacy/*************************************************** 1656181641Skmacy* Pmap allocation/deallocation routines. 1657181641Skmacy ***************************************************/ 1658181641Skmacy 1659181641Skmacy#ifdef SMP 1660181641Skmacy/* 1661181641Skmacy * Deal with a SMP shootdown of other users of the pmap that we are 1662181641Skmacy * trying to dispose of. This can be a bit hairy. 1663181641Skmacy */ 1664222813Sattiliostatic cpuset_t *lazymask; 1665181641Skmacystatic u_int lazyptd; 1666181641Skmacystatic volatile u_int lazywait; 1667181641Skmacy 1668181641Skmacyvoid pmap_lazyfix_action(void); 1669181641Skmacy 1670181641Skmacyvoid 1671181641Skmacypmap_lazyfix_action(void) 1672181641Skmacy{ 1673181641Skmacy 1674181641Skmacy#ifdef COUNT_IPIS 1675181641Skmacy (*ipi_lazypmap_counts[PCPU_GET(cpuid)])++; 1676181641Skmacy#endif 1677181641Skmacy if (rcr3() == lazyptd) 1678181641Skmacy load_cr3(PCPU_GET(curpcb)->pcb_cr3); 1679222813Sattilio CPU_CLR_ATOMIC(PCPU_GET(cpuid), lazymask); 1680181641Skmacy atomic_store_rel_int(&lazywait, 1); 1681181641Skmacy} 1682181641Skmacy 1683181641Skmacystatic void 1684223758Sattiliopmap_lazyfix_self(u_int cpuid) 1685181641Skmacy{ 1686181641Skmacy 1687181641Skmacy if (rcr3() == lazyptd) 1688181641Skmacy load_cr3(PCPU_GET(curpcb)->pcb_cr3); 1689223758Sattilio CPU_CLR_ATOMIC(cpuid, lazymask); 1690181641Skmacy} 1691181641Skmacy 1692181641Skmacy 1693181641Skmacystatic void 1694181641Skmacypmap_lazyfix(pmap_t pmap) 1695181641Skmacy{ 1696222813Sattilio cpuset_t mymask, mask; 1697223758Sattilio u_int cpuid, spins; 1698222813Sattilio int lsb; 1699181641Skmacy 1700222813Sattilio mask = pmap->pm_active; 1701222813Sattilio while (!CPU_EMPTY(&mask)) { 1702181641Skmacy spins = 50000000; 1703222813Sattilio 1704222813Sattilio /* Find least significant set bit. */ 1705256207Smav lsb = CPU_FFS(&mask); 1706222813Sattilio MPASS(lsb != 0); 1707222813Sattilio lsb--; 1708222813Sattilio CPU_SETOF(lsb, &mask); 1709181641Skmacy mtx_lock_spin(&smp_ipi_mtx); 1710181641Skmacy#ifdef PAE 1711181641Skmacy lazyptd = vtophys(pmap->pm_pdpt); 1712181641Skmacy#else 1713181641Skmacy lazyptd = vtophys(pmap->pm_pdir); 1714181641Skmacy#endif 1715223758Sattilio cpuid = PCPU_GET(cpuid); 1716223758Sattilio 1717223758Sattilio /* Use a cpuset just for having an easy check. */ 1718223758Sattilio CPU_SETOF(cpuid, &mymask); 1719222813Sattilio if (!CPU_CMP(&mask, &mymask)) { 1720181641Skmacy lazymask = &pmap->pm_active; 1721223758Sattilio pmap_lazyfix_self(cpuid); 1722181641Skmacy } else { 1723181641Skmacy atomic_store_rel_int((u_int *)&lazymask, 1724181641Skmacy (u_int)&pmap->pm_active); 1725181641Skmacy atomic_store_rel_int(&lazywait, 0); 1726181641Skmacy ipi_selected(mask, IPI_LAZYPMAP); 1727181641Skmacy while (lazywait == 0) { 1728181641Skmacy ia32_pause(); 1729181641Skmacy if (--spins == 0) 1730181641Skmacy break; 1731181641Skmacy } 1732181641Skmacy } 1733181641Skmacy mtx_unlock_spin(&smp_ipi_mtx); 1734181641Skmacy if (spins == 0) 1735181641Skmacy printf("pmap_lazyfix: spun for 50000000\n"); 1736222813Sattilio mask = pmap->pm_active; 1737181641Skmacy } 1738181641Skmacy} 1739181641Skmacy 1740181641Skmacy#else /* SMP */ 1741181641Skmacy 1742181641Skmacy/* 1743181641Skmacy * Cleaning up on uniprocessor is easy. For various reasons, we're 1744181641Skmacy * unlikely to have to even execute this code, including the fact 1745181641Skmacy * that the cleanup is deferred until the parent does a wait(2), which 1746181641Skmacy * means that another userland process has run. 1747181641Skmacy */ 1748181641Skmacystatic void 1749181641Skmacypmap_lazyfix(pmap_t pmap) 1750181641Skmacy{ 1751181641Skmacy u_int cr3; 1752181641Skmacy 1753181641Skmacy cr3 = vtophys(pmap->pm_pdir); 1754181641Skmacy if (cr3 == rcr3()) { 1755181641Skmacy load_cr3(PCPU_GET(curpcb)->pcb_cr3); 1756222813Sattilio CPU_CLR(PCPU_GET(cpuid), &pmap->pm_active); 1757181641Skmacy } 1758181641Skmacy} 1759181641Skmacy#endif /* SMP */ 1760181641Skmacy 1761181641Skmacy/* 1762181641Skmacy * Release any resources held by the given physical map. 1763181641Skmacy * Called when a pmap initialized by pmap_pinit is being released. 1764181641Skmacy * Should only be called if the map contains no valid mappings. 1765181641Skmacy */ 1766181641Skmacyvoid 1767181641Skmacypmap_release(pmap_t pmap) 1768181641Skmacy{ 1769181641Skmacy vm_page_t m, ptdpg[2*NPGPTD+1]; 1770181641Skmacy vm_paddr_t ma; 1771181641Skmacy int i; 1772181641Skmacy#ifdef PAE 1773181641Skmacy int npgptd = NPGPTD + 1; 1774181641Skmacy#else 1775181641Skmacy int npgptd = NPGPTD; 1776181641Skmacy#endif 1777230435Salc 1778181641Skmacy KASSERT(pmap->pm_stats.resident_count == 0, 1779181641Skmacy ("pmap_release: pmap resident count %ld != 0", 1780181641Skmacy pmap->pm_stats.resident_count)); 1781181641Skmacy PT_UPDATES_FLUSH(); 1782181641Skmacy 1783216960Scperciva#ifdef HAMFISTED_LOCKING 1784216960Scperciva mtx_lock(&createdelete_lock); 1785216960Scperciva#endif 1786216960Scperciva 1787181641Skmacy pmap_lazyfix(pmap); 1788181641Skmacy mtx_lock_spin(&allpmaps_lock); 1789181641Skmacy LIST_REMOVE(pmap, pm_list); 1790181641Skmacy mtx_unlock_spin(&allpmaps_lock); 1791181641Skmacy 1792181641Skmacy for (i = 0; i < NPGPTD; i++) 1793181641Skmacy ptdpg[i] = PHYS_TO_VM_PAGE(vtophys(pmap->pm_pdir + (i*NPDEPG)) & PG_FRAME); 1794181641Skmacy pmap_qremove((vm_offset_t)pmap->pm_pdir, NPGPTD); 1795215593Scperciva#ifdef PAE 1796181641Skmacy ptdpg[NPGPTD] = PHYS_TO_VM_PAGE(vtophys(pmap->pm_pdpt)); 1797181641Skmacy#endif 1798181641Skmacy 1799181641Skmacy for (i = 0; i < npgptd; i++) { 1800181641Skmacy m = ptdpg[i]; 1801215587Scperciva ma = VM_PAGE_TO_MACH(m); 1802181641Skmacy /* unpinning L1 and L2 treated the same */ 1803215525Scperciva#if 0 1804181641Skmacy xen_pgd_unpin(ma); 1805215525Scperciva#else 1806215525Scperciva if (i == NPGPTD) 1807215525Scperciva xen_pgd_unpin(ma); 1808215525Scperciva#endif 1809181641Skmacy#ifdef PAE 1810215470Scperciva if (i < NPGPTD) 1811215587Scperciva KASSERT(VM_PAGE_TO_MACH(m) == (pmap->pm_pdpt[i] & PG_FRAME), 1812215470Scperciva ("pmap_release: got wrong ptd page")); 1813181641Skmacy#endif 1814181641Skmacy m->wire_count--; 1815181641Skmacy atomic_subtract_int(&cnt.v_wire_count, 1); 1816181641Skmacy vm_page_free(m); 1817181641Skmacy } 1818215472Scperciva#ifdef PAE 1819215472Scperciva pmap_qremove((vm_offset_t)pmap->pm_pdpt, 1); 1820215472Scperciva#endif 1821181641Skmacy PMAP_LOCK_DESTROY(pmap); 1822216960Scperciva 1823216960Scperciva#ifdef HAMFISTED_LOCKING 1824216960Scperciva mtx_unlock(&createdelete_lock); 1825216960Scperciva#endif 1826181641Skmacy} 1827181641Skmacy 1828181641Skmacystatic int 1829181641Skmacykvm_size(SYSCTL_HANDLER_ARGS) 1830181641Skmacy{ 1831181641Skmacy unsigned long ksize = VM_MAX_KERNEL_ADDRESS - KERNBASE; 1832181641Skmacy 1833230435Salc return (sysctl_handle_long(oidp, &ksize, 0, req)); 1834181641Skmacy} 1835181641SkmacySYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG|CTLFLAG_RD, 1836181641Skmacy 0, 0, kvm_size, "IU", "Size of KVM"); 1837181641Skmacy 1838181641Skmacystatic int 1839181641Skmacykvm_free(SYSCTL_HANDLER_ARGS) 1840181641Skmacy{ 1841181641Skmacy unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end; 1842181641Skmacy 1843230435Salc return (sysctl_handle_long(oidp, &kfree, 0, req)); 1844181641Skmacy} 1845181641SkmacySYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG|CTLFLAG_RD, 1846181641Skmacy 0, 0, kvm_free, "IU", "Amount of KVM free"); 1847181641Skmacy 1848181641Skmacy/* 1849181641Skmacy * grow the number of kernel page table entries, if needed 1850181641Skmacy */ 1851181641Skmacyvoid 1852181641Skmacypmap_growkernel(vm_offset_t addr) 1853181641Skmacy{ 1854181641Skmacy struct pmap *pmap; 1855181641Skmacy vm_paddr_t ptppaddr; 1856181641Skmacy vm_page_t nkpg; 1857181641Skmacy pd_entry_t newpdir; 1858181641Skmacy 1859181641Skmacy mtx_assert(&kernel_map->system_mtx, MA_OWNED); 1860181641Skmacy if (kernel_vm_end == 0) { 1861181641Skmacy kernel_vm_end = KERNBASE; 1862181641Skmacy nkpt = 0; 1863181641Skmacy while (pdir_pde(PTD, kernel_vm_end)) { 1864181641Skmacy kernel_vm_end = (kernel_vm_end + PAGE_SIZE * NPTEPG) & ~(PAGE_SIZE * NPTEPG - 1); 1865181641Skmacy nkpt++; 1866181641Skmacy if (kernel_vm_end - 1 >= kernel_map->max_offset) { 1867181641Skmacy kernel_vm_end = kernel_map->max_offset; 1868181641Skmacy break; 1869181641Skmacy } 1870181641Skmacy } 1871181641Skmacy } 1872230435Salc addr = roundup2(addr, NBPDR); 1873181641Skmacy if (addr - 1 >= kernel_map->max_offset) 1874181641Skmacy addr = kernel_map->max_offset; 1875181641Skmacy while (kernel_vm_end < addr) { 1876181641Skmacy if (pdir_pde(PTD, kernel_vm_end)) { 1877230435Salc kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK; 1878181641Skmacy if (kernel_vm_end - 1 >= kernel_map->max_offset) { 1879181641Skmacy kernel_vm_end = kernel_map->max_offset; 1880181641Skmacy break; 1881181641Skmacy } 1882181641Skmacy continue; 1883181641Skmacy } 1884181641Skmacy 1885230435Salc nkpg = vm_page_alloc(NULL, kernel_vm_end >> PDRSHIFT, 1886230435Salc VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | 1887230435Salc VM_ALLOC_ZERO); 1888230435Salc if (nkpg == NULL) 1889181641Skmacy panic("pmap_growkernel: no memory to grow kernel"); 1890181641Skmacy 1891181641Skmacy nkpt++; 1892181641Skmacy 1893230435Salc if ((nkpg->flags & PG_ZERO) == 0) 1894230435Salc pmap_zero_page(nkpg); 1895181641Skmacy ptppaddr = VM_PAGE_TO_PHYS(nkpg); 1896181641Skmacy newpdir = (pd_entry_t) (ptppaddr | PG_V | PG_RW | PG_A | PG_M); 1897181946Skmacy vm_page_lock_queues(); 1898181641Skmacy PD_SET_VA(kernel_pmap, (kernel_vm_end >> PDRSHIFT), newpdir, TRUE); 1899181641Skmacy mtx_lock_spin(&allpmaps_lock); 1900181641Skmacy LIST_FOREACH(pmap, &allpmaps, pm_list) 1901181641Skmacy PD_SET_VA(pmap, (kernel_vm_end >> PDRSHIFT), newpdir, TRUE); 1902181641Skmacy 1903181641Skmacy mtx_unlock_spin(&allpmaps_lock); 1904181946Skmacy vm_page_unlock_queues(); 1905181946Skmacy 1906230435Salc kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK; 1907181641Skmacy if (kernel_vm_end - 1 >= kernel_map->max_offset) { 1908181641Skmacy kernel_vm_end = kernel_map->max_offset; 1909181641Skmacy break; 1910181641Skmacy } 1911181641Skmacy } 1912181641Skmacy} 1913181641Skmacy 1914181641Skmacy 1915181641Skmacy/*************************************************** 1916181641Skmacy * page management routines. 1917181641Skmacy ***************************************************/ 1918181641Skmacy 1919181641SkmacyCTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE); 1920181641SkmacyCTASSERT(_NPCM == 11); 1921237950SalcCTASSERT(_NPCPV == 336); 1922181641Skmacy 1923181641Skmacystatic __inline struct pv_chunk * 1924181641Skmacypv_to_chunk(pv_entry_t pv) 1925181641Skmacy{ 1926181641Skmacy 1927230435Salc return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK)); 1928181641Skmacy} 1929181641Skmacy 1930181641Skmacy#define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap) 1931181641Skmacy 1932181641Skmacy#define PC_FREE0_9 0xfffffffful /* Free values for index 0 through 9 */ 1933181641Skmacy#define PC_FREE10 0x0000fffful /* Free values for index 10 */ 1934181641Skmacy 1935238005Salcstatic const uint32_t pc_freemask[_NPCM] = { 1936181641Skmacy PC_FREE0_9, PC_FREE0_9, PC_FREE0_9, 1937181641Skmacy PC_FREE0_9, PC_FREE0_9, PC_FREE0_9, 1938181641Skmacy PC_FREE0_9, PC_FREE0_9, PC_FREE0_9, 1939181641Skmacy PC_FREE0_9, PC_FREE10 1940181641Skmacy}; 1941181641Skmacy 1942181641SkmacySYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0, 1943181641Skmacy "Current number of pv entries"); 1944181641Skmacy 1945181641Skmacy#ifdef PV_STATS 1946181641Skmacystatic int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail; 1947181641Skmacy 1948181641SkmacySYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0, 1949181641Skmacy "Current number of pv entry chunks"); 1950181641SkmacySYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0, 1951181641Skmacy "Current number of pv entry chunks allocated"); 1952181641SkmacySYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0, 1953181641Skmacy "Current number of pv entry chunks frees"); 1954181641SkmacySYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0, 1955181641Skmacy "Number of times tried to get a chunk page but failed."); 1956181641Skmacy 1957181641Skmacystatic long pv_entry_frees, pv_entry_allocs; 1958181641Skmacystatic int pv_entry_spare; 1959181641Skmacy 1960181641SkmacySYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0, 1961181641Skmacy "Current number of pv entry frees"); 1962181641SkmacySYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0, 1963181641Skmacy "Current number of pv entry allocs"); 1964181641SkmacySYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0, 1965181641Skmacy "Current number of spare pv entries"); 1966181641Skmacy#endif 1967181641Skmacy 1968181641Skmacy/* 1969181641Skmacy * We are in a serious low memory condition. Resort to 1970181641Skmacy * drastic measures to free some pages so we can allocate 1971237950Salc * another pv entry chunk. 1972181641Skmacy */ 1973237950Salcstatic vm_page_t 1974237950Salcpmap_pv_reclaim(pmap_t locked_pmap) 1975181641Skmacy{ 1976237950Salc struct pch newtail; 1977237950Salc struct pv_chunk *pc; 1978181641Skmacy pmap_t pmap; 1979181641Skmacy pt_entry_t *pte, tpte; 1980237950Salc pv_entry_t pv; 1981181641Skmacy vm_offset_t va; 1982237950Salc vm_page_t free, m, m_pc; 1983238005Salc uint32_t inuse; 1984237950Salc int bit, field, freed; 1985181641Skmacy 1986237950Salc PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED); 1987237950Salc pmap = NULL; 1988237950Salc free = m_pc = NULL; 1989237950Salc TAILQ_INIT(&newtail); 1990237950Salc while ((pc = TAILQ_FIRST(&pv_chunks)) != NULL && (pv_vafree == 0 || 1991237950Salc free == NULL)) { 1992237950Salc TAILQ_REMOVE(&pv_chunks, pc, pc_lru); 1993237950Salc if (pmap != pc->pc_pmap) { 1994237950Salc if (pmap != NULL) { 1995237950Salc pmap_invalidate_all(pmap); 1996237950Salc if (pmap != locked_pmap) 1997237950Salc PMAP_UNLOCK(pmap); 1998237950Salc } 1999237950Salc pmap = pc->pc_pmap; 2000181641Skmacy /* Avoid deadlock and lock recursion. */ 2001181641Skmacy if (pmap > locked_pmap) 2002181641Skmacy PMAP_LOCK(pmap); 2003237950Salc else if (pmap != locked_pmap && !PMAP_TRYLOCK(pmap)) { 2004237950Salc pmap = NULL; 2005237950Salc TAILQ_INSERT_TAIL(&newtail, pc, pc_lru); 2006181641Skmacy continue; 2007237950Salc } 2008181641Skmacy } 2009237950Salc 2010237950Salc /* 2011237950Salc * Destroy every non-wired, 4 KB page mapping in the chunk. 2012237950Salc */ 2013237950Salc freed = 0; 2014237950Salc for (field = 0; field < _NPCM; field++) { 2015237950Salc for (inuse = ~pc->pc_map[field] & pc_freemask[field]; 2016237950Salc inuse != 0; inuse &= ~(1UL << bit)) { 2017237950Salc bit = bsfl(inuse); 2018237950Salc pv = &pc->pc_pventry[field * 32 + bit]; 2019237950Salc va = pv->pv_va; 2020241518Salc pte = pmap_pte(pmap, va); 2021241518Salc tpte = *pte; 2022241518Salc if ((tpte & PG_W) == 0) 2023241518Salc tpte = pte_load_clear(pte); 2024241518Salc pmap_pte_release(pte); 2025241518Salc if ((tpte & PG_W) != 0) 2026237950Salc continue; 2027241518Salc KASSERT(tpte != 0, 2028241518Salc ("pmap_pv_reclaim: pmap %p va %x zero pte", 2029241518Salc pmap, va)); 2030237950Salc if ((tpte & PG_G) != 0) 2031237950Salc pmap_invalidate_page(pmap, va); 2032237950Salc m = PHYS_TO_VM_PAGE(tpte & PG_FRAME); 2033237950Salc if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) 2034237950Salc vm_page_dirty(m); 2035237950Salc if ((tpte & PG_A) != 0) 2036237950Salc vm_page_aflag_set(m, PGA_REFERENCED); 2037237950Salc TAILQ_REMOVE(&m->md.pv_list, pv, pv_list); 2038237950Salc if (TAILQ_EMPTY(&m->md.pv_list)) 2039237950Salc vm_page_aflag_clear(m, PGA_WRITEABLE); 2040238005Salc pc->pc_map[field] |= 1UL << bit; 2041237950Salc pmap_unuse_pt(pmap, va, &free); 2042237950Salc freed++; 2043237950Salc } 2044237950Salc } 2045237950Salc if (freed == 0) { 2046237950Salc TAILQ_INSERT_TAIL(&newtail, pc, pc_lru); 2047237950Salc continue; 2048237950Salc } 2049238005Salc /* Every freed mapping is for a 4 KB page. */ 2050237950Salc pmap->pm_stats.resident_count -= freed; 2051237950Salc PV_STAT(pv_entry_frees += freed); 2052237950Salc PV_STAT(pv_entry_spare += freed); 2053237950Salc pv_entry_count -= freed; 2054237950Salc TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 2055237950Salc for (field = 0; field < _NPCM; field++) 2056237950Salc if (pc->pc_map[field] != pc_freemask[field]) { 2057237950Salc TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, 2058237950Salc pc_list); 2059237950Salc TAILQ_INSERT_TAIL(&newtail, pc, pc_lru); 2060237950Salc 2061237950Salc /* 2062237950Salc * One freed pv entry in locked_pmap is 2063237950Salc * sufficient. 2064237950Salc */ 2065237950Salc if (pmap == locked_pmap) 2066237950Salc goto out; 2067237950Salc break; 2068237950Salc } 2069237950Salc if (field == _NPCM) { 2070237950Salc PV_STAT(pv_entry_spare -= _NPCPV); 2071237950Salc PV_STAT(pc_chunk_count--); 2072237950Salc PV_STAT(pc_chunk_frees++); 2073237950Salc /* Entire chunk is free; return it. */ 2074237950Salc m_pc = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc)); 2075237950Salc pmap_qremove((vm_offset_t)pc, 1); 2076237950Salc pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc); 2077237950Salc break; 2078237950Salc } 2079181641Skmacy } 2080237950Salcout: 2081237950Salc TAILQ_CONCAT(&pv_chunks, &newtail, pc_lru); 2082237950Salc if (pmap != NULL) { 2083237950Salc pmap_invalidate_all(pmap); 2084237950Salc if (pmap != locked_pmap) 2085237950Salc PMAP_UNLOCK(pmap); 2086237950Salc } 2087237950Salc if (m_pc == NULL && pv_vafree != 0 && free != NULL) { 2088237950Salc m_pc = free; 2089237950Salc free = m_pc->right; 2090237950Salc /* Recycle a freed page table page. */ 2091237950Salc m_pc->wire_count = 1; 2092237950Salc atomic_add_int(&cnt.v_wire_count, 1); 2093237950Salc } 2094237950Salc pmap_free_zero_pages(free); 2095237950Salc return (m_pc); 2096181641Skmacy} 2097181641Skmacy 2098181641Skmacy/* 2099181641Skmacy * free the pv_entry back to the free list 2100181641Skmacy */ 2101181641Skmacystatic void 2102181641Skmacyfree_pv_entry(pmap_t pmap, pv_entry_t pv) 2103181641Skmacy{ 2104181641Skmacy struct pv_chunk *pc; 2105181641Skmacy int idx, field, bit; 2106181641Skmacy 2107181641Skmacy mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2108181641Skmacy PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2109181641Skmacy PV_STAT(pv_entry_frees++); 2110181641Skmacy PV_STAT(pv_entry_spare++); 2111181641Skmacy pv_entry_count--; 2112181641Skmacy pc = pv_to_chunk(pv); 2113181641Skmacy idx = pv - &pc->pc_pventry[0]; 2114181641Skmacy field = idx / 32; 2115181641Skmacy bit = idx % 32; 2116181641Skmacy pc->pc_map[field] |= 1ul << bit; 2117181641Skmacy for (idx = 0; idx < _NPCM; idx++) 2118230435Salc if (pc->pc_map[idx] != pc_freemask[idx]) { 2119238005Salc /* 2120238005Salc * 98% of the time, pc is already at the head of the 2121238005Salc * list. If it isn't already, move it to the head. 2122238005Salc */ 2123238005Salc if (__predict_false(TAILQ_FIRST(&pmap->pm_pvchunk) != 2124238005Salc pc)) { 2125238005Salc TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 2126238005Salc TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, 2127238005Salc pc_list); 2128238005Salc } 2129181641Skmacy return; 2130230435Salc } 2131238005Salc TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 2132237950Salc free_pv_chunk(pc); 2133237950Salc} 2134237950Salc 2135237950Salcstatic void 2136237950Salcfree_pv_chunk(struct pv_chunk *pc) 2137237950Salc{ 2138237950Salc vm_page_t m; 2139237950Salc 2140237950Salc TAILQ_REMOVE(&pv_chunks, pc, pc_lru); 2141181641Skmacy PV_STAT(pv_entry_spare -= _NPCPV); 2142181641Skmacy PV_STAT(pc_chunk_count--); 2143181641Skmacy PV_STAT(pc_chunk_frees++); 2144181641Skmacy /* entire chunk is free, return it */ 2145181641Skmacy m = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc)); 2146181641Skmacy pmap_qremove((vm_offset_t)pc, 1); 2147181641Skmacy vm_page_unwire(m, 0); 2148181641Skmacy vm_page_free(m); 2149181641Skmacy pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc); 2150181641Skmacy} 2151181641Skmacy 2152181641Skmacy/* 2153181641Skmacy * get a new pv_entry, allocating a block from the system 2154181641Skmacy * when needed. 2155181641Skmacy */ 2156181641Skmacystatic pv_entry_t 2157237950Salcget_pv_entry(pmap_t pmap, boolean_t try) 2158181641Skmacy{ 2159181641Skmacy static const struct timeval printinterval = { 60, 0 }; 2160181641Skmacy static struct timeval lastprint; 2161181641Skmacy int bit, field; 2162181641Skmacy pv_entry_t pv; 2163181641Skmacy struct pv_chunk *pc; 2164181641Skmacy vm_page_t m; 2165181641Skmacy 2166181641Skmacy PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2167181641Skmacy mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2168181641Skmacy PV_STAT(pv_entry_allocs++); 2169181641Skmacy pv_entry_count++; 2170181641Skmacy if (pv_entry_count > pv_entry_high_water) 2171181641Skmacy if (ratecheck(&lastprint, &printinterval)) 2172181641Skmacy printf("Approaching the limit on PV entries, consider " 2173181641Skmacy "increasing either the vm.pmap.shpgperproc or the " 2174181641Skmacy "vm.pmap.pv_entry_max tunable.\n"); 2175181641Skmacyretry: 2176181641Skmacy pc = TAILQ_FIRST(&pmap->pm_pvchunk); 2177181641Skmacy if (pc != NULL) { 2178181641Skmacy for (field = 0; field < _NPCM; field++) { 2179181641Skmacy if (pc->pc_map[field]) { 2180181641Skmacy bit = bsfl(pc->pc_map[field]); 2181181641Skmacy break; 2182181641Skmacy } 2183181641Skmacy } 2184181641Skmacy if (field < _NPCM) { 2185181641Skmacy pv = &pc->pc_pventry[field * 32 + bit]; 2186181641Skmacy pc->pc_map[field] &= ~(1ul << bit); 2187181641Skmacy /* If this was the last item, move it to tail */ 2188181641Skmacy for (field = 0; field < _NPCM; field++) 2189181641Skmacy if (pc->pc_map[field] != 0) { 2190181641Skmacy PV_STAT(pv_entry_spare--); 2191181641Skmacy return (pv); /* not full, return */ 2192181641Skmacy } 2193181641Skmacy TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 2194181641Skmacy TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list); 2195181641Skmacy PV_STAT(pv_entry_spare--); 2196181641Skmacy return (pv); 2197181641Skmacy } 2198181641Skmacy } 2199181641Skmacy /* 2200181641Skmacy * Access to the ptelist "pv_vafree" is synchronized by the page 2201181641Skmacy * queues lock. If "pv_vafree" is currently non-empty, it will 2202181641Skmacy * remain non-empty until pmap_ptelist_alloc() completes. 2203181641Skmacy */ 2204237950Salc if (pv_vafree == 0 || (m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | 2205181641Skmacy VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) { 2206181641Skmacy if (try) { 2207181641Skmacy pv_entry_count--; 2208181641Skmacy PV_STAT(pc_chunk_tryfail++); 2209181641Skmacy return (NULL); 2210181641Skmacy } 2211237950Salc m = pmap_pv_reclaim(pmap); 2212237950Salc if (m == NULL) 2213237950Salc goto retry; 2214181641Skmacy } 2215181641Skmacy PV_STAT(pc_chunk_count++); 2216181641Skmacy PV_STAT(pc_chunk_allocs++); 2217181641Skmacy pc = (struct pv_chunk *)pmap_ptelist_alloc(&pv_vafree); 2218181641Skmacy pmap_qenter((vm_offset_t)pc, &m, 1); 2219181641Skmacy if ((m->flags & PG_ZERO) == 0) 2220181641Skmacy pagezero(pc); 2221181641Skmacy pc->pc_pmap = pmap; 2222181641Skmacy pc->pc_map[0] = pc_freemask[0] & ~1ul; /* preallocated bit 0 */ 2223181641Skmacy for (field = 1; field < _NPCM; field++) 2224181641Skmacy pc->pc_map[field] = pc_freemask[field]; 2225237950Salc TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru); 2226181641Skmacy pv = &pc->pc_pventry[0]; 2227181641Skmacy TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list); 2228181641Skmacy PV_STAT(pv_entry_spare += _NPCPV - 1); 2229181641Skmacy return (pv); 2230181641Skmacy} 2231181641Skmacy 2232208651Salcstatic __inline pv_entry_t 2233208651Salcpmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va) 2234181641Skmacy{ 2235181641Skmacy pv_entry_t pv; 2236181641Skmacy 2237181641Skmacy mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2238208651Salc TAILQ_FOREACH(pv, &pvh->pv_list, pv_list) { 2239208651Salc if (pmap == PV_PMAP(pv) && va == pv->pv_va) { 2240208651Salc TAILQ_REMOVE(&pvh->pv_list, pv, pv_list); 2241181641Skmacy break; 2242208651Salc } 2243181641Skmacy } 2244208651Salc return (pv); 2245181641Skmacy} 2246181641Skmacy 2247181641Skmacystatic void 2248208651Salcpmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va) 2249181641Skmacy{ 2250181641Skmacy pv_entry_t pv; 2251181641Skmacy 2252208651Salc pv = pmap_pvh_remove(pvh, pmap, va); 2253208651Salc KASSERT(pv != NULL, ("pmap_pvh_free: pv not found")); 2254208651Salc free_pv_entry(pmap, pv); 2255208651Salc} 2256208651Salc 2257208651Salcstatic void 2258208651Salcpmap_remove_entry(pmap_t pmap, vm_page_t m, vm_offset_t va) 2259208651Salc{ 2260208651Salc 2261181641Skmacy mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2262208651Salc pmap_pvh_free(&m->md, pmap, va); 2263208651Salc if (TAILQ_EMPTY(&m->md.pv_list)) 2264225418Skib vm_page_aflag_clear(m, PGA_WRITEABLE); 2265181641Skmacy} 2266181641Skmacy 2267181641Skmacy/* 2268181641Skmacy * Conditionally create a pv entry. 2269181641Skmacy */ 2270181641Skmacystatic boolean_t 2271181641Skmacypmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m) 2272181641Skmacy{ 2273181641Skmacy pv_entry_t pv; 2274181641Skmacy 2275181641Skmacy PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2276181641Skmacy mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2277181641Skmacy if (pv_entry_count < pv_entry_high_water && 2278181641Skmacy (pv = get_pv_entry(pmap, TRUE)) != NULL) { 2279181641Skmacy pv->pv_va = va; 2280181641Skmacy TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list); 2281181641Skmacy return (TRUE); 2282181641Skmacy } else 2283181641Skmacy return (FALSE); 2284181641Skmacy} 2285181641Skmacy 2286181641Skmacy/* 2287181641Skmacy * pmap_remove_pte: do the things to unmap a page in a process 2288181641Skmacy */ 2289181641Skmacystatic int 2290181641Skmacypmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t va, vm_page_t *free) 2291181641Skmacy{ 2292181641Skmacy pt_entry_t oldpte; 2293181641Skmacy vm_page_t m; 2294181641Skmacy 2295181641Skmacy CTR3(KTR_PMAP, "pmap_remove_pte: pmap=%p *ptq=0x%x va=0x%x", 2296181641Skmacy pmap, (u_long)*ptq, va); 2297181641Skmacy 2298181641Skmacy mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2299181641Skmacy PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2300181641Skmacy oldpte = *ptq; 2301181641Skmacy PT_SET_VA_MA(ptq, 0, TRUE); 2302241518Salc KASSERT(oldpte != 0, 2303241518Salc ("pmap_remove_pte: pmap %p va %x zero pte", pmap, va)); 2304181641Skmacy if (oldpte & PG_W) 2305181641Skmacy pmap->pm_stats.wired_count -= 1; 2306181641Skmacy /* 2307181641Skmacy * Machines that don't support invlpg, also don't support 2308181641Skmacy * PG_G. 2309181641Skmacy */ 2310181641Skmacy if (oldpte & PG_G) 2311181641Skmacy pmap_invalidate_page(kernel_pmap, va); 2312181641Skmacy pmap->pm_stats.resident_count -= 1; 2313216762Scperciva if (oldpte & PG_MANAGED) { 2314181641Skmacy m = PHYS_TO_VM_PAGE(xpmap_mtop(oldpte) & PG_FRAME); 2315208651Salc if ((oldpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) 2316181641Skmacy vm_page_dirty(m); 2317181641Skmacy if (oldpte & PG_A) 2318225418Skib vm_page_aflag_set(m, PGA_REFERENCED); 2319181641Skmacy pmap_remove_entry(pmap, m, va); 2320216762Scperciva } 2321181641Skmacy return (pmap_unuse_pt(pmap, va, free)); 2322181641Skmacy} 2323181641Skmacy 2324181641Skmacy/* 2325181641Skmacy * Remove a single page from a process address space 2326181641Skmacy */ 2327181641Skmacystatic void 2328181641Skmacypmap_remove_page(pmap_t pmap, vm_offset_t va, vm_page_t *free) 2329181641Skmacy{ 2330181641Skmacy pt_entry_t *pte; 2331181641Skmacy 2332181641Skmacy CTR2(KTR_PMAP, "pmap_remove_page: pmap=%p va=0x%x", 2333181641Skmacy pmap, va); 2334181641Skmacy 2335181641Skmacy mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2336181641Skmacy KASSERT(curthread->td_pinned > 0, ("curthread not pinned")); 2337181641Skmacy PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2338181641Skmacy if ((pte = pmap_pte_quick(pmap, va)) == NULL || (*pte & PG_V) == 0) 2339181641Skmacy return; 2340181641Skmacy pmap_remove_pte(pmap, pte, va, free); 2341181641Skmacy pmap_invalidate_page(pmap, va); 2342181641Skmacy if (*PMAP1) 2343181641Skmacy PT_SET_MA(PADDR1, 0); 2344181641Skmacy 2345181641Skmacy} 2346181641Skmacy 2347181641Skmacy/* 2348181641Skmacy * Remove the given range of addresses from the specified map. 2349181641Skmacy * 2350181641Skmacy * It is assumed that the start and end are properly 2351181641Skmacy * rounded to the page size. 2352181641Skmacy */ 2353181641Skmacyvoid 2354181641Skmacypmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 2355181641Skmacy{ 2356181641Skmacy vm_offset_t pdnxt; 2357181641Skmacy pd_entry_t ptpaddr; 2358181641Skmacy pt_entry_t *pte; 2359181641Skmacy vm_page_t free = NULL; 2360181641Skmacy int anyvalid; 2361230435Salc 2362181641Skmacy CTR3(KTR_PMAP, "pmap_remove: pmap=%p sva=0x%x eva=0x%x", 2363181641Skmacy pmap, sva, eva); 2364230435Salc 2365181641Skmacy /* 2366181641Skmacy * Perform an unsynchronized read. This is, however, safe. 2367181641Skmacy */ 2368181641Skmacy if (pmap->pm_stats.resident_count == 0) 2369181641Skmacy return; 2370181641Skmacy 2371181641Skmacy anyvalid = 0; 2372181641Skmacy 2373181641Skmacy vm_page_lock_queues(); 2374181641Skmacy sched_pin(); 2375181641Skmacy PMAP_LOCK(pmap); 2376181641Skmacy 2377181641Skmacy /* 2378181641Skmacy * special handling of removing one page. a very 2379181641Skmacy * common operation and easy to short circuit some 2380181641Skmacy * code. 2381181641Skmacy */ 2382181641Skmacy if ((sva + PAGE_SIZE == eva) && 2383181641Skmacy ((pmap->pm_pdir[(sva >> PDRSHIFT)] & PG_PS) == 0)) { 2384181641Skmacy pmap_remove_page(pmap, sva, &free); 2385181641Skmacy goto out; 2386181641Skmacy } 2387181641Skmacy 2388181641Skmacy for (; sva < eva; sva = pdnxt) { 2389230435Salc u_int pdirindex; 2390181641Skmacy 2391181641Skmacy /* 2392181641Skmacy * Calculate index for next page table. 2393181641Skmacy */ 2394181641Skmacy pdnxt = (sva + NBPDR) & ~PDRMASK; 2395230435Salc if (pdnxt < sva) 2396230435Salc pdnxt = eva; 2397181641Skmacy if (pmap->pm_stats.resident_count == 0) 2398181641Skmacy break; 2399181641Skmacy 2400181641Skmacy pdirindex = sva >> PDRSHIFT; 2401181641Skmacy ptpaddr = pmap->pm_pdir[pdirindex]; 2402181641Skmacy 2403181641Skmacy /* 2404181641Skmacy * Weed out invalid mappings. Note: we assume that the page 2405181641Skmacy * directory table is always allocated, and in kernel virtual. 2406181641Skmacy */ 2407181641Skmacy if (ptpaddr == 0) 2408181641Skmacy continue; 2409181641Skmacy 2410181641Skmacy /* 2411181641Skmacy * Check for large page. 2412181641Skmacy */ 2413181641Skmacy if ((ptpaddr & PG_PS) != 0) { 2414181641Skmacy PD_CLEAR_VA(pmap, pdirindex, TRUE); 2415181641Skmacy pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE; 2416181641Skmacy anyvalid = 1; 2417181641Skmacy continue; 2418181641Skmacy } 2419181641Skmacy 2420181641Skmacy /* 2421181641Skmacy * Limit our scan to either the end of the va represented 2422181641Skmacy * by the current page table page, or to the end of the 2423181641Skmacy * range being removed. 2424181641Skmacy */ 2425181641Skmacy if (pdnxt > eva) 2426181641Skmacy pdnxt = eva; 2427181641Skmacy 2428181641Skmacy for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++, 2429181641Skmacy sva += PAGE_SIZE) { 2430181641Skmacy if ((*pte & PG_V) == 0) 2431181641Skmacy continue; 2432181641Skmacy 2433181641Skmacy /* 2434181641Skmacy * The TLB entry for a PG_G mapping is invalidated 2435181641Skmacy * by pmap_remove_pte(). 2436181641Skmacy */ 2437181641Skmacy if ((*pte & PG_G) == 0) 2438181641Skmacy anyvalid = 1; 2439181641Skmacy if (pmap_remove_pte(pmap, pte, sva, &free)) 2440181641Skmacy break; 2441181641Skmacy } 2442181641Skmacy } 2443181641Skmacy PT_UPDATES_FLUSH(); 2444181641Skmacy if (*PMAP1) 2445181641Skmacy PT_SET_VA_MA(PMAP1, 0, TRUE); 2446181641Skmacyout: 2447181641Skmacy if (anyvalid) 2448181641Skmacy pmap_invalidate_all(pmap); 2449181641Skmacy sched_unpin(); 2450181641Skmacy vm_page_unlock_queues(); 2451181641Skmacy PMAP_UNLOCK(pmap); 2452181641Skmacy pmap_free_zero_pages(free); 2453181641Skmacy} 2454181641Skmacy 2455181641Skmacy/* 2456181641Skmacy * Routine: pmap_remove_all 2457181641Skmacy * Function: 2458181641Skmacy * Removes this physical page from 2459181641Skmacy * all physical maps in which it resides. 2460181641Skmacy * Reflects back modify bits to the pager. 2461181641Skmacy * 2462181641Skmacy * Notes: 2463181641Skmacy * Original versions of this routine were very 2464181641Skmacy * inefficient because they iteratively called 2465181641Skmacy * pmap_remove (slow...) 2466181641Skmacy */ 2467181641Skmacy 2468181641Skmacyvoid 2469181641Skmacypmap_remove_all(vm_page_t m) 2470181641Skmacy{ 2471181641Skmacy pv_entry_t pv; 2472181641Skmacy pmap_t pmap; 2473181641Skmacy pt_entry_t *pte, tpte; 2474181641Skmacy vm_page_t free; 2475181641Skmacy 2476224746Skib KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2477223677Salc ("pmap_remove_all: page %p is not managed", m)); 2478208651Salc free = NULL; 2479207796Salc vm_page_lock_queues(); 2480181641Skmacy sched_pin(); 2481181641Skmacy while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) { 2482181641Skmacy pmap = PV_PMAP(pv); 2483181641Skmacy PMAP_LOCK(pmap); 2484181641Skmacy pmap->pm_stats.resident_count--; 2485181641Skmacy pte = pmap_pte_quick(pmap, pv->pv_va); 2486181641Skmacy tpte = *pte; 2487181641Skmacy PT_SET_VA_MA(pte, 0, TRUE); 2488241518Salc KASSERT(tpte != 0, ("pmap_remove_all: pmap %p va %x zero pte", 2489241518Salc pmap, pv->pv_va)); 2490181641Skmacy if (tpte & PG_W) 2491181641Skmacy pmap->pm_stats.wired_count--; 2492181641Skmacy if (tpte & PG_A) 2493225418Skib vm_page_aflag_set(m, PGA_REFERENCED); 2494181641Skmacy 2495181641Skmacy /* 2496181641Skmacy * Update the vm_page_t clean and reference bits. 2497181641Skmacy */ 2498208651Salc if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) 2499181641Skmacy vm_page_dirty(m); 2500181641Skmacy pmap_unuse_pt(pmap, pv->pv_va, &free); 2501181641Skmacy pmap_invalidate_page(pmap, pv->pv_va); 2502181641Skmacy TAILQ_REMOVE(&m->md.pv_list, pv, pv_list); 2503181641Skmacy free_pv_entry(pmap, pv); 2504181641Skmacy PMAP_UNLOCK(pmap); 2505181641Skmacy } 2506225418Skib vm_page_aflag_clear(m, PGA_WRITEABLE); 2507181641Skmacy PT_UPDATES_FLUSH(); 2508181641Skmacy if (*PMAP1) 2509181641Skmacy PT_SET_MA(PADDR1, 0); 2510181641Skmacy sched_unpin(); 2511207796Salc vm_page_unlock_queues(); 2512208651Salc pmap_free_zero_pages(free); 2513181641Skmacy} 2514181641Skmacy 2515181641Skmacy/* 2516181641Skmacy * Set the physical protection on the 2517181641Skmacy * specified range of this map as requested. 2518181641Skmacy */ 2519181641Skmacyvoid 2520181641Skmacypmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot) 2521181641Skmacy{ 2522181641Skmacy vm_offset_t pdnxt; 2523181641Skmacy pd_entry_t ptpaddr; 2524181641Skmacy pt_entry_t *pte; 2525181641Skmacy int anychanged; 2526181641Skmacy 2527181641Skmacy CTR4(KTR_PMAP, "pmap_protect: pmap=%p sva=0x%x eva=0x%x prot=0x%x", 2528181641Skmacy pmap, sva, eva, prot); 2529181641Skmacy 2530181641Skmacy if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 2531181641Skmacy pmap_remove(pmap, sva, eva); 2532181641Skmacy return; 2533181641Skmacy } 2534181641Skmacy 2535181641Skmacy#ifdef PAE 2536181641Skmacy if ((prot & (VM_PROT_WRITE|VM_PROT_EXECUTE)) == 2537181641Skmacy (VM_PROT_WRITE|VM_PROT_EXECUTE)) 2538181641Skmacy return; 2539181641Skmacy#else 2540181641Skmacy if (prot & VM_PROT_WRITE) 2541181641Skmacy return; 2542181641Skmacy#endif 2543181641Skmacy 2544181641Skmacy anychanged = 0; 2545181641Skmacy 2546181641Skmacy vm_page_lock_queues(); 2547181641Skmacy sched_pin(); 2548181641Skmacy PMAP_LOCK(pmap); 2549181641Skmacy for (; sva < eva; sva = pdnxt) { 2550181641Skmacy pt_entry_t obits, pbits; 2551230435Salc u_int pdirindex; 2552181641Skmacy 2553181641Skmacy pdnxt = (sva + NBPDR) & ~PDRMASK; 2554230435Salc if (pdnxt < sva) 2555230435Salc pdnxt = eva; 2556181641Skmacy 2557181641Skmacy pdirindex = sva >> PDRSHIFT; 2558181641Skmacy ptpaddr = pmap->pm_pdir[pdirindex]; 2559181641Skmacy 2560181641Skmacy /* 2561181641Skmacy * Weed out invalid mappings. Note: we assume that the page 2562181641Skmacy * directory table is always allocated, and in kernel virtual. 2563181641Skmacy */ 2564181641Skmacy if (ptpaddr == 0) 2565181641Skmacy continue; 2566181641Skmacy 2567181641Skmacy /* 2568181641Skmacy * Check for large page. 2569181641Skmacy */ 2570181641Skmacy if ((ptpaddr & PG_PS) != 0) { 2571181641Skmacy if ((prot & VM_PROT_WRITE) == 0) 2572181641Skmacy pmap->pm_pdir[pdirindex] &= ~(PG_M|PG_RW); 2573181641Skmacy#ifdef PAE 2574181641Skmacy if ((prot & VM_PROT_EXECUTE) == 0) 2575181641Skmacy pmap->pm_pdir[pdirindex] |= pg_nx; 2576181641Skmacy#endif 2577181641Skmacy anychanged = 1; 2578181641Skmacy continue; 2579181641Skmacy } 2580181641Skmacy 2581181641Skmacy if (pdnxt > eva) 2582181641Skmacy pdnxt = eva; 2583181641Skmacy 2584181641Skmacy for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++, 2585181641Skmacy sva += PAGE_SIZE) { 2586181641Skmacy vm_page_t m; 2587181641Skmacy 2588181641Skmacyretry: 2589181641Skmacy /* 2590181641Skmacy * Regardless of whether a pte is 32 or 64 bits in 2591181641Skmacy * size, PG_RW, PG_A, and PG_M are among the least 2592181641Skmacy * significant 32 bits. 2593181641Skmacy */ 2594181641Skmacy obits = pbits = *pte; 2595181641Skmacy if ((pbits & PG_V) == 0) 2596181641Skmacy continue; 2597207262Salc 2598207262Salc if ((prot & VM_PROT_WRITE) == 0) { 2599207262Salc if ((pbits & (PG_MANAGED | PG_M | PG_RW)) == 2600207262Salc (PG_MANAGED | PG_M | PG_RW)) { 2601207262Salc m = PHYS_TO_VM_PAGE(xpmap_mtop(pbits) & 2602207262Salc PG_FRAME); 2603181641Skmacy vm_page_dirty(m); 2604181641Skmacy } 2605207262Salc pbits &= ~(PG_RW | PG_M); 2606181641Skmacy } 2607181641Skmacy#ifdef PAE 2608181641Skmacy if ((prot & VM_PROT_EXECUTE) == 0) 2609181641Skmacy pbits |= pg_nx; 2610181641Skmacy#endif 2611181641Skmacy 2612181641Skmacy if (pbits != obits) { 2613181641Skmacy obits = *pte; 2614181641Skmacy PT_SET_VA_MA(pte, pbits, TRUE); 2615181641Skmacy if (*pte != pbits) 2616181641Skmacy goto retry; 2617181641Skmacy if (obits & PG_G) 2618181641Skmacy pmap_invalidate_page(pmap, sva); 2619181641Skmacy else 2620181641Skmacy anychanged = 1; 2621181641Skmacy } 2622181641Skmacy } 2623181641Skmacy } 2624181641Skmacy PT_UPDATES_FLUSH(); 2625181641Skmacy if (*PMAP1) 2626181641Skmacy PT_SET_VA_MA(PMAP1, 0, TRUE); 2627181641Skmacy if (anychanged) 2628181641Skmacy pmap_invalidate_all(pmap); 2629181641Skmacy sched_unpin(); 2630181641Skmacy vm_page_unlock_queues(); 2631181641Skmacy PMAP_UNLOCK(pmap); 2632181641Skmacy} 2633181641Skmacy 2634181641Skmacy/* 2635181641Skmacy * Insert the given physical page (p) at 2636181641Skmacy * the specified virtual address (v) in the 2637181641Skmacy * target physical map with the protection requested. 2638181641Skmacy * 2639181641Skmacy * If specified, the page will be wired down, meaning 2640181641Skmacy * that the related pte can not be reclaimed. 2641181641Skmacy * 2642181641Skmacy * NB: This is the only routine which MAY NOT lazy-evaluate 2643181641Skmacy * or lose information. That is, this routine must actually 2644181641Skmacy * insert this page into the given map NOW. 2645181641Skmacy */ 2646181641Skmacyvoid 2647181641Skmacypmap_enter(pmap_t pmap, vm_offset_t va, vm_prot_t access, vm_page_t m, 2648181641Skmacy vm_prot_t prot, boolean_t wired) 2649181641Skmacy{ 2650181641Skmacy pd_entry_t *pde; 2651181641Skmacy pt_entry_t *pte; 2652208651Salc pt_entry_t newpte, origpte; 2653208651Salc pv_entry_t pv; 2654208651Salc vm_paddr_t opa, pa; 2655181641Skmacy vm_page_t mpte, om; 2656181641Skmacy boolean_t invlva; 2657181641Skmacy 2658181641Skmacy CTR6(KTR_PMAP, "pmap_enter: pmap=%08p va=0x%08x access=0x%x ma=0x%08x prot=0x%x wired=%d", 2659215587Scperciva pmap, va, access, VM_PAGE_TO_MACH(m), prot, wired); 2660181641Skmacy va = trunc_page(va); 2661208651Salc KASSERT(va <= VM_MAX_KERNEL_ADDRESS, ("pmap_enter: toobig")); 2662208651Salc KASSERT(va < UPT_MIN_ADDRESS || va >= UPT_MAX_ADDRESS, 2663208175Salc ("pmap_enter: invalid to pmap_enter page table pages (va: 0x%x)", 2664208175Salc va)); 2665230435Salc KASSERT((m->oflags & (VPO_UNMANAGED | VPO_BUSY)) != 0 || 2666230435Salc VM_OBJECT_LOCKED(m->object), 2667208175Salc ("pmap_enter: page %p is not busy", m)); 2668181641Skmacy 2669181641Skmacy mpte = NULL; 2670181641Skmacy 2671181641Skmacy vm_page_lock_queues(); 2672181641Skmacy PMAP_LOCK(pmap); 2673181641Skmacy sched_pin(); 2674181641Skmacy 2675181641Skmacy /* 2676181641Skmacy * In the case that a page table page is not 2677181641Skmacy * resident, we are creating it here. 2678181641Skmacy */ 2679181641Skmacy if (va < VM_MAXUSER_ADDRESS) { 2680181641Skmacy mpte = pmap_allocpte(pmap, va, M_WAITOK); 2681181641Skmacy } 2682181641Skmacy 2683181641Skmacy pde = pmap_pde(pmap, va); 2684181641Skmacy if ((*pde & PG_PS) != 0) 2685181641Skmacy panic("pmap_enter: attempted pmap_enter on 4MB page"); 2686181641Skmacy pte = pmap_pte_quick(pmap, va); 2687181641Skmacy 2688181641Skmacy /* 2689181641Skmacy * Page Directory table entry not valid, we need a new PT page 2690181641Skmacy */ 2691181641Skmacy if (pte == NULL) { 2692208651Salc panic("pmap_enter: invalid page directory pdir=%#jx, va=%#x", 2693181641Skmacy (uintmax_t)pmap->pm_pdir[va >> PDRSHIFT], va); 2694181641Skmacy } 2695181641Skmacy 2696181641Skmacy pa = VM_PAGE_TO_PHYS(m); 2697181641Skmacy om = NULL; 2698181641Skmacy opa = origpte = 0; 2699181641Skmacy 2700181641Skmacy#if 0 2701181641Skmacy KASSERT((*pte & PG_V) || (*pte == 0), ("address set but not valid pte=%p *pte=0x%016jx", 2702181641Skmacy pte, *pte)); 2703181641Skmacy#endif 2704181641Skmacy origpte = *pte; 2705181641Skmacy if (origpte) 2706181641Skmacy origpte = xpmap_mtop(origpte); 2707181641Skmacy opa = origpte & PG_FRAME; 2708181641Skmacy 2709181641Skmacy /* 2710181641Skmacy * Mapping has not changed, must be protection or wiring change. 2711181641Skmacy */ 2712181641Skmacy if (origpte && (opa == pa)) { 2713181641Skmacy /* 2714181641Skmacy * Wiring change, just update stats. We don't worry about 2715181641Skmacy * wiring PT pages as they remain resident as long as there 2716181641Skmacy * are valid mappings in them. Hence, if a user page is wired, 2717181641Skmacy * the PT page will be also. 2718181641Skmacy */ 2719181641Skmacy if (wired && ((origpte & PG_W) == 0)) 2720181641Skmacy pmap->pm_stats.wired_count++; 2721181641Skmacy else if (!wired && (origpte & PG_W)) 2722181641Skmacy pmap->pm_stats.wired_count--; 2723181641Skmacy 2724181641Skmacy /* 2725181641Skmacy * Remove extra pte reference 2726181641Skmacy */ 2727181641Skmacy if (mpte) 2728181641Skmacy mpte->wire_count--; 2729181641Skmacy 2730181641Skmacy if (origpte & PG_MANAGED) { 2731181641Skmacy om = m; 2732181641Skmacy pa |= PG_MANAGED; 2733181641Skmacy } 2734181641Skmacy goto validate; 2735181641Skmacy } 2736208651Salc 2737208651Salc pv = NULL; 2738208651Salc 2739181641Skmacy /* 2740181641Skmacy * Mapping has changed, invalidate old range and fall through to 2741181641Skmacy * handle validating new mapping. 2742181641Skmacy */ 2743181641Skmacy if (opa) { 2744181641Skmacy if (origpte & PG_W) 2745181641Skmacy pmap->pm_stats.wired_count--; 2746181641Skmacy if (origpte & PG_MANAGED) { 2747181641Skmacy om = PHYS_TO_VM_PAGE(opa); 2748208651Salc pv = pmap_pvh_remove(&om->md, pmap, va); 2749181641Skmacy } else if (va < VM_MAXUSER_ADDRESS) 2750181641Skmacy printf("va=0x%x is unmanaged :-( \n", va); 2751181641Skmacy 2752181641Skmacy if (mpte != NULL) { 2753181641Skmacy mpte->wire_count--; 2754181641Skmacy KASSERT(mpte->wire_count > 0, 2755181641Skmacy ("pmap_enter: missing reference to page table page," 2756181641Skmacy " va: 0x%x", va)); 2757181641Skmacy } 2758181641Skmacy } else 2759181641Skmacy pmap->pm_stats.resident_count++; 2760181641Skmacy 2761181641Skmacy /* 2762181641Skmacy * Enter on the PV list if part of our managed memory. 2763181641Skmacy */ 2764224746Skib if ((m->oflags & VPO_UNMANAGED) == 0) { 2765181641Skmacy KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva, 2766181641Skmacy ("pmap_enter: managed mapping within the clean submap")); 2767208651Salc if (pv == NULL) 2768208651Salc pv = get_pv_entry(pmap, FALSE); 2769208651Salc pv->pv_va = va; 2770208651Salc TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list); 2771181641Skmacy pa |= PG_MANAGED; 2772208651Salc } else if (pv != NULL) 2773208651Salc free_pv_entry(pmap, pv); 2774181641Skmacy 2775181641Skmacy /* 2776181641Skmacy * Increment counters 2777181641Skmacy */ 2778181641Skmacy if (wired) 2779181641Skmacy pmap->pm_stats.wired_count++; 2780181641Skmacy 2781181641Skmacyvalidate: 2782181641Skmacy /* 2783181641Skmacy * Now validate mapping with desired protection/wiring. 2784181641Skmacy */ 2785181641Skmacy newpte = (pt_entry_t)(pa | PG_V); 2786181641Skmacy if ((prot & VM_PROT_WRITE) != 0) { 2787181641Skmacy newpte |= PG_RW; 2788208651Salc if ((newpte & PG_MANAGED) != 0) 2789225418Skib vm_page_aflag_set(m, PGA_WRITEABLE); 2790181641Skmacy } 2791181641Skmacy#ifdef PAE 2792181641Skmacy if ((prot & VM_PROT_EXECUTE) == 0) 2793181641Skmacy newpte |= pg_nx; 2794181641Skmacy#endif 2795181641Skmacy if (wired) 2796181641Skmacy newpte |= PG_W; 2797181641Skmacy if (va < VM_MAXUSER_ADDRESS) 2798181641Skmacy newpte |= PG_U; 2799181641Skmacy if (pmap == kernel_pmap) 2800181641Skmacy newpte |= pgeflag; 2801181641Skmacy 2802181641Skmacy critical_enter(); 2803181641Skmacy /* 2804181641Skmacy * if the mapping or permission bits are different, we need 2805181641Skmacy * to update the pte. 2806181641Skmacy */ 2807181641Skmacy if ((origpte & ~(PG_M|PG_A)) != newpte) { 2808181641Skmacy if (origpte) { 2809181641Skmacy invlva = FALSE; 2810181641Skmacy origpte = *pte; 2811181641Skmacy PT_SET_VA(pte, newpte | PG_A, FALSE); 2812181641Skmacy if (origpte & PG_A) { 2813181641Skmacy if (origpte & PG_MANAGED) 2814225418Skib vm_page_aflag_set(om, PGA_REFERENCED); 2815181641Skmacy if (opa != VM_PAGE_TO_PHYS(m)) 2816181641Skmacy invlva = TRUE; 2817181641Skmacy#ifdef PAE 2818181641Skmacy if ((origpte & PG_NX) == 0 && 2819181641Skmacy (newpte & PG_NX) != 0) 2820181641Skmacy invlva = TRUE; 2821181641Skmacy#endif 2822181641Skmacy } 2823208651Salc if ((origpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) { 2824181641Skmacy if ((origpte & PG_MANAGED) != 0) 2825181641Skmacy vm_page_dirty(om); 2826181641Skmacy if ((prot & VM_PROT_WRITE) == 0) 2827181641Skmacy invlva = TRUE; 2828181641Skmacy } 2829208651Salc if ((origpte & PG_MANAGED) != 0 && 2830208651Salc TAILQ_EMPTY(&om->md.pv_list)) 2831225418Skib vm_page_aflag_clear(om, PGA_WRITEABLE); 2832181641Skmacy if (invlva) 2833181641Skmacy pmap_invalidate_page(pmap, va); 2834181641Skmacy } else{ 2835181641Skmacy PT_SET_VA(pte, newpte | PG_A, FALSE); 2836181641Skmacy } 2837181641Skmacy 2838181641Skmacy } 2839181641Skmacy PT_UPDATES_FLUSH(); 2840181641Skmacy critical_exit(); 2841181641Skmacy if (*PMAP1) 2842181641Skmacy PT_SET_VA_MA(PMAP1, 0, TRUE); 2843181641Skmacy sched_unpin(); 2844181641Skmacy vm_page_unlock_queues(); 2845181641Skmacy PMAP_UNLOCK(pmap); 2846181641Skmacy} 2847181641Skmacy 2848181641Skmacy/* 2849181641Skmacy * Maps a sequence of resident pages belonging to the same object. 2850181641Skmacy * The sequence begins with the given page m_start. This page is 2851181641Skmacy * mapped at the given virtual address start. Each subsequent page is 2852181641Skmacy * mapped at a virtual address that is offset from start by the same 2853181641Skmacy * amount as the page is offset from m_start within the object. The 2854181641Skmacy * last page in the sequence is the page with the largest offset from 2855181641Skmacy * m_start that can be mapped at a virtual address less than the given 2856181641Skmacy * virtual address end. Not every virtual page between start and end 2857181641Skmacy * is mapped; only those for which a resident page exists with the 2858181641Skmacy * corresponding offset from m_start are mapped. 2859181641Skmacy */ 2860181641Skmacyvoid 2861181641Skmacypmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end, 2862181641Skmacy vm_page_t m_start, vm_prot_t prot) 2863181641Skmacy{ 2864181641Skmacy vm_page_t m, mpte; 2865181641Skmacy vm_pindex_t diff, psize; 2866181641Skmacy multicall_entry_t mcl[16]; 2867181641Skmacy multicall_entry_t *mclp = mcl; 2868181641Skmacy int error, count = 0; 2869230435Salc 2870181641Skmacy VM_OBJECT_LOCK_ASSERT(m_start->object, MA_OWNED); 2871181641Skmacy psize = atop(end - start); 2872181641Skmacy mpte = NULL; 2873181641Skmacy m = m_start; 2874208574Salc vm_page_lock_queues(); 2875181641Skmacy PMAP_LOCK(pmap); 2876181641Skmacy while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 2877181641Skmacy mpte = pmap_enter_quick_locked(&mclp, &count, pmap, start + ptoa(diff), m, 2878181641Skmacy prot, mpte); 2879181641Skmacy m = TAILQ_NEXT(m, listq); 2880181641Skmacy if (count == 16) { 2881181641Skmacy error = HYPERVISOR_multicall(mcl, count); 2882181641Skmacy KASSERT(error == 0, ("bad multicall %d", error)); 2883181641Skmacy mclp = mcl; 2884181641Skmacy count = 0; 2885181641Skmacy } 2886181641Skmacy } 2887181641Skmacy if (count) { 2888181641Skmacy error = HYPERVISOR_multicall(mcl, count); 2889181641Skmacy KASSERT(error == 0, ("bad multicall %d", error)); 2890181641Skmacy } 2891208574Salc vm_page_unlock_queues(); 2892181641Skmacy PMAP_UNLOCK(pmap); 2893181641Skmacy} 2894181641Skmacy 2895181641Skmacy/* 2896181641Skmacy * this code makes some *MAJOR* assumptions: 2897181641Skmacy * 1. Current pmap & pmap exists. 2898181641Skmacy * 2. Not wired. 2899181641Skmacy * 3. Read access. 2900181641Skmacy * 4. No page table pages. 2901181641Skmacy * but is *MUCH* faster than pmap_enter... 2902181641Skmacy */ 2903181641Skmacy 2904181641Skmacyvoid 2905181641Skmacypmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot) 2906181641Skmacy{ 2907181641Skmacy multicall_entry_t mcl, *mclp; 2908181641Skmacy int count = 0; 2909181641Skmacy mclp = &mcl; 2910230435Salc 2911181641Skmacy CTR4(KTR_PMAP, "pmap_enter_quick: pmap=%p va=0x%x m=%p prot=0x%x", 2912181641Skmacy pmap, va, m, prot); 2913181641Skmacy 2914207796Salc vm_page_lock_queues(); 2915181641Skmacy PMAP_LOCK(pmap); 2916207796Salc (void)pmap_enter_quick_locked(&mclp, &count, pmap, va, m, prot, NULL); 2917181641Skmacy if (count) 2918181641Skmacy HYPERVISOR_multicall(&mcl, count); 2919207796Salc vm_page_unlock_queues(); 2920181641Skmacy PMAP_UNLOCK(pmap); 2921181641Skmacy} 2922181641Skmacy 2923181747Skmacy#ifdef notyet 2924181641Skmacyvoid 2925181641Skmacypmap_enter_quick_range(pmap_t pmap, vm_offset_t *addrs, vm_page_t *pages, vm_prot_t *prots, int count) 2926181641Skmacy{ 2927181641Skmacy int i, error, index = 0; 2928181641Skmacy multicall_entry_t mcl[16]; 2929181641Skmacy multicall_entry_t *mclp = mcl; 2930181641Skmacy 2931181641Skmacy PMAP_LOCK(pmap); 2932181641Skmacy for (i = 0; i < count; i++, addrs++, pages++, prots++) { 2933181641Skmacy if (!pmap_is_prefaultable_locked(pmap, *addrs)) 2934181641Skmacy continue; 2935181641Skmacy 2936181641Skmacy (void) pmap_enter_quick_locked(&mclp, &index, pmap, *addrs, *pages, *prots, NULL); 2937181641Skmacy if (index == 16) { 2938181641Skmacy error = HYPERVISOR_multicall(mcl, index); 2939181641Skmacy mclp = mcl; 2940181641Skmacy index = 0; 2941181641Skmacy KASSERT(error == 0, ("bad multicall %d", error)); 2942181641Skmacy } 2943181641Skmacy } 2944181641Skmacy if (index) { 2945181641Skmacy error = HYPERVISOR_multicall(mcl, index); 2946181641Skmacy KASSERT(error == 0, ("bad multicall %d", error)); 2947181641Skmacy } 2948181641Skmacy 2949181641Skmacy PMAP_UNLOCK(pmap); 2950181641Skmacy} 2951181747Skmacy#endif 2952181641Skmacy 2953181641Skmacystatic vm_page_t 2954181641Skmacypmap_enter_quick_locked(multicall_entry_t **mclpp, int *count, pmap_t pmap, vm_offset_t va, vm_page_t m, 2955181641Skmacy vm_prot_t prot, vm_page_t mpte) 2956181641Skmacy{ 2957181641Skmacy pt_entry_t *pte; 2958181641Skmacy vm_paddr_t pa; 2959181641Skmacy vm_page_t free; 2960181641Skmacy multicall_entry_t *mcl = *mclpp; 2961230435Salc 2962181641Skmacy KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva || 2963224746Skib (m->oflags & VPO_UNMANAGED) != 0, 2964181641Skmacy ("pmap_enter_quick_locked: managed mapping within the clean submap")); 2965181641Skmacy mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2966181641Skmacy PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2967181641Skmacy 2968181641Skmacy /* 2969181641Skmacy * In the case that a page table page is not 2970181641Skmacy * resident, we are creating it here. 2971181641Skmacy */ 2972181641Skmacy if (va < VM_MAXUSER_ADDRESS) { 2973230435Salc u_int ptepindex; 2974181641Skmacy pd_entry_t ptema; 2975181641Skmacy 2976181641Skmacy /* 2977181641Skmacy * Calculate pagetable page index 2978181641Skmacy */ 2979181641Skmacy ptepindex = va >> PDRSHIFT; 2980181641Skmacy if (mpte && (mpte->pindex == ptepindex)) { 2981181641Skmacy mpte->wire_count++; 2982181641Skmacy } else { 2983181641Skmacy /* 2984181641Skmacy * Get the page directory entry 2985181641Skmacy */ 2986181641Skmacy ptema = pmap->pm_pdir[ptepindex]; 2987181641Skmacy 2988181641Skmacy /* 2989181641Skmacy * If the page table page is mapped, we just increment 2990181641Skmacy * the hold count, and activate it. 2991181641Skmacy */ 2992181641Skmacy if (ptema & PG_V) { 2993181641Skmacy if (ptema & PG_PS) 2994181641Skmacy panic("pmap_enter_quick: unexpected mapping into 4MB page"); 2995181641Skmacy mpte = PHYS_TO_VM_PAGE(xpmap_mtop(ptema) & PG_FRAME); 2996181641Skmacy mpte->wire_count++; 2997181641Skmacy } else { 2998181641Skmacy mpte = _pmap_allocpte(pmap, ptepindex, 2999181641Skmacy M_NOWAIT); 3000181641Skmacy if (mpte == NULL) 3001181641Skmacy return (mpte); 3002181641Skmacy } 3003181641Skmacy } 3004181641Skmacy } else { 3005181641Skmacy mpte = NULL; 3006181641Skmacy } 3007181641Skmacy 3008181641Skmacy /* 3009181641Skmacy * This call to vtopte makes the assumption that we are 3010181641Skmacy * entering the page into the current pmap. In order to support 3011181641Skmacy * quick entry into any pmap, one would likely use pmap_pte_quick. 3012181641Skmacy * But that isn't as quick as vtopte. 3013181641Skmacy */ 3014181641Skmacy KASSERT(pmap_is_current(pmap), ("entering pages in non-current pmap")); 3015181641Skmacy pte = vtopte(va); 3016181641Skmacy if (*pte & PG_V) { 3017181641Skmacy if (mpte != NULL) { 3018181641Skmacy mpte->wire_count--; 3019181641Skmacy mpte = NULL; 3020181641Skmacy } 3021181641Skmacy return (mpte); 3022181641Skmacy } 3023181641Skmacy 3024181641Skmacy /* 3025181641Skmacy * Enter on the PV list if part of our managed memory. 3026181641Skmacy */ 3027224746Skib if ((m->oflags & VPO_UNMANAGED) == 0 && 3028181641Skmacy !pmap_try_insert_pv_entry(pmap, va, m)) { 3029181641Skmacy if (mpte != NULL) { 3030181641Skmacy free = NULL; 3031240151Skib if (pmap_unwire_ptp(pmap, mpte, &free)) { 3032181641Skmacy pmap_invalidate_page(pmap, va); 3033181641Skmacy pmap_free_zero_pages(free); 3034181641Skmacy } 3035181641Skmacy 3036181641Skmacy mpte = NULL; 3037181641Skmacy } 3038181641Skmacy return (mpte); 3039181641Skmacy } 3040181641Skmacy 3041181641Skmacy /* 3042181641Skmacy * Increment counters 3043181641Skmacy */ 3044181641Skmacy pmap->pm_stats.resident_count++; 3045181641Skmacy 3046181641Skmacy pa = VM_PAGE_TO_PHYS(m); 3047181641Skmacy#ifdef PAE 3048181641Skmacy if ((prot & VM_PROT_EXECUTE) == 0) 3049181641Skmacy pa |= pg_nx; 3050181641Skmacy#endif 3051181641Skmacy 3052181641Skmacy#if 0 3053181641Skmacy /* 3054181641Skmacy * Now validate mapping with RO protection 3055181641Skmacy */ 3056224746Skib if ((m->oflags & VPO_UNMANAGED) != 0) 3057181641Skmacy pte_store(pte, pa | PG_V | PG_U); 3058181641Skmacy else 3059181641Skmacy pte_store(pte, pa | PG_V | PG_U | PG_MANAGED); 3060181641Skmacy#else 3061181641Skmacy /* 3062181641Skmacy * Now validate mapping with RO protection 3063181641Skmacy */ 3064224746Skib if ((m->oflags & VPO_UNMANAGED) != 0) 3065181641Skmacy pa = xpmap_ptom(pa | PG_V | PG_U); 3066181641Skmacy else 3067181641Skmacy pa = xpmap_ptom(pa | PG_V | PG_U | PG_MANAGED); 3068181641Skmacy 3069181641Skmacy mcl->op = __HYPERVISOR_update_va_mapping; 3070181641Skmacy mcl->args[0] = va; 3071181641Skmacy mcl->args[1] = (uint32_t)(pa & 0xffffffff); 3072181641Skmacy mcl->args[2] = (uint32_t)(pa >> 32); 3073181641Skmacy mcl->args[3] = 0; 3074181641Skmacy *mclpp = mcl + 1; 3075181641Skmacy *count = *count + 1; 3076181641Skmacy#endif 3077230435Salc return (mpte); 3078181641Skmacy} 3079181641Skmacy 3080181641Skmacy/* 3081181641Skmacy * Make a temporary mapping for a physical address. This is only intended 3082181641Skmacy * to be used for panic dumps. 3083181641Skmacy */ 3084181641Skmacyvoid * 3085181641Skmacypmap_kenter_temporary(vm_paddr_t pa, int i) 3086181641Skmacy{ 3087181641Skmacy vm_offset_t va; 3088200346Skmacy vm_paddr_t ma = xpmap_ptom(pa); 3089181641Skmacy 3090181641Skmacy va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE); 3091200346Skmacy PT_SET_MA(va, (ma & ~PAGE_MASK) | PG_V | pgeflag); 3092181641Skmacy invlpg(va); 3093181641Skmacy return ((void *)crashdumpmap); 3094181641Skmacy} 3095181641Skmacy 3096181641Skmacy/* 3097181641Skmacy * This code maps large physical mmap regions into the 3098181641Skmacy * processor address space. Note that some shortcuts 3099181641Skmacy * are taken, but the code works. 3100181641Skmacy */ 3101181641Skmacyvoid 3102230435Salcpmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object, 3103230435Salc vm_pindex_t pindex, vm_size_t size) 3104181641Skmacy{ 3105207419Skmacy pd_entry_t *pde; 3106207419Skmacy vm_paddr_t pa, ptepa; 3107181641Skmacy vm_page_t p; 3108207419Skmacy int pat_mode; 3109181641Skmacy 3110181641Skmacy VM_OBJECT_LOCK_ASSERT(object, MA_OWNED); 3111195840Sjhb KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG, 3112181641Skmacy ("pmap_object_init_pt: non-device object")); 3113181641Skmacy if (pseflag && 3114207419Skmacy (addr & (NBPDR - 1)) == 0 && (size & (NBPDR - 1)) == 0) { 3115207419Skmacy if (!vm_object_populate(object, pindex, pindex + atop(size))) 3116207419Skmacy return; 3117181641Skmacy p = vm_page_lookup(object, pindex); 3118207419Skmacy KASSERT(p->valid == VM_PAGE_BITS_ALL, 3119207419Skmacy ("pmap_object_init_pt: invalid page %p", p)); 3120207419Skmacy pat_mode = p->md.pat_mode; 3121230435Salc 3122207419Skmacy /* 3123207419Skmacy * Abort the mapping if the first page is not physically 3124207419Skmacy * aligned to a 2/4MB page boundary. 3125207419Skmacy */ 3126181641Skmacy ptepa = VM_PAGE_TO_PHYS(p); 3127181641Skmacy if (ptepa & (NBPDR - 1)) 3128181641Skmacy return; 3129230435Salc 3130207419Skmacy /* 3131207419Skmacy * Skip the first page. Abort the mapping if the rest of 3132207419Skmacy * the pages are not physically contiguous or have differing 3133207419Skmacy * memory attributes. 3134207419Skmacy */ 3135207419Skmacy p = TAILQ_NEXT(p, listq); 3136207419Skmacy for (pa = ptepa + PAGE_SIZE; pa < ptepa + size; 3137207419Skmacy pa += PAGE_SIZE) { 3138207419Skmacy KASSERT(p->valid == VM_PAGE_BITS_ALL, 3139207419Skmacy ("pmap_object_init_pt: invalid page %p", p)); 3140207419Skmacy if (pa != VM_PAGE_TO_PHYS(p) || 3141207419Skmacy pat_mode != p->md.pat_mode) 3142207419Skmacy return; 3143207419Skmacy p = TAILQ_NEXT(p, listq); 3144207419Skmacy } 3145230435Salc 3146230435Salc /* 3147230435Salc * Map using 2/4MB pages. Since "ptepa" is 2/4M aligned and 3148230435Salc * "size" is a multiple of 2/4M, adding the PAT setting to 3149230435Salc * "pa" will not affect the termination of this loop. 3150230435Salc */ 3151181641Skmacy PMAP_LOCK(pmap); 3152207419Skmacy for (pa = ptepa | pmap_cache_bits(pat_mode, 1); pa < ptepa + 3153207419Skmacy size; pa += NBPDR) { 3154207419Skmacy pde = pmap_pde(pmap, addr); 3155207419Skmacy if (*pde == 0) { 3156207419Skmacy pde_store(pde, pa | PG_PS | PG_M | PG_A | 3157207419Skmacy PG_U | PG_RW | PG_V); 3158207419Skmacy pmap->pm_stats.resident_count += NBPDR / 3159207419Skmacy PAGE_SIZE; 3160207419Skmacy pmap_pde_mappings++; 3161207419Skmacy } 3162207419Skmacy /* Else continue on if the PDE is already valid. */ 3163207419Skmacy addr += NBPDR; 3164181641Skmacy } 3165181641Skmacy PMAP_UNLOCK(pmap); 3166181641Skmacy } 3167181641Skmacy} 3168181641Skmacy 3169181641Skmacy/* 3170181641Skmacy * Routine: pmap_change_wiring 3171181641Skmacy * Function: Change the wiring attribute for a map/virtual-address 3172181641Skmacy * pair. 3173181641Skmacy * In/out conditions: 3174181641Skmacy * The mapping must already exist in the pmap. 3175181641Skmacy */ 3176181641Skmacyvoid 3177181641Skmacypmap_change_wiring(pmap_t pmap, vm_offset_t va, boolean_t wired) 3178181641Skmacy{ 3179181641Skmacy pt_entry_t *pte; 3180181641Skmacy 3181181641Skmacy vm_page_lock_queues(); 3182181641Skmacy PMAP_LOCK(pmap); 3183181641Skmacy pte = pmap_pte(pmap, va); 3184181641Skmacy 3185181641Skmacy if (wired && !pmap_pte_w(pte)) { 3186181641Skmacy PT_SET_VA_MA((pte), *(pte) | PG_W, TRUE); 3187181641Skmacy pmap->pm_stats.wired_count++; 3188181641Skmacy } else if (!wired && pmap_pte_w(pte)) { 3189181641Skmacy PT_SET_VA_MA((pte), *(pte) & ~PG_W, TRUE); 3190181641Skmacy pmap->pm_stats.wired_count--; 3191181641Skmacy } 3192181641Skmacy 3193181641Skmacy /* 3194181641Skmacy * Wiring is not a hardware characteristic so there is no need to 3195181641Skmacy * invalidate TLB. 3196181641Skmacy */ 3197181641Skmacy pmap_pte_release(pte); 3198181641Skmacy PMAP_UNLOCK(pmap); 3199181641Skmacy vm_page_unlock_queues(); 3200181641Skmacy} 3201181641Skmacy 3202181641Skmacy 3203181641Skmacy 3204181641Skmacy/* 3205181641Skmacy * Copy the range specified by src_addr/len 3206181641Skmacy * from the source map to the range dst_addr/len 3207181641Skmacy * in the destination map. 3208181641Skmacy * 3209181641Skmacy * This routine is only advisory and need not do anything. 3210181641Skmacy */ 3211181641Skmacy 3212181641Skmacyvoid 3213181641Skmacypmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len, 3214230435Salc vm_offset_t src_addr) 3215181641Skmacy{ 3216181641Skmacy vm_page_t free; 3217181641Skmacy vm_offset_t addr; 3218181641Skmacy vm_offset_t end_addr = src_addr + len; 3219181641Skmacy vm_offset_t pdnxt; 3220181641Skmacy 3221181641Skmacy if (dst_addr != src_addr) 3222181641Skmacy return; 3223181641Skmacy 3224181641Skmacy if (!pmap_is_current(src_pmap)) { 3225181641Skmacy CTR2(KTR_PMAP, 3226181641Skmacy "pmap_copy, skipping: pdir[PTDPTDI]=0x%jx PTDpde[0]=0x%jx", 3227181641Skmacy (src_pmap->pm_pdir[PTDPTDI] & PG_FRAME), (PTDpde[0] & PG_FRAME)); 3228181641Skmacy 3229181641Skmacy return; 3230181641Skmacy } 3231181641Skmacy CTR5(KTR_PMAP, "pmap_copy: dst_pmap=%p src_pmap=%p dst_addr=0x%x len=%d src_addr=0x%x", 3232181641Skmacy dst_pmap, src_pmap, dst_addr, len, src_addr); 3233181641Skmacy 3234216960Scperciva#ifdef HAMFISTED_LOCKING 3235216960Scperciva mtx_lock(&createdelete_lock); 3236216960Scperciva#endif 3237216960Scperciva 3238181641Skmacy vm_page_lock_queues(); 3239181641Skmacy if (dst_pmap < src_pmap) { 3240181641Skmacy PMAP_LOCK(dst_pmap); 3241181641Skmacy PMAP_LOCK(src_pmap); 3242181641Skmacy } else { 3243181641Skmacy PMAP_LOCK(src_pmap); 3244181641Skmacy PMAP_LOCK(dst_pmap); 3245181641Skmacy } 3246181641Skmacy sched_pin(); 3247181641Skmacy for (addr = src_addr; addr < end_addr; addr = pdnxt) { 3248181641Skmacy pt_entry_t *src_pte, *dst_pte; 3249181641Skmacy vm_page_t dstmpte, srcmpte; 3250181641Skmacy pd_entry_t srcptepaddr; 3251230435Salc u_int ptepindex; 3252181641Skmacy 3253208651Salc KASSERT(addr < UPT_MIN_ADDRESS, 3254208651Salc ("pmap_copy: invalid to pmap_copy page tables")); 3255181641Skmacy 3256181641Skmacy pdnxt = (addr + NBPDR) & ~PDRMASK; 3257230435Salc if (pdnxt < addr) 3258230435Salc pdnxt = end_addr; 3259181641Skmacy ptepindex = addr >> PDRSHIFT; 3260181641Skmacy 3261181641Skmacy srcptepaddr = PT_GET(&src_pmap->pm_pdir[ptepindex]); 3262181641Skmacy if (srcptepaddr == 0) 3263181641Skmacy continue; 3264181641Skmacy 3265181641Skmacy if (srcptepaddr & PG_PS) { 3266181641Skmacy if (dst_pmap->pm_pdir[ptepindex] == 0) { 3267181641Skmacy PD_SET_VA(dst_pmap, ptepindex, srcptepaddr & ~PG_W, TRUE); 3268181641Skmacy dst_pmap->pm_stats.resident_count += 3269181641Skmacy NBPDR / PAGE_SIZE; 3270181641Skmacy } 3271181641Skmacy continue; 3272181641Skmacy } 3273181641Skmacy 3274181641Skmacy srcmpte = PHYS_TO_VM_PAGE(srcptepaddr & PG_FRAME); 3275208651Salc KASSERT(srcmpte->wire_count > 0, 3276208651Salc ("pmap_copy: source page table page is unused")); 3277181641Skmacy 3278181641Skmacy if (pdnxt > end_addr) 3279181641Skmacy pdnxt = end_addr; 3280181641Skmacy 3281181641Skmacy src_pte = vtopte(addr); 3282181641Skmacy while (addr < pdnxt) { 3283181641Skmacy pt_entry_t ptetemp; 3284181641Skmacy ptetemp = *src_pte; 3285181641Skmacy /* 3286181641Skmacy * we only virtual copy managed pages 3287181641Skmacy */ 3288181641Skmacy if ((ptetemp & PG_MANAGED) != 0) { 3289181641Skmacy dstmpte = pmap_allocpte(dst_pmap, addr, 3290181641Skmacy M_NOWAIT); 3291181641Skmacy if (dstmpte == NULL) 3292230435Salc goto out; 3293181641Skmacy dst_pte = pmap_pte_quick(dst_pmap, addr); 3294181641Skmacy if (*dst_pte == 0 && 3295181641Skmacy pmap_try_insert_pv_entry(dst_pmap, addr, 3296181641Skmacy PHYS_TO_VM_PAGE(xpmap_mtop(ptetemp) & PG_FRAME))) { 3297181641Skmacy /* 3298181641Skmacy * Clear the wired, modified, and 3299181641Skmacy * accessed (referenced) bits 3300181641Skmacy * during the copy. 3301181641Skmacy */ 3302181641Skmacy KASSERT(ptetemp != 0, ("src_pte not set")); 3303181641Skmacy PT_SET_VA_MA(dst_pte, ptetemp & ~(PG_W | PG_M | PG_A), TRUE /* XXX debug */); 3304181641Skmacy KASSERT(*dst_pte == (ptetemp & ~(PG_W | PG_M | PG_A)), 3305181641Skmacy ("no pmap copy expected: 0x%jx saw: 0x%jx", 3306181641Skmacy ptetemp & ~(PG_W | PG_M | PG_A), *dst_pte)); 3307181641Skmacy dst_pmap->pm_stats.resident_count++; 3308181641Skmacy } else { 3309181641Skmacy free = NULL; 3310240151Skib if (pmap_unwire_ptp(dst_pmap, dstmpte, 3311240151Skib &free)) { 3312181641Skmacy pmap_invalidate_page(dst_pmap, 3313181641Skmacy addr); 3314181641Skmacy pmap_free_zero_pages(free); 3315181641Skmacy } 3316230435Salc goto out; 3317181641Skmacy } 3318181641Skmacy if (dstmpte->wire_count >= srcmpte->wire_count) 3319181641Skmacy break; 3320181641Skmacy } 3321181641Skmacy addr += PAGE_SIZE; 3322181641Skmacy src_pte++; 3323181641Skmacy } 3324181641Skmacy } 3325230435Salcout: 3326181641Skmacy PT_UPDATES_FLUSH(); 3327181641Skmacy sched_unpin(); 3328181641Skmacy vm_page_unlock_queues(); 3329181641Skmacy PMAP_UNLOCK(src_pmap); 3330181641Skmacy PMAP_UNLOCK(dst_pmap); 3331216960Scperciva 3332216960Scperciva#ifdef HAMFISTED_LOCKING 3333216960Scperciva mtx_unlock(&createdelete_lock); 3334216960Scperciva#endif 3335181641Skmacy} 3336181641Skmacy 3337196723Sadrianstatic __inline void 3338196723Sadrianpagezero(void *page) 3339196723Sadrian{ 3340196723Sadrian#if defined(I686_CPU) 3341196723Sadrian if (cpu_class == CPUCLASS_686) { 3342196723Sadrian#if defined(CPU_ENABLE_SSE) 3343196723Sadrian if (cpu_feature & CPUID_SSE2) 3344196723Sadrian sse2_pagezero(page); 3345196723Sadrian else 3346196723Sadrian#endif 3347196723Sadrian i686_pagezero(page); 3348196723Sadrian } else 3349196723Sadrian#endif 3350196723Sadrian bzero(page, PAGE_SIZE); 3351196723Sadrian} 3352196723Sadrian 3353181641Skmacy/* 3354181641Skmacy * pmap_zero_page zeros the specified hardware page by mapping 3355181641Skmacy * the page into KVM and using bzero to clear its contents. 3356181641Skmacy */ 3357181641Skmacyvoid 3358181641Skmacypmap_zero_page(vm_page_t m) 3359181641Skmacy{ 3360181641Skmacy struct sysmaps *sysmaps; 3361181641Skmacy 3362181641Skmacy sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)]; 3363181641Skmacy mtx_lock(&sysmaps->lock); 3364181641Skmacy if (*sysmaps->CMAP2) 3365181641Skmacy panic("pmap_zero_page: CMAP2 busy"); 3366181641Skmacy sched_pin(); 3367215587Scperciva PT_SET_MA(sysmaps->CADDR2, PG_V | PG_RW | VM_PAGE_TO_MACH(m) | PG_A | PG_M); 3368181641Skmacy pagezero(sysmaps->CADDR2); 3369181641Skmacy PT_SET_MA(sysmaps->CADDR2, 0); 3370181641Skmacy sched_unpin(); 3371181641Skmacy mtx_unlock(&sysmaps->lock); 3372181641Skmacy} 3373181641Skmacy 3374181641Skmacy/* 3375181641Skmacy * pmap_zero_page_area zeros the specified hardware page by mapping 3376181641Skmacy * the page into KVM and using bzero to clear its contents. 3377181641Skmacy * 3378181641Skmacy * off and size may not cover an area beyond a single hardware page. 3379181641Skmacy */ 3380181641Skmacyvoid 3381181641Skmacypmap_zero_page_area(vm_page_t m, int off, int size) 3382181641Skmacy{ 3383181641Skmacy struct sysmaps *sysmaps; 3384181641Skmacy 3385181641Skmacy sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)]; 3386181641Skmacy mtx_lock(&sysmaps->lock); 3387181641Skmacy if (*sysmaps->CMAP2) 3388230435Salc panic("pmap_zero_page_area: CMAP2 busy"); 3389181641Skmacy sched_pin(); 3390215587Scperciva PT_SET_MA(sysmaps->CADDR2, PG_V | PG_RW | VM_PAGE_TO_MACH(m) | PG_A | PG_M); 3391181641Skmacy 3392181641Skmacy if (off == 0 && size == PAGE_SIZE) 3393181641Skmacy pagezero(sysmaps->CADDR2); 3394181641Skmacy else 3395181641Skmacy bzero((char *)sysmaps->CADDR2 + off, size); 3396181641Skmacy PT_SET_MA(sysmaps->CADDR2, 0); 3397181641Skmacy sched_unpin(); 3398181641Skmacy mtx_unlock(&sysmaps->lock); 3399181641Skmacy} 3400181641Skmacy 3401181641Skmacy/* 3402181641Skmacy * pmap_zero_page_idle zeros the specified hardware page by mapping 3403181641Skmacy * the page into KVM and using bzero to clear its contents. This 3404181641Skmacy * is intended to be called from the vm_pagezero process only and 3405181641Skmacy * outside of Giant. 3406181641Skmacy */ 3407181641Skmacyvoid 3408181641Skmacypmap_zero_page_idle(vm_page_t m) 3409181641Skmacy{ 3410181641Skmacy 3411181641Skmacy if (*CMAP3) 3412230435Salc panic("pmap_zero_page_idle: CMAP3 busy"); 3413181641Skmacy sched_pin(); 3414215587Scperciva PT_SET_MA(CADDR3, PG_V | PG_RW | VM_PAGE_TO_MACH(m) | PG_A | PG_M); 3415181641Skmacy pagezero(CADDR3); 3416181641Skmacy PT_SET_MA(CADDR3, 0); 3417181641Skmacy sched_unpin(); 3418181641Skmacy} 3419181641Skmacy 3420181641Skmacy/* 3421181641Skmacy * pmap_copy_page copies the specified (machine independent) 3422181641Skmacy * page by mapping the page into virtual memory and using 3423181641Skmacy * bcopy to copy the page, one machine dependent page at a 3424181641Skmacy * time. 3425181641Skmacy */ 3426181641Skmacyvoid 3427181641Skmacypmap_copy_page(vm_page_t src, vm_page_t dst) 3428181641Skmacy{ 3429181641Skmacy struct sysmaps *sysmaps; 3430181641Skmacy 3431181641Skmacy sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)]; 3432181641Skmacy mtx_lock(&sysmaps->lock); 3433181641Skmacy if (*sysmaps->CMAP1) 3434181641Skmacy panic("pmap_copy_page: CMAP1 busy"); 3435181641Skmacy if (*sysmaps->CMAP2) 3436181641Skmacy panic("pmap_copy_page: CMAP2 busy"); 3437181641Skmacy sched_pin(); 3438215587Scperciva PT_SET_MA(sysmaps->CADDR1, PG_V | VM_PAGE_TO_MACH(src) | PG_A); 3439215587Scperciva PT_SET_MA(sysmaps->CADDR2, PG_V | PG_RW | VM_PAGE_TO_MACH(dst) | PG_A | PG_M); 3440181641Skmacy bcopy(sysmaps->CADDR1, sysmaps->CADDR2, PAGE_SIZE); 3441181641Skmacy PT_SET_MA(sysmaps->CADDR1, 0); 3442181641Skmacy PT_SET_MA(sysmaps->CADDR2, 0); 3443181641Skmacy sched_unpin(); 3444181641Skmacy mtx_unlock(&sysmaps->lock); 3445181641Skmacy} 3446181641Skmacy 3447251897Sscottlint unmapped_buf_allowed = 1; 3448251897Sscottl 3449248814Skibvoid 3450248814Skibpmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[], 3451248814Skib vm_offset_t b_offset, int xfersize) 3452248814Skib{ 3453248814Skib struct sysmaps *sysmaps; 3454248814Skib vm_page_t a_pg, b_pg; 3455248814Skib char *a_cp, *b_cp; 3456248814Skib vm_offset_t a_pg_offset, b_pg_offset; 3457248814Skib int cnt; 3458248814Skib 3459248814Skib sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)]; 3460248814Skib mtx_lock(&sysmaps->lock); 3461248814Skib if (*sysmaps->CMAP1 != 0) 3462248814Skib panic("pmap_copy_pages: CMAP1 busy"); 3463248814Skib if (*sysmaps->CMAP2 != 0) 3464248814Skib panic("pmap_copy_pages: CMAP2 busy"); 3465248814Skib sched_pin(); 3466248814Skib while (xfersize > 0) { 3467248814Skib a_pg = ma[a_offset >> PAGE_SHIFT]; 3468248814Skib a_pg_offset = a_offset & PAGE_MASK; 3469248814Skib cnt = min(xfersize, PAGE_SIZE - a_pg_offset); 3470248814Skib b_pg = mb[b_offset >> PAGE_SHIFT]; 3471248814Skib b_pg_offset = b_offset & PAGE_MASK; 3472248814Skib cnt = min(cnt, PAGE_SIZE - b_pg_offset); 3473248814Skib PT_SET_MA(sysmaps->CADDR1, PG_V | VM_PAGE_TO_MACH(a_pg) | PG_A); 3474248814Skib PT_SET_MA(sysmaps->CADDR2, PG_V | PG_RW | 3475248814Skib VM_PAGE_TO_MACH(b_pg) | PG_A | PG_M); 3476248814Skib a_cp = sysmaps->CADDR1 + a_pg_offset; 3477248814Skib b_cp = sysmaps->CADDR2 + b_pg_offset; 3478248814Skib bcopy(a_cp, b_cp, cnt); 3479248814Skib a_offset += cnt; 3480248814Skib b_offset += cnt; 3481248814Skib xfersize -= cnt; 3482248814Skib } 3483248814Skib PT_SET_MA(sysmaps->CADDR1, 0); 3484248814Skib PT_SET_MA(sysmaps->CADDR2, 0); 3485248814Skib sched_unpin(); 3486248814Skib mtx_unlock(&sysmaps->lock); 3487248814Skib} 3488248814Skib 3489181641Skmacy/* 3490181641Skmacy * Returns true if the pmap's pv is one of the first 3491181641Skmacy * 16 pvs linked to from this page. This count may 3492181641Skmacy * be changed upwards or downwards in the future; it 3493181641Skmacy * is only necessary that true be returned for a small 3494181641Skmacy * subset of pmaps for proper page aging. 3495181641Skmacy */ 3496181641Skmacyboolean_t 3497181641Skmacypmap_page_exists_quick(pmap_t pmap, vm_page_t m) 3498181641Skmacy{ 3499181641Skmacy pv_entry_t pv; 3500181641Skmacy int loops = 0; 3501208990Salc boolean_t rv; 3502181641Skmacy 3503224746Skib KASSERT((m->oflags & VPO_UNMANAGED) == 0, 3504208990Salc ("pmap_page_exists_quick: page %p is not managed", m)); 3505208990Salc rv = FALSE; 3506208990Salc vm_page_lock_queues(); 3507181641Skmacy TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 3508181641Skmacy if (PV_PMAP(pv) == pmap) { 3509208990Salc rv = TRUE; 3510208990Salc break; 3511181641Skmacy } 3512181641Skmacy loops++; 3513181641Skmacy if (loops >= 16) 3514181641Skmacy break; 3515181641Skmacy } 3516208990Salc vm_page_unlock_queues(); 3517208990Salc return (rv); 3518181641Skmacy} 3519181641Skmacy 3520181641Skmacy/* 3521181641Skmacy * pmap_page_wired_mappings: 3522181641Skmacy * 3523181641Skmacy * Return the number of managed mappings to the given physical page 3524181641Skmacy * that are wired. 3525181641Skmacy */ 3526181641Skmacyint 3527181641Skmacypmap_page_wired_mappings(vm_page_t m) 3528181641Skmacy{ 3529181641Skmacy pv_entry_t pv; 3530181641Skmacy pt_entry_t *pte; 3531181641Skmacy pmap_t pmap; 3532181641Skmacy int count; 3533181641Skmacy 3534181641Skmacy count = 0; 3535224746Skib if ((m->oflags & VPO_UNMANAGED) != 0) 3536181641Skmacy return (count); 3537207796Salc vm_page_lock_queues(); 3538181641Skmacy sched_pin(); 3539181641Skmacy TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 3540181641Skmacy pmap = PV_PMAP(pv); 3541181641Skmacy PMAP_LOCK(pmap); 3542181641Skmacy pte = pmap_pte_quick(pmap, pv->pv_va); 3543181641Skmacy if ((*pte & PG_W) != 0) 3544181641Skmacy count++; 3545181641Skmacy PMAP_UNLOCK(pmap); 3546181641Skmacy } 3547181641Skmacy sched_unpin(); 3548207796Salc vm_page_unlock_queues(); 3549181641Skmacy return (count); 3550181641Skmacy} 3551181641Skmacy 3552181641Skmacy/* 3553230431Salc * Returns TRUE if the given page is mapped. Otherwise, returns FALSE. 3554181747Skmacy */ 3555181747Skmacyboolean_t 3556181747Skmacypmap_page_is_mapped(vm_page_t m) 3557181747Skmacy{ 3558181747Skmacy 3559224746Skib if ((m->oflags & VPO_UNMANAGED) != 0) 3560181747Skmacy return (FALSE); 3561230431Salc return (!TAILQ_EMPTY(&m->md.pv_list)); 3562181747Skmacy} 3563181747Skmacy 3564181747Skmacy/* 3565181641Skmacy * Remove all pages from specified address space 3566181641Skmacy * this aids process exit speeds. Also, this code 3567181641Skmacy * is special cased for current process only, but 3568181641Skmacy * can have the more generic (and slightly slower) 3569181641Skmacy * mode enabled. This is much faster than pmap_remove 3570181641Skmacy * in the case of running down an entire address space. 3571181641Skmacy */ 3572181641Skmacyvoid 3573181641Skmacypmap_remove_pages(pmap_t pmap) 3574181641Skmacy{ 3575181641Skmacy pt_entry_t *pte, tpte; 3576181641Skmacy vm_page_t m, free = NULL; 3577181641Skmacy pv_entry_t pv; 3578181641Skmacy struct pv_chunk *pc, *npc; 3579181641Skmacy int field, idx; 3580181641Skmacy int32_t bit; 3581181641Skmacy uint32_t inuse, bitmask; 3582181641Skmacy int allfree; 3583181641Skmacy 3584181641Skmacy CTR1(KTR_PMAP, "pmap_remove_pages: pmap=%p", pmap); 3585181641Skmacy 3586181641Skmacy if (pmap != vmspace_pmap(curthread->td_proc->p_vmspace)) { 3587181641Skmacy printf("warning: pmap_remove_pages called with non-current pmap\n"); 3588181641Skmacy return; 3589181641Skmacy } 3590181641Skmacy vm_page_lock_queues(); 3591181641Skmacy KASSERT(pmap_is_current(pmap), ("removing pages from non-current pmap")); 3592181641Skmacy PMAP_LOCK(pmap); 3593181641Skmacy sched_pin(); 3594181641Skmacy TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) { 3595241518Salc KASSERT(pc->pc_pmap == pmap, ("Wrong pmap %p %p", pmap, 3596241518Salc pc->pc_pmap)); 3597181641Skmacy allfree = 1; 3598181641Skmacy for (field = 0; field < _NPCM; field++) { 3599238005Salc inuse = ~pc->pc_map[field] & pc_freemask[field]; 3600181641Skmacy while (inuse != 0) { 3601181641Skmacy bit = bsfl(inuse); 3602181641Skmacy bitmask = 1UL << bit; 3603181641Skmacy idx = field * 32 + bit; 3604181641Skmacy pv = &pc->pc_pventry[idx]; 3605181641Skmacy inuse &= ~bitmask; 3606181641Skmacy 3607181641Skmacy pte = vtopte(pv->pv_va); 3608181641Skmacy tpte = *pte ? xpmap_mtop(*pte) : 0; 3609181641Skmacy 3610181641Skmacy if (tpte == 0) { 3611181641Skmacy printf( 3612181641Skmacy "TPTE at %p IS ZERO @ VA %08x\n", 3613181641Skmacy pte, pv->pv_va); 3614181641Skmacy panic("bad pte"); 3615181641Skmacy } 3616181641Skmacy 3617181641Skmacy/* 3618181641Skmacy * We cannot remove wired pages from a process' mapping at this time 3619181641Skmacy */ 3620181641Skmacy if (tpte & PG_W) { 3621181641Skmacy allfree = 0; 3622181641Skmacy continue; 3623181641Skmacy } 3624181641Skmacy 3625181641Skmacy m = PHYS_TO_VM_PAGE(tpte & PG_FRAME); 3626181641Skmacy KASSERT(m->phys_addr == (tpte & PG_FRAME), 3627181641Skmacy ("vm_page_t %p phys_addr mismatch %016jx %016jx", 3628181641Skmacy m, (uintmax_t)m->phys_addr, 3629181641Skmacy (uintmax_t)tpte)); 3630181641Skmacy 3631181641Skmacy KASSERT(m < &vm_page_array[vm_page_array_size], 3632181641Skmacy ("pmap_remove_pages: bad tpte %#jx", 3633181641Skmacy (uintmax_t)tpte)); 3634181641Skmacy 3635181641Skmacy 3636181641Skmacy PT_CLEAR_VA(pte, FALSE); 3637181641Skmacy 3638181641Skmacy /* 3639181641Skmacy * Update the vm_page_t clean/reference bits. 3640181641Skmacy */ 3641181641Skmacy if (tpte & PG_M) 3642181641Skmacy vm_page_dirty(m); 3643181641Skmacy 3644181641Skmacy TAILQ_REMOVE(&m->md.pv_list, pv, pv_list); 3645181641Skmacy if (TAILQ_EMPTY(&m->md.pv_list)) 3646225418Skib vm_page_aflag_clear(m, PGA_WRITEABLE); 3647181641Skmacy 3648181641Skmacy pmap_unuse_pt(pmap, pv->pv_va, &free); 3649181641Skmacy 3650181641Skmacy /* Mark free */ 3651181641Skmacy PV_STAT(pv_entry_frees++); 3652181641Skmacy PV_STAT(pv_entry_spare++); 3653181641Skmacy pv_entry_count--; 3654181641Skmacy pc->pc_map[field] |= bitmask; 3655181641Skmacy pmap->pm_stats.resident_count--; 3656181641Skmacy } 3657181641Skmacy } 3658181641Skmacy PT_UPDATES_FLUSH(); 3659181641Skmacy if (allfree) { 3660181641Skmacy TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 3661237950Salc free_pv_chunk(pc); 3662181641Skmacy } 3663181641Skmacy } 3664181641Skmacy PT_UPDATES_FLUSH(); 3665181641Skmacy if (*PMAP1) 3666181641Skmacy PT_SET_MA(PADDR1, 0); 3667181641Skmacy 3668181641Skmacy sched_unpin(); 3669181641Skmacy pmap_invalidate_all(pmap); 3670181641Skmacy vm_page_unlock_queues(); 3671181641Skmacy PMAP_UNLOCK(pmap); 3672181641Skmacy pmap_free_zero_pages(free); 3673181641Skmacy} 3674181641Skmacy 3675181641Skmacy/* 3676181641Skmacy * pmap_is_modified: 3677181641Skmacy * 3678181641Skmacy * Return whether or not the specified physical page was modified 3679181641Skmacy * in any physical maps. 3680181641Skmacy */ 3681181641Skmacyboolean_t 3682181641Skmacypmap_is_modified(vm_page_t m) 3683181641Skmacy{ 3684181641Skmacy pv_entry_t pv; 3685181641Skmacy pt_entry_t *pte; 3686181641Skmacy pmap_t pmap; 3687181641Skmacy boolean_t rv; 3688181641Skmacy 3689224746Skib KASSERT((m->oflags & VPO_UNMANAGED) == 0, 3690208504Salc ("pmap_is_modified: page %p is not managed", m)); 3691181641Skmacy rv = FALSE; 3692208504Salc 3693208504Salc /* 3694225418Skib * If the page is not VPO_BUSY, then PGA_WRITEABLE cannot be 3695225418Skib * concurrently set while the object is locked. Thus, if PGA_WRITEABLE 3696208504Salc * is clear, no PTEs can have PG_M set. 3697208504Salc */ 3698208504Salc VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 3699208504Salc if ((m->oflags & VPO_BUSY) == 0 && 3700225418Skib (m->aflags & PGA_WRITEABLE) == 0) 3701181641Skmacy return (rv); 3702208504Salc vm_page_lock_queues(); 3703181641Skmacy sched_pin(); 3704181641Skmacy TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 3705181641Skmacy pmap = PV_PMAP(pv); 3706181641Skmacy PMAP_LOCK(pmap); 3707181641Skmacy pte = pmap_pte_quick(pmap, pv->pv_va); 3708181641Skmacy rv = (*pte & PG_M) != 0; 3709181641Skmacy PMAP_UNLOCK(pmap); 3710181641Skmacy if (rv) 3711181641Skmacy break; 3712181641Skmacy } 3713181641Skmacy if (*PMAP1) 3714181641Skmacy PT_SET_MA(PADDR1, 0); 3715181641Skmacy sched_unpin(); 3716208504Salc vm_page_unlock_queues(); 3717181641Skmacy return (rv); 3718181641Skmacy} 3719181641Skmacy 3720181641Skmacy/* 3721181641Skmacy * pmap_is_prefaultable: 3722181641Skmacy * 3723181641Skmacy * Return whether or not the specified virtual address is elgible 3724181641Skmacy * for prefault. 3725181641Skmacy */ 3726181641Skmacystatic boolean_t 3727181641Skmacypmap_is_prefaultable_locked(pmap_t pmap, vm_offset_t addr) 3728181641Skmacy{ 3729181641Skmacy pt_entry_t *pte; 3730181641Skmacy boolean_t rv = FALSE; 3731181641Skmacy 3732181641Skmacy return (rv); 3733181641Skmacy 3734181641Skmacy if (pmap_is_current(pmap) && *pmap_pde(pmap, addr)) { 3735181641Skmacy pte = vtopte(addr); 3736181641Skmacy rv = (*pte == 0); 3737181641Skmacy } 3738181641Skmacy return (rv); 3739181641Skmacy} 3740181641Skmacy 3741181641Skmacyboolean_t 3742181641Skmacypmap_is_prefaultable(pmap_t pmap, vm_offset_t addr) 3743181641Skmacy{ 3744181641Skmacy boolean_t rv; 3745181641Skmacy 3746181641Skmacy PMAP_LOCK(pmap); 3747181641Skmacy rv = pmap_is_prefaultable_locked(pmap, addr); 3748181641Skmacy PMAP_UNLOCK(pmap); 3749181641Skmacy return (rv); 3750181641Skmacy} 3751181641Skmacy 3752207155Salcboolean_t 3753207155Salcpmap_is_referenced(vm_page_t m) 3754207155Salc{ 3755207155Salc pv_entry_t pv; 3756207155Salc pt_entry_t *pte; 3757207155Salc pmap_t pmap; 3758207155Salc boolean_t rv; 3759207155Salc 3760224746Skib KASSERT((m->oflags & VPO_UNMANAGED) == 0, 3761208574Salc ("pmap_is_referenced: page %p is not managed", m)); 3762207155Salc rv = FALSE; 3763208574Salc vm_page_lock_queues(); 3764207155Salc sched_pin(); 3765207155Salc TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 3766207155Salc pmap = PV_PMAP(pv); 3767207155Salc PMAP_LOCK(pmap); 3768207155Salc pte = pmap_pte_quick(pmap, pv->pv_va); 3769207155Salc rv = (*pte & (PG_A | PG_V)) == (PG_A | PG_V); 3770207155Salc PMAP_UNLOCK(pmap); 3771207155Salc if (rv) 3772207155Salc break; 3773207155Salc } 3774207155Salc if (*PMAP1) 3775207155Salc PT_SET_MA(PADDR1, 0); 3776207155Salc sched_unpin(); 3777208574Salc vm_page_unlock_queues(); 3778207155Salc return (rv); 3779207155Salc} 3780207155Salc 3781181641Skmacyvoid 3782181641Skmacypmap_map_readonly(pmap_t pmap, vm_offset_t va, int len) 3783181641Skmacy{ 3784181641Skmacy int i, npages = round_page(len) >> PAGE_SHIFT; 3785181641Skmacy for (i = 0; i < npages; i++) { 3786181641Skmacy pt_entry_t *pte; 3787181641Skmacy pte = pmap_pte(pmap, (vm_offset_t)(va + i*PAGE_SIZE)); 3788216843Scperciva vm_page_lock_queues(); 3789181641Skmacy pte_store(pte, xpmap_mtop(*pte & ~(PG_RW|PG_M))); 3790216843Scperciva vm_page_unlock_queues(); 3791181641Skmacy PMAP_MARK_PRIV(xpmap_mtop(*pte)); 3792181641Skmacy pmap_pte_release(pte); 3793181641Skmacy } 3794181641Skmacy} 3795181641Skmacy 3796181641Skmacyvoid 3797181641Skmacypmap_map_readwrite(pmap_t pmap, vm_offset_t va, int len) 3798181641Skmacy{ 3799181641Skmacy int i, npages = round_page(len) >> PAGE_SHIFT; 3800181641Skmacy for (i = 0; i < npages; i++) { 3801181641Skmacy pt_entry_t *pte; 3802181641Skmacy pte = pmap_pte(pmap, (vm_offset_t)(va + i*PAGE_SIZE)); 3803181641Skmacy PMAP_MARK_UNPRIV(xpmap_mtop(*pte)); 3804216843Scperciva vm_page_lock_queues(); 3805181641Skmacy pte_store(pte, xpmap_mtop(*pte) | (PG_RW|PG_M)); 3806216843Scperciva vm_page_unlock_queues(); 3807181641Skmacy pmap_pte_release(pte); 3808181641Skmacy } 3809181641Skmacy} 3810181641Skmacy 3811181641Skmacy/* 3812181641Skmacy * Clear the write and modified bits in each of the given page's mappings. 3813181641Skmacy */ 3814181641Skmacyvoid 3815181641Skmacypmap_remove_write(vm_page_t m) 3816181641Skmacy{ 3817181641Skmacy pv_entry_t pv; 3818181641Skmacy pmap_t pmap; 3819181641Skmacy pt_entry_t oldpte, *pte; 3820181641Skmacy 3821224746Skib KASSERT((m->oflags & VPO_UNMANAGED) == 0, 3822208175Salc ("pmap_remove_write: page %p is not managed", m)); 3823208175Salc 3824208175Salc /* 3825225418Skib * If the page is not VPO_BUSY, then PGA_WRITEABLE cannot be set by 3826225418Skib * another thread while the object is locked. Thus, if PGA_WRITEABLE 3827208175Salc * is clear, no page table entries need updating. 3828208175Salc */ 3829208175Salc VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 3830208175Salc if ((m->oflags & VPO_BUSY) == 0 && 3831225418Skib (m->aflags & PGA_WRITEABLE) == 0) 3832181641Skmacy return; 3833207796Salc vm_page_lock_queues(); 3834181641Skmacy sched_pin(); 3835181641Skmacy TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 3836181641Skmacy pmap = PV_PMAP(pv); 3837181641Skmacy PMAP_LOCK(pmap); 3838181641Skmacy pte = pmap_pte_quick(pmap, pv->pv_va); 3839181641Skmacyretry: 3840181641Skmacy oldpte = *pte; 3841181641Skmacy if ((oldpte & PG_RW) != 0) { 3842188341Skmacy vm_paddr_t newpte = oldpte & ~(PG_RW | PG_M); 3843188341Skmacy 3844181641Skmacy /* 3845181641Skmacy * Regardless of whether a pte is 32 or 64 bits 3846181641Skmacy * in size, PG_RW and PG_M are among the least 3847181641Skmacy * significant 32 bits. 3848181641Skmacy */ 3849188341Skmacy PT_SET_VA_MA(pte, newpte, TRUE); 3850188341Skmacy if (*pte != newpte) 3851181641Skmacy goto retry; 3852188341Skmacy 3853181641Skmacy if ((oldpte & PG_M) != 0) 3854181641Skmacy vm_page_dirty(m); 3855181641Skmacy pmap_invalidate_page(pmap, pv->pv_va); 3856181641Skmacy } 3857181641Skmacy PMAP_UNLOCK(pmap); 3858181641Skmacy } 3859225418Skib vm_page_aflag_clear(m, PGA_WRITEABLE); 3860181641Skmacy PT_UPDATES_FLUSH(); 3861181641Skmacy if (*PMAP1) 3862181641Skmacy PT_SET_MA(PADDR1, 0); 3863181641Skmacy sched_unpin(); 3864207796Salc vm_page_unlock_queues(); 3865181641Skmacy} 3866181641Skmacy 3867181641Skmacy/* 3868181641Skmacy * pmap_ts_referenced: 3869181641Skmacy * 3870181641Skmacy * Return a count of reference bits for a page, clearing those bits. 3871181641Skmacy * It is not necessary for every reference bit to be cleared, but it 3872181641Skmacy * is necessary that 0 only be returned when there are truly no 3873181641Skmacy * reference bits set. 3874181641Skmacy * 3875181641Skmacy * XXX: The exact number of bits to check and clear is a matter that 3876181641Skmacy * should be tested and standardized at some point in the future for 3877181641Skmacy * optimal aging of shared pages. 3878181641Skmacy */ 3879181641Skmacyint 3880181641Skmacypmap_ts_referenced(vm_page_t m) 3881181641Skmacy{ 3882181641Skmacy pv_entry_t pv, pvf, pvn; 3883181641Skmacy pmap_t pmap; 3884181641Skmacy pt_entry_t *pte; 3885181641Skmacy int rtval = 0; 3886181641Skmacy 3887224746Skib KASSERT((m->oflags & VPO_UNMANAGED) == 0, 3888208990Salc ("pmap_ts_referenced: page %p is not managed", m)); 3889208990Salc vm_page_lock_queues(); 3890181641Skmacy sched_pin(); 3891181641Skmacy if ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) { 3892181641Skmacy pvf = pv; 3893181641Skmacy do { 3894181641Skmacy pvn = TAILQ_NEXT(pv, pv_list); 3895181641Skmacy TAILQ_REMOVE(&m->md.pv_list, pv, pv_list); 3896181641Skmacy TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list); 3897181641Skmacy pmap = PV_PMAP(pv); 3898181641Skmacy PMAP_LOCK(pmap); 3899181641Skmacy pte = pmap_pte_quick(pmap, pv->pv_va); 3900181641Skmacy if ((*pte & PG_A) != 0) { 3901181641Skmacy PT_SET_VA_MA(pte, *pte & ~PG_A, FALSE); 3902181641Skmacy pmap_invalidate_page(pmap, pv->pv_va); 3903181641Skmacy rtval++; 3904181641Skmacy if (rtval > 4) 3905181641Skmacy pvn = NULL; 3906181641Skmacy } 3907181641Skmacy PMAP_UNLOCK(pmap); 3908181641Skmacy } while ((pv = pvn) != NULL && pv != pvf); 3909181641Skmacy } 3910181641Skmacy PT_UPDATES_FLUSH(); 3911181641Skmacy if (*PMAP1) 3912181641Skmacy PT_SET_MA(PADDR1, 0); 3913181641Skmacy sched_unpin(); 3914208990Salc vm_page_unlock_queues(); 3915181641Skmacy return (rtval); 3916181641Skmacy} 3917181641Skmacy 3918181641Skmacy/* 3919181641Skmacy * Clear the modify bits on the specified physical page. 3920181641Skmacy */ 3921181641Skmacyvoid 3922181641Skmacypmap_clear_modify(vm_page_t m) 3923181641Skmacy{ 3924181641Skmacy pv_entry_t pv; 3925181641Skmacy pmap_t pmap; 3926181641Skmacy pt_entry_t *pte; 3927181641Skmacy 3928224746Skib KASSERT((m->oflags & VPO_UNMANAGED) == 0, 3929208504Salc ("pmap_clear_modify: page %p is not managed", m)); 3930208504Salc VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 3931208504Salc KASSERT((m->oflags & VPO_BUSY) == 0, 3932208504Salc ("pmap_clear_modify: page %p is busy", m)); 3933208504Salc 3934208504Salc /* 3935225418Skib * If the page is not PGA_WRITEABLE, then no PTEs can have PG_M set. 3936208504Salc * If the object containing the page is locked and the page is not 3937225418Skib * VPO_BUSY, then PGA_WRITEABLE cannot be concurrently set. 3938208504Salc */ 3939225418Skib if ((m->aflags & PGA_WRITEABLE) == 0) 3940181641Skmacy return; 3941208504Salc vm_page_lock_queues(); 3942181641Skmacy sched_pin(); 3943181641Skmacy TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 3944181641Skmacy pmap = PV_PMAP(pv); 3945181641Skmacy PMAP_LOCK(pmap); 3946181641Skmacy pte = pmap_pte_quick(pmap, pv->pv_va); 3947230435Salc if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) { 3948181641Skmacy /* 3949181641Skmacy * Regardless of whether a pte is 32 or 64 bits 3950181641Skmacy * in size, PG_M is among the least significant 3951181641Skmacy * 32 bits. 3952181641Skmacy */ 3953181641Skmacy PT_SET_VA_MA(pte, *pte & ~PG_M, FALSE); 3954181641Skmacy pmap_invalidate_page(pmap, pv->pv_va); 3955181641Skmacy } 3956181641Skmacy PMAP_UNLOCK(pmap); 3957181641Skmacy } 3958181641Skmacy sched_unpin(); 3959208504Salc vm_page_unlock_queues(); 3960181641Skmacy} 3961181641Skmacy 3962181641Skmacy/* 3963181641Skmacy * pmap_clear_reference: 3964181641Skmacy * 3965181641Skmacy * Clear the reference bit on the specified physical page. 3966181641Skmacy */ 3967181641Skmacyvoid 3968181641Skmacypmap_clear_reference(vm_page_t m) 3969181641Skmacy{ 3970181641Skmacy pv_entry_t pv; 3971181641Skmacy pmap_t pmap; 3972181641Skmacy pt_entry_t *pte; 3973181641Skmacy 3974224746Skib KASSERT((m->oflags & VPO_UNMANAGED) == 0, 3975208504Salc ("pmap_clear_reference: page %p is not managed", m)); 3976208504Salc vm_page_lock_queues(); 3977181641Skmacy sched_pin(); 3978181641Skmacy TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 3979181641Skmacy pmap = PV_PMAP(pv); 3980181641Skmacy PMAP_LOCK(pmap); 3981181641Skmacy pte = pmap_pte_quick(pmap, pv->pv_va); 3982181641Skmacy if ((*pte & PG_A) != 0) { 3983181641Skmacy /* 3984181641Skmacy * Regardless of whether a pte is 32 or 64 bits 3985181641Skmacy * in size, PG_A is among the least significant 3986181641Skmacy * 32 bits. 3987181641Skmacy */ 3988181641Skmacy PT_SET_VA_MA(pte, *pte & ~PG_A, FALSE); 3989181641Skmacy pmap_invalidate_page(pmap, pv->pv_va); 3990181641Skmacy } 3991181641Skmacy PMAP_UNLOCK(pmap); 3992181641Skmacy } 3993181641Skmacy sched_unpin(); 3994208504Salc vm_page_unlock_queues(); 3995181641Skmacy} 3996181641Skmacy 3997181641Skmacy/* 3998181641Skmacy * Miscellaneous support routines follow 3999181641Skmacy */ 4000181641Skmacy 4001181641Skmacy/* 4002181641Skmacy * Map a set of physical memory pages into the kernel virtual 4003181641Skmacy * address space. Return a pointer to where it is mapped. This 4004181641Skmacy * routine is intended to be used for mapping device memory, 4005181641Skmacy * NOT real memory. 4006181641Skmacy */ 4007181641Skmacyvoid * 4008181641Skmacypmap_mapdev_attr(vm_paddr_t pa, vm_size_t size, int mode) 4009181641Skmacy{ 4010195949Skib vm_offset_t va, offset; 4011195949Skib vm_size_t tmpsize; 4012181641Skmacy 4013181641Skmacy offset = pa & PAGE_MASK; 4014181641Skmacy size = roundup(offset + size, PAGE_SIZE); 4015181641Skmacy pa = pa & PG_FRAME; 4016181641Skmacy 4017181641Skmacy if (pa < KERNLOAD && pa + size <= KERNLOAD) 4018181641Skmacy va = KERNBASE + pa; 4019181641Skmacy else 4020181641Skmacy va = kmem_alloc_nofault(kernel_map, size); 4021181641Skmacy if (!va) 4022181641Skmacy panic("pmap_mapdev: Couldn't alloc kernel virtual memory"); 4023181641Skmacy 4024195949Skib for (tmpsize = 0; tmpsize < size; tmpsize += PAGE_SIZE) 4025195949Skib pmap_kenter_attr(va + tmpsize, pa + tmpsize, mode); 4026195949Skib pmap_invalidate_range(kernel_pmap, va, va + tmpsize); 4027195949Skib pmap_invalidate_cache_range(va, va + size); 4028181641Skmacy return ((void *)(va + offset)); 4029181641Skmacy} 4030181641Skmacy 4031181641Skmacyvoid * 4032181641Skmacypmap_mapdev(vm_paddr_t pa, vm_size_t size) 4033181641Skmacy{ 4034181641Skmacy 4035181641Skmacy return (pmap_mapdev_attr(pa, size, PAT_UNCACHEABLE)); 4036181641Skmacy} 4037181641Skmacy 4038181641Skmacyvoid * 4039181641Skmacypmap_mapbios(vm_paddr_t pa, vm_size_t size) 4040181641Skmacy{ 4041181641Skmacy 4042181641Skmacy return (pmap_mapdev_attr(pa, size, PAT_WRITE_BACK)); 4043181641Skmacy} 4044181641Skmacy 4045181641Skmacyvoid 4046181641Skmacypmap_unmapdev(vm_offset_t va, vm_size_t size) 4047181641Skmacy{ 4048240754Salc vm_offset_t base, offset; 4049181641Skmacy 4050181641Skmacy if (va >= KERNBASE && va + size <= KERNBASE + KERNLOAD) 4051181641Skmacy return; 4052181641Skmacy base = trunc_page(va); 4053181641Skmacy offset = va & PAGE_MASK; 4054181641Skmacy size = roundup(offset + size, PAGE_SIZE); 4055181641Skmacy kmem_free(kernel_map, base, size); 4056181641Skmacy} 4057181641Skmacy 4058195774Salc/* 4059195774Salc * Sets the memory attribute for the specified page. 4060195774Salc */ 4061195774Salcvoid 4062195774Salcpmap_page_set_memattr(vm_page_t m, vm_memattr_t ma) 4063195774Salc{ 4064195774Salc 4065195774Salc m->md.pat_mode = ma; 4066195949Skib if ((m->flags & PG_FICTITIOUS) != 0) 4067195949Skib return; 4068195774Salc 4069195774Salc /* 4070195774Salc * If "m" is a normal page, flush it from the cache. 4071195949Skib * See pmap_invalidate_cache_range(). 4072195949Skib * 4073195949Skib * First, try to find an existing mapping of the page by sf 4074195949Skib * buffer. sf_buf_invalidate_cache() modifies mapping and 4075195949Skib * flushes the cache. 4076195774Salc */ 4077195949Skib if (sf_buf_invalidate_cache(m)) 4078195949Skib return; 4079195949Skib 4080195949Skib /* 4081195949Skib * If page is not mapped by sf buffer, but CPU does not 4082195949Skib * support self snoop, map the page transient and do 4083195949Skib * invalidation. In the worst case, whole cache is flushed by 4084195949Skib * pmap_invalidate_cache_range(). 4085195949Skib */ 4086230435Salc if ((cpu_feature & CPUID_SS) == 0) 4087230435Salc pmap_flush_page(m); 4088230435Salc} 4089230435Salc 4090230435Salcstatic void 4091230435Salcpmap_flush_page(vm_page_t m) 4092230435Salc{ 4093230435Salc struct sysmaps *sysmaps; 4094230435Salc vm_offset_t sva, eva; 4095230435Salc 4096230435Salc if ((cpu_feature & CPUID_CLFSH) != 0) { 4097195949Skib sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)]; 4098195949Skib mtx_lock(&sysmaps->lock); 4099195949Skib if (*sysmaps->CMAP2) 4100230435Salc panic("pmap_flush_page: CMAP2 busy"); 4101195949Skib sched_pin(); 4102195949Skib PT_SET_MA(sysmaps->CADDR2, PG_V | PG_RW | 4103215587Scperciva VM_PAGE_TO_MACH(m) | PG_A | PG_M | 4104195949Skib pmap_cache_bits(m->md.pat_mode, 0)); 4105195949Skib invlcaddr(sysmaps->CADDR2); 4106195949Skib sva = (vm_offset_t)sysmaps->CADDR2; 4107195949Skib eva = sva + PAGE_SIZE; 4108230435Salc 4109230435Salc /* 4110230435Salc * Use mfence despite the ordering implied by 4111230435Salc * mtx_{un,}lock() because clflush is not guaranteed 4112230435Salc * to be ordered by any other instruction. 4113230435Salc */ 4114230435Salc mfence(); 4115230435Salc for (; sva < eva; sva += cpu_clflush_line_size) 4116230435Salc clflush(sva); 4117230435Salc mfence(); 4118195949Skib PT_SET_MA(sysmaps->CADDR2, 0); 4119195949Skib sched_unpin(); 4120195949Skib mtx_unlock(&sysmaps->lock); 4121230435Salc } else 4122230435Salc pmap_invalidate_cache(); 4123195774Salc} 4124195774Salc 4125230435Salc/* 4126230435Salc * Changes the specified virtual address range's memory type to that given by 4127230435Salc * the parameter "mode". The specified virtual address range must be 4128230435Salc * completely contained within either the kernel map. 4129230435Salc * 4130230435Salc * Returns zero if the change completed successfully, and either EINVAL or 4131230435Salc * ENOMEM if the change failed. Specifically, EINVAL is returned if some part 4132230435Salc * of the virtual address range was not mapped, and ENOMEM is returned if 4133230435Salc * there was insufficient memory available to complete the change. 4134230435Salc */ 4135181641Skmacyint 4136230435Salcpmap_change_attr(vm_offset_t va, vm_size_t size, int mode) 4137181641Skmacy{ 4138181641Skmacy vm_offset_t base, offset, tmpva; 4139181641Skmacy pt_entry_t *pte; 4140181641Skmacy u_int opte, npte; 4141181641Skmacy pd_entry_t *pde; 4142195949Skib boolean_t changed; 4143181641Skmacy 4144181641Skmacy base = trunc_page(va); 4145181641Skmacy offset = va & PAGE_MASK; 4146181641Skmacy size = roundup(offset + size, PAGE_SIZE); 4147181641Skmacy 4148181641Skmacy /* Only supported on kernel virtual addresses. */ 4149181641Skmacy if (base <= VM_MAXUSER_ADDRESS) 4150181641Skmacy return (EINVAL); 4151181641Skmacy 4152181641Skmacy /* 4MB pages and pages that aren't mapped aren't supported. */ 4153181641Skmacy for (tmpva = base; tmpva < (base + size); tmpva += PAGE_SIZE) { 4154181641Skmacy pde = pmap_pde(kernel_pmap, tmpva); 4155181641Skmacy if (*pde & PG_PS) 4156181641Skmacy return (EINVAL); 4157181641Skmacy if ((*pde & PG_V) == 0) 4158181641Skmacy return (EINVAL); 4159181641Skmacy pte = vtopte(va); 4160181641Skmacy if ((*pte & PG_V) == 0) 4161181641Skmacy return (EINVAL); 4162181641Skmacy } 4163181641Skmacy 4164195949Skib changed = FALSE; 4165195949Skib 4166181641Skmacy /* 4167181641Skmacy * Ok, all the pages exist and are 4k, so run through them updating 4168181641Skmacy * their cache mode. 4169181641Skmacy */ 4170181641Skmacy for (tmpva = base; size > 0; ) { 4171181641Skmacy pte = vtopte(tmpva); 4172181641Skmacy 4173181641Skmacy /* 4174181641Skmacy * The cache mode bits are all in the low 32-bits of the 4175181641Skmacy * PTE, so we can just spin on updating the low 32-bits. 4176181641Skmacy */ 4177181641Skmacy do { 4178181641Skmacy opte = *(u_int *)pte; 4179181641Skmacy npte = opte & ~(PG_PTE_PAT | PG_NC_PCD | PG_NC_PWT); 4180181641Skmacy npte |= pmap_cache_bits(mode, 0); 4181181641Skmacy PT_SET_VA_MA(pte, npte, TRUE); 4182181641Skmacy } while (npte != opte && (*pte != npte)); 4183195949Skib if (npte != opte) 4184195949Skib changed = TRUE; 4185181641Skmacy tmpva += PAGE_SIZE; 4186181641Skmacy size -= PAGE_SIZE; 4187181641Skmacy } 4188181641Skmacy 4189181641Skmacy /* 4190230435Salc * Flush CPU caches to make sure any data isn't cached that 4191230435Salc * shouldn't be, etc. 4192181641Skmacy */ 4193195949Skib if (changed) { 4194195949Skib pmap_invalidate_range(kernel_pmap, base, tmpva); 4195195949Skib pmap_invalidate_cache_range(base, tmpva); 4196195949Skib } 4197181641Skmacy return (0); 4198181641Skmacy} 4199181641Skmacy 4200181641Skmacy/* 4201181641Skmacy * perform the pmap work for mincore 4202181641Skmacy */ 4203181641Skmacyint 4204208504Salcpmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa) 4205181641Skmacy{ 4206181641Skmacy pt_entry_t *ptep, pte; 4207208504Salc vm_paddr_t pa; 4208208504Salc int val; 4209230435Salc 4210181641Skmacy PMAP_LOCK(pmap); 4211208504Salcretry: 4212181641Skmacy ptep = pmap_pte(pmap, addr); 4213181641Skmacy pte = (ptep != NULL) ? PT_GET(ptep) : 0; 4214181641Skmacy pmap_pte_release(ptep); 4215208504Salc val = 0; 4216208504Salc if ((pte & PG_V) != 0) { 4217208504Salc val |= MINCORE_INCORE; 4218208504Salc if ((pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) 4219208504Salc val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER; 4220208504Salc if ((pte & PG_A) != 0) 4221208504Salc val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER; 4222208504Salc } 4223208504Salc if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) != 4224208504Salc (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) && 4225208504Salc (pte & (PG_MANAGED | PG_V)) == (PG_MANAGED | PG_V)) { 4226208504Salc pa = pte & PG_FRAME; 4227208504Salc /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */ 4228208504Salc if (vm_page_pa_tryrelock(pmap, pa, locked_pa)) 4229208504Salc goto retry; 4230208504Salc } else 4231208504Salc PA_UNLOCK_COND(*locked_pa); 4232181641Skmacy PMAP_UNLOCK(pmap); 4233208504Salc return (val); 4234181641Skmacy} 4235181641Skmacy 4236181641Skmacyvoid 4237181641Skmacypmap_activate(struct thread *td) 4238181641Skmacy{ 4239181641Skmacy pmap_t pmap, oldpmap; 4240223758Sattilio u_int cpuid; 4241181641Skmacy u_int32_t cr3; 4242181641Skmacy 4243181641Skmacy critical_enter(); 4244181641Skmacy pmap = vmspace_pmap(td->td_proc->p_vmspace); 4245181641Skmacy oldpmap = PCPU_GET(curpmap); 4246223758Sattilio cpuid = PCPU_GET(cpuid); 4247181641Skmacy#if defined(SMP) 4248223758Sattilio CPU_CLR_ATOMIC(cpuid, &oldpmap->pm_active); 4249223758Sattilio CPU_SET_ATOMIC(cpuid, &pmap->pm_active); 4250181641Skmacy#else 4251223758Sattilio CPU_CLR(cpuid, &oldpmap->pm_active); 4252223758Sattilio CPU_SET(cpuid, &pmap->pm_active); 4253181641Skmacy#endif 4254181641Skmacy#ifdef PAE 4255181641Skmacy cr3 = vtophys(pmap->pm_pdpt); 4256181641Skmacy#else 4257181641Skmacy cr3 = vtophys(pmap->pm_pdir); 4258181641Skmacy#endif 4259181641Skmacy /* 4260181641Skmacy * pmap_activate is for the current thread on the current cpu 4261181641Skmacy */ 4262181641Skmacy td->td_pcb->pcb_cr3 = cr3; 4263181641Skmacy PT_UPDATES_FLUSH(); 4264181641Skmacy load_cr3(cr3); 4265181641Skmacy PCPU_SET(curpmap, pmap); 4266181641Skmacy critical_exit(); 4267181641Skmacy} 4268181641Skmacy 4269198341Smarcelvoid 4270198341Smarcelpmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz) 4271198341Smarcel{ 4272198341Smarcel} 4273198341Smarcel 4274181747Skmacy/* 4275181747Skmacy * Increase the starting virtual address of the given mapping if a 4276181747Skmacy * different alignment might result in more superpage mappings. 4277181747Skmacy */ 4278181747Skmacyvoid 4279181747Skmacypmap_align_superpage(vm_object_t object, vm_ooffset_t offset, 4280181747Skmacy vm_offset_t *addr, vm_size_t size) 4281181641Skmacy{ 4282181747Skmacy vm_offset_t superpage_offset; 4283181641Skmacy 4284181747Skmacy if (size < NBPDR) 4285181747Skmacy return; 4286181747Skmacy if (object != NULL && (object->flags & OBJ_COLORED) != 0) 4287181747Skmacy offset += ptoa(object->pg_color); 4288181747Skmacy superpage_offset = offset & PDRMASK; 4289181747Skmacy if (size - ((NBPDR - superpage_offset) & PDRMASK) < NBPDR || 4290181747Skmacy (*addr & PDRMASK) == superpage_offset) 4291181747Skmacy return; 4292181747Skmacy if ((*addr & PDRMASK) < superpage_offset) 4293181747Skmacy *addr = (*addr & ~PDRMASK) + superpage_offset; 4294181747Skmacy else 4295181747Skmacy *addr = ((*addr + PDRMASK) & ~PDRMASK) + superpage_offset; 4296181641Skmacy} 4297181641Skmacy 4298190627Sdfrvoid 4299190627Sdfrpmap_suspend() 4300190627Sdfr{ 4301190627Sdfr pmap_t pmap; 4302190627Sdfr int i, pdir, offset; 4303190627Sdfr vm_paddr_t pdirma; 4304190627Sdfr mmu_update_t mu[4]; 4305190627Sdfr 4306190627Sdfr /* 4307190627Sdfr * We need to remove the recursive mapping structure from all 4308190627Sdfr * our pmaps so that Xen doesn't get confused when it restores 4309190627Sdfr * the page tables. The recursive map lives at page directory 4310190627Sdfr * index PTDPTDI. We assume that the suspend code has stopped 4311190627Sdfr * the other vcpus (if any). 4312190627Sdfr */ 4313190627Sdfr LIST_FOREACH(pmap, &allpmaps, pm_list) { 4314190627Sdfr for (i = 0; i < 4; i++) { 4315190627Sdfr /* 4316190627Sdfr * Figure out which page directory (L2) page 4317190627Sdfr * contains this bit of the recursive map and 4318190627Sdfr * the offset within that page of the map 4319190627Sdfr * entry 4320190627Sdfr */ 4321190627Sdfr pdir = (PTDPTDI + i) / NPDEPG; 4322190627Sdfr offset = (PTDPTDI + i) % NPDEPG; 4323190627Sdfr pdirma = pmap->pm_pdpt[pdir] & PG_FRAME; 4324190627Sdfr mu[i].ptr = pdirma + offset * sizeof(pd_entry_t); 4325190627Sdfr mu[i].val = 0; 4326190627Sdfr } 4327190627Sdfr HYPERVISOR_mmu_update(mu, 4, NULL, DOMID_SELF); 4328190627Sdfr } 4329190627Sdfr} 4330190627Sdfr 4331190627Sdfrvoid 4332190627Sdfrpmap_resume() 4333190627Sdfr{ 4334190627Sdfr pmap_t pmap; 4335190627Sdfr int i, pdir, offset; 4336190627Sdfr vm_paddr_t pdirma; 4337190627Sdfr mmu_update_t mu[4]; 4338190627Sdfr 4339190627Sdfr /* 4340190627Sdfr * Restore the recursive map that we removed on suspend. 4341190627Sdfr */ 4342190627Sdfr LIST_FOREACH(pmap, &allpmaps, pm_list) { 4343190627Sdfr for (i = 0; i < 4; i++) { 4344190627Sdfr /* 4345190627Sdfr * Figure out which page directory (L2) page 4346190627Sdfr * contains this bit of the recursive map and 4347190627Sdfr * the offset within that page of the map 4348190627Sdfr * entry 4349190627Sdfr */ 4350190627Sdfr pdir = (PTDPTDI + i) / NPDEPG; 4351190627Sdfr offset = (PTDPTDI + i) % NPDEPG; 4352190627Sdfr pdirma = pmap->pm_pdpt[pdir] & PG_FRAME; 4353190627Sdfr mu[i].ptr = pdirma + offset * sizeof(pd_entry_t); 4354190627Sdfr mu[i].val = (pmap->pm_pdpt[i] & PG_FRAME) | PG_V; 4355190627Sdfr } 4356190627Sdfr HYPERVISOR_mmu_update(mu, 4, NULL, DOMID_SELF); 4357190627Sdfr } 4358190627Sdfr} 4359190627Sdfr 4360181641Skmacy#if defined(PMAP_DEBUG) 4361181641Skmacypmap_pid_dump(int pid) 4362181641Skmacy{ 4363181641Skmacy pmap_t pmap; 4364181641Skmacy struct proc *p; 4365181641Skmacy int npte = 0; 4366181641Skmacy int index; 4367181641Skmacy 4368181641Skmacy sx_slock(&allproc_lock); 4369181641Skmacy FOREACH_PROC_IN_SYSTEM(p) { 4370181641Skmacy if (p->p_pid != pid) 4371181641Skmacy continue; 4372181641Skmacy 4373181641Skmacy if (p->p_vmspace) { 4374181641Skmacy int i,j; 4375181641Skmacy index = 0; 4376181641Skmacy pmap = vmspace_pmap(p->p_vmspace); 4377181641Skmacy for (i = 0; i < NPDEPTD; i++) { 4378181641Skmacy pd_entry_t *pde; 4379181641Skmacy pt_entry_t *pte; 4380181641Skmacy vm_offset_t base = i << PDRSHIFT; 4381181641Skmacy 4382181641Skmacy pde = &pmap->pm_pdir[i]; 4383181641Skmacy if (pde && pmap_pde_v(pde)) { 4384181641Skmacy for (j = 0; j < NPTEPG; j++) { 4385181641Skmacy vm_offset_t va = base + (j << PAGE_SHIFT); 4386181641Skmacy if (va >= (vm_offset_t) VM_MIN_KERNEL_ADDRESS) { 4387181641Skmacy if (index) { 4388181641Skmacy index = 0; 4389181641Skmacy printf("\n"); 4390181641Skmacy } 4391181641Skmacy sx_sunlock(&allproc_lock); 4392230435Salc return (npte); 4393181641Skmacy } 4394181641Skmacy pte = pmap_pte(pmap, va); 4395181641Skmacy if (pte && pmap_pte_v(pte)) { 4396181641Skmacy pt_entry_t pa; 4397181641Skmacy vm_page_t m; 4398181641Skmacy pa = PT_GET(pte); 4399181641Skmacy m = PHYS_TO_VM_PAGE(pa & PG_FRAME); 4400181641Skmacy printf("va: 0x%x, pt: 0x%x, h: %d, w: %d, f: 0x%x", 4401181641Skmacy va, pa, m->hold_count, m->wire_count, m->flags); 4402181641Skmacy npte++; 4403181641Skmacy index++; 4404181641Skmacy if (index >= 2) { 4405181641Skmacy index = 0; 4406181641Skmacy printf("\n"); 4407181641Skmacy } else { 4408181641Skmacy printf(" "); 4409181641Skmacy } 4410181641Skmacy } 4411181641Skmacy } 4412181641Skmacy } 4413181641Skmacy } 4414181641Skmacy } 4415181641Skmacy } 4416181641Skmacy sx_sunlock(&allproc_lock); 4417230435Salc return (npte); 4418181641Skmacy} 4419181641Skmacy#endif 4420181641Skmacy 4421181641Skmacy#if defined(DEBUG) 4422181641Skmacy 4423181641Skmacystatic void pads(pmap_t pm); 4424181641Skmacyvoid pmap_pvdump(vm_paddr_t pa); 4425181641Skmacy 4426181641Skmacy/* print address space of pmap*/ 4427181641Skmacystatic void 4428181641Skmacypads(pmap_t pm) 4429181641Skmacy{ 4430181641Skmacy int i, j; 4431181641Skmacy vm_paddr_t va; 4432181641Skmacy pt_entry_t *ptep; 4433181641Skmacy 4434181641Skmacy if (pm == kernel_pmap) 4435181641Skmacy return; 4436181641Skmacy for (i = 0; i < NPDEPTD; i++) 4437181641Skmacy if (pm->pm_pdir[i]) 4438181641Skmacy for (j = 0; j < NPTEPG; j++) { 4439181641Skmacy va = (i << PDRSHIFT) + (j << PAGE_SHIFT); 4440181641Skmacy if (pm == kernel_pmap && va < KERNBASE) 4441181641Skmacy continue; 4442181641Skmacy if (pm != kernel_pmap && va > UPT_MAX_ADDRESS) 4443181641Skmacy continue; 4444181641Skmacy ptep = pmap_pte(pm, va); 4445181641Skmacy if (pmap_pte_v(ptep)) 4446181641Skmacy printf("%x:%x ", va, *ptep); 4447181641Skmacy }; 4448181641Skmacy 4449181641Skmacy} 4450181641Skmacy 4451181641Skmacyvoid 4452181641Skmacypmap_pvdump(vm_paddr_t pa) 4453181641Skmacy{ 4454181641Skmacy pv_entry_t pv; 4455181641Skmacy pmap_t pmap; 4456181641Skmacy vm_page_t m; 4457181641Skmacy 4458181641Skmacy printf("pa %x", pa); 4459181641Skmacy m = PHYS_TO_VM_PAGE(pa); 4460181641Skmacy TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 4461181641Skmacy pmap = PV_PMAP(pv); 4462181641Skmacy printf(" -> pmap %p, va %x", (void *)pmap, pv->pv_va); 4463181641Skmacy pads(pmap); 4464181641Skmacy } 4465181641Skmacy printf(" "); 4466181641Skmacy} 4467181641Skmacy#endif 4468