pci_pir.c revision 52480 
1/*
2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice unmodified, this list of conditions, and the following
10 *    disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 *    notice, this list of conditions and the following disclaimer in the
13 *    documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * $FreeBSD: head/sys/i386/pci/pci_pir.c 52480 1999-10-25 06:28:04Z alc $
27 *
28 */
29
30#include <sys/param.h>
31#include <sys/systm.h>
32#include <sys/bus.h>
33#include <sys/kernel.h>
34
35#include <pci/pcivar.h>
36#include <pci/pcireg.h>
37#include <i386/isa/pcibus.h>
38
39#ifdef PCI_COMPAT
40/* XXX this is a terrible hack, which keeps the Tekram AMD SCSI driver happy */
41#define cfgmech pci_mechanism
42int cfgmech;
43#else
44static int cfgmech;
45#endif /* PCI_COMPAT */
46static int devmax;
47
48/* enable configuration space accesses and return data port address */
49
50static int
51pci_cfgenable(unsigned bus, unsigned slot, unsigned func, int reg, int bytes)
52{
53	int dataport = 0;
54
55	if (bus <= PCI_BUSMAX
56	    && slot < devmax
57	    && func <= PCI_FUNCMAX
58	    && reg <= PCI_REGMAX
59	    && bytes != 3
60	    && (unsigned) bytes <= 4
61	    && (reg & (bytes -1)) == 0) {
62		switch (cfgmech) {
63		case 1:
64			outl(CONF1_ADDR_PORT, (1 << 31)
65			     | (bus << 16) | (slot << 11)
66			     | (func << 8) | (reg & ~0x03));
67			dataport = CONF1_DATA_PORT + (reg & 0x03);
68			break;
69		case 2:
70			outb(CONF2_ENABLE_PORT, 0xf0 | (func << 1));
71			outb(CONF2_FORWARD_PORT, bus);
72			dataport = 0xc000 | (slot << 8) | reg;
73			break;
74		}
75	}
76	return (dataport);
77}
78
79/* disable configuration space accesses */
80
81static void
82pci_cfgdisable(void)
83{
84	switch (cfgmech) {
85	case 1:
86		outl(CONF1_ADDR_PORT, 0);
87		break;
88	case 2:
89		outb(CONF2_ENABLE_PORT, 0);
90		outb(CONF2_FORWARD_PORT, 0);
91		break;
92	}
93}
94
95/* read configuration space register */
96
97int
98pci_cfgread(pcicfgregs *cfg, int reg, int bytes)
99{
100	int data = -1;
101	int port;
102
103	port = pci_cfgenable(cfg->bus, cfg->slot, cfg->func, reg, bytes);
104
105	if (port != 0) {
106		switch (bytes) {
107		case 1:
108			data = inb(port);
109			break;
110		case 2:
111			data = inw(port);
112			break;
113		case 4:
114			data = inl(port);
115			break;
116		}
117		pci_cfgdisable();
118	}
119	return (data);
120}
121
122/* write configuration space register */
123
124void
125pci_cfgwrite(pcicfgregs *cfg, int reg, int data, int bytes)
126{
127	int port;
128
129	port = pci_cfgenable(cfg->bus, cfg->slot, cfg->func, reg, bytes);
130	if (port != 0) {
131		switch (bytes) {
132		case 1:
133			outb(port, data);
134			break;
135		case 2:
136			outw(port, data);
137			break;
138		case 4:
139			outl(port, data);
140			break;
141		}
142		pci_cfgdisable();
143	}
144}
145
146/* check whether the configuration mechanism has been correct identified */
147
148static int
149pci_cfgcheck(int maxdev)
150{
151	u_char device;
152
153	if (bootverbose)
154		printf("pci_cfgcheck:\tdevice ");
155
156	for (device = 0; device < maxdev; device++) {
157		unsigned id, class, header;
158		if (bootverbose)
159			printf("%d ", device);
160
161		id = inl(pci_cfgenable(0, device, 0, 0, 4));
162		if (id == 0 || id == -1)
163			continue;
164
165		class = inl(pci_cfgenable(0, device, 0, 8, 4)) >> 8;
166		if (bootverbose)
167			printf("[class=%06x] ", class);
168		if (class == 0 || (class & 0xf870ff) != 0)
169			continue;
170
171		header = inb(pci_cfgenable(0, device, 0, 14, 1));
172		if (bootverbose)
173			printf("[hdr=%02x] ", header);
174		if ((header & 0x7e) != 0)
175			continue;
176
177		if (bootverbose)
178			printf("is there (id=%08x)\n", id);
179
180		pci_cfgdisable();
181		return (1);
182	}
183	if (bootverbose)
184		printf("-- nothing found\n");
185
186	pci_cfgdisable();
187	return (0);
188}
189
190static int
191pci_cfgopen(void)
192{
193	unsigned long mode1res,oldval1;
194	unsigned char mode2res,oldval2;
195
196	oldval1 = inl(CONF1_ADDR_PORT);
197
198	if (bootverbose) {
199		printf("pci_open(1):\tmode 1 addr port (0x0cf8) is 0x%08lx\n",
200		       oldval1);
201	}
202
203	if ((oldval1 & CONF1_ENABLE_MSK) == 0) {
204
205		cfgmech = 1;
206		devmax = 32;
207
208		outl(CONF1_ADDR_PORT, CONF1_ENABLE_CHK);
209		outb(CONF1_ADDR_PORT +3, 0);
210		mode1res = inl(CONF1_ADDR_PORT);
211		outl(CONF1_ADDR_PORT, oldval1);
212
213		if (bootverbose)
214			printf("pci_open(1a):\tmode1res=0x%08lx (0x%08lx)\n",
215			       mode1res, CONF1_ENABLE_CHK);
216
217		if (mode1res) {
218			if (pci_cfgcheck(32))
219				return (cfgmech);
220		}
221
222		outl(CONF1_ADDR_PORT, CONF1_ENABLE_CHK1);
223		mode1res = inl(CONF1_ADDR_PORT);
224		outl(CONF1_ADDR_PORT, oldval1);
225
226		if (bootverbose)
227			printf("pci_open(1b):\tmode1res=0x%08lx (0x%08lx)\n",
228			       mode1res, CONF1_ENABLE_CHK1);
229
230		if ((mode1res & CONF1_ENABLE_MSK1) == CONF1_ENABLE_RES1) {
231			if (pci_cfgcheck(32))
232				return (cfgmech);
233		}
234	}
235
236	oldval2 = inb(CONF2_ENABLE_PORT);
237
238	if (bootverbose) {
239		printf("pci_open(2):\tmode 2 enable port (0x0cf8) is 0x%02x\n",
240		       oldval2);
241	}
242
243	if ((oldval2 & 0xf0) == 0) {
244
245		cfgmech = 2;
246		devmax = 16;
247
248		outb(CONF2_ENABLE_PORT, CONF2_ENABLE_CHK);
249		mode2res = inb(CONF2_ENABLE_PORT);
250		outb(CONF2_ENABLE_PORT, oldval2);
251
252		if (bootverbose)
253			printf("pci_open(2a):\tmode2res=0x%02x (0x%02x)\n",
254			       mode2res, CONF2_ENABLE_CHK);
255
256		if (mode2res == CONF2_ENABLE_RES) {
257			if (bootverbose)
258				printf("pci_open(2a):\tnow trying mechanism 2\n");
259
260			if (pci_cfgcheck(16))
261				return (cfgmech);
262		}
263	}
264
265	cfgmech = 0;
266	devmax = 0;
267	return (cfgmech);
268}
269
270static devclass_t	pcib_devclass;
271
272static const char *
273nexus_pcib_is_host_bridge(pcicfgregs *cfg,
274			  u_int32_t id, u_int8_t class, u_int8_t subclass,
275			  u_int8_t *busnum)
276{
277	const char *s = NULL;
278	static u_int8_t pxb[4];	/* hack for 450nx */
279
280	*busnum = 0;
281
282	switch (id) {
283	case 0x12258086:
284		s = "Intel 824?? host to PCI bridge";
285		/* XXX This is a guess */
286		*busnum = pci_cfgread(cfg, 0x41, 1);
287		break;
288	case 0x71808086:
289		s = "Intel 82443LX (440 LX) host to PCI bridge";
290		break;
291	case 0x71908086:
292		s = "Intel 82443BX (440 BX) host to PCI bridge";
293		break;
294	case 0x71928086:
295		s = "Intel 82443BX host to PCI bridge (AGP disabled)";
296		break;
297	case 0x71a08086:
298		s = "Intel 82443GX host to PCI bridge";
299		break;
300	case 0x71a18086:
301		s = "Intel 82443GX host to AGP bridge";
302		break;
303	case 0x71a28086:
304		s = "Intel 82443GX host to PCI bridge (AGP disabled)";
305		break;
306	case 0x84c48086:
307		s = "Intel 82454KX/GX (Orion) host to PCI bridge";
308		*busnum = pci_cfgread(cfg, 0x4a, 1);
309		break;
310	case 0x84ca8086:
311		/*
312		 * For the 450nx chipset, there is a whole bundle of
313		 * things pretending to be host bridges. The MIOC will
314		 * be seen first and isn't really a pci bridge (the
315		 * actual busses are attached to the PXB's). We need to
316		 * read the registers of the MIOC to figure out the
317		 * bus numbers for the PXB channels.
318		 *
319		 * Since the MIOC doesn't have a pci bus attached, we
320		 * pretend it wasn't there.
321		 */
322		pxb[0] = pci_cfgread(cfg, 0xd0, 1); /* BUSNO[0] */
323		pxb[1] = pci_cfgread(cfg, 0xd1, 1) + 1;	/* SUBA[0]+1 */
324		pxb[2] = pci_cfgread(cfg, 0xd3, 1); /* BUSNO[1] */
325		pxb[3] = pci_cfgread(cfg, 0xd4, 1) + 1;	/* SUBA[1]+1 */
326		return NULL;
327	case 0x84cb8086:
328		switch (cfg->slot) {
329		case 0x12:
330			s = "Intel 82454NX PXB#0, Bus#A";
331			*busnum = pxb[0];
332			break;
333		case 0x13:
334			s = "Intel 82454NX PXB#0, Bus#B";
335			*busnum = pxb[1];
336			break;
337		case 0x14:
338			s = "Intel 82454NX PXB#1, Bus#A";
339			*busnum = pxb[2];
340			break;
341		case 0x15:
342			s = "Intel 82454NX PXB#1, Bus#B";
343			*busnum = pxb[3];
344			break;
345		}
346		break;
347
348		/* AMD -- vendor 0x1022 */
349	case 0x70061022:
350		s = "AMD-751 host to PCI bridge";
351		break;
352
353		/* SiS -- vendor 0x1039 */
354	case 0x04961039:
355		s = "SiS 85c496";
356		break;
357	case 0x04061039:
358		s = "SiS 85c501";
359		break;
360	case 0x06011039:
361		s = "SiS 85c601";
362		break;
363	case 0x55911039:
364		s = "SiS 5591 host to PCI bridge";
365		break;
366	case 0x00011039:
367		s = "SiS 5591 host to AGP bridge";
368		break;
369
370		/* VLSI -- vendor 0x1004 */
371	case 0x00051004:
372		s = "VLSI 82C592 Host to PCI bridge";
373		break;
374
375		/* XXX Here is MVP3, I got the datasheet but NO M/B to test it  */
376		/* totally. Please let me know if anything wrong.            -F */
377		/* XXX need info on the MVP3 -- any takers? */
378	case 0x05981106:
379		s = "VIA 82C598MVP (Apollo MVP3) host bridge";
380		break;
381
382		/* AcerLabs -- vendor 0x10b9 */
383		/* Funny : The datasheet told me vendor id is "10b8",sub-vendor */
384		/* id is '10b9" but the register always shows "10b9". -Foxfair  */
385	case 0x154110b9:
386		s = "AcerLabs M1541 (Aladdin-V) PCI host bridge";
387		break;
388
389		/* OPTi -- vendor 0x1045 */
390	case 0xc8221045:
391		s = "OPTi 82C822 host to PCI Bridge";
392		break;
393
394		/* Ross (?) -- vendor 0x1166 */
395	case 0x00051166:
396		s = "Ross (?) host to PCI bridge";
397		/* just guessing the secondary bus register number ... */
398		*busnum = pci_cfgread(cfg, 0x45, 1);
399		break;
400
401		/* Integrated Micro Solutions -- vendor 0x10e0 */
402	case 0x884910e0:
403		s = "Integrated Micro Solutions VL Bridge";
404		break;
405
406	default:
407		if (class == PCIC_BRIDGE && subclass == PCIS_BRIDGE_HOST)
408			s = "Host to PCI bridge";
409		break;
410	}
411
412	return s;
413}
414
415/*
416 * Scan the first pci bus for host-pci bridges and add pcib instances
417 * to the nexus for each bridge.
418 */
419static void
420nexus_pcib_identify(driver_t *driver, device_t parent)
421{
422	pcicfgregs probe;
423
424	if (pci_cfgopen() == 0)
425		return;
426	probe.hose = 0;
427	probe.bus = 0;
428	for (probe.slot = 0; probe.slot <= PCI_SLOTMAX; probe.slot++) {
429		int pcifunchigh = 0;
430		for (probe.func = 0;
431		     probe.func <= pcifunchigh;
432		     probe.func++) {
433			/*
434			 * Read the IDs and class from the device.
435			 */
436			u_int32_t id;
437			u_int8_t class, subclass, busnum;
438			device_t child;
439			const char *s;
440
441			id = pci_cfgread(&probe, PCIR_DEVVENDOR, 4);
442			if (id == -1)
443				continue;
444			class = pci_cfgread(&probe, PCIR_CLASS, 1);
445			subclass = pci_cfgread(&probe, PCIR_SUBCLASS, 1);
446
447			s = nexus_pcib_is_host_bridge(&probe, id,
448						      class, subclass,
449						      &busnum);
450			if (s) {
451				/*
452				 * Add at priority 100 to make sure we
453				 * go after any motherboard resources
454				 */
455				child = BUS_ADD_CHILD(parent, 100,
456						      "pcib", busnum);
457				device_set_desc(child, s);
458			}
459		}
460	}
461}
462
463static int
464nexus_pcib_probe(device_t dev)
465{
466	if (pci_cfgopen() != 0) {
467		device_add_child(dev, "pci", device_get_unit(dev), 0);
468		return 0;
469	}
470	return ENXIO;
471}
472
473static device_method_t nexus_pcib_methods[] = {
474	/* Device interface */
475	DEVMETHOD(device_identify,	nexus_pcib_identify),
476	DEVMETHOD(device_probe,		nexus_pcib_probe),
477	DEVMETHOD(device_attach,	bus_generic_attach),
478	DEVMETHOD(device_shutdown,	bus_generic_shutdown),
479	DEVMETHOD(device_suspend,	bus_generic_suspend),
480	DEVMETHOD(device_resume,	bus_generic_resume),
481
482	/* Bus interface */
483	DEVMETHOD(bus_print_child,	bus_generic_print_child),
484	DEVMETHOD(bus_alloc_resource,	bus_generic_alloc_resource),
485	DEVMETHOD(bus_release_resource,	bus_generic_release_resource),
486	DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
487	DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
488	DEVMETHOD(bus_setup_intr,	bus_generic_setup_intr),
489	DEVMETHOD(bus_teardown_intr,	bus_generic_teardown_intr),
490
491	{ 0, 0 }
492};
493
494static driver_t nexus_pcib_driver = {
495	"pcib",
496	nexus_pcib_methods,
497	1,
498};
499
500DRIVER_MODULE(pcib, nexus, nexus_pcib_driver, pcib_devclass, 0, 0);
501