specialreg.h revision 220578
190075Sobrien/*- 290075Sobrien * Copyright (c) 1991 The Regents of the University of California. 390075Sobrien * All rights reserved. 490075Sobrien * 590075Sobrien * Redistribution and use in source and binary forms, with or without 690075Sobrien * modification, are permitted provided that the following conditions 790075Sobrien * are met: 890075Sobrien * 1. Redistributions of source code must retain the above copyright 990075Sobrien * notice, this list of conditions and the following disclaimer. 1090075Sobrien * 2. Redistributions in binary form must reproduce the above copyright 1190075Sobrien * notice, this list of conditions and the following disclaimer in the 12117395Skan * documentation and/or other materials provided with the distribution. 13117395Skan * 4. Neither the name of the University nor the names of its contributors 14117395Skan * may be used to endorse or promote products derived from this software 15132718Skan * without specific prior written permission. 16117395Skan * 17117395Skan * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 1890075Sobrien * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 1990075Sobrien * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2090075Sobrien * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 21132718Skan * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 2290075Sobrien * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23132718Skan * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24132718Skan * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25132718Skan * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26132718Skan * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27132718Skan * SUCH DAMAGE. 28132718Skan * 29132718Skan * from: @(#)specialreg.h 7.1 (Berkeley) 5/9/91 3090075Sobrien * $FreeBSD: head/sys/i386/include/specialreg.h 220578 2011-04-12 22:12:23Z jkim $ 3190075Sobrien */ 3290075Sobrien 3390075Sobrien#ifndef _MACHINE_SPECIALREG_H_ 3490075Sobrien#define _MACHINE_SPECIALREG_H_ 35132718Skan 3690075Sobrien/* 3790075Sobrien * Bits in 386 special registers: 3890075Sobrien */ 3990075Sobrien#define CR0_PE 0x00000001 /* Protected mode Enable */ 40169689Skan#define CR0_MP 0x00000002 /* "Math" (fpu) Present */ 41169689Skan#define CR0_EM 0x00000004 /* EMulate FPU instructions. (trap ESC only) */ 4290075Sobrien#define CR0_TS 0x00000008 /* Task Switched (if MP, trap ESC and WAIT) */ 4390075Sobrien#define CR0_PG 0x80000000 /* PaGing enable */ 4490075Sobrien 4590075Sobrien/* 4690075Sobrien * Bits in 486 special registers: 4790075Sobrien */ 48169689Skan#define CR0_NE 0x00000020 /* Numeric Error enable (EX16 vs IRQ13) */ 4990075Sobrien#define CR0_WP 0x00010000 /* Write Protect (honor page protect in 5090075Sobrien all modes) */ 51169689Skan#define CR0_AM 0x00040000 /* Alignment Mask (set to enable AC flag) */ 5290075Sobrien#define CR0_NW 0x20000000 /* Not Write-through */ 5390075Sobrien#define CR0_CD 0x40000000 /* Cache Disable */ 5490075Sobrien 5590075Sobrien/* 5690075Sobrien * Bits in PPro special registers 5790075Sobrien */ 5890075Sobrien#define CR4_VME 0x00000001 /* Virtual 8086 mode extensions */ 5990075Sobrien#define CR4_PVI 0x00000002 /* Protected-mode virtual interrupts */ 6090075Sobrien#define CR4_TSD 0x00000004 /* Time stamp disable */ 61169689Skan#define CR4_DE 0x00000008 /* Debugging extensions */ 62#define CR4_PSE 0x00000010 /* Page size extensions */ 63#define CR4_PAE 0x00000020 /* Physical address extension */ 64#define CR4_MCE 0x00000040 /* Machine check enable */ 65#define CR4_PGE 0x00000080 /* Page global enable */ 66#define CR4_PCE 0x00000100 /* Performance monitoring counter enable */ 67#define CR4_FXSR 0x00000200 /* Fast FPU save/restore used by OS */ 68#define CR4_XMM 0x00000400 /* enable SIMD/MMX2 to use except 16 */ 69 70/* 71 * Bits in AMD64 special registers. EFER is 64 bits wide. 72 */ 73#define EFER_NXE 0x000000800 /* PTE No-Execute bit enable (R/W) */ 74 75/* 76 * CPUID instruction features register 77 */ 78#define CPUID_FPU 0x00000001 79#define CPUID_VME 0x00000002 80#define CPUID_DE 0x00000004 81#define CPUID_PSE 0x00000008 82#define CPUID_TSC 0x00000010 83#define CPUID_MSR 0x00000020 84#define CPUID_PAE 0x00000040 85#define CPUID_MCE 0x00000080 86#define CPUID_CX8 0x00000100 87#define CPUID_APIC 0x00000200 88#define CPUID_B10 0x00000400 89#define CPUID_SEP 0x00000800 90#define CPUID_MTRR 0x00001000 91#define CPUID_PGE 0x00002000 92#define CPUID_MCA 0x00004000 93#define CPUID_CMOV 0x00008000 94#define CPUID_PAT 0x00010000 95#define CPUID_PSE36 0x00020000 96#define CPUID_PSN 0x00040000 97#define CPUID_CLFSH 0x00080000 98#define CPUID_B20 0x00100000 99#define CPUID_DS 0x00200000 100#define CPUID_ACPI 0x00400000 101#define CPUID_MMX 0x00800000 102#define CPUID_FXSR 0x01000000 103#define CPUID_SSE 0x02000000 104#define CPUID_XMM 0x02000000 105#define CPUID_SSE2 0x04000000 106#define CPUID_SS 0x08000000 107#define CPUID_HTT 0x10000000 108#define CPUID_TM 0x20000000 109#define CPUID_IA64 0x40000000 110#define CPUID_PBE 0x80000000 111 112#define CPUID2_SSE3 0x00000001 113#define CPUID2_PCLMULQDQ 0x00000002 114#define CPUID2_DTES64 0x00000004 115#define CPUID2_MON 0x00000008 116#define CPUID2_DS_CPL 0x00000010 117#define CPUID2_VMX 0x00000020 118#define CPUID2_SMX 0x00000040 119#define CPUID2_EST 0x00000080 120#define CPUID2_TM2 0x00000100 121#define CPUID2_SSSE3 0x00000200 122#define CPUID2_CNXTID 0x00000400 123#define CPUID2_CX16 0x00002000 124#define CPUID2_XTPR 0x00004000 125#define CPUID2_PDCM 0x00008000 126#define CPUID2_PCID 0x00020000 127#define CPUID2_DCA 0x00040000 128#define CPUID2_SSE41 0x00080000 129#define CPUID2_SSE42 0x00100000 130#define CPUID2_X2APIC 0x00200000 131#define CPUID2_MOVBE 0x00400000 132#define CPUID2_POPCNT 0x00800000 133#define CPUID2_AESNI 0x02000000 134 135/* 136 * Important bits in the Thermal and Power Management flags 137 * CPUID.6 EAX and ECX. 138 */ 139#define CPUTPM1_SENSOR 0x00000001 140#define CPUTPM1_TURBO 0x00000002 141#define CPUTPM1_ARAT 0x00000004 142#define CPUTPM2_EFFREQ 0x00000001 143 144/* 145 * Important bits in the AMD extended cpuid flags 146 */ 147#define AMDID_SYSCALL 0x00000800 148#define AMDID_MP 0x00080000 149#define AMDID_NX 0x00100000 150#define AMDID_EXT_MMX 0x00400000 151#define AMDID_FFXSR 0x01000000 152#define AMDID_PAGE1GB 0x04000000 153#define AMDID_RDTSCP 0x08000000 154#define AMDID_LM 0x20000000 155#define AMDID_EXT_3DNOW 0x40000000 156#define AMDID_3DNOW 0x80000000 157 158#define AMDID2_LAHF 0x00000001 159#define AMDID2_CMP 0x00000002 160#define AMDID2_SVM 0x00000004 161#define AMDID2_EXT_APIC 0x00000008 162#define AMDID2_CR8 0x00000010 163#define AMDID2_ABM 0x00000020 164#define AMDID2_SSE4A 0x00000040 165#define AMDID2_MAS 0x00000080 166#define AMDID2_PREFETCH 0x00000100 167#define AMDID2_OSVW 0x00000200 168#define AMDID2_IBS 0x00000400 169#define AMDID2_SSE5 0x00000800 170#define AMDID2_SKINIT 0x00001000 171#define AMDID2_WDT 0x00002000 172 173/* 174 * CPUID instruction 1 eax info 175 */ 176#define CPUID_STEPPING 0x0000000f 177#define CPUID_MODEL 0x000000f0 178#define CPUID_FAMILY 0x00000f00 179#define CPUID_EXT_MODEL 0x000f0000 180#define CPUID_EXT_FAMILY 0x0ff00000 181#define CPUID_TO_MODEL(id) \ 182 ((((id) & CPUID_MODEL) >> 4) | \ 183 ((((id) & CPUID_FAMILY) >= 0x600) ? \ 184 (((id) & CPUID_EXT_MODEL) >> 12) : 0)) 185#define CPUID_TO_FAMILY(id) \ 186 ((((id) & CPUID_FAMILY) >> 8) + \ 187 ((((id) & CPUID_FAMILY) == 0xf00) ? \ 188 (((id) & CPUID_EXT_FAMILY) >> 20) : 0)) 189 190/* 191 * CPUID instruction 1 ebx info 192 */ 193#define CPUID_BRAND_INDEX 0x000000ff 194#define CPUID_CLFUSH_SIZE 0x0000ff00 195#define CPUID_HTT_CORES 0x00ff0000 196#define CPUID_LOCAL_APIC_ID 0xff000000 197 198/* 199 * CPUID instruction 6 ecx info 200 */ 201#define CPUID_PERF_STAT 0x00000001 202#define CPUID_PERF_BIAS 0x00000008 203 204/* 205 * CPUID instruction 0xb ebx info. 206 */ 207#define CPUID_TYPE_INVAL 0 208#define CPUID_TYPE_SMT 1 209#define CPUID_TYPE_CORE 2 210 211/* 212 * AMD extended function 8000_0007h edx info 213 */ 214#define AMDPM_TS 0x00000001 215#define AMDPM_FID 0x00000002 216#define AMDPM_VID 0x00000004 217#define AMDPM_TTP 0x00000008 218#define AMDPM_TM 0x00000010 219#define AMDPM_STC 0x00000020 220#define AMDPM_100MHZ_STEPS 0x00000040 221#define AMDPM_HW_PSTATE 0x00000080 222#define AMDPM_TSC_INVARIANT 0x00000100 223#define AMDPM_CPB 0x00000200 224 225/* 226 * AMD extended function 8000_0008h ecx info 227 */ 228#define AMDID_CMP_CORES 0x000000ff 229 230/* 231 * CPUID manufacturers identifiers 232 */ 233#define AMD_VENDOR_ID "AuthenticAMD" 234#define CENTAUR_VENDOR_ID "CentaurHauls" 235#define CYRIX_VENDOR_ID "CyrixInstead" 236#define INTEL_VENDOR_ID "GenuineIntel" 237#define NEXGEN_VENDOR_ID "NexGenDriven" 238#define NSC_VENDOR_ID "Geode by NSC" 239#define RISE_VENDOR_ID "RiseRiseRise" 240#define SIS_VENDOR_ID "SiS SiS SiS " 241#define TRANSMETA_VENDOR_ID "GenuineTMx86" 242#define UMC_VENDOR_ID "UMC UMC UMC " 243 244/* 245 * Model-specific registers for the i386 family 246 */ 247#define MSR_P5_MC_ADDR 0x000 248#define MSR_P5_MC_TYPE 0x001 249#define MSR_TSC 0x010 250#define MSR_P5_CESR 0x011 251#define MSR_P5_CTR0 0x012 252#define MSR_P5_CTR1 0x013 253#define MSR_IA32_PLATFORM_ID 0x017 254#define MSR_APICBASE 0x01b 255#define MSR_EBL_CR_POWERON 0x02a 256#define MSR_TEST_CTL 0x033 257#define MSR_BIOS_UPDT_TRIG 0x079 258#define MSR_BBL_CR_D0 0x088 259#define MSR_BBL_CR_D1 0x089 260#define MSR_BBL_CR_D2 0x08a 261#define MSR_BIOS_SIGN 0x08b 262#define MSR_PERFCTR0 0x0c1 263#define MSR_PERFCTR1 0x0c2 264#define MSR_MPERF 0x0e7 265#define MSR_APERF 0x0e8 266#define MSR_IA32_EXT_CONFIG 0x0ee /* Undocumented. Core Solo/Duo only */ 267#define MSR_MTRRcap 0x0fe 268#define MSR_BBL_CR_ADDR 0x116 269#define MSR_BBL_CR_DECC 0x118 270#define MSR_BBL_CR_CTL 0x119 271#define MSR_BBL_CR_TRIG 0x11a 272#define MSR_BBL_CR_BUSY 0x11b 273#define MSR_BBL_CR_CTL3 0x11e 274#define MSR_SYSENTER_CS_MSR 0x174 275#define MSR_SYSENTER_ESP_MSR 0x175 276#define MSR_SYSENTER_EIP_MSR 0x176 277#define MSR_MCG_CAP 0x179 278#define MSR_MCG_STATUS 0x17a 279#define MSR_MCG_CTL 0x17b 280#define MSR_EVNTSEL0 0x186 281#define MSR_EVNTSEL1 0x187 282#define MSR_THERM_CONTROL 0x19a 283#define MSR_THERM_INTERRUPT 0x19b 284#define MSR_THERM_STATUS 0x19c 285#define MSR_IA32_MISC_ENABLE 0x1a0 286#define MSR_IA32_TEMPERATURE_TARGET 0x1a2 287#define MSR_DEBUGCTLMSR 0x1d9 288#define MSR_LASTBRANCHFROMIP 0x1db 289#define MSR_LASTBRANCHTOIP 0x1dc 290#define MSR_LASTINTFROMIP 0x1dd 291#define MSR_LASTINTTOIP 0x1de 292#define MSR_ROB_CR_BKUPTMPDR6 0x1e0 293#define MSR_MTRRVarBase 0x200 294#define MSR_MTRR64kBase 0x250 295#define MSR_MTRR16kBase 0x258 296#define MSR_MTRR4kBase 0x268 297#define MSR_PAT 0x277 298#define MSR_MC0_CTL2 0x280 299#define MSR_MTRRdefType 0x2ff 300#define MSR_MC0_CTL 0x400 301#define MSR_MC0_STATUS 0x401 302#define MSR_MC0_ADDR 0x402 303#define MSR_MC0_MISC 0x403 304#define MSR_MC1_CTL 0x404 305#define MSR_MC1_STATUS 0x405 306#define MSR_MC1_ADDR 0x406 307#define MSR_MC1_MISC 0x407 308#define MSR_MC2_CTL 0x408 309#define MSR_MC2_STATUS 0x409 310#define MSR_MC2_ADDR 0x40a 311#define MSR_MC2_MISC 0x40b 312#define MSR_MC3_CTL 0x40c 313#define MSR_MC3_STATUS 0x40d 314#define MSR_MC3_ADDR 0x40e 315#define MSR_MC3_MISC 0x40f 316#define MSR_MC4_CTL 0x410 317#define MSR_MC4_STATUS 0x411 318#define MSR_MC4_ADDR 0x412 319#define MSR_MC4_MISC 0x413 320 321/* 322 * Constants related to MSR's. 323 */ 324#define APICBASE_RESERVED 0x000006ff 325#define APICBASE_BSP 0x00000100 326#define APICBASE_ENABLED 0x00000800 327#define APICBASE_ADDRESS 0xfffff000 328 329/* 330 * PAT modes. 331 */ 332#define PAT_UNCACHEABLE 0x00 333#define PAT_WRITE_COMBINING 0x01 334#define PAT_WRITE_THROUGH 0x04 335#define PAT_WRITE_PROTECTED 0x05 336#define PAT_WRITE_BACK 0x06 337#define PAT_UNCACHED 0x07 338#define PAT_VALUE(i, m) ((long long)(m) << (8 * (i))) 339#define PAT_MASK(i) PAT_VALUE(i, 0xff) 340 341/* 342 * Constants related to MTRRs 343 */ 344#define MTRR_UNCACHEABLE 0x00 345#define MTRR_WRITE_COMBINING 0x01 346#define MTRR_WRITE_THROUGH 0x04 347#define MTRR_WRITE_PROTECTED 0x05 348#define MTRR_WRITE_BACK 0x06 349#define MTRR_N64K 8 /* numbers of fixed-size entries */ 350#define MTRR_N16K 16 351#define MTRR_N4K 64 352#define MTRR_CAP_WC 0x0000000000000400 353#define MTRR_CAP_FIXED 0x0000000000000100 354#define MTRR_CAP_VCNT 0x00000000000000ff 355#define MTRR_DEF_ENABLE 0x0000000000000800 356#define MTRR_DEF_FIXED_ENABLE 0x0000000000000400 357#define MTRR_DEF_TYPE 0x00000000000000ff 358#define MTRR_PHYSBASE_PHYSBASE 0x000ffffffffff000 359#define MTRR_PHYSBASE_TYPE 0x00000000000000ff 360#define MTRR_PHYSMASK_PHYSMASK 0x000ffffffffff000 361#define MTRR_PHYSMASK_VALID 0x0000000000000800 362 363/* 364 * Cyrix configuration registers, accessible as IO ports. 365 */ 366#define CCR0 0xc0 /* Configuration control register 0 */ 367#define CCR0_NC0 0x01 /* First 64K of each 1M memory region is 368 non-cacheable */ 369#define CCR0_NC1 0x02 /* 640K-1M region is non-cacheable */ 370#define CCR0_A20M 0x04 /* Enables A20M# input pin */ 371#define CCR0_KEN 0x08 /* Enables KEN# input pin */ 372#define CCR0_FLUSH 0x10 /* Enables FLUSH# input pin */ 373#define CCR0_BARB 0x20 /* Flushes internal cache when entering hold 374 state */ 375#define CCR0_CO 0x40 /* Cache org: 1=direct mapped, 0=2x set 376 assoc */ 377#define CCR0_SUSPEND 0x80 /* Enables SUSP# and SUSPA# pins */ 378 379#define CCR1 0xc1 /* Configuration control register 1 */ 380#define CCR1_RPL 0x01 /* Enables RPLSET and RPLVAL# pins */ 381#define CCR1_SMI 0x02 /* Enables SMM pins */ 382#define CCR1_SMAC 0x04 /* System management memory access */ 383#define CCR1_MMAC 0x08 /* Main memory access */ 384#define CCR1_NO_LOCK 0x10 /* Negate LOCK# */ 385#define CCR1_SM3 0x80 /* SMM address space address region 3 */ 386 387#define CCR2 0xc2 388#define CCR2_WB 0x02 /* Enables WB cache interface pins */ 389#define CCR2_SADS 0x02 /* Slow ADS */ 390#define CCR2_LOCK_NW 0x04 /* LOCK NW Bit */ 391#define CCR2_SUSP_HLT 0x08 /* Suspend on HALT */ 392#define CCR2_WT1 0x10 /* WT region 1 */ 393#define CCR2_WPR1 0x10 /* Write-protect region 1 */ 394#define CCR2_BARB 0x20 /* Flushes write-back cache when entering 395 hold state. */ 396#define CCR2_BWRT 0x40 /* Enables burst write cycles */ 397#define CCR2_USE_SUSP 0x80 /* Enables suspend pins */ 398 399#define CCR3 0xc3 400#define CCR3_SMILOCK 0x01 /* SMM register lock */ 401#define CCR3_NMI 0x02 /* Enables NMI during SMM */ 402#define CCR3_LINBRST 0x04 /* Linear address burst cycles */ 403#define CCR3_SMMMODE 0x08 /* SMM Mode */ 404#define CCR3_MAPEN0 0x10 /* Enables Map0 */ 405#define CCR3_MAPEN1 0x20 /* Enables Map1 */ 406#define CCR3_MAPEN2 0x40 /* Enables Map2 */ 407#define CCR3_MAPEN3 0x80 /* Enables Map3 */ 408 409#define CCR4 0xe8 410#define CCR4_IOMASK 0x07 411#define CCR4_MEM 0x08 /* Enables momory bypassing */ 412#define CCR4_DTE 0x10 /* Enables directory table entry cache */ 413#define CCR4_FASTFPE 0x20 /* Fast FPU exception */ 414#define CCR4_CPUID 0x80 /* Enables CPUID instruction */ 415 416#define CCR5 0xe9 417#define CCR5_WT_ALLOC 0x01 /* Write-through allocate */ 418#define CCR5_SLOP 0x02 /* LOOP instruction slowed down */ 419#define CCR5_LBR1 0x10 /* Local bus region 1 */ 420#define CCR5_ARREN 0x20 /* Enables ARR region */ 421 422#define CCR6 0xea 423 424#define CCR7 0xeb 425 426/* Performance Control Register (5x86 only). */ 427#define PCR0 0x20 428#define PCR0_RSTK 0x01 /* Enables return stack */ 429#define PCR0_BTB 0x02 /* Enables branch target buffer */ 430#define PCR0_LOOP 0x04 /* Enables loop */ 431#define PCR0_AIS 0x08 /* Enables all instrcutions stalled to 432 serialize pipe. */ 433#define PCR0_MLR 0x10 /* Enables reordering of misaligned loads */ 434#define PCR0_BTBRT 0x40 /* Enables BTB test register. */ 435#define PCR0_LSSER 0x80 /* Disable reorder */ 436 437/* Device Identification Registers */ 438#define DIR0 0xfe 439#define DIR1 0xff 440 441/* 442 * Machine Check register constants. 443 */ 444#define MCG_CAP_COUNT 0x000000ff 445#define MCG_CAP_CTL_P 0x00000100 446#define MCG_CAP_EXT_P 0x00000200 447#define MCG_CAP_CMCI_P 0x00000400 448#define MCG_CAP_TES_P 0x00000800 449#define MCG_CAP_EXT_CNT 0x00ff0000 450#define MCG_CAP_SER_P 0x01000000 451#define MCG_STATUS_RIPV 0x00000001 452#define MCG_STATUS_EIPV 0x00000002 453#define MCG_STATUS_MCIP 0x00000004 454#define MCG_CTL_ENABLE 0xffffffffffffffff 455#define MCG_CTL_DISABLE 0x0000000000000000 456#define MSR_MC_CTL(x) (MSR_MC0_CTL + (x) * 4) 457#define MSR_MC_STATUS(x) (MSR_MC0_STATUS + (x) * 4) 458#define MSR_MC_ADDR(x) (MSR_MC0_ADDR + (x) * 4) 459#define MSR_MC_MISC(x) (MSR_MC0_MISC + (x) * 4) 460#define MSR_MC_CTL2(x) (MSR_MC0_CTL2 + (x)) /* If MCG_CAP_CMCI_P */ 461#define MC_STATUS_MCA_ERROR 0x000000000000ffff 462#define MC_STATUS_MODEL_ERROR 0x00000000ffff0000 463#define MC_STATUS_OTHER_INFO 0x01ffffff00000000 464#define MC_STATUS_COR_COUNT 0x001fffc000000000 /* If MCG_CAP_CMCI_P */ 465#define MC_STATUS_TES_STATUS 0x0060000000000000 /* If MCG_CAP_TES_P */ 466#define MC_STATUS_AR 0x0080000000000000 /* If MCG_CAP_TES_P */ 467#define MC_STATUS_S 0x0100000000000000 /* If MCG_CAP_TES_P */ 468#define MC_STATUS_PCC 0x0200000000000000 469#define MC_STATUS_ADDRV 0x0400000000000000 470#define MC_STATUS_MISCV 0x0800000000000000 471#define MC_STATUS_EN 0x1000000000000000 472#define MC_STATUS_UC 0x2000000000000000 473#define MC_STATUS_OVER 0x4000000000000000 474#define MC_STATUS_VAL 0x8000000000000000 475#define MC_MISC_RA_LSB 0x000000000000003f /* If MCG_CAP_SER_P */ 476#define MC_MISC_ADDRESS_MODE 0x00000000000001c0 /* If MCG_CAP_SER_P */ 477#define MC_CTL2_THRESHOLD 0x0000000000007fff 478#define MC_CTL2_CMCI_EN 0x0000000040000000 479 480/* 481 * The following four 3-byte registers control the non-cacheable regions. 482 * These registers must be written as three separate bytes. 483 * 484 * NCRx+0: A31-A24 of starting address 485 * NCRx+1: A23-A16 of starting address 486 * NCRx+2: A15-A12 of starting address | NCR_SIZE_xx. 487 * 488 * The non-cacheable region's starting address must be aligned to the 489 * size indicated by the NCR_SIZE_xx field. 490 */ 491#define NCR1 0xc4 492#define NCR2 0xc7 493#define NCR3 0xca 494#define NCR4 0xcd 495 496#define NCR_SIZE_0K 0 497#define NCR_SIZE_4K 1 498#define NCR_SIZE_8K 2 499#define NCR_SIZE_16K 3 500#define NCR_SIZE_32K 4 501#define NCR_SIZE_64K 5 502#define NCR_SIZE_128K 6 503#define NCR_SIZE_256K 7 504#define NCR_SIZE_512K 8 505#define NCR_SIZE_1M 9 506#define NCR_SIZE_2M 10 507#define NCR_SIZE_4M 11 508#define NCR_SIZE_8M 12 509#define NCR_SIZE_16M 13 510#define NCR_SIZE_32M 14 511#define NCR_SIZE_4G 15 512 513/* 514 * The address region registers are used to specify the location and 515 * size for the eight address regions. 516 * 517 * ARRx + 0: A31-A24 of start address 518 * ARRx + 1: A23-A16 of start address 519 * ARRx + 2: A15-A12 of start address | ARR_SIZE_xx 520 */ 521#define ARR0 0xc4 522#define ARR1 0xc7 523#define ARR2 0xca 524#define ARR3 0xcd 525#define ARR4 0xd0 526#define ARR5 0xd3 527#define ARR6 0xd6 528#define ARR7 0xd9 529 530#define ARR_SIZE_0K 0 531#define ARR_SIZE_4K 1 532#define ARR_SIZE_8K 2 533#define ARR_SIZE_16K 3 534#define ARR_SIZE_32K 4 535#define ARR_SIZE_64K 5 536#define ARR_SIZE_128K 6 537#define ARR_SIZE_256K 7 538#define ARR_SIZE_512K 8 539#define ARR_SIZE_1M 9 540#define ARR_SIZE_2M 10 541#define ARR_SIZE_4M 11 542#define ARR_SIZE_8M 12 543#define ARR_SIZE_16M 13 544#define ARR_SIZE_32M 14 545#define ARR_SIZE_4G 15 546 547/* 548 * The region control registers specify the attributes associated with 549 * the ARRx addres regions. 550 */ 551#define RCR0 0xdc 552#define RCR1 0xdd 553#define RCR2 0xde 554#define RCR3 0xdf 555#define RCR4 0xe0 556#define RCR5 0xe1 557#define RCR6 0xe2 558#define RCR7 0xe3 559 560#define RCR_RCD 0x01 /* Disables caching for ARRx (x = 0-6). */ 561#define RCR_RCE 0x01 /* Enables caching for ARR7. */ 562#define RCR_WWO 0x02 /* Weak write ordering. */ 563#define RCR_WL 0x04 /* Weak locking. */ 564#define RCR_WG 0x08 /* Write gathering. */ 565#define RCR_WT 0x10 /* Write-through. */ 566#define RCR_NLB 0x20 /* LBA# pin is not asserted. */ 567 568/* AMD Write Allocate Top-Of-Memory and Control Register */ 569#define AMD_WT_ALLOC_TME 0x40000 /* top-of-memory enable */ 570#define AMD_WT_ALLOC_PRE 0x20000 /* programmable range enable */ 571#define AMD_WT_ALLOC_FRE 0x10000 /* fixed (A0000-FFFFF) range enable */ 572 573/* AMD64 MSR's */ 574#define MSR_EFER 0xc0000080 /* extended features */ 575#define MSR_HWCR 0xc0010015 576#define MSR_K8_UCODE_UPDATE 0xc0010020 /* update microcode */ 577#define MSR_MC0_CTL_MASK 0xc0010044 578 579/* VIA ACE crypto featureset: for via_feature_rng */ 580#define VIA_HAS_RNG 1 /* cpu has RNG */ 581 582/* VIA ACE crypto featureset: for via_feature_xcrypt */ 583#define VIA_HAS_AES 1 /* cpu has AES */ 584#define VIA_HAS_SHA 2 /* cpu has SHA1 & SHA256 */ 585#define VIA_HAS_MM 4 /* cpu has RSA instructions */ 586#define VIA_HAS_AESCTR 8 /* cpu has AES-CTR instructions */ 587 588/* Centaur Extended Feature flags */ 589#define VIA_CPUID_HAS_RNG 0x000004 590#define VIA_CPUID_DO_RNG 0x000008 591#define VIA_CPUID_HAS_ACE 0x000040 592#define VIA_CPUID_DO_ACE 0x000080 593#define VIA_CPUID_HAS_ACE2 0x000100 594#define VIA_CPUID_DO_ACE2 0x000200 595#define VIA_CPUID_HAS_PHE 0x000400 596#define VIA_CPUID_DO_PHE 0x000800 597#define VIA_CPUID_HAS_PMM 0x001000 598#define VIA_CPUID_DO_PMM 0x002000 599 600/* VIA ACE xcrypt-* instruction context control options */ 601#define VIA_CRYPT_CWLO_ROUND_M 0x0000000f 602#define VIA_CRYPT_CWLO_ALG_M 0x00000070 603#define VIA_CRYPT_CWLO_ALG_AES 0x00000000 604#define VIA_CRYPT_CWLO_KEYGEN_M 0x00000080 605#define VIA_CRYPT_CWLO_KEYGEN_HW 0x00000000 606#define VIA_CRYPT_CWLO_KEYGEN_SW 0x00000080 607#define VIA_CRYPT_CWLO_NORMAL 0x00000000 608#define VIA_CRYPT_CWLO_INTERMEDIATE 0x00000100 609#define VIA_CRYPT_CWLO_ENCRYPT 0x00000000 610#define VIA_CRYPT_CWLO_DECRYPT 0x00000200 611#define VIA_CRYPT_CWLO_KEY128 0x0000000a /* 128bit, 10 rds */ 612#define VIA_CRYPT_CWLO_KEY192 0x0000040c /* 192bit, 12 rds */ 613#define VIA_CRYPT_CWLO_KEY256 0x0000080e /* 256bit, 15 rds */ 614 615#endif /* !_MACHINE_SPECIALREG_H_ */ 616