specialreg.h revision 167493
14Srgrimes/*- 24Srgrimes * Copyright (c) 1991 The Regents of the University of California. 34Srgrimes * All rights reserved. 44Srgrimes * 54Srgrimes * Redistribution and use in source and binary forms, with or without 64Srgrimes * modification, are permitted provided that the following conditions 74Srgrimes * are met: 84Srgrimes * 1. Redistributions of source code must retain the above copyright 94Srgrimes * notice, this list of conditions and the following disclaimer. 104Srgrimes * 2. Redistributions in binary form must reproduce the above copyright 114Srgrimes * notice, this list of conditions and the following disclaimer in the 124Srgrimes * documentation and/or other materials provided with the distribution. 134Srgrimes * 4. Neither the name of the University nor the names of its contributors 144Srgrimes * may be used to endorse or promote products derived from this software 154Srgrimes * without specific prior written permission. 164Srgrimes * 174Srgrimes * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 184Srgrimes * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 194Srgrimes * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 204Srgrimes * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 214Srgrimes * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 224Srgrimes * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 234Srgrimes * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 244Srgrimes * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 254Srgrimes * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 264Srgrimes * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 274Srgrimes * SUCH DAMAGE. 284Srgrimes * 29621Srgrimes * from: @(#)specialreg.h 7.1 (Berkeley) 5/9/91 3050477Speter * $FreeBSD: head/sys/i386/include/specialreg.h 167493 2007-03-12 20:27:21Z jkim $ 314Srgrimes */ 324Srgrimes 33719Swollman#ifndef _MACHINE_SPECIALREG_H_ 345594Sbde#define _MACHINE_SPECIALREG_H_ 35719Swollman 364Srgrimes/* 374Srgrimes * Bits in 386 special registers: 384Srgrimes */ 394Srgrimes#define CR0_PE 0x00000001 /* Protected mode Enable */ 40160329Sjkim#define CR0_MP 0x00000002 /* "Math" (fpu) Present */ 41160329Sjkim#define CR0_EM 0x00000004 /* EMulate FPU instructions. (trap ESC only) */ 424Srgrimes#define CR0_TS 0x00000008 /* Task Switched (if MP, trap ESC and WAIT) */ 434Srgrimes#define CR0_PG 0x80000000 /* PaGing enable */ 444Srgrimes 454Srgrimes/* 464Srgrimes * Bits in 486 special registers: 474Srgrimes */ 4824112Skato#define CR0_NE 0x00000020 /* Numeric Error enable (EX16 vs IRQ13) */ 4924112Skato#define CR0_WP 0x00010000 /* Write Protect (honor page protect in 5024112Skato all modes) */ 5124112Skato#define CR0_AM 0x00040000 /* Alignment Mask (set to enable AC flag) */ 5224112Skato#define CR0_NW 0x20000000 /* Not Write-through */ 5324112Skato#define CR0_CD 0x40000000 /* Cache Disable */ 542495Spst 552495Spst/* 5619621Sdyson * Bits in PPro special registers 5719621Sdyson */ 5819621Sdyson#define CR4_VME 0x00000001 /* Virtual 8086 mode extensions */ 5919621Sdyson#define CR4_PVI 0x00000002 /* Protected-mode virtual interrupts */ 6019621Sdyson#define CR4_TSD 0x00000004 /* Time stamp disable */ 6119621Sdyson#define CR4_DE 0x00000008 /* Debugging extensions */ 6219621Sdyson#define CR4_PSE 0x00000010 /* Page size extensions */ 6319621Sdyson#define CR4_PAE 0x00000020 /* Physical address extension */ 6419621Sdyson#define CR4_MCE 0x00000040 /* Machine check enable */ 6519621Sdyson#define CR4_PGE 0x00000080 /* Page global enable */ 6619621Sdyson#define CR4_PCE 0x00000100 /* Performance monitoring counter enable */ 6751127Speter#define CR4_FXSR 0x00000200 /* Fast FPU save/restore used by OS */ 6851127Speter#define CR4_XMM 0x00000400 /* enable SIMD/MMX2 to use except 16 */ 6919621Sdyson 7019621Sdyson/* 7119621Sdyson * CPUID instruction features register 7219621Sdyson */ 7398650Smp#define CPUID_FPU 0x00000001 7498650Smp#define CPUID_VME 0x00000002 7598650Smp#define CPUID_DE 0x00000004 7698650Smp#define CPUID_PSE 0x00000008 7798650Smp#define CPUID_TSC 0x00000010 7898650Smp#define CPUID_MSR 0x00000020 7998650Smp#define CPUID_PAE 0x00000040 8098650Smp#define CPUID_MCE 0x00000080 8198650Smp#define CPUID_CX8 0x00000100 8298650Smp#define CPUID_APIC 0x00000200 8398650Smp#define CPUID_B10 0x00000400 8498650Smp#define CPUID_SEP 0x00000800 8598650Smp#define CPUID_MTRR 0x00001000 8698650Smp#define CPUID_PGE 0x00002000 8798650Smp#define CPUID_MCA 0x00004000 8898650Smp#define CPUID_CMOV 0x00008000 8998650Smp#define CPUID_PAT 0x00010000 9098650Smp#define CPUID_PSE36 0x00020000 9198650Smp#define CPUID_PSN 0x00040000 9298650Smp#define CPUID_CLFSH 0x00080000 9398650Smp#define CPUID_B20 0x00100000 9498650Smp#define CPUID_DS 0x00200000 9598650Smp#define CPUID_ACPI 0x00400000 9698650Smp#define CPUID_MMX 0x00800000 9798650Smp#define CPUID_FXSR 0x01000000 9898650Smp#define CPUID_SSE 0x02000000 9998650Smp#define CPUID_XMM 0x02000000 10098650Smp#define CPUID_SSE2 0x04000000 10198650Smp#define CPUID_SS 0x08000000 102108909Sjhb#define CPUID_HTT 0x10000000 10398650Smp#define CPUID_TM 0x20000000 104114376Speter#define CPUID_IA64 0x40000000 10598650Smp#define CPUID_PBE 0x80000000 10619621Sdyson 107167493Sjkim#define CPUID2_SSE3 0x00000001 108167493Sjkim#define CPUID2_MON 0x00000008 109167493Sjkim#define CPUID2_DS_CPL 0x00000010 110167493Sjkim#define CPUID2_VMX 0x00000020 111167493Sjkim#define CPUID2_EST 0x00000080 112167493Sjkim#define CPUID2_TM2 0x00000100 113167493Sjkim#define CPUID2_SSSE3 0x00000200 114167493Sjkim#define CPUID2_CNXTID 0x00000400 115167493Sjkim#define CPUID2_CX16 0x00002000 116167493Sjkim#define CPUID2_XTPR 0x00004000 117160329Sjkim 11819621Sdyson/* 119151348Sjkim * Important bits in the AMD extended cpuid flags 120151348Sjkim */ 121167493Sjkim#define AMDID_SYSCALL 0x00000800 122167493Sjkim#define AMDID_MP 0x00080000 123167493Sjkim#define AMDID_NX 0x00100000 124167493Sjkim#define AMDID_EXT_MMX 0x00400000 125167493Sjkim#define AMDID_FFXSR 0x01000000 126167493Sjkim#define AMDID_RDTSCP 0x08000000 127167493Sjkim#define AMDID_LM 0x20000000 128167493Sjkim#define AMDID_EXT_3DNOW 0x40000000 129167493Sjkim#define AMDID_3DNOW 0x80000000 130151348Sjkim 131167493Sjkim#define AMDID2_LAHF 0x00000001 132167493Sjkim#define AMDID2_CMP 0x00000002 133167493Sjkim#define AMDID2_SVM 0x00000004 134167493Sjkim#define AMDID2_EXT_APIC 0x00000008 135167493Sjkim#define AMDID2_CR8 0x00000010 136167493Sjkim#define AMDID2_PREFETCH 0x00000100 137151348Sjkim 138151348Sjkim/* 139109691Sjhb * CPUID instruction 1 ebx info 140108909Sjhb */ 141108909Sjhb#define CPUID_BRAND_INDEX 0x000000ff 142108909Sjhb#define CPUID_CLFUSH_SIZE 0x0000ff00 143108909Sjhb#define CPUID_HTT_CORES 0x00ff0000 144108909Sjhb#define CPUID_LOCAL_APIC_ID 0xff000000 145108909Sjhb 146108909Sjhb/* 147151348Sjkim * AMD extended function 8000_0008h ecx info 148151348Sjkim */ 149167493Sjkim#define AMDID_CMP_CORES 0x000000ff 150151348Sjkim 151151348Sjkim/* 15245406Smsmith * Model-specific registers for the i386 family 15345406Smsmith */ 154167493Sjkim#define MSR_P5_MC_ADDR 0x000 155167493Sjkim#define MSR_P5_MC_TYPE 0x001 156167493Sjkim#define MSR_TSC 0x010 157118954Sjhb#define MSR_P5_CESR 0x011 158118954Sjhb#define MSR_P5_CTR0 0x012 159118954Sjhb#define MSR_P5_CTR1 0x013 160118954Sjhb#define MSR_IA32_PLATFORM_ID 0x017 161167493Sjkim#define MSR_APICBASE 0x01b 162167493Sjkim#define MSR_EBL_CR_POWERON 0x02a 163118954Sjhb#define MSR_TEST_CTL 0x033 164167493Sjkim#define MSR_BIOS_UPDT_TRIG 0x079 165118954Sjhb#define MSR_BBL_CR_D0 0x088 166118954Sjhb#define MSR_BBL_CR_D1 0x089 167118954Sjhb#define MSR_BBL_CR_D2 0x08a 168167493Sjkim#define MSR_BIOS_SIGN 0x08b 169167493Sjkim#define MSR_PERFCTR0 0x0c1 170167493Sjkim#define MSR_PERFCTR1 0x0c2 171167493Sjkim#define MSR_MTRRcap 0x0fe 172118954Sjhb#define MSR_BBL_CR_ADDR 0x116 173118954Sjhb#define MSR_BBL_CR_DECC 0x118 174118954Sjhb#define MSR_BBL_CR_CTL 0x119 175118954Sjhb#define MSR_BBL_CR_TRIG 0x11a 176118954Sjhb#define MSR_BBL_CR_BUSY 0x11b 177118954Sjhb#define MSR_BBL_CR_CTL3 0x11e 178118954Sjhb#define MSR_SYSENTER_CS_MSR 0x174 179118954Sjhb#define MSR_SYSENTER_ESP_MSR 0x175 180118954Sjhb#define MSR_SYSENTER_EIP_MSR 0x176 181167493Sjkim#define MSR_MCG_CAP 0x179 182167493Sjkim#define MSR_MCG_STATUS 0x17a 183167493Sjkim#define MSR_MCG_CTL 0x17b 184167493Sjkim#define MSR_EVNTSEL0 0x186 185167493Sjkim#define MSR_EVNTSEL1 0x187 186167493Sjkim#define MSR_THERM_CONTROL 0x19a 187167493Sjkim#define MSR_THERM_INTERRUPT 0x19b 188167493Sjkim#define MSR_THERM_STATUS 0x19c 189159768Sdavidxu#define MSR_IA32_MISC_ENABLE 0x1a0 190167493Sjkim#define MSR_DEBUGCTLMSR 0x1d9 191167493Sjkim#define MSR_LASTBRANCHFROMIP 0x1db 192167493Sjkim#define MSR_LASTBRANCHTOIP 0x1dc 193167493Sjkim#define MSR_LASTINTFROMIP 0x1dd 194167493Sjkim#define MSR_LASTINTTOIP 0x1de 195167493Sjkim#define MSR_ROB_CR_BKUPTMPDR6 0x1e0 196167493Sjkim#define MSR_MTRRVarBase 0x200 197167493Sjkim#define MSR_MTRR64kBase 0x250 198167493Sjkim#define MSR_MTRR16kBase 0x258 199167493Sjkim#define MSR_MTRR4kBase 0x268 200167493Sjkim#define MSR_PAT 0x277 201167493Sjkim#define MSR_MTRRdefType 0x2ff 202167493Sjkim#define MSR_MC0_CTL 0x400 203167493Sjkim#define MSR_MC0_STATUS 0x401 204167493Sjkim#define MSR_MC0_ADDR 0x402 205167493Sjkim#define MSR_MC0_MISC 0x403 206167493Sjkim#define MSR_MC1_CTL 0x404 207167493Sjkim#define MSR_MC1_STATUS 0x405 208167493Sjkim#define MSR_MC1_ADDR 0x406 209167493Sjkim#define MSR_MC1_MISC 0x407 210167493Sjkim#define MSR_MC2_CTL 0x408 211167493Sjkim#define MSR_MC2_STATUS 0x409 212167493Sjkim#define MSR_MC2_ADDR 0x40a 213167493Sjkim#define MSR_MC2_MISC 0x40b 214167493Sjkim#define MSR_MC3_CTL 0x40c 215167493Sjkim#define MSR_MC3_STATUS 0x40d 216167493Sjkim#define MSR_MC3_ADDR 0x40e 217167493Sjkim#define MSR_MC3_MISC 0x40f 218167493Sjkim#define MSR_MC4_CTL 0x410 219167493Sjkim#define MSR_MC4_STATUS 0x411 220167493Sjkim#define MSR_MC4_ADDR 0x412 221167493Sjkim#define MSR_MC4_MISC 0x413 22245406Smsmith 22345406Smsmith/* 224118954Sjhb * Constants related to MSR's. 225118954Sjhb */ 226118954Sjhb#define APICBASE_RESERVED 0x000006ff 227118954Sjhb#define APICBASE_BSP 0x00000100 228118954Sjhb#define APICBASE_ENABLED 0x00000800 229118954Sjhb#define APICBASE_ADDRESS 0xfffff000 230118954Sjhb 231118954Sjhb/* 232158238Sjhb * PAT modes. 233158238Sjhb */ 234158238Sjhb#define PAT_UNCACHEABLE 0x00 235158238Sjhb#define PAT_WRITE_COMBINING 0x01 236158238Sjhb#define PAT_WRITE_THROUGH 0x04 237158238Sjhb#define PAT_WRITE_PROTECTED 0x05 238158238Sjhb#define PAT_WRITE_BACK 0x06 239158238Sjhb#define PAT_UNCACHED 0x07 240158238Sjhb#define PAT_VALUE(i, m) ((long long)(m) << (8 * (i))) 241158238Sjhb#define PAT_MASK(i) PAT_VALUE(i, 0xff) 242158238Sjhb 243158238Sjhb/* 24445406Smsmith * Constants related to MTRRs 24545406Smsmith */ 246167493Sjkim#define MTRR_N64K 8 /* numbers of fixed-size entries */ 247167493Sjkim#define MTRR_N16K 16 248167493Sjkim#define MTRR_N4K 64 24945406Smsmith 25045406Smsmith/* 25124112Skato * Cyrix configuration registers, accessible as IO ports. 2522495Spst */ 25324112Skato#define CCR0 0xc0 /* Configuration control register 0 */ 25424112Skato#define CCR0_NC0 0x01 /* First 64K of each 1M memory region is 25524112Skato non-cacheable */ 25624112Skato#define CCR0_NC1 0x02 /* 640K-1M region is non-cacheable */ 25724112Skato#define CCR0_A20M 0x04 /* Enables A20M# input pin */ 25824112Skato#define CCR0_KEN 0x08 /* Enables KEN# input pin */ 25924112Skato#define CCR0_FLUSH 0x10 /* Enables FLUSH# input pin */ 26024112Skato#define CCR0_BARB 0x20 /* Flushes internal cache when entering hold 26124112Skato state */ 26224112Skato#define CCR0_CO 0x40 /* Cache org: 1=direct mapped, 0=2x set 26324112Skato assoc */ 26424112Skato#define CCR0_SUSPEND 0x80 /* Enables SUSP# and SUSPA# pins */ 2652495Spst 26624112Skato#define CCR1 0xc1 /* Configuration control register 1 */ 26724112Skato#define CCR1_RPL 0x01 /* Enables RPLSET and RPLVAL# pins */ 26824112Skato#define CCR1_SMI 0x02 /* Enables SMM pins */ 26924112Skato#define CCR1_SMAC 0x04 /* System management memory access */ 27024112Skato#define CCR1_MMAC 0x08 /* Main memory access */ 27124112Skato#define CCR1_NO_LOCK 0x10 /* Negate LOCK# */ 27224112Skato#define CCR1_SM3 0x80 /* SMM address space address region 3 */ 2732495Spst 27424112Skato#define CCR2 0xc2 27524112Skato#define CCR2_WB 0x02 /* Enables WB cache interface pins */ 27624112Skato#define CCR2_SADS 0x02 /* Slow ADS */ 27724112Skato#define CCR2_LOCK_NW 0x04 /* LOCK NW Bit */ 27824112Skato#define CCR2_SUSP_HLT 0x08 /* Suspend on HALT */ 27924112Skato#define CCR2_WT1 0x10 /* WT region 1 */ 28024112Skato#define CCR2_WPR1 0x10 /* Write-protect region 1 */ 281167493Sjkim#define CCR2_BARB 0x20 /* Flushes write-back cache when entering 28224112Skato hold state. */ 28324112Skato#define CCR2_BWRT 0x40 /* Enables burst write cycles */ 28424112Skato#define CCR2_USE_SUSP 0x80 /* Enables suspend pins */ 28524112Skato 28624112Skato#define CCR3 0xc3 28724112Skato#define CCR3_SMILOCK 0x01 /* SMM register lock */ 28824112Skato#define CCR3_NMI 0x02 /* Enables NMI during SMM */ 28924112Skato#define CCR3_LINBRST 0x04 /* Linear address burst cycles */ 29024112Skato#define CCR3_SMMMODE 0x08 /* SMM Mode */ 29124112Skato#define CCR3_MAPEN0 0x10 /* Enables Map0 */ 29224112Skato#define CCR3_MAPEN1 0x20 /* Enables Map1 */ 29324112Skato#define CCR3_MAPEN2 0x40 /* Enables Map2 */ 29424112Skato#define CCR3_MAPEN3 0x80 /* Enables Map3 */ 29524112Skato 29624112Skato#define CCR4 0xe8 29724112Skato#define CCR4_IOMASK 0x07 29824112Skato#define CCR4_MEM 0x08 /* Enables momory bypassing */ 29924112Skato#define CCR4_DTE 0x10 /* Enables directory table entry cache */ 30024112Skato#define CCR4_FASTFPE 0x20 /* Fast FPU exception */ 30124112Skato#define CCR4_CPUID 0x80 /* Enables CPUID instruction */ 30224112Skato 30324112Skato#define CCR5 0xe9 30424112Skato#define CCR5_WT_ALLOC 0x01 /* Write-through allocate */ 30524112Skato#define CCR5_SLOP 0x02 /* LOOP instruction slowed down */ 30624112Skato#define CCR5_LBR1 0x10 /* Local bus region 1 */ 30724112Skato#define CCR5_ARREN 0x20 /* Enables ARR region */ 30824112Skato 30934031Skato#define CCR6 0xea 31034031Skato 31134031Skato#define CCR7 0xeb 31234031Skato 31324112Skato/* Performance Control Register (5x86 only). */ 31424112Skato#define PCR0 0x20 31524112Skato#define PCR0_RSTK 0x01 /* Enables return stack */ 31624112Skato#define PCR0_BTB 0x02 /* Enables branch target buffer */ 31724112Skato#define PCR0_LOOP 0x04 /* Enables loop */ 31824112Skato#define PCR0_AIS 0x08 /* Enables all instrcutions stalled to 31924112Skato serialize pipe. */ 32024112Skato#define PCR0_MLR 0x10 /* Enables reordering of misaligned loads */ 32124112Skato#define PCR0_BTBRT 0x40 /* Enables BTB test register. */ 32224112Skato#define PCR0_LSSER 0x80 /* Disable reorder */ 32324112Skato 32424112Skato/* Device Identification Registers */ 32524112Skato#define DIR0 0xfe 32624112Skato#define DIR1 0xff 32724112Skato 3282495Spst/* 32924112Skato * The following four 3-byte registers control the non-cacheable regions. 33013765Smpp * These registers must be written as three separate bytes. 3312495Spst * 3322495Spst * NCRx+0: A31-A24 of starting address 3332495Spst * NCRx+1: A23-A16 of starting address 3342495Spst * NCRx+2: A15-A12 of starting address | NCR_SIZE_xx. 3358876Srgrimes * 3362495Spst * The non-cacheable region's starting address must be aligned to the 3372495Spst * size indicated by the NCR_SIZE_xx field. 3382495Spst */ 33924112Skato#define NCR1 0xc4 34024112Skato#define NCR2 0xc7 34124112Skato#define NCR3 0xca 34224112Skato#define NCR4 0xcd 3432495Spst 34424112Skato#define NCR_SIZE_0K 0 34524112Skato#define NCR_SIZE_4K 1 34624112Skato#define NCR_SIZE_8K 2 34724112Skato#define NCR_SIZE_16K 3 34824112Skato#define NCR_SIZE_32K 4 34924112Skato#define NCR_SIZE_64K 5 35024112Skato#define NCR_SIZE_128K 6 35124112Skato#define NCR_SIZE_256K 7 35224112Skato#define NCR_SIZE_512K 8 35324112Skato#define NCR_SIZE_1M 9 35424112Skato#define NCR_SIZE_2M 10 35524112Skato#define NCR_SIZE_4M 11 35624112Skato#define NCR_SIZE_8M 12 35724112Skato#define NCR_SIZE_16M 13 35824112Skato#define NCR_SIZE_32M 14 35924112Skato#define NCR_SIZE_4G 15 3602495Spst 36124112Skato/* 36224112Skato * The address region registers are used to specify the location and 36324112Skato * size for the eight address regions. 36424112Skato * 36524112Skato * ARRx + 0: A31-A24 of start address 36624112Skato * ARRx + 1: A23-A16 of start address 36724112Skato * ARRx + 2: A15-A12 of start address | ARR_SIZE_xx 36824112Skato */ 36924112Skato#define ARR0 0xc4 37024112Skato#define ARR1 0xc7 37124112Skato#define ARR2 0xca 37224112Skato#define ARR3 0xcd 37324112Skato#define ARR4 0xd0 37424112Skato#define ARR5 0xd3 37524112Skato#define ARR6 0xd6 37624112Skato#define ARR7 0xd9 37724112Skato 37824112Skato#define ARR_SIZE_0K 0 37924112Skato#define ARR_SIZE_4K 1 38024112Skato#define ARR_SIZE_8K 2 38124112Skato#define ARR_SIZE_16K 3 38224112Skato#define ARR_SIZE_32K 4 38324112Skato#define ARR_SIZE_64K 5 38424112Skato#define ARR_SIZE_128K 6 38524112Skato#define ARR_SIZE_256K 7 38624112Skato#define ARR_SIZE_512K 8 38724112Skato#define ARR_SIZE_1M 9 38824112Skato#define ARR_SIZE_2M 10 38924112Skato#define ARR_SIZE_4M 11 39024112Skato#define ARR_SIZE_8M 12 39124112Skato#define ARR_SIZE_16M 13 39224112Skato#define ARR_SIZE_32M 14 39324112Skato#define ARR_SIZE_4G 15 39424112Skato 39524112Skato/* 39624112Skato * The region control registers specify the attributes associated with 39724112Skato * the ARRx addres regions. 39824112Skato */ 39924112Skato#define RCR0 0xdc 40024112Skato#define RCR1 0xdd 40124112Skato#define RCR2 0xde 40224112Skato#define RCR3 0xdf 40324112Skato#define RCR4 0xe0 40424112Skato#define RCR5 0xe1 40524112Skato#define RCR6 0xe2 40624112Skato#define RCR7 0xe3 40724112Skato 408167493Sjkim#define RCR_RCD 0x01 /* Disables caching for ARRx (x = 0-6). */ 409167493Sjkim#define RCR_RCE 0x01 /* Enables caching for ARR7. */ 410167493Sjkim#define RCR_WWO 0x02 /* Weak write ordering. */ 41124112Skato#define RCR_WL 0x04 /* Weak locking. */ 412167493Sjkim#define RCR_WG 0x08 /* Write gathering. */ 41324112Skato#define RCR_WT 0x10 /* Write-through. */ 41424112Skato#define RCR_NLB 0x20 /* LBA# pin is not asserted. */ 41524112Skato 41640003Skato/* AMD Write Allocate Top-Of-Memory and Control Register */ 41740003Skato#define AMD_WT_ALLOC_TME 0x40000 /* top-of-memory enable */ 41840003Skato#define AMD_WT_ALLOC_PRE 0x20000 /* programmable range enable */ 41940003Skato#define AMD_WT_ALLOC_FRE 0x10000 /* fixed (A0000-FFFFF) range enable */ 42024112Skato 421160305Smr/* VIA ACE crypto featureset: for via_feature_rng */ 422167493Sjkim#define VIA_HAS_RNG 1 /* cpu has RNG */ 423160305Smr 424160305Smr/* VIA ACE crypto featureset: for via_feature_xcrypt */ 425167493Sjkim#define VIA_HAS_AES 1 /* cpu has AES */ 426167493Sjkim#define VIA_HAS_SHA 2 /* cpu has SHA1 & SHA256 */ 427167493Sjkim#define VIA_HAS_MM 4 /* cpu has RSA instructions */ 428167493Sjkim#define VIA_HAS_AESCTR 8 /* cpu has AES-CTR instructions */ 42940003Skato 430160298Smr/* Centaur Extended Feature flags */ 431167493Sjkim#define VIA_CPUID_HAS_RNG 0x000004 432167493Sjkim#define VIA_CPUID_DO_RNG 0x000008 433167493Sjkim#define VIA_CPUID_HAS_ACE 0x000040 434167493Sjkim#define VIA_CPUID_DO_ACE 0x000080 435167493Sjkim#define VIA_CPUID_HAS_ACE2 0x000100 436167493Sjkim#define VIA_CPUID_DO_ACE2 0x000200 437167493Sjkim#define VIA_CPUID_HAS_PHE 0x000400 438167493Sjkim#define VIA_CPUID_DO_PHE 0x000800 439167493Sjkim#define VIA_CPUID_HAS_PMM 0x001000 440167493Sjkim#define VIA_CPUID_DO_PMM 0x002000 441160298Smr 442160298Smr/* VIA ACE xcrypt-* instruction context control options */ 443167493Sjkim#define VIA_CRYPT_CWLO_ROUND_M 0x0000000f 444167493Sjkim#define VIA_CRYPT_CWLO_ALG_M 0x00000070 445167493Sjkim#define VIA_CRYPT_CWLO_ALG_AES 0x00000000 446167493Sjkim#define VIA_CRYPT_CWLO_KEYGEN_M 0x00000080 447167493Sjkim#define VIA_CRYPT_CWLO_KEYGEN_HW 0x00000000 448167493Sjkim#define VIA_CRYPT_CWLO_KEYGEN_SW 0x00000080 449167493Sjkim#define VIA_CRYPT_CWLO_NORMAL 0x00000000 450167493Sjkim#define VIA_CRYPT_CWLO_INTERMEDIATE 0x00000100 451167493Sjkim#define VIA_CRYPT_CWLO_ENCRYPT 0x00000000 452167493Sjkim#define VIA_CRYPT_CWLO_DECRYPT 0x00000200 453167493Sjkim#define VIA_CRYPT_CWLO_KEY128 0x0000000a /* 128bit, 10 rds */ 454167493Sjkim#define VIA_CRYPT_CWLO_KEY192 0x0000040c /* 192bit, 12 rds */ 455167493Sjkim#define VIA_CRYPT_CWLO_KEY256 0x0000080e /* 256bit, 15 rds */ 456160298Smr 45724112Skato#ifndef LOCORE 45824112Skatostatic __inline u_char 45924112Skatoread_cyrix_reg(u_char reg) 46024112Skato{ 46124112Skato outb(0x22, reg); 46224112Skato return inb(0x23); 46324112Skato} 46424112Skato 46524112Skatostatic __inline void 46624112Skatowrite_cyrix_reg(u_char reg, u_char data) 46724112Skato{ 46824112Skato outb(0x22, reg); 46924112Skato outb(0x23, data); 47024112Skato} 47124112Skato#endif 47224112Skato 4735594Sbde#endif /* !_MACHINE_SPECIALREG_H_ */ 474