14Srgrimes/*- 24Srgrimes * Copyright (c) 1991 The Regents of the University of California. 34Srgrimes * All rights reserved. 44Srgrimes * 54Srgrimes * Redistribution and use in source and binary forms, with or without 64Srgrimes * modification, are permitted provided that the following conditions 74Srgrimes * are met: 84Srgrimes * 1. Redistributions of source code must retain the above copyright 94Srgrimes * notice, this list of conditions and the following disclaimer. 104Srgrimes * 2. Redistributions in binary form must reproduce the above copyright 114Srgrimes * notice, this list of conditions and the following disclaimer in the 124Srgrimes * documentation and/or other materials provided with the distribution. 134Srgrimes * 4. Neither the name of the University nor the names of its contributors 144Srgrimes * may be used to endorse or promote products derived from this software 154Srgrimes * without specific prior written permission. 164Srgrimes * 174Srgrimes * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 184Srgrimes * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 194Srgrimes * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 204Srgrimes * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 214Srgrimes * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 224Srgrimes * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 234Srgrimes * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 244Srgrimes * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 254Srgrimes * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 264Srgrimes * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 274Srgrimes * SUCH DAMAGE. 284Srgrimes * 29621Srgrimes * from: @(#)specialreg.h 7.1 (Berkeley) 5/9/91 3050477Speter * $FreeBSD$ 314Srgrimes */ 324Srgrimes 33719Swollman#ifndef _MACHINE_SPECIALREG_H_ 345594Sbde#define _MACHINE_SPECIALREG_H_ 35719Swollman 364Srgrimes/* 374Srgrimes * Bits in 386 special registers: 384Srgrimes */ 394Srgrimes#define CR0_PE 0x00000001 /* Protected mode Enable */ 40160329Sjkim#define CR0_MP 0x00000002 /* "Math" (fpu) Present */ 41160329Sjkim#define CR0_EM 0x00000004 /* EMulate FPU instructions. (trap ESC only) */ 424Srgrimes#define CR0_TS 0x00000008 /* Task Switched (if MP, trap ESC and WAIT) */ 434Srgrimes#define CR0_PG 0x80000000 /* PaGing enable */ 444Srgrimes 454Srgrimes/* 464Srgrimes * Bits in 486 special registers: 474Srgrimes */ 4824112Skato#define CR0_NE 0x00000020 /* Numeric Error enable (EX16 vs IRQ13) */ 4924112Skato#define CR0_WP 0x00010000 /* Write Protect (honor page protect in 5024112Skato all modes) */ 5124112Skato#define CR0_AM 0x00040000 /* Alignment Mask (set to enable AC flag) */ 5224112Skato#define CR0_NW 0x20000000 /* Not Write-through */ 5324112Skato#define CR0_CD 0x40000000 /* Cache Disable */ 542495Spst 552495Spst/* 5619621Sdyson * Bits in PPro special registers 5719621Sdyson */ 5819621Sdyson#define CR4_VME 0x00000001 /* Virtual 8086 mode extensions */ 5919621Sdyson#define CR4_PVI 0x00000002 /* Protected-mode virtual interrupts */ 6019621Sdyson#define CR4_TSD 0x00000004 /* Time stamp disable */ 6119621Sdyson#define CR4_DE 0x00000008 /* Debugging extensions */ 6219621Sdyson#define CR4_PSE 0x00000010 /* Page size extensions */ 6319621Sdyson#define CR4_PAE 0x00000020 /* Physical address extension */ 6419621Sdyson#define CR4_MCE 0x00000040 /* Machine check enable */ 6519621Sdyson#define CR4_PGE 0x00000080 /* Page global enable */ 6619621Sdyson#define CR4_PCE 0x00000100 /* Performance monitoring counter enable */ 6751127Speter#define CR4_FXSR 0x00000200 /* Fast FPU save/restore used by OS */ 6851127Speter#define CR4_XMM 0x00000400 /* enable SIMD/MMX2 to use except 16 */ 69230501Skib#define CR4_XSAVE 0x00040000 /* XSETBV/XGETBV */ 7019621Sdyson 7119621Sdyson/* 72168439Sru * Bits in AMD64 special registers. EFER is 64 bits wide. 73168439Sru */ 74168439Sru#define EFER_NXE 0x000000800 /* PTE No-Execute bit enable (R/W) */ 75168439Sru 76168439Sru/* 7719621Sdyson * CPUID instruction features register 7819621Sdyson */ 7998650Smp#define CPUID_FPU 0x00000001 8098650Smp#define CPUID_VME 0x00000002 8198650Smp#define CPUID_DE 0x00000004 8298650Smp#define CPUID_PSE 0x00000008 8398650Smp#define CPUID_TSC 0x00000010 8498650Smp#define CPUID_MSR 0x00000020 8598650Smp#define CPUID_PAE 0x00000040 8698650Smp#define CPUID_MCE 0x00000080 8798650Smp#define CPUID_CX8 0x00000100 8898650Smp#define CPUID_APIC 0x00000200 8998650Smp#define CPUID_B10 0x00000400 9098650Smp#define CPUID_SEP 0x00000800 9198650Smp#define CPUID_MTRR 0x00001000 9298650Smp#define CPUID_PGE 0x00002000 9398650Smp#define CPUID_MCA 0x00004000 9498650Smp#define CPUID_CMOV 0x00008000 9598650Smp#define CPUID_PAT 0x00010000 9698650Smp#define CPUID_PSE36 0x00020000 9798650Smp#define CPUID_PSN 0x00040000 9898650Smp#define CPUID_CLFSH 0x00080000 9998650Smp#define CPUID_B20 0x00100000 10098650Smp#define CPUID_DS 0x00200000 10198650Smp#define CPUID_ACPI 0x00400000 10298650Smp#define CPUID_MMX 0x00800000 10398650Smp#define CPUID_FXSR 0x01000000 10498650Smp#define CPUID_SSE 0x02000000 10598650Smp#define CPUID_XMM 0x02000000 10698650Smp#define CPUID_SSE2 0x04000000 10798650Smp#define CPUID_SS 0x08000000 108108909Sjhb#define CPUID_HTT 0x10000000 10998650Smp#define CPUID_TM 0x20000000 110114376Speter#define CPUID_IA64 0x40000000 11198650Smp#define CPUID_PBE 0x80000000 11219621Sdyson 113167493Sjkim#define CPUID2_SSE3 0x00000001 114207676Skib#define CPUID2_PCLMULQDQ 0x00000002 115183128Sjhb#define CPUID2_DTES64 0x00000004 116167493Sjkim#define CPUID2_MON 0x00000008 117167493Sjkim#define CPUID2_DS_CPL 0x00000010 118167493Sjkim#define CPUID2_VMX 0x00000020 119167744Sjkim#define CPUID2_SMX 0x00000040 120167493Sjkim#define CPUID2_EST 0x00000080 121167493Sjkim#define CPUID2_TM2 0x00000100 122167493Sjkim#define CPUID2_SSSE3 0x00000200 123167493Sjkim#define CPUID2_CNXTID 0x00000400 124222043Sjkim#define CPUID2_FMA 0x00001000 125167493Sjkim#define CPUID2_CX16 0x00002000 126167493Sjkim#define CPUID2_XTPR 0x00004000 127170150Sdes#define CPUID2_PDCM 0x00008000 128213452Skib#define CPUID2_PCID 0x00020000 129167744Sjkim#define CPUID2_DCA 0x00040000 130183128Sjhb#define CPUID2_SSE41 0x00080000 131183128Sjhb#define CPUID2_SSE42 0x00100000 132183128Sjhb#define CPUID2_X2APIC 0x00200000 133199968Savg#define CPUID2_MOVBE 0x00400000 134183128Sjhb#define CPUID2_POPCNT 0x00800000 135222043Sjkim#define CPUID2_TSCDLT 0x01000000 136207676Skib#define CPUID2_AESNI 0x02000000 137222043Sjkim#define CPUID2_XSAVE 0x04000000 138222043Sjkim#define CPUID2_OSXSAVE 0x08000000 139222043Sjkim#define CPUID2_AVX 0x10000000 140222043Sjkim#define CPUID2_F16C 0x20000000 141234391Sjhb#define CPUID2_RDRAND 0x40000000 142221188Sjkim#define CPUID2_HV 0x80000000 143160329Sjkim 14419621Sdyson/* 145215748Savg * Important bits in the Thermal and Power Management flags 146215748Savg * CPUID.6 EAX and ECX. 147215748Savg */ 148215748Savg#define CPUTPM1_SENSOR 0x00000001 149215748Savg#define CPUTPM1_TURBO 0x00000002 150215748Savg#define CPUTPM1_ARAT 0x00000004 151215748Savg#define CPUTPM2_EFFREQ 0x00000001 152215748Savg 153215748Savg/* 154151348Sjkim * Important bits in the AMD extended cpuid flags 155151348Sjkim */ 156167493Sjkim#define AMDID_SYSCALL 0x00000800 157167493Sjkim#define AMDID_MP 0x00080000 158167493Sjkim#define AMDID_NX 0x00100000 159167493Sjkim#define AMDID_EXT_MMX 0x00400000 160167493Sjkim#define AMDID_FFXSR 0x01000000 161183128Sjhb#define AMDID_PAGE1GB 0x04000000 162167493Sjkim#define AMDID_RDTSCP 0x08000000 163167493Sjkim#define AMDID_LM 0x20000000 164167493Sjkim#define AMDID_EXT_3DNOW 0x40000000 165167493Sjkim#define AMDID_3DNOW 0x80000000 166151348Sjkim 167167493Sjkim#define AMDID2_LAHF 0x00000001 168167493Sjkim#define AMDID2_CMP 0x00000002 169167493Sjkim#define AMDID2_SVM 0x00000004 170167493Sjkim#define AMDID2_EXT_APIC 0x00000008 171167493Sjkim#define AMDID2_CR8 0x00000010 172186009Sjkim#define AMDID2_ABM 0x00000020 173186009Sjkim#define AMDID2_SSE4A 0x00000040 174186009Sjkim#define AMDID2_MAS 0x00000080 175167493Sjkim#define AMDID2_PREFETCH 0x00000100 176186009Sjkim#define AMDID2_OSVW 0x00000200 177186009Sjkim#define AMDID2_IBS 0x00000400 178222043Sjkim#define AMDID2_XOP 0x00000800 179186009Sjkim#define AMDID2_SKINIT 0x00001000 180186009Sjkim#define AMDID2_WDT 0x00002000 181222043Sjkim#define AMDID2_LWP 0x00008000 182222043Sjkim#define AMDID2_FMA4 0x00010000 183258161Skib#define AMDID2_TCE 0x00020000 184222043Sjkim#define AMDID2_NODE_ID 0x00080000 185222043Sjkim#define AMDID2_TBM 0x00200000 186222043Sjkim#define AMDID2_TOPOLOGY 0x00400000 187258161Skib#define AMDID2_PCXC 0x00800000 188258161Skib#define AMDID2_PNXC 0x01000000 189258161Skib#define AMDID2_DBE 0x04000000 190258161Skib#define AMDID2_PTSC 0x08000000 191258161Skib#define AMDID2_PTSCEL2I 0x10000000 192151348Sjkim 193151348Sjkim/* 194184146Sjkim * CPUID instruction 1 eax info 195184146Sjkim */ 196184146Sjkim#define CPUID_STEPPING 0x0000000f 197184146Sjkim#define CPUID_MODEL 0x000000f0 198184146Sjkim#define CPUID_FAMILY 0x00000f00 199184146Sjkim#define CPUID_EXT_MODEL 0x000f0000 200184146Sjkim#define CPUID_EXT_FAMILY 0x0ff00000 201197070Sjkim#define CPUID_TO_MODEL(id) \ 202184146Sjkim ((((id) & CPUID_MODEL) >> 4) | \ 203184146Sjkim ((((id) & CPUID_FAMILY) >= 0x600) ? \ 204184146Sjkim (((id) & CPUID_EXT_MODEL) >> 12) : 0)) 205197070Sjkim#define CPUID_TO_FAMILY(id) \ 206184146Sjkim ((((id) & CPUID_FAMILY) >> 8) + \ 207184146Sjkim ((((id) & CPUID_FAMILY) == 0xf00) ? \ 208184146Sjkim (((id) & CPUID_EXT_FAMILY) >> 20) : 0)) 209184146Sjkim 210184146Sjkim/* 211109691Sjhb * CPUID instruction 1 ebx info 212108909Sjhb */ 213108909Sjhb#define CPUID_BRAND_INDEX 0x000000ff 214108909Sjhb#define CPUID_CLFUSH_SIZE 0x0000ff00 215108909Sjhb#define CPUID_HTT_CORES 0x00ff0000 216108909Sjhb#define CPUID_LOCAL_APIC_ID 0xff000000 217108909Sjhb 218220578Sjkim/* 219220578Sjkim * CPUID instruction 6 ecx info 220220578Sjkim */ 221220578Sjkim#define CPUID_PERF_STAT 0x00000001 222220578Sjkim#define CPUID_PERF_BIAS 0x00000008 223220578Sjkim 224191648Sjeff/* 225191648Sjeff * CPUID instruction 0xb ebx info. 226191648Sjeff */ 227191648Sjeff#define CPUID_TYPE_INVAL 0 228191648Sjeff#define CPUID_TYPE_SMT 1 229191648Sjeff#define CPUID_TYPE_CORE 2 230191648Sjeff 231108909Sjhb/* 232239942Skib * CPUID instruction 0xd Processor Extended State Enumeration Sub-leaf 1 233239942Skib */ 234239942Skib#define CPUID_EXTSTATE_XSAVEOPT 0x00000001 235239942Skib 236239942Skib/* 237184101Sjkim * AMD extended function 8000_0007h edx info 238184101Sjkim */ 239184101Sjkim#define AMDPM_TS 0x00000001 240184101Sjkim#define AMDPM_FID 0x00000002 241184101Sjkim#define AMDPM_VID 0x00000004 242184101Sjkim#define AMDPM_TTP 0x00000008 243184101Sjkim#define AMDPM_TM 0x00000010 244184101Sjkim#define AMDPM_STC 0x00000020 245184101Sjkim#define AMDPM_100MHZ_STEPS 0x00000040 246184101Sjkim#define AMDPM_HW_PSTATE 0x00000080 247184101Sjkim#define AMDPM_TSC_INVARIANT 0x00000100 248215522Savg#define AMDPM_CPB 0x00000200 249184101Sjkim 250184101Sjkim/* 251151348Sjkim * AMD extended function 8000_0008h ecx info 252151348Sjkim */ 253167493Sjkim#define AMDID_CMP_CORES 0x000000ff 254221527Savg#define AMDID_COREID_SIZE 0x0000f000 255221527Savg#define AMDID_COREID_SIZE_SHIFT 12 256151348Sjkim 257151348Sjkim/* 258181430Sstas * CPUID manufacturers identifiers 259181430Sstas */ 260185341Sjkim#define AMD_VENDOR_ID "AuthenticAMD" 261185341Sjkim#define CENTAUR_VENDOR_ID "CentaurHauls" 262185341Sjkim#define CYRIX_VENDOR_ID "CyrixInstead" 263185341Sjkim#define INTEL_VENDOR_ID "GenuineIntel" 264185341Sjkim#define NEXGEN_VENDOR_ID "NexGenDriven" 265185341Sjkim#define NSC_VENDOR_ID "Geode by NSC" 266185341Sjkim#define RISE_VENDOR_ID "RiseRiseRise" 267185341Sjkim#define SIS_VENDOR_ID "SiS SiS SiS " 268185341Sjkim#define TRANSMETA_VENDOR_ID "GenuineTMx86" 269185341Sjkim#define UMC_VENDOR_ID "UMC UMC UMC " 270181430Sstas 271181430Sstas/* 27245406Smsmith * Model-specific registers for the i386 family 27345406Smsmith */ 274167493Sjkim#define MSR_P5_MC_ADDR 0x000 275167493Sjkim#define MSR_P5_MC_TYPE 0x001 276167493Sjkim#define MSR_TSC 0x010 277118954Sjhb#define MSR_P5_CESR 0x011 278118954Sjhb#define MSR_P5_CTR0 0x012 279118954Sjhb#define MSR_P5_CTR1 0x013 280118954Sjhb#define MSR_IA32_PLATFORM_ID 0x017 281167493Sjkim#define MSR_APICBASE 0x01b 282167493Sjkim#define MSR_EBL_CR_POWERON 0x02a 283118954Sjhb#define MSR_TEST_CTL 0x033 284167493Sjkim#define MSR_BIOS_UPDT_TRIG 0x079 285118954Sjhb#define MSR_BBL_CR_D0 0x088 286118954Sjhb#define MSR_BBL_CR_D1 0x089 287118954Sjhb#define MSR_BBL_CR_D2 0x08a 288167493Sjkim#define MSR_BIOS_SIGN 0x08b 289167493Sjkim#define MSR_PERFCTR0 0x0c1 290167493Sjkim#define MSR_PERFCTR1 0x0c2 291215524Savg#define MSR_MPERF 0x0e7 292215524Savg#define MSR_APERF 0x0e8 293171854Sdes#define MSR_IA32_EXT_CONFIG 0x0ee /* Undocumented. Core Solo/Duo only */ 294167493Sjkim#define MSR_MTRRcap 0x0fe 295118954Sjhb#define MSR_BBL_CR_ADDR 0x116 296118954Sjhb#define MSR_BBL_CR_DECC 0x118 297118954Sjhb#define MSR_BBL_CR_CTL 0x119 298118954Sjhb#define MSR_BBL_CR_TRIG 0x11a 299118954Sjhb#define MSR_BBL_CR_BUSY 0x11b 300118954Sjhb#define MSR_BBL_CR_CTL3 0x11e 301118954Sjhb#define MSR_SYSENTER_CS_MSR 0x174 302118954Sjhb#define MSR_SYSENTER_ESP_MSR 0x175 303118954Sjhb#define MSR_SYSENTER_EIP_MSR 0x176 304167493Sjkim#define MSR_MCG_CAP 0x179 305167493Sjkim#define MSR_MCG_STATUS 0x17a 306167493Sjkim#define MSR_MCG_CTL 0x17b 307167493Sjkim#define MSR_EVNTSEL0 0x186 308167493Sjkim#define MSR_EVNTSEL1 0x187 309167493Sjkim#define MSR_THERM_CONTROL 0x19a 310167493Sjkim#define MSR_THERM_INTERRUPT 0x19b 311167493Sjkim#define MSR_THERM_STATUS 0x19c 312159768Sdavidxu#define MSR_IA32_MISC_ENABLE 0x1a0 313210624Sdelphij#define MSR_IA32_TEMPERATURE_TARGET 0x1a2 314167493Sjkim#define MSR_DEBUGCTLMSR 0x1d9 315167493Sjkim#define MSR_LASTBRANCHFROMIP 0x1db 316167493Sjkim#define MSR_LASTBRANCHTOIP 0x1dc 317167493Sjkim#define MSR_LASTINTFROMIP 0x1dd 318167493Sjkim#define MSR_LASTINTTOIP 0x1de 319167493Sjkim#define MSR_ROB_CR_BKUPTMPDR6 0x1e0 320167493Sjkim#define MSR_MTRRVarBase 0x200 321167493Sjkim#define MSR_MTRR64kBase 0x250 322167493Sjkim#define MSR_MTRR16kBase 0x258 323167493Sjkim#define MSR_MTRR4kBase 0x268 324167493Sjkim#define MSR_PAT 0x277 325205214Sjhb#define MSR_MC0_CTL2 0x280 326167493Sjkim#define MSR_MTRRdefType 0x2ff 327167493Sjkim#define MSR_MC0_CTL 0x400 328167493Sjkim#define MSR_MC0_STATUS 0x401 329167493Sjkim#define MSR_MC0_ADDR 0x402 330167493Sjkim#define MSR_MC0_MISC 0x403 331167493Sjkim#define MSR_MC1_CTL 0x404 332167493Sjkim#define MSR_MC1_STATUS 0x405 333167493Sjkim#define MSR_MC1_ADDR 0x406 334167493Sjkim#define MSR_MC1_MISC 0x407 335167493Sjkim#define MSR_MC2_CTL 0x408 336167493Sjkim#define MSR_MC2_STATUS 0x409 337167493Sjkim#define MSR_MC2_ADDR 0x40a 338167493Sjkim#define MSR_MC2_MISC 0x40b 339167493Sjkim#define MSR_MC3_CTL 0x40c 340167493Sjkim#define MSR_MC3_STATUS 0x40d 341167493Sjkim#define MSR_MC3_ADDR 0x40e 342167493Sjkim#define MSR_MC3_MISC 0x40f 343167493Sjkim#define MSR_MC4_CTL 0x410 344167493Sjkim#define MSR_MC4_STATUS 0x411 345167493Sjkim#define MSR_MC4_ADDR 0x412 346167493Sjkim#define MSR_MC4_MISC 0x413 34745406Smsmith 34845406Smsmith/* 349118954Sjhb * Constants related to MSR's. 350118954Sjhb */ 351118954Sjhb#define APICBASE_RESERVED 0x000006ff 352118954Sjhb#define APICBASE_BSP 0x00000100 353118954Sjhb#define APICBASE_ENABLED 0x00000800 354118954Sjhb#define APICBASE_ADDRESS 0xfffff000 355118954Sjhb 356118954Sjhb/* 357158238Sjhb * PAT modes. 358158238Sjhb */ 359158238Sjhb#define PAT_UNCACHEABLE 0x00 360158238Sjhb#define PAT_WRITE_COMBINING 0x01 361158238Sjhb#define PAT_WRITE_THROUGH 0x04 362158238Sjhb#define PAT_WRITE_PROTECTED 0x05 363158238Sjhb#define PAT_WRITE_BACK 0x06 364158238Sjhb#define PAT_UNCACHED 0x07 365158238Sjhb#define PAT_VALUE(i, m) ((long long)(m) << (8 * (i))) 366158238Sjhb#define PAT_MASK(i) PAT_VALUE(i, 0xff) 367158238Sjhb 368158238Sjhb/* 36945406Smsmith * Constants related to MTRRs 37045406Smsmith */ 371177069Sjhb#define MTRR_UNCACHEABLE 0x00 372177069Sjhb#define MTRR_WRITE_COMBINING 0x01 373177069Sjhb#define MTRR_WRITE_THROUGH 0x04 374177069Sjhb#define MTRR_WRITE_PROTECTED 0x05 375177069Sjhb#define MTRR_WRITE_BACK 0x06 376167493Sjkim#define MTRR_N64K 8 /* numbers of fixed-size entries */ 377167493Sjkim#define MTRR_N16K 16 378167493Sjkim#define MTRR_N4K 64 379205448Sjhb#define MTRR_CAP_WC 0x0000000000000400 380205448Sjhb#define MTRR_CAP_FIXED 0x0000000000000100 381205448Sjhb#define MTRR_CAP_VCNT 0x00000000000000ff 382205448Sjhb#define MTRR_DEF_ENABLE 0x0000000000000800 383205448Sjhb#define MTRR_DEF_FIXED_ENABLE 0x0000000000000400 384205448Sjhb#define MTRR_DEF_TYPE 0x00000000000000ff 385205448Sjhb#define MTRR_PHYSBASE_PHYSBASE 0x000ffffffffff000 386205448Sjhb#define MTRR_PHYSBASE_TYPE 0x00000000000000ff 387205448Sjhb#define MTRR_PHYSMASK_PHYSMASK 0x000ffffffffff000 388205448Sjhb#define MTRR_PHYSMASK_VALID 0x0000000000000800 38945406Smsmith 39045406Smsmith/* 39124112Skato * Cyrix configuration registers, accessible as IO ports. 3922495Spst */ 39324112Skato#define CCR0 0xc0 /* Configuration control register 0 */ 39424112Skato#define CCR0_NC0 0x01 /* First 64K of each 1M memory region is 39524112Skato non-cacheable */ 39624112Skato#define CCR0_NC1 0x02 /* 640K-1M region is non-cacheable */ 39724112Skato#define CCR0_A20M 0x04 /* Enables A20M# input pin */ 39824112Skato#define CCR0_KEN 0x08 /* Enables KEN# input pin */ 39924112Skato#define CCR0_FLUSH 0x10 /* Enables FLUSH# input pin */ 40024112Skato#define CCR0_BARB 0x20 /* Flushes internal cache when entering hold 40124112Skato state */ 40224112Skato#define CCR0_CO 0x40 /* Cache org: 1=direct mapped, 0=2x set 40324112Skato assoc */ 40424112Skato#define CCR0_SUSPEND 0x80 /* Enables SUSP# and SUSPA# pins */ 4052495Spst 40624112Skato#define CCR1 0xc1 /* Configuration control register 1 */ 40724112Skato#define CCR1_RPL 0x01 /* Enables RPLSET and RPLVAL# pins */ 40824112Skato#define CCR1_SMI 0x02 /* Enables SMM pins */ 40924112Skato#define CCR1_SMAC 0x04 /* System management memory access */ 41024112Skato#define CCR1_MMAC 0x08 /* Main memory access */ 41124112Skato#define CCR1_NO_LOCK 0x10 /* Negate LOCK# */ 41224112Skato#define CCR1_SM3 0x80 /* SMM address space address region 3 */ 4132495Spst 41424112Skato#define CCR2 0xc2 41524112Skato#define CCR2_WB 0x02 /* Enables WB cache interface pins */ 41624112Skato#define CCR2_SADS 0x02 /* Slow ADS */ 41724112Skato#define CCR2_LOCK_NW 0x04 /* LOCK NW Bit */ 41824112Skato#define CCR2_SUSP_HLT 0x08 /* Suspend on HALT */ 41924112Skato#define CCR2_WT1 0x10 /* WT region 1 */ 42024112Skato#define CCR2_WPR1 0x10 /* Write-protect region 1 */ 421167493Sjkim#define CCR2_BARB 0x20 /* Flushes write-back cache when entering 42224112Skato hold state. */ 42324112Skato#define CCR2_BWRT 0x40 /* Enables burst write cycles */ 42424112Skato#define CCR2_USE_SUSP 0x80 /* Enables suspend pins */ 42524112Skato 42624112Skato#define CCR3 0xc3 42724112Skato#define CCR3_SMILOCK 0x01 /* SMM register lock */ 42824112Skato#define CCR3_NMI 0x02 /* Enables NMI during SMM */ 42924112Skato#define CCR3_LINBRST 0x04 /* Linear address burst cycles */ 43024112Skato#define CCR3_SMMMODE 0x08 /* SMM Mode */ 43124112Skato#define CCR3_MAPEN0 0x10 /* Enables Map0 */ 43224112Skato#define CCR3_MAPEN1 0x20 /* Enables Map1 */ 43324112Skato#define CCR3_MAPEN2 0x40 /* Enables Map2 */ 43424112Skato#define CCR3_MAPEN3 0x80 /* Enables Map3 */ 43524112Skato 43624112Skato#define CCR4 0xe8 43724112Skato#define CCR4_IOMASK 0x07 43824112Skato#define CCR4_MEM 0x08 /* Enables momory bypassing */ 43924112Skato#define CCR4_DTE 0x10 /* Enables directory table entry cache */ 44024112Skato#define CCR4_FASTFPE 0x20 /* Fast FPU exception */ 44124112Skato#define CCR4_CPUID 0x80 /* Enables CPUID instruction */ 44224112Skato 44324112Skato#define CCR5 0xe9 44424112Skato#define CCR5_WT_ALLOC 0x01 /* Write-through allocate */ 44524112Skato#define CCR5_SLOP 0x02 /* LOOP instruction slowed down */ 44624112Skato#define CCR5_LBR1 0x10 /* Local bus region 1 */ 44724112Skato#define CCR5_ARREN 0x20 /* Enables ARR region */ 44824112Skato 44934031Skato#define CCR6 0xea 45034031Skato 45134031Skato#define CCR7 0xeb 45234031Skato 45324112Skato/* Performance Control Register (5x86 only). */ 45424112Skato#define PCR0 0x20 45524112Skato#define PCR0_RSTK 0x01 /* Enables return stack */ 45624112Skato#define PCR0_BTB 0x02 /* Enables branch target buffer */ 45724112Skato#define PCR0_LOOP 0x04 /* Enables loop */ 45824112Skato#define PCR0_AIS 0x08 /* Enables all instrcutions stalled to 45924112Skato serialize pipe. */ 46024112Skato#define PCR0_MLR 0x10 /* Enables reordering of misaligned loads */ 46124112Skato#define PCR0_BTBRT 0x40 /* Enables BTB test register. */ 46224112Skato#define PCR0_LSSER 0x80 /* Disable reorder */ 46324112Skato 46424112Skato/* Device Identification Registers */ 46524112Skato#define DIR0 0xfe 46624112Skato#define DIR1 0xff 46724112Skato 4682495Spst/* 469192050Sjhb * Machine Check register constants. 470192050Sjhb */ 471192050Sjhb#define MCG_CAP_COUNT 0x000000ff 472192050Sjhb#define MCG_CAP_CTL_P 0x00000100 473192050Sjhb#define MCG_CAP_EXT_P 0x00000200 474205214Sjhb#define MCG_CAP_CMCI_P 0x00000400 475192050Sjhb#define MCG_CAP_TES_P 0x00000800 476192050Sjhb#define MCG_CAP_EXT_CNT 0x00ff0000 477205214Sjhb#define MCG_CAP_SER_P 0x01000000 478192050Sjhb#define MCG_STATUS_RIPV 0x00000001 479192050Sjhb#define MCG_STATUS_EIPV 0x00000002 480192050Sjhb#define MCG_STATUS_MCIP 0x00000004 481205448Sjhb#define MCG_CTL_ENABLE 0xffffffffffffffff 482205448Sjhb#define MCG_CTL_DISABLE 0x0000000000000000 483192050Sjhb#define MSR_MC_CTL(x) (MSR_MC0_CTL + (x) * 4) 484192050Sjhb#define MSR_MC_STATUS(x) (MSR_MC0_STATUS + (x) * 4) 485192050Sjhb#define MSR_MC_ADDR(x) (MSR_MC0_ADDR + (x) * 4) 486192050Sjhb#define MSR_MC_MISC(x) (MSR_MC0_MISC + (x) * 4) 487205214Sjhb#define MSR_MC_CTL2(x) (MSR_MC0_CTL2 + (x)) /* If MCG_CAP_CMCI_P */ 488205448Sjhb#define MC_STATUS_MCA_ERROR 0x000000000000ffff 489205448Sjhb#define MC_STATUS_MODEL_ERROR 0x00000000ffff0000 490205448Sjhb#define MC_STATUS_OTHER_INFO 0x01ffffff00000000 491210577Sjhb#define MC_STATUS_COR_COUNT 0x001fffc000000000 /* If MCG_CAP_CMCI_P */ 492205448Sjhb#define MC_STATUS_TES_STATUS 0x0060000000000000 /* If MCG_CAP_TES_P */ 493210577Sjhb#define MC_STATUS_AR 0x0080000000000000 /* If MCG_CAP_TES_P */ 494210577Sjhb#define MC_STATUS_S 0x0100000000000000 /* If MCG_CAP_TES_P */ 495205448Sjhb#define MC_STATUS_PCC 0x0200000000000000 496205448Sjhb#define MC_STATUS_ADDRV 0x0400000000000000 497205448Sjhb#define MC_STATUS_MISCV 0x0800000000000000 498205448Sjhb#define MC_STATUS_EN 0x1000000000000000 499205448Sjhb#define MC_STATUS_UC 0x2000000000000000 500205448Sjhb#define MC_STATUS_OVER 0x4000000000000000 501205448Sjhb#define MC_STATUS_VAL 0x8000000000000000 502205448Sjhb#define MC_MISC_RA_LSB 0x000000000000003f /* If MCG_CAP_SER_P */ 503205448Sjhb#define MC_MISC_ADDRESS_MODE 0x00000000000001c0 /* If MCG_CAP_SER_P */ 504208507Sjhb#define MC_CTL2_THRESHOLD 0x0000000000007fff 505205448Sjhb#define MC_CTL2_CMCI_EN 0x0000000040000000 506192050Sjhb 507192050Sjhb/* 50824112Skato * The following four 3-byte registers control the non-cacheable regions. 50913765Smpp * These registers must be written as three separate bytes. 5102495Spst * 5112495Spst * NCRx+0: A31-A24 of starting address 5122495Spst * NCRx+1: A23-A16 of starting address 5132495Spst * NCRx+2: A15-A12 of starting address | NCR_SIZE_xx. 5148876Srgrimes * 5152495Spst * The non-cacheable region's starting address must be aligned to the 5162495Spst * size indicated by the NCR_SIZE_xx field. 5172495Spst */ 51824112Skato#define NCR1 0xc4 51924112Skato#define NCR2 0xc7 52024112Skato#define NCR3 0xca 52124112Skato#define NCR4 0xcd 5222495Spst 52324112Skato#define NCR_SIZE_0K 0 52424112Skato#define NCR_SIZE_4K 1 52524112Skato#define NCR_SIZE_8K 2 52624112Skato#define NCR_SIZE_16K 3 52724112Skato#define NCR_SIZE_32K 4 52824112Skato#define NCR_SIZE_64K 5 52924112Skato#define NCR_SIZE_128K 6 53024112Skato#define NCR_SIZE_256K 7 53124112Skato#define NCR_SIZE_512K 8 53224112Skato#define NCR_SIZE_1M 9 53324112Skato#define NCR_SIZE_2M 10 53424112Skato#define NCR_SIZE_4M 11 53524112Skato#define NCR_SIZE_8M 12 53624112Skato#define NCR_SIZE_16M 13 53724112Skato#define NCR_SIZE_32M 14 53824112Skato#define NCR_SIZE_4G 15 5392495Spst 54024112Skato/* 54124112Skato * The address region registers are used to specify the location and 54224112Skato * size for the eight address regions. 54324112Skato * 54424112Skato * ARRx + 0: A31-A24 of start address 54524112Skato * ARRx + 1: A23-A16 of start address 54624112Skato * ARRx + 2: A15-A12 of start address | ARR_SIZE_xx 54724112Skato */ 54824112Skato#define ARR0 0xc4 54924112Skato#define ARR1 0xc7 55024112Skato#define ARR2 0xca 55124112Skato#define ARR3 0xcd 55224112Skato#define ARR4 0xd0 55324112Skato#define ARR5 0xd3 55424112Skato#define ARR6 0xd6 55524112Skato#define ARR7 0xd9 55624112Skato 55724112Skato#define ARR_SIZE_0K 0 55824112Skato#define ARR_SIZE_4K 1 55924112Skato#define ARR_SIZE_8K 2 56024112Skato#define ARR_SIZE_16K 3 56124112Skato#define ARR_SIZE_32K 4 56224112Skato#define ARR_SIZE_64K 5 56324112Skato#define ARR_SIZE_128K 6 56424112Skato#define ARR_SIZE_256K 7 56524112Skato#define ARR_SIZE_512K 8 56624112Skato#define ARR_SIZE_1M 9 56724112Skato#define ARR_SIZE_2M 10 56824112Skato#define ARR_SIZE_4M 11 56924112Skato#define ARR_SIZE_8M 12 57024112Skato#define ARR_SIZE_16M 13 57124112Skato#define ARR_SIZE_32M 14 57224112Skato#define ARR_SIZE_4G 15 57324112Skato 57424112Skato/* 57524112Skato * The region control registers specify the attributes associated with 57624112Skato * the ARRx addres regions. 57724112Skato */ 57824112Skato#define RCR0 0xdc 57924112Skato#define RCR1 0xdd 58024112Skato#define RCR2 0xde 58124112Skato#define RCR3 0xdf 58224112Skato#define RCR4 0xe0 58324112Skato#define RCR5 0xe1 58424112Skato#define RCR6 0xe2 58524112Skato#define RCR7 0xe3 58624112Skato 587167493Sjkim#define RCR_RCD 0x01 /* Disables caching for ARRx (x = 0-6). */ 588167493Sjkim#define RCR_RCE 0x01 /* Enables caching for ARR7. */ 589167493Sjkim#define RCR_WWO 0x02 /* Weak write ordering. */ 59024112Skato#define RCR_WL 0x04 /* Weak locking. */ 591167493Sjkim#define RCR_WG 0x08 /* Write gathering. */ 59224112Skato#define RCR_WT 0x10 /* Write-through. */ 59324112Skato#define RCR_NLB 0x20 /* LBA# pin is not asserted. */ 59424112Skato 59540003Skato/* AMD Write Allocate Top-Of-Memory and Control Register */ 59640003Skato#define AMD_WT_ALLOC_TME 0x40000 /* top-of-memory enable */ 59740003Skato#define AMD_WT_ALLOC_PRE 0x20000 /* programmable range enable */ 59840003Skato#define AMD_WT_ALLOC_FRE 0x10000 /* fixed (A0000-FFFFF) range enable */ 59924112Skato 600168439Sru/* AMD64 MSR's */ 601215523Savg#define MSR_EFER 0xc0000080 /* extended features */ 602215523Savg#define MSR_HWCR 0xc0010015 603181430Sstas#define MSR_K8_UCODE_UPDATE 0xc0010020 /* update microcode */ 604205573Salc#define MSR_MC0_CTL_MASK 0xc0010044 605168439Sru 606160305Smr/* VIA ACE crypto featureset: for via_feature_rng */ 607167493Sjkim#define VIA_HAS_RNG 1 /* cpu has RNG */ 608160305Smr 609160305Smr/* VIA ACE crypto featureset: for via_feature_xcrypt */ 610167493Sjkim#define VIA_HAS_AES 1 /* cpu has AES */ 611167493Sjkim#define VIA_HAS_SHA 2 /* cpu has SHA1 & SHA256 */ 612167493Sjkim#define VIA_HAS_MM 4 /* cpu has RSA instructions */ 613167493Sjkim#define VIA_HAS_AESCTR 8 /* cpu has AES-CTR instructions */ 61440003Skato 615160298Smr/* Centaur Extended Feature flags */ 616167493Sjkim#define VIA_CPUID_HAS_RNG 0x000004 617167493Sjkim#define VIA_CPUID_DO_RNG 0x000008 618167493Sjkim#define VIA_CPUID_HAS_ACE 0x000040 619167493Sjkim#define VIA_CPUID_DO_ACE 0x000080 620167493Sjkim#define VIA_CPUID_HAS_ACE2 0x000100 621167493Sjkim#define VIA_CPUID_DO_ACE2 0x000200 622167493Sjkim#define VIA_CPUID_HAS_PHE 0x000400 623167493Sjkim#define VIA_CPUID_DO_PHE 0x000800 624167493Sjkim#define VIA_CPUID_HAS_PMM 0x001000 625167493Sjkim#define VIA_CPUID_DO_PMM 0x002000 626160298Smr 627160298Smr/* VIA ACE xcrypt-* instruction context control options */ 628167493Sjkim#define VIA_CRYPT_CWLO_ROUND_M 0x0000000f 629167493Sjkim#define VIA_CRYPT_CWLO_ALG_M 0x00000070 630167493Sjkim#define VIA_CRYPT_CWLO_ALG_AES 0x00000000 631167493Sjkim#define VIA_CRYPT_CWLO_KEYGEN_M 0x00000080 632167493Sjkim#define VIA_CRYPT_CWLO_KEYGEN_HW 0x00000000 633167493Sjkim#define VIA_CRYPT_CWLO_KEYGEN_SW 0x00000080 634167493Sjkim#define VIA_CRYPT_CWLO_NORMAL 0x00000000 635167493Sjkim#define VIA_CRYPT_CWLO_INTERMEDIATE 0x00000100 636167493Sjkim#define VIA_CRYPT_CWLO_ENCRYPT 0x00000000 637167493Sjkim#define VIA_CRYPT_CWLO_DECRYPT 0x00000200 638167493Sjkim#define VIA_CRYPT_CWLO_KEY128 0x0000000a /* 128bit, 10 rds */ 639167493Sjkim#define VIA_CRYPT_CWLO_KEY192 0x0000040c /* 192bit, 12 rds */ 640167493Sjkim#define VIA_CRYPT_CWLO_KEY256 0x0000080e /* 256bit, 15 rds */ 641160298Smr 6425594Sbde#endif /* !_MACHINE_SPECIALREG_H_ */ 643