pmap.c revision 209887
1/*- 2 * Copyright (c) 1991 Regents of the University of California. 3 * All rights reserved. 4 * Copyright (c) 1994 John S. Dyson 5 * All rights reserved. 6 * Copyright (c) 1994 David Greenman 7 * All rights reserved. 8 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu> 9 * All rights reserved. 10 * 11 * This code is derived from software contributed to Berkeley by 12 * the Systems Programming Group of the University of Utah Computer 13 * Science Department and William Jolitz of UUNET Technologies Inc. 14 * 15 * Redistribution and use in source and binary forms, with or without 16 * modification, are permitted provided that the following conditions 17 * are met: 18 * 1. Redistributions of source code must retain the above copyright 19 * notice, this list of conditions and the following disclaimer. 20 * 2. Redistributions in binary form must reproduce the above copyright 21 * notice, this list of conditions and the following disclaimer in the 22 * documentation and/or other materials provided with the distribution. 23 * 3. All advertising materials mentioning features or use of this software 24 * must display the following acknowledgement: 25 * This product includes software developed by the University of 26 * California, Berkeley and its contributors. 27 * 4. Neither the name of the University nor the names of its contributors 28 * may be used to endorse or promote products derived from this software 29 * without specific prior written permission. 30 * 31 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 32 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 33 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 34 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 35 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 36 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 37 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 38 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 39 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 40 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 41 * SUCH DAMAGE. 42 * 43 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91 44 */ 45/*- 46 * Copyright (c) 2003 Networks Associates Technology, Inc. 47 * All rights reserved. 48 * 49 * This software was developed for the FreeBSD Project by Jake Burkholder, 50 * Safeport Network Services, and Network Associates Laboratories, the 51 * Security Research Division of Network Associates, Inc. under 52 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA 53 * CHATS research program. 54 * 55 * Redistribution and use in source and binary forms, with or without 56 * modification, are permitted provided that the following conditions 57 * are met: 58 * 1. Redistributions of source code must retain the above copyright 59 * notice, this list of conditions and the following disclaimer. 60 * 2. Redistributions in binary form must reproduce the above copyright 61 * notice, this list of conditions and the following disclaimer in the 62 * documentation and/or other materials provided with the distribution. 63 * 64 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 65 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 66 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 67 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 68 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 69 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 70 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 71 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 72 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 73 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 74 * SUCH DAMAGE. 75 */ 76 77#include <sys/cdefs.h> 78__FBSDID("$FreeBSD: head/sys/i386/i386/pmap.c 209887 2010-07-10 18:22:44Z alc $"); 79 80/* 81 * Manages physical address maps. 82 * 83 * In addition to hardware address maps, this 84 * module is called upon to provide software-use-only 85 * maps which may or may not be stored in the same 86 * form as hardware maps. These pseudo-maps are 87 * used to store intermediate results from copy 88 * operations to and from address spaces. 89 * 90 * Since the information managed by this module is 91 * also stored by the logical address mapping module, 92 * this module may throw away valid virtual-to-physical 93 * mappings at almost any time. However, invalidations 94 * of virtual-to-physical mappings must be done as 95 * requested. 96 * 97 * In order to cope with hardware architectures which 98 * make virtual-to-physical map invalidates expensive, 99 * this module may delay invalidate or reduced protection 100 * operations until such time as they are actually 101 * necessary. This module is given full information as 102 * to which processors are currently using which maps, 103 * and to when physical maps must be made correct. 104 */ 105 106#include "opt_cpu.h" 107#include "opt_pmap.h" 108#include "opt_msgbuf.h" 109#include "opt_smp.h" 110#include "opt_xbox.h" 111 112#include <sys/param.h> 113#include <sys/systm.h> 114#include <sys/kernel.h> 115#include <sys/ktr.h> 116#include <sys/lock.h> 117#include <sys/malloc.h> 118#include <sys/mman.h> 119#include <sys/msgbuf.h> 120#include <sys/mutex.h> 121#include <sys/proc.h> 122#include <sys/sf_buf.h> 123#include <sys/sx.h> 124#include <sys/vmmeter.h> 125#include <sys/sched.h> 126#include <sys/sysctl.h> 127#ifdef SMP 128#include <sys/smp.h> 129#endif 130 131#include <vm/vm.h> 132#include <vm/vm_param.h> 133#include <vm/vm_kern.h> 134#include <vm/vm_page.h> 135#include <vm/vm_map.h> 136#include <vm/vm_object.h> 137#include <vm/vm_extern.h> 138#include <vm/vm_pageout.h> 139#include <vm/vm_pager.h> 140#include <vm/vm_reserv.h> 141#include <vm/uma.h> 142 143#include <machine/cpu.h> 144#include <machine/cputypes.h> 145#include <machine/md_var.h> 146#include <machine/pcb.h> 147#include <machine/specialreg.h> 148#ifdef SMP 149#include <machine/smp.h> 150#endif 151 152#ifdef XBOX 153#include <machine/xbox.h> 154#endif 155 156#if !defined(CPU_DISABLE_SSE) && defined(I686_CPU) 157#define CPU_ENABLE_SSE 158#endif 159 160#ifndef PMAP_SHPGPERPROC 161#define PMAP_SHPGPERPROC 200 162#endif 163 164#if !defined(DIAGNOSTIC) 165#ifdef __GNUC_GNU_INLINE__ 166#define PMAP_INLINE __attribute__((__gnu_inline__)) inline 167#else 168#define PMAP_INLINE extern inline 169#endif 170#else 171#define PMAP_INLINE 172#endif 173 174#define PV_STATS 175#ifdef PV_STATS 176#define PV_STAT(x) do { x ; } while (0) 177#else 178#define PV_STAT(x) do { } while (0) 179#endif 180 181#define pa_index(pa) ((pa) >> PDRSHIFT) 182#define pa_to_pvh(pa) (&pv_table[pa_index(pa)]) 183 184/* 185 * Get PDEs and PTEs for user/kernel address space 186 */ 187#define pmap_pde(m, v) (&((m)->pm_pdir[(vm_offset_t)(v) >> PDRSHIFT])) 188#define pdir_pde(m, v) (m[(vm_offset_t)(v) >> PDRSHIFT]) 189 190#define pmap_pde_v(pte) ((*(int *)pte & PG_V) != 0) 191#define pmap_pte_w(pte) ((*(int *)pte & PG_W) != 0) 192#define pmap_pte_m(pte) ((*(int *)pte & PG_M) != 0) 193#define pmap_pte_u(pte) ((*(int *)pte & PG_A) != 0) 194#define pmap_pte_v(pte) ((*(int *)pte & PG_V) != 0) 195 196#define pmap_pte_set_w(pte, v) ((v) ? atomic_set_int((u_int *)(pte), PG_W) : \ 197 atomic_clear_int((u_int *)(pte), PG_W)) 198#define pmap_pte_set_prot(pte, v) ((*(int *)pte &= ~PG_PROT), (*(int *)pte |= (v))) 199 200struct pmap kernel_pmap_store; 201LIST_HEAD(pmaplist, pmap); 202static struct pmaplist allpmaps; 203static struct mtx allpmaps_lock; 204 205vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */ 206vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */ 207int pgeflag = 0; /* PG_G or-in */ 208int pseflag = 0; /* PG_PS or-in */ 209 210static int nkpt = NKPT; 211vm_offset_t kernel_vm_end = KERNBASE + NKPT * NBPDR; 212extern u_int32_t KERNend; 213extern u_int32_t KPTphys; 214 215#ifdef PAE 216pt_entry_t pg_nx; 217static uma_zone_t pdptzone; 218#endif 219 220static int pat_works = 0; /* Is page attribute table sane? */ 221 222SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD, 0, "VM/pmap parameters"); 223 224static int pg_ps_enabled = 1; 225SYSCTL_INT(_vm_pmap, OID_AUTO, pg_ps_enabled, CTLFLAG_RDTUN, &pg_ps_enabled, 0, 226 "Are large page mappings enabled?"); 227 228/* 229 * Data for the pv entry allocation mechanism 230 */ 231static int pv_entry_count = 0, pv_entry_max = 0, pv_entry_high_water = 0; 232static struct md_page *pv_table; 233static int shpgperproc = PMAP_SHPGPERPROC; 234 235struct pv_chunk *pv_chunkbase; /* KVA block for pv_chunks */ 236int pv_maxchunks; /* How many chunks we have KVA for */ 237vm_offset_t pv_vafree; /* freelist stored in the PTE */ 238 239/* 240 * All those kernel PT submaps that BSD is so fond of 241 */ 242struct sysmaps { 243 struct mtx lock; 244 pt_entry_t *CMAP1; 245 pt_entry_t *CMAP2; 246 caddr_t CADDR1; 247 caddr_t CADDR2; 248}; 249static struct sysmaps sysmaps_pcpu[MAXCPU]; 250pt_entry_t *CMAP1 = 0, *KPTmap; 251static pt_entry_t *CMAP3; 252static pd_entry_t *KPTD; 253caddr_t CADDR1 = 0, ptvmmap = 0; 254static caddr_t CADDR3; 255struct msgbuf *msgbufp = 0; 256 257/* 258 * Crashdump maps. 259 */ 260static caddr_t crashdumpmap; 261 262static pt_entry_t *PMAP1 = 0, *PMAP2; 263static pt_entry_t *PADDR1 = 0, *PADDR2; 264#ifdef SMP 265static int PMAP1cpu; 266static int PMAP1changedcpu; 267SYSCTL_INT(_debug, OID_AUTO, PMAP1changedcpu, CTLFLAG_RD, 268 &PMAP1changedcpu, 0, 269 "Number of times pmap_pte_quick changed CPU with same PMAP1"); 270#endif 271static int PMAP1changed; 272SYSCTL_INT(_debug, OID_AUTO, PMAP1changed, CTLFLAG_RD, 273 &PMAP1changed, 0, 274 "Number of times pmap_pte_quick changed PMAP1"); 275static int PMAP1unchanged; 276SYSCTL_INT(_debug, OID_AUTO, PMAP1unchanged, CTLFLAG_RD, 277 &PMAP1unchanged, 0, 278 "Number of times pmap_pte_quick didn't change PMAP1"); 279static struct mtx PMAP2mutex; 280 281static void free_pv_entry(pmap_t pmap, pv_entry_t pv); 282static pv_entry_t get_pv_entry(pmap_t locked_pmap, int try); 283static void pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa); 284static boolean_t pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa); 285static void pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa); 286static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va); 287static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, 288 vm_offset_t va); 289static int pmap_pvh_wired_mappings(struct md_page *pvh, int count); 290 291static boolean_t pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va); 292static boolean_t pmap_enter_pde(pmap_t pmap, vm_offset_t va, vm_page_t m, 293 vm_prot_t prot); 294static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, 295 vm_page_t m, vm_prot_t prot, vm_page_t mpte); 296static void pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte); 297static void pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte); 298static boolean_t pmap_is_modified_pvh(struct md_page *pvh); 299static boolean_t pmap_is_referenced_pvh(struct md_page *pvh); 300static void pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode); 301static void pmap_kenter_pde(vm_offset_t va, pd_entry_t newpde); 302static vm_page_t pmap_lookup_pt_page(pmap_t pmap, vm_offset_t va); 303static void pmap_pde_attr(pd_entry_t *pde, int cache_bits); 304static void pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va); 305static boolean_t pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva, 306 vm_prot_t prot); 307static void pmap_pte_attr(pt_entry_t *pte, int cache_bits); 308static void pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva, 309 vm_page_t *free); 310static int pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t sva, 311 vm_page_t *free); 312static void pmap_remove_pt_page(pmap_t pmap, vm_page_t mpte); 313static void pmap_remove_page(struct pmap *pmap, vm_offset_t va, 314 vm_page_t *free); 315static void pmap_remove_entry(struct pmap *pmap, vm_page_t m, 316 vm_offset_t va); 317static void pmap_insert_entry(pmap_t pmap, vm_offset_t va, vm_page_t m); 318static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, 319 vm_page_t m); 320static void pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, 321 pd_entry_t newpde); 322static void pmap_update_pde_invalidate(vm_offset_t va, pd_entry_t newpde); 323 324static vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va, int flags); 325 326static vm_page_t _pmap_allocpte(pmap_t pmap, unsigned ptepindex, int flags); 327static int _pmap_unwire_pte_hold(pmap_t pmap, vm_page_t m, vm_page_t *free); 328static pt_entry_t *pmap_pte_quick(pmap_t pmap, vm_offset_t va); 329static void pmap_pte_release(pt_entry_t *pte); 330static int pmap_unuse_pt(pmap_t, vm_offset_t, vm_page_t *); 331#ifdef PAE 332static void *pmap_pdpt_allocf(uma_zone_t zone, int bytes, u_int8_t *flags, int wait); 333#endif 334static void pmap_set_pg(void); 335 336CTASSERT(1 << PDESHIFT == sizeof(pd_entry_t)); 337CTASSERT(1 << PTESHIFT == sizeof(pt_entry_t)); 338 339/* 340 * If you get an error here, then you set KVA_PAGES wrong! See the 341 * description of KVA_PAGES in sys/i386/include/pmap.h. It must be 342 * multiple of 4 for a normal kernel, or a multiple of 8 for a PAE. 343 */ 344CTASSERT(KERNBASE % (1 << 24) == 0); 345 346/* 347 * Bootstrap the system enough to run with virtual memory. 348 * 349 * On the i386 this is called after mapping has already been enabled 350 * and just syncs the pmap module with what has already been done. 351 * [We can't call it easily with mapping off since the kernel is not 352 * mapped with PA == VA, hence we would have to relocate every address 353 * from the linked base (virtual) address "KERNBASE" to the actual 354 * (physical) address starting relative to 0] 355 */ 356void 357pmap_bootstrap(vm_paddr_t firstaddr) 358{ 359 vm_offset_t va; 360 pt_entry_t *pte, *unused; 361 struct sysmaps *sysmaps; 362 int i; 363 364 /* 365 * XXX The calculation of virtual_avail is wrong. It's NKPT*PAGE_SIZE too 366 * large. It should instead be correctly calculated in locore.s and 367 * not based on 'first' (which is a physical address, not a virtual 368 * address, for the start of unused physical memory). The kernel 369 * page tables are NOT double mapped and thus should not be included 370 * in this calculation. 371 */ 372 virtual_avail = (vm_offset_t) KERNBASE + firstaddr; 373 374 virtual_end = VM_MAX_KERNEL_ADDRESS; 375 376 /* 377 * Initialize the kernel pmap (which is statically allocated). 378 */ 379 PMAP_LOCK_INIT(kernel_pmap); 380 kernel_pmap->pm_pdir = (pd_entry_t *) (KERNBASE + (u_int)IdlePTD); 381#ifdef PAE 382 kernel_pmap->pm_pdpt = (pdpt_entry_t *) (KERNBASE + (u_int)IdlePDPT); 383#endif 384 kernel_pmap->pm_root = NULL; 385 kernel_pmap->pm_active = -1; /* don't allow deactivation */ 386 TAILQ_INIT(&kernel_pmap->pm_pvchunk); 387 LIST_INIT(&allpmaps); 388 389 /* 390 * Request a spin mutex so that changes to allpmaps cannot be 391 * preempted by smp_rendezvous_cpus(). Otherwise, 392 * pmap_update_pde_kernel() could access allpmaps while it is 393 * being changed. 394 */ 395 mtx_init(&allpmaps_lock, "allpmaps", NULL, MTX_SPIN); 396 mtx_lock_spin(&allpmaps_lock); 397 LIST_INSERT_HEAD(&allpmaps, kernel_pmap, pm_list); 398 mtx_unlock_spin(&allpmaps_lock); 399 400 /* 401 * Reserve some special page table entries/VA space for temporary 402 * mapping of pages. 403 */ 404#define SYSMAP(c, p, v, n) \ 405 v = (c)va; va += ((n)*PAGE_SIZE); p = pte; pte += (n); 406 407 va = virtual_avail; 408 pte = vtopte(va); 409 410 /* 411 * CMAP1/CMAP2 are used for zeroing and copying pages. 412 * CMAP3 is used for the idle process page zeroing. 413 */ 414 for (i = 0; i < MAXCPU; i++) { 415 sysmaps = &sysmaps_pcpu[i]; 416 mtx_init(&sysmaps->lock, "SYSMAPS", NULL, MTX_DEF); 417 SYSMAP(caddr_t, sysmaps->CMAP1, sysmaps->CADDR1, 1) 418 SYSMAP(caddr_t, sysmaps->CMAP2, sysmaps->CADDR2, 1) 419 } 420 SYSMAP(caddr_t, CMAP1, CADDR1, 1) 421 SYSMAP(caddr_t, CMAP3, CADDR3, 1) 422 423 /* 424 * Crashdump maps. 425 */ 426 SYSMAP(caddr_t, unused, crashdumpmap, MAXDUMPPGS) 427 428 /* 429 * ptvmmap is used for reading arbitrary physical pages via /dev/mem. 430 */ 431 SYSMAP(caddr_t, unused, ptvmmap, 1) 432 433 /* 434 * msgbufp is used to map the system message buffer. 435 */ 436 SYSMAP(struct msgbuf *, unused, msgbufp, atop(round_page(MSGBUF_SIZE))) 437 438 /* 439 * KPTmap is used by pmap_kextract(). 440 */ 441 SYSMAP(pt_entry_t *, KPTD, KPTmap, KVA_PAGES) 442 443 for (i = 0; i < NKPT; i++) 444 KPTD[i] = (KPTphys + (i << PAGE_SHIFT)) | pgeflag | PG_RW | PG_V; 445 446 /* 447 * Adjust the start of the KPTD and KPTmap so that the implementation 448 * of pmap_kextract() and pmap_growkernel() can be made simpler. 449 */ 450 KPTD -= KPTDI; 451 KPTmap -= i386_btop(KPTDI << PDRSHIFT); 452 453 /* 454 * ptemap is used for pmap_pte_quick 455 */ 456 SYSMAP(pt_entry_t *, PMAP1, PADDR1, 1) 457 SYSMAP(pt_entry_t *, PMAP2, PADDR2, 1) 458 459 mtx_init(&PMAP2mutex, "PMAP2", NULL, MTX_DEF); 460 461 virtual_avail = va; 462 463 /* 464 * Leave in place an identity mapping (virt == phys) for the low 1 MB 465 * physical memory region that is used by the ACPI wakeup code. This 466 * mapping must not have PG_G set. 467 */ 468#ifdef XBOX 469 /* FIXME: This is gross, but needed for the XBOX. Since we are in such 470 * an early stadium, we cannot yet neatly map video memory ... :-( 471 * Better fixes are very welcome! */ 472 if (!arch_i386_is_xbox) 473#endif 474 for (i = 1; i < NKPT; i++) 475 PTD[i] = 0; 476 477 /* Initialize the PAT MSR if present. */ 478 pmap_init_pat(); 479 480 /* Turn on PG_G on kernel page(s) */ 481 pmap_set_pg(); 482} 483 484/* 485 * Setup the PAT MSR. 486 */ 487void 488pmap_init_pat(void) 489{ 490 uint64_t pat_msr; 491 char *sysenv; 492 static int pat_tested = 0; 493 494 /* Bail if this CPU doesn't implement PAT. */ 495 if (!(cpu_feature & CPUID_PAT)) 496 return; 497 498 /* 499 * Due to some Intel errata, we can only safely use the lower 4 500 * PAT entries. 501 * 502 * Intel Pentium III Processor Specification Update 503 * Errata E.27 (Upper Four PAT Entries Not Usable With Mode B 504 * or Mode C Paging) 505 * 506 * Intel Pentium IV Processor Specification Update 507 * Errata N46 (PAT Index MSB May Be Calculated Incorrectly) 508 * 509 * Some Apple Macs based on nVidia chipsets cannot enter ACPI mode 510 * via SMI# when we use upper 4 PAT entries for unknown reason. 511 */ 512 if (!pat_tested) { 513 if (cpu_vendor_id != CPU_VENDOR_INTEL || 514 (CPUID_TO_FAMILY(cpu_id) == 6 && 515 CPUID_TO_MODEL(cpu_id) >= 0xe)) { 516 pat_works = 1; 517 sysenv = getenv("smbios.system.product"); 518 if (sysenv != NULL) { 519 if (strncmp(sysenv, "MacBook5,1", 10) == 0 || 520 strncmp(sysenv, "MacBookPro5,5", 13) == 0 || 521 strncmp(sysenv, "Macmini3,1", 10) == 0) 522 pat_works = 0; 523 freeenv(sysenv); 524 } 525 } 526 pat_tested = 1; 527 } 528 529 /* Initialize default PAT entries. */ 530 pat_msr = PAT_VALUE(0, PAT_WRITE_BACK) | 531 PAT_VALUE(1, PAT_WRITE_THROUGH) | 532 PAT_VALUE(2, PAT_UNCACHED) | 533 PAT_VALUE(3, PAT_UNCACHEABLE) | 534 PAT_VALUE(4, PAT_WRITE_BACK) | 535 PAT_VALUE(5, PAT_WRITE_THROUGH) | 536 PAT_VALUE(6, PAT_UNCACHED) | 537 PAT_VALUE(7, PAT_UNCACHEABLE); 538 539 if (pat_works) { 540 /* 541 * Leave the indices 0-3 at the default of WB, WT, UC-, and UC. 542 * Program 4 and 5 as WP and WC. 543 * Leave 6 and 7 as UC- and UC. 544 */ 545 pat_msr &= ~(PAT_MASK(4) | PAT_MASK(5)); 546 pat_msr |= PAT_VALUE(4, PAT_WRITE_PROTECTED) | 547 PAT_VALUE(5, PAT_WRITE_COMBINING); 548 } else { 549 /* 550 * Just replace PAT Index 2 with WC instead of UC-. 551 */ 552 pat_msr &= ~PAT_MASK(2); 553 pat_msr |= PAT_VALUE(2, PAT_WRITE_COMBINING); 554 } 555 wrmsr(MSR_PAT, pat_msr); 556} 557 558/* 559 * Set PG_G on kernel pages. Only the BSP calls this when SMP is turned on. 560 */ 561static void 562pmap_set_pg(void) 563{ 564 pt_entry_t *pte; 565 vm_offset_t va, endva; 566 567 if (pgeflag == 0) 568 return; 569 570 endva = KERNBASE + KERNend; 571 572 if (pseflag) { 573 va = KERNBASE + KERNLOAD; 574 while (va < endva) { 575 pdir_pde(PTD, va) |= pgeflag; 576 invltlb(); /* Play it safe, invltlb() every time */ 577 va += NBPDR; 578 } 579 } else { 580 va = (vm_offset_t)btext; 581 while (va < endva) { 582 pte = vtopte(va); 583 if (*pte) 584 *pte |= pgeflag; 585 invltlb(); /* Play it safe, invltlb() every time */ 586 va += PAGE_SIZE; 587 } 588 } 589} 590 591/* 592 * Initialize a vm_page's machine-dependent fields. 593 */ 594void 595pmap_page_init(vm_page_t m) 596{ 597 598 TAILQ_INIT(&m->md.pv_list); 599 m->md.pat_mode = PAT_WRITE_BACK; 600} 601 602#ifdef PAE 603static void * 604pmap_pdpt_allocf(uma_zone_t zone, int bytes, u_int8_t *flags, int wait) 605{ 606 607 /* Inform UMA that this allocator uses kernel_map/object. */ 608 *flags = UMA_SLAB_KERNEL; 609 return ((void *)kmem_alloc_contig(kernel_map, bytes, wait, 0x0ULL, 610 0xffffffffULL, 1, 0, VM_MEMATTR_DEFAULT)); 611} 612#endif 613 614/* 615 * ABuse the pte nodes for unmapped kva to thread a kva freelist through. 616 * Requirements: 617 * - Must deal with pages in order to ensure that none of the PG_* bits 618 * are ever set, PG_V in particular. 619 * - Assumes we can write to ptes without pte_store() atomic ops, even 620 * on PAE systems. This should be ok. 621 * - Assumes nothing will ever test these addresses for 0 to indicate 622 * no mapping instead of correctly checking PG_V. 623 * - Assumes a vm_offset_t will fit in a pte (true for i386). 624 * Because PG_V is never set, there can be no mappings to invalidate. 625 */ 626static vm_offset_t 627pmap_ptelist_alloc(vm_offset_t *head) 628{ 629 pt_entry_t *pte; 630 vm_offset_t va; 631 632 va = *head; 633 if (va == 0) 634 return (va); /* Out of memory */ 635 pte = vtopte(va); 636 *head = *pte; 637 if (*head & PG_V) 638 panic("pmap_ptelist_alloc: va with PG_V set!"); 639 *pte = 0; 640 return (va); 641} 642 643static void 644pmap_ptelist_free(vm_offset_t *head, vm_offset_t va) 645{ 646 pt_entry_t *pte; 647 648 if (va & PG_V) 649 panic("pmap_ptelist_free: freeing va with PG_V set!"); 650 pte = vtopte(va); 651 *pte = *head; /* virtual! PG_V is 0 though */ 652 *head = va; 653} 654 655static void 656pmap_ptelist_init(vm_offset_t *head, void *base, int npages) 657{ 658 int i; 659 vm_offset_t va; 660 661 *head = 0; 662 for (i = npages - 1; i >= 0; i--) { 663 va = (vm_offset_t)base + i * PAGE_SIZE; 664 pmap_ptelist_free(head, va); 665 } 666} 667 668 669/* 670 * Initialize the pmap module. 671 * Called by vm_init, to initialize any structures that the pmap 672 * system needs to map virtual memory. 673 */ 674void 675pmap_init(void) 676{ 677 vm_page_t mpte; 678 vm_size_t s; 679 int i, pv_npg; 680 681 /* 682 * Initialize the vm page array entries for the kernel pmap's 683 * page table pages. 684 */ 685 for (i = 0; i < NKPT; i++) { 686 mpte = PHYS_TO_VM_PAGE(KPTphys + (i << PAGE_SHIFT)); 687 KASSERT(mpte >= vm_page_array && 688 mpte < &vm_page_array[vm_page_array_size], 689 ("pmap_init: page table page is out of range")); 690 mpte->pindex = i + KPTDI; 691 mpte->phys_addr = KPTphys + (i << PAGE_SHIFT); 692 } 693 694 /* 695 * Initialize the address space (zone) for the pv entries. Set a 696 * high water mark so that the system can recover from excessive 697 * numbers of pv entries. 698 */ 699 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc); 700 pv_entry_max = shpgperproc * maxproc + cnt.v_page_count; 701 TUNABLE_INT_FETCH("vm.pmap.pv_entries", &pv_entry_max); 702 pv_entry_max = roundup(pv_entry_max, _NPCPV); 703 pv_entry_high_water = 9 * (pv_entry_max / 10); 704 705 /* 706 * If the kernel is running in a virtual machine on an AMD Family 10h 707 * processor, then it must assume that MCA is enabled by the virtual 708 * machine monitor. 709 */ 710 if (vm_guest == VM_GUEST_VM && cpu_vendor_id == CPU_VENDOR_AMD && 711 CPUID_TO_FAMILY(cpu_id) == 0x10) 712 workaround_erratum383 = 1; 713 714 /* 715 * Are large page mappings supported and enabled? 716 */ 717 TUNABLE_INT_FETCH("vm.pmap.pg_ps_enabled", &pg_ps_enabled); 718 if (pseflag == 0) 719 pg_ps_enabled = 0; 720 else if (pg_ps_enabled) { 721 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0, 722 ("pmap_init: can't assign to pagesizes[1]")); 723 pagesizes[1] = NBPDR; 724 } 725 726 /* 727 * Calculate the size of the pv head table for superpages. 728 */ 729 for (i = 0; phys_avail[i + 1]; i += 2); 730 pv_npg = round_4mpage(phys_avail[(i - 2) + 1]) / NBPDR; 731 732 /* 733 * Allocate memory for the pv head table for superpages. 734 */ 735 s = (vm_size_t)(pv_npg * sizeof(struct md_page)); 736 s = round_page(s); 737 pv_table = (struct md_page *)kmem_alloc(kernel_map, s); 738 for (i = 0; i < pv_npg; i++) 739 TAILQ_INIT(&pv_table[i].pv_list); 740 741 pv_maxchunks = MAX(pv_entry_max / _NPCPV, maxproc); 742 pv_chunkbase = (struct pv_chunk *)kmem_alloc_nofault(kernel_map, 743 PAGE_SIZE * pv_maxchunks); 744 if (pv_chunkbase == NULL) 745 panic("pmap_init: not enough kvm for pv chunks"); 746 pmap_ptelist_init(&pv_vafree, pv_chunkbase, pv_maxchunks); 747#ifdef PAE 748 pdptzone = uma_zcreate("PDPT", NPGPTD * sizeof(pdpt_entry_t), NULL, 749 NULL, NULL, NULL, (NPGPTD * sizeof(pdpt_entry_t)) - 1, 750 UMA_ZONE_VM | UMA_ZONE_NOFREE); 751 uma_zone_set_allocf(pdptzone, pmap_pdpt_allocf); 752#endif 753} 754 755 756SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_max, CTLFLAG_RD, &pv_entry_max, 0, 757 "Max number of PV entries"); 758SYSCTL_INT(_vm_pmap, OID_AUTO, shpgperproc, CTLFLAG_RD, &shpgperproc, 0, 759 "Page share factor per proc"); 760 761SYSCTL_NODE(_vm_pmap, OID_AUTO, pde, CTLFLAG_RD, 0, 762 "2/4MB page mapping counters"); 763 764static u_long pmap_pde_demotions; 765SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, demotions, CTLFLAG_RD, 766 &pmap_pde_demotions, 0, "2/4MB page demotions"); 767 768static u_long pmap_pde_mappings; 769SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, mappings, CTLFLAG_RD, 770 &pmap_pde_mappings, 0, "2/4MB page mappings"); 771 772static u_long pmap_pde_p_failures; 773SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, p_failures, CTLFLAG_RD, 774 &pmap_pde_p_failures, 0, "2/4MB page promotion failures"); 775 776static u_long pmap_pde_promotions; 777SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, promotions, CTLFLAG_RD, 778 &pmap_pde_promotions, 0, "2/4MB page promotions"); 779 780/*************************************************** 781 * Low level helper routines..... 782 ***************************************************/ 783 784/* 785 * Determine the appropriate bits to set in a PTE or PDE for a specified 786 * caching mode. 787 */ 788int 789pmap_cache_bits(int mode, boolean_t is_pde) 790{ 791 int pat_flag, pat_index, cache_bits; 792 793 /* The PAT bit is different for PTE's and PDE's. */ 794 pat_flag = is_pde ? PG_PDE_PAT : PG_PTE_PAT; 795 796 /* If we don't support PAT, map extended modes to older ones. */ 797 if (!(cpu_feature & CPUID_PAT)) { 798 switch (mode) { 799 case PAT_UNCACHEABLE: 800 case PAT_WRITE_THROUGH: 801 case PAT_WRITE_BACK: 802 break; 803 case PAT_UNCACHED: 804 case PAT_WRITE_COMBINING: 805 case PAT_WRITE_PROTECTED: 806 mode = PAT_UNCACHEABLE; 807 break; 808 } 809 } 810 811 /* Map the caching mode to a PAT index. */ 812 if (pat_works) { 813 switch (mode) { 814 case PAT_UNCACHEABLE: 815 pat_index = 3; 816 break; 817 case PAT_WRITE_THROUGH: 818 pat_index = 1; 819 break; 820 case PAT_WRITE_BACK: 821 pat_index = 0; 822 break; 823 case PAT_UNCACHED: 824 pat_index = 2; 825 break; 826 case PAT_WRITE_COMBINING: 827 pat_index = 5; 828 break; 829 case PAT_WRITE_PROTECTED: 830 pat_index = 4; 831 break; 832 default: 833 panic("Unknown caching mode %d\n", mode); 834 } 835 } else { 836 switch (mode) { 837 case PAT_UNCACHED: 838 case PAT_UNCACHEABLE: 839 case PAT_WRITE_PROTECTED: 840 pat_index = 3; 841 break; 842 case PAT_WRITE_THROUGH: 843 pat_index = 1; 844 break; 845 case PAT_WRITE_BACK: 846 pat_index = 0; 847 break; 848 case PAT_WRITE_COMBINING: 849 pat_index = 2; 850 break; 851 default: 852 panic("Unknown caching mode %d\n", mode); 853 } 854 } 855 856 /* Map the 3-bit index value into the PAT, PCD, and PWT bits. */ 857 cache_bits = 0; 858 if (pat_index & 0x4) 859 cache_bits |= pat_flag; 860 if (pat_index & 0x2) 861 cache_bits |= PG_NC_PCD; 862 if (pat_index & 0x1) 863 cache_bits |= PG_NC_PWT; 864 return (cache_bits); 865} 866 867/* 868 * The caller is responsible for maintaining TLB consistency. 869 */ 870static void 871pmap_kenter_pde(vm_offset_t va, pd_entry_t newpde) 872{ 873 pd_entry_t *pde; 874 pmap_t pmap; 875 boolean_t PTD_updated; 876 877 PTD_updated = FALSE; 878 mtx_lock_spin(&allpmaps_lock); 879 LIST_FOREACH(pmap, &allpmaps, pm_list) { 880 if ((pmap->pm_pdir[PTDPTDI] & PG_FRAME) == (PTDpde[0] & 881 PG_FRAME)) 882 PTD_updated = TRUE; 883 pde = pmap_pde(pmap, va); 884 pde_store(pde, newpde); 885 } 886 mtx_unlock_spin(&allpmaps_lock); 887 KASSERT(PTD_updated, 888 ("pmap_kenter_pde: current page table is not in allpmaps")); 889} 890 891/* 892 * After changing the page size for the specified virtual address in the page 893 * table, flush the corresponding entries from the processor's TLB. Only the 894 * calling processor's TLB is affected. 895 * 896 * The calling thread must be pinned to a processor. 897 */ 898static void 899pmap_update_pde_invalidate(vm_offset_t va, pd_entry_t newpde) 900{ 901 u_long cr4; 902 903 if ((newpde & PG_PS) == 0) 904 /* Demotion: flush a specific 2MB page mapping. */ 905 invlpg(va); 906 else if ((newpde & PG_G) == 0) 907 /* 908 * Promotion: flush every 4KB page mapping from the TLB 909 * because there are too many to flush individually. 910 */ 911 invltlb(); 912 else { 913 /* 914 * Promotion: flush every 4KB page mapping from the TLB, 915 * including any global (PG_G) mappings. 916 */ 917 cr4 = rcr4(); 918 load_cr4(cr4 & ~CR4_PGE); 919 /* 920 * Although preemption at this point could be detrimental to 921 * performance, it would not lead to an error. PG_G is simply 922 * ignored if CR4.PGE is clear. Moreover, in case this block 923 * is re-entered, the load_cr4() either above or below will 924 * modify CR4.PGE flushing the TLB. 925 */ 926 load_cr4(cr4 | CR4_PGE); 927 } 928} 929#ifdef SMP 930/* 931 * For SMP, these functions have to use the IPI mechanism for coherence. 932 * 933 * N.B.: Before calling any of the following TLB invalidation functions, 934 * the calling processor must ensure that all stores updating a non- 935 * kernel page table are globally performed. Otherwise, another 936 * processor could cache an old, pre-update entry without being 937 * invalidated. This can happen one of two ways: (1) The pmap becomes 938 * active on another processor after its pm_active field is checked by 939 * one of the following functions but before a store updating the page 940 * table is globally performed. (2) The pmap becomes active on another 941 * processor before its pm_active field is checked but due to 942 * speculative loads one of the following functions stills reads the 943 * pmap as inactive on the other processor. 944 * 945 * The kernel page table is exempt because its pm_active field is 946 * immutable. The kernel page table is always active on every 947 * processor. 948 */ 949void 950pmap_invalidate_page(pmap_t pmap, vm_offset_t va) 951{ 952 u_int cpumask; 953 u_int other_cpus; 954 955 sched_pin(); 956 if (pmap == kernel_pmap || pmap->pm_active == all_cpus) { 957 invlpg(va); 958 smp_invlpg(va); 959 } else { 960 cpumask = PCPU_GET(cpumask); 961 other_cpus = PCPU_GET(other_cpus); 962 if (pmap->pm_active & cpumask) 963 invlpg(va); 964 if (pmap->pm_active & other_cpus) 965 smp_masked_invlpg(pmap->pm_active & other_cpus, va); 966 } 967 sched_unpin(); 968} 969 970void 971pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 972{ 973 u_int cpumask; 974 u_int other_cpus; 975 vm_offset_t addr; 976 977 sched_pin(); 978 if (pmap == kernel_pmap || pmap->pm_active == all_cpus) { 979 for (addr = sva; addr < eva; addr += PAGE_SIZE) 980 invlpg(addr); 981 smp_invlpg_range(sva, eva); 982 } else { 983 cpumask = PCPU_GET(cpumask); 984 other_cpus = PCPU_GET(other_cpus); 985 if (pmap->pm_active & cpumask) 986 for (addr = sva; addr < eva; addr += PAGE_SIZE) 987 invlpg(addr); 988 if (pmap->pm_active & other_cpus) 989 smp_masked_invlpg_range(pmap->pm_active & other_cpus, 990 sva, eva); 991 } 992 sched_unpin(); 993} 994 995void 996pmap_invalidate_all(pmap_t pmap) 997{ 998 u_int cpumask; 999 u_int other_cpus; 1000 1001 sched_pin(); 1002 if (pmap == kernel_pmap || pmap->pm_active == all_cpus) { 1003 invltlb(); 1004 smp_invltlb(); 1005 } else { 1006 cpumask = PCPU_GET(cpumask); 1007 other_cpus = PCPU_GET(other_cpus); 1008 if (pmap->pm_active & cpumask) 1009 invltlb(); 1010 if (pmap->pm_active & other_cpus) 1011 smp_masked_invltlb(pmap->pm_active & other_cpus); 1012 } 1013 sched_unpin(); 1014} 1015 1016void 1017pmap_invalidate_cache(void) 1018{ 1019 1020 sched_pin(); 1021 wbinvd(); 1022 smp_cache_flush(); 1023 sched_unpin(); 1024} 1025 1026struct pde_action { 1027 cpumask_t store; /* processor that updates the PDE */ 1028 cpumask_t invalidate; /* processors that invalidate their TLB */ 1029 vm_offset_t va; 1030 pd_entry_t *pde; 1031 pd_entry_t newpde; 1032}; 1033 1034static void 1035pmap_update_pde_kernel(void *arg) 1036{ 1037 struct pde_action *act = arg; 1038 pd_entry_t *pde; 1039 pmap_t pmap; 1040 1041 if (act->store == PCPU_GET(cpumask)) 1042 /* 1043 * Elsewhere, this operation requires allpmaps_lock for 1044 * synchronization. Here, it does not because it is being 1045 * performed in the context of an all_cpus rendezvous. 1046 */ 1047 LIST_FOREACH(pmap, &allpmaps, pm_list) { 1048 pde = pmap_pde(pmap, act->va); 1049 pde_store(pde, act->newpde); 1050 } 1051} 1052 1053static void 1054pmap_update_pde_user(void *arg) 1055{ 1056 struct pde_action *act = arg; 1057 1058 if (act->store == PCPU_GET(cpumask)) 1059 pde_store(act->pde, act->newpde); 1060} 1061 1062static void 1063pmap_update_pde_teardown(void *arg) 1064{ 1065 struct pde_action *act = arg; 1066 1067 if ((act->invalidate & PCPU_GET(cpumask)) != 0) 1068 pmap_update_pde_invalidate(act->va, act->newpde); 1069} 1070 1071/* 1072 * Change the page size for the specified virtual address in a way that 1073 * prevents any possibility of the TLB ever having two entries that map the 1074 * same virtual address using different page sizes. This is the recommended 1075 * workaround for Erratum 383 on AMD Family 10h processors. It prevents a 1076 * machine check exception for a TLB state that is improperly diagnosed as a 1077 * hardware error. 1078 */ 1079static void 1080pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde) 1081{ 1082 struct pde_action act; 1083 cpumask_t active, cpumask; 1084 1085 sched_pin(); 1086 cpumask = PCPU_GET(cpumask); 1087 if (pmap == kernel_pmap) 1088 active = all_cpus; 1089 else 1090 active = pmap->pm_active; 1091 if ((active & PCPU_GET(other_cpus)) != 0) { 1092 act.store = cpumask; 1093 act.invalidate = active; 1094 act.va = va; 1095 act.pde = pde; 1096 act.newpde = newpde; 1097 smp_rendezvous_cpus(cpumask | active, 1098 smp_no_rendevous_barrier, pmap == kernel_pmap ? 1099 pmap_update_pde_kernel : pmap_update_pde_user, 1100 pmap_update_pde_teardown, &act); 1101 } else { 1102 if (pmap == kernel_pmap) 1103 pmap_kenter_pde(va, newpde); 1104 else 1105 pde_store(pde, newpde); 1106 if ((active & cpumask) != 0) 1107 pmap_update_pde_invalidate(va, newpde); 1108 } 1109 sched_unpin(); 1110} 1111#else /* !SMP */ 1112/* 1113 * Normal, non-SMP, 486+ invalidation functions. 1114 * We inline these within pmap.c for speed. 1115 */ 1116PMAP_INLINE void 1117pmap_invalidate_page(pmap_t pmap, vm_offset_t va) 1118{ 1119 1120 if (pmap == kernel_pmap || pmap->pm_active) 1121 invlpg(va); 1122} 1123 1124PMAP_INLINE void 1125pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 1126{ 1127 vm_offset_t addr; 1128 1129 if (pmap == kernel_pmap || pmap->pm_active) 1130 for (addr = sva; addr < eva; addr += PAGE_SIZE) 1131 invlpg(addr); 1132} 1133 1134PMAP_INLINE void 1135pmap_invalidate_all(pmap_t pmap) 1136{ 1137 1138 if (pmap == kernel_pmap || pmap->pm_active) 1139 invltlb(); 1140} 1141 1142PMAP_INLINE void 1143pmap_invalidate_cache(void) 1144{ 1145 1146 wbinvd(); 1147} 1148 1149static void 1150pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde) 1151{ 1152 1153 if (pmap == kernel_pmap) 1154 pmap_kenter_pde(va, newpde); 1155 else 1156 pde_store(pde, newpde); 1157 if (pmap == kernel_pmap || pmap->pm_active) 1158 pmap_update_pde_invalidate(va, newpde); 1159} 1160#endif /* !SMP */ 1161 1162void 1163pmap_invalidate_cache_range(vm_offset_t sva, vm_offset_t eva) 1164{ 1165 1166 KASSERT((sva & PAGE_MASK) == 0, 1167 ("pmap_invalidate_cache_range: sva not page-aligned")); 1168 KASSERT((eva & PAGE_MASK) == 0, 1169 ("pmap_invalidate_cache_range: eva not page-aligned")); 1170 1171 if (cpu_feature & CPUID_SS) 1172 ; /* If "Self Snoop" is supported, do nothing. */ 1173 else if ((cpu_feature & CPUID_CLFSH) != 0 && 1174 eva - sva < 2 * 1024 * 1024) { 1175 1176 /* 1177 * Otherwise, do per-cache line flush. Use the mfence 1178 * instruction to insure that previous stores are 1179 * included in the write-back. The processor 1180 * propagates flush to other processors in the cache 1181 * coherence domain. 1182 */ 1183 mfence(); 1184 for (; sva < eva; sva += cpu_clflush_line_size) 1185 clflush(sva); 1186 mfence(); 1187 } else { 1188 1189 /* 1190 * No targeted cache flush methods are supported by CPU, 1191 * or the supplied range is bigger than 2MB. 1192 * Globally invalidate cache. 1193 */ 1194 pmap_invalidate_cache(); 1195 } 1196} 1197 1198/* 1199 * Are we current address space or kernel? N.B. We return FALSE when 1200 * a pmap's page table is in use because a kernel thread is borrowing 1201 * it. The borrowed page table can change spontaneously, making any 1202 * dependence on its continued use subject to a race condition. 1203 */ 1204static __inline int 1205pmap_is_current(pmap_t pmap) 1206{ 1207 1208 return (pmap == kernel_pmap || 1209 (pmap == vmspace_pmap(curthread->td_proc->p_vmspace) && 1210 (pmap->pm_pdir[PTDPTDI] & PG_FRAME) == (PTDpde[0] & PG_FRAME))); 1211} 1212 1213/* 1214 * If the given pmap is not the current or kernel pmap, the returned pte must 1215 * be released by passing it to pmap_pte_release(). 1216 */ 1217pt_entry_t * 1218pmap_pte(pmap_t pmap, vm_offset_t va) 1219{ 1220 pd_entry_t newpf; 1221 pd_entry_t *pde; 1222 1223 pde = pmap_pde(pmap, va); 1224 if (*pde & PG_PS) 1225 return (pde); 1226 if (*pde != 0) { 1227 /* are we current address space or kernel? */ 1228 if (pmap_is_current(pmap)) 1229 return (vtopte(va)); 1230 mtx_lock(&PMAP2mutex); 1231 newpf = *pde & PG_FRAME; 1232 if ((*PMAP2 & PG_FRAME) != newpf) { 1233 *PMAP2 = newpf | PG_RW | PG_V | PG_A | PG_M; 1234 pmap_invalidate_page(kernel_pmap, (vm_offset_t)PADDR2); 1235 } 1236 return (PADDR2 + (i386_btop(va) & (NPTEPG - 1))); 1237 } 1238 return (0); 1239} 1240 1241/* 1242 * Releases a pte that was obtained from pmap_pte(). Be prepared for the pte 1243 * being NULL. 1244 */ 1245static __inline void 1246pmap_pte_release(pt_entry_t *pte) 1247{ 1248 1249 if ((pt_entry_t *)((vm_offset_t)pte & ~PAGE_MASK) == PADDR2) 1250 mtx_unlock(&PMAP2mutex); 1251} 1252 1253static __inline void 1254invlcaddr(void *caddr) 1255{ 1256 1257 invlpg((u_int)caddr); 1258} 1259 1260/* 1261 * Super fast pmap_pte routine best used when scanning 1262 * the pv lists. This eliminates many coarse-grained 1263 * invltlb calls. Note that many of the pv list 1264 * scans are across different pmaps. It is very wasteful 1265 * to do an entire invltlb for checking a single mapping. 1266 * 1267 * If the given pmap is not the current pmap, vm_page_queue_mtx 1268 * must be held and curthread pinned to a CPU. 1269 */ 1270static pt_entry_t * 1271pmap_pte_quick(pmap_t pmap, vm_offset_t va) 1272{ 1273 pd_entry_t newpf; 1274 pd_entry_t *pde; 1275 1276 pde = pmap_pde(pmap, va); 1277 if (*pde & PG_PS) 1278 return (pde); 1279 if (*pde != 0) { 1280 /* are we current address space or kernel? */ 1281 if (pmap_is_current(pmap)) 1282 return (vtopte(va)); 1283 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1284 KASSERT(curthread->td_pinned > 0, ("curthread not pinned")); 1285 newpf = *pde & PG_FRAME; 1286 if ((*PMAP1 & PG_FRAME) != newpf) { 1287 *PMAP1 = newpf | PG_RW | PG_V | PG_A | PG_M; 1288#ifdef SMP 1289 PMAP1cpu = PCPU_GET(cpuid); 1290#endif 1291 invlcaddr(PADDR1); 1292 PMAP1changed++; 1293 } else 1294#ifdef SMP 1295 if (PMAP1cpu != PCPU_GET(cpuid)) { 1296 PMAP1cpu = PCPU_GET(cpuid); 1297 invlcaddr(PADDR1); 1298 PMAP1changedcpu++; 1299 } else 1300#endif 1301 PMAP1unchanged++; 1302 return (PADDR1 + (i386_btop(va) & (NPTEPG - 1))); 1303 } 1304 return (0); 1305} 1306 1307/* 1308 * Routine: pmap_extract 1309 * Function: 1310 * Extract the physical page address associated 1311 * with the given map/virtual_address pair. 1312 */ 1313vm_paddr_t 1314pmap_extract(pmap_t pmap, vm_offset_t va) 1315{ 1316 vm_paddr_t rtval; 1317 pt_entry_t *pte; 1318 pd_entry_t pde; 1319 1320 rtval = 0; 1321 PMAP_LOCK(pmap); 1322 pde = pmap->pm_pdir[va >> PDRSHIFT]; 1323 if (pde != 0) { 1324 if ((pde & PG_PS) != 0) 1325 rtval = (pde & PG_PS_FRAME) | (va & PDRMASK); 1326 else { 1327 pte = pmap_pte(pmap, va); 1328 rtval = (*pte & PG_FRAME) | (va & PAGE_MASK); 1329 pmap_pte_release(pte); 1330 } 1331 } 1332 PMAP_UNLOCK(pmap); 1333 return (rtval); 1334} 1335 1336/* 1337 * Routine: pmap_extract_and_hold 1338 * Function: 1339 * Atomically extract and hold the physical page 1340 * with the given pmap and virtual address pair 1341 * if that mapping permits the given protection. 1342 */ 1343vm_page_t 1344pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot) 1345{ 1346 pd_entry_t pde; 1347 pt_entry_t pte; 1348 vm_page_t m; 1349 vm_paddr_t pa; 1350 1351 pa = 0; 1352 m = NULL; 1353 PMAP_LOCK(pmap); 1354retry: 1355 pde = *pmap_pde(pmap, va); 1356 if (pde != 0) { 1357 if (pde & PG_PS) { 1358 if ((pde & PG_RW) || (prot & VM_PROT_WRITE) == 0) { 1359 if (vm_page_pa_tryrelock(pmap, (pde & PG_PS_FRAME) | 1360 (va & PDRMASK), &pa)) 1361 goto retry; 1362 m = PHYS_TO_VM_PAGE((pde & PG_PS_FRAME) | 1363 (va & PDRMASK)); 1364 vm_page_hold(m); 1365 } 1366 } else { 1367 sched_pin(); 1368 pte = *pmap_pte_quick(pmap, va); 1369 if (pte != 0 && 1370 ((pte & PG_RW) || (prot & VM_PROT_WRITE) == 0)) { 1371 if (vm_page_pa_tryrelock(pmap, pte & PG_FRAME, &pa)) 1372 goto retry; 1373 m = PHYS_TO_VM_PAGE(pte & PG_FRAME); 1374 vm_page_hold(m); 1375 } 1376 sched_unpin(); 1377 } 1378 } 1379 PA_UNLOCK_COND(pa); 1380 PMAP_UNLOCK(pmap); 1381 return (m); 1382} 1383 1384/*************************************************** 1385 * Low level mapping routines..... 1386 ***************************************************/ 1387 1388/* 1389 * Add a wired page to the kva. 1390 * Note: not SMP coherent. 1391 */ 1392PMAP_INLINE void 1393pmap_kenter(vm_offset_t va, vm_paddr_t pa) 1394{ 1395 pt_entry_t *pte; 1396 1397 pte = vtopte(va); 1398 pte_store(pte, pa | PG_RW | PG_V | pgeflag); 1399} 1400 1401static __inline void 1402pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode) 1403{ 1404 pt_entry_t *pte; 1405 1406 pte = vtopte(va); 1407 pte_store(pte, pa | PG_RW | PG_V | pgeflag | pmap_cache_bits(mode, 0)); 1408} 1409 1410/* 1411 * Remove a page from the kernel pagetables. 1412 * Note: not SMP coherent. 1413 */ 1414PMAP_INLINE void 1415pmap_kremove(vm_offset_t va) 1416{ 1417 pt_entry_t *pte; 1418 1419 pte = vtopte(va); 1420 pte_clear(pte); 1421} 1422 1423/* 1424 * Used to map a range of physical addresses into kernel 1425 * virtual address space. 1426 * 1427 * The value passed in '*virt' is a suggested virtual address for 1428 * the mapping. Architectures which can support a direct-mapped 1429 * physical to virtual region can return the appropriate address 1430 * within that region, leaving '*virt' unchanged. Other 1431 * architectures should map the pages starting at '*virt' and 1432 * update '*virt' with the first usable address after the mapped 1433 * region. 1434 */ 1435vm_offset_t 1436pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot) 1437{ 1438 vm_offset_t va, sva; 1439 1440 va = sva = *virt; 1441 while (start < end) { 1442 pmap_kenter(va, start); 1443 va += PAGE_SIZE; 1444 start += PAGE_SIZE; 1445 } 1446 pmap_invalidate_range(kernel_pmap, sva, va); 1447 *virt = va; 1448 return (sva); 1449} 1450 1451 1452/* 1453 * Add a list of wired pages to the kva 1454 * this routine is only used for temporary 1455 * kernel mappings that do not need to have 1456 * page modification or references recorded. 1457 * Note that old mappings are simply written 1458 * over. The page *must* be wired. 1459 * Note: SMP coherent. Uses a ranged shootdown IPI. 1460 */ 1461void 1462pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count) 1463{ 1464 pt_entry_t *endpte, oldpte, pa, *pte; 1465 vm_page_t m; 1466 1467 oldpte = 0; 1468 pte = vtopte(sva); 1469 endpte = pte + count; 1470 while (pte < endpte) { 1471 m = *ma++; 1472 pa = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(m->md.pat_mode, 0); 1473 if ((*pte & (PG_FRAME | PG_PTE_CACHE)) != pa) { 1474 oldpte |= *pte; 1475 pte_store(pte, pa | pgeflag | PG_RW | PG_V); 1476 } 1477 pte++; 1478 } 1479 if (__predict_false((oldpte & PG_V) != 0)) 1480 pmap_invalidate_range(kernel_pmap, sva, sva + count * 1481 PAGE_SIZE); 1482} 1483 1484/* 1485 * This routine tears out page mappings from the 1486 * kernel -- it is meant only for temporary mappings. 1487 * Note: SMP coherent. Uses a ranged shootdown IPI. 1488 */ 1489void 1490pmap_qremove(vm_offset_t sva, int count) 1491{ 1492 vm_offset_t va; 1493 1494 va = sva; 1495 while (count-- > 0) { 1496 pmap_kremove(va); 1497 va += PAGE_SIZE; 1498 } 1499 pmap_invalidate_range(kernel_pmap, sva, va); 1500} 1501 1502/*************************************************** 1503 * Page table page management routines..... 1504 ***************************************************/ 1505static __inline void 1506pmap_free_zero_pages(vm_page_t free) 1507{ 1508 vm_page_t m; 1509 1510 while (free != NULL) { 1511 m = free; 1512 free = m->right; 1513 /* Preserve the page's PG_ZERO setting. */ 1514 vm_page_free_toq(m); 1515 } 1516} 1517 1518/* 1519 * Schedule the specified unused page table page to be freed. Specifically, 1520 * add the page to the specified list of pages that will be released to the 1521 * physical memory manager after the TLB has been updated. 1522 */ 1523static __inline void 1524pmap_add_delayed_free_list(vm_page_t m, vm_page_t *free, boolean_t set_PG_ZERO) 1525{ 1526 1527 if (set_PG_ZERO) 1528 m->flags |= PG_ZERO; 1529 else 1530 m->flags &= ~PG_ZERO; 1531 m->right = *free; 1532 *free = m; 1533} 1534 1535/* 1536 * Inserts the specified page table page into the specified pmap's collection 1537 * of idle page table pages. Each of a pmap's page table pages is responsible 1538 * for mapping a distinct range of virtual addresses. The pmap's collection is 1539 * ordered by this virtual address range. 1540 */ 1541static void 1542pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte) 1543{ 1544 vm_page_t root; 1545 1546 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1547 root = pmap->pm_root; 1548 if (root == NULL) { 1549 mpte->left = NULL; 1550 mpte->right = NULL; 1551 } else { 1552 root = vm_page_splay(mpte->pindex, root); 1553 if (mpte->pindex < root->pindex) { 1554 mpte->left = root->left; 1555 mpte->right = root; 1556 root->left = NULL; 1557 } else if (mpte->pindex == root->pindex) 1558 panic("pmap_insert_pt_page: pindex already inserted"); 1559 else { 1560 mpte->right = root->right; 1561 mpte->left = root; 1562 root->right = NULL; 1563 } 1564 } 1565 pmap->pm_root = mpte; 1566} 1567 1568/* 1569 * Looks for a page table page mapping the specified virtual address in the 1570 * specified pmap's collection of idle page table pages. Returns NULL if there 1571 * is no page table page corresponding to the specified virtual address. 1572 */ 1573static vm_page_t 1574pmap_lookup_pt_page(pmap_t pmap, vm_offset_t va) 1575{ 1576 vm_page_t mpte; 1577 vm_pindex_t pindex = va >> PDRSHIFT; 1578 1579 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1580 if ((mpte = pmap->pm_root) != NULL && mpte->pindex != pindex) { 1581 mpte = vm_page_splay(pindex, mpte); 1582 if ((pmap->pm_root = mpte)->pindex != pindex) 1583 mpte = NULL; 1584 } 1585 return (mpte); 1586} 1587 1588/* 1589 * Removes the specified page table page from the specified pmap's collection 1590 * of idle page table pages. The specified page table page must be a member of 1591 * the pmap's collection. 1592 */ 1593static void 1594pmap_remove_pt_page(pmap_t pmap, vm_page_t mpte) 1595{ 1596 vm_page_t root; 1597 1598 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1599 if (mpte != pmap->pm_root) 1600 vm_page_splay(mpte->pindex, pmap->pm_root); 1601 if (mpte->left == NULL) 1602 root = mpte->right; 1603 else { 1604 root = vm_page_splay(mpte->pindex, mpte->left); 1605 root->right = mpte->right; 1606 } 1607 pmap->pm_root = root; 1608} 1609 1610/* 1611 * This routine unholds page table pages, and if the hold count 1612 * drops to zero, then it decrements the wire count. 1613 */ 1614static __inline int 1615pmap_unwire_pte_hold(pmap_t pmap, vm_page_t m, vm_page_t *free) 1616{ 1617 1618 --m->wire_count; 1619 if (m->wire_count == 0) 1620 return (_pmap_unwire_pte_hold(pmap, m, free)); 1621 else 1622 return (0); 1623} 1624 1625static int 1626_pmap_unwire_pte_hold(pmap_t pmap, vm_page_t m, vm_page_t *free) 1627{ 1628 vm_offset_t pteva; 1629 1630 /* 1631 * unmap the page table page 1632 */ 1633 pmap->pm_pdir[m->pindex] = 0; 1634 --pmap->pm_stats.resident_count; 1635 1636 /* 1637 * This is a release store so that the ordinary store unmapping 1638 * the page table page is globally performed before TLB shoot- 1639 * down is begun. 1640 */ 1641 atomic_subtract_rel_int(&cnt.v_wire_count, 1); 1642 1643 /* 1644 * Do an invltlb to make the invalidated mapping 1645 * take effect immediately. 1646 */ 1647 pteva = VM_MAXUSER_ADDRESS + i386_ptob(m->pindex); 1648 pmap_invalidate_page(pmap, pteva); 1649 1650 /* 1651 * Put page on a list so that it is released after 1652 * *ALL* TLB shootdown is done 1653 */ 1654 pmap_add_delayed_free_list(m, free, TRUE); 1655 1656 return (1); 1657} 1658 1659/* 1660 * After removing a page table entry, this routine is used to 1661 * conditionally free the page, and manage the hold/wire counts. 1662 */ 1663static int 1664pmap_unuse_pt(pmap_t pmap, vm_offset_t va, vm_page_t *free) 1665{ 1666 pd_entry_t ptepde; 1667 vm_page_t mpte; 1668 1669 if (va >= VM_MAXUSER_ADDRESS) 1670 return (0); 1671 ptepde = *pmap_pde(pmap, va); 1672 mpte = PHYS_TO_VM_PAGE(ptepde & PG_FRAME); 1673 return (pmap_unwire_pte_hold(pmap, mpte, free)); 1674} 1675 1676void 1677pmap_pinit0(pmap_t pmap) 1678{ 1679 1680 PMAP_LOCK_INIT(pmap); 1681 pmap->pm_pdir = (pd_entry_t *)(KERNBASE + (vm_offset_t)IdlePTD); 1682#ifdef PAE 1683 pmap->pm_pdpt = (pdpt_entry_t *)(KERNBASE + (vm_offset_t)IdlePDPT); 1684#endif 1685 pmap->pm_root = NULL; 1686 pmap->pm_active = 0; 1687 PCPU_SET(curpmap, pmap); 1688 TAILQ_INIT(&pmap->pm_pvchunk); 1689 bzero(&pmap->pm_stats, sizeof pmap->pm_stats); 1690 mtx_lock_spin(&allpmaps_lock); 1691 LIST_INSERT_HEAD(&allpmaps, pmap, pm_list); 1692 mtx_unlock_spin(&allpmaps_lock); 1693} 1694 1695/* 1696 * Initialize a preallocated and zeroed pmap structure, 1697 * such as one in a vmspace structure. 1698 */ 1699int 1700pmap_pinit(pmap_t pmap) 1701{ 1702 vm_page_t m, ptdpg[NPGPTD]; 1703 vm_paddr_t pa; 1704 static int color; 1705 int i; 1706 1707 PMAP_LOCK_INIT(pmap); 1708 1709 /* 1710 * No need to allocate page table space yet but we do need a valid 1711 * page directory table. 1712 */ 1713 if (pmap->pm_pdir == NULL) { 1714 pmap->pm_pdir = (pd_entry_t *)kmem_alloc_nofault(kernel_map, 1715 NBPTD); 1716 1717 if (pmap->pm_pdir == NULL) { 1718 PMAP_LOCK_DESTROY(pmap); 1719 return (0); 1720 } 1721#ifdef PAE 1722 pmap->pm_pdpt = uma_zalloc(pdptzone, M_WAITOK | M_ZERO); 1723 KASSERT(((vm_offset_t)pmap->pm_pdpt & 1724 ((NPGPTD * sizeof(pdpt_entry_t)) - 1)) == 0, 1725 ("pmap_pinit: pdpt misaligned")); 1726 KASSERT(pmap_kextract((vm_offset_t)pmap->pm_pdpt) < (4ULL<<30), 1727 ("pmap_pinit: pdpt above 4g")); 1728#endif 1729 pmap->pm_root = NULL; 1730 } 1731 KASSERT(pmap->pm_root == NULL, 1732 ("pmap_pinit: pmap has reserved page table page(s)")); 1733 1734 /* 1735 * allocate the page directory page(s) 1736 */ 1737 for (i = 0; i < NPGPTD;) { 1738 m = vm_page_alloc(NULL, color++, 1739 VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | 1740 VM_ALLOC_ZERO); 1741 if (m == NULL) 1742 VM_WAIT; 1743 else { 1744 ptdpg[i++] = m; 1745 } 1746 } 1747 1748 pmap_qenter((vm_offset_t)pmap->pm_pdir, ptdpg, NPGPTD); 1749 1750 for (i = 0; i < NPGPTD; i++) { 1751 if ((ptdpg[i]->flags & PG_ZERO) == 0) 1752 bzero(pmap->pm_pdir + (i * NPDEPG), PAGE_SIZE); 1753 } 1754 1755 mtx_lock_spin(&allpmaps_lock); 1756 LIST_INSERT_HEAD(&allpmaps, pmap, pm_list); 1757 mtx_unlock_spin(&allpmaps_lock); 1758 /* Wire in kernel global address entries. */ 1759 bcopy(PTD + KPTDI, pmap->pm_pdir + KPTDI, nkpt * sizeof(pd_entry_t)); 1760 1761 /* install self-referential address mapping entry(s) */ 1762 for (i = 0; i < NPGPTD; i++) { 1763 pa = VM_PAGE_TO_PHYS(ptdpg[i]); 1764 pmap->pm_pdir[PTDPTDI + i] = pa | PG_V | PG_RW | PG_A | PG_M; 1765#ifdef PAE 1766 pmap->pm_pdpt[i] = pa | PG_V; 1767#endif 1768 } 1769 1770 pmap->pm_active = 0; 1771 TAILQ_INIT(&pmap->pm_pvchunk); 1772 bzero(&pmap->pm_stats, sizeof pmap->pm_stats); 1773 1774 return (1); 1775} 1776 1777/* 1778 * this routine is called if the page table page is not 1779 * mapped correctly. 1780 */ 1781static vm_page_t 1782_pmap_allocpte(pmap_t pmap, unsigned ptepindex, int flags) 1783{ 1784 vm_paddr_t ptepa; 1785 vm_page_t m; 1786 1787 KASSERT((flags & (M_NOWAIT | M_WAITOK)) == M_NOWAIT || 1788 (flags & (M_NOWAIT | M_WAITOK)) == M_WAITOK, 1789 ("_pmap_allocpte: flags is neither M_NOWAIT nor M_WAITOK")); 1790 1791 /* 1792 * Allocate a page table page. 1793 */ 1794 if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ | 1795 VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) { 1796 if (flags & M_WAITOK) { 1797 PMAP_UNLOCK(pmap); 1798 vm_page_unlock_queues(); 1799 VM_WAIT; 1800 vm_page_lock_queues(); 1801 PMAP_LOCK(pmap); 1802 } 1803 1804 /* 1805 * Indicate the need to retry. While waiting, the page table 1806 * page may have been allocated. 1807 */ 1808 return (NULL); 1809 } 1810 if ((m->flags & PG_ZERO) == 0) 1811 pmap_zero_page(m); 1812 1813 /* 1814 * Map the pagetable page into the process address space, if 1815 * it isn't already there. 1816 */ 1817 1818 pmap->pm_stats.resident_count++; 1819 1820 ptepa = VM_PAGE_TO_PHYS(m); 1821 pmap->pm_pdir[ptepindex] = 1822 (pd_entry_t) (ptepa | PG_U | PG_RW | PG_V | PG_A | PG_M); 1823 1824 return (m); 1825} 1826 1827static vm_page_t 1828pmap_allocpte(pmap_t pmap, vm_offset_t va, int flags) 1829{ 1830 unsigned ptepindex; 1831 pd_entry_t ptepa; 1832 vm_page_t m; 1833 1834 KASSERT((flags & (M_NOWAIT | M_WAITOK)) == M_NOWAIT || 1835 (flags & (M_NOWAIT | M_WAITOK)) == M_WAITOK, 1836 ("pmap_allocpte: flags is neither M_NOWAIT nor M_WAITOK")); 1837 1838 /* 1839 * Calculate pagetable page index 1840 */ 1841 ptepindex = va >> PDRSHIFT; 1842retry: 1843 /* 1844 * Get the page directory entry 1845 */ 1846 ptepa = pmap->pm_pdir[ptepindex]; 1847 1848 /* 1849 * This supports switching from a 4MB page to a 1850 * normal 4K page. 1851 */ 1852 if (ptepa & PG_PS) { 1853 (void)pmap_demote_pde(pmap, &pmap->pm_pdir[ptepindex], va); 1854 ptepa = pmap->pm_pdir[ptepindex]; 1855 } 1856 1857 /* 1858 * If the page table page is mapped, we just increment the 1859 * hold count, and activate it. 1860 */ 1861 if (ptepa) { 1862 m = PHYS_TO_VM_PAGE(ptepa & PG_FRAME); 1863 m->wire_count++; 1864 } else { 1865 /* 1866 * Here if the pte page isn't mapped, or if it has 1867 * been deallocated. 1868 */ 1869 m = _pmap_allocpte(pmap, ptepindex, flags); 1870 if (m == NULL && (flags & M_WAITOK)) 1871 goto retry; 1872 } 1873 return (m); 1874} 1875 1876 1877/*************************************************** 1878* Pmap allocation/deallocation routines. 1879 ***************************************************/ 1880 1881#ifdef SMP 1882/* 1883 * Deal with a SMP shootdown of other users of the pmap that we are 1884 * trying to dispose of. This can be a bit hairy. 1885 */ 1886static cpumask_t *lazymask; 1887static u_int lazyptd; 1888static volatile u_int lazywait; 1889 1890void pmap_lazyfix_action(void); 1891 1892void 1893pmap_lazyfix_action(void) 1894{ 1895 cpumask_t mymask = PCPU_GET(cpumask); 1896 1897#ifdef COUNT_IPIS 1898 (*ipi_lazypmap_counts[PCPU_GET(cpuid)])++; 1899#endif 1900 if (rcr3() == lazyptd) 1901 load_cr3(PCPU_GET(curpcb)->pcb_cr3); 1902 atomic_clear_int(lazymask, mymask); 1903 atomic_store_rel_int(&lazywait, 1); 1904} 1905 1906static void 1907pmap_lazyfix_self(cpumask_t mymask) 1908{ 1909 1910 if (rcr3() == lazyptd) 1911 load_cr3(PCPU_GET(curpcb)->pcb_cr3); 1912 atomic_clear_int(lazymask, mymask); 1913} 1914 1915 1916static void 1917pmap_lazyfix(pmap_t pmap) 1918{ 1919 cpumask_t mymask, mask; 1920 u_int spins; 1921 1922 while ((mask = pmap->pm_active) != 0) { 1923 spins = 50000000; 1924 mask = mask & -mask; /* Find least significant set bit */ 1925 mtx_lock_spin(&smp_ipi_mtx); 1926#ifdef PAE 1927 lazyptd = vtophys(pmap->pm_pdpt); 1928#else 1929 lazyptd = vtophys(pmap->pm_pdir); 1930#endif 1931 mymask = PCPU_GET(cpumask); 1932 if (mask == mymask) { 1933 lazymask = &pmap->pm_active; 1934 pmap_lazyfix_self(mymask); 1935 } else { 1936 atomic_store_rel_int((u_int *)&lazymask, 1937 (u_int)&pmap->pm_active); 1938 atomic_store_rel_int(&lazywait, 0); 1939 ipi_selected(mask, IPI_LAZYPMAP); 1940 while (lazywait == 0) { 1941 ia32_pause(); 1942 if (--spins == 0) 1943 break; 1944 } 1945 } 1946 mtx_unlock_spin(&smp_ipi_mtx); 1947 if (spins == 0) 1948 printf("pmap_lazyfix: spun for 50000000\n"); 1949 } 1950} 1951 1952#else /* SMP */ 1953 1954/* 1955 * Cleaning up on uniprocessor is easy. For various reasons, we're 1956 * unlikely to have to even execute this code, including the fact 1957 * that the cleanup is deferred until the parent does a wait(2), which 1958 * means that another userland process has run. 1959 */ 1960static void 1961pmap_lazyfix(pmap_t pmap) 1962{ 1963 u_int cr3; 1964 1965 cr3 = vtophys(pmap->pm_pdir); 1966 if (cr3 == rcr3()) { 1967 load_cr3(PCPU_GET(curpcb)->pcb_cr3); 1968 pmap->pm_active &= ~(PCPU_GET(cpumask)); 1969 } 1970} 1971#endif /* SMP */ 1972 1973/* 1974 * Release any resources held by the given physical map. 1975 * Called when a pmap initialized by pmap_pinit is being released. 1976 * Should only be called if the map contains no valid mappings. 1977 */ 1978void 1979pmap_release(pmap_t pmap) 1980{ 1981 vm_page_t m, ptdpg[NPGPTD]; 1982 int i; 1983 1984 KASSERT(pmap->pm_stats.resident_count == 0, 1985 ("pmap_release: pmap resident count %ld != 0", 1986 pmap->pm_stats.resident_count)); 1987 KASSERT(pmap->pm_root == NULL, 1988 ("pmap_release: pmap has reserved page table page(s)")); 1989 1990 pmap_lazyfix(pmap); 1991 mtx_lock_spin(&allpmaps_lock); 1992 LIST_REMOVE(pmap, pm_list); 1993 mtx_unlock_spin(&allpmaps_lock); 1994 1995 for (i = 0; i < NPGPTD; i++) 1996 ptdpg[i] = PHYS_TO_VM_PAGE(pmap->pm_pdir[PTDPTDI + i] & 1997 PG_FRAME); 1998 1999 bzero(pmap->pm_pdir + PTDPTDI, (nkpt + NPGPTD) * 2000 sizeof(*pmap->pm_pdir)); 2001 2002 pmap_qremove((vm_offset_t)pmap->pm_pdir, NPGPTD); 2003 2004 for (i = 0; i < NPGPTD; i++) { 2005 m = ptdpg[i]; 2006#ifdef PAE 2007 KASSERT(VM_PAGE_TO_PHYS(m) == (pmap->pm_pdpt[i] & PG_FRAME), 2008 ("pmap_release: got wrong ptd page")); 2009#endif 2010 m->wire_count--; 2011 atomic_subtract_int(&cnt.v_wire_count, 1); 2012 vm_page_free_zero(m); 2013 } 2014 PMAP_LOCK_DESTROY(pmap); 2015} 2016 2017static int 2018kvm_size(SYSCTL_HANDLER_ARGS) 2019{ 2020 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - KERNBASE; 2021 2022 return (sysctl_handle_long(oidp, &ksize, 0, req)); 2023} 2024SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG|CTLFLAG_RD, 2025 0, 0, kvm_size, "IU", "Size of KVM"); 2026 2027static int 2028kvm_free(SYSCTL_HANDLER_ARGS) 2029{ 2030 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end; 2031 2032 return (sysctl_handle_long(oidp, &kfree, 0, req)); 2033} 2034SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG|CTLFLAG_RD, 2035 0, 0, kvm_free, "IU", "Amount of KVM free"); 2036 2037/* 2038 * grow the number of kernel page table entries, if needed 2039 */ 2040void 2041pmap_growkernel(vm_offset_t addr) 2042{ 2043 vm_paddr_t ptppaddr; 2044 vm_page_t nkpg; 2045 pd_entry_t newpdir; 2046 2047 mtx_assert(&kernel_map->system_mtx, MA_OWNED); 2048 addr = roundup2(addr, NBPDR); 2049 if (addr - 1 >= kernel_map->max_offset) 2050 addr = kernel_map->max_offset; 2051 while (kernel_vm_end < addr) { 2052 if (pdir_pde(PTD, kernel_vm_end)) { 2053 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK; 2054 if (kernel_vm_end - 1 >= kernel_map->max_offset) { 2055 kernel_vm_end = kernel_map->max_offset; 2056 break; 2057 } 2058 continue; 2059 } 2060 2061 nkpg = vm_page_alloc(NULL, kernel_vm_end >> PDRSHIFT, 2062 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | 2063 VM_ALLOC_ZERO); 2064 if (nkpg == NULL) 2065 panic("pmap_growkernel: no memory to grow kernel"); 2066 2067 nkpt++; 2068 2069 if ((nkpg->flags & PG_ZERO) == 0) 2070 pmap_zero_page(nkpg); 2071 ptppaddr = VM_PAGE_TO_PHYS(nkpg); 2072 newpdir = (pd_entry_t) (ptppaddr | PG_V | PG_RW | PG_A | PG_M); 2073 pdir_pde(KPTD, kernel_vm_end) = pgeflag | newpdir; 2074 2075 pmap_kenter_pde(kernel_vm_end, newpdir); 2076 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK; 2077 if (kernel_vm_end - 1 >= kernel_map->max_offset) { 2078 kernel_vm_end = kernel_map->max_offset; 2079 break; 2080 } 2081 } 2082} 2083 2084 2085/*************************************************** 2086 * page management routines. 2087 ***************************************************/ 2088 2089CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE); 2090CTASSERT(_NPCM == 11); 2091 2092static __inline struct pv_chunk * 2093pv_to_chunk(pv_entry_t pv) 2094{ 2095 2096 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK)); 2097} 2098 2099#define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap) 2100 2101#define PC_FREE0_9 0xfffffffful /* Free values for index 0 through 9 */ 2102#define PC_FREE10 0x0000fffful /* Free values for index 10 */ 2103 2104static uint32_t pc_freemask[11] = { 2105 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9, 2106 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9, 2107 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9, 2108 PC_FREE0_9, PC_FREE10 2109}; 2110 2111SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0, 2112 "Current number of pv entries"); 2113 2114#ifdef PV_STATS 2115static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail; 2116 2117SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0, 2118 "Current number of pv entry chunks"); 2119SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0, 2120 "Current number of pv entry chunks allocated"); 2121SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0, 2122 "Current number of pv entry chunks frees"); 2123SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0, 2124 "Number of times tried to get a chunk page but failed."); 2125 2126static long pv_entry_frees, pv_entry_allocs; 2127static int pv_entry_spare; 2128 2129SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0, 2130 "Current number of pv entry frees"); 2131SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0, 2132 "Current number of pv entry allocs"); 2133SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0, 2134 "Current number of spare pv entries"); 2135 2136static int pmap_collect_inactive, pmap_collect_active; 2137 2138SYSCTL_INT(_vm_pmap, OID_AUTO, pmap_collect_inactive, CTLFLAG_RD, &pmap_collect_inactive, 0, 2139 "Current number times pmap_collect called on inactive queue"); 2140SYSCTL_INT(_vm_pmap, OID_AUTO, pmap_collect_active, CTLFLAG_RD, &pmap_collect_active, 0, 2141 "Current number times pmap_collect called on active queue"); 2142#endif 2143 2144/* 2145 * We are in a serious low memory condition. Resort to 2146 * drastic measures to free some pages so we can allocate 2147 * another pv entry chunk. This is normally called to 2148 * unmap inactive pages, and if necessary, active pages. 2149 */ 2150static void 2151pmap_collect(pmap_t locked_pmap, struct vpgqueues *vpq) 2152{ 2153 pd_entry_t *pde; 2154 pmap_t pmap; 2155 pt_entry_t *pte, tpte; 2156 pv_entry_t next_pv, pv; 2157 vm_offset_t va; 2158 vm_page_t m, free; 2159 2160 sched_pin(); 2161 TAILQ_FOREACH(m, &vpq->pl, pageq) { 2162 if (m->hold_count || m->busy) 2163 continue; 2164 TAILQ_FOREACH_SAFE(pv, &m->md.pv_list, pv_list, next_pv) { 2165 va = pv->pv_va; 2166 pmap = PV_PMAP(pv); 2167 /* Avoid deadlock and lock recursion. */ 2168 if (pmap > locked_pmap) 2169 PMAP_LOCK(pmap); 2170 else if (pmap != locked_pmap && !PMAP_TRYLOCK(pmap)) 2171 continue; 2172 pmap->pm_stats.resident_count--; 2173 pde = pmap_pde(pmap, va); 2174 KASSERT((*pde & PG_PS) == 0, ("pmap_collect: found" 2175 " a 4mpage in page %p's pv list", m)); 2176 pte = pmap_pte_quick(pmap, va); 2177 tpte = pte_load_clear(pte); 2178 KASSERT((tpte & PG_W) == 0, 2179 ("pmap_collect: wired pte %#jx", (uintmax_t)tpte)); 2180 if (tpte & PG_A) 2181 vm_page_flag_set(m, PG_REFERENCED); 2182 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) 2183 vm_page_dirty(m); 2184 free = NULL; 2185 pmap_unuse_pt(pmap, va, &free); 2186 pmap_invalidate_page(pmap, va); 2187 pmap_free_zero_pages(free); 2188 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list); 2189 free_pv_entry(pmap, pv); 2190 if (pmap != locked_pmap) 2191 PMAP_UNLOCK(pmap); 2192 } 2193 if (TAILQ_EMPTY(&m->md.pv_list) && 2194 TAILQ_EMPTY(&pa_to_pvh(VM_PAGE_TO_PHYS(m))->pv_list)) 2195 vm_page_flag_clear(m, PG_WRITEABLE); 2196 } 2197 sched_unpin(); 2198} 2199 2200 2201/* 2202 * free the pv_entry back to the free list 2203 */ 2204static void 2205free_pv_entry(pmap_t pmap, pv_entry_t pv) 2206{ 2207 vm_page_t m; 2208 struct pv_chunk *pc; 2209 int idx, field, bit; 2210 2211 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2212 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2213 PV_STAT(pv_entry_frees++); 2214 PV_STAT(pv_entry_spare++); 2215 pv_entry_count--; 2216 pc = pv_to_chunk(pv); 2217 idx = pv - &pc->pc_pventry[0]; 2218 field = idx / 32; 2219 bit = idx % 32; 2220 pc->pc_map[field] |= 1ul << bit; 2221 /* move to head of list */ 2222 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 2223 for (idx = 0; idx < _NPCM; idx++) 2224 if (pc->pc_map[idx] != pc_freemask[idx]) { 2225 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list); 2226 return; 2227 } 2228 PV_STAT(pv_entry_spare -= _NPCPV); 2229 PV_STAT(pc_chunk_count--); 2230 PV_STAT(pc_chunk_frees++); 2231 /* entire chunk is free, return it */ 2232 m = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc)); 2233 pmap_qremove((vm_offset_t)pc, 1); 2234 vm_page_unwire(m, 0); 2235 vm_page_free(m); 2236 pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc); 2237} 2238 2239/* 2240 * get a new pv_entry, allocating a block from the system 2241 * when needed. 2242 */ 2243static pv_entry_t 2244get_pv_entry(pmap_t pmap, int try) 2245{ 2246 static const struct timeval printinterval = { 60, 0 }; 2247 static struct timeval lastprint; 2248 static vm_pindex_t colour; 2249 struct vpgqueues *pq; 2250 int bit, field; 2251 pv_entry_t pv; 2252 struct pv_chunk *pc; 2253 vm_page_t m; 2254 2255 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2256 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2257 PV_STAT(pv_entry_allocs++); 2258 pv_entry_count++; 2259 if (pv_entry_count > pv_entry_high_water) 2260 if (ratecheck(&lastprint, &printinterval)) 2261 printf("Approaching the limit on PV entries, consider " 2262 "increasing either the vm.pmap.shpgperproc or the " 2263 "vm.pmap.pv_entry_max tunable.\n"); 2264 pq = NULL; 2265retry: 2266 pc = TAILQ_FIRST(&pmap->pm_pvchunk); 2267 if (pc != NULL) { 2268 for (field = 0; field < _NPCM; field++) { 2269 if (pc->pc_map[field]) { 2270 bit = bsfl(pc->pc_map[field]); 2271 break; 2272 } 2273 } 2274 if (field < _NPCM) { 2275 pv = &pc->pc_pventry[field * 32 + bit]; 2276 pc->pc_map[field] &= ~(1ul << bit); 2277 /* If this was the last item, move it to tail */ 2278 for (field = 0; field < _NPCM; field++) 2279 if (pc->pc_map[field] != 0) { 2280 PV_STAT(pv_entry_spare--); 2281 return (pv); /* not full, return */ 2282 } 2283 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 2284 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list); 2285 PV_STAT(pv_entry_spare--); 2286 return (pv); 2287 } 2288 } 2289 /* 2290 * Access to the ptelist "pv_vafree" is synchronized by the page 2291 * queues lock. If "pv_vafree" is currently non-empty, it will 2292 * remain non-empty until pmap_ptelist_alloc() completes. 2293 */ 2294 if (pv_vafree == 0 || (m = vm_page_alloc(NULL, colour, (pq == 2295 &vm_page_queues[PQ_ACTIVE] ? VM_ALLOC_SYSTEM : VM_ALLOC_NORMAL) | 2296 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) { 2297 if (try) { 2298 pv_entry_count--; 2299 PV_STAT(pc_chunk_tryfail++); 2300 return (NULL); 2301 } 2302 /* 2303 * Reclaim pv entries: At first, destroy mappings to 2304 * inactive pages. After that, if a pv chunk entry 2305 * is still needed, destroy mappings to active pages. 2306 */ 2307 if (pq == NULL) { 2308 PV_STAT(pmap_collect_inactive++); 2309 pq = &vm_page_queues[PQ_INACTIVE]; 2310 } else if (pq == &vm_page_queues[PQ_INACTIVE]) { 2311 PV_STAT(pmap_collect_active++); 2312 pq = &vm_page_queues[PQ_ACTIVE]; 2313 } else 2314 panic("get_pv_entry: increase vm.pmap.shpgperproc"); 2315 pmap_collect(pmap, pq); 2316 goto retry; 2317 } 2318 PV_STAT(pc_chunk_count++); 2319 PV_STAT(pc_chunk_allocs++); 2320 colour++; 2321 pc = (struct pv_chunk *)pmap_ptelist_alloc(&pv_vafree); 2322 pmap_qenter((vm_offset_t)pc, &m, 1); 2323 pc->pc_pmap = pmap; 2324 pc->pc_map[0] = pc_freemask[0] & ~1ul; /* preallocated bit 0 */ 2325 for (field = 1; field < _NPCM; field++) 2326 pc->pc_map[field] = pc_freemask[field]; 2327 pv = &pc->pc_pventry[0]; 2328 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list); 2329 PV_STAT(pv_entry_spare += _NPCPV - 1); 2330 return (pv); 2331} 2332 2333static __inline pv_entry_t 2334pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va) 2335{ 2336 pv_entry_t pv; 2337 2338 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2339 TAILQ_FOREACH(pv, &pvh->pv_list, pv_list) { 2340 if (pmap == PV_PMAP(pv) && va == pv->pv_va) { 2341 TAILQ_REMOVE(&pvh->pv_list, pv, pv_list); 2342 break; 2343 } 2344 } 2345 return (pv); 2346} 2347 2348static void 2349pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa) 2350{ 2351 struct md_page *pvh; 2352 pv_entry_t pv; 2353 vm_offset_t va_last; 2354 vm_page_t m; 2355 2356 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2357 KASSERT((pa & PDRMASK) == 0, 2358 ("pmap_pv_demote_pde: pa is not 4mpage aligned")); 2359 2360 /* 2361 * Transfer the 4mpage's pv entry for this mapping to the first 2362 * page's pv list. 2363 */ 2364 pvh = pa_to_pvh(pa); 2365 va = trunc_4mpage(va); 2366 pv = pmap_pvh_remove(pvh, pmap, va); 2367 KASSERT(pv != NULL, ("pmap_pv_demote_pde: pv not found")); 2368 m = PHYS_TO_VM_PAGE(pa); 2369 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list); 2370 /* Instantiate the remaining NPTEPG - 1 pv entries. */ 2371 va_last = va + NBPDR - PAGE_SIZE; 2372 do { 2373 m++; 2374 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 2375 ("pmap_pv_demote_pde: page %p is not managed", m)); 2376 va += PAGE_SIZE; 2377 pmap_insert_entry(pmap, va, m); 2378 } while (va < va_last); 2379} 2380 2381static void 2382pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa) 2383{ 2384 struct md_page *pvh; 2385 pv_entry_t pv; 2386 vm_offset_t va_last; 2387 vm_page_t m; 2388 2389 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2390 KASSERT((pa & PDRMASK) == 0, 2391 ("pmap_pv_promote_pde: pa is not 4mpage aligned")); 2392 2393 /* 2394 * Transfer the first page's pv entry for this mapping to the 2395 * 4mpage's pv list. Aside from avoiding the cost of a call 2396 * to get_pv_entry(), a transfer avoids the possibility that 2397 * get_pv_entry() calls pmap_collect() and that pmap_collect() 2398 * removes one of the mappings that is being promoted. 2399 */ 2400 m = PHYS_TO_VM_PAGE(pa); 2401 va = trunc_4mpage(va); 2402 pv = pmap_pvh_remove(&m->md, pmap, va); 2403 KASSERT(pv != NULL, ("pmap_pv_promote_pde: pv not found")); 2404 pvh = pa_to_pvh(pa); 2405 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_list); 2406 /* Free the remaining NPTEPG - 1 pv entries. */ 2407 va_last = va + NBPDR - PAGE_SIZE; 2408 do { 2409 m++; 2410 va += PAGE_SIZE; 2411 pmap_pvh_free(&m->md, pmap, va); 2412 } while (va < va_last); 2413} 2414 2415static void 2416pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va) 2417{ 2418 pv_entry_t pv; 2419 2420 pv = pmap_pvh_remove(pvh, pmap, va); 2421 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found")); 2422 free_pv_entry(pmap, pv); 2423} 2424 2425static void 2426pmap_remove_entry(pmap_t pmap, vm_page_t m, vm_offset_t va) 2427{ 2428 struct md_page *pvh; 2429 2430 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2431 pmap_pvh_free(&m->md, pmap, va); 2432 if (TAILQ_EMPTY(&m->md.pv_list)) { 2433 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 2434 if (TAILQ_EMPTY(&pvh->pv_list)) 2435 vm_page_flag_clear(m, PG_WRITEABLE); 2436 } 2437} 2438 2439/* 2440 * Create a pv entry for page at pa for 2441 * (pmap, va). 2442 */ 2443static void 2444pmap_insert_entry(pmap_t pmap, vm_offset_t va, vm_page_t m) 2445{ 2446 pv_entry_t pv; 2447 2448 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2449 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2450 pv = get_pv_entry(pmap, FALSE); 2451 pv->pv_va = va; 2452 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list); 2453} 2454 2455/* 2456 * Conditionally create a pv entry. 2457 */ 2458static boolean_t 2459pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m) 2460{ 2461 pv_entry_t pv; 2462 2463 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2464 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2465 if (pv_entry_count < pv_entry_high_water && 2466 (pv = get_pv_entry(pmap, TRUE)) != NULL) { 2467 pv->pv_va = va; 2468 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list); 2469 return (TRUE); 2470 } else 2471 return (FALSE); 2472} 2473 2474/* 2475 * Create the pv entries for each of the pages within a superpage. 2476 */ 2477static boolean_t 2478pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa) 2479{ 2480 struct md_page *pvh; 2481 pv_entry_t pv; 2482 2483 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2484 if (pv_entry_count < pv_entry_high_water && 2485 (pv = get_pv_entry(pmap, TRUE)) != NULL) { 2486 pv->pv_va = va; 2487 pvh = pa_to_pvh(pa); 2488 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_list); 2489 return (TRUE); 2490 } else 2491 return (FALSE); 2492} 2493 2494/* 2495 * Fills a page table page with mappings to consecutive physical pages. 2496 */ 2497static void 2498pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte) 2499{ 2500 pt_entry_t *pte; 2501 2502 for (pte = firstpte; pte < firstpte + NPTEPG; pte++) { 2503 *pte = newpte; 2504 newpte += PAGE_SIZE; 2505 } 2506} 2507 2508/* 2509 * Tries to demote a 2- or 4MB page mapping. If demotion fails, the 2510 * 2- or 4MB page mapping is invalidated. 2511 */ 2512static boolean_t 2513pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va) 2514{ 2515 pd_entry_t newpde, oldpde; 2516 pt_entry_t *firstpte, newpte; 2517 vm_paddr_t mptepa; 2518 vm_page_t free, mpte; 2519 2520 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2521 oldpde = *pde; 2522 KASSERT((oldpde & (PG_PS | PG_V)) == (PG_PS | PG_V), 2523 ("pmap_demote_pde: oldpde is missing PG_PS and/or PG_V")); 2524 mpte = pmap_lookup_pt_page(pmap, va); 2525 if (mpte != NULL) 2526 pmap_remove_pt_page(pmap, mpte); 2527 else { 2528 KASSERT((oldpde & PG_W) == 0, 2529 ("pmap_demote_pde: page table page for a wired mapping" 2530 " is missing")); 2531 2532 /* 2533 * Invalidate the 2- or 4MB page mapping and return 2534 * "failure" if the mapping was never accessed or the 2535 * allocation of the new page table page fails. 2536 */ 2537 if ((oldpde & PG_A) == 0 || (mpte = vm_page_alloc(NULL, 2538 va >> PDRSHIFT, VM_ALLOC_NOOBJ | VM_ALLOC_NORMAL | 2539 VM_ALLOC_WIRED)) == NULL) { 2540 free = NULL; 2541 pmap_remove_pde(pmap, pde, trunc_4mpage(va), &free); 2542 pmap_invalidate_page(pmap, trunc_4mpage(va)); 2543 pmap_free_zero_pages(free); 2544 CTR2(KTR_PMAP, "pmap_demote_pde: failure for va %#x" 2545 " in pmap %p", va, pmap); 2546 return (FALSE); 2547 } 2548 if (va < VM_MAXUSER_ADDRESS) 2549 pmap->pm_stats.resident_count++; 2550 } 2551 mptepa = VM_PAGE_TO_PHYS(mpte); 2552 2553 /* 2554 * If the page mapping is in the kernel's address space, then the 2555 * KPTmap can provide access to the page table page. Otherwise, 2556 * temporarily map the page table page (mpte) into the kernel's 2557 * address space at either PADDR1 or PADDR2. 2558 */ 2559 if (va >= KERNBASE) 2560 firstpte = &KPTmap[i386_btop(trunc_4mpage(va))]; 2561 else if (curthread->td_pinned > 0 && mtx_owned(&vm_page_queue_mtx)) { 2562 if ((*PMAP1 & PG_FRAME) != mptepa) { 2563 *PMAP1 = mptepa | PG_RW | PG_V | PG_A | PG_M; 2564#ifdef SMP 2565 PMAP1cpu = PCPU_GET(cpuid); 2566#endif 2567 invlcaddr(PADDR1); 2568 PMAP1changed++; 2569 } else 2570#ifdef SMP 2571 if (PMAP1cpu != PCPU_GET(cpuid)) { 2572 PMAP1cpu = PCPU_GET(cpuid); 2573 invlcaddr(PADDR1); 2574 PMAP1changedcpu++; 2575 } else 2576#endif 2577 PMAP1unchanged++; 2578 firstpte = PADDR1; 2579 } else { 2580 mtx_lock(&PMAP2mutex); 2581 if ((*PMAP2 & PG_FRAME) != mptepa) { 2582 *PMAP2 = mptepa | PG_RW | PG_V | PG_A | PG_M; 2583 pmap_invalidate_page(kernel_pmap, (vm_offset_t)PADDR2); 2584 } 2585 firstpte = PADDR2; 2586 } 2587 newpde = mptepa | PG_M | PG_A | (oldpde & PG_U) | PG_RW | PG_V; 2588 KASSERT((oldpde & PG_A) != 0, 2589 ("pmap_demote_pde: oldpde is missing PG_A")); 2590 KASSERT((oldpde & (PG_M | PG_RW)) != PG_RW, 2591 ("pmap_demote_pde: oldpde is missing PG_M")); 2592 newpte = oldpde & ~PG_PS; 2593 if ((newpte & PG_PDE_PAT) != 0) 2594 newpte ^= PG_PDE_PAT | PG_PTE_PAT; 2595 2596 /* 2597 * If the page table page is new, initialize it. 2598 */ 2599 if (mpte->wire_count == 1) { 2600 mpte->wire_count = NPTEPG; 2601 pmap_fill_ptp(firstpte, newpte); 2602 } 2603 KASSERT((*firstpte & PG_FRAME) == (newpte & PG_FRAME), 2604 ("pmap_demote_pde: firstpte and newpte map different physical" 2605 " addresses")); 2606 2607 /* 2608 * If the mapping has changed attributes, update the page table 2609 * entries. 2610 */ 2611 if ((*firstpte & PG_PTE_PROMOTE) != (newpte & PG_PTE_PROMOTE)) 2612 pmap_fill_ptp(firstpte, newpte); 2613 2614 /* 2615 * Demote the mapping. This pmap is locked. The old PDE has 2616 * PG_A set. If the old PDE has PG_RW set, it also has PG_M 2617 * set. Thus, there is no danger of a race with another 2618 * processor changing the setting of PG_A and/or PG_M between 2619 * the read above and the store below. 2620 */ 2621 if (workaround_erratum383) 2622 pmap_update_pde(pmap, va, pde, newpde); 2623 else if (pmap == kernel_pmap) 2624 pmap_kenter_pde(va, newpde); 2625 else 2626 pde_store(pde, newpde); 2627 if (firstpte == PADDR2) 2628 mtx_unlock(&PMAP2mutex); 2629 2630 /* 2631 * Invalidate the recursive mapping of the page table page. 2632 */ 2633 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va)); 2634 2635 /* 2636 * Demote the pv entry. This depends on the earlier demotion 2637 * of the mapping. Specifically, the (re)creation of a per- 2638 * page pv entry might trigger the execution of pmap_collect(), 2639 * which might reclaim a newly (re)created per-page pv entry 2640 * and destroy the associated mapping. In order to destroy 2641 * the mapping, the PDE must have already changed from mapping 2642 * the 2mpage to referencing the page table page. 2643 */ 2644 if ((oldpde & PG_MANAGED) != 0) 2645 pmap_pv_demote_pde(pmap, va, oldpde & PG_PS_FRAME); 2646 2647 pmap_pde_demotions++; 2648 CTR2(KTR_PMAP, "pmap_demote_pde: success for va %#x" 2649 " in pmap %p", va, pmap); 2650 return (TRUE); 2651} 2652 2653/* 2654 * pmap_remove_pde: do the things to unmap a superpage in a process 2655 */ 2656static void 2657pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva, 2658 vm_page_t *free) 2659{ 2660 struct md_page *pvh; 2661 pd_entry_t oldpde; 2662 vm_offset_t eva, va; 2663 vm_page_t m, mpte; 2664 2665 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2666 KASSERT((sva & PDRMASK) == 0, 2667 ("pmap_remove_pde: sva is not 4mpage aligned")); 2668 oldpde = pte_load_clear(pdq); 2669 if (oldpde & PG_W) 2670 pmap->pm_stats.wired_count -= NBPDR / PAGE_SIZE; 2671 2672 /* 2673 * Machines that don't support invlpg, also don't support 2674 * PG_G. 2675 */ 2676 if (oldpde & PG_G) 2677 pmap_invalidate_page(kernel_pmap, sva); 2678 pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE; 2679 if (oldpde & PG_MANAGED) { 2680 pvh = pa_to_pvh(oldpde & PG_PS_FRAME); 2681 pmap_pvh_free(pvh, pmap, sva); 2682 eva = sva + NBPDR; 2683 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME); 2684 va < eva; va += PAGE_SIZE, m++) { 2685 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW)) 2686 vm_page_dirty(m); 2687 if (oldpde & PG_A) 2688 vm_page_flag_set(m, PG_REFERENCED); 2689 if (TAILQ_EMPTY(&m->md.pv_list) && 2690 TAILQ_EMPTY(&pvh->pv_list)) 2691 vm_page_flag_clear(m, PG_WRITEABLE); 2692 } 2693 } 2694 if (pmap == kernel_pmap) { 2695 if (!pmap_demote_pde(pmap, pdq, sva)) 2696 panic("pmap_remove_pde: failed demotion"); 2697 } else { 2698 mpte = pmap_lookup_pt_page(pmap, sva); 2699 if (mpte != NULL) { 2700 pmap_remove_pt_page(pmap, mpte); 2701 pmap->pm_stats.resident_count--; 2702 KASSERT(mpte->wire_count == NPTEPG, 2703 ("pmap_remove_pde: pte page wire count error")); 2704 mpte->wire_count = 0; 2705 pmap_add_delayed_free_list(mpte, free, FALSE); 2706 atomic_subtract_int(&cnt.v_wire_count, 1); 2707 } 2708 } 2709} 2710 2711/* 2712 * pmap_remove_pte: do the things to unmap a page in a process 2713 */ 2714static int 2715pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t va, vm_page_t *free) 2716{ 2717 pt_entry_t oldpte; 2718 vm_page_t m; 2719 2720 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2721 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2722 oldpte = pte_load_clear(ptq); 2723 if (oldpte & PG_W) 2724 pmap->pm_stats.wired_count -= 1; 2725 /* 2726 * Machines that don't support invlpg, also don't support 2727 * PG_G. 2728 */ 2729 if (oldpte & PG_G) 2730 pmap_invalidate_page(kernel_pmap, va); 2731 pmap->pm_stats.resident_count -= 1; 2732 if (oldpte & PG_MANAGED) { 2733 m = PHYS_TO_VM_PAGE(oldpte & PG_FRAME); 2734 if ((oldpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) 2735 vm_page_dirty(m); 2736 if (oldpte & PG_A) 2737 vm_page_flag_set(m, PG_REFERENCED); 2738 pmap_remove_entry(pmap, m, va); 2739 } 2740 return (pmap_unuse_pt(pmap, va, free)); 2741} 2742 2743/* 2744 * Remove a single page from a process address space 2745 */ 2746static void 2747pmap_remove_page(pmap_t pmap, vm_offset_t va, vm_page_t *free) 2748{ 2749 pt_entry_t *pte; 2750 2751 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2752 KASSERT(curthread->td_pinned > 0, ("curthread not pinned")); 2753 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2754 if ((pte = pmap_pte_quick(pmap, va)) == NULL || *pte == 0) 2755 return; 2756 pmap_remove_pte(pmap, pte, va, free); 2757 pmap_invalidate_page(pmap, va); 2758} 2759 2760/* 2761 * Remove the given range of addresses from the specified map. 2762 * 2763 * It is assumed that the start and end are properly 2764 * rounded to the page size. 2765 */ 2766void 2767pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 2768{ 2769 vm_offset_t pdnxt; 2770 pd_entry_t ptpaddr; 2771 pt_entry_t *pte; 2772 vm_page_t free = NULL; 2773 int anyvalid; 2774 2775 /* 2776 * Perform an unsynchronized read. This is, however, safe. 2777 */ 2778 if (pmap->pm_stats.resident_count == 0) 2779 return; 2780 2781 anyvalid = 0; 2782 2783 vm_page_lock_queues(); 2784 sched_pin(); 2785 PMAP_LOCK(pmap); 2786 2787 /* 2788 * special handling of removing one page. a very 2789 * common operation and easy to short circuit some 2790 * code. 2791 */ 2792 if ((sva + PAGE_SIZE == eva) && 2793 ((pmap->pm_pdir[(sva >> PDRSHIFT)] & PG_PS) == 0)) { 2794 pmap_remove_page(pmap, sva, &free); 2795 goto out; 2796 } 2797 2798 for (; sva < eva; sva = pdnxt) { 2799 unsigned pdirindex; 2800 2801 /* 2802 * Calculate index for next page table. 2803 */ 2804 pdnxt = (sva + NBPDR) & ~PDRMASK; 2805 if (pdnxt < sva) 2806 pdnxt = eva; 2807 if (pmap->pm_stats.resident_count == 0) 2808 break; 2809 2810 pdirindex = sva >> PDRSHIFT; 2811 ptpaddr = pmap->pm_pdir[pdirindex]; 2812 2813 /* 2814 * Weed out invalid mappings. Note: we assume that the page 2815 * directory table is always allocated, and in kernel virtual. 2816 */ 2817 if (ptpaddr == 0) 2818 continue; 2819 2820 /* 2821 * Check for large page. 2822 */ 2823 if ((ptpaddr & PG_PS) != 0) { 2824 /* 2825 * Are we removing the entire large page? If not, 2826 * demote the mapping and fall through. 2827 */ 2828 if (sva + NBPDR == pdnxt && eva >= pdnxt) { 2829 /* 2830 * The TLB entry for a PG_G mapping is 2831 * invalidated by pmap_remove_pde(). 2832 */ 2833 if ((ptpaddr & PG_G) == 0) 2834 anyvalid = 1; 2835 pmap_remove_pde(pmap, 2836 &pmap->pm_pdir[pdirindex], sva, &free); 2837 continue; 2838 } else if (!pmap_demote_pde(pmap, 2839 &pmap->pm_pdir[pdirindex], sva)) { 2840 /* The large page mapping was destroyed. */ 2841 continue; 2842 } 2843 } 2844 2845 /* 2846 * Limit our scan to either the end of the va represented 2847 * by the current page table page, or to the end of the 2848 * range being removed. 2849 */ 2850 if (pdnxt > eva) 2851 pdnxt = eva; 2852 2853 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++, 2854 sva += PAGE_SIZE) { 2855 if (*pte == 0) 2856 continue; 2857 2858 /* 2859 * The TLB entry for a PG_G mapping is invalidated 2860 * by pmap_remove_pte(). 2861 */ 2862 if ((*pte & PG_G) == 0) 2863 anyvalid = 1; 2864 if (pmap_remove_pte(pmap, pte, sva, &free)) 2865 break; 2866 } 2867 } 2868out: 2869 sched_unpin(); 2870 if (anyvalid) 2871 pmap_invalidate_all(pmap); 2872 vm_page_unlock_queues(); 2873 PMAP_UNLOCK(pmap); 2874 pmap_free_zero_pages(free); 2875} 2876 2877/* 2878 * Routine: pmap_remove_all 2879 * Function: 2880 * Removes this physical page from 2881 * all physical maps in which it resides. 2882 * Reflects back modify bits to the pager. 2883 * 2884 * Notes: 2885 * Original versions of this routine were very 2886 * inefficient because they iteratively called 2887 * pmap_remove (slow...) 2888 */ 2889 2890void 2891pmap_remove_all(vm_page_t m) 2892{ 2893 struct md_page *pvh; 2894 pv_entry_t pv; 2895 pmap_t pmap; 2896 pt_entry_t *pte, tpte; 2897 pd_entry_t *pde; 2898 vm_offset_t va; 2899 vm_page_t free; 2900 2901 KASSERT((m->flags & PG_FICTITIOUS) == 0, 2902 ("pmap_remove_all: page %p is fictitious", m)); 2903 free = NULL; 2904 vm_page_lock_queues(); 2905 sched_pin(); 2906 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 2907 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) { 2908 va = pv->pv_va; 2909 pmap = PV_PMAP(pv); 2910 PMAP_LOCK(pmap); 2911 pde = pmap_pde(pmap, va); 2912 (void)pmap_demote_pde(pmap, pde, va); 2913 PMAP_UNLOCK(pmap); 2914 } 2915 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) { 2916 pmap = PV_PMAP(pv); 2917 PMAP_LOCK(pmap); 2918 pmap->pm_stats.resident_count--; 2919 pde = pmap_pde(pmap, pv->pv_va); 2920 KASSERT((*pde & PG_PS) == 0, ("pmap_remove_all: found" 2921 " a 4mpage in page %p's pv list", m)); 2922 pte = pmap_pte_quick(pmap, pv->pv_va); 2923 tpte = pte_load_clear(pte); 2924 if (tpte & PG_W) 2925 pmap->pm_stats.wired_count--; 2926 if (tpte & PG_A) 2927 vm_page_flag_set(m, PG_REFERENCED); 2928 2929 /* 2930 * Update the vm_page_t clean and reference bits. 2931 */ 2932 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) 2933 vm_page_dirty(m); 2934 pmap_unuse_pt(pmap, pv->pv_va, &free); 2935 pmap_invalidate_page(pmap, pv->pv_va); 2936 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list); 2937 free_pv_entry(pmap, pv); 2938 PMAP_UNLOCK(pmap); 2939 } 2940 vm_page_flag_clear(m, PG_WRITEABLE); 2941 sched_unpin(); 2942 vm_page_unlock_queues(); 2943 pmap_free_zero_pages(free); 2944} 2945 2946/* 2947 * pmap_protect_pde: do the things to protect a 4mpage in a process 2948 */ 2949static boolean_t 2950pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva, vm_prot_t prot) 2951{ 2952 pd_entry_t newpde, oldpde; 2953 vm_offset_t eva, va; 2954 vm_page_t m; 2955 boolean_t anychanged; 2956 2957 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2958 KASSERT((sva & PDRMASK) == 0, 2959 ("pmap_protect_pde: sva is not 4mpage aligned")); 2960 anychanged = FALSE; 2961retry: 2962 oldpde = newpde = *pde; 2963 if (oldpde & PG_MANAGED) { 2964 eva = sva + NBPDR; 2965 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME); 2966 va < eva; va += PAGE_SIZE, m++) 2967 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW)) 2968 vm_page_dirty(m); 2969 } 2970 if ((prot & VM_PROT_WRITE) == 0) 2971 newpde &= ~(PG_RW | PG_M); 2972#ifdef PAE 2973 if ((prot & VM_PROT_EXECUTE) == 0) 2974 newpde |= pg_nx; 2975#endif 2976 if (newpde != oldpde) { 2977 if (!pde_cmpset(pde, oldpde, newpde)) 2978 goto retry; 2979 if (oldpde & PG_G) 2980 pmap_invalidate_page(pmap, sva); 2981 else 2982 anychanged = TRUE; 2983 } 2984 return (anychanged); 2985} 2986 2987/* 2988 * Set the physical protection on the 2989 * specified range of this map as requested. 2990 */ 2991void 2992pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot) 2993{ 2994 vm_offset_t pdnxt; 2995 pd_entry_t ptpaddr; 2996 pt_entry_t *pte; 2997 int anychanged; 2998 2999 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 3000 pmap_remove(pmap, sva, eva); 3001 return; 3002 } 3003 3004#ifdef PAE 3005 if ((prot & (VM_PROT_WRITE|VM_PROT_EXECUTE)) == 3006 (VM_PROT_WRITE|VM_PROT_EXECUTE)) 3007 return; 3008#else 3009 if (prot & VM_PROT_WRITE) 3010 return; 3011#endif 3012 3013 anychanged = 0; 3014 3015 vm_page_lock_queues(); 3016 sched_pin(); 3017 PMAP_LOCK(pmap); 3018 for (; sva < eva; sva = pdnxt) { 3019 pt_entry_t obits, pbits; 3020 unsigned pdirindex; 3021 3022 pdnxt = (sva + NBPDR) & ~PDRMASK; 3023 if (pdnxt < sva) 3024 pdnxt = eva; 3025 3026 pdirindex = sva >> PDRSHIFT; 3027 ptpaddr = pmap->pm_pdir[pdirindex]; 3028 3029 /* 3030 * Weed out invalid mappings. Note: we assume that the page 3031 * directory table is always allocated, and in kernel virtual. 3032 */ 3033 if (ptpaddr == 0) 3034 continue; 3035 3036 /* 3037 * Check for large page. 3038 */ 3039 if ((ptpaddr & PG_PS) != 0) { 3040 /* 3041 * Are we protecting the entire large page? If not, 3042 * demote the mapping and fall through. 3043 */ 3044 if (sva + NBPDR == pdnxt && eva >= pdnxt) { 3045 /* 3046 * The TLB entry for a PG_G mapping is 3047 * invalidated by pmap_protect_pde(). 3048 */ 3049 if (pmap_protect_pde(pmap, 3050 &pmap->pm_pdir[pdirindex], sva, prot)) 3051 anychanged = 1; 3052 continue; 3053 } else if (!pmap_demote_pde(pmap, 3054 &pmap->pm_pdir[pdirindex], sva)) { 3055 /* The large page mapping was destroyed. */ 3056 continue; 3057 } 3058 } 3059 3060 if (pdnxt > eva) 3061 pdnxt = eva; 3062 3063 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++, 3064 sva += PAGE_SIZE) { 3065 vm_page_t m; 3066 3067retry: 3068 /* 3069 * Regardless of whether a pte is 32 or 64 bits in 3070 * size, PG_RW, PG_A, and PG_M are among the least 3071 * significant 32 bits. 3072 */ 3073 obits = pbits = *pte; 3074 if ((pbits & PG_V) == 0) 3075 continue; 3076 3077 if ((prot & VM_PROT_WRITE) == 0) { 3078 if ((pbits & (PG_MANAGED | PG_M | PG_RW)) == 3079 (PG_MANAGED | PG_M | PG_RW)) { 3080 m = PHYS_TO_VM_PAGE(pbits & PG_FRAME); 3081 vm_page_dirty(m); 3082 } 3083 pbits &= ~(PG_RW | PG_M); 3084 } 3085#ifdef PAE 3086 if ((prot & VM_PROT_EXECUTE) == 0) 3087 pbits |= pg_nx; 3088#endif 3089 3090 if (pbits != obits) { 3091#ifdef PAE 3092 if (!atomic_cmpset_64(pte, obits, pbits)) 3093 goto retry; 3094#else 3095 if (!atomic_cmpset_int((u_int *)pte, obits, 3096 pbits)) 3097 goto retry; 3098#endif 3099 if (obits & PG_G) 3100 pmap_invalidate_page(pmap, sva); 3101 else 3102 anychanged = 1; 3103 } 3104 } 3105 } 3106 sched_unpin(); 3107 if (anychanged) 3108 pmap_invalidate_all(pmap); 3109 vm_page_unlock_queues(); 3110 PMAP_UNLOCK(pmap); 3111} 3112 3113/* 3114 * Tries to promote the 512 or 1024, contiguous 4KB page mappings that are 3115 * within a single page table page (PTP) to a single 2- or 4MB page mapping. 3116 * For promotion to occur, two conditions must be met: (1) the 4KB page 3117 * mappings must map aligned, contiguous physical memory and (2) the 4KB page 3118 * mappings must have identical characteristics. 3119 * 3120 * Managed (PG_MANAGED) mappings within the kernel address space are not 3121 * promoted. The reason is that kernel PDEs are replicated in each pmap but 3122 * pmap_clear_ptes() and pmap_ts_referenced() only read the PDE from the kernel 3123 * pmap. 3124 */ 3125static void 3126pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va) 3127{ 3128 pd_entry_t newpde; 3129 pt_entry_t *firstpte, oldpte, pa, *pte; 3130 vm_offset_t oldpteva; 3131 vm_page_t mpte; 3132 3133 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 3134 3135 /* 3136 * Examine the first PTE in the specified PTP. Abort if this PTE is 3137 * either invalid, unused, or does not map the first 4KB physical page 3138 * within a 2- or 4MB page. 3139 */ 3140 firstpte = pmap_pte_quick(pmap, trunc_4mpage(va)); 3141setpde: 3142 newpde = *firstpte; 3143 if ((newpde & ((PG_FRAME & PDRMASK) | PG_A | PG_V)) != (PG_A | PG_V)) { 3144 pmap_pde_p_failures++; 3145 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x" 3146 " in pmap %p", va, pmap); 3147 return; 3148 } 3149 if ((*firstpte & PG_MANAGED) != 0 && pmap == kernel_pmap) { 3150 pmap_pde_p_failures++; 3151 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x" 3152 " in pmap %p", va, pmap); 3153 return; 3154 } 3155 if ((newpde & (PG_M | PG_RW)) == PG_RW) { 3156 /* 3157 * When PG_M is already clear, PG_RW can be cleared without 3158 * a TLB invalidation. 3159 */ 3160 if (!atomic_cmpset_int((u_int *)firstpte, newpde, newpde & 3161 ~PG_RW)) 3162 goto setpde; 3163 newpde &= ~PG_RW; 3164 } 3165 3166 /* 3167 * Examine each of the other PTEs in the specified PTP. Abort if this 3168 * PTE maps an unexpected 4KB physical page or does not have identical 3169 * characteristics to the first PTE. 3170 */ 3171 pa = (newpde & (PG_PS_FRAME | PG_A | PG_V)) + NBPDR - PAGE_SIZE; 3172 for (pte = firstpte + NPTEPG - 1; pte > firstpte; pte--) { 3173setpte: 3174 oldpte = *pte; 3175 if ((oldpte & (PG_FRAME | PG_A | PG_V)) != pa) { 3176 pmap_pde_p_failures++; 3177 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x" 3178 " in pmap %p", va, pmap); 3179 return; 3180 } 3181 if ((oldpte & (PG_M | PG_RW)) == PG_RW) { 3182 /* 3183 * When PG_M is already clear, PG_RW can be cleared 3184 * without a TLB invalidation. 3185 */ 3186 if (!atomic_cmpset_int((u_int *)pte, oldpte, 3187 oldpte & ~PG_RW)) 3188 goto setpte; 3189 oldpte &= ~PG_RW; 3190 oldpteva = (oldpte & PG_FRAME & PDRMASK) | 3191 (va & ~PDRMASK); 3192 CTR2(KTR_PMAP, "pmap_promote_pde: protect for va %#x" 3193 " in pmap %p", oldpteva, pmap); 3194 } 3195 if ((oldpte & PG_PTE_PROMOTE) != (newpde & PG_PTE_PROMOTE)) { 3196 pmap_pde_p_failures++; 3197 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x" 3198 " in pmap %p", va, pmap); 3199 return; 3200 } 3201 pa -= PAGE_SIZE; 3202 } 3203 3204 /* 3205 * Save the page table page in its current state until the PDE 3206 * mapping the superpage is demoted by pmap_demote_pde() or 3207 * destroyed by pmap_remove_pde(). 3208 */ 3209 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME); 3210 KASSERT(mpte >= vm_page_array && 3211 mpte < &vm_page_array[vm_page_array_size], 3212 ("pmap_promote_pde: page table page is out of range")); 3213 KASSERT(mpte->pindex == va >> PDRSHIFT, 3214 ("pmap_promote_pde: page table page's pindex is wrong")); 3215 pmap_insert_pt_page(pmap, mpte); 3216 3217 /* 3218 * Promote the pv entries. 3219 */ 3220 if ((newpde & PG_MANAGED) != 0) 3221 pmap_pv_promote_pde(pmap, va, newpde & PG_PS_FRAME); 3222 3223 /* 3224 * Propagate the PAT index to its proper position. 3225 */ 3226 if ((newpde & PG_PTE_PAT) != 0) 3227 newpde ^= PG_PDE_PAT | PG_PTE_PAT; 3228 3229 /* 3230 * Map the superpage. 3231 */ 3232 if (workaround_erratum383) 3233 pmap_update_pde(pmap, va, pde, PG_PS | newpde); 3234 else if (pmap == kernel_pmap) 3235 pmap_kenter_pde(va, PG_PS | newpde); 3236 else 3237 pde_store(pde, PG_PS | newpde); 3238 3239 pmap_pde_promotions++; 3240 CTR2(KTR_PMAP, "pmap_promote_pde: success for va %#x" 3241 " in pmap %p", va, pmap); 3242} 3243 3244/* 3245 * Insert the given physical page (p) at 3246 * the specified virtual address (v) in the 3247 * target physical map with the protection requested. 3248 * 3249 * If specified, the page will be wired down, meaning 3250 * that the related pte can not be reclaimed. 3251 * 3252 * NB: This is the only routine which MAY NOT lazy-evaluate 3253 * or lose information. That is, this routine must actually 3254 * insert this page into the given map NOW. 3255 */ 3256void 3257pmap_enter(pmap_t pmap, vm_offset_t va, vm_prot_t access, vm_page_t m, 3258 vm_prot_t prot, boolean_t wired) 3259{ 3260 pd_entry_t *pde; 3261 pt_entry_t *pte; 3262 pt_entry_t newpte, origpte; 3263 pv_entry_t pv; 3264 vm_paddr_t opa, pa; 3265 vm_page_t mpte, om; 3266 boolean_t invlva; 3267 3268 va = trunc_page(va); 3269 KASSERT(va <= VM_MAX_KERNEL_ADDRESS, ("pmap_enter: toobig")); 3270 KASSERT(va < UPT_MIN_ADDRESS || va >= UPT_MAX_ADDRESS, 3271 ("pmap_enter: invalid to pmap_enter page table pages (va: 0x%x)", 3272 va)); 3273 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0 || 3274 (m->oflags & VPO_BUSY) != 0, 3275 ("pmap_enter: page %p is not busy", m)); 3276 3277 mpte = NULL; 3278 3279 vm_page_lock_queues(); 3280 PMAP_LOCK(pmap); 3281 sched_pin(); 3282 3283 /* 3284 * In the case that a page table page is not 3285 * resident, we are creating it here. 3286 */ 3287 if (va < VM_MAXUSER_ADDRESS) { 3288 mpte = pmap_allocpte(pmap, va, M_WAITOK); 3289 } 3290 3291 pde = pmap_pde(pmap, va); 3292 if ((*pde & PG_PS) != 0) 3293 panic("pmap_enter: attempted pmap_enter on 4MB page"); 3294 pte = pmap_pte_quick(pmap, va); 3295 3296 /* 3297 * Page Directory table entry not valid, we need a new PT page 3298 */ 3299 if (pte == NULL) { 3300 panic("pmap_enter: invalid page directory pdir=%#jx, va=%#x", 3301 (uintmax_t)pmap->pm_pdir[PTDPTDI], va); 3302 } 3303 3304 pa = VM_PAGE_TO_PHYS(m); 3305 om = NULL; 3306 origpte = *pte; 3307 opa = origpte & PG_FRAME; 3308 3309 /* 3310 * Mapping has not changed, must be protection or wiring change. 3311 */ 3312 if (origpte && (opa == pa)) { 3313 /* 3314 * Wiring change, just update stats. We don't worry about 3315 * wiring PT pages as they remain resident as long as there 3316 * are valid mappings in them. Hence, if a user page is wired, 3317 * the PT page will be also. 3318 */ 3319 if (wired && ((origpte & PG_W) == 0)) 3320 pmap->pm_stats.wired_count++; 3321 else if (!wired && (origpte & PG_W)) 3322 pmap->pm_stats.wired_count--; 3323 3324 /* 3325 * Remove extra pte reference 3326 */ 3327 if (mpte) 3328 mpte->wire_count--; 3329 3330 if (origpte & PG_MANAGED) { 3331 om = m; 3332 pa |= PG_MANAGED; 3333 } 3334 goto validate; 3335 } 3336 3337 pv = NULL; 3338 3339 /* 3340 * Mapping has changed, invalidate old range and fall through to 3341 * handle validating new mapping. 3342 */ 3343 if (opa) { 3344 if (origpte & PG_W) 3345 pmap->pm_stats.wired_count--; 3346 if (origpte & PG_MANAGED) { 3347 om = PHYS_TO_VM_PAGE(opa); 3348 pv = pmap_pvh_remove(&om->md, pmap, va); 3349 } 3350 if (mpte != NULL) { 3351 mpte->wire_count--; 3352 KASSERT(mpte->wire_count > 0, 3353 ("pmap_enter: missing reference to page table page," 3354 " va: 0x%x", va)); 3355 } 3356 } else 3357 pmap->pm_stats.resident_count++; 3358 3359 /* 3360 * Enter on the PV list if part of our managed memory. 3361 */ 3362 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0) { 3363 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva, 3364 ("pmap_enter: managed mapping within the clean submap")); 3365 if (pv == NULL) 3366 pv = get_pv_entry(pmap, FALSE); 3367 pv->pv_va = va; 3368 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list); 3369 pa |= PG_MANAGED; 3370 } else if (pv != NULL) 3371 free_pv_entry(pmap, pv); 3372 3373 /* 3374 * Increment counters 3375 */ 3376 if (wired) 3377 pmap->pm_stats.wired_count++; 3378 3379validate: 3380 /* 3381 * Now validate mapping with desired protection/wiring. 3382 */ 3383 newpte = (pt_entry_t)(pa | pmap_cache_bits(m->md.pat_mode, 0) | PG_V); 3384 if ((prot & VM_PROT_WRITE) != 0) { 3385 newpte |= PG_RW; 3386 if ((newpte & PG_MANAGED) != 0) 3387 vm_page_flag_set(m, PG_WRITEABLE); 3388 } 3389#ifdef PAE 3390 if ((prot & VM_PROT_EXECUTE) == 0) 3391 newpte |= pg_nx; 3392#endif 3393 if (wired) 3394 newpte |= PG_W; 3395 if (va < VM_MAXUSER_ADDRESS) 3396 newpte |= PG_U; 3397 if (pmap == kernel_pmap) 3398 newpte |= pgeflag; 3399 3400 /* 3401 * if the mapping or permission bits are different, we need 3402 * to update the pte. 3403 */ 3404 if ((origpte & ~(PG_M|PG_A)) != newpte) { 3405 newpte |= PG_A; 3406 if ((access & VM_PROT_WRITE) != 0) 3407 newpte |= PG_M; 3408 if (origpte & PG_V) { 3409 invlva = FALSE; 3410 origpte = pte_load_store(pte, newpte); 3411 if (origpte & PG_A) { 3412 if (origpte & PG_MANAGED) 3413 vm_page_flag_set(om, PG_REFERENCED); 3414 if (opa != VM_PAGE_TO_PHYS(m)) 3415 invlva = TRUE; 3416#ifdef PAE 3417 if ((origpte & PG_NX) == 0 && 3418 (newpte & PG_NX) != 0) 3419 invlva = TRUE; 3420#endif 3421 } 3422 if ((origpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) { 3423 if ((origpte & PG_MANAGED) != 0) 3424 vm_page_dirty(om); 3425 if ((prot & VM_PROT_WRITE) == 0) 3426 invlva = TRUE; 3427 } 3428 if ((origpte & PG_MANAGED) != 0 && 3429 TAILQ_EMPTY(&om->md.pv_list) && 3430 TAILQ_EMPTY(&pa_to_pvh(opa)->pv_list)) 3431 vm_page_flag_clear(om, PG_WRITEABLE); 3432 if (invlva) 3433 pmap_invalidate_page(pmap, va); 3434 } else 3435 pte_store(pte, newpte); 3436 } 3437 3438 /* 3439 * If both the page table page and the reservation are fully 3440 * populated, then attempt promotion. 3441 */ 3442 if ((mpte == NULL || mpte->wire_count == NPTEPG) && 3443 pg_ps_enabled && vm_reserv_level_iffullpop(m) == 0) 3444 pmap_promote_pde(pmap, pde, va); 3445 3446 sched_unpin(); 3447 vm_page_unlock_queues(); 3448 PMAP_UNLOCK(pmap); 3449} 3450 3451/* 3452 * Tries to create a 2- or 4MB page mapping. Returns TRUE if successful and 3453 * FALSE otherwise. Fails if (1) a page table page cannot be allocated without 3454 * blocking, (2) a mapping already exists at the specified virtual address, or 3455 * (3) a pv entry cannot be allocated without reclaiming another pv entry. 3456 */ 3457static boolean_t 3458pmap_enter_pde(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot) 3459{ 3460 pd_entry_t *pde, newpde; 3461 3462 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 3463 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 3464 pde = pmap_pde(pmap, va); 3465 if (*pde != 0) { 3466 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx" 3467 " in pmap %p", va, pmap); 3468 return (FALSE); 3469 } 3470 newpde = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(m->md.pat_mode, 1) | 3471 PG_PS | PG_V; 3472 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0) { 3473 newpde |= PG_MANAGED; 3474 3475 /* 3476 * Abort this mapping if its PV entry could not be created. 3477 */ 3478 if (!pmap_pv_insert_pde(pmap, va, VM_PAGE_TO_PHYS(m))) { 3479 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx" 3480 " in pmap %p", va, pmap); 3481 return (FALSE); 3482 } 3483 } 3484#ifdef PAE 3485 if ((prot & VM_PROT_EXECUTE) == 0) 3486 newpde |= pg_nx; 3487#endif 3488 if (va < VM_MAXUSER_ADDRESS) 3489 newpde |= PG_U; 3490 3491 /* 3492 * Increment counters. 3493 */ 3494 pmap->pm_stats.resident_count += NBPDR / PAGE_SIZE; 3495 3496 /* 3497 * Map the superpage. 3498 */ 3499 pde_store(pde, newpde); 3500 3501 pmap_pde_mappings++; 3502 CTR2(KTR_PMAP, "pmap_enter_pde: success for va %#lx" 3503 " in pmap %p", va, pmap); 3504 return (TRUE); 3505} 3506 3507/* 3508 * Maps a sequence of resident pages belonging to the same object. 3509 * The sequence begins with the given page m_start. This page is 3510 * mapped at the given virtual address start. Each subsequent page is 3511 * mapped at a virtual address that is offset from start by the same 3512 * amount as the page is offset from m_start within the object. The 3513 * last page in the sequence is the page with the largest offset from 3514 * m_start that can be mapped at a virtual address less than the given 3515 * virtual address end. Not every virtual page between start and end 3516 * is mapped; only those for which a resident page exists with the 3517 * corresponding offset from m_start are mapped. 3518 */ 3519void 3520pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end, 3521 vm_page_t m_start, vm_prot_t prot) 3522{ 3523 vm_offset_t va; 3524 vm_page_t m, mpte; 3525 vm_pindex_t diff, psize; 3526 3527 VM_OBJECT_LOCK_ASSERT(m_start->object, MA_OWNED); 3528 psize = atop(end - start); 3529 mpte = NULL; 3530 m = m_start; 3531 vm_page_lock_queues(); 3532 PMAP_LOCK(pmap); 3533 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 3534 va = start + ptoa(diff); 3535 if ((va & PDRMASK) == 0 && va + NBPDR <= end && 3536 (VM_PAGE_TO_PHYS(m) & PDRMASK) == 0 && 3537 pg_ps_enabled && vm_reserv_level_iffullpop(m) == 0 && 3538 pmap_enter_pde(pmap, va, m, prot)) 3539 m = &m[NBPDR / PAGE_SIZE - 1]; 3540 else 3541 mpte = pmap_enter_quick_locked(pmap, va, m, prot, 3542 mpte); 3543 m = TAILQ_NEXT(m, listq); 3544 } 3545 vm_page_unlock_queues(); 3546 PMAP_UNLOCK(pmap); 3547} 3548 3549/* 3550 * this code makes some *MAJOR* assumptions: 3551 * 1. Current pmap & pmap exists. 3552 * 2. Not wired. 3553 * 3. Read access. 3554 * 4. No page table pages. 3555 * but is *MUCH* faster than pmap_enter... 3556 */ 3557 3558void 3559pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot) 3560{ 3561 3562 vm_page_lock_queues(); 3563 PMAP_LOCK(pmap); 3564 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL); 3565 vm_page_unlock_queues(); 3566 PMAP_UNLOCK(pmap); 3567} 3568 3569static vm_page_t 3570pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m, 3571 vm_prot_t prot, vm_page_t mpte) 3572{ 3573 pt_entry_t *pte; 3574 vm_paddr_t pa; 3575 vm_page_t free; 3576 3577 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva || 3578 (m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0, 3579 ("pmap_enter_quick_locked: managed mapping within the clean submap")); 3580 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 3581 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 3582 3583 /* 3584 * In the case that a page table page is not 3585 * resident, we are creating it here. 3586 */ 3587 if (va < VM_MAXUSER_ADDRESS) { 3588 unsigned ptepindex; 3589 pd_entry_t ptepa; 3590 3591 /* 3592 * Calculate pagetable page index 3593 */ 3594 ptepindex = va >> PDRSHIFT; 3595 if (mpte && (mpte->pindex == ptepindex)) { 3596 mpte->wire_count++; 3597 } else { 3598 /* 3599 * Get the page directory entry 3600 */ 3601 ptepa = pmap->pm_pdir[ptepindex]; 3602 3603 /* 3604 * If the page table page is mapped, we just increment 3605 * the hold count, and activate it. 3606 */ 3607 if (ptepa) { 3608 if (ptepa & PG_PS) 3609 return (NULL); 3610 mpte = PHYS_TO_VM_PAGE(ptepa & PG_FRAME); 3611 mpte->wire_count++; 3612 } else { 3613 mpte = _pmap_allocpte(pmap, ptepindex, 3614 M_NOWAIT); 3615 if (mpte == NULL) 3616 return (mpte); 3617 } 3618 } 3619 } else { 3620 mpte = NULL; 3621 } 3622 3623 /* 3624 * This call to vtopte makes the assumption that we are 3625 * entering the page into the current pmap. In order to support 3626 * quick entry into any pmap, one would likely use pmap_pte_quick. 3627 * But that isn't as quick as vtopte. 3628 */ 3629 pte = vtopte(va); 3630 if (*pte) { 3631 if (mpte != NULL) { 3632 mpte->wire_count--; 3633 mpte = NULL; 3634 } 3635 return (mpte); 3636 } 3637 3638 /* 3639 * Enter on the PV list if part of our managed memory. 3640 */ 3641 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0 && 3642 !pmap_try_insert_pv_entry(pmap, va, m)) { 3643 if (mpte != NULL) { 3644 free = NULL; 3645 if (pmap_unwire_pte_hold(pmap, mpte, &free)) { 3646 pmap_invalidate_page(pmap, va); 3647 pmap_free_zero_pages(free); 3648 } 3649 3650 mpte = NULL; 3651 } 3652 return (mpte); 3653 } 3654 3655 /* 3656 * Increment counters 3657 */ 3658 pmap->pm_stats.resident_count++; 3659 3660 pa = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(m->md.pat_mode, 0); 3661#ifdef PAE 3662 if ((prot & VM_PROT_EXECUTE) == 0) 3663 pa |= pg_nx; 3664#endif 3665 3666 /* 3667 * Now validate mapping with RO protection 3668 */ 3669 if (m->flags & (PG_FICTITIOUS|PG_UNMANAGED)) 3670 pte_store(pte, pa | PG_V | PG_U); 3671 else 3672 pte_store(pte, pa | PG_V | PG_U | PG_MANAGED); 3673 return (mpte); 3674} 3675 3676/* 3677 * Make a temporary mapping for a physical address. This is only intended 3678 * to be used for panic dumps. 3679 */ 3680void * 3681pmap_kenter_temporary(vm_paddr_t pa, int i) 3682{ 3683 vm_offset_t va; 3684 3685 va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE); 3686 pmap_kenter(va, pa); 3687 invlpg(va); 3688 return ((void *)crashdumpmap); 3689} 3690 3691/* 3692 * This code maps large physical mmap regions into the 3693 * processor address space. Note that some shortcuts 3694 * are taken, but the code works. 3695 */ 3696void 3697pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object, 3698 vm_pindex_t pindex, vm_size_t size) 3699{ 3700 pd_entry_t *pde; 3701 vm_paddr_t pa, ptepa; 3702 vm_page_t p; 3703 int pat_mode; 3704 3705 VM_OBJECT_LOCK_ASSERT(object, MA_OWNED); 3706 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG, 3707 ("pmap_object_init_pt: non-device object")); 3708 if (pseflag && 3709 (addr & (NBPDR - 1)) == 0 && (size & (NBPDR - 1)) == 0) { 3710 if (!vm_object_populate(object, pindex, pindex + atop(size))) 3711 return; 3712 p = vm_page_lookup(object, pindex); 3713 KASSERT(p->valid == VM_PAGE_BITS_ALL, 3714 ("pmap_object_init_pt: invalid page %p", p)); 3715 pat_mode = p->md.pat_mode; 3716 3717 /* 3718 * Abort the mapping if the first page is not physically 3719 * aligned to a 2/4MB page boundary. 3720 */ 3721 ptepa = VM_PAGE_TO_PHYS(p); 3722 if (ptepa & (NBPDR - 1)) 3723 return; 3724 3725 /* 3726 * Skip the first page. Abort the mapping if the rest of 3727 * the pages are not physically contiguous or have differing 3728 * memory attributes. 3729 */ 3730 p = TAILQ_NEXT(p, listq); 3731 for (pa = ptepa + PAGE_SIZE; pa < ptepa + size; 3732 pa += PAGE_SIZE) { 3733 KASSERT(p->valid == VM_PAGE_BITS_ALL, 3734 ("pmap_object_init_pt: invalid page %p", p)); 3735 if (pa != VM_PAGE_TO_PHYS(p) || 3736 pat_mode != p->md.pat_mode) 3737 return; 3738 p = TAILQ_NEXT(p, listq); 3739 } 3740 3741 /* 3742 * Map using 2/4MB pages. Since "ptepa" is 2/4M aligned and 3743 * "size" is a multiple of 2/4M, adding the PAT setting to 3744 * "pa" will not affect the termination of this loop. 3745 */ 3746 PMAP_LOCK(pmap); 3747 for (pa = ptepa | pmap_cache_bits(pat_mode, 1); pa < ptepa + 3748 size; pa += NBPDR) { 3749 pde = pmap_pde(pmap, addr); 3750 if (*pde == 0) { 3751 pde_store(pde, pa | PG_PS | PG_M | PG_A | 3752 PG_U | PG_RW | PG_V); 3753 pmap->pm_stats.resident_count += NBPDR / 3754 PAGE_SIZE; 3755 pmap_pde_mappings++; 3756 } 3757 /* Else continue on if the PDE is already valid. */ 3758 addr += NBPDR; 3759 } 3760 PMAP_UNLOCK(pmap); 3761 } 3762} 3763 3764/* 3765 * Routine: pmap_change_wiring 3766 * Function: Change the wiring attribute for a map/virtual-address 3767 * pair. 3768 * In/out conditions: 3769 * The mapping must already exist in the pmap. 3770 */ 3771void 3772pmap_change_wiring(pmap_t pmap, vm_offset_t va, boolean_t wired) 3773{ 3774 pd_entry_t *pde; 3775 pt_entry_t *pte; 3776 boolean_t are_queues_locked; 3777 3778 are_queues_locked = FALSE; 3779retry: 3780 PMAP_LOCK(pmap); 3781 pde = pmap_pde(pmap, va); 3782 if ((*pde & PG_PS) != 0) { 3783 if (!wired != ((*pde & PG_W) == 0)) { 3784 if (!are_queues_locked) { 3785 are_queues_locked = TRUE; 3786 if (!mtx_trylock(&vm_page_queue_mtx)) { 3787 PMAP_UNLOCK(pmap); 3788 vm_page_lock_queues(); 3789 goto retry; 3790 } 3791 } 3792 if (!pmap_demote_pde(pmap, pde, va)) 3793 panic("pmap_change_wiring: demotion failed"); 3794 } else 3795 goto out; 3796 } 3797 pte = pmap_pte(pmap, va); 3798 3799 if (wired && !pmap_pte_w(pte)) 3800 pmap->pm_stats.wired_count++; 3801 else if (!wired && pmap_pte_w(pte)) 3802 pmap->pm_stats.wired_count--; 3803 3804 /* 3805 * Wiring is not a hardware characteristic so there is no need to 3806 * invalidate TLB. 3807 */ 3808 pmap_pte_set_w(pte, wired); 3809 pmap_pte_release(pte); 3810out: 3811 if (are_queues_locked) 3812 vm_page_unlock_queues(); 3813 PMAP_UNLOCK(pmap); 3814} 3815 3816 3817 3818/* 3819 * Copy the range specified by src_addr/len 3820 * from the source map to the range dst_addr/len 3821 * in the destination map. 3822 * 3823 * This routine is only advisory and need not do anything. 3824 */ 3825 3826void 3827pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len, 3828 vm_offset_t src_addr) 3829{ 3830 vm_page_t free; 3831 vm_offset_t addr; 3832 vm_offset_t end_addr = src_addr + len; 3833 vm_offset_t pdnxt; 3834 3835 if (dst_addr != src_addr) 3836 return; 3837 3838 if (!pmap_is_current(src_pmap)) 3839 return; 3840 3841 vm_page_lock_queues(); 3842 if (dst_pmap < src_pmap) { 3843 PMAP_LOCK(dst_pmap); 3844 PMAP_LOCK(src_pmap); 3845 } else { 3846 PMAP_LOCK(src_pmap); 3847 PMAP_LOCK(dst_pmap); 3848 } 3849 sched_pin(); 3850 for (addr = src_addr; addr < end_addr; addr = pdnxt) { 3851 pt_entry_t *src_pte, *dst_pte; 3852 vm_page_t dstmpte, srcmpte; 3853 pd_entry_t srcptepaddr; 3854 unsigned ptepindex; 3855 3856 KASSERT(addr < UPT_MIN_ADDRESS, 3857 ("pmap_copy: invalid to pmap_copy page tables")); 3858 3859 pdnxt = (addr + NBPDR) & ~PDRMASK; 3860 if (pdnxt < addr) 3861 pdnxt = end_addr; 3862 ptepindex = addr >> PDRSHIFT; 3863 3864 srcptepaddr = src_pmap->pm_pdir[ptepindex]; 3865 if (srcptepaddr == 0) 3866 continue; 3867 3868 if (srcptepaddr & PG_PS) { 3869 if (dst_pmap->pm_pdir[ptepindex] == 0 && 3870 ((srcptepaddr & PG_MANAGED) == 0 || 3871 pmap_pv_insert_pde(dst_pmap, addr, srcptepaddr & 3872 PG_PS_FRAME))) { 3873 dst_pmap->pm_pdir[ptepindex] = srcptepaddr & 3874 ~PG_W; 3875 dst_pmap->pm_stats.resident_count += 3876 NBPDR / PAGE_SIZE; 3877 } 3878 continue; 3879 } 3880 3881 srcmpte = PHYS_TO_VM_PAGE(srcptepaddr & PG_FRAME); 3882 KASSERT(srcmpte->wire_count > 0, 3883 ("pmap_copy: source page table page is unused")); 3884 3885 if (pdnxt > end_addr) 3886 pdnxt = end_addr; 3887 3888 src_pte = vtopte(addr); 3889 while (addr < pdnxt) { 3890 pt_entry_t ptetemp; 3891 ptetemp = *src_pte; 3892 /* 3893 * we only virtual copy managed pages 3894 */ 3895 if ((ptetemp & PG_MANAGED) != 0) { 3896 dstmpte = pmap_allocpte(dst_pmap, addr, 3897 M_NOWAIT); 3898 if (dstmpte == NULL) 3899 goto out; 3900 dst_pte = pmap_pte_quick(dst_pmap, addr); 3901 if (*dst_pte == 0 && 3902 pmap_try_insert_pv_entry(dst_pmap, addr, 3903 PHYS_TO_VM_PAGE(ptetemp & PG_FRAME))) { 3904 /* 3905 * Clear the wired, modified, and 3906 * accessed (referenced) bits 3907 * during the copy. 3908 */ 3909 *dst_pte = ptetemp & ~(PG_W | PG_M | 3910 PG_A); 3911 dst_pmap->pm_stats.resident_count++; 3912 } else { 3913 free = NULL; 3914 if (pmap_unwire_pte_hold(dst_pmap, 3915 dstmpte, &free)) { 3916 pmap_invalidate_page(dst_pmap, 3917 addr); 3918 pmap_free_zero_pages(free); 3919 } 3920 goto out; 3921 } 3922 if (dstmpte->wire_count >= srcmpte->wire_count) 3923 break; 3924 } 3925 addr += PAGE_SIZE; 3926 src_pte++; 3927 } 3928 } 3929out: 3930 sched_unpin(); 3931 vm_page_unlock_queues(); 3932 PMAP_UNLOCK(src_pmap); 3933 PMAP_UNLOCK(dst_pmap); 3934} 3935 3936static __inline void 3937pagezero(void *page) 3938{ 3939#if defined(I686_CPU) 3940 if (cpu_class == CPUCLASS_686) { 3941#if defined(CPU_ENABLE_SSE) 3942 if (cpu_feature & CPUID_SSE2) 3943 sse2_pagezero(page); 3944 else 3945#endif 3946 i686_pagezero(page); 3947 } else 3948#endif 3949 bzero(page, PAGE_SIZE); 3950} 3951 3952/* 3953 * pmap_zero_page zeros the specified hardware page by mapping 3954 * the page into KVM and using bzero to clear its contents. 3955 */ 3956void 3957pmap_zero_page(vm_page_t m) 3958{ 3959 struct sysmaps *sysmaps; 3960 3961 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)]; 3962 mtx_lock(&sysmaps->lock); 3963 if (*sysmaps->CMAP2) 3964 panic("pmap_zero_page: CMAP2 busy"); 3965 sched_pin(); 3966 *sysmaps->CMAP2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M | 3967 pmap_cache_bits(m->md.pat_mode, 0); 3968 invlcaddr(sysmaps->CADDR2); 3969 pagezero(sysmaps->CADDR2); 3970 *sysmaps->CMAP2 = 0; 3971 sched_unpin(); 3972 mtx_unlock(&sysmaps->lock); 3973} 3974 3975/* 3976 * pmap_zero_page_area zeros the specified hardware page by mapping 3977 * the page into KVM and using bzero to clear its contents. 3978 * 3979 * off and size may not cover an area beyond a single hardware page. 3980 */ 3981void 3982pmap_zero_page_area(vm_page_t m, int off, int size) 3983{ 3984 struct sysmaps *sysmaps; 3985 3986 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)]; 3987 mtx_lock(&sysmaps->lock); 3988 if (*sysmaps->CMAP2) 3989 panic("pmap_zero_page_area: CMAP2 busy"); 3990 sched_pin(); 3991 *sysmaps->CMAP2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M | 3992 pmap_cache_bits(m->md.pat_mode, 0); 3993 invlcaddr(sysmaps->CADDR2); 3994 if (off == 0 && size == PAGE_SIZE) 3995 pagezero(sysmaps->CADDR2); 3996 else 3997 bzero((char *)sysmaps->CADDR2 + off, size); 3998 *sysmaps->CMAP2 = 0; 3999 sched_unpin(); 4000 mtx_unlock(&sysmaps->lock); 4001} 4002 4003/* 4004 * pmap_zero_page_idle zeros the specified hardware page by mapping 4005 * the page into KVM and using bzero to clear its contents. This 4006 * is intended to be called from the vm_pagezero process only and 4007 * outside of Giant. 4008 */ 4009void 4010pmap_zero_page_idle(vm_page_t m) 4011{ 4012 4013 if (*CMAP3) 4014 panic("pmap_zero_page_idle: CMAP3 busy"); 4015 sched_pin(); 4016 *CMAP3 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M | 4017 pmap_cache_bits(m->md.pat_mode, 0); 4018 invlcaddr(CADDR3); 4019 pagezero(CADDR3); 4020 *CMAP3 = 0; 4021 sched_unpin(); 4022} 4023 4024/* 4025 * pmap_copy_page copies the specified (machine independent) 4026 * page by mapping the page into virtual memory and using 4027 * bcopy to copy the page, one machine dependent page at a 4028 * time. 4029 */ 4030void 4031pmap_copy_page(vm_page_t src, vm_page_t dst) 4032{ 4033 struct sysmaps *sysmaps; 4034 4035 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)]; 4036 mtx_lock(&sysmaps->lock); 4037 if (*sysmaps->CMAP1) 4038 panic("pmap_copy_page: CMAP1 busy"); 4039 if (*sysmaps->CMAP2) 4040 panic("pmap_copy_page: CMAP2 busy"); 4041 sched_pin(); 4042 invlpg((u_int)sysmaps->CADDR1); 4043 invlpg((u_int)sysmaps->CADDR2); 4044 *sysmaps->CMAP1 = PG_V | VM_PAGE_TO_PHYS(src) | PG_A | 4045 pmap_cache_bits(src->md.pat_mode, 0); 4046 *sysmaps->CMAP2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(dst) | PG_A | PG_M | 4047 pmap_cache_bits(dst->md.pat_mode, 0); 4048 bcopy(sysmaps->CADDR1, sysmaps->CADDR2, PAGE_SIZE); 4049 *sysmaps->CMAP1 = 0; 4050 *sysmaps->CMAP2 = 0; 4051 sched_unpin(); 4052 mtx_unlock(&sysmaps->lock); 4053} 4054 4055/* 4056 * Returns true if the pmap's pv is one of the first 4057 * 16 pvs linked to from this page. This count may 4058 * be changed upwards or downwards in the future; it 4059 * is only necessary that true be returned for a small 4060 * subset of pmaps for proper page aging. 4061 */ 4062boolean_t 4063pmap_page_exists_quick(pmap_t pmap, vm_page_t m) 4064{ 4065 struct md_page *pvh; 4066 pv_entry_t pv; 4067 int loops = 0; 4068 boolean_t rv; 4069 4070 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 4071 ("pmap_page_exists_quick: page %p is not managed", m)); 4072 rv = FALSE; 4073 vm_page_lock_queues(); 4074 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 4075 if (PV_PMAP(pv) == pmap) { 4076 rv = TRUE; 4077 break; 4078 } 4079 loops++; 4080 if (loops >= 16) 4081 break; 4082 } 4083 if (!rv && loops < 16) { 4084 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 4085 TAILQ_FOREACH(pv, &pvh->pv_list, pv_list) { 4086 if (PV_PMAP(pv) == pmap) { 4087 rv = TRUE; 4088 break; 4089 } 4090 loops++; 4091 if (loops >= 16) 4092 break; 4093 } 4094 } 4095 vm_page_unlock_queues(); 4096 return (rv); 4097} 4098 4099/* 4100 * pmap_page_wired_mappings: 4101 * 4102 * Return the number of managed mappings to the given physical page 4103 * that are wired. 4104 */ 4105int 4106pmap_page_wired_mappings(vm_page_t m) 4107{ 4108 int count; 4109 4110 count = 0; 4111 if ((m->flags & PG_FICTITIOUS) != 0) 4112 return (count); 4113 vm_page_lock_queues(); 4114 count = pmap_pvh_wired_mappings(&m->md, count); 4115 count = pmap_pvh_wired_mappings(pa_to_pvh(VM_PAGE_TO_PHYS(m)), count); 4116 vm_page_unlock_queues(); 4117 return (count); 4118} 4119 4120/* 4121 * pmap_pvh_wired_mappings: 4122 * 4123 * Return the updated number "count" of managed mappings that are wired. 4124 */ 4125static int 4126pmap_pvh_wired_mappings(struct md_page *pvh, int count) 4127{ 4128 pmap_t pmap; 4129 pt_entry_t *pte; 4130 pv_entry_t pv; 4131 4132 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 4133 sched_pin(); 4134 TAILQ_FOREACH(pv, &pvh->pv_list, pv_list) { 4135 pmap = PV_PMAP(pv); 4136 PMAP_LOCK(pmap); 4137 pte = pmap_pte_quick(pmap, pv->pv_va); 4138 if ((*pte & PG_W) != 0) 4139 count++; 4140 PMAP_UNLOCK(pmap); 4141 } 4142 sched_unpin(); 4143 return (count); 4144} 4145 4146/* 4147 * Returns TRUE if the given page is mapped individually or as part of 4148 * a 4mpage. Otherwise, returns FALSE. 4149 */ 4150boolean_t 4151pmap_page_is_mapped(vm_page_t m) 4152{ 4153 boolean_t rv; 4154 4155 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0) 4156 return (FALSE); 4157 vm_page_lock_queues(); 4158 rv = !TAILQ_EMPTY(&m->md.pv_list) || 4159 !TAILQ_EMPTY(&pa_to_pvh(VM_PAGE_TO_PHYS(m))->pv_list); 4160 vm_page_unlock_queues(); 4161 return (rv); 4162} 4163 4164/* 4165 * Remove all pages from specified address space 4166 * this aids process exit speeds. Also, this code 4167 * is special cased for current process only, but 4168 * can have the more generic (and slightly slower) 4169 * mode enabled. This is much faster than pmap_remove 4170 * in the case of running down an entire address space. 4171 */ 4172void 4173pmap_remove_pages(pmap_t pmap) 4174{ 4175 pt_entry_t *pte, tpte; 4176 vm_page_t free = NULL; 4177 vm_page_t m, mpte, mt; 4178 pv_entry_t pv; 4179 struct md_page *pvh; 4180 struct pv_chunk *pc, *npc; 4181 int field, idx; 4182 int32_t bit; 4183 uint32_t inuse, bitmask; 4184 int allfree; 4185 4186 if (pmap != PCPU_GET(curpmap)) { 4187 printf("warning: pmap_remove_pages called with non-current pmap\n"); 4188 return; 4189 } 4190 vm_page_lock_queues(); 4191 PMAP_LOCK(pmap); 4192 sched_pin(); 4193 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) { 4194 allfree = 1; 4195 for (field = 0; field < _NPCM; field++) { 4196 inuse = (~(pc->pc_map[field])) & pc_freemask[field]; 4197 while (inuse != 0) { 4198 bit = bsfl(inuse); 4199 bitmask = 1UL << bit; 4200 idx = field * 32 + bit; 4201 pv = &pc->pc_pventry[idx]; 4202 inuse &= ~bitmask; 4203 4204 pte = pmap_pde(pmap, pv->pv_va); 4205 tpte = *pte; 4206 if ((tpte & PG_PS) == 0) { 4207 pte = vtopte(pv->pv_va); 4208 tpte = *pte & ~PG_PTE_PAT; 4209 } 4210 4211 if (tpte == 0) { 4212 printf( 4213 "TPTE at %p IS ZERO @ VA %08x\n", 4214 pte, pv->pv_va); 4215 panic("bad pte"); 4216 } 4217 4218/* 4219 * We cannot remove wired pages from a process' mapping at this time 4220 */ 4221 if (tpte & PG_W) { 4222 allfree = 0; 4223 continue; 4224 } 4225 4226 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME); 4227 KASSERT(m->phys_addr == (tpte & PG_FRAME), 4228 ("vm_page_t %p phys_addr mismatch %016jx %016jx", 4229 m, (uintmax_t)m->phys_addr, 4230 (uintmax_t)tpte)); 4231 4232 KASSERT(m < &vm_page_array[vm_page_array_size], 4233 ("pmap_remove_pages: bad tpte %#jx", 4234 (uintmax_t)tpte)); 4235 4236 pte_clear(pte); 4237 4238 /* 4239 * Update the vm_page_t clean/reference bits. 4240 */ 4241 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) { 4242 if ((tpte & PG_PS) != 0) { 4243 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++) 4244 vm_page_dirty(mt); 4245 } else 4246 vm_page_dirty(m); 4247 } 4248 4249 /* Mark free */ 4250 PV_STAT(pv_entry_frees++); 4251 PV_STAT(pv_entry_spare++); 4252 pv_entry_count--; 4253 pc->pc_map[field] |= bitmask; 4254 if ((tpte & PG_PS) != 0) { 4255 pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE; 4256 pvh = pa_to_pvh(tpte & PG_PS_FRAME); 4257 TAILQ_REMOVE(&pvh->pv_list, pv, pv_list); 4258 if (TAILQ_EMPTY(&pvh->pv_list)) { 4259 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++) 4260 if (TAILQ_EMPTY(&mt->md.pv_list)) 4261 vm_page_flag_clear(mt, PG_WRITEABLE); 4262 } 4263 mpte = pmap_lookup_pt_page(pmap, pv->pv_va); 4264 if (mpte != NULL) { 4265 pmap_remove_pt_page(pmap, mpte); 4266 pmap->pm_stats.resident_count--; 4267 KASSERT(mpte->wire_count == NPTEPG, 4268 ("pmap_remove_pages: pte page wire count error")); 4269 mpte->wire_count = 0; 4270 pmap_add_delayed_free_list(mpte, &free, FALSE); 4271 atomic_subtract_int(&cnt.v_wire_count, 1); 4272 } 4273 } else { 4274 pmap->pm_stats.resident_count--; 4275 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list); 4276 if (TAILQ_EMPTY(&m->md.pv_list)) { 4277 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 4278 if (TAILQ_EMPTY(&pvh->pv_list)) 4279 vm_page_flag_clear(m, PG_WRITEABLE); 4280 } 4281 pmap_unuse_pt(pmap, pv->pv_va, &free); 4282 } 4283 } 4284 } 4285 if (allfree) { 4286 PV_STAT(pv_entry_spare -= _NPCPV); 4287 PV_STAT(pc_chunk_count--); 4288 PV_STAT(pc_chunk_frees++); 4289 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 4290 m = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc)); 4291 pmap_qremove((vm_offset_t)pc, 1); 4292 vm_page_unwire(m, 0); 4293 vm_page_free(m); 4294 pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc); 4295 } 4296 } 4297 sched_unpin(); 4298 pmap_invalidate_all(pmap); 4299 vm_page_unlock_queues(); 4300 PMAP_UNLOCK(pmap); 4301 pmap_free_zero_pages(free); 4302} 4303 4304/* 4305 * pmap_is_modified: 4306 * 4307 * Return whether or not the specified physical page was modified 4308 * in any physical maps. 4309 */ 4310boolean_t 4311pmap_is_modified(vm_page_t m) 4312{ 4313 boolean_t rv; 4314 4315 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 4316 ("pmap_is_modified: page %p is not managed", m)); 4317 4318 /* 4319 * If the page is not VPO_BUSY, then PG_WRITEABLE cannot be 4320 * concurrently set while the object is locked. Thus, if PG_WRITEABLE 4321 * is clear, no PTEs can have PG_M set. 4322 */ 4323 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 4324 if ((m->oflags & VPO_BUSY) == 0 && 4325 (m->flags & PG_WRITEABLE) == 0) 4326 return (FALSE); 4327 vm_page_lock_queues(); 4328 rv = pmap_is_modified_pvh(&m->md) || 4329 pmap_is_modified_pvh(pa_to_pvh(VM_PAGE_TO_PHYS(m))); 4330 vm_page_unlock_queues(); 4331 return (rv); 4332} 4333 4334/* 4335 * Returns TRUE if any of the given mappings were used to modify 4336 * physical memory. Otherwise, returns FALSE. Both page and 2mpage 4337 * mappings are supported. 4338 */ 4339static boolean_t 4340pmap_is_modified_pvh(struct md_page *pvh) 4341{ 4342 pv_entry_t pv; 4343 pt_entry_t *pte; 4344 pmap_t pmap; 4345 boolean_t rv; 4346 4347 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 4348 rv = FALSE; 4349 sched_pin(); 4350 TAILQ_FOREACH(pv, &pvh->pv_list, pv_list) { 4351 pmap = PV_PMAP(pv); 4352 PMAP_LOCK(pmap); 4353 pte = pmap_pte_quick(pmap, pv->pv_va); 4354 rv = (*pte & (PG_M | PG_RW)) == (PG_M | PG_RW); 4355 PMAP_UNLOCK(pmap); 4356 if (rv) 4357 break; 4358 } 4359 sched_unpin(); 4360 return (rv); 4361} 4362 4363/* 4364 * pmap_is_prefaultable: 4365 * 4366 * Return whether or not the specified virtual address is elgible 4367 * for prefault. 4368 */ 4369boolean_t 4370pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr) 4371{ 4372 pd_entry_t *pde; 4373 pt_entry_t *pte; 4374 boolean_t rv; 4375 4376 rv = FALSE; 4377 PMAP_LOCK(pmap); 4378 pde = pmap_pde(pmap, addr); 4379 if (*pde != 0 && (*pde & PG_PS) == 0) { 4380 pte = vtopte(addr); 4381 rv = *pte == 0; 4382 } 4383 PMAP_UNLOCK(pmap); 4384 return (rv); 4385} 4386 4387/* 4388 * pmap_is_referenced: 4389 * 4390 * Return whether or not the specified physical page was referenced 4391 * in any physical maps. 4392 */ 4393boolean_t 4394pmap_is_referenced(vm_page_t m) 4395{ 4396 boolean_t rv; 4397 4398 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 4399 ("pmap_is_referenced: page %p is not managed", m)); 4400 vm_page_lock_queues(); 4401 rv = pmap_is_referenced_pvh(&m->md) || 4402 pmap_is_referenced_pvh(pa_to_pvh(VM_PAGE_TO_PHYS(m))); 4403 vm_page_unlock_queues(); 4404 return (rv); 4405} 4406 4407/* 4408 * Returns TRUE if any of the given mappings were referenced and FALSE 4409 * otherwise. Both page and 4mpage mappings are supported. 4410 */ 4411static boolean_t 4412pmap_is_referenced_pvh(struct md_page *pvh) 4413{ 4414 pv_entry_t pv; 4415 pt_entry_t *pte; 4416 pmap_t pmap; 4417 boolean_t rv; 4418 4419 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 4420 rv = FALSE; 4421 sched_pin(); 4422 TAILQ_FOREACH(pv, &pvh->pv_list, pv_list) { 4423 pmap = PV_PMAP(pv); 4424 PMAP_LOCK(pmap); 4425 pte = pmap_pte_quick(pmap, pv->pv_va); 4426 rv = (*pte & (PG_A | PG_V)) == (PG_A | PG_V); 4427 PMAP_UNLOCK(pmap); 4428 if (rv) 4429 break; 4430 } 4431 sched_unpin(); 4432 return (rv); 4433} 4434 4435/* 4436 * Clear the write and modified bits in each of the given page's mappings. 4437 */ 4438void 4439pmap_remove_write(vm_page_t m) 4440{ 4441 struct md_page *pvh; 4442 pv_entry_t next_pv, pv; 4443 pmap_t pmap; 4444 pd_entry_t *pde; 4445 pt_entry_t oldpte, *pte; 4446 vm_offset_t va; 4447 4448 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 4449 ("pmap_remove_write: page %p is not managed", m)); 4450 4451 /* 4452 * If the page is not VPO_BUSY, then PG_WRITEABLE cannot be set by 4453 * another thread while the object is locked. Thus, if PG_WRITEABLE 4454 * is clear, no page table entries need updating. 4455 */ 4456 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 4457 if ((m->oflags & VPO_BUSY) == 0 && 4458 (m->flags & PG_WRITEABLE) == 0) 4459 return; 4460 vm_page_lock_queues(); 4461 sched_pin(); 4462 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 4463 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_list, next_pv) { 4464 va = pv->pv_va; 4465 pmap = PV_PMAP(pv); 4466 PMAP_LOCK(pmap); 4467 pde = pmap_pde(pmap, va); 4468 if ((*pde & PG_RW) != 0) 4469 (void)pmap_demote_pde(pmap, pde, va); 4470 PMAP_UNLOCK(pmap); 4471 } 4472 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 4473 pmap = PV_PMAP(pv); 4474 PMAP_LOCK(pmap); 4475 pde = pmap_pde(pmap, pv->pv_va); 4476 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_write: found" 4477 " a 4mpage in page %p's pv list", m)); 4478 pte = pmap_pte_quick(pmap, pv->pv_va); 4479retry: 4480 oldpte = *pte; 4481 if ((oldpte & PG_RW) != 0) { 4482 /* 4483 * Regardless of whether a pte is 32 or 64 bits 4484 * in size, PG_RW and PG_M are among the least 4485 * significant 32 bits. 4486 */ 4487 if (!atomic_cmpset_int((u_int *)pte, oldpte, 4488 oldpte & ~(PG_RW | PG_M))) 4489 goto retry; 4490 if ((oldpte & PG_M) != 0) 4491 vm_page_dirty(m); 4492 pmap_invalidate_page(pmap, pv->pv_va); 4493 } 4494 PMAP_UNLOCK(pmap); 4495 } 4496 vm_page_flag_clear(m, PG_WRITEABLE); 4497 sched_unpin(); 4498 vm_page_unlock_queues(); 4499} 4500 4501/* 4502 * pmap_ts_referenced: 4503 * 4504 * Return a count of reference bits for a page, clearing those bits. 4505 * It is not necessary for every reference bit to be cleared, but it 4506 * is necessary that 0 only be returned when there are truly no 4507 * reference bits set. 4508 * 4509 * XXX: The exact number of bits to check and clear is a matter that 4510 * should be tested and standardized at some point in the future for 4511 * optimal aging of shared pages. 4512 */ 4513int 4514pmap_ts_referenced(vm_page_t m) 4515{ 4516 struct md_page *pvh; 4517 pv_entry_t pv, pvf, pvn; 4518 pmap_t pmap; 4519 pd_entry_t oldpde, *pde; 4520 pt_entry_t *pte; 4521 vm_offset_t va; 4522 int rtval = 0; 4523 4524 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 4525 ("pmap_ts_referenced: page %p is not managed", m)); 4526 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 4527 vm_page_lock_queues(); 4528 sched_pin(); 4529 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_list, pvn) { 4530 va = pv->pv_va; 4531 pmap = PV_PMAP(pv); 4532 PMAP_LOCK(pmap); 4533 pde = pmap_pde(pmap, va); 4534 oldpde = *pde; 4535 if ((oldpde & PG_A) != 0) { 4536 if (pmap_demote_pde(pmap, pde, va)) { 4537 if ((oldpde & PG_W) == 0) { 4538 /* 4539 * Remove the mapping to a single page 4540 * so that a subsequent access may 4541 * repromote. Since the underlying 4542 * page table page is fully populated, 4543 * this removal never frees a page 4544 * table page. 4545 */ 4546 va += VM_PAGE_TO_PHYS(m) - (oldpde & 4547 PG_PS_FRAME); 4548 pmap_remove_page(pmap, va, NULL); 4549 rtval++; 4550 if (rtval > 4) { 4551 PMAP_UNLOCK(pmap); 4552 goto out; 4553 } 4554 } 4555 } 4556 } 4557 PMAP_UNLOCK(pmap); 4558 } 4559 if ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) { 4560 pvf = pv; 4561 do { 4562 pvn = TAILQ_NEXT(pv, pv_list); 4563 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list); 4564 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list); 4565 pmap = PV_PMAP(pv); 4566 PMAP_LOCK(pmap); 4567 pde = pmap_pde(pmap, pv->pv_va); 4568 KASSERT((*pde & PG_PS) == 0, ("pmap_ts_referenced:" 4569 " found a 4mpage in page %p's pv list", m)); 4570 pte = pmap_pte_quick(pmap, pv->pv_va); 4571 if ((*pte & PG_A) != 0) { 4572 atomic_clear_int((u_int *)pte, PG_A); 4573 pmap_invalidate_page(pmap, pv->pv_va); 4574 rtval++; 4575 if (rtval > 4) 4576 pvn = NULL; 4577 } 4578 PMAP_UNLOCK(pmap); 4579 } while ((pv = pvn) != NULL && pv != pvf); 4580 } 4581out: 4582 sched_unpin(); 4583 vm_page_unlock_queues(); 4584 return (rtval); 4585} 4586 4587/* 4588 * Clear the modify bits on the specified physical page. 4589 */ 4590void 4591pmap_clear_modify(vm_page_t m) 4592{ 4593 struct md_page *pvh; 4594 pv_entry_t next_pv, pv; 4595 pmap_t pmap; 4596 pd_entry_t oldpde, *pde; 4597 pt_entry_t oldpte, *pte; 4598 vm_offset_t va; 4599 4600 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 4601 ("pmap_clear_modify: page %p is not managed", m)); 4602 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 4603 KASSERT((m->oflags & VPO_BUSY) == 0, 4604 ("pmap_clear_modify: page %p is busy", m)); 4605 4606 /* 4607 * If the page is not PG_WRITEABLE, then no PTEs can have PG_M set. 4608 * If the object containing the page is locked and the page is not 4609 * VPO_BUSY, then PG_WRITEABLE cannot be concurrently set. 4610 */ 4611 if ((m->flags & PG_WRITEABLE) == 0) 4612 return; 4613 vm_page_lock_queues(); 4614 sched_pin(); 4615 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 4616 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_list, next_pv) { 4617 va = pv->pv_va; 4618 pmap = PV_PMAP(pv); 4619 PMAP_LOCK(pmap); 4620 pde = pmap_pde(pmap, va); 4621 oldpde = *pde; 4622 if ((oldpde & PG_RW) != 0) { 4623 if (pmap_demote_pde(pmap, pde, va)) { 4624 if ((oldpde & PG_W) == 0) { 4625 /* 4626 * Write protect the mapping to a 4627 * single page so that a subsequent 4628 * write access may repromote. 4629 */ 4630 va += VM_PAGE_TO_PHYS(m) - (oldpde & 4631 PG_PS_FRAME); 4632 pte = pmap_pte_quick(pmap, va); 4633 oldpte = *pte; 4634 if ((oldpte & PG_V) != 0) { 4635 /* 4636 * Regardless of whether a pte is 32 or 64 bits 4637 * in size, PG_RW and PG_M are among the least 4638 * significant 32 bits. 4639 */ 4640 while (!atomic_cmpset_int((u_int *)pte, 4641 oldpte, 4642 oldpte & ~(PG_M | PG_RW))) 4643 oldpte = *pte; 4644 vm_page_dirty(m); 4645 pmap_invalidate_page(pmap, va); 4646 } 4647 } 4648 } 4649 } 4650 PMAP_UNLOCK(pmap); 4651 } 4652 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 4653 pmap = PV_PMAP(pv); 4654 PMAP_LOCK(pmap); 4655 pde = pmap_pde(pmap, pv->pv_va); 4656 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_modify: found" 4657 " a 4mpage in page %p's pv list", m)); 4658 pte = pmap_pte_quick(pmap, pv->pv_va); 4659 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) { 4660 /* 4661 * Regardless of whether a pte is 32 or 64 bits 4662 * in size, PG_M is among the least significant 4663 * 32 bits. 4664 */ 4665 atomic_clear_int((u_int *)pte, PG_M); 4666 pmap_invalidate_page(pmap, pv->pv_va); 4667 } 4668 PMAP_UNLOCK(pmap); 4669 } 4670 sched_unpin(); 4671 vm_page_unlock_queues(); 4672} 4673 4674/* 4675 * pmap_clear_reference: 4676 * 4677 * Clear the reference bit on the specified physical page. 4678 */ 4679void 4680pmap_clear_reference(vm_page_t m) 4681{ 4682 struct md_page *pvh; 4683 pv_entry_t next_pv, pv; 4684 pmap_t pmap; 4685 pd_entry_t oldpde, *pde; 4686 pt_entry_t *pte; 4687 vm_offset_t va; 4688 4689 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 4690 ("pmap_clear_reference: page %p is not managed", m)); 4691 vm_page_lock_queues(); 4692 sched_pin(); 4693 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 4694 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_list, next_pv) { 4695 va = pv->pv_va; 4696 pmap = PV_PMAP(pv); 4697 PMAP_LOCK(pmap); 4698 pde = pmap_pde(pmap, va); 4699 oldpde = *pde; 4700 if ((oldpde & PG_A) != 0) { 4701 if (pmap_demote_pde(pmap, pde, va)) { 4702 /* 4703 * Remove the mapping to a single page so 4704 * that a subsequent access may repromote. 4705 * Since the underlying page table page is 4706 * fully populated, this removal never frees 4707 * a page table page. 4708 */ 4709 va += VM_PAGE_TO_PHYS(m) - (oldpde & 4710 PG_PS_FRAME); 4711 pmap_remove_page(pmap, va, NULL); 4712 } 4713 } 4714 PMAP_UNLOCK(pmap); 4715 } 4716 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 4717 pmap = PV_PMAP(pv); 4718 PMAP_LOCK(pmap); 4719 pde = pmap_pde(pmap, pv->pv_va); 4720 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_reference: found" 4721 " a 4mpage in page %p's pv list", m)); 4722 pte = pmap_pte_quick(pmap, pv->pv_va); 4723 if ((*pte & PG_A) != 0) { 4724 /* 4725 * Regardless of whether a pte is 32 or 64 bits 4726 * in size, PG_A is among the least significant 4727 * 32 bits. 4728 */ 4729 atomic_clear_int((u_int *)pte, PG_A); 4730 pmap_invalidate_page(pmap, pv->pv_va); 4731 } 4732 PMAP_UNLOCK(pmap); 4733 } 4734 sched_unpin(); 4735 vm_page_unlock_queues(); 4736} 4737 4738/* 4739 * Miscellaneous support routines follow 4740 */ 4741 4742/* Adjust the cache mode for a 4KB page mapped via a PTE. */ 4743static __inline void 4744pmap_pte_attr(pt_entry_t *pte, int cache_bits) 4745{ 4746 u_int opte, npte; 4747 4748 /* 4749 * The cache mode bits are all in the low 32-bits of the 4750 * PTE, so we can just spin on updating the low 32-bits. 4751 */ 4752 do { 4753 opte = *(u_int *)pte; 4754 npte = opte & ~PG_PTE_CACHE; 4755 npte |= cache_bits; 4756 } while (npte != opte && !atomic_cmpset_int((u_int *)pte, opte, npte)); 4757} 4758 4759/* Adjust the cache mode for a 2/4MB page mapped via a PDE. */ 4760static __inline void 4761pmap_pde_attr(pd_entry_t *pde, int cache_bits) 4762{ 4763 u_int opde, npde; 4764 4765 /* 4766 * The cache mode bits are all in the low 32-bits of the 4767 * PDE, so we can just spin on updating the low 32-bits. 4768 */ 4769 do { 4770 opde = *(u_int *)pde; 4771 npde = opde & ~PG_PDE_CACHE; 4772 npde |= cache_bits; 4773 } while (npde != opde && !atomic_cmpset_int((u_int *)pde, opde, npde)); 4774} 4775 4776/* 4777 * Map a set of physical memory pages into the kernel virtual 4778 * address space. Return a pointer to where it is mapped. This 4779 * routine is intended to be used for mapping device memory, 4780 * NOT real memory. 4781 */ 4782void * 4783pmap_mapdev_attr(vm_paddr_t pa, vm_size_t size, int mode) 4784{ 4785 vm_offset_t va, offset; 4786 vm_size_t tmpsize; 4787 4788 offset = pa & PAGE_MASK; 4789 size = roundup(offset + size, PAGE_SIZE); 4790 pa = pa & PG_FRAME; 4791 4792 if (pa < KERNLOAD && pa + size <= KERNLOAD) 4793 va = KERNBASE + pa; 4794 else 4795 va = kmem_alloc_nofault(kernel_map, size); 4796 if (!va) 4797 panic("pmap_mapdev: Couldn't alloc kernel virtual memory"); 4798 4799 for (tmpsize = 0; tmpsize < size; tmpsize += PAGE_SIZE) 4800 pmap_kenter_attr(va + tmpsize, pa + tmpsize, mode); 4801 pmap_invalidate_range(kernel_pmap, va, va + tmpsize); 4802 pmap_invalidate_cache_range(va, va + size); 4803 return ((void *)(va + offset)); 4804} 4805 4806void * 4807pmap_mapdev(vm_paddr_t pa, vm_size_t size) 4808{ 4809 4810 return (pmap_mapdev_attr(pa, size, PAT_UNCACHEABLE)); 4811} 4812 4813void * 4814pmap_mapbios(vm_paddr_t pa, vm_size_t size) 4815{ 4816 4817 return (pmap_mapdev_attr(pa, size, PAT_WRITE_BACK)); 4818} 4819 4820void 4821pmap_unmapdev(vm_offset_t va, vm_size_t size) 4822{ 4823 vm_offset_t base, offset, tmpva; 4824 4825 if (va >= KERNBASE && va + size <= KERNBASE + KERNLOAD) 4826 return; 4827 base = trunc_page(va); 4828 offset = va & PAGE_MASK; 4829 size = roundup(offset + size, PAGE_SIZE); 4830 for (tmpva = base; tmpva < (base + size); tmpva += PAGE_SIZE) 4831 pmap_kremove(tmpva); 4832 pmap_invalidate_range(kernel_pmap, va, tmpva); 4833 kmem_free(kernel_map, base, size); 4834} 4835 4836/* 4837 * Sets the memory attribute for the specified page. 4838 */ 4839void 4840pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma) 4841{ 4842 struct sysmaps *sysmaps; 4843 vm_offset_t sva, eva; 4844 4845 m->md.pat_mode = ma; 4846 if ((m->flags & PG_FICTITIOUS) != 0) 4847 return; 4848 4849 /* 4850 * If "m" is a normal page, flush it from the cache. 4851 * See pmap_invalidate_cache_range(). 4852 * 4853 * First, try to find an existing mapping of the page by sf 4854 * buffer. sf_buf_invalidate_cache() modifies mapping and 4855 * flushes the cache. 4856 */ 4857 if (sf_buf_invalidate_cache(m)) 4858 return; 4859 4860 /* 4861 * If page is not mapped by sf buffer, but CPU does not 4862 * support self snoop, map the page transient and do 4863 * invalidation. In the worst case, whole cache is flushed by 4864 * pmap_invalidate_cache_range(). 4865 */ 4866 if ((cpu_feature & (CPUID_SS|CPUID_CLFSH)) == CPUID_CLFSH) { 4867 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)]; 4868 mtx_lock(&sysmaps->lock); 4869 if (*sysmaps->CMAP2) 4870 panic("pmap_page_set_memattr: CMAP2 busy"); 4871 sched_pin(); 4872 *sysmaps->CMAP2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | 4873 PG_A | PG_M | pmap_cache_bits(m->md.pat_mode, 0); 4874 invlcaddr(sysmaps->CADDR2); 4875 sva = (vm_offset_t)sysmaps->CADDR2; 4876 eva = sva + PAGE_SIZE; 4877 } else 4878 sva = eva = 0; /* gcc */ 4879 pmap_invalidate_cache_range(sva, eva); 4880 if (sva != 0) { 4881 *sysmaps->CMAP2 = 0; 4882 sched_unpin(); 4883 mtx_unlock(&sysmaps->lock); 4884 } 4885} 4886 4887/* 4888 * Changes the specified virtual address range's memory type to that given by 4889 * the parameter "mode". The specified virtual address range must be 4890 * completely contained within either the kernel map. 4891 * 4892 * Returns zero if the change completed successfully, and either EINVAL or 4893 * ENOMEM if the change failed. Specifically, EINVAL is returned if some part 4894 * of the virtual address range was not mapped, and ENOMEM is returned if 4895 * there was insufficient memory available to complete the change. 4896 */ 4897int 4898pmap_change_attr(vm_offset_t va, vm_size_t size, int mode) 4899{ 4900 vm_offset_t base, offset, tmpva; 4901 pd_entry_t *pde; 4902 pt_entry_t *pte; 4903 int cache_bits_pte, cache_bits_pde; 4904 boolean_t changed; 4905 4906 base = trunc_page(va); 4907 offset = va & PAGE_MASK; 4908 size = roundup(offset + size, PAGE_SIZE); 4909 4910 /* 4911 * Only supported on kernel virtual addresses above the recursive map. 4912 */ 4913 if (base < VM_MIN_KERNEL_ADDRESS) 4914 return (EINVAL); 4915 4916 cache_bits_pde = pmap_cache_bits(mode, 1); 4917 cache_bits_pte = pmap_cache_bits(mode, 0); 4918 changed = FALSE; 4919 4920 /* 4921 * Pages that aren't mapped aren't supported. Also break down 4922 * 2/4MB pages into 4KB pages if required. 4923 */ 4924 PMAP_LOCK(kernel_pmap); 4925 for (tmpva = base; tmpva < base + size; ) { 4926 pde = pmap_pde(kernel_pmap, tmpva); 4927 if (*pde == 0) { 4928 PMAP_UNLOCK(kernel_pmap); 4929 return (EINVAL); 4930 } 4931 if (*pde & PG_PS) { 4932 /* 4933 * If the current 2/4MB page already has 4934 * the required memory type, then we need not 4935 * demote this page. Just increment tmpva to 4936 * the next 2/4MB page frame. 4937 */ 4938 if ((*pde & PG_PDE_CACHE) == cache_bits_pde) { 4939 tmpva = trunc_4mpage(tmpva) + NBPDR; 4940 continue; 4941 } 4942 4943 /* 4944 * If the current offset aligns with a 2/4MB 4945 * page frame and there is at least 2/4MB left 4946 * within the range, then we need not break 4947 * down this page into 4KB pages. 4948 */ 4949 if ((tmpva & PDRMASK) == 0 && 4950 tmpva + PDRMASK < base + size) { 4951 tmpva += NBPDR; 4952 continue; 4953 } 4954 if (!pmap_demote_pde(kernel_pmap, pde, tmpva)) { 4955 PMAP_UNLOCK(kernel_pmap); 4956 return (ENOMEM); 4957 } 4958 } 4959 pte = vtopte(tmpva); 4960 if (*pte == 0) { 4961 PMAP_UNLOCK(kernel_pmap); 4962 return (EINVAL); 4963 } 4964 tmpva += PAGE_SIZE; 4965 } 4966 PMAP_UNLOCK(kernel_pmap); 4967 4968 /* 4969 * Ok, all the pages exist, so run through them updating their 4970 * cache mode if required. 4971 */ 4972 for (tmpva = base; tmpva < base + size; ) { 4973 pde = pmap_pde(kernel_pmap, tmpva); 4974 if (*pde & PG_PS) { 4975 if ((*pde & PG_PDE_CACHE) != cache_bits_pde) { 4976 pmap_pde_attr(pde, cache_bits_pde); 4977 changed = TRUE; 4978 } 4979 tmpva = trunc_4mpage(tmpva) + NBPDR; 4980 } else { 4981 pte = vtopte(tmpva); 4982 if ((*pte & PG_PTE_CACHE) != cache_bits_pte) { 4983 pmap_pte_attr(pte, cache_bits_pte); 4984 changed = TRUE; 4985 } 4986 tmpva += PAGE_SIZE; 4987 } 4988 } 4989 4990 /* 4991 * Flush CPU caches to make sure any data isn't cached that 4992 * shouldn't be, etc. 4993 */ 4994 if (changed) { 4995 pmap_invalidate_range(kernel_pmap, base, tmpva); 4996 pmap_invalidate_cache_range(base, tmpva); 4997 } 4998 return (0); 4999} 5000 5001/* 5002 * perform the pmap work for mincore 5003 */ 5004int 5005pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa) 5006{ 5007 pd_entry_t *pdep; 5008 pt_entry_t *ptep, pte; 5009 vm_paddr_t pa; 5010 int val; 5011 5012 PMAP_LOCK(pmap); 5013retry: 5014 pdep = pmap_pde(pmap, addr); 5015 if (*pdep != 0) { 5016 if (*pdep & PG_PS) { 5017 pte = *pdep; 5018 /* Compute the physical address of the 4KB page. */ 5019 pa = ((*pdep & PG_PS_FRAME) | (addr & PDRMASK)) & 5020 PG_FRAME; 5021 val = MINCORE_SUPER; 5022 } else { 5023 ptep = pmap_pte(pmap, addr); 5024 pte = *ptep; 5025 pmap_pte_release(ptep); 5026 pa = pte & PG_FRAME; 5027 val = 0; 5028 } 5029 } else { 5030 pte = 0; 5031 pa = 0; 5032 val = 0; 5033 } 5034 if ((pte & PG_V) != 0) { 5035 val |= MINCORE_INCORE; 5036 if ((pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) 5037 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER; 5038 if ((pte & PG_A) != 0) 5039 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER; 5040 } 5041 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) != 5042 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) && 5043 (pte & (PG_MANAGED | PG_V)) == (PG_MANAGED | PG_V)) { 5044 /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */ 5045 if (vm_page_pa_tryrelock(pmap, pa, locked_pa)) 5046 goto retry; 5047 } else 5048 PA_UNLOCK_COND(*locked_pa); 5049 PMAP_UNLOCK(pmap); 5050 return (val); 5051} 5052 5053void 5054pmap_activate(struct thread *td) 5055{ 5056 pmap_t pmap, oldpmap; 5057 u_int32_t cr3; 5058 5059 critical_enter(); 5060 pmap = vmspace_pmap(td->td_proc->p_vmspace); 5061 oldpmap = PCPU_GET(curpmap); 5062#if defined(SMP) 5063 atomic_clear_int(&oldpmap->pm_active, PCPU_GET(cpumask)); 5064 atomic_set_int(&pmap->pm_active, PCPU_GET(cpumask)); 5065#else 5066 oldpmap->pm_active &= ~1; 5067 pmap->pm_active |= 1; 5068#endif 5069#ifdef PAE 5070 cr3 = vtophys(pmap->pm_pdpt); 5071#else 5072 cr3 = vtophys(pmap->pm_pdir); 5073#endif 5074 /* 5075 * pmap_activate is for the current thread on the current cpu 5076 */ 5077 td->td_pcb->pcb_cr3 = cr3; 5078 load_cr3(cr3); 5079 PCPU_SET(curpmap, pmap); 5080 critical_exit(); 5081} 5082 5083void 5084pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz) 5085{ 5086} 5087 5088/* 5089 * Increase the starting virtual address of the given mapping if a 5090 * different alignment might result in more superpage mappings. 5091 */ 5092void 5093pmap_align_superpage(vm_object_t object, vm_ooffset_t offset, 5094 vm_offset_t *addr, vm_size_t size) 5095{ 5096 vm_offset_t superpage_offset; 5097 5098 if (size < NBPDR) 5099 return; 5100 if (object != NULL && (object->flags & OBJ_COLORED) != 0) 5101 offset += ptoa(object->pg_color); 5102 superpage_offset = offset & PDRMASK; 5103 if (size - ((NBPDR - superpage_offset) & PDRMASK) < NBPDR || 5104 (*addr & PDRMASK) == superpage_offset) 5105 return; 5106 if ((*addr & PDRMASK) < superpage_offset) 5107 *addr = (*addr & ~PDRMASK) + superpage_offset; 5108 else 5109 *addr = ((*addr + PDRMASK) & ~PDRMASK) + superpage_offset; 5110} 5111 5112 5113#if defined(PMAP_DEBUG) 5114pmap_pid_dump(int pid) 5115{ 5116 pmap_t pmap; 5117 struct proc *p; 5118 int npte = 0; 5119 int index; 5120 5121 sx_slock(&allproc_lock); 5122 FOREACH_PROC_IN_SYSTEM(p) { 5123 if (p->p_pid != pid) 5124 continue; 5125 5126 if (p->p_vmspace) { 5127 int i,j; 5128 index = 0; 5129 pmap = vmspace_pmap(p->p_vmspace); 5130 for (i = 0; i < NPDEPTD; i++) { 5131 pd_entry_t *pde; 5132 pt_entry_t *pte; 5133 vm_offset_t base = i << PDRSHIFT; 5134 5135 pde = &pmap->pm_pdir[i]; 5136 if (pde && pmap_pde_v(pde)) { 5137 for (j = 0; j < NPTEPG; j++) { 5138 vm_offset_t va = base + (j << PAGE_SHIFT); 5139 if (va >= (vm_offset_t) VM_MIN_KERNEL_ADDRESS) { 5140 if (index) { 5141 index = 0; 5142 printf("\n"); 5143 } 5144 sx_sunlock(&allproc_lock); 5145 return (npte); 5146 } 5147 pte = pmap_pte(pmap, va); 5148 if (pte && pmap_pte_v(pte)) { 5149 pt_entry_t pa; 5150 vm_page_t m; 5151 pa = *pte; 5152 m = PHYS_TO_VM_PAGE(pa & PG_FRAME); 5153 printf("va: 0x%x, pt: 0x%x, h: %d, w: %d, f: 0x%x", 5154 va, pa, m->hold_count, m->wire_count, m->flags); 5155 npte++; 5156 index++; 5157 if (index >= 2) { 5158 index = 0; 5159 printf("\n"); 5160 } else { 5161 printf(" "); 5162 } 5163 } 5164 } 5165 } 5166 } 5167 } 5168 } 5169 sx_sunlock(&allproc_lock); 5170 return (npte); 5171} 5172#endif 5173 5174#if defined(DEBUG) 5175 5176static void pads(pmap_t pm); 5177void pmap_pvdump(vm_offset_t pa); 5178 5179/* print address space of pmap*/ 5180static void 5181pads(pmap_t pm) 5182{ 5183 int i, j; 5184 vm_paddr_t va; 5185 pt_entry_t *ptep; 5186 5187 if (pm == kernel_pmap) 5188 return; 5189 for (i = 0; i < NPDEPTD; i++) 5190 if (pm->pm_pdir[i]) 5191 for (j = 0; j < NPTEPG; j++) { 5192 va = (i << PDRSHIFT) + (j << PAGE_SHIFT); 5193 if (pm == kernel_pmap && va < KERNBASE) 5194 continue; 5195 if (pm != kernel_pmap && va > UPT_MAX_ADDRESS) 5196 continue; 5197 ptep = pmap_pte(pm, va); 5198 if (pmap_pte_v(ptep)) 5199 printf("%x:%x ", va, *ptep); 5200 }; 5201 5202} 5203 5204void 5205pmap_pvdump(vm_paddr_t pa) 5206{ 5207 pv_entry_t pv; 5208 pmap_t pmap; 5209 vm_page_t m; 5210 5211 printf("pa %x", pa); 5212 m = PHYS_TO_VM_PAGE(pa); 5213 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 5214 pmap = PV_PMAP(pv); 5215 printf(" -> pmap %p, va %x", (void *)pmap, pv->pv_va); 5216 pads(pmap); 5217 } 5218 printf(" "); 5219} 5220#endif 5221