pmap.c revision 208667
1/*- 2 * Copyright (c) 1991 Regents of the University of California. 3 * All rights reserved. 4 * Copyright (c) 1994 John S. Dyson 5 * All rights reserved. 6 * Copyright (c) 1994 David Greenman 7 * All rights reserved. 8 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu> 9 * All rights reserved. 10 * 11 * This code is derived from software contributed to Berkeley by 12 * the Systems Programming Group of the University of Utah Computer 13 * Science Department and William Jolitz of UUNET Technologies Inc. 14 * 15 * Redistribution and use in source and binary forms, with or without 16 * modification, are permitted provided that the following conditions 17 * are met: 18 * 1. Redistributions of source code must retain the above copyright 19 * notice, this list of conditions and the following disclaimer. 20 * 2. Redistributions in binary form must reproduce the above copyright 21 * notice, this list of conditions and the following disclaimer in the 22 * documentation and/or other materials provided with the distribution. 23 * 3. All advertising materials mentioning features or use of this software 24 * must display the following acknowledgement: 25 * This product includes software developed by the University of 26 * California, Berkeley and its contributors. 27 * 4. Neither the name of the University nor the names of its contributors 28 * may be used to endorse or promote products derived from this software 29 * without specific prior written permission. 30 * 31 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 32 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 33 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 34 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 35 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 36 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 37 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 38 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 39 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 40 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 41 * SUCH DAMAGE. 42 * 43 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91 44 */ 45/*- 46 * Copyright (c) 2003 Networks Associates Technology, Inc. 47 * All rights reserved. 48 * 49 * This software was developed for the FreeBSD Project by Jake Burkholder, 50 * Safeport Network Services, and Network Associates Laboratories, the 51 * Security Research Division of Network Associates, Inc. under 52 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA 53 * CHATS research program. 54 * 55 * Redistribution and use in source and binary forms, with or without 56 * modification, are permitted provided that the following conditions 57 * are met: 58 * 1. Redistributions of source code must retain the above copyright 59 * notice, this list of conditions and the following disclaimer. 60 * 2. Redistributions in binary form must reproduce the above copyright 61 * notice, this list of conditions and the following disclaimer in the 62 * documentation and/or other materials provided with the distribution. 63 * 64 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 65 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 66 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 67 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 68 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 69 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 70 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 71 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 72 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 73 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 74 * SUCH DAMAGE. 75 */ 76 77#include <sys/cdefs.h> 78__FBSDID("$FreeBSD: head/sys/i386/i386/pmap.c 208667 2010-05-31 06:06:10Z alc $"); 79 80/* 81 * Manages physical address maps. 82 * 83 * In addition to hardware address maps, this 84 * module is called upon to provide software-use-only 85 * maps which may or may not be stored in the same 86 * form as hardware maps. These pseudo-maps are 87 * used to store intermediate results from copy 88 * operations to and from address spaces. 89 * 90 * Since the information managed by this module is 91 * also stored by the logical address mapping module, 92 * this module may throw away valid virtual-to-physical 93 * mappings at almost any time. However, invalidations 94 * of virtual-to-physical mappings must be done as 95 * requested. 96 * 97 * In order to cope with hardware architectures which 98 * make virtual-to-physical map invalidates expensive, 99 * this module may delay invalidate or reduced protection 100 * operations until such time as they are actually 101 * necessary. This module is given full information as 102 * to which processors are currently using which maps, 103 * and to when physical maps must be made correct. 104 */ 105 106#include "opt_cpu.h" 107#include "opt_pmap.h" 108#include "opt_msgbuf.h" 109#include "opt_smp.h" 110#include "opt_xbox.h" 111 112#include <sys/param.h> 113#include <sys/systm.h> 114#include <sys/kernel.h> 115#include <sys/ktr.h> 116#include <sys/lock.h> 117#include <sys/malloc.h> 118#include <sys/mman.h> 119#include <sys/msgbuf.h> 120#include <sys/mutex.h> 121#include <sys/proc.h> 122#include <sys/sf_buf.h> 123#include <sys/sx.h> 124#include <sys/vmmeter.h> 125#include <sys/sched.h> 126#include <sys/sysctl.h> 127#ifdef SMP 128#include <sys/smp.h> 129#endif 130 131#include <vm/vm.h> 132#include <vm/vm_param.h> 133#include <vm/vm_kern.h> 134#include <vm/vm_page.h> 135#include <vm/vm_map.h> 136#include <vm/vm_object.h> 137#include <vm/vm_extern.h> 138#include <vm/vm_pageout.h> 139#include <vm/vm_pager.h> 140#include <vm/vm_reserv.h> 141#include <vm/uma.h> 142 143#include <machine/cpu.h> 144#include <machine/cputypes.h> 145#include <machine/md_var.h> 146#include <machine/pcb.h> 147#include <machine/specialreg.h> 148#ifdef SMP 149#include <machine/smp.h> 150#endif 151 152#ifdef XBOX 153#include <machine/xbox.h> 154#endif 155 156#if !defined(CPU_DISABLE_SSE) && defined(I686_CPU) 157#define CPU_ENABLE_SSE 158#endif 159 160#ifndef PMAP_SHPGPERPROC 161#define PMAP_SHPGPERPROC 200 162#endif 163 164#if !defined(DIAGNOSTIC) 165#ifdef __GNUC_GNU_INLINE__ 166#define PMAP_INLINE __attribute__((__gnu_inline__)) inline 167#else 168#define PMAP_INLINE extern inline 169#endif 170#else 171#define PMAP_INLINE 172#endif 173 174#define PV_STATS 175#ifdef PV_STATS 176#define PV_STAT(x) do { x ; } while (0) 177#else 178#define PV_STAT(x) do { } while (0) 179#endif 180 181#define pa_index(pa) ((pa) >> PDRSHIFT) 182#define pa_to_pvh(pa) (&pv_table[pa_index(pa)]) 183 184/* 185 * Get PDEs and PTEs for user/kernel address space 186 */ 187#define pmap_pde(m, v) (&((m)->pm_pdir[(vm_offset_t)(v) >> PDRSHIFT])) 188#define pdir_pde(m, v) (m[(vm_offset_t)(v) >> PDRSHIFT]) 189 190#define pmap_pde_v(pte) ((*(int *)pte & PG_V) != 0) 191#define pmap_pte_w(pte) ((*(int *)pte & PG_W) != 0) 192#define pmap_pte_m(pte) ((*(int *)pte & PG_M) != 0) 193#define pmap_pte_u(pte) ((*(int *)pte & PG_A) != 0) 194#define pmap_pte_v(pte) ((*(int *)pte & PG_V) != 0) 195 196#define pmap_pte_set_w(pte, v) ((v) ? atomic_set_int((u_int *)(pte), PG_W) : \ 197 atomic_clear_int((u_int *)(pte), PG_W)) 198#define pmap_pte_set_prot(pte, v) ((*(int *)pte &= ~PG_PROT), (*(int *)pte |= (v))) 199 200struct pmap kernel_pmap_store; 201LIST_HEAD(pmaplist, pmap); 202static struct pmaplist allpmaps; 203static struct mtx allpmaps_lock; 204 205vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */ 206vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */ 207int pgeflag = 0; /* PG_G or-in */ 208int pseflag = 0; /* PG_PS or-in */ 209 210static int nkpt = NKPT; 211vm_offset_t kernel_vm_end = KERNBASE + NKPT * NBPDR; 212extern u_int32_t KERNend; 213extern u_int32_t KPTphys; 214 215#ifdef PAE 216pt_entry_t pg_nx; 217static uma_zone_t pdptzone; 218#endif 219 220static int pat_works = 0; /* Is page attribute table sane? */ 221 222SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD, 0, "VM/pmap parameters"); 223 224static int pg_ps_enabled = 1; 225SYSCTL_INT(_vm_pmap, OID_AUTO, pg_ps_enabled, CTLFLAG_RDTUN, &pg_ps_enabled, 0, 226 "Are large page mappings enabled?"); 227 228/* 229 * Data for the pv entry allocation mechanism 230 */ 231static int pv_entry_count = 0, pv_entry_max = 0, pv_entry_high_water = 0; 232static struct md_page *pv_table; 233static int shpgperproc = PMAP_SHPGPERPROC; 234 235struct pv_chunk *pv_chunkbase; /* KVA block for pv_chunks */ 236int pv_maxchunks; /* How many chunks we have KVA for */ 237vm_offset_t pv_vafree; /* freelist stored in the PTE */ 238 239/* 240 * All those kernel PT submaps that BSD is so fond of 241 */ 242struct sysmaps { 243 struct mtx lock; 244 pt_entry_t *CMAP1; 245 pt_entry_t *CMAP2; 246 caddr_t CADDR1; 247 caddr_t CADDR2; 248}; 249static struct sysmaps sysmaps_pcpu[MAXCPU]; 250pt_entry_t *CMAP1 = 0, *KPTmap; 251static pt_entry_t *CMAP3; 252static pd_entry_t *KPTD; 253caddr_t CADDR1 = 0, ptvmmap = 0; 254static caddr_t CADDR3; 255struct msgbuf *msgbufp = 0; 256 257/* 258 * Crashdump maps. 259 */ 260static caddr_t crashdumpmap; 261 262static pt_entry_t *PMAP1 = 0, *PMAP2; 263static pt_entry_t *PADDR1 = 0, *PADDR2; 264#ifdef SMP 265static int PMAP1cpu; 266static int PMAP1changedcpu; 267SYSCTL_INT(_debug, OID_AUTO, PMAP1changedcpu, CTLFLAG_RD, 268 &PMAP1changedcpu, 0, 269 "Number of times pmap_pte_quick changed CPU with same PMAP1"); 270#endif 271static int PMAP1changed; 272SYSCTL_INT(_debug, OID_AUTO, PMAP1changed, CTLFLAG_RD, 273 &PMAP1changed, 0, 274 "Number of times pmap_pte_quick changed PMAP1"); 275static int PMAP1unchanged; 276SYSCTL_INT(_debug, OID_AUTO, PMAP1unchanged, CTLFLAG_RD, 277 &PMAP1unchanged, 0, 278 "Number of times pmap_pte_quick didn't change PMAP1"); 279static struct mtx PMAP2mutex; 280 281static void free_pv_entry(pmap_t pmap, pv_entry_t pv); 282static pv_entry_t get_pv_entry(pmap_t locked_pmap, int try); 283static void pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa); 284static boolean_t pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa); 285static void pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa); 286static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va); 287static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, 288 vm_offset_t va); 289static int pmap_pvh_wired_mappings(struct md_page *pvh, int count); 290 291static boolean_t pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va); 292static boolean_t pmap_enter_pde(pmap_t pmap, vm_offset_t va, vm_page_t m, 293 vm_prot_t prot); 294static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, 295 vm_page_t m, vm_prot_t prot, vm_page_t mpte); 296static void pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte); 297static void pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte); 298static boolean_t pmap_is_modified_pvh(struct md_page *pvh); 299static boolean_t pmap_is_referenced_pvh(struct md_page *pvh); 300static void pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode); 301static void pmap_kenter_pde(vm_offset_t va, pd_entry_t newpde); 302static vm_page_t pmap_lookup_pt_page(pmap_t pmap, vm_offset_t va); 303static void pmap_pde_attr(pd_entry_t *pde, int cache_bits); 304static void pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va); 305static boolean_t pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva, 306 vm_prot_t prot); 307static void pmap_pte_attr(pt_entry_t *pte, int cache_bits); 308static void pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva, 309 vm_page_t *free); 310static int pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t sva, 311 vm_page_t *free); 312static void pmap_remove_pt_page(pmap_t pmap, vm_page_t mpte); 313static void pmap_remove_page(struct pmap *pmap, vm_offset_t va, 314 vm_page_t *free); 315static void pmap_remove_entry(struct pmap *pmap, vm_page_t m, 316 vm_offset_t va); 317static void pmap_insert_entry(pmap_t pmap, vm_offset_t va, vm_page_t m); 318static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, 319 vm_page_t m); 320static void pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, 321 pd_entry_t newpde); 322static void pmap_update_pde_invalidate(vm_offset_t va, pd_entry_t newpde); 323 324static vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va, int flags); 325 326static vm_page_t _pmap_allocpte(pmap_t pmap, unsigned ptepindex, int flags); 327static int _pmap_unwire_pte_hold(pmap_t pmap, vm_page_t m, vm_page_t *free); 328static pt_entry_t *pmap_pte_quick(pmap_t pmap, vm_offset_t va); 329static void pmap_pte_release(pt_entry_t *pte); 330static int pmap_unuse_pt(pmap_t, vm_offset_t, vm_page_t *); 331#ifdef PAE 332static void *pmap_pdpt_allocf(uma_zone_t zone, int bytes, u_int8_t *flags, int wait); 333#endif 334static void pmap_set_pg(void); 335 336CTASSERT(1 << PDESHIFT == sizeof(pd_entry_t)); 337CTASSERT(1 << PTESHIFT == sizeof(pt_entry_t)); 338 339/* 340 * If you get an error here, then you set KVA_PAGES wrong! See the 341 * description of KVA_PAGES in sys/i386/include/pmap.h. It must be 342 * multiple of 4 for a normal kernel, or a multiple of 8 for a PAE. 343 */ 344CTASSERT(KERNBASE % (1 << 24) == 0); 345 346/* 347 * Bootstrap the system enough to run with virtual memory. 348 * 349 * On the i386 this is called after mapping has already been enabled 350 * and just syncs the pmap module with what has already been done. 351 * [We can't call it easily with mapping off since the kernel is not 352 * mapped with PA == VA, hence we would have to relocate every address 353 * from the linked base (virtual) address "KERNBASE" to the actual 354 * (physical) address starting relative to 0] 355 */ 356void 357pmap_bootstrap(vm_paddr_t firstaddr) 358{ 359 vm_offset_t va; 360 pt_entry_t *pte, *unused; 361 struct sysmaps *sysmaps; 362 int i; 363 364 /* 365 * XXX The calculation of virtual_avail is wrong. It's NKPT*PAGE_SIZE too 366 * large. It should instead be correctly calculated in locore.s and 367 * not based on 'first' (which is a physical address, not a virtual 368 * address, for the start of unused physical memory). The kernel 369 * page tables are NOT double mapped and thus should not be included 370 * in this calculation. 371 */ 372 virtual_avail = (vm_offset_t) KERNBASE + firstaddr; 373 374 virtual_end = VM_MAX_KERNEL_ADDRESS; 375 376 /* 377 * Initialize the kernel pmap (which is statically allocated). 378 */ 379 PMAP_LOCK_INIT(kernel_pmap); 380 kernel_pmap->pm_pdir = (pd_entry_t *) (KERNBASE + (u_int)IdlePTD); 381#ifdef PAE 382 kernel_pmap->pm_pdpt = (pdpt_entry_t *) (KERNBASE + (u_int)IdlePDPT); 383#endif 384 kernel_pmap->pm_root = NULL; 385 kernel_pmap->pm_active = -1; /* don't allow deactivation */ 386 TAILQ_INIT(&kernel_pmap->pm_pvchunk); 387 LIST_INIT(&allpmaps); 388 389 /* 390 * Request a spin mutex so that changes to allpmaps cannot be 391 * preempted by smp_rendezvous_cpus(). Otherwise, 392 * pmap_update_pde_kernel() could access allpmaps while it is 393 * being changed. 394 */ 395 mtx_init(&allpmaps_lock, "allpmaps", NULL, MTX_SPIN); 396 mtx_lock_spin(&allpmaps_lock); 397 LIST_INSERT_HEAD(&allpmaps, kernel_pmap, pm_list); 398 mtx_unlock_spin(&allpmaps_lock); 399 400 /* 401 * Reserve some special page table entries/VA space for temporary 402 * mapping of pages. 403 */ 404#define SYSMAP(c, p, v, n) \ 405 v = (c)va; va += ((n)*PAGE_SIZE); p = pte; pte += (n); 406 407 va = virtual_avail; 408 pte = vtopte(va); 409 410 /* 411 * CMAP1/CMAP2 are used for zeroing and copying pages. 412 * CMAP3 is used for the idle process page zeroing. 413 */ 414 for (i = 0; i < MAXCPU; i++) { 415 sysmaps = &sysmaps_pcpu[i]; 416 mtx_init(&sysmaps->lock, "SYSMAPS", NULL, MTX_DEF); 417 SYSMAP(caddr_t, sysmaps->CMAP1, sysmaps->CADDR1, 1) 418 SYSMAP(caddr_t, sysmaps->CMAP2, sysmaps->CADDR2, 1) 419 } 420 SYSMAP(caddr_t, CMAP1, CADDR1, 1) 421 SYSMAP(caddr_t, CMAP3, CADDR3, 1) 422 423 /* 424 * Crashdump maps. 425 */ 426 SYSMAP(caddr_t, unused, crashdumpmap, MAXDUMPPGS) 427 428 /* 429 * ptvmmap is used for reading arbitrary physical pages via /dev/mem. 430 */ 431 SYSMAP(caddr_t, unused, ptvmmap, 1) 432 433 /* 434 * msgbufp is used to map the system message buffer. 435 */ 436 SYSMAP(struct msgbuf *, unused, msgbufp, atop(round_page(MSGBUF_SIZE))) 437 438 /* 439 * KPTmap is used by pmap_kextract(). 440 */ 441 SYSMAP(pt_entry_t *, KPTD, KPTmap, KVA_PAGES) 442 443 for (i = 0; i < NKPT; i++) 444 KPTD[i] = (KPTphys + (i << PAGE_SHIFT)) | pgeflag | PG_RW | PG_V; 445 446 /* 447 * Adjust the start of the KPTD and KPTmap so that the implementation 448 * of pmap_kextract() and pmap_growkernel() can be made simpler. 449 */ 450 KPTD -= KPTDI; 451 KPTmap -= i386_btop(KPTDI << PDRSHIFT); 452 453 /* 454 * ptemap is used for pmap_pte_quick 455 */ 456 SYSMAP(pt_entry_t *, PMAP1, PADDR1, 1) 457 SYSMAP(pt_entry_t *, PMAP2, PADDR2, 1) 458 459 mtx_init(&PMAP2mutex, "PMAP2", NULL, MTX_DEF); 460 461 virtual_avail = va; 462 463 /* 464 * Leave in place an identity mapping (virt == phys) for the low 1 MB 465 * physical memory region that is used by the ACPI wakeup code. This 466 * mapping must not have PG_G set. 467 */ 468#ifdef XBOX 469 /* FIXME: This is gross, but needed for the XBOX. Since we are in such 470 * an early stadium, we cannot yet neatly map video memory ... :-( 471 * Better fixes are very welcome! */ 472 if (!arch_i386_is_xbox) 473#endif 474 for (i = 1; i < NKPT; i++) 475 PTD[i] = 0; 476 477 /* Initialize the PAT MSR if present. */ 478 pmap_init_pat(); 479 480 /* Turn on PG_G on kernel page(s) */ 481 pmap_set_pg(); 482} 483 484/* 485 * Setup the PAT MSR. 486 */ 487void 488pmap_init_pat(void) 489{ 490 uint64_t pat_msr; 491 char *sysenv; 492 static int pat_tested = 0; 493 494 /* Bail if this CPU doesn't implement PAT. */ 495 if (!(cpu_feature & CPUID_PAT)) 496 return; 497 498 /* 499 * Due to some Intel errata, we can only safely use the lower 4 500 * PAT entries. 501 * 502 * Intel Pentium III Processor Specification Update 503 * Errata E.27 (Upper Four PAT Entries Not Usable With Mode B 504 * or Mode C Paging) 505 * 506 * Intel Pentium IV Processor Specification Update 507 * Errata N46 (PAT Index MSB May Be Calculated Incorrectly) 508 * 509 * Some Apple Macs based on nVidia chipsets cannot enter ACPI mode 510 * via SMI# when we use upper 4 PAT entries for unknown reason. 511 */ 512 if (!pat_tested) { 513 if (cpu_vendor_id != CPU_VENDOR_INTEL || 514 (CPUID_TO_FAMILY(cpu_id) == 6 && 515 CPUID_TO_MODEL(cpu_id) >= 0xe)) { 516 pat_works = 1; 517 sysenv = getenv("smbios.system.product"); 518 if (sysenv != NULL) { 519 if (strncmp(sysenv, "MacBook5,1", 10) == 0 || 520 strncmp(sysenv, "MacBookPro5,5", 13) == 0 || 521 strncmp(sysenv, "Macmini3,1", 10) == 0) 522 pat_works = 0; 523 freeenv(sysenv); 524 } 525 } 526 pat_tested = 1; 527 } 528 529 /* Initialize default PAT entries. */ 530 pat_msr = PAT_VALUE(0, PAT_WRITE_BACK) | 531 PAT_VALUE(1, PAT_WRITE_THROUGH) | 532 PAT_VALUE(2, PAT_UNCACHED) | 533 PAT_VALUE(3, PAT_UNCACHEABLE) | 534 PAT_VALUE(4, PAT_WRITE_BACK) | 535 PAT_VALUE(5, PAT_WRITE_THROUGH) | 536 PAT_VALUE(6, PAT_UNCACHED) | 537 PAT_VALUE(7, PAT_UNCACHEABLE); 538 539 if (pat_works) { 540 /* 541 * Leave the indices 0-3 at the default of WB, WT, UC-, and UC. 542 * Program 4 and 5 as WP and WC. 543 * Leave 6 and 7 as UC- and UC. 544 */ 545 pat_msr &= ~(PAT_MASK(4) | PAT_MASK(5)); 546 pat_msr |= PAT_VALUE(4, PAT_WRITE_PROTECTED) | 547 PAT_VALUE(5, PAT_WRITE_COMBINING); 548 } else { 549 /* 550 * Just replace PAT Index 2 with WC instead of UC-. 551 */ 552 pat_msr &= ~PAT_MASK(2); 553 pat_msr |= PAT_VALUE(2, PAT_WRITE_COMBINING); 554 } 555 wrmsr(MSR_PAT, pat_msr); 556} 557 558/* 559 * Set PG_G on kernel pages. Only the BSP calls this when SMP is turned on. 560 */ 561static void 562pmap_set_pg(void) 563{ 564 pt_entry_t *pte; 565 vm_offset_t va, endva; 566 567 if (pgeflag == 0) 568 return; 569 570 endva = KERNBASE + KERNend; 571 572 if (pseflag) { 573 va = KERNBASE + KERNLOAD; 574 while (va < endva) { 575 pdir_pde(PTD, va) |= pgeflag; 576 invltlb(); /* Play it safe, invltlb() every time */ 577 va += NBPDR; 578 } 579 } else { 580 va = (vm_offset_t)btext; 581 while (va < endva) { 582 pte = vtopte(va); 583 if (*pte) 584 *pte |= pgeflag; 585 invltlb(); /* Play it safe, invltlb() every time */ 586 va += PAGE_SIZE; 587 } 588 } 589} 590 591/* 592 * Initialize a vm_page's machine-dependent fields. 593 */ 594void 595pmap_page_init(vm_page_t m) 596{ 597 598 TAILQ_INIT(&m->md.pv_list); 599 m->md.pat_mode = PAT_WRITE_BACK; 600} 601 602#ifdef PAE 603static void * 604pmap_pdpt_allocf(uma_zone_t zone, int bytes, u_int8_t *flags, int wait) 605{ 606 607 /* Inform UMA that this allocator uses kernel_map/object. */ 608 *flags = UMA_SLAB_KERNEL; 609 return ((void *)kmem_alloc_contig(kernel_map, bytes, wait, 0x0ULL, 610 0xffffffffULL, 1, 0, VM_MEMATTR_DEFAULT)); 611} 612#endif 613 614/* 615 * ABuse the pte nodes for unmapped kva to thread a kva freelist through. 616 * Requirements: 617 * - Must deal with pages in order to ensure that none of the PG_* bits 618 * are ever set, PG_V in particular. 619 * - Assumes we can write to ptes without pte_store() atomic ops, even 620 * on PAE systems. This should be ok. 621 * - Assumes nothing will ever test these addresses for 0 to indicate 622 * no mapping instead of correctly checking PG_V. 623 * - Assumes a vm_offset_t will fit in a pte (true for i386). 624 * Because PG_V is never set, there can be no mappings to invalidate. 625 */ 626static vm_offset_t 627pmap_ptelist_alloc(vm_offset_t *head) 628{ 629 pt_entry_t *pte; 630 vm_offset_t va; 631 632 va = *head; 633 if (va == 0) 634 return (va); /* Out of memory */ 635 pte = vtopte(va); 636 *head = *pte; 637 if (*head & PG_V) 638 panic("pmap_ptelist_alloc: va with PG_V set!"); 639 *pte = 0; 640 return (va); 641} 642 643static void 644pmap_ptelist_free(vm_offset_t *head, vm_offset_t va) 645{ 646 pt_entry_t *pte; 647 648 if (va & PG_V) 649 panic("pmap_ptelist_free: freeing va with PG_V set!"); 650 pte = vtopte(va); 651 *pte = *head; /* virtual! PG_V is 0 though */ 652 *head = va; 653} 654 655static void 656pmap_ptelist_init(vm_offset_t *head, void *base, int npages) 657{ 658 int i; 659 vm_offset_t va; 660 661 *head = 0; 662 for (i = npages - 1; i >= 0; i--) { 663 va = (vm_offset_t)base + i * PAGE_SIZE; 664 pmap_ptelist_free(head, va); 665 } 666} 667 668 669/* 670 * Initialize the pmap module. 671 * Called by vm_init, to initialize any structures that the pmap 672 * system needs to map virtual memory. 673 */ 674void 675pmap_init(void) 676{ 677 vm_page_t mpte; 678 vm_size_t s; 679 int i, pv_npg; 680 681 /* 682 * Initialize the vm page array entries for the kernel pmap's 683 * page table pages. 684 */ 685 for (i = 0; i < NKPT; i++) { 686 mpte = PHYS_TO_VM_PAGE(KPTphys + (i << PAGE_SHIFT)); 687 KASSERT(mpte >= vm_page_array && 688 mpte < &vm_page_array[vm_page_array_size], 689 ("pmap_init: page table page is out of range")); 690 mpte->pindex = i + KPTDI; 691 mpte->phys_addr = KPTphys + (i << PAGE_SHIFT); 692 } 693 694 /* 695 * Initialize the address space (zone) for the pv entries. Set a 696 * high water mark so that the system can recover from excessive 697 * numbers of pv entries. 698 */ 699 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc); 700 pv_entry_max = shpgperproc * maxproc + cnt.v_page_count; 701 TUNABLE_INT_FETCH("vm.pmap.pv_entries", &pv_entry_max); 702 pv_entry_max = roundup(pv_entry_max, _NPCPV); 703 pv_entry_high_water = 9 * (pv_entry_max / 10); 704 705 /* 706 * If the kernel is running in a virtual machine on an AMD Family 10h 707 * processor, then it must assume that MCA is enabled by the virtual 708 * machine monitor. 709 */ 710 if (vm_guest == VM_GUEST_VM && cpu_vendor_id == CPU_VENDOR_AMD && 711 CPUID_TO_FAMILY(cpu_id) == 0x10) 712 workaround_erratum383 = 1; 713 714 /* 715 * Are large page mappings supported and enabled? 716 */ 717 TUNABLE_INT_FETCH("vm.pmap.pg_ps_enabled", &pg_ps_enabled); 718 if (pseflag == 0) 719 pg_ps_enabled = 0; 720 else if (pg_ps_enabled) { 721 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0, 722 ("pmap_init: can't assign to pagesizes[1]")); 723 pagesizes[1] = NBPDR; 724 } 725 726 /* 727 * Calculate the size of the pv head table for superpages. 728 */ 729 for (i = 0; phys_avail[i + 1]; i += 2); 730 pv_npg = round_4mpage(phys_avail[(i - 2) + 1]) / NBPDR; 731 732 /* 733 * Allocate memory for the pv head table for superpages. 734 */ 735 s = (vm_size_t)(pv_npg * sizeof(struct md_page)); 736 s = round_page(s); 737 pv_table = (struct md_page *)kmem_alloc(kernel_map, s); 738 for (i = 0; i < pv_npg; i++) 739 TAILQ_INIT(&pv_table[i].pv_list); 740 741 pv_maxchunks = MAX(pv_entry_max / _NPCPV, maxproc); 742 pv_chunkbase = (struct pv_chunk *)kmem_alloc_nofault(kernel_map, 743 PAGE_SIZE * pv_maxchunks); 744 if (pv_chunkbase == NULL) 745 panic("pmap_init: not enough kvm for pv chunks"); 746 pmap_ptelist_init(&pv_vafree, pv_chunkbase, pv_maxchunks); 747#ifdef PAE 748 pdptzone = uma_zcreate("PDPT", NPGPTD * sizeof(pdpt_entry_t), NULL, 749 NULL, NULL, NULL, (NPGPTD * sizeof(pdpt_entry_t)) - 1, 750 UMA_ZONE_VM | UMA_ZONE_NOFREE); 751 uma_zone_set_allocf(pdptzone, pmap_pdpt_allocf); 752#endif 753} 754 755 756SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_max, CTLFLAG_RD, &pv_entry_max, 0, 757 "Max number of PV entries"); 758SYSCTL_INT(_vm_pmap, OID_AUTO, shpgperproc, CTLFLAG_RD, &shpgperproc, 0, 759 "Page share factor per proc"); 760 761SYSCTL_NODE(_vm_pmap, OID_AUTO, pde, CTLFLAG_RD, 0, 762 "2/4MB page mapping counters"); 763 764static u_long pmap_pde_demotions; 765SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, demotions, CTLFLAG_RD, 766 &pmap_pde_demotions, 0, "2/4MB page demotions"); 767 768static u_long pmap_pde_mappings; 769SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, mappings, CTLFLAG_RD, 770 &pmap_pde_mappings, 0, "2/4MB page mappings"); 771 772static u_long pmap_pde_p_failures; 773SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, p_failures, CTLFLAG_RD, 774 &pmap_pde_p_failures, 0, "2/4MB page promotion failures"); 775 776static u_long pmap_pde_promotions; 777SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, promotions, CTLFLAG_RD, 778 &pmap_pde_promotions, 0, "2/4MB page promotions"); 779 780/*************************************************** 781 * Low level helper routines..... 782 ***************************************************/ 783 784/* 785 * Determine the appropriate bits to set in a PTE or PDE for a specified 786 * caching mode. 787 */ 788int 789pmap_cache_bits(int mode, boolean_t is_pde) 790{ 791 int pat_flag, pat_index, cache_bits; 792 793 /* The PAT bit is different for PTE's and PDE's. */ 794 pat_flag = is_pde ? PG_PDE_PAT : PG_PTE_PAT; 795 796 /* If we don't support PAT, map extended modes to older ones. */ 797 if (!(cpu_feature & CPUID_PAT)) { 798 switch (mode) { 799 case PAT_UNCACHEABLE: 800 case PAT_WRITE_THROUGH: 801 case PAT_WRITE_BACK: 802 break; 803 case PAT_UNCACHED: 804 case PAT_WRITE_COMBINING: 805 case PAT_WRITE_PROTECTED: 806 mode = PAT_UNCACHEABLE; 807 break; 808 } 809 } 810 811 /* Map the caching mode to a PAT index. */ 812 if (pat_works) { 813 switch (mode) { 814 case PAT_UNCACHEABLE: 815 pat_index = 3; 816 break; 817 case PAT_WRITE_THROUGH: 818 pat_index = 1; 819 break; 820 case PAT_WRITE_BACK: 821 pat_index = 0; 822 break; 823 case PAT_UNCACHED: 824 pat_index = 2; 825 break; 826 case PAT_WRITE_COMBINING: 827 pat_index = 5; 828 break; 829 case PAT_WRITE_PROTECTED: 830 pat_index = 4; 831 break; 832 default: 833 panic("Unknown caching mode %d\n", mode); 834 } 835 } else { 836 switch (mode) { 837 case PAT_UNCACHED: 838 case PAT_UNCACHEABLE: 839 case PAT_WRITE_PROTECTED: 840 pat_index = 3; 841 break; 842 case PAT_WRITE_THROUGH: 843 pat_index = 1; 844 break; 845 case PAT_WRITE_BACK: 846 pat_index = 0; 847 break; 848 case PAT_WRITE_COMBINING: 849 pat_index = 2; 850 break; 851 default: 852 panic("Unknown caching mode %d\n", mode); 853 } 854 } 855 856 /* Map the 3-bit index value into the PAT, PCD, and PWT bits. */ 857 cache_bits = 0; 858 if (pat_index & 0x4) 859 cache_bits |= pat_flag; 860 if (pat_index & 0x2) 861 cache_bits |= PG_NC_PCD; 862 if (pat_index & 0x1) 863 cache_bits |= PG_NC_PWT; 864 return (cache_bits); 865} 866 867/* 868 * The caller is responsible for maintaining TLB consistency. 869 */ 870static void 871pmap_kenter_pde(vm_offset_t va, pd_entry_t newpde) 872{ 873 pd_entry_t *pde; 874 pmap_t pmap; 875 boolean_t PTD_updated; 876 877 PTD_updated = FALSE; 878 mtx_lock_spin(&allpmaps_lock); 879 LIST_FOREACH(pmap, &allpmaps, pm_list) { 880 if ((pmap->pm_pdir[PTDPTDI] & PG_FRAME) == (PTDpde[0] & 881 PG_FRAME)) 882 PTD_updated = TRUE; 883 pde = pmap_pde(pmap, va); 884 pde_store(pde, newpde); 885 } 886 mtx_unlock_spin(&allpmaps_lock); 887 KASSERT(PTD_updated, 888 ("pmap_kenter_pde: current page table is not in allpmaps")); 889} 890 891/* 892 * After changing the page size for the specified virtual address in the page 893 * table, flush the corresponding entries from the processor's TLB. Only the 894 * calling processor's TLB is affected. 895 * 896 * The calling thread must be pinned to a processor. 897 */ 898static void 899pmap_update_pde_invalidate(vm_offset_t va, pd_entry_t newpde) 900{ 901 u_long cr4; 902 903 if ((newpde & PG_PS) == 0) 904 /* Demotion: flush a specific 2MB page mapping. */ 905 invlpg(va); 906 else if ((newpde & PG_G) == 0) 907 /* 908 * Promotion: flush every 4KB page mapping from the TLB 909 * because there are too many to flush individually. 910 */ 911 invltlb(); 912 else { 913 /* 914 * Promotion: flush every 4KB page mapping from the TLB, 915 * including any global (PG_G) mappings. 916 */ 917 cr4 = rcr4(); 918 load_cr4(cr4 & ~CR4_PGE); 919 /* 920 * Although preemption at this point could be detrimental to 921 * performance, it would not lead to an error. PG_G is simply 922 * ignored if CR4.PGE is clear. Moreover, in case this block 923 * is re-entered, the load_cr4() either above or below will 924 * modify CR4.PGE flushing the TLB. 925 */ 926 load_cr4(cr4 | CR4_PGE); 927 } 928} 929#ifdef SMP 930/* 931 * For SMP, these functions have to use the IPI mechanism for coherence. 932 * 933 * N.B.: Before calling any of the following TLB invalidation functions, 934 * the calling processor must ensure that all stores updating a non- 935 * kernel page table are globally performed. Otherwise, another 936 * processor could cache an old, pre-update entry without being 937 * invalidated. This can happen one of two ways: (1) The pmap becomes 938 * active on another processor after its pm_active field is checked by 939 * one of the following functions but before a store updating the page 940 * table is globally performed. (2) The pmap becomes active on another 941 * processor before its pm_active field is checked but due to 942 * speculative loads one of the following functions stills reads the 943 * pmap as inactive on the other processor. 944 * 945 * The kernel page table is exempt because its pm_active field is 946 * immutable. The kernel page table is always active on every 947 * processor. 948 */ 949void 950pmap_invalidate_page(pmap_t pmap, vm_offset_t va) 951{ 952 u_int cpumask; 953 u_int other_cpus; 954 955 sched_pin(); 956 if (pmap == kernel_pmap || pmap->pm_active == all_cpus) { 957 invlpg(va); 958 smp_invlpg(va); 959 } else { 960 cpumask = PCPU_GET(cpumask); 961 other_cpus = PCPU_GET(other_cpus); 962 if (pmap->pm_active & cpumask) 963 invlpg(va); 964 if (pmap->pm_active & other_cpus) 965 smp_masked_invlpg(pmap->pm_active & other_cpus, va); 966 } 967 sched_unpin(); 968} 969 970void 971pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 972{ 973 u_int cpumask; 974 u_int other_cpus; 975 vm_offset_t addr; 976 977 sched_pin(); 978 if (pmap == kernel_pmap || pmap->pm_active == all_cpus) { 979 for (addr = sva; addr < eva; addr += PAGE_SIZE) 980 invlpg(addr); 981 smp_invlpg_range(sva, eva); 982 } else { 983 cpumask = PCPU_GET(cpumask); 984 other_cpus = PCPU_GET(other_cpus); 985 if (pmap->pm_active & cpumask) 986 for (addr = sva; addr < eva; addr += PAGE_SIZE) 987 invlpg(addr); 988 if (pmap->pm_active & other_cpus) 989 smp_masked_invlpg_range(pmap->pm_active & other_cpus, 990 sva, eva); 991 } 992 sched_unpin(); 993} 994 995void 996pmap_invalidate_all(pmap_t pmap) 997{ 998 u_int cpumask; 999 u_int other_cpus; 1000 1001 sched_pin(); 1002 if (pmap == kernel_pmap || pmap->pm_active == all_cpus) { 1003 invltlb(); 1004 smp_invltlb(); 1005 } else { 1006 cpumask = PCPU_GET(cpumask); 1007 other_cpus = PCPU_GET(other_cpus); 1008 if (pmap->pm_active & cpumask) 1009 invltlb(); 1010 if (pmap->pm_active & other_cpus) 1011 smp_masked_invltlb(pmap->pm_active & other_cpus); 1012 } 1013 sched_unpin(); 1014} 1015 1016void 1017pmap_invalidate_cache(void) 1018{ 1019 1020 sched_pin(); 1021 wbinvd(); 1022 smp_cache_flush(); 1023 sched_unpin(); 1024} 1025 1026struct pde_action { 1027 cpumask_t store; /* processor that updates the PDE */ 1028 cpumask_t invalidate; /* processors that invalidate their TLB */ 1029 vm_offset_t va; 1030 pd_entry_t *pde; 1031 pd_entry_t newpde; 1032}; 1033 1034static void 1035pmap_update_pde_kernel(void *arg) 1036{ 1037 struct pde_action *act = arg; 1038 pd_entry_t *pde; 1039 pmap_t pmap; 1040 1041 if (act->store == PCPU_GET(cpumask)) 1042 /* 1043 * Elsewhere, this operation requires allpmaps_lock for 1044 * synchronization. Here, it does not because it is being 1045 * performed in the context of an all_cpus rendezvous. 1046 */ 1047 LIST_FOREACH(pmap, &allpmaps, pm_list) { 1048 pde = pmap_pde(pmap, act->va); 1049 pde_store(pde, act->newpde); 1050 } 1051} 1052 1053static void 1054pmap_update_pde_user(void *arg) 1055{ 1056 struct pde_action *act = arg; 1057 1058 if (act->store == PCPU_GET(cpumask)) 1059 pde_store(act->pde, act->newpde); 1060} 1061 1062static void 1063pmap_update_pde_teardown(void *arg) 1064{ 1065 struct pde_action *act = arg; 1066 1067 if ((act->invalidate & PCPU_GET(cpumask)) != 0) 1068 pmap_update_pde_invalidate(act->va, act->newpde); 1069} 1070 1071/* 1072 * Change the page size for the specified virtual address in a way that 1073 * prevents any possibility of the TLB ever having two entries that map the 1074 * same virtual address using different page sizes. This is the recommended 1075 * workaround for Erratum 383 on AMD Family 10h processors. It prevents a 1076 * machine check exception for a TLB state that is improperly diagnosed as a 1077 * hardware error. 1078 */ 1079static void 1080pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde) 1081{ 1082 struct pde_action act; 1083 cpumask_t active, cpumask; 1084 1085 sched_pin(); 1086 cpumask = PCPU_GET(cpumask); 1087 if (pmap == kernel_pmap) 1088 active = all_cpus; 1089 else 1090 active = pmap->pm_active; 1091 if ((active & PCPU_GET(other_cpus)) != 0) { 1092 act.store = cpumask; 1093 act.invalidate = active; 1094 act.va = va; 1095 act.pde = pde; 1096 act.newpde = newpde; 1097 smp_rendezvous_cpus(cpumask | active, 1098 smp_no_rendevous_barrier, pmap == kernel_pmap ? 1099 pmap_update_pde_kernel : pmap_update_pde_user, 1100 pmap_update_pde_teardown, &act); 1101 } else { 1102 if (pmap == kernel_pmap) 1103 pmap_kenter_pde(va, newpde); 1104 else 1105 pde_store(pde, newpde); 1106 if ((active & cpumask) != 0) 1107 pmap_update_pde_invalidate(va, newpde); 1108 } 1109 sched_unpin(); 1110} 1111#else /* !SMP */ 1112/* 1113 * Normal, non-SMP, 486+ invalidation functions. 1114 * We inline these within pmap.c for speed. 1115 */ 1116PMAP_INLINE void 1117pmap_invalidate_page(pmap_t pmap, vm_offset_t va) 1118{ 1119 1120 if (pmap == kernel_pmap || pmap->pm_active) 1121 invlpg(va); 1122} 1123 1124PMAP_INLINE void 1125pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 1126{ 1127 vm_offset_t addr; 1128 1129 if (pmap == kernel_pmap || pmap->pm_active) 1130 for (addr = sva; addr < eva; addr += PAGE_SIZE) 1131 invlpg(addr); 1132} 1133 1134PMAP_INLINE void 1135pmap_invalidate_all(pmap_t pmap) 1136{ 1137 1138 if (pmap == kernel_pmap || pmap->pm_active) 1139 invltlb(); 1140} 1141 1142PMAP_INLINE void 1143pmap_invalidate_cache(void) 1144{ 1145 1146 wbinvd(); 1147} 1148 1149static void 1150pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde) 1151{ 1152 1153 if (pmap == kernel_pmap) 1154 pmap_kenter_pde(va, newpde); 1155 else 1156 pde_store(pde, newpde); 1157 if (pmap == kernel_pmap || pmap->pm_active) 1158 pmap_update_pde_invalidate(va, newpde); 1159} 1160#endif /* !SMP */ 1161 1162void 1163pmap_invalidate_cache_range(vm_offset_t sva, vm_offset_t eva) 1164{ 1165 1166 KASSERT((sva & PAGE_MASK) == 0, 1167 ("pmap_invalidate_cache_range: sva not page-aligned")); 1168 KASSERT((eva & PAGE_MASK) == 0, 1169 ("pmap_invalidate_cache_range: eva not page-aligned")); 1170 1171 if (cpu_feature & CPUID_SS) 1172 ; /* If "Self Snoop" is supported, do nothing. */ 1173 else if ((cpu_feature & CPUID_CLFSH) != 0 && 1174 eva - sva < 2 * 1024 * 1024) { 1175 1176 /* 1177 * Otherwise, do per-cache line flush. Use the mfence 1178 * instruction to insure that previous stores are 1179 * included in the write-back. The processor 1180 * propagates flush to other processors in the cache 1181 * coherence domain. 1182 */ 1183 mfence(); 1184 for (; sva < eva; sva += cpu_clflush_line_size) 1185 clflush(sva); 1186 mfence(); 1187 } else { 1188 1189 /* 1190 * No targeted cache flush methods are supported by CPU, 1191 * or the supplied range is bigger than 2MB. 1192 * Globally invalidate cache. 1193 */ 1194 pmap_invalidate_cache(); 1195 } 1196} 1197 1198/* 1199 * Are we current address space or kernel? N.B. We return FALSE when 1200 * a pmap's page table is in use because a kernel thread is borrowing 1201 * it. The borrowed page table can change spontaneously, making any 1202 * dependence on its continued use subject to a race condition. 1203 */ 1204static __inline int 1205pmap_is_current(pmap_t pmap) 1206{ 1207 1208 return (pmap == kernel_pmap || 1209 (pmap == vmspace_pmap(curthread->td_proc->p_vmspace) && 1210 (pmap->pm_pdir[PTDPTDI] & PG_FRAME) == (PTDpde[0] & PG_FRAME))); 1211} 1212 1213/* 1214 * If the given pmap is not the current or kernel pmap, the returned pte must 1215 * be released by passing it to pmap_pte_release(). 1216 */ 1217pt_entry_t * 1218pmap_pte(pmap_t pmap, vm_offset_t va) 1219{ 1220 pd_entry_t newpf; 1221 pd_entry_t *pde; 1222 1223 pde = pmap_pde(pmap, va); 1224 if (*pde & PG_PS) 1225 return (pde); 1226 if (*pde != 0) { 1227 /* are we current address space or kernel? */ 1228 if (pmap_is_current(pmap)) 1229 return (vtopte(va)); 1230 mtx_lock(&PMAP2mutex); 1231 newpf = *pde & PG_FRAME; 1232 if ((*PMAP2 & PG_FRAME) != newpf) { 1233 *PMAP2 = newpf | PG_RW | PG_V | PG_A | PG_M; 1234 pmap_invalidate_page(kernel_pmap, (vm_offset_t)PADDR2); 1235 } 1236 return (PADDR2 + (i386_btop(va) & (NPTEPG - 1))); 1237 } 1238 return (0); 1239} 1240 1241/* 1242 * Releases a pte that was obtained from pmap_pte(). Be prepared for the pte 1243 * being NULL. 1244 */ 1245static __inline void 1246pmap_pte_release(pt_entry_t *pte) 1247{ 1248 1249 if ((pt_entry_t *)((vm_offset_t)pte & ~PAGE_MASK) == PADDR2) 1250 mtx_unlock(&PMAP2mutex); 1251} 1252 1253static __inline void 1254invlcaddr(void *caddr) 1255{ 1256 1257 invlpg((u_int)caddr); 1258} 1259 1260/* 1261 * Super fast pmap_pte routine best used when scanning 1262 * the pv lists. This eliminates many coarse-grained 1263 * invltlb calls. Note that many of the pv list 1264 * scans are across different pmaps. It is very wasteful 1265 * to do an entire invltlb for checking a single mapping. 1266 * 1267 * If the given pmap is not the current pmap, vm_page_queue_mtx 1268 * must be held and curthread pinned to a CPU. 1269 */ 1270static pt_entry_t * 1271pmap_pte_quick(pmap_t pmap, vm_offset_t va) 1272{ 1273 pd_entry_t newpf; 1274 pd_entry_t *pde; 1275 1276 pde = pmap_pde(pmap, va); 1277 if (*pde & PG_PS) 1278 return (pde); 1279 if (*pde != 0) { 1280 /* are we current address space or kernel? */ 1281 if (pmap_is_current(pmap)) 1282 return (vtopte(va)); 1283 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1284 KASSERT(curthread->td_pinned > 0, ("curthread not pinned")); 1285 newpf = *pde & PG_FRAME; 1286 if ((*PMAP1 & PG_FRAME) != newpf) { 1287 *PMAP1 = newpf | PG_RW | PG_V | PG_A | PG_M; 1288#ifdef SMP 1289 PMAP1cpu = PCPU_GET(cpuid); 1290#endif 1291 invlcaddr(PADDR1); 1292 PMAP1changed++; 1293 } else 1294#ifdef SMP 1295 if (PMAP1cpu != PCPU_GET(cpuid)) { 1296 PMAP1cpu = PCPU_GET(cpuid); 1297 invlcaddr(PADDR1); 1298 PMAP1changedcpu++; 1299 } else 1300#endif 1301 PMAP1unchanged++; 1302 return (PADDR1 + (i386_btop(va) & (NPTEPG - 1))); 1303 } 1304 return (0); 1305} 1306 1307/* 1308 * Routine: pmap_extract 1309 * Function: 1310 * Extract the physical page address associated 1311 * with the given map/virtual_address pair. 1312 */ 1313vm_paddr_t 1314pmap_extract(pmap_t pmap, vm_offset_t va) 1315{ 1316 vm_paddr_t rtval; 1317 pt_entry_t *pte; 1318 pd_entry_t pde; 1319 1320 rtval = 0; 1321 PMAP_LOCK(pmap); 1322 pde = pmap->pm_pdir[va >> PDRSHIFT]; 1323 if (pde != 0) { 1324 if ((pde & PG_PS) != 0) 1325 rtval = (pde & PG_PS_FRAME) | (va & PDRMASK); 1326 else { 1327 pte = pmap_pte(pmap, va); 1328 rtval = (*pte & PG_FRAME) | (va & PAGE_MASK); 1329 pmap_pte_release(pte); 1330 } 1331 } 1332 PMAP_UNLOCK(pmap); 1333 return (rtval); 1334} 1335 1336/* 1337 * Routine: pmap_extract_and_hold 1338 * Function: 1339 * Atomically extract and hold the physical page 1340 * with the given pmap and virtual address pair 1341 * if that mapping permits the given protection. 1342 */ 1343vm_page_t 1344pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot) 1345{ 1346 pd_entry_t pde; 1347 pt_entry_t pte; 1348 vm_page_t m; 1349 vm_paddr_t pa; 1350 1351 pa = 0; 1352 m = NULL; 1353 PMAP_LOCK(pmap); 1354retry: 1355 pde = *pmap_pde(pmap, va); 1356 if (pde != 0) { 1357 if (pde & PG_PS) { 1358 if ((pde & PG_RW) || (prot & VM_PROT_WRITE) == 0) { 1359 if (vm_page_pa_tryrelock(pmap, (pde & PG_PS_FRAME) | 1360 (va & PDRMASK), &pa)) 1361 goto retry; 1362 m = PHYS_TO_VM_PAGE((pde & PG_PS_FRAME) | 1363 (va & PDRMASK)); 1364 vm_page_hold(m); 1365 } 1366 } else { 1367 sched_pin(); 1368 pte = *pmap_pte_quick(pmap, va); 1369 if (pte != 0 && 1370 ((pte & PG_RW) || (prot & VM_PROT_WRITE) == 0)) { 1371 if (vm_page_pa_tryrelock(pmap, pte & PG_FRAME, &pa)) 1372 goto retry; 1373 m = PHYS_TO_VM_PAGE(pte & PG_FRAME); 1374 vm_page_hold(m); 1375 } 1376 sched_unpin(); 1377 } 1378 } 1379 PA_UNLOCK_COND(pa); 1380 PMAP_UNLOCK(pmap); 1381 return (m); 1382} 1383 1384/*************************************************** 1385 * Low level mapping routines..... 1386 ***************************************************/ 1387 1388/* 1389 * Add a wired page to the kva. 1390 * Note: not SMP coherent. 1391 */ 1392PMAP_INLINE void 1393pmap_kenter(vm_offset_t va, vm_paddr_t pa) 1394{ 1395 pt_entry_t *pte; 1396 1397 pte = vtopte(va); 1398 pte_store(pte, pa | PG_RW | PG_V | pgeflag); 1399} 1400 1401static __inline void 1402pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode) 1403{ 1404 pt_entry_t *pte; 1405 1406 pte = vtopte(va); 1407 pte_store(pte, pa | PG_RW | PG_V | pgeflag | pmap_cache_bits(mode, 0)); 1408} 1409 1410/* 1411 * Remove a page from the kernel pagetables. 1412 * Note: not SMP coherent. 1413 */ 1414PMAP_INLINE void 1415pmap_kremove(vm_offset_t va) 1416{ 1417 pt_entry_t *pte; 1418 1419 pte = vtopte(va); 1420 pte_clear(pte); 1421} 1422 1423/* 1424 * Used to map a range of physical addresses into kernel 1425 * virtual address space. 1426 * 1427 * The value passed in '*virt' is a suggested virtual address for 1428 * the mapping. Architectures which can support a direct-mapped 1429 * physical to virtual region can return the appropriate address 1430 * within that region, leaving '*virt' unchanged. Other 1431 * architectures should map the pages starting at '*virt' and 1432 * update '*virt' with the first usable address after the mapped 1433 * region. 1434 */ 1435vm_offset_t 1436pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot) 1437{ 1438 vm_offset_t va, sva; 1439 1440 va = sva = *virt; 1441 while (start < end) { 1442 pmap_kenter(va, start); 1443 va += PAGE_SIZE; 1444 start += PAGE_SIZE; 1445 } 1446 pmap_invalidate_range(kernel_pmap, sva, va); 1447 *virt = va; 1448 return (sva); 1449} 1450 1451 1452/* 1453 * Add a list of wired pages to the kva 1454 * this routine is only used for temporary 1455 * kernel mappings that do not need to have 1456 * page modification or references recorded. 1457 * Note that old mappings are simply written 1458 * over. The page *must* be wired. 1459 * Note: SMP coherent. Uses a ranged shootdown IPI. 1460 */ 1461void 1462pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count) 1463{ 1464 pt_entry_t *endpte, oldpte, *pte; 1465 1466 oldpte = 0; 1467 pte = vtopte(sva); 1468 endpte = pte + count; 1469 while (pte < endpte) { 1470 oldpte |= *pte; 1471 pte_store(pte, VM_PAGE_TO_PHYS(*ma) | pgeflag | 1472 pmap_cache_bits((*ma)->md.pat_mode, 0) | PG_RW | PG_V); 1473 pte++; 1474 ma++; 1475 } 1476 if ((oldpte & PG_V) != 0) 1477 pmap_invalidate_range(kernel_pmap, sva, sva + count * 1478 PAGE_SIZE); 1479} 1480 1481/* 1482 * This routine tears out page mappings from the 1483 * kernel -- it is meant only for temporary mappings. 1484 * Note: SMP coherent. Uses a ranged shootdown IPI. 1485 */ 1486void 1487pmap_qremove(vm_offset_t sva, int count) 1488{ 1489 vm_offset_t va; 1490 1491 va = sva; 1492 while (count-- > 0) { 1493 pmap_kremove(va); 1494 va += PAGE_SIZE; 1495 } 1496 pmap_invalidate_range(kernel_pmap, sva, va); 1497} 1498 1499/*************************************************** 1500 * Page table page management routines..... 1501 ***************************************************/ 1502static __inline void 1503pmap_free_zero_pages(vm_page_t free) 1504{ 1505 vm_page_t m; 1506 1507 while (free != NULL) { 1508 m = free; 1509 free = m->right; 1510 /* Preserve the page's PG_ZERO setting. */ 1511 vm_page_free_toq(m); 1512 } 1513} 1514 1515/* 1516 * Schedule the specified unused page table page to be freed. Specifically, 1517 * add the page to the specified list of pages that will be released to the 1518 * physical memory manager after the TLB has been updated. 1519 */ 1520static __inline void 1521pmap_add_delayed_free_list(vm_page_t m, vm_page_t *free, boolean_t set_PG_ZERO) 1522{ 1523 1524 if (set_PG_ZERO) 1525 m->flags |= PG_ZERO; 1526 else 1527 m->flags &= ~PG_ZERO; 1528 m->right = *free; 1529 *free = m; 1530} 1531 1532/* 1533 * Inserts the specified page table page into the specified pmap's collection 1534 * of idle page table pages. Each of a pmap's page table pages is responsible 1535 * for mapping a distinct range of virtual addresses. The pmap's collection is 1536 * ordered by this virtual address range. 1537 */ 1538static void 1539pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte) 1540{ 1541 vm_page_t root; 1542 1543 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1544 root = pmap->pm_root; 1545 if (root == NULL) { 1546 mpte->left = NULL; 1547 mpte->right = NULL; 1548 } else { 1549 root = vm_page_splay(mpte->pindex, root); 1550 if (mpte->pindex < root->pindex) { 1551 mpte->left = root->left; 1552 mpte->right = root; 1553 root->left = NULL; 1554 } else if (mpte->pindex == root->pindex) 1555 panic("pmap_insert_pt_page: pindex already inserted"); 1556 else { 1557 mpte->right = root->right; 1558 mpte->left = root; 1559 root->right = NULL; 1560 } 1561 } 1562 pmap->pm_root = mpte; 1563} 1564 1565/* 1566 * Looks for a page table page mapping the specified virtual address in the 1567 * specified pmap's collection of idle page table pages. Returns NULL if there 1568 * is no page table page corresponding to the specified virtual address. 1569 */ 1570static vm_page_t 1571pmap_lookup_pt_page(pmap_t pmap, vm_offset_t va) 1572{ 1573 vm_page_t mpte; 1574 vm_pindex_t pindex = va >> PDRSHIFT; 1575 1576 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1577 if ((mpte = pmap->pm_root) != NULL && mpte->pindex != pindex) { 1578 mpte = vm_page_splay(pindex, mpte); 1579 if ((pmap->pm_root = mpte)->pindex != pindex) 1580 mpte = NULL; 1581 } 1582 return (mpte); 1583} 1584 1585/* 1586 * Removes the specified page table page from the specified pmap's collection 1587 * of idle page table pages. The specified page table page must be a member of 1588 * the pmap's collection. 1589 */ 1590static void 1591pmap_remove_pt_page(pmap_t pmap, vm_page_t mpte) 1592{ 1593 vm_page_t root; 1594 1595 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1596 if (mpte != pmap->pm_root) 1597 vm_page_splay(mpte->pindex, pmap->pm_root); 1598 if (mpte->left == NULL) 1599 root = mpte->right; 1600 else { 1601 root = vm_page_splay(mpte->pindex, mpte->left); 1602 root->right = mpte->right; 1603 } 1604 pmap->pm_root = root; 1605} 1606 1607/* 1608 * This routine unholds page table pages, and if the hold count 1609 * drops to zero, then it decrements the wire count. 1610 */ 1611static __inline int 1612pmap_unwire_pte_hold(pmap_t pmap, vm_page_t m, vm_page_t *free) 1613{ 1614 1615 --m->wire_count; 1616 if (m->wire_count == 0) 1617 return (_pmap_unwire_pte_hold(pmap, m, free)); 1618 else 1619 return (0); 1620} 1621 1622static int 1623_pmap_unwire_pte_hold(pmap_t pmap, vm_page_t m, vm_page_t *free) 1624{ 1625 vm_offset_t pteva; 1626 1627 /* 1628 * unmap the page table page 1629 */ 1630 pmap->pm_pdir[m->pindex] = 0; 1631 --pmap->pm_stats.resident_count; 1632 1633 /* 1634 * This is a release store so that the ordinary store unmapping 1635 * the page table page is globally performed before TLB shoot- 1636 * down is begun. 1637 */ 1638 atomic_subtract_rel_int(&cnt.v_wire_count, 1); 1639 1640 /* 1641 * Do an invltlb to make the invalidated mapping 1642 * take effect immediately. 1643 */ 1644 pteva = VM_MAXUSER_ADDRESS + i386_ptob(m->pindex); 1645 pmap_invalidate_page(pmap, pteva); 1646 1647 /* 1648 * Put page on a list so that it is released after 1649 * *ALL* TLB shootdown is done 1650 */ 1651 pmap_add_delayed_free_list(m, free, TRUE); 1652 1653 return (1); 1654} 1655 1656/* 1657 * After removing a page table entry, this routine is used to 1658 * conditionally free the page, and manage the hold/wire counts. 1659 */ 1660static int 1661pmap_unuse_pt(pmap_t pmap, vm_offset_t va, vm_page_t *free) 1662{ 1663 pd_entry_t ptepde; 1664 vm_page_t mpte; 1665 1666 if (va >= VM_MAXUSER_ADDRESS) 1667 return (0); 1668 ptepde = *pmap_pde(pmap, va); 1669 mpte = PHYS_TO_VM_PAGE(ptepde & PG_FRAME); 1670 return (pmap_unwire_pte_hold(pmap, mpte, free)); 1671} 1672 1673void 1674pmap_pinit0(pmap_t pmap) 1675{ 1676 1677 PMAP_LOCK_INIT(pmap); 1678 pmap->pm_pdir = (pd_entry_t *)(KERNBASE + (vm_offset_t)IdlePTD); 1679#ifdef PAE 1680 pmap->pm_pdpt = (pdpt_entry_t *)(KERNBASE + (vm_offset_t)IdlePDPT); 1681#endif 1682 pmap->pm_root = NULL; 1683 pmap->pm_active = 0; 1684 PCPU_SET(curpmap, pmap); 1685 TAILQ_INIT(&pmap->pm_pvchunk); 1686 bzero(&pmap->pm_stats, sizeof pmap->pm_stats); 1687 mtx_lock_spin(&allpmaps_lock); 1688 LIST_INSERT_HEAD(&allpmaps, pmap, pm_list); 1689 mtx_unlock_spin(&allpmaps_lock); 1690} 1691 1692/* 1693 * Initialize a preallocated and zeroed pmap structure, 1694 * such as one in a vmspace structure. 1695 */ 1696int 1697pmap_pinit(pmap_t pmap) 1698{ 1699 vm_page_t m, ptdpg[NPGPTD]; 1700 vm_paddr_t pa; 1701 static int color; 1702 int i; 1703 1704 PMAP_LOCK_INIT(pmap); 1705 1706 /* 1707 * No need to allocate page table space yet but we do need a valid 1708 * page directory table. 1709 */ 1710 if (pmap->pm_pdir == NULL) { 1711 pmap->pm_pdir = (pd_entry_t *)kmem_alloc_nofault(kernel_map, 1712 NBPTD); 1713 1714 if (pmap->pm_pdir == NULL) { 1715 PMAP_LOCK_DESTROY(pmap); 1716 return (0); 1717 } 1718#ifdef PAE 1719 pmap->pm_pdpt = uma_zalloc(pdptzone, M_WAITOK | M_ZERO); 1720 KASSERT(((vm_offset_t)pmap->pm_pdpt & 1721 ((NPGPTD * sizeof(pdpt_entry_t)) - 1)) == 0, 1722 ("pmap_pinit: pdpt misaligned")); 1723 KASSERT(pmap_kextract((vm_offset_t)pmap->pm_pdpt) < (4ULL<<30), 1724 ("pmap_pinit: pdpt above 4g")); 1725#endif 1726 pmap->pm_root = NULL; 1727 } 1728 KASSERT(pmap->pm_root == NULL, 1729 ("pmap_pinit: pmap has reserved page table page(s)")); 1730 1731 /* 1732 * allocate the page directory page(s) 1733 */ 1734 for (i = 0; i < NPGPTD;) { 1735 m = vm_page_alloc(NULL, color++, 1736 VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | 1737 VM_ALLOC_ZERO); 1738 if (m == NULL) 1739 VM_WAIT; 1740 else { 1741 ptdpg[i++] = m; 1742 } 1743 } 1744 1745 pmap_qenter((vm_offset_t)pmap->pm_pdir, ptdpg, NPGPTD); 1746 1747 for (i = 0; i < NPGPTD; i++) { 1748 if ((ptdpg[i]->flags & PG_ZERO) == 0) 1749 bzero(pmap->pm_pdir + (i * NPDEPG), PAGE_SIZE); 1750 } 1751 1752 mtx_lock_spin(&allpmaps_lock); 1753 LIST_INSERT_HEAD(&allpmaps, pmap, pm_list); 1754 mtx_unlock_spin(&allpmaps_lock); 1755 /* Wire in kernel global address entries. */ 1756 bcopy(PTD + KPTDI, pmap->pm_pdir + KPTDI, nkpt * sizeof(pd_entry_t)); 1757 1758 /* install self-referential address mapping entry(s) */ 1759 for (i = 0; i < NPGPTD; i++) { 1760 pa = VM_PAGE_TO_PHYS(ptdpg[i]); 1761 pmap->pm_pdir[PTDPTDI + i] = pa | PG_V | PG_RW | PG_A | PG_M; 1762#ifdef PAE 1763 pmap->pm_pdpt[i] = pa | PG_V; 1764#endif 1765 } 1766 1767 pmap->pm_active = 0; 1768 TAILQ_INIT(&pmap->pm_pvchunk); 1769 bzero(&pmap->pm_stats, sizeof pmap->pm_stats); 1770 1771 return (1); 1772} 1773 1774/* 1775 * this routine is called if the page table page is not 1776 * mapped correctly. 1777 */ 1778static vm_page_t 1779_pmap_allocpte(pmap_t pmap, unsigned ptepindex, int flags) 1780{ 1781 vm_paddr_t ptepa; 1782 vm_page_t m; 1783 1784 KASSERT((flags & (M_NOWAIT | M_WAITOK)) == M_NOWAIT || 1785 (flags & (M_NOWAIT | M_WAITOK)) == M_WAITOK, 1786 ("_pmap_allocpte: flags is neither M_NOWAIT nor M_WAITOK")); 1787 1788 /* 1789 * Allocate a page table page. 1790 */ 1791 if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ | 1792 VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) { 1793 if (flags & M_WAITOK) { 1794 PMAP_UNLOCK(pmap); 1795 vm_page_unlock_queues(); 1796 VM_WAIT; 1797 vm_page_lock_queues(); 1798 PMAP_LOCK(pmap); 1799 } 1800 1801 /* 1802 * Indicate the need to retry. While waiting, the page table 1803 * page may have been allocated. 1804 */ 1805 return (NULL); 1806 } 1807 if ((m->flags & PG_ZERO) == 0) 1808 pmap_zero_page(m); 1809 1810 /* 1811 * Map the pagetable page into the process address space, if 1812 * it isn't already there. 1813 */ 1814 1815 pmap->pm_stats.resident_count++; 1816 1817 ptepa = VM_PAGE_TO_PHYS(m); 1818 pmap->pm_pdir[ptepindex] = 1819 (pd_entry_t) (ptepa | PG_U | PG_RW | PG_V | PG_A | PG_M); 1820 1821 return (m); 1822} 1823 1824static vm_page_t 1825pmap_allocpte(pmap_t pmap, vm_offset_t va, int flags) 1826{ 1827 unsigned ptepindex; 1828 pd_entry_t ptepa; 1829 vm_page_t m; 1830 1831 KASSERT((flags & (M_NOWAIT | M_WAITOK)) == M_NOWAIT || 1832 (flags & (M_NOWAIT | M_WAITOK)) == M_WAITOK, 1833 ("pmap_allocpte: flags is neither M_NOWAIT nor M_WAITOK")); 1834 1835 /* 1836 * Calculate pagetable page index 1837 */ 1838 ptepindex = va >> PDRSHIFT; 1839retry: 1840 /* 1841 * Get the page directory entry 1842 */ 1843 ptepa = pmap->pm_pdir[ptepindex]; 1844 1845 /* 1846 * This supports switching from a 4MB page to a 1847 * normal 4K page. 1848 */ 1849 if (ptepa & PG_PS) { 1850 (void)pmap_demote_pde(pmap, &pmap->pm_pdir[ptepindex], va); 1851 ptepa = pmap->pm_pdir[ptepindex]; 1852 } 1853 1854 /* 1855 * If the page table page is mapped, we just increment the 1856 * hold count, and activate it. 1857 */ 1858 if (ptepa) { 1859 m = PHYS_TO_VM_PAGE(ptepa & PG_FRAME); 1860 m->wire_count++; 1861 } else { 1862 /* 1863 * Here if the pte page isn't mapped, or if it has 1864 * been deallocated. 1865 */ 1866 m = _pmap_allocpte(pmap, ptepindex, flags); 1867 if (m == NULL && (flags & M_WAITOK)) 1868 goto retry; 1869 } 1870 return (m); 1871} 1872 1873 1874/*************************************************** 1875* Pmap allocation/deallocation routines. 1876 ***************************************************/ 1877 1878#ifdef SMP 1879/* 1880 * Deal with a SMP shootdown of other users of the pmap that we are 1881 * trying to dispose of. This can be a bit hairy. 1882 */ 1883static cpumask_t *lazymask; 1884static u_int lazyptd; 1885static volatile u_int lazywait; 1886 1887void pmap_lazyfix_action(void); 1888 1889void 1890pmap_lazyfix_action(void) 1891{ 1892 cpumask_t mymask = PCPU_GET(cpumask); 1893 1894#ifdef COUNT_IPIS 1895 (*ipi_lazypmap_counts[PCPU_GET(cpuid)])++; 1896#endif 1897 if (rcr3() == lazyptd) 1898 load_cr3(PCPU_GET(curpcb)->pcb_cr3); 1899 atomic_clear_int(lazymask, mymask); 1900 atomic_store_rel_int(&lazywait, 1); 1901} 1902 1903static void 1904pmap_lazyfix_self(cpumask_t mymask) 1905{ 1906 1907 if (rcr3() == lazyptd) 1908 load_cr3(PCPU_GET(curpcb)->pcb_cr3); 1909 atomic_clear_int(lazymask, mymask); 1910} 1911 1912 1913static void 1914pmap_lazyfix(pmap_t pmap) 1915{ 1916 cpumask_t mymask, mask; 1917 u_int spins; 1918 1919 while ((mask = pmap->pm_active) != 0) { 1920 spins = 50000000; 1921 mask = mask & -mask; /* Find least significant set bit */ 1922 mtx_lock_spin(&smp_ipi_mtx); 1923#ifdef PAE 1924 lazyptd = vtophys(pmap->pm_pdpt); 1925#else 1926 lazyptd = vtophys(pmap->pm_pdir); 1927#endif 1928 mymask = PCPU_GET(cpumask); 1929 if (mask == mymask) { 1930 lazymask = &pmap->pm_active; 1931 pmap_lazyfix_self(mymask); 1932 } else { 1933 atomic_store_rel_int((u_int *)&lazymask, 1934 (u_int)&pmap->pm_active); 1935 atomic_store_rel_int(&lazywait, 0); 1936 ipi_selected(mask, IPI_LAZYPMAP); 1937 while (lazywait == 0) { 1938 ia32_pause(); 1939 if (--spins == 0) 1940 break; 1941 } 1942 } 1943 mtx_unlock_spin(&smp_ipi_mtx); 1944 if (spins == 0) 1945 printf("pmap_lazyfix: spun for 50000000\n"); 1946 } 1947} 1948 1949#else /* SMP */ 1950 1951/* 1952 * Cleaning up on uniprocessor is easy. For various reasons, we're 1953 * unlikely to have to even execute this code, including the fact 1954 * that the cleanup is deferred until the parent does a wait(2), which 1955 * means that another userland process has run. 1956 */ 1957static void 1958pmap_lazyfix(pmap_t pmap) 1959{ 1960 u_int cr3; 1961 1962 cr3 = vtophys(pmap->pm_pdir); 1963 if (cr3 == rcr3()) { 1964 load_cr3(PCPU_GET(curpcb)->pcb_cr3); 1965 pmap->pm_active &= ~(PCPU_GET(cpumask)); 1966 } 1967} 1968#endif /* SMP */ 1969 1970/* 1971 * Release any resources held by the given physical map. 1972 * Called when a pmap initialized by pmap_pinit is being released. 1973 * Should only be called if the map contains no valid mappings. 1974 */ 1975void 1976pmap_release(pmap_t pmap) 1977{ 1978 vm_page_t m, ptdpg[NPGPTD]; 1979 int i; 1980 1981 KASSERT(pmap->pm_stats.resident_count == 0, 1982 ("pmap_release: pmap resident count %ld != 0", 1983 pmap->pm_stats.resident_count)); 1984 KASSERT(pmap->pm_root == NULL, 1985 ("pmap_release: pmap has reserved page table page(s)")); 1986 1987 pmap_lazyfix(pmap); 1988 mtx_lock_spin(&allpmaps_lock); 1989 LIST_REMOVE(pmap, pm_list); 1990 mtx_unlock_spin(&allpmaps_lock); 1991 1992 for (i = 0; i < NPGPTD; i++) 1993 ptdpg[i] = PHYS_TO_VM_PAGE(pmap->pm_pdir[PTDPTDI + i] & 1994 PG_FRAME); 1995 1996 bzero(pmap->pm_pdir + PTDPTDI, (nkpt + NPGPTD) * 1997 sizeof(*pmap->pm_pdir)); 1998 1999 pmap_qremove((vm_offset_t)pmap->pm_pdir, NPGPTD); 2000 2001 for (i = 0; i < NPGPTD; i++) { 2002 m = ptdpg[i]; 2003#ifdef PAE 2004 KASSERT(VM_PAGE_TO_PHYS(m) == (pmap->pm_pdpt[i] & PG_FRAME), 2005 ("pmap_release: got wrong ptd page")); 2006#endif 2007 m->wire_count--; 2008 atomic_subtract_int(&cnt.v_wire_count, 1); 2009 vm_page_free_zero(m); 2010 } 2011 PMAP_LOCK_DESTROY(pmap); 2012} 2013 2014static int 2015kvm_size(SYSCTL_HANDLER_ARGS) 2016{ 2017 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - KERNBASE; 2018 2019 return (sysctl_handle_long(oidp, &ksize, 0, req)); 2020} 2021SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG|CTLFLAG_RD, 2022 0, 0, kvm_size, "IU", "Size of KVM"); 2023 2024static int 2025kvm_free(SYSCTL_HANDLER_ARGS) 2026{ 2027 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end; 2028 2029 return (sysctl_handle_long(oidp, &kfree, 0, req)); 2030} 2031SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG|CTLFLAG_RD, 2032 0, 0, kvm_free, "IU", "Amount of KVM free"); 2033 2034/* 2035 * grow the number of kernel page table entries, if needed 2036 */ 2037void 2038pmap_growkernel(vm_offset_t addr) 2039{ 2040 vm_paddr_t ptppaddr; 2041 vm_page_t nkpg; 2042 pd_entry_t newpdir; 2043 2044 mtx_assert(&kernel_map->system_mtx, MA_OWNED); 2045 addr = roundup2(addr, NBPDR); 2046 if (addr - 1 >= kernel_map->max_offset) 2047 addr = kernel_map->max_offset; 2048 while (kernel_vm_end < addr) { 2049 if (pdir_pde(PTD, kernel_vm_end)) { 2050 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK; 2051 if (kernel_vm_end - 1 >= kernel_map->max_offset) { 2052 kernel_vm_end = kernel_map->max_offset; 2053 break; 2054 } 2055 continue; 2056 } 2057 2058 nkpg = vm_page_alloc(NULL, kernel_vm_end >> PDRSHIFT, 2059 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | 2060 VM_ALLOC_ZERO); 2061 if (nkpg == NULL) 2062 panic("pmap_growkernel: no memory to grow kernel"); 2063 2064 nkpt++; 2065 2066 if ((nkpg->flags & PG_ZERO) == 0) 2067 pmap_zero_page(nkpg); 2068 ptppaddr = VM_PAGE_TO_PHYS(nkpg); 2069 newpdir = (pd_entry_t) (ptppaddr | PG_V | PG_RW | PG_A | PG_M); 2070 pdir_pde(KPTD, kernel_vm_end) = pgeflag | newpdir; 2071 2072 pmap_kenter_pde(kernel_vm_end, newpdir); 2073 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK; 2074 if (kernel_vm_end - 1 >= kernel_map->max_offset) { 2075 kernel_vm_end = kernel_map->max_offset; 2076 break; 2077 } 2078 } 2079} 2080 2081 2082/*************************************************** 2083 * page management routines. 2084 ***************************************************/ 2085 2086CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE); 2087CTASSERT(_NPCM == 11); 2088 2089static __inline struct pv_chunk * 2090pv_to_chunk(pv_entry_t pv) 2091{ 2092 2093 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK)); 2094} 2095 2096#define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap) 2097 2098#define PC_FREE0_9 0xfffffffful /* Free values for index 0 through 9 */ 2099#define PC_FREE10 0x0000fffful /* Free values for index 10 */ 2100 2101static uint32_t pc_freemask[11] = { 2102 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9, 2103 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9, 2104 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9, 2105 PC_FREE0_9, PC_FREE10 2106}; 2107 2108SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0, 2109 "Current number of pv entries"); 2110 2111#ifdef PV_STATS 2112static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail; 2113 2114SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0, 2115 "Current number of pv entry chunks"); 2116SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0, 2117 "Current number of pv entry chunks allocated"); 2118SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0, 2119 "Current number of pv entry chunks frees"); 2120SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0, 2121 "Number of times tried to get a chunk page but failed."); 2122 2123static long pv_entry_frees, pv_entry_allocs; 2124static int pv_entry_spare; 2125 2126SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0, 2127 "Current number of pv entry frees"); 2128SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0, 2129 "Current number of pv entry allocs"); 2130SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0, 2131 "Current number of spare pv entries"); 2132 2133static int pmap_collect_inactive, pmap_collect_active; 2134 2135SYSCTL_INT(_vm_pmap, OID_AUTO, pmap_collect_inactive, CTLFLAG_RD, &pmap_collect_inactive, 0, 2136 "Current number times pmap_collect called on inactive queue"); 2137SYSCTL_INT(_vm_pmap, OID_AUTO, pmap_collect_active, CTLFLAG_RD, &pmap_collect_active, 0, 2138 "Current number times pmap_collect called on active queue"); 2139#endif 2140 2141/* 2142 * We are in a serious low memory condition. Resort to 2143 * drastic measures to free some pages so we can allocate 2144 * another pv entry chunk. This is normally called to 2145 * unmap inactive pages, and if necessary, active pages. 2146 */ 2147static void 2148pmap_collect(pmap_t locked_pmap, struct vpgqueues *vpq) 2149{ 2150 pd_entry_t *pde; 2151 pmap_t pmap; 2152 pt_entry_t *pte, tpte; 2153 pv_entry_t next_pv, pv; 2154 vm_offset_t va; 2155 vm_page_t m, free; 2156 2157 sched_pin(); 2158 TAILQ_FOREACH(m, &vpq->pl, pageq) { 2159 if (m->hold_count || m->busy) 2160 continue; 2161 TAILQ_FOREACH_SAFE(pv, &m->md.pv_list, pv_list, next_pv) { 2162 va = pv->pv_va; 2163 pmap = PV_PMAP(pv); 2164 /* Avoid deadlock and lock recursion. */ 2165 if (pmap > locked_pmap) 2166 PMAP_LOCK(pmap); 2167 else if (pmap != locked_pmap && !PMAP_TRYLOCK(pmap)) 2168 continue; 2169 pmap->pm_stats.resident_count--; 2170 pde = pmap_pde(pmap, va); 2171 KASSERT((*pde & PG_PS) == 0, ("pmap_collect: found" 2172 " a 4mpage in page %p's pv list", m)); 2173 pte = pmap_pte_quick(pmap, va); 2174 tpte = pte_load_clear(pte); 2175 KASSERT((tpte & PG_W) == 0, 2176 ("pmap_collect: wired pte %#jx", (uintmax_t)tpte)); 2177 if (tpte & PG_A) 2178 vm_page_flag_set(m, PG_REFERENCED); 2179 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) 2180 vm_page_dirty(m); 2181 free = NULL; 2182 pmap_unuse_pt(pmap, va, &free); 2183 pmap_invalidate_page(pmap, va); 2184 pmap_free_zero_pages(free); 2185 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list); 2186 free_pv_entry(pmap, pv); 2187 if (pmap != locked_pmap) 2188 PMAP_UNLOCK(pmap); 2189 } 2190 if (TAILQ_EMPTY(&m->md.pv_list) && 2191 TAILQ_EMPTY(&pa_to_pvh(VM_PAGE_TO_PHYS(m))->pv_list)) 2192 vm_page_flag_clear(m, PG_WRITEABLE); 2193 } 2194 sched_unpin(); 2195} 2196 2197 2198/* 2199 * free the pv_entry back to the free list 2200 */ 2201static void 2202free_pv_entry(pmap_t pmap, pv_entry_t pv) 2203{ 2204 vm_page_t m; 2205 struct pv_chunk *pc; 2206 int idx, field, bit; 2207 2208 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2209 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2210 PV_STAT(pv_entry_frees++); 2211 PV_STAT(pv_entry_spare++); 2212 pv_entry_count--; 2213 pc = pv_to_chunk(pv); 2214 idx = pv - &pc->pc_pventry[0]; 2215 field = idx / 32; 2216 bit = idx % 32; 2217 pc->pc_map[field] |= 1ul << bit; 2218 /* move to head of list */ 2219 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 2220 for (idx = 0; idx < _NPCM; idx++) 2221 if (pc->pc_map[idx] != pc_freemask[idx]) { 2222 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list); 2223 return; 2224 } 2225 PV_STAT(pv_entry_spare -= _NPCPV); 2226 PV_STAT(pc_chunk_count--); 2227 PV_STAT(pc_chunk_frees++); 2228 /* entire chunk is free, return it */ 2229 m = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc)); 2230 pmap_qremove((vm_offset_t)pc, 1); 2231 vm_page_unwire(m, 0); 2232 vm_page_free(m); 2233 pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc); 2234} 2235 2236/* 2237 * get a new pv_entry, allocating a block from the system 2238 * when needed. 2239 */ 2240static pv_entry_t 2241get_pv_entry(pmap_t pmap, int try) 2242{ 2243 static const struct timeval printinterval = { 60, 0 }; 2244 static struct timeval lastprint; 2245 static vm_pindex_t colour; 2246 struct vpgqueues *pq; 2247 int bit, field; 2248 pv_entry_t pv; 2249 struct pv_chunk *pc; 2250 vm_page_t m; 2251 2252 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2253 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2254 PV_STAT(pv_entry_allocs++); 2255 pv_entry_count++; 2256 if (pv_entry_count > pv_entry_high_water) 2257 if (ratecheck(&lastprint, &printinterval)) 2258 printf("Approaching the limit on PV entries, consider " 2259 "increasing either the vm.pmap.shpgperproc or the " 2260 "vm.pmap.pv_entry_max tunable.\n"); 2261 pq = NULL; 2262retry: 2263 pc = TAILQ_FIRST(&pmap->pm_pvchunk); 2264 if (pc != NULL) { 2265 for (field = 0; field < _NPCM; field++) { 2266 if (pc->pc_map[field]) { 2267 bit = bsfl(pc->pc_map[field]); 2268 break; 2269 } 2270 } 2271 if (field < _NPCM) { 2272 pv = &pc->pc_pventry[field * 32 + bit]; 2273 pc->pc_map[field] &= ~(1ul << bit); 2274 /* If this was the last item, move it to tail */ 2275 for (field = 0; field < _NPCM; field++) 2276 if (pc->pc_map[field] != 0) { 2277 PV_STAT(pv_entry_spare--); 2278 return (pv); /* not full, return */ 2279 } 2280 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 2281 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list); 2282 PV_STAT(pv_entry_spare--); 2283 return (pv); 2284 } 2285 } 2286 /* 2287 * Access to the ptelist "pv_vafree" is synchronized by the page 2288 * queues lock. If "pv_vafree" is currently non-empty, it will 2289 * remain non-empty until pmap_ptelist_alloc() completes. 2290 */ 2291 if (pv_vafree == 0 || (m = vm_page_alloc(NULL, colour, (pq == 2292 &vm_page_queues[PQ_ACTIVE] ? VM_ALLOC_SYSTEM : VM_ALLOC_NORMAL) | 2293 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) { 2294 if (try) { 2295 pv_entry_count--; 2296 PV_STAT(pc_chunk_tryfail++); 2297 return (NULL); 2298 } 2299 /* 2300 * Reclaim pv entries: At first, destroy mappings to 2301 * inactive pages. After that, if a pv chunk entry 2302 * is still needed, destroy mappings to active pages. 2303 */ 2304 if (pq == NULL) { 2305 PV_STAT(pmap_collect_inactive++); 2306 pq = &vm_page_queues[PQ_INACTIVE]; 2307 } else if (pq == &vm_page_queues[PQ_INACTIVE]) { 2308 PV_STAT(pmap_collect_active++); 2309 pq = &vm_page_queues[PQ_ACTIVE]; 2310 } else 2311 panic("get_pv_entry: increase vm.pmap.shpgperproc"); 2312 pmap_collect(pmap, pq); 2313 goto retry; 2314 } 2315 PV_STAT(pc_chunk_count++); 2316 PV_STAT(pc_chunk_allocs++); 2317 colour++; 2318 pc = (struct pv_chunk *)pmap_ptelist_alloc(&pv_vafree); 2319 pmap_qenter((vm_offset_t)pc, &m, 1); 2320 pc->pc_pmap = pmap; 2321 pc->pc_map[0] = pc_freemask[0] & ~1ul; /* preallocated bit 0 */ 2322 for (field = 1; field < _NPCM; field++) 2323 pc->pc_map[field] = pc_freemask[field]; 2324 pv = &pc->pc_pventry[0]; 2325 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list); 2326 PV_STAT(pv_entry_spare += _NPCPV - 1); 2327 return (pv); 2328} 2329 2330static __inline pv_entry_t 2331pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va) 2332{ 2333 pv_entry_t pv; 2334 2335 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2336 TAILQ_FOREACH(pv, &pvh->pv_list, pv_list) { 2337 if (pmap == PV_PMAP(pv) && va == pv->pv_va) { 2338 TAILQ_REMOVE(&pvh->pv_list, pv, pv_list); 2339 break; 2340 } 2341 } 2342 return (pv); 2343} 2344 2345static void 2346pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa) 2347{ 2348 struct md_page *pvh; 2349 pv_entry_t pv; 2350 vm_offset_t va_last; 2351 vm_page_t m; 2352 2353 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2354 KASSERT((pa & PDRMASK) == 0, 2355 ("pmap_pv_demote_pde: pa is not 4mpage aligned")); 2356 2357 /* 2358 * Transfer the 4mpage's pv entry for this mapping to the first 2359 * page's pv list. 2360 */ 2361 pvh = pa_to_pvh(pa); 2362 va = trunc_4mpage(va); 2363 pv = pmap_pvh_remove(pvh, pmap, va); 2364 KASSERT(pv != NULL, ("pmap_pv_demote_pde: pv not found")); 2365 m = PHYS_TO_VM_PAGE(pa); 2366 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list); 2367 /* Instantiate the remaining NPTEPG - 1 pv entries. */ 2368 va_last = va + NBPDR - PAGE_SIZE; 2369 do { 2370 m++; 2371 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 2372 ("pmap_pv_demote_pde: page %p is not managed", m)); 2373 va += PAGE_SIZE; 2374 pmap_insert_entry(pmap, va, m); 2375 } while (va < va_last); 2376} 2377 2378static void 2379pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa) 2380{ 2381 struct md_page *pvh; 2382 pv_entry_t pv; 2383 vm_offset_t va_last; 2384 vm_page_t m; 2385 2386 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2387 KASSERT((pa & PDRMASK) == 0, 2388 ("pmap_pv_promote_pde: pa is not 4mpage aligned")); 2389 2390 /* 2391 * Transfer the first page's pv entry for this mapping to the 2392 * 4mpage's pv list. Aside from avoiding the cost of a call 2393 * to get_pv_entry(), a transfer avoids the possibility that 2394 * get_pv_entry() calls pmap_collect() and that pmap_collect() 2395 * removes one of the mappings that is being promoted. 2396 */ 2397 m = PHYS_TO_VM_PAGE(pa); 2398 va = trunc_4mpage(va); 2399 pv = pmap_pvh_remove(&m->md, pmap, va); 2400 KASSERT(pv != NULL, ("pmap_pv_promote_pde: pv not found")); 2401 pvh = pa_to_pvh(pa); 2402 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_list); 2403 /* Free the remaining NPTEPG - 1 pv entries. */ 2404 va_last = va + NBPDR - PAGE_SIZE; 2405 do { 2406 m++; 2407 va += PAGE_SIZE; 2408 pmap_pvh_free(&m->md, pmap, va); 2409 } while (va < va_last); 2410} 2411 2412static void 2413pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va) 2414{ 2415 pv_entry_t pv; 2416 2417 pv = pmap_pvh_remove(pvh, pmap, va); 2418 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found")); 2419 free_pv_entry(pmap, pv); 2420} 2421 2422static void 2423pmap_remove_entry(pmap_t pmap, vm_page_t m, vm_offset_t va) 2424{ 2425 struct md_page *pvh; 2426 2427 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2428 pmap_pvh_free(&m->md, pmap, va); 2429 if (TAILQ_EMPTY(&m->md.pv_list)) { 2430 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 2431 if (TAILQ_EMPTY(&pvh->pv_list)) 2432 vm_page_flag_clear(m, PG_WRITEABLE); 2433 } 2434} 2435 2436/* 2437 * Create a pv entry for page at pa for 2438 * (pmap, va). 2439 */ 2440static void 2441pmap_insert_entry(pmap_t pmap, vm_offset_t va, vm_page_t m) 2442{ 2443 pv_entry_t pv; 2444 2445 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2446 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2447 pv = get_pv_entry(pmap, FALSE); 2448 pv->pv_va = va; 2449 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list); 2450} 2451 2452/* 2453 * Conditionally create a pv entry. 2454 */ 2455static boolean_t 2456pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m) 2457{ 2458 pv_entry_t pv; 2459 2460 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2461 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2462 if (pv_entry_count < pv_entry_high_water && 2463 (pv = get_pv_entry(pmap, TRUE)) != NULL) { 2464 pv->pv_va = va; 2465 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list); 2466 return (TRUE); 2467 } else 2468 return (FALSE); 2469} 2470 2471/* 2472 * Create the pv entries for each of the pages within a superpage. 2473 */ 2474static boolean_t 2475pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa) 2476{ 2477 struct md_page *pvh; 2478 pv_entry_t pv; 2479 2480 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2481 if (pv_entry_count < pv_entry_high_water && 2482 (pv = get_pv_entry(pmap, TRUE)) != NULL) { 2483 pv->pv_va = va; 2484 pvh = pa_to_pvh(pa); 2485 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_list); 2486 return (TRUE); 2487 } else 2488 return (FALSE); 2489} 2490 2491/* 2492 * Fills a page table page with mappings to consecutive physical pages. 2493 */ 2494static void 2495pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte) 2496{ 2497 pt_entry_t *pte; 2498 2499 for (pte = firstpte; pte < firstpte + NPTEPG; pte++) { 2500 *pte = newpte; 2501 newpte += PAGE_SIZE; 2502 } 2503} 2504 2505/* 2506 * Tries to demote a 2- or 4MB page mapping. If demotion fails, the 2507 * 2- or 4MB page mapping is invalidated. 2508 */ 2509static boolean_t 2510pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va) 2511{ 2512 pd_entry_t newpde, oldpde; 2513 pt_entry_t *firstpte, newpte; 2514 vm_paddr_t mptepa; 2515 vm_page_t free, mpte; 2516 2517 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2518 oldpde = *pde; 2519 KASSERT((oldpde & (PG_PS | PG_V)) == (PG_PS | PG_V), 2520 ("pmap_demote_pde: oldpde is missing PG_PS and/or PG_V")); 2521 mpte = pmap_lookup_pt_page(pmap, va); 2522 if (mpte != NULL) 2523 pmap_remove_pt_page(pmap, mpte); 2524 else { 2525 KASSERT((oldpde & PG_W) == 0, 2526 ("pmap_demote_pde: page table page for a wired mapping" 2527 " is missing")); 2528 2529 /* 2530 * Invalidate the 2- or 4MB page mapping and return 2531 * "failure" if the mapping was never accessed or the 2532 * allocation of the new page table page fails. 2533 */ 2534 if ((oldpde & PG_A) == 0 || (mpte = vm_page_alloc(NULL, 2535 va >> PDRSHIFT, VM_ALLOC_NOOBJ | VM_ALLOC_NORMAL | 2536 VM_ALLOC_WIRED)) == NULL) { 2537 free = NULL; 2538 pmap_remove_pde(pmap, pde, trunc_4mpage(va), &free); 2539 pmap_invalidate_page(pmap, trunc_4mpage(va)); 2540 pmap_free_zero_pages(free); 2541 CTR2(KTR_PMAP, "pmap_demote_pde: failure for va %#x" 2542 " in pmap %p", va, pmap); 2543 return (FALSE); 2544 } 2545 if (va < VM_MAXUSER_ADDRESS) 2546 pmap->pm_stats.resident_count++; 2547 } 2548 mptepa = VM_PAGE_TO_PHYS(mpte); 2549 2550 /* 2551 * If the page mapping is in the kernel's address space, then the 2552 * KPTmap can provide access to the page table page. Otherwise, 2553 * temporarily map the page table page (mpte) into the kernel's 2554 * address space at either PADDR1 or PADDR2. 2555 */ 2556 if (va >= KERNBASE) 2557 firstpte = &KPTmap[i386_btop(trunc_4mpage(va))]; 2558 else if (curthread->td_pinned > 0 && mtx_owned(&vm_page_queue_mtx)) { 2559 if ((*PMAP1 & PG_FRAME) != mptepa) { 2560 *PMAP1 = mptepa | PG_RW | PG_V | PG_A | PG_M; 2561#ifdef SMP 2562 PMAP1cpu = PCPU_GET(cpuid); 2563#endif 2564 invlcaddr(PADDR1); 2565 PMAP1changed++; 2566 } else 2567#ifdef SMP 2568 if (PMAP1cpu != PCPU_GET(cpuid)) { 2569 PMAP1cpu = PCPU_GET(cpuid); 2570 invlcaddr(PADDR1); 2571 PMAP1changedcpu++; 2572 } else 2573#endif 2574 PMAP1unchanged++; 2575 firstpte = PADDR1; 2576 } else { 2577 mtx_lock(&PMAP2mutex); 2578 if ((*PMAP2 & PG_FRAME) != mptepa) { 2579 *PMAP2 = mptepa | PG_RW | PG_V | PG_A | PG_M; 2580 pmap_invalidate_page(kernel_pmap, (vm_offset_t)PADDR2); 2581 } 2582 firstpte = PADDR2; 2583 } 2584 newpde = mptepa | PG_M | PG_A | (oldpde & PG_U) | PG_RW | PG_V; 2585 KASSERT((oldpde & PG_A) != 0, 2586 ("pmap_demote_pde: oldpde is missing PG_A")); 2587 KASSERT((oldpde & (PG_M | PG_RW)) != PG_RW, 2588 ("pmap_demote_pde: oldpde is missing PG_M")); 2589 newpte = oldpde & ~PG_PS; 2590 if ((newpte & PG_PDE_PAT) != 0) 2591 newpte ^= PG_PDE_PAT | PG_PTE_PAT; 2592 2593 /* 2594 * If the page table page is new, initialize it. 2595 */ 2596 if (mpte->wire_count == 1) { 2597 mpte->wire_count = NPTEPG; 2598 pmap_fill_ptp(firstpte, newpte); 2599 } 2600 KASSERT((*firstpte & PG_FRAME) == (newpte & PG_FRAME), 2601 ("pmap_demote_pde: firstpte and newpte map different physical" 2602 " addresses")); 2603 2604 /* 2605 * If the mapping has changed attributes, update the page table 2606 * entries. 2607 */ 2608 if ((*firstpte & PG_PTE_PROMOTE) != (newpte & PG_PTE_PROMOTE)) 2609 pmap_fill_ptp(firstpte, newpte); 2610 2611 /* 2612 * Demote the mapping. This pmap is locked. The old PDE has 2613 * PG_A set. If the old PDE has PG_RW set, it also has PG_M 2614 * set. Thus, there is no danger of a race with another 2615 * processor changing the setting of PG_A and/or PG_M between 2616 * the read above and the store below. 2617 */ 2618 if (workaround_erratum383) 2619 pmap_update_pde(pmap, va, pde, newpde); 2620 else if (pmap == kernel_pmap) 2621 pmap_kenter_pde(va, newpde); 2622 else 2623 pde_store(pde, newpde); 2624 if (firstpte == PADDR2) 2625 mtx_unlock(&PMAP2mutex); 2626 2627 /* 2628 * Invalidate the recursive mapping of the page table page. 2629 */ 2630 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va)); 2631 2632 /* 2633 * Demote the pv entry. This depends on the earlier demotion 2634 * of the mapping. Specifically, the (re)creation of a per- 2635 * page pv entry might trigger the execution of pmap_collect(), 2636 * which might reclaim a newly (re)created per-page pv entry 2637 * and destroy the associated mapping. In order to destroy 2638 * the mapping, the PDE must have already changed from mapping 2639 * the 2mpage to referencing the page table page. 2640 */ 2641 if ((oldpde & PG_MANAGED) != 0) 2642 pmap_pv_demote_pde(pmap, va, oldpde & PG_PS_FRAME); 2643 2644 pmap_pde_demotions++; 2645 CTR2(KTR_PMAP, "pmap_demote_pde: success for va %#x" 2646 " in pmap %p", va, pmap); 2647 return (TRUE); 2648} 2649 2650/* 2651 * pmap_remove_pde: do the things to unmap a superpage in a process 2652 */ 2653static void 2654pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva, 2655 vm_page_t *free) 2656{ 2657 struct md_page *pvh; 2658 pd_entry_t oldpde; 2659 vm_offset_t eva, va; 2660 vm_page_t m, mpte; 2661 2662 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2663 KASSERT((sva & PDRMASK) == 0, 2664 ("pmap_remove_pde: sva is not 4mpage aligned")); 2665 oldpde = pte_load_clear(pdq); 2666 if (oldpde & PG_W) 2667 pmap->pm_stats.wired_count -= NBPDR / PAGE_SIZE; 2668 2669 /* 2670 * Machines that don't support invlpg, also don't support 2671 * PG_G. 2672 */ 2673 if (oldpde & PG_G) 2674 pmap_invalidate_page(kernel_pmap, sva); 2675 pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE; 2676 if (oldpde & PG_MANAGED) { 2677 pvh = pa_to_pvh(oldpde & PG_PS_FRAME); 2678 pmap_pvh_free(pvh, pmap, sva); 2679 eva = sva + NBPDR; 2680 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME); 2681 va < eva; va += PAGE_SIZE, m++) { 2682 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW)) 2683 vm_page_dirty(m); 2684 if (oldpde & PG_A) 2685 vm_page_flag_set(m, PG_REFERENCED); 2686 if (TAILQ_EMPTY(&m->md.pv_list) && 2687 TAILQ_EMPTY(&pvh->pv_list)) 2688 vm_page_flag_clear(m, PG_WRITEABLE); 2689 } 2690 } 2691 if (pmap == kernel_pmap) { 2692 if (!pmap_demote_pde(pmap, pdq, sva)) 2693 panic("pmap_remove_pde: failed demotion"); 2694 } else { 2695 mpte = pmap_lookup_pt_page(pmap, sva); 2696 if (mpte != NULL) { 2697 pmap_remove_pt_page(pmap, mpte); 2698 pmap->pm_stats.resident_count--; 2699 KASSERT(mpte->wire_count == NPTEPG, 2700 ("pmap_remove_pde: pte page wire count error")); 2701 mpte->wire_count = 0; 2702 pmap_add_delayed_free_list(mpte, free, FALSE); 2703 atomic_subtract_int(&cnt.v_wire_count, 1); 2704 } 2705 } 2706} 2707 2708/* 2709 * pmap_remove_pte: do the things to unmap a page in a process 2710 */ 2711static int 2712pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t va, vm_page_t *free) 2713{ 2714 pt_entry_t oldpte; 2715 vm_page_t m; 2716 2717 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2718 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2719 oldpte = pte_load_clear(ptq); 2720 if (oldpte & PG_W) 2721 pmap->pm_stats.wired_count -= 1; 2722 /* 2723 * Machines that don't support invlpg, also don't support 2724 * PG_G. 2725 */ 2726 if (oldpte & PG_G) 2727 pmap_invalidate_page(kernel_pmap, va); 2728 pmap->pm_stats.resident_count -= 1; 2729 if (oldpte & PG_MANAGED) { 2730 m = PHYS_TO_VM_PAGE(oldpte & PG_FRAME); 2731 if ((oldpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) 2732 vm_page_dirty(m); 2733 if (oldpte & PG_A) 2734 vm_page_flag_set(m, PG_REFERENCED); 2735 pmap_remove_entry(pmap, m, va); 2736 } 2737 return (pmap_unuse_pt(pmap, va, free)); 2738} 2739 2740/* 2741 * Remove a single page from a process address space 2742 */ 2743static void 2744pmap_remove_page(pmap_t pmap, vm_offset_t va, vm_page_t *free) 2745{ 2746 pt_entry_t *pte; 2747 2748 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2749 KASSERT(curthread->td_pinned > 0, ("curthread not pinned")); 2750 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2751 if ((pte = pmap_pte_quick(pmap, va)) == NULL || *pte == 0) 2752 return; 2753 pmap_remove_pte(pmap, pte, va, free); 2754 pmap_invalidate_page(pmap, va); 2755} 2756 2757/* 2758 * Remove the given range of addresses from the specified map. 2759 * 2760 * It is assumed that the start and end are properly 2761 * rounded to the page size. 2762 */ 2763void 2764pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 2765{ 2766 vm_offset_t pdnxt; 2767 pd_entry_t ptpaddr; 2768 pt_entry_t *pte; 2769 vm_page_t free = NULL; 2770 int anyvalid; 2771 2772 /* 2773 * Perform an unsynchronized read. This is, however, safe. 2774 */ 2775 if (pmap->pm_stats.resident_count == 0) 2776 return; 2777 2778 anyvalid = 0; 2779 2780 vm_page_lock_queues(); 2781 sched_pin(); 2782 PMAP_LOCK(pmap); 2783 2784 /* 2785 * special handling of removing one page. a very 2786 * common operation and easy to short circuit some 2787 * code. 2788 */ 2789 if ((sva + PAGE_SIZE == eva) && 2790 ((pmap->pm_pdir[(sva >> PDRSHIFT)] & PG_PS) == 0)) { 2791 pmap_remove_page(pmap, sva, &free); 2792 goto out; 2793 } 2794 2795 for (; sva < eva; sva = pdnxt) { 2796 unsigned pdirindex; 2797 2798 /* 2799 * Calculate index for next page table. 2800 */ 2801 pdnxt = (sva + NBPDR) & ~PDRMASK; 2802 if (pdnxt < sva) 2803 pdnxt = eva; 2804 if (pmap->pm_stats.resident_count == 0) 2805 break; 2806 2807 pdirindex = sva >> PDRSHIFT; 2808 ptpaddr = pmap->pm_pdir[pdirindex]; 2809 2810 /* 2811 * Weed out invalid mappings. Note: we assume that the page 2812 * directory table is always allocated, and in kernel virtual. 2813 */ 2814 if (ptpaddr == 0) 2815 continue; 2816 2817 /* 2818 * Check for large page. 2819 */ 2820 if ((ptpaddr & PG_PS) != 0) { 2821 /* 2822 * Are we removing the entire large page? If not, 2823 * demote the mapping and fall through. 2824 */ 2825 if (sva + NBPDR == pdnxt && eva >= pdnxt) { 2826 /* 2827 * The TLB entry for a PG_G mapping is 2828 * invalidated by pmap_remove_pde(). 2829 */ 2830 if ((ptpaddr & PG_G) == 0) 2831 anyvalid = 1; 2832 pmap_remove_pde(pmap, 2833 &pmap->pm_pdir[pdirindex], sva, &free); 2834 continue; 2835 } else if (!pmap_demote_pde(pmap, 2836 &pmap->pm_pdir[pdirindex], sva)) { 2837 /* The large page mapping was destroyed. */ 2838 continue; 2839 } 2840 } 2841 2842 /* 2843 * Limit our scan to either the end of the va represented 2844 * by the current page table page, or to the end of the 2845 * range being removed. 2846 */ 2847 if (pdnxt > eva) 2848 pdnxt = eva; 2849 2850 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++, 2851 sva += PAGE_SIZE) { 2852 if (*pte == 0) 2853 continue; 2854 2855 /* 2856 * The TLB entry for a PG_G mapping is invalidated 2857 * by pmap_remove_pte(). 2858 */ 2859 if ((*pte & PG_G) == 0) 2860 anyvalid = 1; 2861 if (pmap_remove_pte(pmap, pte, sva, &free)) 2862 break; 2863 } 2864 } 2865out: 2866 sched_unpin(); 2867 if (anyvalid) 2868 pmap_invalidate_all(pmap); 2869 vm_page_unlock_queues(); 2870 PMAP_UNLOCK(pmap); 2871 pmap_free_zero_pages(free); 2872} 2873 2874/* 2875 * Routine: pmap_remove_all 2876 * Function: 2877 * Removes this physical page from 2878 * all physical maps in which it resides. 2879 * Reflects back modify bits to the pager. 2880 * 2881 * Notes: 2882 * Original versions of this routine were very 2883 * inefficient because they iteratively called 2884 * pmap_remove (slow...) 2885 */ 2886 2887void 2888pmap_remove_all(vm_page_t m) 2889{ 2890 struct md_page *pvh; 2891 pv_entry_t pv; 2892 pmap_t pmap; 2893 pt_entry_t *pte, tpte; 2894 pd_entry_t *pde; 2895 vm_offset_t va; 2896 vm_page_t free; 2897 2898 KASSERT((m->flags & PG_FICTITIOUS) == 0, 2899 ("pmap_remove_all: page %p is fictitious", m)); 2900 free = NULL; 2901 vm_page_lock_queues(); 2902 sched_pin(); 2903 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 2904 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) { 2905 va = pv->pv_va; 2906 pmap = PV_PMAP(pv); 2907 PMAP_LOCK(pmap); 2908 pde = pmap_pde(pmap, va); 2909 (void)pmap_demote_pde(pmap, pde, va); 2910 PMAP_UNLOCK(pmap); 2911 } 2912 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) { 2913 pmap = PV_PMAP(pv); 2914 PMAP_LOCK(pmap); 2915 pmap->pm_stats.resident_count--; 2916 pde = pmap_pde(pmap, pv->pv_va); 2917 KASSERT((*pde & PG_PS) == 0, ("pmap_remove_all: found" 2918 " a 4mpage in page %p's pv list", m)); 2919 pte = pmap_pte_quick(pmap, pv->pv_va); 2920 tpte = pte_load_clear(pte); 2921 if (tpte & PG_W) 2922 pmap->pm_stats.wired_count--; 2923 if (tpte & PG_A) 2924 vm_page_flag_set(m, PG_REFERENCED); 2925 2926 /* 2927 * Update the vm_page_t clean and reference bits. 2928 */ 2929 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) 2930 vm_page_dirty(m); 2931 pmap_unuse_pt(pmap, pv->pv_va, &free); 2932 pmap_invalidate_page(pmap, pv->pv_va); 2933 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list); 2934 free_pv_entry(pmap, pv); 2935 PMAP_UNLOCK(pmap); 2936 } 2937 vm_page_flag_clear(m, PG_WRITEABLE); 2938 sched_unpin(); 2939 vm_page_unlock_queues(); 2940 pmap_free_zero_pages(free); 2941} 2942 2943/* 2944 * pmap_protect_pde: do the things to protect a 4mpage in a process 2945 */ 2946static boolean_t 2947pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva, vm_prot_t prot) 2948{ 2949 pd_entry_t newpde, oldpde; 2950 vm_offset_t eva, va; 2951 vm_page_t m; 2952 boolean_t anychanged; 2953 2954 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2955 KASSERT((sva & PDRMASK) == 0, 2956 ("pmap_protect_pde: sva is not 4mpage aligned")); 2957 anychanged = FALSE; 2958retry: 2959 oldpde = newpde = *pde; 2960 if (oldpde & PG_MANAGED) { 2961 eva = sva + NBPDR; 2962 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME); 2963 va < eva; va += PAGE_SIZE, m++) 2964 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW)) 2965 vm_page_dirty(m); 2966 } 2967 if ((prot & VM_PROT_WRITE) == 0) 2968 newpde &= ~(PG_RW | PG_M); 2969#ifdef PAE 2970 if ((prot & VM_PROT_EXECUTE) == 0) 2971 newpde |= pg_nx; 2972#endif 2973 if (newpde != oldpde) { 2974 if (!pde_cmpset(pde, oldpde, newpde)) 2975 goto retry; 2976 if (oldpde & PG_G) 2977 pmap_invalidate_page(pmap, sva); 2978 else 2979 anychanged = TRUE; 2980 } 2981 return (anychanged); 2982} 2983 2984/* 2985 * Set the physical protection on the 2986 * specified range of this map as requested. 2987 */ 2988void 2989pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot) 2990{ 2991 vm_offset_t pdnxt; 2992 pd_entry_t ptpaddr; 2993 pt_entry_t *pte; 2994 int anychanged; 2995 2996 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 2997 pmap_remove(pmap, sva, eva); 2998 return; 2999 } 3000 3001#ifdef PAE 3002 if ((prot & (VM_PROT_WRITE|VM_PROT_EXECUTE)) == 3003 (VM_PROT_WRITE|VM_PROT_EXECUTE)) 3004 return; 3005#else 3006 if (prot & VM_PROT_WRITE) 3007 return; 3008#endif 3009 3010 anychanged = 0; 3011 3012 vm_page_lock_queues(); 3013 sched_pin(); 3014 PMAP_LOCK(pmap); 3015 for (; sva < eva; sva = pdnxt) { 3016 pt_entry_t obits, pbits; 3017 unsigned pdirindex; 3018 3019 pdnxt = (sva + NBPDR) & ~PDRMASK; 3020 if (pdnxt < sva) 3021 pdnxt = eva; 3022 3023 pdirindex = sva >> PDRSHIFT; 3024 ptpaddr = pmap->pm_pdir[pdirindex]; 3025 3026 /* 3027 * Weed out invalid mappings. Note: we assume that the page 3028 * directory table is always allocated, and in kernel virtual. 3029 */ 3030 if (ptpaddr == 0) 3031 continue; 3032 3033 /* 3034 * Check for large page. 3035 */ 3036 if ((ptpaddr & PG_PS) != 0) { 3037 /* 3038 * Are we protecting the entire large page? If not, 3039 * demote the mapping and fall through. 3040 */ 3041 if (sva + NBPDR == pdnxt && eva >= pdnxt) { 3042 /* 3043 * The TLB entry for a PG_G mapping is 3044 * invalidated by pmap_protect_pde(). 3045 */ 3046 if (pmap_protect_pde(pmap, 3047 &pmap->pm_pdir[pdirindex], sva, prot)) 3048 anychanged = 1; 3049 continue; 3050 } else if (!pmap_demote_pde(pmap, 3051 &pmap->pm_pdir[pdirindex], sva)) { 3052 /* The large page mapping was destroyed. */ 3053 continue; 3054 } 3055 } 3056 3057 if (pdnxt > eva) 3058 pdnxt = eva; 3059 3060 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++, 3061 sva += PAGE_SIZE) { 3062 vm_page_t m; 3063 3064retry: 3065 /* 3066 * Regardless of whether a pte is 32 or 64 bits in 3067 * size, PG_RW, PG_A, and PG_M are among the least 3068 * significant 32 bits. 3069 */ 3070 obits = pbits = *pte; 3071 if ((pbits & PG_V) == 0) 3072 continue; 3073 3074 if ((prot & VM_PROT_WRITE) == 0) { 3075 if ((pbits & (PG_MANAGED | PG_M | PG_RW)) == 3076 (PG_MANAGED | PG_M | PG_RW)) { 3077 m = PHYS_TO_VM_PAGE(pbits & PG_FRAME); 3078 vm_page_dirty(m); 3079 } 3080 pbits &= ~(PG_RW | PG_M); 3081 } 3082#ifdef PAE 3083 if ((prot & VM_PROT_EXECUTE) == 0) 3084 pbits |= pg_nx; 3085#endif 3086 3087 if (pbits != obits) { 3088#ifdef PAE 3089 if (!atomic_cmpset_64(pte, obits, pbits)) 3090 goto retry; 3091#else 3092 if (!atomic_cmpset_int((u_int *)pte, obits, 3093 pbits)) 3094 goto retry; 3095#endif 3096 if (obits & PG_G) 3097 pmap_invalidate_page(pmap, sva); 3098 else 3099 anychanged = 1; 3100 } 3101 } 3102 } 3103 sched_unpin(); 3104 if (anychanged) 3105 pmap_invalidate_all(pmap); 3106 vm_page_unlock_queues(); 3107 PMAP_UNLOCK(pmap); 3108} 3109 3110/* 3111 * Tries to promote the 512 or 1024, contiguous 4KB page mappings that are 3112 * within a single page table page (PTP) to a single 2- or 4MB page mapping. 3113 * For promotion to occur, two conditions must be met: (1) the 4KB page 3114 * mappings must map aligned, contiguous physical memory and (2) the 4KB page 3115 * mappings must have identical characteristics. 3116 * 3117 * Managed (PG_MANAGED) mappings within the kernel address space are not 3118 * promoted. The reason is that kernel PDEs are replicated in each pmap but 3119 * pmap_clear_ptes() and pmap_ts_referenced() only read the PDE from the kernel 3120 * pmap. 3121 */ 3122static void 3123pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va) 3124{ 3125 pd_entry_t newpde; 3126 pt_entry_t *firstpte, oldpte, pa, *pte; 3127 vm_offset_t oldpteva; 3128 vm_page_t mpte; 3129 3130 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 3131 3132 /* 3133 * Examine the first PTE in the specified PTP. Abort if this PTE is 3134 * either invalid, unused, or does not map the first 4KB physical page 3135 * within a 2- or 4MB page. 3136 */ 3137 firstpte = pmap_pte_quick(pmap, trunc_4mpage(va)); 3138setpde: 3139 newpde = *firstpte; 3140 if ((newpde & ((PG_FRAME & PDRMASK) | PG_A | PG_V)) != (PG_A | PG_V)) { 3141 pmap_pde_p_failures++; 3142 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x" 3143 " in pmap %p", va, pmap); 3144 return; 3145 } 3146 if ((*firstpte & PG_MANAGED) != 0 && pmap == kernel_pmap) { 3147 pmap_pde_p_failures++; 3148 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x" 3149 " in pmap %p", va, pmap); 3150 return; 3151 } 3152 if ((newpde & (PG_M | PG_RW)) == PG_RW) { 3153 /* 3154 * When PG_M is already clear, PG_RW can be cleared without 3155 * a TLB invalidation. 3156 */ 3157 if (!atomic_cmpset_int((u_int *)firstpte, newpde, newpde & 3158 ~PG_RW)) 3159 goto setpde; 3160 newpde &= ~PG_RW; 3161 } 3162 3163 /* 3164 * Examine each of the other PTEs in the specified PTP. Abort if this 3165 * PTE maps an unexpected 4KB physical page or does not have identical 3166 * characteristics to the first PTE. 3167 */ 3168 pa = (newpde & (PG_PS_FRAME | PG_A | PG_V)) + NBPDR - PAGE_SIZE; 3169 for (pte = firstpte + NPTEPG - 1; pte > firstpte; pte--) { 3170setpte: 3171 oldpte = *pte; 3172 if ((oldpte & (PG_FRAME | PG_A | PG_V)) != pa) { 3173 pmap_pde_p_failures++; 3174 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x" 3175 " in pmap %p", va, pmap); 3176 return; 3177 } 3178 if ((oldpte & (PG_M | PG_RW)) == PG_RW) { 3179 /* 3180 * When PG_M is already clear, PG_RW can be cleared 3181 * without a TLB invalidation. 3182 */ 3183 if (!atomic_cmpset_int((u_int *)pte, oldpte, 3184 oldpte & ~PG_RW)) 3185 goto setpte; 3186 oldpte &= ~PG_RW; 3187 oldpteva = (oldpte & PG_FRAME & PDRMASK) | 3188 (va & ~PDRMASK); 3189 CTR2(KTR_PMAP, "pmap_promote_pde: protect for va %#x" 3190 " in pmap %p", oldpteva, pmap); 3191 } 3192 if ((oldpte & PG_PTE_PROMOTE) != (newpde & PG_PTE_PROMOTE)) { 3193 pmap_pde_p_failures++; 3194 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x" 3195 " in pmap %p", va, pmap); 3196 return; 3197 } 3198 pa -= PAGE_SIZE; 3199 } 3200 3201 /* 3202 * Save the page table page in its current state until the PDE 3203 * mapping the superpage is demoted by pmap_demote_pde() or 3204 * destroyed by pmap_remove_pde(). 3205 */ 3206 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME); 3207 KASSERT(mpte >= vm_page_array && 3208 mpte < &vm_page_array[vm_page_array_size], 3209 ("pmap_promote_pde: page table page is out of range")); 3210 KASSERT(mpte->pindex == va >> PDRSHIFT, 3211 ("pmap_promote_pde: page table page's pindex is wrong")); 3212 pmap_insert_pt_page(pmap, mpte); 3213 3214 /* 3215 * Promote the pv entries. 3216 */ 3217 if ((newpde & PG_MANAGED) != 0) 3218 pmap_pv_promote_pde(pmap, va, newpde & PG_PS_FRAME); 3219 3220 /* 3221 * Propagate the PAT index to its proper position. 3222 */ 3223 if ((newpde & PG_PTE_PAT) != 0) 3224 newpde ^= PG_PDE_PAT | PG_PTE_PAT; 3225 3226 /* 3227 * Map the superpage. 3228 */ 3229 if (workaround_erratum383) 3230 pmap_update_pde(pmap, va, pde, PG_PS | newpde); 3231 else if (pmap == kernel_pmap) 3232 pmap_kenter_pde(va, PG_PS | newpde); 3233 else 3234 pde_store(pde, PG_PS | newpde); 3235 3236 pmap_pde_promotions++; 3237 CTR2(KTR_PMAP, "pmap_promote_pde: success for va %#x" 3238 " in pmap %p", va, pmap); 3239} 3240 3241/* 3242 * Insert the given physical page (p) at 3243 * the specified virtual address (v) in the 3244 * target physical map with the protection requested. 3245 * 3246 * If specified, the page will be wired down, meaning 3247 * that the related pte can not be reclaimed. 3248 * 3249 * NB: This is the only routine which MAY NOT lazy-evaluate 3250 * or lose information. That is, this routine must actually 3251 * insert this page into the given map NOW. 3252 */ 3253void 3254pmap_enter(pmap_t pmap, vm_offset_t va, vm_prot_t access, vm_page_t m, 3255 vm_prot_t prot, boolean_t wired) 3256{ 3257 pd_entry_t *pde; 3258 pt_entry_t *pte; 3259 pt_entry_t newpte, origpte; 3260 pv_entry_t pv; 3261 vm_paddr_t opa, pa; 3262 vm_page_t mpte, om; 3263 boolean_t invlva; 3264 3265 va = trunc_page(va); 3266 KASSERT(va <= VM_MAX_KERNEL_ADDRESS, ("pmap_enter: toobig")); 3267 KASSERT(va < UPT_MIN_ADDRESS || va >= UPT_MAX_ADDRESS, 3268 ("pmap_enter: invalid to pmap_enter page table pages (va: 0x%x)", 3269 va)); 3270 KASSERT((m->oflags & VPO_BUSY) != 0, 3271 ("pmap_enter: page %p is not busy", m)); 3272 3273 mpte = NULL; 3274 3275 vm_page_lock_queues(); 3276 PMAP_LOCK(pmap); 3277 sched_pin(); 3278 3279 /* 3280 * In the case that a page table page is not 3281 * resident, we are creating it here. 3282 */ 3283 if (va < VM_MAXUSER_ADDRESS) { 3284 mpte = pmap_allocpte(pmap, va, M_WAITOK); 3285 } 3286 3287 pde = pmap_pde(pmap, va); 3288 if ((*pde & PG_PS) != 0) 3289 panic("pmap_enter: attempted pmap_enter on 4MB page"); 3290 pte = pmap_pte_quick(pmap, va); 3291 3292 /* 3293 * Page Directory table entry not valid, we need a new PT page 3294 */ 3295 if (pte == NULL) { 3296 panic("pmap_enter: invalid page directory pdir=%#jx, va=%#x", 3297 (uintmax_t)pmap->pm_pdir[PTDPTDI], va); 3298 } 3299 3300 pa = VM_PAGE_TO_PHYS(m); 3301 om = NULL; 3302 origpte = *pte; 3303 opa = origpte & PG_FRAME; 3304 3305 /* 3306 * Mapping has not changed, must be protection or wiring change. 3307 */ 3308 if (origpte && (opa == pa)) { 3309 /* 3310 * Wiring change, just update stats. We don't worry about 3311 * wiring PT pages as they remain resident as long as there 3312 * are valid mappings in them. Hence, if a user page is wired, 3313 * the PT page will be also. 3314 */ 3315 if (wired && ((origpte & PG_W) == 0)) 3316 pmap->pm_stats.wired_count++; 3317 else if (!wired && (origpte & PG_W)) 3318 pmap->pm_stats.wired_count--; 3319 3320 /* 3321 * Remove extra pte reference 3322 */ 3323 if (mpte) 3324 mpte->wire_count--; 3325 3326 if (origpte & PG_MANAGED) { 3327 om = m; 3328 pa |= PG_MANAGED; 3329 } 3330 goto validate; 3331 } 3332 3333 pv = NULL; 3334 3335 /* 3336 * Mapping has changed, invalidate old range and fall through to 3337 * handle validating new mapping. 3338 */ 3339 if (opa) { 3340 if (origpte & PG_W) 3341 pmap->pm_stats.wired_count--; 3342 if (origpte & PG_MANAGED) { 3343 om = PHYS_TO_VM_PAGE(opa); 3344 pv = pmap_pvh_remove(&om->md, pmap, va); 3345 } 3346 if (mpte != NULL) { 3347 mpte->wire_count--; 3348 KASSERT(mpte->wire_count > 0, 3349 ("pmap_enter: missing reference to page table page," 3350 " va: 0x%x", va)); 3351 } 3352 } else 3353 pmap->pm_stats.resident_count++; 3354 3355 /* 3356 * Enter on the PV list if part of our managed memory. 3357 */ 3358 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0) { 3359 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva, 3360 ("pmap_enter: managed mapping within the clean submap")); 3361 if (pv == NULL) 3362 pv = get_pv_entry(pmap, FALSE); 3363 pv->pv_va = va; 3364 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list); 3365 pa |= PG_MANAGED; 3366 } else if (pv != NULL) 3367 free_pv_entry(pmap, pv); 3368 3369 /* 3370 * Increment counters 3371 */ 3372 if (wired) 3373 pmap->pm_stats.wired_count++; 3374 3375validate: 3376 /* 3377 * Now validate mapping with desired protection/wiring. 3378 */ 3379 newpte = (pt_entry_t)(pa | pmap_cache_bits(m->md.pat_mode, 0) | PG_V); 3380 if ((prot & VM_PROT_WRITE) != 0) { 3381 newpte |= PG_RW; 3382 if ((newpte & PG_MANAGED) != 0) 3383 vm_page_flag_set(m, PG_WRITEABLE); 3384 } 3385#ifdef PAE 3386 if ((prot & VM_PROT_EXECUTE) == 0) 3387 newpte |= pg_nx; 3388#endif 3389 if (wired) 3390 newpte |= PG_W; 3391 if (va < VM_MAXUSER_ADDRESS) 3392 newpte |= PG_U; 3393 if (pmap == kernel_pmap) 3394 newpte |= pgeflag; 3395 3396 /* 3397 * if the mapping or permission bits are different, we need 3398 * to update the pte. 3399 */ 3400 if ((origpte & ~(PG_M|PG_A)) != newpte) { 3401 newpte |= PG_A; 3402 if ((access & VM_PROT_WRITE) != 0) 3403 newpte |= PG_M; 3404 if (origpte & PG_V) { 3405 invlva = FALSE; 3406 origpte = pte_load_store(pte, newpte); 3407 if (origpte & PG_A) { 3408 if (origpte & PG_MANAGED) 3409 vm_page_flag_set(om, PG_REFERENCED); 3410 if (opa != VM_PAGE_TO_PHYS(m)) 3411 invlva = TRUE; 3412#ifdef PAE 3413 if ((origpte & PG_NX) == 0 && 3414 (newpte & PG_NX) != 0) 3415 invlva = TRUE; 3416#endif 3417 } 3418 if ((origpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) { 3419 if ((origpte & PG_MANAGED) != 0) 3420 vm_page_dirty(om); 3421 if ((prot & VM_PROT_WRITE) == 0) 3422 invlva = TRUE; 3423 } 3424 if ((origpte & PG_MANAGED) != 0 && 3425 TAILQ_EMPTY(&om->md.pv_list) && 3426 TAILQ_EMPTY(&pa_to_pvh(opa)->pv_list)) 3427 vm_page_flag_clear(om, PG_WRITEABLE); 3428 if (invlva) 3429 pmap_invalidate_page(pmap, va); 3430 } else 3431 pte_store(pte, newpte); 3432 } 3433 3434 /* 3435 * If both the page table page and the reservation are fully 3436 * populated, then attempt promotion. 3437 */ 3438 if ((mpte == NULL || mpte->wire_count == NPTEPG) && 3439 pg_ps_enabled && vm_reserv_level_iffullpop(m) == 0) 3440 pmap_promote_pde(pmap, pde, va); 3441 3442 sched_unpin(); 3443 vm_page_unlock_queues(); 3444 PMAP_UNLOCK(pmap); 3445} 3446 3447/* 3448 * Tries to create a 2- or 4MB page mapping. Returns TRUE if successful and 3449 * FALSE otherwise. Fails if (1) a page table page cannot be allocated without 3450 * blocking, (2) a mapping already exists at the specified virtual address, or 3451 * (3) a pv entry cannot be allocated without reclaiming another pv entry. 3452 */ 3453static boolean_t 3454pmap_enter_pde(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot) 3455{ 3456 pd_entry_t *pde, newpde; 3457 3458 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 3459 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 3460 pde = pmap_pde(pmap, va); 3461 if (*pde != 0) { 3462 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx" 3463 " in pmap %p", va, pmap); 3464 return (FALSE); 3465 } 3466 newpde = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(m->md.pat_mode, 1) | 3467 PG_PS | PG_V; 3468 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0) { 3469 newpde |= PG_MANAGED; 3470 3471 /* 3472 * Abort this mapping if its PV entry could not be created. 3473 */ 3474 if (!pmap_pv_insert_pde(pmap, va, VM_PAGE_TO_PHYS(m))) { 3475 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx" 3476 " in pmap %p", va, pmap); 3477 return (FALSE); 3478 } 3479 } 3480#ifdef PAE 3481 if ((prot & VM_PROT_EXECUTE) == 0) 3482 newpde |= pg_nx; 3483#endif 3484 if (va < VM_MAXUSER_ADDRESS) 3485 newpde |= PG_U; 3486 3487 /* 3488 * Increment counters. 3489 */ 3490 pmap->pm_stats.resident_count += NBPDR / PAGE_SIZE; 3491 3492 /* 3493 * Map the superpage. 3494 */ 3495 pde_store(pde, newpde); 3496 3497 pmap_pde_mappings++; 3498 CTR2(KTR_PMAP, "pmap_enter_pde: success for va %#lx" 3499 " in pmap %p", va, pmap); 3500 return (TRUE); 3501} 3502 3503/* 3504 * Maps a sequence of resident pages belonging to the same object. 3505 * The sequence begins with the given page m_start. This page is 3506 * mapped at the given virtual address start. Each subsequent page is 3507 * mapped at a virtual address that is offset from start by the same 3508 * amount as the page is offset from m_start within the object. The 3509 * last page in the sequence is the page with the largest offset from 3510 * m_start that can be mapped at a virtual address less than the given 3511 * virtual address end. Not every virtual page between start and end 3512 * is mapped; only those for which a resident page exists with the 3513 * corresponding offset from m_start are mapped. 3514 */ 3515void 3516pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end, 3517 vm_page_t m_start, vm_prot_t prot) 3518{ 3519 vm_offset_t va; 3520 vm_page_t m, mpte; 3521 vm_pindex_t diff, psize; 3522 3523 VM_OBJECT_LOCK_ASSERT(m_start->object, MA_OWNED); 3524 psize = atop(end - start); 3525 mpte = NULL; 3526 m = m_start; 3527 vm_page_lock_queues(); 3528 PMAP_LOCK(pmap); 3529 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 3530 va = start + ptoa(diff); 3531 if ((va & PDRMASK) == 0 && va + NBPDR <= end && 3532 (VM_PAGE_TO_PHYS(m) & PDRMASK) == 0 && 3533 pg_ps_enabled && vm_reserv_level_iffullpop(m) == 0 && 3534 pmap_enter_pde(pmap, va, m, prot)) 3535 m = &m[NBPDR / PAGE_SIZE - 1]; 3536 else 3537 mpte = pmap_enter_quick_locked(pmap, va, m, prot, 3538 mpte); 3539 m = TAILQ_NEXT(m, listq); 3540 } 3541 vm_page_unlock_queues(); 3542 PMAP_UNLOCK(pmap); 3543} 3544 3545/* 3546 * this code makes some *MAJOR* assumptions: 3547 * 1. Current pmap & pmap exists. 3548 * 2. Not wired. 3549 * 3. Read access. 3550 * 4. No page table pages. 3551 * but is *MUCH* faster than pmap_enter... 3552 */ 3553 3554void 3555pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot) 3556{ 3557 3558 vm_page_lock_queues(); 3559 PMAP_LOCK(pmap); 3560 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL); 3561 vm_page_unlock_queues(); 3562 PMAP_UNLOCK(pmap); 3563} 3564 3565static vm_page_t 3566pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m, 3567 vm_prot_t prot, vm_page_t mpte) 3568{ 3569 pt_entry_t *pte; 3570 vm_paddr_t pa; 3571 vm_page_t free; 3572 3573 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva || 3574 (m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0, 3575 ("pmap_enter_quick_locked: managed mapping within the clean submap")); 3576 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 3577 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 3578 3579 /* 3580 * In the case that a page table page is not 3581 * resident, we are creating it here. 3582 */ 3583 if (va < VM_MAXUSER_ADDRESS) { 3584 unsigned ptepindex; 3585 pd_entry_t ptepa; 3586 3587 /* 3588 * Calculate pagetable page index 3589 */ 3590 ptepindex = va >> PDRSHIFT; 3591 if (mpte && (mpte->pindex == ptepindex)) { 3592 mpte->wire_count++; 3593 } else { 3594 /* 3595 * Get the page directory entry 3596 */ 3597 ptepa = pmap->pm_pdir[ptepindex]; 3598 3599 /* 3600 * If the page table page is mapped, we just increment 3601 * the hold count, and activate it. 3602 */ 3603 if (ptepa) { 3604 if (ptepa & PG_PS) 3605 return (NULL); 3606 mpte = PHYS_TO_VM_PAGE(ptepa & PG_FRAME); 3607 mpte->wire_count++; 3608 } else { 3609 mpte = _pmap_allocpte(pmap, ptepindex, 3610 M_NOWAIT); 3611 if (mpte == NULL) 3612 return (mpte); 3613 } 3614 } 3615 } else { 3616 mpte = NULL; 3617 } 3618 3619 /* 3620 * This call to vtopte makes the assumption that we are 3621 * entering the page into the current pmap. In order to support 3622 * quick entry into any pmap, one would likely use pmap_pte_quick. 3623 * But that isn't as quick as vtopte. 3624 */ 3625 pte = vtopte(va); 3626 if (*pte) { 3627 if (mpte != NULL) { 3628 mpte->wire_count--; 3629 mpte = NULL; 3630 } 3631 return (mpte); 3632 } 3633 3634 /* 3635 * Enter on the PV list if part of our managed memory. 3636 */ 3637 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0 && 3638 !pmap_try_insert_pv_entry(pmap, va, m)) { 3639 if (mpte != NULL) { 3640 free = NULL; 3641 if (pmap_unwire_pte_hold(pmap, mpte, &free)) { 3642 pmap_invalidate_page(pmap, va); 3643 pmap_free_zero_pages(free); 3644 } 3645 3646 mpte = NULL; 3647 } 3648 return (mpte); 3649 } 3650 3651 /* 3652 * Increment counters 3653 */ 3654 pmap->pm_stats.resident_count++; 3655 3656 pa = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(m->md.pat_mode, 0); 3657#ifdef PAE 3658 if ((prot & VM_PROT_EXECUTE) == 0) 3659 pa |= pg_nx; 3660#endif 3661 3662 /* 3663 * Now validate mapping with RO protection 3664 */ 3665 if (m->flags & (PG_FICTITIOUS|PG_UNMANAGED)) 3666 pte_store(pte, pa | PG_V | PG_U); 3667 else 3668 pte_store(pte, pa | PG_V | PG_U | PG_MANAGED); 3669 return (mpte); 3670} 3671 3672/* 3673 * Make a temporary mapping for a physical address. This is only intended 3674 * to be used for panic dumps. 3675 */ 3676void * 3677pmap_kenter_temporary(vm_paddr_t pa, int i) 3678{ 3679 vm_offset_t va; 3680 3681 va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE); 3682 pmap_kenter(va, pa); 3683 invlpg(va); 3684 return ((void *)crashdumpmap); 3685} 3686 3687/* 3688 * This code maps large physical mmap regions into the 3689 * processor address space. Note that some shortcuts 3690 * are taken, but the code works. 3691 */ 3692void 3693pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object, 3694 vm_pindex_t pindex, vm_size_t size) 3695{ 3696 pd_entry_t *pde; 3697 vm_paddr_t pa, ptepa; 3698 vm_page_t p; 3699 int pat_mode; 3700 3701 VM_OBJECT_LOCK_ASSERT(object, MA_OWNED); 3702 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG, 3703 ("pmap_object_init_pt: non-device object")); 3704 if (pseflag && 3705 (addr & (NBPDR - 1)) == 0 && (size & (NBPDR - 1)) == 0) { 3706 if (!vm_object_populate(object, pindex, pindex + atop(size))) 3707 return; 3708 p = vm_page_lookup(object, pindex); 3709 KASSERT(p->valid == VM_PAGE_BITS_ALL, 3710 ("pmap_object_init_pt: invalid page %p", p)); 3711 pat_mode = p->md.pat_mode; 3712 3713 /* 3714 * Abort the mapping if the first page is not physically 3715 * aligned to a 2/4MB page boundary. 3716 */ 3717 ptepa = VM_PAGE_TO_PHYS(p); 3718 if (ptepa & (NBPDR - 1)) 3719 return; 3720 3721 /* 3722 * Skip the first page. Abort the mapping if the rest of 3723 * the pages are not physically contiguous or have differing 3724 * memory attributes. 3725 */ 3726 p = TAILQ_NEXT(p, listq); 3727 for (pa = ptepa + PAGE_SIZE; pa < ptepa + size; 3728 pa += PAGE_SIZE) { 3729 KASSERT(p->valid == VM_PAGE_BITS_ALL, 3730 ("pmap_object_init_pt: invalid page %p", p)); 3731 if (pa != VM_PAGE_TO_PHYS(p) || 3732 pat_mode != p->md.pat_mode) 3733 return; 3734 p = TAILQ_NEXT(p, listq); 3735 } 3736 3737 /* 3738 * Map using 2/4MB pages. Since "ptepa" is 2/4M aligned and 3739 * "size" is a multiple of 2/4M, adding the PAT setting to 3740 * "pa" will not affect the termination of this loop. 3741 */ 3742 PMAP_LOCK(pmap); 3743 for (pa = ptepa | pmap_cache_bits(pat_mode, 1); pa < ptepa + 3744 size; pa += NBPDR) { 3745 pde = pmap_pde(pmap, addr); 3746 if (*pde == 0) { 3747 pde_store(pde, pa | PG_PS | PG_M | PG_A | 3748 PG_U | PG_RW | PG_V); 3749 pmap->pm_stats.resident_count += NBPDR / 3750 PAGE_SIZE; 3751 pmap_pde_mappings++; 3752 } 3753 /* Else continue on if the PDE is already valid. */ 3754 addr += NBPDR; 3755 } 3756 PMAP_UNLOCK(pmap); 3757 } 3758} 3759 3760/* 3761 * Routine: pmap_change_wiring 3762 * Function: Change the wiring attribute for a map/virtual-address 3763 * pair. 3764 * In/out conditions: 3765 * The mapping must already exist in the pmap. 3766 */ 3767void 3768pmap_change_wiring(pmap_t pmap, vm_offset_t va, boolean_t wired) 3769{ 3770 pd_entry_t *pde; 3771 pt_entry_t *pte; 3772 boolean_t are_queues_locked; 3773 3774 are_queues_locked = FALSE; 3775retry: 3776 PMAP_LOCK(pmap); 3777 pde = pmap_pde(pmap, va); 3778 if ((*pde & PG_PS) != 0) { 3779 if (!wired != ((*pde & PG_W) == 0)) { 3780 if (!are_queues_locked) { 3781 are_queues_locked = TRUE; 3782 if (!mtx_trylock(&vm_page_queue_mtx)) { 3783 PMAP_UNLOCK(pmap); 3784 vm_page_lock_queues(); 3785 goto retry; 3786 } 3787 } 3788 if (!pmap_demote_pde(pmap, pde, va)) 3789 panic("pmap_change_wiring: demotion failed"); 3790 } else 3791 goto out; 3792 } 3793 pte = pmap_pte(pmap, va); 3794 3795 if (wired && !pmap_pte_w(pte)) 3796 pmap->pm_stats.wired_count++; 3797 else if (!wired && pmap_pte_w(pte)) 3798 pmap->pm_stats.wired_count--; 3799 3800 /* 3801 * Wiring is not a hardware characteristic so there is no need to 3802 * invalidate TLB. 3803 */ 3804 pmap_pte_set_w(pte, wired); 3805 pmap_pte_release(pte); 3806out: 3807 if (are_queues_locked) 3808 vm_page_unlock_queues(); 3809 PMAP_UNLOCK(pmap); 3810} 3811 3812 3813 3814/* 3815 * Copy the range specified by src_addr/len 3816 * from the source map to the range dst_addr/len 3817 * in the destination map. 3818 * 3819 * This routine is only advisory and need not do anything. 3820 */ 3821 3822void 3823pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len, 3824 vm_offset_t src_addr) 3825{ 3826 vm_page_t free; 3827 vm_offset_t addr; 3828 vm_offset_t end_addr = src_addr + len; 3829 vm_offset_t pdnxt; 3830 3831 if (dst_addr != src_addr) 3832 return; 3833 3834 if (!pmap_is_current(src_pmap)) 3835 return; 3836 3837 vm_page_lock_queues(); 3838 if (dst_pmap < src_pmap) { 3839 PMAP_LOCK(dst_pmap); 3840 PMAP_LOCK(src_pmap); 3841 } else { 3842 PMAP_LOCK(src_pmap); 3843 PMAP_LOCK(dst_pmap); 3844 } 3845 sched_pin(); 3846 for (addr = src_addr; addr < end_addr; addr = pdnxt) { 3847 pt_entry_t *src_pte, *dst_pte; 3848 vm_page_t dstmpte, srcmpte; 3849 pd_entry_t srcptepaddr; 3850 unsigned ptepindex; 3851 3852 KASSERT(addr < UPT_MIN_ADDRESS, 3853 ("pmap_copy: invalid to pmap_copy page tables")); 3854 3855 pdnxt = (addr + NBPDR) & ~PDRMASK; 3856 if (pdnxt < addr) 3857 pdnxt = end_addr; 3858 ptepindex = addr >> PDRSHIFT; 3859 3860 srcptepaddr = src_pmap->pm_pdir[ptepindex]; 3861 if (srcptepaddr == 0) 3862 continue; 3863 3864 if (srcptepaddr & PG_PS) { 3865 if (dst_pmap->pm_pdir[ptepindex] == 0 && 3866 ((srcptepaddr & PG_MANAGED) == 0 || 3867 pmap_pv_insert_pde(dst_pmap, addr, srcptepaddr & 3868 PG_PS_FRAME))) { 3869 dst_pmap->pm_pdir[ptepindex] = srcptepaddr & 3870 ~PG_W; 3871 dst_pmap->pm_stats.resident_count += 3872 NBPDR / PAGE_SIZE; 3873 } 3874 continue; 3875 } 3876 3877 srcmpte = PHYS_TO_VM_PAGE(srcptepaddr & PG_FRAME); 3878 KASSERT(srcmpte->wire_count > 0, 3879 ("pmap_copy: source page table page is unused")); 3880 3881 if (pdnxt > end_addr) 3882 pdnxt = end_addr; 3883 3884 src_pte = vtopte(addr); 3885 while (addr < pdnxt) { 3886 pt_entry_t ptetemp; 3887 ptetemp = *src_pte; 3888 /* 3889 * we only virtual copy managed pages 3890 */ 3891 if ((ptetemp & PG_MANAGED) != 0) { 3892 dstmpte = pmap_allocpte(dst_pmap, addr, 3893 M_NOWAIT); 3894 if (dstmpte == NULL) 3895 goto out; 3896 dst_pte = pmap_pte_quick(dst_pmap, addr); 3897 if (*dst_pte == 0 && 3898 pmap_try_insert_pv_entry(dst_pmap, addr, 3899 PHYS_TO_VM_PAGE(ptetemp & PG_FRAME))) { 3900 /* 3901 * Clear the wired, modified, and 3902 * accessed (referenced) bits 3903 * during the copy. 3904 */ 3905 *dst_pte = ptetemp & ~(PG_W | PG_M | 3906 PG_A); 3907 dst_pmap->pm_stats.resident_count++; 3908 } else { 3909 free = NULL; 3910 if (pmap_unwire_pte_hold(dst_pmap, 3911 dstmpte, &free)) { 3912 pmap_invalidate_page(dst_pmap, 3913 addr); 3914 pmap_free_zero_pages(free); 3915 } 3916 goto out; 3917 } 3918 if (dstmpte->wire_count >= srcmpte->wire_count) 3919 break; 3920 } 3921 addr += PAGE_SIZE; 3922 src_pte++; 3923 } 3924 } 3925out: 3926 sched_unpin(); 3927 vm_page_unlock_queues(); 3928 PMAP_UNLOCK(src_pmap); 3929 PMAP_UNLOCK(dst_pmap); 3930} 3931 3932static __inline void 3933pagezero(void *page) 3934{ 3935#if defined(I686_CPU) 3936 if (cpu_class == CPUCLASS_686) { 3937#if defined(CPU_ENABLE_SSE) 3938 if (cpu_feature & CPUID_SSE2) 3939 sse2_pagezero(page); 3940 else 3941#endif 3942 i686_pagezero(page); 3943 } else 3944#endif 3945 bzero(page, PAGE_SIZE); 3946} 3947 3948/* 3949 * pmap_zero_page zeros the specified hardware page by mapping 3950 * the page into KVM and using bzero to clear its contents. 3951 */ 3952void 3953pmap_zero_page(vm_page_t m) 3954{ 3955 struct sysmaps *sysmaps; 3956 3957 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)]; 3958 mtx_lock(&sysmaps->lock); 3959 if (*sysmaps->CMAP2) 3960 panic("pmap_zero_page: CMAP2 busy"); 3961 sched_pin(); 3962 *sysmaps->CMAP2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M | 3963 pmap_cache_bits(m->md.pat_mode, 0); 3964 invlcaddr(sysmaps->CADDR2); 3965 pagezero(sysmaps->CADDR2); 3966 *sysmaps->CMAP2 = 0; 3967 sched_unpin(); 3968 mtx_unlock(&sysmaps->lock); 3969} 3970 3971/* 3972 * pmap_zero_page_area zeros the specified hardware page by mapping 3973 * the page into KVM and using bzero to clear its contents. 3974 * 3975 * off and size may not cover an area beyond a single hardware page. 3976 */ 3977void 3978pmap_zero_page_area(vm_page_t m, int off, int size) 3979{ 3980 struct sysmaps *sysmaps; 3981 3982 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)]; 3983 mtx_lock(&sysmaps->lock); 3984 if (*sysmaps->CMAP2) 3985 panic("pmap_zero_page_area: CMAP2 busy"); 3986 sched_pin(); 3987 *sysmaps->CMAP2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M | 3988 pmap_cache_bits(m->md.pat_mode, 0); 3989 invlcaddr(sysmaps->CADDR2); 3990 if (off == 0 && size == PAGE_SIZE) 3991 pagezero(sysmaps->CADDR2); 3992 else 3993 bzero((char *)sysmaps->CADDR2 + off, size); 3994 *sysmaps->CMAP2 = 0; 3995 sched_unpin(); 3996 mtx_unlock(&sysmaps->lock); 3997} 3998 3999/* 4000 * pmap_zero_page_idle zeros the specified hardware page by mapping 4001 * the page into KVM and using bzero to clear its contents. This 4002 * is intended to be called from the vm_pagezero process only and 4003 * outside of Giant. 4004 */ 4005void 4006pmap_zero_page_idle(vm_page_t m) 4007{ 4008 4009 if (*CMAP3) 4010 panic("pmap_zero_page_idle: CMAP3 busy"); 4011 sched_pin(); 4012 *CMAP3 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M | 4013 pmap_cache_bits(m->md.pat_mode, 0); 4014 invlcaddr(CADDR3); 4015 pagezero(CADDR3); 4016 *CMAP3 = 0; 4017 sched_unpin(); 4018} 4019 4020/* 4021 * pmap_copy_page copies the specified (machine independent) 4022 * page by mapping the page into virtual memory and using 4023 * bcopy to copy the page, one machine dependent page at a 4024 * time. 4025 */ 4026void 4027pmap_copy_page(vm_page_t src, vm_page_t dst) 4028{ 4029 struct sysmaps *sysmaps; 4030 4031 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)]; 4032 mtx_lock(&sysmaps->lock); 4033 if (*sysmaps->CMAP1) 4034 panic("pmap_copy_page: CMAP1 busy"); 4035 if (*sysmaps->CMAP2) 4036 panic("pmap_copy_page: CMAP2 busy"); 4037 sched_pin(); 4038 invlpg((u_int)sysmaps->CADDR1); 4039 invlpg((u_int)sysmaps->CADDR2); 4040 *sysmaps->CMAP1 = PG_V | VM_PAGE_TO_PHYS(src) | PG_A | 4041 pmap_cache_bits(src->md.pat_mode, 0); 4042 *sysmaps->CMAP2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(dst) | PG_A | PG_M | 4043 pmap_cache_bits(dst->md.pat_mode, 0); 4044 bcopy(sysmaps->CADDR1, sysmaps->CADDR2, PAGE_SIZE); 4045 *sysmaps->CMAP1 = 0; 4046 *sysmaps->CMAP2 = 0; 4047 sched_unpin(); 4048 mtx_unlock(&sysmaps->lock); 4049} 4050 4051/* 4052 * Returns true if the pmap's pv is one of the first 4053 * 16 pvs linked to from this page. This count may 4054 * be changed upwards or downwards in the future; it 4055 * is only necessary that true be returned for a small 4056 * subset of pmaps for proper page aging. 4057 */ 4058boolean_t 4059pmap_page_exists_quick(pmap_t pmap, vm_page_t m) 4060{ 4061 struct md_page *pvh; 4062 pv_entry_t pv; 4063 int loops = 0; 4064 4065 if (m->flags & PG_FICTITIOUS) 4066 return (FALSE); 4067 4068 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 4069 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 4070 if (PV_PMAP(pv) == pmap) { 4071 return (TRUE); 4072 } 4073 loops++; 4074 if (loops >= 16) 4075 break; 4076 } 4077 if (loops < 16) { 4078 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 4079 TAILQ_FOREACH(pv, &pvh->pv_list, pv_list) { 4080 if (PV_PMAP(pv) == pmap) 4081 return (TRUE); 4082 loops++; 4083 if (loops >= 16) 4084 break; 4085 } 4086 } 4087 return (FALSE); 4088} 4089 4090/* 4091 * pmap_page_wired_mappings: 4092 * 4093 * Return the number of managed mappings to the given physical page 4094 * that are wired. 4095 */ 4096int 4097pmap_page_wired_mappings(vm_page_t m) 4098{ 4099 int count; 4100 4101 count = 0; 4102 if ((m->flags & PG_FICTITIOUS) != 0) 4103 return (count); 4104 vm_page_lock_queues(); 4105 count = pmap_pvh_wired_mappings(&m->md, count); 4106 count = pmap_pvh_wired_mappings(pa_to_pvh(VM_PAGE_TO_PHYS(m)), count); 4107 vm_page_unlock_queues(); 4108 return (count); 4109} 4110 4111/* 4112 * pmap_pvh_wired_mappings: 4113 * 4114 * Return the updated number "count" of managed mappings that are wired. 4115 */ 4116static int 4117pmap_pvh_wired_mappings(struct md_page *pvh, int count) 4118{ 4119 pmap_t pmap; 4120 pt_entry_t *pte; 4121 pv_entry_t pv; 4122 4123 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 4124 sched_pin(); 4125 TAILQ_FOREACH(pv, &pvh->pv_list, pv_list) { 4126 pmap = PV_PMAP(pv); 4127 PMAP_LOCK(pmap); 4128 pte = pmap_pte_quick(pmap, pv->pv_va); 4129 if ((*pte & PG_W) != 0) 4130 count++; 4131 PMAP_UNLOCK(pmap); 4132 } 4133 sched_unpin(); 4134 return (count); 4135} 4136 4137/* 4138 * Returns TRUE if the given page is mapped individually or as part of 4139 * a 4mpage. Otherwise, returns FALSE. 4140 */ 4141boolean_t 4142pmap_page_is_mapped(vm_page_t m) 4143{ 4144 boolean_t rv; 4145 4146 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0) 4147 return (FALSE); 4148 vm_page_lock_queues(); 4149 rv = !TAILQ_EMPTY(&m->md.pv_list) || 4150 !TAILQ_EMPTY(&pa_to_pvh(VM_PAGE_TO_PHYS(m))->pv_list); 4151 vm_page_unlock_queues(); 4152 return (rv); 4153} 4154 4155/* 4156 * Remove all pages from specified address space 4157 * this aids process exit speeds. Also, this code 4158 * is special cased for current process only, but 4159 * can have the more generic (and slightly slower) 4160 * mode enabled. This is much faster than pmap_remove 4161 * in the case of running down an entire address space. 4162 */ 4163void 4164pmap_remove_pages(pmap_t pmap) 4165{ 4166 pt_entry_t *pte, tpte; 4167 vm_page_t free = NULL; 4168 vm_page_t m, mpte, mt; 4169 pv_entry_t pv; 4170 struct md_page *pvh; 4171 struct pv_chunk *pc, *npc; 4172 int field, idx; 4173 int32_t bit; 4174 uint32_t inuse, bitmask; 4175 int allfree; 4176 4177 if (pmap != vmspace_pmap(curthread->td_proc->p_vmspace)) { 4178 printf("warning: pmap_remove_pages called with non-current pmap\n"); 4179 return; 4180 } 4181 vm_page_lock_queues(); 4182 PMAP_LOCK(pmap); 4183 sched_pin(); 4184 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) { 4185 allfree = 1; 4186 for (field = 0; field < _NPCM; field++) { 4187 inuse = (~(pc->pc_map[field])) & pc_freemask[field]; 4188 while (inuse != 0) { 4189 bit = bsfl(inuse); 4190 bitmask = 1UL << bit; 4191 idx = field * 32 + bit; 4192 pv = &pc->pc_pventry[idx]; 4193 inuse &= ~bitmask; 4194 4195 pte = pmap_pde(pmap, pv->pv_va); 4196 tpte = *pte; 4197 if ((tpte & PG_PS) == 0) { 4198 pte = vtopte(pv->pv_va); 4199 tpte = *pte & ~PG_PTE_PAT; 4200 } 4201 4202 if (tpte == 0) { 4203 printf( 4204 "TPTE at %p IS ZERO @ VA %08x\n", 4205 pte, pv->pv_va); 4206 panic("bad pte"); 4207 } 4208 4209/* 4210 * We cannot remove wired pages from a process' mapping at this time 4211 */ 4212 if (tpte & PG_W) { 4213 allfree = 0; 4214 continue; 4215 } 4216 4217 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME); 4218 KASSERT(m->phys_addr == (tpte & PG_FRAME), 4219 ("vm_page_t %p phys_addr mismatch %016jx %016jx", 4220 m, (uintmax_t)m->phys_addr, 4221 (uintmax_t)tpte)); 4222 4223 KASSERT(m < &vm_page_array[vm_page_array_size], 4224 ("pmap_remove_pages: bad tpte %#jx", 4225 (uintmax_t)tpte)); 4226 4227 pte_clear(pte); 4228 4229 /* 4230 * Update the vm_page_t clean/reference bits. 4231 */ 4232 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) { 4233 if ((tpte & PG_PS) != 0) { 4234 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++) 4235 vm_page_dirty(mt); 4236 } else 4237 vm_page_dirty(m); 4238 } 4239 4240 /* Mark free */ 4241 PV_STAT(pv_entry_frees++); 4242 PV_STAT(pv_entry_spare++); 4243 pv_entry_count--; 4244 pc->pc_map[field] |= bitmask; 4245 if ((tpte & PG_PS) != 0) { 4246 pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE; 4247 pvh = pa_to_pvh(tpte & PG_PS_FRAME); 4248 TAILQ_REMOVE(&pvh->pv_list, pv, pv_list); 4249 if (TAILQ_EMPTY(&pvh->pv_list)) { 4250 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++) 4251 if (TAILQ_EMPTY(&mt->md.pv_list)) 4252 vm_page_flag_clear(mt, PG_WRITEABLE); 4253 } 4254 mpte = pmap_lookup_pt_page(pmap, pv->pv_va); 4255 if (mpte != NULL) { 4256 pmap_remove_pt_page(pmap, mpte); 4257 pmap->pm_stats.resident_count--; 4258 KASSERT(mpte->wire_count == NPTEPG, 4259 ("pmap_remove_pages: pte page wire count error")); 4260 mpte->wire_count = 0; 4261 pmap_add_delayed_free_list(mpte, &free, FALSE); 4262 atomic_subtract_int(&cnt.v_wire_count, 1); 4263 } 4264 } else { 4265 pmap->pm_stats.resident_count--; 4266 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list); 4267 if (TAILQ_EMPTY(&m->md.pv_list)) { 4268 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 4269 if (TAILQ_EMPTY(&pvh->pv_list)) 4270 vm_page_flag_clear(m, PG_WRITEABLE); 4271 } 4272 pmap_unuse_pt(pmap, pv->pv_va, &free); 4273 } 4274 } 4275 } 4276 if (allfree) { 4277 PV_STAT(pv_entry_spare -= _NPCPV); 4278 PV_STAT(pc_chunk_count--); 4279 PV_STAT(pc_chunk_frees++); 4280 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 4281 m = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc)); 4282 pmap_qremove((vm_offset_t)pc, 1); 4283 vm_page_unwire(m, 0); 4284 vm_page_free(m); 4285 pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc); 4286 } 4287 } 4288 sched_unpin(); 4289 pmap_invalidate_all(pmap); 4290 vm_page_unlock_queues(); 4291 PMAP_UNLOCK(pmap); 4292 pmap_free_zero_pages(free); 4293} 4294 4295/* 4296 * pmap_is_modified: 4297 * 4298 * Return whether or not the specified physical page was modified 4299 * in any physical maps. 4300 */ 4301boolean_t 4302pmap_is_modified(vm_page_t m) 4303{ 4304 boolean_t rv; 4305 4306 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 4307 ("pmap_is_modified: page %p is not managed", m)); 4308 4309 /* 4310 * If the page is not VPO_BUSY, then PG_WRITEABLE cannot be 4311 * concurrently set while the object is locked. Thus, if PG_WRITEABLE 4312 * is clear, no PTEs can have PG_M set. 4313 */ 4314 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 4315 if ((m->oflags & VPO_BUSY) == 0 && 4316 (m->flags & PG_WRITEABLE) == 0) 4317 return (FALSE); 4318 vm_page_lock_queues(); 4319 rv = pmap_is_modified_pvh(&m->md) || 4320 pmap_is_modified_pvh(pa_to_pvh(VM_PAGE_TO_PHYS(m))); 4321 vm_page_unlock_queues(); 4322 return (rv); 4323} 4324 4325/* 4326 * Returns TRUE if any of the given mappings were used to modify 4327 * physical memory. Otherwise, returns FALSE. Both page and 2mpage 4328 * mappings are supported. 4329 */ 4330static boolean_t 4331pmap_is_modified_pvh(struct md_page *pvh) 4332{ 4333 pv_entry_t pv; 4334 pt_entry_t *pte; 4335 pmap_t pmap; 4336 boolean_t rv; 4337 4338 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 4339 rv = FALSE; 4340 sched_pin(); 4341 TAILQ_FOREACH(pv, &pvh->pv_list, pv_list) { 4342 pmap = PV_PMAP(pv); 4343 PMAP_LOCK(pmap); 4344 pte = pmap_pte_quick(pmap, pv->pv_va); 4345 rv = (*pte & (PG_M | PG_RW)) == (PG_M | PG_RW); 4346 PMAP_UNLOCK(pmap); 4347 if (rv) 4348 break; 4349 } 4350 sched_unpin(); 4351 return (rv); 4352} 4353 4354/* 4355 * pmap_is_prefaultable: 4356 * 4357 * Return whether or not the specified virtual address is elgible 4358 * for prefault. 4359 */ 4360boolean_t 4361pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr) 4362{ 4363 pd_entry_t *pde; 4364 pt_entry_t *pte; 4365 boolean_t rv; 4366 4367 rv = FALSE; 4368 PMAP_LOCK(pmap); 4369 pde = pmap_pde(pmap, addr); 4370 if (*pde != 0 && (*pde & PG_PS) == 0) { 4371 pte = vtopte(addr); 4372 rv = *pte == 0; 4373 } 4374 PMAP_UNLOCK(pmap); 4375 return (rv); 4376} 4377 4378/* 4379 * pmap_is_referenced: 4380 * 4381 * Return whether or not the specified physical page was referenced 4382 * in any physical maps. 4383 */ 4384boolean_t 4385pmap_is_referenced(vm_page_t m) 4386{ 4387 boolean_t rv; 4388 4389 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 4390 ("pmap_is_referenced: page %p is not managed", m)); 4391 vm_page_lock_queues(); 4392 rv = pmap_is_referenced_pvh(&m->md) || 4393 pmap_is_referenced_pvh(pa_to_pvh(VM_PAGE_TO_PHYS(m))); 4394 vm_page_unlock_queues(); 4395 return (rv); 4396} 4397 4398/* 4399 * Returns TRUE if any of the given mappings were referenced and FALSE 4400 * otherwise. Both page and 4mpage mappings are supported. 4401 */ 4402static boolean_t 4403pmap_is_referenced_pvh(struct md_page *pvh) 4404{ 4405 pv_entry_t pv; 4406 pt_entry_t *pte; 4407 pmap_t pmap; 4408 boolean_t rv; 4409 4410 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 4411 rv = FALSE; 4412 sched_pin(); 4413 TAILQ_FOREACH(pv, &pvh->pv_list, pv_list) { 4414 pmap = PV_PMAP(pv); 4415 PMAP_LOCK(pmap); 4416 pte = pmap_pte_quick(pmap, pv->pv_va); 4417 rv = (*pte & (PG_A | PG_V)) == (PG_A | PG_V); 4418 PMAP_UNLOCK(pmap); 4419 if (rv) 4420 break; 4421 } 4422 sched_unpin(); 4423 return (rv); 4424} 4425 4426/* 4427 * Clear the write and modified bits in each of the given page's mappings. 4428 */ 4429void 4430pmap_remove_write(vm_page_t m) 4431{ 4432 struct md_page *pvh; 4433 pv_entry_t next_pv, pv; 4434 pmap_t pmap; 4435 pd_entry_t *pde; 4436 pt_entry_t oldpte, *pte; 4437 vm_offset_t va; 4438 4439 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 4440 ("pmap_remove_write: page %p is not managed", m)); 4441 4442 /* 4443 * If the page is not VPO_BUSY, then PG_WRITEABLE cannot be set by 4444 * another thread while the object is locked. Thus, if PG_WRITEABLE 4445 * is clear, no page table entries need updating. 4446 */ 4447 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 4448 if ((m->oflags & VPO_BUSY) == 0 && 4449 (m->flags & PG_WRITEABLE) == 0) 4450 return; 4451 vm_page_lock_queues(); 4452 sched_pin(); 4453 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 4454 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_list, next_pv) { 4455 va = pv->pv_va; 4456 pmap = PV_PMAP(pv); 4457 PMAP_LOCK(pmap); 4458 pde = pmap_pde(pmap, va); 4459 if ((*pde & PG_RW) != 0) 4460 (void)pmap_demote_pde(pmap, pde, va); 4461 PMAP_UNLOCK(pmap); 4462 } 4463 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 4464 pmap = PV_PMAP(pv); 4465 PMAP_LOCK(pmap); 4466 pde = pmap_pde(pmap, pv->pv_va); 4467 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_write: found" 4468 " a 4mpage in page %p's pv list", m)); 4469 pte = pmap_pte_quick(pmap, pv->pv_va); 4470retry: 4471 oldpte = *pte; 4472 if ((oldpte & PG_RW) != 0) { 4473 /* 4474 * Regardless of whether a pte is 32 or 64 bits 4475 * in size, PG_RW and PG_M are among the least 4476 * significant 32 bits. 4477 */ 4478 if (!atomic_cmpset_int((u_int *)pte, oldpte, 4479 oldpte & ~(PG_RW | PG_M))) 4480 goto retry; 4481 if ((oldpte & PG_M) != 0) 4482 vm_page_dirty(m); 4483 pmap_invalidate_page(pmap, pv->pv_va); 4484 } 4485 PMAP_UNLOCK(pmap); 4486 } 4487 vm_page_flag_clear(m, PG_WRITEABLE); 4488 sched_unpin(); 4489 vm_page_unlock_queues(); 4490} 4491 4492/* 4493 * pmap_ts_referenced: 4494 * 4495 * Return a count of reference bits for a page, clearing those bits. 4496 * It is not necessary for every reference bit to be cleared, but it 4497 * is necessary that 0 only be returned when there are truly no 4498 * reference bits set. 4499 * 4500 * XXX: The exact number of bits to check and clear is a matter that 4501 * should be tested and standardized at some point in the future for 4502 * optimal aging of shared pages. 4503 */ 4504int 4505pmap_ts_referenced(vm_page_t m) 4506{ 4507 struct md_page *pvh; 4508 pv_entry_t pv, pvf, pvn; 4509 pmap_t pmap; 4510 pd_entry_t oldpde, *pde; 4511 pt_entry_t *pte; 4512 vm_offset_t va; 4513 int rtval = 0; 4514 4515 if (m->flags & PG_FICTITIOUS) 4516 return (rtval); 4517 sched_pin(); 4518 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 4519 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 4520 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_list, pvn) { 4521 va = pv->pv_va; 4522 pmap = PV_PMAP(pv); 4523 PMAP_LOCK(pmap); 4524 pde = pmap_pde(pmap, va); 4525 oldpde = *pde; 4526 if ((oldpde & PG_A) != 0) { 4527 if (pmap_demote_pde(pmap, pde, va)) { 4528 if ((oldpde & PG_W) == 0) { 4529 /* 4530 * Remove the mapping to a single page 4531 * so that a subsequent access may 4532 * repromote. Since the underlying 4533 * page table page is fully populated, 4534 * this removal never frees a page 4535 * table page. 4536 */ 4537 va += VM_PAGE_TO_PHYS(m) - (oldpde & 4538 PG_PS_FRAME); 4539 pmap_remove_page(pmap, va, NULL); 4540 rtval++; 4541 if (rtval > 4) { 4542 PMAP_UNLOCK(pmap); 4543 return (rtval); 4544 } 4545 } 4546 } 4547 } 4548 PMAP_UNLOCK(pmap); 4549 } 4550 if ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) { 4551 pvf = pv; 4552 do { 4553 pvn = TAILQ_NEXT(pv, pv_list); 4554 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list); 4555 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list); 4556 pmap = PV_PMAP(pv); 4557 PMAP_LOCK(pmap); 4558 pde = pmap_pde(pmap, pv->pv_va); 4559 KASSERT((*pde & PG_PS) == 0, ("pmap_ts_referenced:" 4560 " found a 4mpage in page %p's pv list", m)); 4561 pte = pmap_pte_quick(pmap, pv->pv_va); 4562 if ((*pte & PG_A) != 0) { 4563 atomic_clear_int((u_int *)pte, PG_A); 4564 pmap_invalidate_page(pmap, pv->pv_va); 4565 rtval++; 4566 if (rtval > 4) 4567 pvn = NULL; 4568 } 4569 PMAP_UNLOCK(pmap); 4570 } while ((pv = pvn) != NULL && pv != pvf); 4571 } 4572 sched_unpin(); 4573 return (rtval); 4574} 4575 4576/* 4577 * Clear the modify bits on the specified physical page. 4578 */ 4579void 4580pmap_clear_modify(vm_page_t m) 4581{ 4582 struct md_page *pvh; 4583 pv_entry_t next_pv, pv; 4584 pmap_t pmap; 4585 pd_entry_t oldpde, *pde; 4586 pt_entry_t oldpte, *pte; 4587 vm_offset_t va; 4588 4589 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 4590 ("pmap_clear_modify: page %p is not managed", m)); 4591 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 4592 KASSERT((m->oflags & VPO_BUSY) == 0, 4593 ("pmap_clear_modify: page %p is busy", m)); 4594 4595 /* 4596 * If the page is not PG_WRITEABLE, then no PTEs can have PG_M set. 4597 * If the object containing the page is locked and the page is not 4598 * VPO_BUSY, then PG_WRITEABLE cannot be concurrently set. 4599 */ 4600 if ((m->flags & PG_WRITEABLE) == 0) 4601 return; 4602 vm_page_lock_queues(); 4603 sched_pin(); 4604 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 4605 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_list, next_pv) { 4606 va = pv->pv_va; 4607 pmap = PV_PMAP(pv); 4608 PMAP_LOCK(pmap); 4609 pde = pmap_pde(pmap, va); 4610 oldpde = *pde; 4611 if ((oldpde & PG_RW) != 0) { 4612 if (pmap_demote_pde(pmap, pde, va)) { 4613 if ((oldpde & PG_W) == 0) { 4614 /* 4615 * Write protect the mapping to a 4616 * single page so that a subsequent 4617 * write access may repromote. 4618 */ 4619 va += VM_PAGE_TO_PHYS(m) - (oldpde & 4620 PG_PS_FRAME); 4621 pte = pmap_pte_quick(pmap, va); 4622 oldpte = *pte; 4623 if ((oldpte & PG_V) != 0) { 4624 /* 4625 * Regardless of whether a pte is 32 or 64 bits 4626 * in size, PG_RW and PG_M are among the least 4627 * significant 32 bits. 4628 */ 4629 while (!atomic_cmpset_int((u_int *)pte, 4630 oldpte, 4631 oldpte & ~(PG_M | PG_RW))) 4632 oldpte = *pte; 4633 vm_page_dirty(m); 4634 pmap_invalidate_page(pmap, va); 4635 } 4636 } 4637 } 4638 } 4639 PMAP_UNLOCK(pmap); 4640 } 4641 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 4642 pmap = PV_PMAP(pv); 4643 PMAP_LOCK(pmap); 4644 pde = pmap_pde(pmap, pv->pv_va); 4645 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_modify: found" 4646 " a 4mpage in page %p's pv list", m)); 4647 pte = pmap_pte_quick(pmap, pv->pv_va); 4648 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) { 4649 /* 4650 * Regardless of whether a pte is 32 or 64 bits 4651 * in size, PG_M is among the least significant 4652 * 32 bits. 4653 */ 4654 atomic_clear_int((u_int *)pte, PG_M); 4655 pmap_invalidate_page(pmap, pv->pv_va); 4656 } 4657 PMAP_UNLOCK(pmap); 4658 } 4659 sched_unpin(); 4660 vm_page_unlock_queues(); 4661} 4662 4663/* 4664 * pmap_clear_reference: 4665 * 4666 * Clear the reference bit on the specified physical page. 4667 */ 4668void 4669pmap_clear_reference(vm_page_t m) 4670{ 4671 struct md_page *pvh; 4672 pv_entry_t next_pv, pv; 4673 pmap_t pmap; 4674 pd_entry_t oldpde, *pde; 4675 pt_entry_t *pte; 4676 vm_offset_t va; 4677 4678 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 4679 ("pmap_clear_reference: page %p is not managed", m)); 4680 vm_page_lock_queues(); 4681 sched_pin(); 4682 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 4683 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_list, next_pv) { 4684 va = pv->pv_va; 4685 pmap = PV_PMAP(pv); 4686 PMAP_LOCK(pmap); 4687 pde = pmap_pde(pmap, va); 4688 oldpde = *pde; 4689 if ((oldpde & PG_A) != 0) { 4690 if (pmap_demote_pde(pmap, pde, va)) { 4691 /* 4692 * Remove the mapping to a single page so 4693 * that a subsequent access may repromote. 4694 * Since the underlying page table page is 4695 * fully populated, this removal never frees 4696 * a page table page. 4697 */ 4698 va += VM_PAGE_TO_PHYS(m) - (oldpde & 4699 PG_PS_FRAME); 4700 pmap_remove_page(pmap, va, NULL); 4701 } 4702 } 4703 PMAP_UNLOCK(pmap); 4704 } 4705 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 4706 pmap = PV_PMAP(pv); 4707 PMAP_LOCK(pmap); 4708 pde = pmap_pde(pmap, pv->pv_va); 4709 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_reference: found" 4710 " a 4mpage in page %p's pv list", m)); 4711 pte = pmap_pte_quick(pmap, pv->pv_va); 4712 if ((*pte & PG_A) != 0) { 4713 /* 4714 * Regardless of whether a pte is 32 or 64 bits 4715 * in size, PG_A is among the least significant 4716 * 32 bits. 4717 */ 4718 atomic_clear_int((u_int *)pte, PG_A); 4719 pmap_invalidate_page(pmap, pv->pv_va); 4720 } 4721 PMAP_UNLOCK(pmap); 4722 } 4723 sched_unpin(); 4724 vm_page_unlock_queues(); 4725} 4726 4727/* 4728 * Miscellaneous support routines follow 4729 */ 4730 4731/* Adjust the cache mode for a 4KB page mapped via a PTE. */ 4732static __inline void 4733pmap_pte_attr(pt_entry_t *pte, int cache_bits) 4734{ 4735 u_int opte, npte; 4736 4737 /* 4738 * The cache mode bits are all in the low 32-bits of the 4739 * PTE, so we can just spin on updating the low 32-bits. 4740 */ 4741 do { 4742 opte = *(u_int *)pte; 4743 npte = opte & ~PG_PTE_CACHE; 4744 npte |= cache_bits; 4745 } while (npte != opte && !atomic_cmpset_int((u_int *)pte, opte, npte)); 4746} 4747 4748/* Adjust the cache mode for a 2/4MB page mapped via a PDE. */ 4749static __inline void 4750pmap_pde_attr(pd_entry_t *pde, int cache_bits) 4751{ 4752 u_int opde, npde; 4753 4754 /* 4755 * The cache mode bits are all in the low 32-bits of the 4756 * PDE, so we can just spin on updating the low 32-bits. 4757 */ 4758 do { 4759 opde = *(u_int *)pde; 4760 npde = opde & ~PG_PDE_CACHE; 4761 npde |= cache_bits; 4762 } while (npde != opde && !atomic_cmpset_int((u_int *)pde, opde, npde)); 4763} 4764 4765/* 4766 * Map a set of physical memory pages into the kernel virtual 4767 * address space. Return a pointer to where it is mapped. This 4768 * routine is intended to be used for mapping device memory, 4769 * NOT real memory. 4770 */ 4771void * 4772pmap_mapdev_attr(vm_paddr_t pa, vm_size_t size, int mode) 4773{ 4774 vm_offset_t va, offset; 4775 vm_size_t tmpsize; 4776 4777 offset = pa & PAGE_MASK; 4778 size = roundup(offset + size, PAGE_SIZE); 4779 pa = pa & PG_FRAME; 4780 4781 if (pa < KERNLOAD && pa + size <= KERNLOAD) 4782 va = KERNBASE + pa; 4783 else 4784 va = kmem_alloc_nofault(kernel_map, size); 4785 if (!va) 4786 panic("pmap_mapdev: Couldn't alloc kernel virtual memory"); 4787 4788 for (tmpsize = 0; tmpsize < size; tmpsize += PAGE_SIZE) 4789 pmap_kenter_attr(va + tmpsize, pa + tmpsize, mode); 4790 pmap_invalidate_range(kernel_pmap, va, va + tmpsize); 4791 pmap_invalidate_cache_range(va, va + size); 4792 return ((void *)(va + offset)); 4793} 4794 4795void * 4796pmap_mapdev(vm_paddr_t pa, vm_size_t size) 4797{ 4798 4799 return (pmap_mapdev_attr(pa, size, PAT_UNCACHEABLE)); 4800} 4801 4802void * 4803pmap_mapbios(vm_paddr_t pa, vm_size_t size) 4804{ 4805 4806 return (pmap_mapdev_attr(pa, size, PAT_WRITE_BACK)); 4807} 4808 4809void 4810pmap_unmapdev(vm_offset_t va, vm_size_t size) 4811{ 4812 vm_offset_t base, offset, tmpva; 4813 4814 if (va >= KERNBASE && va + size <= KERNBASE + KERNLOAD) 4815 return; 4816 base = trunc_page(va); 4817 offset = va & PAGE_MASK; 4818 size = roundup(offset + size, PAGE_SIZE); 4819 for (tmpva = base; tmpva < (base + size); tmpva += PAGE_SIZE) 4820 pmap_kremove(tmpva); 4821 pmap_invalidate_range(kernel_pmap, va, tmpva); 4822 kmem_free(kernel_map, base, size); 4823} 4824 4825/* 4826 * Sets the memory attribute for the specified page. 4827 */ 4828void 4829pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma) 4830{ 4831 struct sysmaps *sysmaps; 4832 vm_offset_t sva, eva; 4833 4834 m->md.pat_mode = ma; 4835 if ((m->flags & PG_FICTITIOUS) != 0) 4836 return; 4837 4838 /* 4839 * If "m" is a normal page, flush it from the cache. 4840 * See pmap_invalidate_cache_range(). 4841 * 4842 * First, try to find an existing mapping of the page by sf 4843 * buffer. sf_buf_invalidate_cache() modifies mapping and 4844 * flushes the cache. 4845 */ 4846 if (sf_buf_invalidate_cache(m)) 4847 return; 4848 4849 /* 4850 * If page is not mapped by sf buffer, but CPU does not 4851 * support self snoop, map the page transient and do 4852 * invalidation. In the worst case, whole cache is flushed by 4853 * pmap_invalidate_cache_range(). 4854 */ 4855 if ((cpu_feature & (CPUID_SS|CPUID_CLFSH)) == CPUID_CLFSH) { 4856 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)]; 4857 mtx_lock(&sysmaps->lock); 4858 if (*sysmaps->CMAP2) 4859 panic("pmap_page_set_memattr: CMAP2 busy"); 4860 sched_pin(); 4861 *sysmaps->CMAP2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | 4862 PG_A | PG_M | pmap_cache_bits(m->md.pat_mode, 0); 4863 invlcaddr(sysmaps->CADDR2); 4864 sva = (vm_offset_t)sysmaps->CADDR2; 4865 eva = sva + PAGE_SIZE; 4866 } else 4867 sva = eva = 0; /* gcc */ 4868 pmap_invalidate_cache_range(sva, eva); 4869 if (sva != 0) { 4870 *sysmaps->CMAP2 = 0; 4871 sched_unpin(); 4872 mtx_unlock(&sysmaps->lock); 4873 } 4874} 4875 4876/* 4877 * Changes the specified virtual address range's memory type to that given by 4878 * the parameter "mode". The specified virtual address range must be 4879 * completely contained within either the kernel map. 4880 * 4881 * Returns zero if the change completed successfully, and either EINVAL or 4882 * ENOMEM if the change failed. Specifically, EINVAL is returned if some part 4883 * of the virtual address range was not mapped, and ENOMEM is returned if 4884 * there was insufficient memory available to complete the change. 4885 */ 4886int 4887pmap_change_attr(vm_offset_t va, vm_size_t size, int mode) 4888{ 4889 vm_offset_t base, offset, tmpva; 4890 pd_entry_t *pde; 4891 pt_entry_t *pte; 4892 int cache_bits_pte, cache_bits_pde; 4893 boolean_t changed; 4894 4895 base = trunc_page(va); 4896 offset = va & PAGE_MASK; 4897 size = roundup(offset + size, PAGE_SIZE); 4898 4899 /* 4900 * Only supported on kernel virtual addresses above the recursive map. 4901 */ 4902 if (base < VM_MIN_KERNEL_ADDRESS) 4903 return (EINVAL); 4904 4905 cache_bits_pde = pmap_cache_bits(mode, 1); 4906 cache_bits_pte = pmap_cache_bits(mode, 0); 4907 changed = FALSE; 4908 4909 /* 4910 * Pages that aren't mapped aren't supported. Also break down 4911 * 2/4MB pages into 4KB pages if required. 4912 */ 4913 PMAP_LOCK(kernel_pmap); 4914 for (tmpva = base; tmpva < base + size; ) { 4915 pde = pmap_pde(kernel_pmap, tmpva); 4916 if (*pde == 0) { 4917 PMAP_UNLOCK(kernel_pmap); 4918 return (EINVAL); 4919 } 4920 if (*pde & PG_PS) { 4921 /* 4922 * If the current 2/4MB page already has 4923 * the required memory type, then we need not 4924 * demote this page. Just increment tmpva to 4925 * the next 2/4MB page frame. 4926 */ 4927 if ((*pde & PG_PDE_CACHE) == cache_bits_pde) { 4928 tmpva = trunc_4mpage(tmpva) + NBPDR; 4929 continue; 4930 } 4931 4932 /* 4933 * If the current offset aligns with a 2/4MB 4934 * page frame and there is at least 2/4MB left 4935 * within the range, then we need not break 4936 * down this page into 4KB pages. 4937 */ 4938 if ((tmpva & PDRMASK) == 0 && 4939 tmpva + PDRMASK < base + size) { 4940 tmpva += NBPDR; 4941 continue; 4942 } 4943 if (!pmap_demote_pde(kernel_pmap, pde, tmpva)) { 4944 PMAP_UNLOCK(kernel_pmap); 4945 return (ENOMEM); 4946 } 4947 } 4948 pte = vtopte(tmpva); 4949 if (*pte == 0) { 4950 PMAP_UNLOCK(kernel_pmap); 4951 return (EINVAL); 4952 } 4953 tmpva += PAGE_SIZE; 4954 } 4955 PMAP_UNLOCK(kernel_pmap); 4956 4957 /* 4958 * Ok, all the pages exist, so run through them updating their 4959 * cache mode if required. 4960 */ 4961 for (tmpva = base; tmpva < base + size; ) { 4962 pde = pmap_pde(kernel_pmap, tmpva); 4963 if (*pde & PG_PS) { 4964 if ((*pde & PG_PDE_CACHE) != cache_bits_pde) { 4965 pmap_pde_attr(pde, cache_bits_pde); 4966 changed = TRUE; 4967 } 4968 tmpva = trunc_4mpage(tmpva) + NBPDR; 4969 } else { 4970 pte = vtopte(tmpva); 4971 if ((*pte & PG_PTE_CACHE) != cache_bits_pte) { 4972 pmap_pte_attr(pte, cache_bits_pte); 4973 changed = TRUE; 4974 } 4975 tmpva += PAGE_SIZE; 4976 } 4977 } 4978 4979 /* 4980 * Flush CPU caches to make sure any data isn't cached that 4981 * shouldn't be, etc. 4982 */ 4983 if (changed) { 4984 pmap_invalidate_range(kernel_pmap, base, tmpva); 4985 pmap_invalidate_cache_range(base, tmpva); 4986 } 4987 return (0); 4988} 4989 4990/* 4991 * perform the pmap work for mincore 4992 */ 4993int 4994pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa) 4995{ 4996 pd_entry_t *pdep; 4997 pt_entry_t *ptep, pte; 4998 vm_paddr_t pa; 4999 int val; 5000 5001 PMAP_LOCK(pmap); 5002retry: 5003 pdep = pmap_pde(pmap, addr); 5004 if (*pdep != 0) { 5005 if (*pdep & PG_PS) { 5006 pte = *pdep; 5007 /* Compute the physical address of the 4KB page. */ 5008 pa = ((*pdep & PG_PS_FRAME) | (addr & PDRMASK)) & 5009 PG_FRAME; 5010 val = MINCORE_SUPER; 5011 } else { 5012 ptep = pmap_pte(pmap, addr); 5013 pte = *ptep; 5014 pmap_pte_release(ptep); 5015 pa = pte & PG_FRAME; 5016 val = 0; 5017 } 5018 } else { 5019 pte = 0; 5020 pa = 0; 5021 val = 0; 5022 } 5023 if ((pte & PG_V) != 0) { 5024 val |= MINCORE_INCORE; 5025 if ((pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) 5026 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER; 5027 if ((pte & PG_A) != 0) 5028 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER; 5029 } 5030 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) != 5031 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) && 5032 (pte & (PG_MANAGED | PG_V)) == (PG_MANAGED | PG_V)) { 5033 /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */ 5034 if (vm_page_pa_tryrelock(pmap, pa, locked_pa)) 5035 goto retry; 5036 } else 5037 PA_UNLOCK_COND(*locked_pa); 5038 PMAP_UNLOCK(pmap); 5039 return (val); 5040} 5041 5042void 5043pmap_activate(struct thread *td) 5044{ 5045 pmap_t pmap, oldpmap; 5046 u_int32_t cr3; 5047 5048 critical_enter(); 5049 pmap = vmspace_pmap(td->td_proc->p_vmspace); 5050 oldpmap = PCPU_GET(curpmap); 5051#if defined(SMP) 5052 atomic_clear_int(&oldpmap->pm_active, PCPU_GET(cpumask)); 5053 atomic_set_int(&pmap->pm_active, PCPU_GET(cpumask)); 5054#else 5055 oldpmap->pm_active &= ~1; 5056 pmap->pm_active |= 1; 5057#endif 5058#ifdef PAE 5059 cr3 = vtophys(pmap->pm_pdpt); 5060#else 5061 cr3 = vtophys(pmap->pm_pdir); 5062#endif 5063 /* 5064 * pmap_activate is for the current thread on the current cpu 5065 */ 5066 td->td_pcb->pcb_cr3 = cr3; 5067 load_cr3(cr3); 5068 PCPU_SET(curpmap, pmap); 5069 critical_exit(); 5070} 5071 5072void 5073pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz) 5074{ 5075} 5076 5077/* 5078 * Increase the starting virtual address of the given mapping if a 5079 * different alignment might result in more superpage mappings. 5080 */ 5081void 5082pmap_align_superpage(vm_object_t object, vm_ooffset_t offset, 5083 vm_offset_t *addr, vm_size_t size) 5084{ 5085 vm_offset_t superpage_offset; 5086 5087 if (size < NBPDR) 5088 return; 5089 if (object != NULL && (object->flags & OBJ_COLORED) != 0) 5090 offset += ptoa(object->pg_color); 5091 superpage_offset = offset & PDRMASK; 5092 if (size - ((NBPDR - superpage_offset) & PDRMASK) < NBPDR || 5093 (*addr & PDRMASK) == superpage_offset) 5094 return; 5095 if ((*addr & PDRMASK) < superpage_offset) 5096 *addr = (*addr & ~PDRMASK) + superpage_offset; 5097 else 5098 *addr = ((*addr + PDRMASK) & ~PDRMASK) + superpage_offset; 5099} 5100 5101 5102#if defined(PMAP_DEBUG) 5103pmap_pid_dump(int pid) 5104{ 5105 pmap_t pmap; 5106 struct proc *p; 5107 int npte = 0; 5108 int index; 5109 5110 sx_slock(&allproc_lock); 5111 FOREACH_PROC_IN_SYSTEM(p) { 5112 if (p->p_pid != pid) 5113 continue; 5114 5115 if (p->p_vmspace) { 5116 int i,j; 5117 index = 0; 5118 pmap = vmspace_pmap(p->p_vmspace); 5119 for (i = 0; i < NPDEPTD; i++) { 5120 pd_entry_t *pde; 5121 pt_entry_t *pte; 5122 vm_offset_t base = i << PDRSHIFT; 5123 5124 pde = &pmap->pm_pdir[i]; 5125 if (pde && pmap_pde_v(pde)) { 5126 for (j = 0; j < NPTEPG; j++) { 5127 vm_offset_t va = base + (j << PAGE_SHIFT); 5128 if (va >= (vm_offset_t) VM_MIN_KERNEL_ADDRESS) { 5129 if (index) { 5130 index = 0; 5131 printf("\n"); 5132 } 5133 sx_sunlock(&allproc_lock); 5134 return (npte); 5135 } 5136 pte = pmap_pte(pmap, va); 5137 if (pte && pmap_pte_v(pte)) { 5138 pt_entry_t pa; 5139 vm_page_t m; 5140 pa = *pte; 5141 m = PHYS_TO_VM_PAGE(pa & PG_FRAME); 5142 printf("va: 0x%x, pt: 0x%x, h: %d, w: %d, f: 0x%x", 5143 va, pa, m->hold_count, m->wire_count, m->flags); 5144 npte++; 5145 index++; 5146 if (index >= 2) { 5147 index = 0; 5148 printf("\n"); 5149 } else { 5150 printf(" "); 5151 } 5152 } 5153 } 5154 } 5155 } 5156 } 5157 } 5158 sx_sunlock(&allproc_lock); 5159 return (npte); 5160} 5161#endif 5162 5163#if defined(DEBUG) 5164 5165static void pads(pmap_t pm); 5166void pmap_pvdump(vm_offset_t pa); 5167 5168/* print address space of pmap*/ 5169static void 5170pads(pmap_t pm) 5171{ 5172 int i, j; 5173 vm_paddr_t va; 5174 pt_entry_t *ptep; 5175 5176 if (pm == kernel_pmap) 5177 return; 5178 for (i = 0; i < NPDEPTD; i++) 5179 if (pm->pm_pdir[i]) 5180 for (j = 0; j < NPTEPG; j++) { 5181 va = (i << PDRSHIFT) + (j << PAGE_SHIFT); 5182 if (pm == kernel_pmap && va < KERNBASE) 5183 continue; 5184 if (pm != kernel_pmap && va > UPT_MAX_ADDRESS) 5185 continue; 5186 ptep = pmap_pte(pm, va); 5187 if (pmap_pte_v(ptep)) 5188 printf("%x:%x ", va, *ptep); 5189 }; 5190 5191} 5192 5193void 5194pmap_pvdump(vm_paddr_t pa) 5195{ 5196 pv_entry_t pv; 5197 pmap_t pmap; 5198 vm_page_t m; 5199 5200 printf("pa %x", pa); 5201 m = PHYS_TO_VM_PAGE(pa); 5202 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 5203 pmap = PV_PMAP(pv); 5204 printf(" -> pmap %p, va %x", (void *)pmap, pv->pv_va); 5205 pads(pmap); 5206 } 5207 printf(" "); 5208} 5209#endif 5210