pmap.c revision 207702
1/*- 2 * Copyright (c) 1991 Regents of the University of California. 3 * All rights reserved. 4 * Copyright (c) 1994 John S. Dyson 5 * All rights reserved. 6 * Copyright (c) 1994 David Greenman 7 * All rights reserved. 8 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu> 9 * All rights reserved. 10 * 11 * This code is derived from software contributed to Berkeley by 12 * the Systems Programming Group of the University of Utah Computer 13 * Science Department and William Jolitz of UUNET Technologies Inc. 14 * 15 * Redistribution and use in source and binary forms, with or without 16 * modification, are permitted provided that the following conditions 17 * are met: 18 * 1. Redistributions of source code must retain the above copyright 19 * notice, this list of conditions and the following disclaimer. 20 * 2. Redistributions in binary form must reproduce the above copyright 21 * notice, this list of conditions and the following disclaimer in the 22 * documentation and/or other materials provided with the distribution. 23 * 3. All advertising materials mentioning features or use of this software 24 * must display the following acknowledgement: 25 * This product includes software developed by the University of 26 * California, Berkeley and its contributors. 27 * 4. Neither the name of the University nor the names of its contributors 28 * may be used to endorse or promote products derived from this software 29 * without specific prior written permission. 30 * 31 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 32 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 33 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 34 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 35 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 36 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 37 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 38 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 39 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 40 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 41 * SUCH DAMAGE. 42 * 43 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91 44 */ 45/*- 46 * Copyright (c) 2003 Networks Associates Technology, Inc. 47 * All rights reserved. 48 * 49 * This software was developed for the FreeBSD Project by Jake Burkholder, 50 * Safeport Network Services, and Network Associates Laboratories, the 51 * Security Research Division of Network Associates, Inc. under 52 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA 53 * CHATS research program. 54 * 55 * Redistribution and use in source and binary forms, with or without 56 * modification, are permitted provided that the following conditions 57 * are met: 58 * 1. Redistributions of source code must retain the above copyright 59 * notice, this list of conditions and the following disclaimer. 60 * 2. Redistributions in binary form must reproduce the above copyright 61 * notice, this list of conditions and the following disclaimer in the 62 * documentation and/or other materials provided with the distribution. 63 * 64 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 65 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 66 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 67 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 68 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 69 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 70 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 71 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 72 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 73 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 74 * SUCH DAMAGE. 75 */ 76 77#include <sys/cdefs.h> 78__FBSDID("$FreeBSD: head/sys/i386/i386/pmap.c 207702 2010-05-06 16:39:43Z alc $"); 79 80/* 81 * Manages physical address maps. 82 * 83 * In addition to hardware address maps, this 84 * module is called upon to provide software-use-only 85 * maps which may or may not be stored in the same 86 * form as hardware maps. These pseudo-maps are 87 * used to store intermediate results from copy 88 * operations to and from address spaces. 89 * 90 * Since the information managed by this module is 91 * also stored by the logical address mapping module, 92 * this module may throw away valid virtual-to-physical 93 * mappings at almost any time. However, invalidations 94 * of virtual-to-physical mappings must be done as 95 * requested. 96 * 97 * In order to cope with hardware architectures which 98 * make virtual-to-physical map invalidates expensive, 99 * this module may delay invalidate or reduced protection 100 * operations until such time as they are actually 101 * necessary. This module is given full information as 102 * to which processors are currently using which maps, 103 * and to when physical maps must be made correct. 104 */ 105 106#include "opt_cpu.h" 107#include "opt_pmap.h" 108#include "opt_msgbuf.h" 109#include "opt_smp.h" 110#include "opt_xbox.h" 111 112#include <sys/param.h> 113#include <sys/systm.h> 114#include <sys/kernel.h> 115#include <sys/ktr.h> 116#include <sys/lock.h> 117#include <sys/malloc.h> 118#include <sys/mman.h> 119#include <sys/msgbuf.h> 120#include <sys/mutex.h> 121#include <sys/proc.h> 122#include <sys/sf_buf.h> 123#include <sys/sx.h> 124#include <sys/vmmeter.h> 125#include <sys/sched.h> 126#include <sys/sysctl.h> 127#ifdef SMP 128#include <sys/smp.h> 129#endif 130 131#include <vm/vm.h> 132#include <vm/vm_param.h> 133#include <vm/vm_kern.h> 134#include <vm/vm_page.h> 135#include <vm/vm_map.h> 136#include <vm/vm_object.h> 137#include <vm/vm_extern.h> 138#include <vm/vm_pageout.h> 139#include <vm/vm_pager.h> 140#include <vm/vm_reserv.h> 141#include <vm/uma.h> 142 143#include <machine/cpu.h> 144#include <machine/cputypes.h> 145#include <machine/md_var.h> 146#include <machine/pcb.h> 147#include <machine/specialreg.h> 148#ifdef SMP 149#include <machine/smp.h> 150#endif 151 152#ifdef XBOX 153#include <machine/xbox.h> 154#endif 155 156#if !defined(CPU_DISABLE_SSE) && defined(I686_CPU) 157#define CPU_ENABLE_SSE 158#endif 159 160#ifndef PMAP_SHPGPERPROC 161#define PMAP_SHPGPERPROC 200 162#endif 163 164#if !defined(DIAGNOSTIC) 165#ifdef __GNUC_GNU_INLINE__ 166#define PMAP_INLINE __attribute__((__gnu_inline__)) inline 167#else 168#define PMAP_INLINE extern inline 169#endif 170#else 171#define PMAP_INLINE 172#endif 173 174#define PV_STATS 175#ifdef PV_STATS 176#define PV_STAT(x) do { x ; } while (0) 177#else 178#define PV_STAT(x) do { } while (0) 179#endif 180 181#define pa_index(pa) ((pa) >> PDRSHIFT) 182#define pa_to_pvh(pa) (&pv_table[pa_index(pa)]) 183 184/* 185 * Get PDEs and PTEs for user/kernel address space 186 */ 187#define pmap_pde(m, v) (&((m)->pm_pdir[(vm_offset_t)(v) >> PDRSHIFT])) 188#define pdir_pde(m, v) (m[(vm_offset_t)(v) >> PDRSHIFT]) 189 190#define pmap_pde_v(pte) ((*(int *)pte & PG_V) != 0) 191#define pmap_pte_w(pte) ((*(int *)pte & PG_W) != 0) 192#define pmap_pte_m(pte) ((*(int *)pte & PG_M) != 0) 193#define pmap_pte_u(pte) ((*(int *)pte & PG_A) != 0) 194#define pmap_pte_v(pte) ((*(int *)pte & PG_V) != 0) 195 196#define pmap_pte_set_w(pte, v) ((v) ? atomic_set_int((u_int *)(pte), PG_W) : \ 197 atomic_clear_int((u_int *)(pte), PG_W)) 198#define pmap_pte_set_prot(pte, v) ((*(int *)pte &= ~PG_PROT), (*(int *)pte |= (v))) 199 200struct pmap kernel_pmap_store; 201LIST_HEAD(pmaplist, pmap); 202static struct pmaplist allpmaps; 203static struct mtx allpmaps_lock; 204 205vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */ 206vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */ 207int pgeflag = 0; /* PG_G or-in */ 208int pseflag = 0; /* PG_PS or-in */ 209 210static int nkpt = NKPT; 211vm_offset_t kernel_vm_end = KERNBASE + NKPT * NBPDR; 212extern u_int32_t KERNend; 213extern u_int32_t KPTphys; 214 215#ifdef PAE 216pt_entry_t pg_nx; 217static uma_zone_t pdptzone; 218#endif 219 220static int pat_works = 0; /* Is page attribute table sane? */ 221 222SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD, 0, "VM/pmap parameters"); 223 224static int pg_ps_enabled = 1; 225SYSCTL_INT(_vm_pmap, OID_AUTO, pg_ps_enabled, CTLFLAG_RDTUN, &pg_ps_enabled, 0, 226 "Are large page mappings enabled?"); 227 228/* 229 * Data for the pv entry allocation mechanism 230 */ 231static int pv_entry_count = 0, pv_entry_max = 0, pv_entry_high_water = 0; 232static struct md_page *pv_table; 233static int shpgperproc = PMAP_SHPGPERPROC; 234 235struct pv_chunk *pv_chunkbase; /* KVA block for pv_chunks */ 236int pv_maxchunks; /* How many chunks we have KVA for */ 237vm_offset_t pv_vafree; /* freelist stored in the PTE */ 238 239/* 240 * All those kernel PT submaps that BSD is so fond of 241 */ 242struct sysmaps { 243 struct mtx lock; 244 pt_entry_t *CMAP1; 245 pt_entry_t *CMAP2; 246 caddr_t CADDR1; 247 caddr_t CADDR2; 248}; 249static struct sysmaps sysmaps_pcpu[MAXCPU]; 250pt_entry_t *CMAP1 = 0, *KPTmap; 251static pt_entry_t *CMAP3; 252static pd_entry_t *KPTD; 253caddr_t CADDR1 = 0, ptvmmap = 0; 254static caddr_t CADDR3; 255struct msgbuf *msgbufp = 0; 256 257/* 258 * Crashdump maps. 259 */ 260static caddr_t crashdumpmap; 261 262static pt_entry_t *PMAP1 = 0, *PMAP2; 263static pt_entry_t *PADDR1 = 0, *PADDR2; 264#ifdef SMP 265static int PMAP1cpu; 266static int PMAP1changedcpu; 267SYSCTL_INT(_debug, OID_AUTO, PMAP1changedcpu, CTLFLAG_RD, 268 &PMAP1changedcpu, 0, 269 "Number of times pmap_pte_quick changed CPU with same PMAP1"); 270#endif 271static int PMAP1changed; 272SYSCTL_INT(_debug, OID_AUTO, PMAP1changed, CTLFLAG_RD, 273 &PMAP1changed, 0, 274 "Number of times pmap_pte_quick changed PMAP1"); 275static int PMAP1unchanged; 276SYSCTL_INT(_debug, OID_AUTO, PMAP1unchanged, CTLFLAG_RD, 277 &PMAP1unchanged, 0, 278 "Number of times pmap_pte_quick didn't change PMAP1"); 279static struct mtx PMAP2mutex; 280 281static void free_pv_entry(pmap_t pmap, pv_entry_t pv); 282static pv_entry_t get_pv_entry(pmap_t locked_pmap, int try); 283static void pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa); 284static boolean_t pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa); 285static void pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa); 286static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va); 287static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, 288 vm_offset_t va); 289static int pmap_pvh_wired_mappings(struct md_page *pvh, int count); 290 291static boolean_t pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va); 292static boolean_t pmap_enter_pde(pmap_t pmap, vm_offset_t va, vm_page_t m, 293 vm_prot_t prot); 294static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, 295 vm_page_t m, vm_prot_t prot, vm_page_t mpte); 296static void pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte); 297static void pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte); 298static boolean_t pmap_is_modified_pvh(struct md_page *pvh); 299static boolean_t pmap_is_referenced_pvh(struct md_page *pvh); 300static void pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode); 301static void pmap_kenter_pde(vm_offset_t va, pd_entry_t newpde); 302static vm_page_t pmap_lookup_pt_page(pmap_t pmap, vm_offset_t va); 303static void pmap_pde_attr(pd_entry_t *pde, int cache_bits); 304static void pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va); 305static boolean_t pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva, 306 vm_prot_t prot); 307static void pmap_pte_attr(pt_entry_t *pte, int cache_bits); 308static void pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva, 309 vm_page_t *free); 310static int pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t sva, 311 vm_page_t *free); 312static void pmap_remove_pt_page(pmap_t pmap, vm_page_t mpte); 313static void pmap_remove_page(struct pmap *pmap, vm_offset_t va, 314 vm_page_t *free); 315static void pmap_remove_entry(struct pmap *pmap, vm_page_t m, 316 vm_offset_t va); 317static void pmap_insert_entry(pmap_t pmap, vm_offset_t va, vm_page_t m); 318static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, 319 vm_page_t m); 320static void pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, 321 pd_entry_t newpde); 322static void pmap_update_pde_invalidate(vm_offset_t va, pd_entry_t newpde); 323 324static vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va, int flags); 325 326static vm_page_t _pmap_allocpte(pmap_t pmap, unsigned ptepindex, int flags); 327static int _pmap_unwire_pte_hold(pmap_t pmap, vm_page_t m, vm_page_t *free); 328static pt_entry_t *pmap_pte_quick(pmap_t pmap, vm_offset_t va); 329static void pmap_pte_release(pt_entry_t *pte); 330static int pmap_unuse_pt(pmap_t, vm_offset_t, vm_page_t *); 331#ifdef PAE 332static void *pmap_pdpt_allocf(uma_zone_t zone, int bytes, u_int8_t *flags, int wait); 333#endif 334static void pmap_set_pg(void); 335 336CTASSERT(1 << PDESHIFT == sizeof(pd_entry_t)); 337CTASSERT(1 << PTESHIFT == sizeof(pt_entry_t)); 338 339/* 340 * If you get an error here, then you set KVA_PAGES wrong! See the 341 * description of KVA_PAGES in sys/i386/include/pmap.h. It must be 342 * multiple of 4 for a normal kernel, or a multiple of 8 for a PAE. 343 */ 344CTASSERT(KERNBASE % (1 << 24) == 0); 345 346/* 347 * Bootstrap the system enough to run with virtual memory. 348 * 349 * On the i386 this is called after mapping has already been enabled 350 * and just syncs the pmap module with what has already been done. 351 * [We can't call it easily with mapping off since the kernel is not 352 * mapped with PA == VA, hence we would have to relocate every address 353 * from the linked base (virtual) address "KERNBASE" to the actual 354 * (physical) address starting relative to 0] 355 */ 356void 357pmap_bootstrap(vm_paddr_t firstaddr) 358{ 359 vm_offset_t va; 360 pt_entry_t *pte, *unused; 361 struct sysmaps *sysmaps; 362 int i; 363 364 /* 365 * XXX The calculation of virtual_avail is wrong. It's NKPT*PAGE_SIZE too 366 * large. It should instead be correctly calculated in locore.s and 367 * not based on 'first' (which is a physical address, not a virtual 368 * address, for the start of unused physical memory). The kernel 369 * page tables are NOT double mapped and thus should not be included 370 * in this calculation. 371 */ 372 virtual_avail = (vm_offset_t) KERNBASE + firstaddr; 373 374 virtual_end = VM_MAX_KERNEL_ADDRESS; 375 376 /* 377 * Initialize the kernel pmap (which is statically allocated). 378 */ 379 PMAP_LOCK_INIT(kernel_pmap); 380 kernel_pmap->pm_pdir = (pd_entry_t *) (KERNBASE + (u_int)IdlePTD); 381#ifdef PAE 382 kernel_pmap->pm_pdpt = (pdpt_entry_t *) (KERNBASE + (u_int)IdlePDPT); 383#endif 384 kernel_pmap->pm_root = NULL; 385 kernel_pmap->pm_active = -1; /* don't allow deactivation */ 386 TAILQ_INIT(&kernel_pmap->pm_pvchunk); 387 LIST_INIT(&allpmaps); 388 389 /* 390 * Request a spin mutex so that changes to allpmaps cannot be 391 * preempted by smp_rendezvous_cpus(). Otherwise, 392 * pmap_update_pde_kernel() could access allpmaps while it is 393 * being changed. 394 */ 395 mtx_init(&allpmaps_lock, "allpmaps", NULL, MTX_SPIN); 396 mtx_lock_spin(&allpmaps_lock); 397 LIST_INSERT_HEAD(&allpmaps, kernel_pmap, pm_list); 398 mtx_unlock_spin(&allpmaps_lock); 399 400 /* 401 * Reserve some special page table entries/VA space for temporary 402 * mapping of pages. 403 */ 404#define SYSMAP(c, p, v, n) \ 405 v = (c)va; va += ((n)*PAGE_SIZE); p = pte; pte += (n); 406 407 va = virtual_avail; 408 pte = vtopte(va); 409 410 /* 411 * CMAP1/CMAP2 are used for zeroing and copying pages. 412 * CMAP3 is used for the idle process page zeroing. 413 */ 414 for (i = 0; i < MAXCPU; i++) { 415 sysmaps = &sysmaps_pcpu[i]; 416 mtx_init(&sysmaps->lock, "SYSMAPS", NULL, MTX_DEF); 417 SYSMAP(caddr_t, sysmaps->CMAP1, sysmaps->CADDR1, 1) 418 SYSMAP(caddr_t, sysmaps->CMAP2, sysmaps->CADDR2, 1) 419 } 420 SYSMAP(caddr_t, CMAP1, CADDR1, 1) 421 SYSMAP(caddr_t, CMAP3, CADDR3, 1) 422 423 /* 424 * Crashdump maps. 425 */ 426 SYSMAP(caddr_t, unused, crashdumpmap, MAXDUMPPGS) 427 428 /* 429 * ptvmmap is used for reading arbitrary physical pages via /dev/mem. 430 */ 431 SYSMAP(caddr_t, unused, ptvmmap, 1) 432 433 /* 434 * msgbufp is used to map the system message buffer. 435 */ 436 SYSMAP(struct msgbuf *, unused, msgbufp, atop(round_page(MSGBUF_SIZE))) 437 438 /* 439 * KPTmap is used by pmap_kextract(). 440 */ 441 SYSMAP(pt_entry_t *, KPTD, KPTmap, KVA_PAGES) 442 443 for (i = 0; i < NKPT; i++) 444 KPTD[i] = (KPTphys + (i << PAGE_SHIFT)) | pgeflag | PG_RW | PG_V; 445 446 /* 447 * Adjust the start of the KPTD and KPTmap so that the implementation 448 * of pmap_kextract() and pmap_growkernel() can be made simpler. 449 */ 450 KPTD -= KPTDI; 451 KPTmap -= i386_btop(KPTDI << PDRSHIFT); 452 453 /* 454 * ptemap is used for pmap_pte_quick 455 */ 456 SYSMAP(pt_entry_t *, PMAP1, PADDR1, 1) 457 SYSMAP(pt_entry_t *, PMAP2, PADDR2, 1) 458 459 mtx_init(&PMAP2mutex, "PMAP2", NULL, MTX_DEF); 460 461 virtual_avail = va; 462 463 /* 464 * Leave in place an identity mapping (virt == phys) for the low 1 MB 465 * physical memory region that is used by the ACPI wakeup code. This 466 * mapping must not have PG_G set. 467 */ 468#ifdef XBOX 469 /* FIXME: This is gross, but needed for the XBOX. Since we are in such 470 * an early stadium, we cannot yet neatly map video memory ... :-( 471 * Better fixes are very welcome! */ 472 if (!arch_i386_is_xbox) 473#endif 474 for (i = 1; i < NKPT; i++) 475 PTD[i] = 0; 476 477 /* Initialize the PAT MSR if present. */ 478 pmap_init_pat(); 479 480 /* Turn on PG_G on kernel page(s) */ 481 pmap_set_pg(); 482} 483 484/* 485 * Setup the PAT MSR. 486 */ 487void 488pmap_init_pat(void) 489{ 490 uint64_t pat_msr; 491 char *sysenv; 492 static int pat_tested = 0; 493 494 /* Bail if this CPU doesn't implement PAT. */ 495 if (!(cpu_feature & CPUID_PAT)) 496 return; 497 498 /* 499 * Due to some Intel errata, we can only safely use the lower 4 500 * PAT entries. 501 * 502 * Intel Pentium III Processor Specification Update 503 * Errata E.27 (Upper Four PAT Entries Not Usable With Mode B 504 * or Mode C Paging) 505 * 506 * Intel Pentium IV Processor Specification Update 507 * Errata N46 (PAT Index MSB May Be Calculated Incorrectly) 508 * 509 * Some Apple Macs based on nVidia chipsets cannot enter ACPI mode 510 * via SMI# when we use upper 4 PAT entries for unknown reason. 511 */ 512 if (!pat_tested) { 513 if (cpu_vendor_id != CPU_VENDOR_INTEL || 514 (CPUID_TO_FAMILY(cpu_id) == 6 && 515 CPUID_TO_MODEL(cpu_id) >= 0xe)) { 516 pat_works = 1; 517 sysenv = getenv("smbios.system.product"); 518 if (sysenv != NULL) { 519 if (strncmp(sysenv, "MacBook5,1", 10) == 0 || 520 strncmp(sysenv, "MacBookPro5,5", 13) == 0 || 521 strncmp(sysenv, "Macmini3,1", 10) == 0) 522 pat_works = 0; 523 freeenv(sysenv); 524 } 525 } 526 pat_tested = 1; 527 } 528 529 /* Initialize default PAT entries. */ 530 pat_msr = PAT_VALUE(0, PAT_WRITE_BACK) | 531 PAT_VALUE(1, PAT_WRITE_THROUGH) | 532 PAT_VALUE(2, PAT_UNCACHED) | 533 PAT_VALUE(3, PAT_UNCACHEABLE) | 534 PAT_VALUE(4, PAT_WRITE_BACK) | 535 PAT_VALUE(5, PAT_WRITE_THROUGH) | 536 PAT_VALUE(6, PAT_UNCACHED) | 537 PAT_VALUE(7, PAT_UNCACHEABLE); 538 539 if (pat_works) { 540 /* 541 * Leave the indices 0-3 at the default of WB, WT, UC-, and UC. 542 * Program 4 and 5 as WP and WC. 543 * Leave 6 and 7 as UC- and UC. 544 */ 545 pat_msr &= ~(PAT_MASK(4) | PAT_MASK(5)); 546 pat_msr |= PAT_VALUE(4, PAT_WRITE_PROTECTED) | 547 PAT_VALUE(5, PAT_WRITE_COMBINING); 548 } else { 549 /* 550 * Just replace PAT Index 2 with WC instead of UC-. 551 */ 552 pat_msr &= ~PAT_MASK(2); 553 pat_msr |= PAT_VALUE(2, PAT_WRITE_COMBINING); 554 } 555 wrmsr(MSR_PAT, pat_msr); 556} 557 558/* 559 * Set PG_G on kernel pages. Only the BSP calls this when SMP is turned on. 560 */ 561static void 562pmap_set_pg(void) 563{ 564 pt_entry_t *pte; 565 vm_offset_t va, endva; 566 567 if (pgeflag == 0) 568 return; 569 570 endva = KERNBASE + KERNend; 571 572 if (pseflag) { 573 va = KERNBASE + KERNLOAD; 574 while (va < endva) { 575 pdir_pde(PTD, va) |= pgeflag; 576 invltlb(); /* Play it safe, invltlb() every time */ 577 va += NBPDR; 578 } 579 } else { 580 va = (vm_offset_t)btext; 581 while (va < endva) { 582 pte = vtopte(va); 583 if (*pte) 584 *pte |= pgeflag; 585 invltlb(); /* Play it safe, invltlb() every time */ 586 va += PAGE_SIZE; 587 } 588 } 589} 590 591/* 592 * Initialize a vm_page's machine-dependent fields. 593 */ 594void 595pmap_page_init(vm_page_t m) 596{ 597 598 TAILQ_INIT(&m->md.pv_list); 599 m->md.pat_mode = PAT_WRITE_BACK; 600} 601 602#ifdef PAE 603static void * 604pmap_pdpt_allocf(uma_zone_t zone, int bytes, u_int8_t *flags, int wait) 605{ 606 607 /* Inform UMA that this allocator uses kernel_map/object. */ 608 *flags = UMA_SLAB_KERNEL; 609 return ((void *)kmem_alloc_contig(kernel_map, bytes, wait, 0x0ULL, 610 0xffffffffULL, 1, 0, VM_MEMATTR_DEFAULT)); 611} 612#endif 613 614/* 615 * ABuse the pte nodes for unmapped kva to thread a kva freelist through. 616 * Requirements: 617 * - Must deal with pages in order to ensure that none of the PG_* bits 618 * are ever set, PG_V in particular. 619 * - Assumes we can write to ptes without pte_store() atomic ops, even 620 * on PAE systems. This should be ok. 621 * - Assumes nothing will ever test these addresses for 0 to indicate 622 * no mapping instead of correctly checking PG_V. 623 * - Assumes a vm_offset_t will fit in a pte (true for i386). 624 * Because PG_V is never set, there can be no mappings to invalidate. 625 */ 626static vm_offset_t 627pmap_ptelist_alloc(vm_offset_t *head) 628{ 629 pt_entry_t *pte; 630 vm_offset_t va; 631 632 va = *head; 633 if (va == 0) 634 return (va); /* Out of memory */ 635 pte = vtopte(va); 636 *head = *pte; 637 if (*head & PG_V) 638 panic("pmap_ptelist_alloc: va with PG_V set!"); 639 *pte = 0; 640 return (va); 641} 642 643static void 644pmap_ptelist_free(vm_offset_t *head, vm_offset_t va) 645{ 646 pt_entry_t *pte; 647 648 if (va & PG_V) 649 panic("pmap_ptelist_free: freeing va with PG_V set!"); 650 pte = vtopte(va); 651 *pte = *head; /* virtual! PG_V is 0 though */ 652 *head = va; 653} 654 655static void 656pmap_ptelist_init(vm_offset_t *head, void *base, int npages) 657{ 658 int i; 659 vm_offset_t va; 660 661 *head = 0; 662 for (i = npages - 1; i >= 0; i--) { 663 va = (vm_offset_t)base + i * PAGE_SIZE; 664 pmap_ptelist_free(head, va); 665 } 666} 667 668 669/* 670 * Initialize the pmap module. 671 * Called by vm_init, to initialize any structures that the pmap 672 * system needs to map virtual memory. 673 */ 674void 675pmap_init(void) 676{ 677 vm_page_t mpte; 678 vm_size_t s; 679 int i, pv_npg; 680 681 /* 682 * Initialize the vm page array entries for the kernel pmap's 683 * page table pages. 684 */ 685 for (i = 0; i < NKPT; i++) { 686 mpte = PHYS_TO_VM_PAGE(KPTphys + (i << PAGE_SHIFT)); 687 KASSERT(mpte >= vm_page_array && 688 mpte < &vm_page_array[vm_page_array_size], 689 ("pmap_init: page table page is out of range")); 690 mpte->pindex = i + KPTDI; 691 mpte->phys_addr = KPTphys + (i << PAGE_SHIFT); 692 } 693 694 /* 695 * Initialize the address space (zone) for the pv entries. Set a 696 * high water mark so that the system can recover from excessive 697 * numbers of pv entries. 698 */ 699 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc); 700 pv_entry_max = shpgperproc * maxproc + cnt.v_page_count; 701 TUNABLE_INT_FETCH("vm.pmap.pv_entries", &pv_entry_max); 702 pv_entry_max = roundup(pv_entry_max, _NPCPV); 703 pv_entry_high_water = 9 * (pv_entry_max / 10); 704 705 /* 706 * If the kernel is running in a virtual machine on an AMD Family 10h 707 * processor, then it must assume that MCA is enabled by the virtual 708 * machine monitor. 709 */ 710 if (vm_guest == VM_GUEST_VM && cpu_vendor_id == CPU_VENDOR_AMD && 711 CPUID_TO_FAMILY(cpu_id) == 0x10) 712 workaround_erratum383 = 1; 713 714 /* 715 * Are large page mappings supported and enabled? 716 */ 717 TUNABLE_INT_FETCH("vm.pmap.pg_ps_enabled", &pg_ps_enabled); 718 if (pseflag == 0) 719 pg_ps_enabled = 0; 720 else if (pg_ps_enabled) { 721 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0, 722 ("pmap_init: can't assign to pagesizes[1]")); 723 pagesizes[1] = NBPDR; 724 } 725 726 /* 727 * Calculate the size of the pv head table for superpages. 728 */ 729 for (i = 0; phys_avail[i + 1]; i += 2); 730 pv_npg = round_4mpage(phys_avail[(i - 2) + 1]) / NBPDR; 731 732 /* 733 * Allocate memory for the pv head table for superpages. 734 */ 735 s = (vm_size_t)(pv_npg * sizeof(struct md_page)); 736 s = round_page(s); 737 pv_table = (struct md_page *)kmem_alloc(kernel_map, s); 738 for (i = 0; i < pv_npg; i++) 739 TAILQ_INIT(&pv_table[i].pv_list); 740 741 pv_maxchunks = MAX(pv_entry_max / _NPCPV, maxproc); 742 pv_chunkbase = (struct pv_chunk *)kmem_alloc_nofault(kernel_map, 743 PAGE_SIZE * pv_maxchunks); 744 if (pv_chunkbase == NULL) 745 panic("pmap_init: not enough kvm for pv chunks"); 746 pmap_ptelist_init(&pv_vafree, pv_chunkbase, pv_maxchunks); 747#ifdef PAE 748 pdptzone = uma_zcreate("PDPT", NPGPTD * sizeof(pdpt_entry_t), NULL, 749 NULL, NULL, NULL, (NPGPTD * sizeof(pdpt_entry_t)) - 1, 750 UMA_ZONE_VM | UMA_ZONE_NOFREE); 751 uma_zone_set_allocf(pdptzone, pmap_pdpt_allocf); 752#endif 753} 754 755 756SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_max, CTLFLAG_RD, &pv_entry_max, 0, 757 "Max number of PV entries"); 758SYSCTL_INT(_vm_pmap, OID_AUTO, shpgperproc, CTLFLAG_RD, &shpgperproc, 0, 759 "Page share factor per proc"); 760 761SYSCTL_NODE(_vm_pmap, OID_AUTO, pde, CTLFLAG_RD, 0, 762 "2/4MB page mapping counters"); 763 764static u_long pmap_pde_demotions; 765SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, demotions, CTLFLAG_RD, 766 &pmap_pde_demotions, 0, "2/4MB page demotions"); 767 768static u_long pmap_pde_mappings; 769SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, mappings, CTLFLAG_RD, 770 &pmap_pde_mappings, 0, "2/4MB page mappings"); 771 772static u_long pmap_pde_p_failures; 773SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, p_failures, CTLFLAG_RD, 774 &pmap_pde_p_failures, 0, "2/4MB page promotion failures"); 775 776static u_long pmap_pde_promotions; 777SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, promotions, CTLFLAG_RD, 778 &pmap_pde_promotions, 0, "2/4MB page promotions"); 779 780/*************************************************** 781 * Low level helper routines..... 782 ***************************************************/ 783 784/* 785 * Determine the appropriate bits to set in a PTE or PDE for a specified 786 * caching mode. 787 */ 788int 789pmap_cache_bits(int mode, boolean_t is_pde) 790{ 791 int pat_flag, pat_index, cache_bits; 792 793 /* The PAT bit is different for PTE's and PDE's. */ 794 pat_flag = is_pde ? PG_PDE_PAT : PG_PTE_PAT; 795 796 /* If we don't support PAT, map extended modes to older ones. */ 797 if (!(cpu_feature & CPUID_PAT)) { 798 switch (mode) { 799 case PAT_UNCACHEABLE: 800 case PAT_WRITE_THROUGH: 801 case PAT_WRITE_BACK: 802 break; 803 case PAT_UNCACHED: 804 case PAT_WRITE_COMBINING: 805 case PAT_WRITE_PROTECTED: 806 mode = PAT_UNCACHEABLE; 807 break; 808 } 809 } 810 811 /* Map the caching mode to a PAT index. */ 812 if (pat_works) { 813 switch (mode) { 814 case PAT_UNCACHEABLE: 815 pat_index = 3; 816 break; 817 case PAT_WRITE_THROUGH: 818 pat_index = 1; 819 break; 820 case PAT_WRITE_BACK: 821 pat_index = 0; 822 break; 823 case PAT_UNCACHED: 824 pat_index = 2; 825 break; 826 case PAT_WRITE_COMBINING: 827 pat_index = 5; 828 break; 829 case PAT_WRITE_PROTECTED: 830 pat_index = 4; 831 break; 832 default: 833 panic("Unknown caching mode %d\n", mode); 834 } 835 } else { 836 switch (mode) { 837 case PAT_UNCACHED: 838 case PAT_UNCACHEABLE: 839 case PAT_WRITE_PROTECTED: 840 pat_index = 3; 841 break; 842 case PAT_WRITE_THROUGH: 843 pat_index = 1; 844 break; 845 case PAT_WRITE_BACK: 846 pat_index = 0; 847 break; 848 case PAT_WRITE_COMBINING: 849 pat_index = 2; 850 break; 851 default: 852 panic("Unknown caching mode %d\n", mode); 853 } 854 } 855 856 /* Map the 3-bit index value into the PAT, PCD, and PWT bits. */ 857 cache_bits = 0; 858 if (pat_index & 0x4) 859 cache_bits |= pat_flag; 860 if (pat_index & 0x2) 861 cache_bits |= PG_NC_PCD; 862 if (pat_index & 0x1) 863 cache_bits |= PG_NC_PWT; 864 return (cache_bits); 865} 866 867/* 868 * The caller is responsible for maintaining TLB consistency. 869 */ 870static void 871pmap_kenter_pde(vm_offset_t va, pd_entry_t newpde) 872{ 873 pd_entry_t *pde; 874 pmap_t pmap; 875 boolean_t PTD_updated; 876 877 PTD_updated = FALSE; 878 mtx_lock_spin(&allpmaps_lock); 879 LIST_FOREACH(pmap, &allpmaps, pm_list) { 880 if ((pmap->pm_pdir[PTDPTDI] & PG_FRAME) == (PTDpde[0] & 881 PG_FRAME)) 882 PTD_updated = TRUE; 883 pde = pmap_pde(pmap, va); 884 pde_store(pde, newpde); 885 } 886 mtx_unlock_spin(&allpmaps_lock); 887 KASSERT(PTD_updated, 888 ("pmap_kenter_pde: current page table is not in allpmaps")); 889} 890 891/* 892 * After changing the page size for the specified virtual address in the page 893 * table, flush the corresponding entries from the processor's TLB. Only the 894 * calling processor's TLB is affected. 895 * 896 * The calling thread must be pinned to a processor. 897 */ 898static void 899pmap_update_pde_invalidate(vm_offset_t va, pd_entry_t newpde) 900{ 901 u_long cr4; 902 903 if ((newpde & PG_PS) == 0) 904 /* Demotion: flush a specific 2MB page mapping. */ 905 invlpg(va); 906 else if ((newpde & PG_G) == 0) 907 /* 908 * Promotion: flush every 4KB page mapping from the TLB 909 * because there are too many to flush individually. 910 */ 911 invltlb(); 912 else { 913 /* 914 * Promotion: flush every 4KB page mapping from the TLB, 915 * including any global (PG_G) mappings. 916 */ 917 cr4 = rcr4(); 918 load_cr4(cr4 & ~CR4_PGE); 919 /* 920 * Although preemption at this point could be detrimental to 921 * performance, it would not lead to an error. PG_G is simply 922 * ignored if CR4.PGE is clear. Moreover, in case this block 923 * is re-entered, the load_cr4() either above or below will 924 * modify CR4.PGE flushing the TLB. 925 */ 926 load_cr4(cr4 | CR4_PGE); 927 } 928} 929#ifdef SMP 930/* 931 * For SMP, these functions have to use the IPI mechanism for coherence. 932 * 933 * N.B.: Before calling any of the following TLB invalidation functions, 934 * the calling processor must ensure that all stores updating a non- 935 * kernel page table are globally performed. Otherwise, another 936 * processor could cache an old, pre-update entry without being 937 * invalidated. This can happen one of two ways: (1) The pmap becomes 938 * active on another processor after its pm_active field is checked by 939 * one of the following functions but before a store updating the page 940 * table is globally performed. (2) The pmap becomes active on another 941 * processor before its pm_active field is checked but due to 942 * speculative loads one of the following functions stills reads the 943 * pmap as inactive on the other processor. 944 * 945 * The kernel page table is exempt because its pm_active field is 946 * immutable. The kernel page table is always active on every 947 * processor. 948 */ 949void 950pmap_invalidate_page(pmap_t pmap, vm_offset_t va) 951{ 952 u_int cpumask; 953 u_int other_cpus; 954 955 sched_pin(); 956 if (pmap == kernel_pmap || pmap->pm_active == all_cpus) { 957 invlpg(va); 958 smp_invlpg(va); 959 } else { 960 cpumask = PCPU_GET(cpumask); 961 other_cpus = PCPU_GET(other_cpus); 962 if (pmap->pm_active & cpumask) 963 invlpg(va); 964 if (pmap->pm_active & other_cpus) 965 smp_masked_invlpg(pmap->pm_active & other_cpus, va); 966 } 967 sched_unpin(); 968} 969 970void 971pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 972{ 973 u_int cpumask; 974 u_int other_cpus; 975 vm_offset_t addr; 976 977 sched_pin(); 978 if (pmap == kernel_pmap || pmap->pm_active == all_cpus) { 979 for (addr = sva; addr < eva; addr += PAGE_SIZE) 980 invlpg(addr); 981 smp_invlpg_range(sva, eva); 982 } else { 983 cpumask = PCPU_GET(cpumask); 984 other_cpus = PCPU_GET(other_cpus); 985 if (pmap->pm_active & cpumask) 986 for (addr = sva; addr < eva; addr += PAGE_SIZE) 987 invlpg(addr); 988 if (pmap->pm_active & other_cpus) 989 smp_masked_invlpg_range(pmap->pm_active & other_cpus, 990 sva, eva); 991 } 992 sched_unpin(); 993} 994 995void 996pmap_invalidate_all(pmap_t pmap) 997{ 998 u_int cpumask; 999 u_int other_cpus; 1000 1001 sched_pin(); 1002 if (pmap == kernel_pmap || pmap->pm_active == all_cpus) { 1003 invltlb(); 1004 smp_invltlb(); 1005 } else { 1006 cpumask = PCPU_GET(cpumask); 1007 other_cpus = PCPU_GET(other_cpus); 1008 if (pmap->pm_active & cpumask) 1009 invltlb(); 1010 if (pmap->pm_active & other_cpus) 1011 smp_masked_invltlb(pmap->pm_active & other_cpus); 1012 } 1013 sched_unpin(); 1014} 1015 1016void 1017pmap_invalidate_cache(void) 1018{ 1019 1020 sched_pin(); 1021 wbinvd(); 1022 smp_cache_flush(); 1023 sched_unpin(); 1024} 1025 1026struct pde_action { 1027 cpumask_t store; /* processor that updates the PDE */ 1028 cpumask_t invalidate; /* processors that invalidate their TLB */ 1029 vm_offset_t va; 1030 pd_entry_t *pde; 1031 pd_entry_t newpde; 1032}; 1033 1034static void 1035pmap_update_pde_kernel(void *arg) 1036{ 1037 struct pde_action *act = arg; 1038 pd_entry_t *pde; 1039 pmap_t pmap; 1040 1041 if (act->store == PCPU_GET(cpumask)) 1042 /* 1043 * Elsewhere, this operation requires allpmaps_lock for 1044 * synchronization. Here, it does not because it is being 1045 * performed in the context of an all_cpus rendezvous. 1046 */ 1047 LIST_FOREACH(pmap, &allpmaps, pm_list) { 1048 pde = pmap_pde(pmap, act->va); 1049 pde_store(pde, act->newpde); 1050 } 1051} 1052 1053static void 1054pmap_update_pde_user(void *arg) 1055{ 1056 struct pde_action *act = arg; 1057 1058 if (act->store == PCPU_GET(cpumask)) 1059 pde_store(act->pde, act->newpde); 1060} 1061 1062static void 1063pmap_update_pde_teardown(void *arg) 1064{ 1065 struct pde_action *act = arg; 1066 1067 if ((act->invalidate & PCPU_GET(cpumask)) != 0) 1068 pmap_update_pde_invalidate(act->va, act->newpde); 1069} 1070 1071/* 1072 * Change the page size for the specified virtual address in a way that 1073 * prevents any possibility of the TLB ever having two entries that map the 1074 * same virtual address using different page sizes. This is the recommended 1075 * workaround for Erratum 383 on AMD Family 10h processors. It prevents a 1076 * machine check exception for a TLB state that is improperly diagnosed as a 1077 * hardware error. 1078 */ 1079static void 1080pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde) 1081{ 1082 struct pde_action act; 1083 cpumask_t active, cpumask; 1084 1085 sched_pin(); 1086 cpumask = PCPU_GET(cpumask); 1087 if (pmap == kernel_pmap) 1088 active = all_cpus; 1089 else 1090 active = pmap->pm_active; 1091 if ((active & PCPU_GET(other_cpus)) != 0) { 1092 act.store = cpumask; 1093 act.invalidate = active; 1094 act.va = va; 1095 act.pde = pde; 1096 act.newpde = newpde; 1097 smp_rendezvous_cpus(cpumask | active, 1098 smp_no_rendevous_barrier, pmap == kernel_pmap ? 1099 pmap_update_pde_kernel : pmap_update_pde_user, 1100 pmap_update_pde_teardown, &act); 1101 } else { 1102 if (pmap == kernel_pmap) 1103 pmap_kenter_pde(va, newpde); 1104 else 1105 pde_store(pde, newpde); 1106 if ((active & cpumask) != 0) 1107 pmap_update_pde_invalidate(va, newpde); 1108 } 1109 sched_unpin(); 1110} 1111#else /* !SMP */ 1112/* 1113 * Normal, non-SMP, 486+ invalidation functions. 1114 * We inline these within pmap.c for speed. 1115 */ 1116PMAP_INLINE void 1117pmap_invalidate_page(pmap_t pmap, vm_offset_t va) 1118{ 1119 1120 if (pmap == kernel_pmap || pmap->pm_active) 1121 invlpg(va); 1122} 1123 1124PMAP_INLINE void 1125pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 1126{ 1127 vm_offset_t addr; 1128 1129 if (pmap == kernel_pmap || pmap->pm_active) 1130 for (addr = sva; addr < eva; addr += PAGE_SIZE) 1131 invlpg(addr); 1132} 1133 1134PMAP_INLINE void 1135pmap_invalidate_all(pmap_t pmap) 1136{ 1137 1138 if (pmap == kernel_pmap || pmap->pm_active) 1139 invltlb(); 1140} 1141 1142PMAP_INLINE void 1143pmap_invalidate_cache(void) 1144{ 1145 1146 wbinvd(); 1147} 1148 1149static void 1150pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde) 1151{ 1152 1153 if (pmap == kernel_pmap) 1154 pmap_kenter_pde(va, newpde); 1155 else 1156 pde_store(pde, newpde); 1157 if (pmap == kernel_pmap || pmap->pm_active) 1158 pmap_update_pde_invalidate(va, newpde); 1159} 1160#endif /* !SMP */ 1161 1162void 1163pmap_invalidate_cache_range(vm_offset_t sva, vm_offset_t eva) 1164{ 1165 1166 KASSERT((sva & PAGE_MASK) == 0, 1167 ("pmap_invalidate_cache_range: sva not page-aligned")); 1168 KASSERT((eva & PAGE_MASK) == 0, 1169 ("pmap_invalidate_cache_range: eva not page-aligned")); 1170 1171 if (cpu_feature & CPUID_SS) 1172 ; /* If "Self Snoop" is supported, do nothing. */ 1173 else if ((cpu_feature & CPUID_CLFSH) != 0 && 1174 eva - sva < 2 * 1024 * 1024) { 1175 1176 /* 1177 * Otherwise, do per-cache line flush. Use the mfence 1178 * instruction to insure that previous stores are 1179 * included in the write-back. The processor 1180 * propagates flush to other processors in the cache 1181 * coherence domain. 1182 */ 1183 mfence(); 1184 for (; sva < eva; sva += cpu_clflush_line_size) 1185 clflush(sva); 1186 mfence(); 1187 } else { 1188 1189 /* 1190 * No targeted cache flush methods are supported by CPU, 1191 * or the supplied range is bigger than 2MB. 1192 * Globally invalidate cache. 1193 */ 1194 pmap_invalidate_cache(); 1195 } 1196} 1197 1198/* 1199 * Are we current address space or kernel? N.B. We return FALSE when 1200 * a pmap's page table is in use because a kernel thread is borrowing 1201 * it. The borrowed page table can change spontaneously, making any 1202 * dependence on its continued use subject to a race condition. 1203 */ 1204static __inline int 1205pmap_is_current(pmap_t pmap) 1206{ 1207 1208 return (pmap == kernel_pmap || 1209 (pmap == vmspace_pmap(curthread->td_proc->p_vmspace) && 1210 (pmap->pm_pdir[PTDPTDI] & PG_FRAME) == (PTDpde[0] & PG_FRAME))); 1211} 1212 1213/* 1214 * If the given pmap is not the current or kernel pmap, the returned pte must 1215 * be released by passing it to pmap_pte_release(). 1216 */ 1217pt_entry_t * 1218pmap_pte(pmap_t pmap, vm_offset_t va) 1219{ 1220 pd_entry_t newpf; 1221 pd_entry_t *pde; 1222 1223 pde = pmap_pde(pmap, va); 1224 if (*pde & PG_PS) 1225 return (pde); 1226 if (*pde != 0) { 1227 /* are we current address space or kernel? */ 1228 if (pmap_is_current(pmap)) 1229 return (vtopte(va)); 1230 mtx_lock(&PMAP2mutex); 1231 newpf = *pde & PG_FRAME; 1232 if ((*PMAP2 & PG_FRAME) != newpf) { 1233 *PMAP2 = newpf | PG_RW | PG_V | PG_A | PG_M; 1234 pmap_invalidate_page(kernel_pmap, (vm_offset_t)PADDR2); 1235 } 1236 return (PADDR2 + (i386_btop(va) & (NPTEPG - 1))); 1237 } 1238 return (0); 1239} 1240 1241/* 1242 * Releases a pte that was obtained from pmap_pte(). Be prepared for the pte 1243 * being NULL. 1244 */ 1245static __inline void 1246pmap_pte_release(pt_entry_t *pte) 1247{ 1248 1249 if ((pt_entry_t *)((vm_offset_t)pte & ~PAGE_MASK) == PADDR2) 1250 mtx_unlock(&PMAP2mutex); 1251} 1252 1253static __inline void 1254invlcaddr(void *caddr) 1255{ 1256 1257 invlpg((u_int)caddr); 1258} 1259 1260/* 1261 * Super fast pmap_pte routine best used when scanning 1262 * the pv lists. This eliminates many coarse-grained 1263 * invltlb calls. Note that many of the pv list 1264 * scans are across different pmaps. It is very wasteful 1265 * to do an entire invltlb for checking a single mapping. 1266 * 1267 * If the given pmap is not the current pmap, vm_page_queue_mtx 1268 * must be held and curthread pinned to a CPU. 1269 */ 1270static pt_entry_t * 1271pmap_pte_quick(pmap_t pmap, vm_offset_t va) 1272{ 1273 pd_entry_t newpf; 1274 pd_entry_t *pde; 1275 1276 pde = pmap_pde(pmap, va); 1277 if (*pde & PG_PS) 1278 return (pde); 1279 if (*pde != 0) { 1280 /* are we current address space or kernel? */ 1281 if (pmap_is_current(pmap)) 1282 return (vtopte(va)); 1283 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1284 KASSERT(curthread->td_pinned > 0, ("curthread not pinned")); 1285 newpf = *pde & PG_FRAME; 1286 if ((*PMAP1 & PG_FRAME) != newpf) { 1287 *PMAP1 = newpf | PG_RW | PG_V | PG_A | PG_M; 1288#ifdef SMP 1289 PMAP1cpu = PCPU_GET(cpuid); 1290#endif 1291 invlcaddr(PADDR1); 1292 PMAP1changed++; 1293 } else 1294#ifdef SMP 1295 if (PMAP1cpu != PCPU_GET(cpuid)) { 1296 PMAP1cpu = PCPU_GET(cpuid); 1297 invlcaddr(PADDR1); 1298 PMAP1changedcpu++; 1299 } else 1300#endif 1301 PMAP1unchanged++; 1302 return (PADDR1 + (i386_btop(va) & (NPTEPG - 1))); 1303 } 1304 return (0); 1305} 1306 1307/* 1308 * Routine: pmap_extract 1309 * Function: 1310 * Extract the physical page address associated 1311 * with the given map/virtual_address pair. 1312 */ 1313vm_paddr_t 1314pmap_extract(pmap_t pmap, vm_offset_t va) 1315{ 1316 vm_paddr_t rtval; 1317 pt_entry_t *pte; 1318 pd_entry_t pde; 1319 1320 rtval = 0; 1321 PMAP_LOCK(pmap); 1322 pde = pmap->pm_pdir[va >> PDRSHIFT]; 1323 if (pde != 0) { 1324 if ((pde & PG_PS) != 0) 1325 rtval = (pde & PG_PS_FRAME) | (va & PDRMASK); 1326 else { 1327 pte = pmap_pte(pmap, va); 1328 rtval = (*pte & PG_FRAME) | (va & PAGE_MASK); 1329 pmap_pte_release(pte); 1330 } 1331 } 1332 PMAP_UNLOCK(pmap); 1333 return (rtval); 1334} 1335 1336/* 1337 * Routine: pmap_extract_and_hold 1338 * Function: 1339 * Atomically extract and hold the physical page 1340 * with the given pmap and virtual address pair 1341 * if that mapping permits the given protection. 1342 */ 1343vm_page_t 1344pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot) 1345{ 1346 pd_entry_t pde; 1347 pt_entry_t pte; 1348 vm_page_t m; 1349 vm_paddr_t pa; 1350 1351 pa = 0; 1352 m = NULL; 1353 PMAP_LOCK(pmap); 1354retry: 1355 pde = *pmap_pde(pmap, va); 1356 if (pde != 0) { 1357 if (pde & PG_PS) { 1358 if ((pde & PG_RW) || (prot & VM_PROT_WRITE) == 0) { 1359 if (vm_page_pa_tryrelock(pmap, (pde & PG_PS_FRAME) | 1360 (va & PDRMASK), &pa)) 1361 goto retry; 1362 m = PHYS_TO_VM_PAGE((pde & PG_PS_FRAME) | 1363 (va & PDRMASK)); 1364 vm_page_hold(m); 1365 } 1366 } else { 1367 sched_pin(); 1368 pte = *pmap_pte_quick(pmap, va); 1369 if (pte != 0 && 1370 ((pte & PG_RW) || (prot & VM_PROT_WRITE) == 0)) { 1371 if (vm_page_pa_tryrelock(pmap, pte & PG_FRAME, &pa)) 1372 goto retry; 1373 m = PHYS_TO_VM_PAGE(pte & PG_FRAME); 1374 vm_page_hold(m); 1375 } 1376 sched_unpin(); 1377 } 1378 } 1379 PA_UNLOCK_COND(pa); 1380 PMAP_UNLOCK(pmap); 1381 return (m); 1382} 1383 1384/*************************************************** 1385 * Low level mapping routines..... 1386 ***************************************************/ 1387 1388/* 1389 * Add a wired page to the kva. 1390 * Note: not SMP coherent. 1391 */ 1392PMAP_INLINE void 1393pmap_kenter(vm_offset_t va, vm_paddr_t pa) 1394{ 1395 pt_entry_t *pte; 1396 1397 pte = vtopte(va); 1398 pte_store(pte, pa | PG_RW | PG_V | pgeflag); 1399} 1400 1401static __inline void 1402pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode) 1403{ 1404 pt_entry_t *pte; 1405 1406 pte = vtopte(va); 1407 pte_store(pte, pa | PG_RW | PG_V | pgeflag | pmap_cache_bits(mode, 0)); 1408} 1409 1410/* 1411 * Remove a page from the kernel pagetables. 1412 * Note: not SMP coherent. 1413 */ 1414PMAP_INLINE void 1415pmap_kremove(vm_offset_t va) 1416{ 1417 pt_entry_t *pte; 1418 1419 pte = vtopte(va); 1420 pte_clear(pte); 1421} 1422 1423/* 1424 * Used to map a range of physical addresses into kernel 1425 * virtual address space. 1426 * 1427 * The value passed in '*virt' is a suggested virtual address for 1428 * the mapping. Architectures which can support a direct-mapped 1429 * physical to virtual region can return the appropriate address 1430 * within that region, leaving '*virt' unchanged. Other 1431 * architectures should map the pages starting at '*virt' and 1432 * update '*virt' with the first usable address after the mapped 1433 * region. 1434 */ 1435vm_offset_t 1436pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot) 1437{ 1438 vm_offset_t va, sva; 1439 1440 va = sva = *virt; 1441 while (start < end) { 1442 pmap_kenter(va, start); 1443 va += PAGE_SIZE; 1444 start += PAGE_SIZE; 1445 } 1446 pmap_invalidate_range(kernel_pmap, sva, va); 1447 *virt = va; 1448 return (sva); 1449} 1450 1451 1452/* 1453 * Add a list of wired pages to the kva 1454 * this routine is only used for temporary 1455 * kernel mappings that do not need to have 1456 * page modification or references recorded. 1457 * Note that old mappings are simply written 1458 * over. The page *must* be wired. 1459 * Note: SMP coherent. Uses a ranged shootdown IPI. 1460 */ 1461void 1462pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count) 1463{ 1464 pt_entry_t *endpte, oldpte, *pte; 1465 1466 oldpte = 0; 1467 pte = vtopte(sva); 1468 endpte = pte + count; 1469 while (pte < endpte) { 1470 oldpte |= *pte; 1471 pte_store(pte, VM_PAGE_TO_PHYS(*ma) | pgeflag | 1472 pmap_cache_bits((*ma)->md.pat_mode, 0) | PG_RW | PG_V); 1473 pte++; 1474 ma++; 1475 } 1476 if ((oldpte & PG_V) != 0) 1477 pmap_invalidate_range(kernel_pmap, sva, sva + count * 1478 PAGE_SIZE); 1479} 1480 1481/* 1482 * This routine tears out page mappings from the 1483 * kernel -- it is meant only for temporary mappings. 1484 * Note: SMP coherent. Uses a ranged shootdown IPI. 1485 */ 1486void 1487pmap_qremove(vm_offset_t sva, int count) 1488{ 1489 vm_offset_t va; 1490 1491 va = sva; 1492 while (count-- > 0) { 1493 pmap_kremove(va); 1494 va += PAGE_SIZE; 1495 } 1496 pmap_invalidate_range(kernel_pmap, sva, va); 1497} 1498 1499/*************************************************** 1500 * Page table page management routines..... 1501 ***************************************************/ 1502static __inline void 1503pmap_free_zero_pages(vm_page_t free) 1504{ 1505 vm_page_t m; 1506 1507 while (free != NULL) { 1508 m = free; 1509 free = m->right; 1510 /* Preserve the page's PG_ZERO setting. */ 1511 vm_page_free_toq(m); 1512 } 1513} 1514 1515/* 1516 * Schedule the specified unused page table page to be freed. Specifically, 1517 * add the page to the specified list of pages that will be released to the 1518 * physical memory manager after the TLB has been updated. 1519 */ 1520static __inline void 1521pmap_add_delayed_free_list(vm_page_t m, vm_page_t *free, boolean_t set_PG_ZERO) 1522{ 1523 1524 if (set_PG_ZERO) 1525 m->flags |= PG_ZERO; 1526 else 1527 m->flags &= ~PG_ZERO; 1528 m->right = *free; 1529 *free = m; 1530} 1531 1532/* 1533 * Inserts the specified page table page into the specified pmap's collection 1534 * of idle page table pages. Each of a pmap's page table pages is responsible 1535 * for mapping a distinct range of virtual addresses. The pmap's collection is 1536 * ordered by this virtual address range. 1537 */ 1538static void 1539pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte) 1540{ 1541 vm_page_t root; 1542 1543 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1544 root = pmap->pm_root; 1545 if (root == NULL) { 1546 mpte->left = NULL; 1547 mpte->right = NULL; 1548 } else { 1549 root = vm_page_splay(mpte->pindex, root); 1550 if (mpte->pindex < root->pindex) { 1551 mpte->left = root->left; 1552 mpte->right = root; 1553 root->left = NULL; 1554 } else if (mpte->pindex == root->pindex) 1555 panic("pmap_insert_pt_page: pindex already inserted"); 1556 else { 1557 mpte->right = root->right; 1558 mpte->left = root; 1559 root->right = NULL; 1560 } 1561 } 1562 pmap->pm_root = mpte; 1563} 1564 1565/* 1566 * Looks for a page table page mapping the specified virtual address in the 1567 * specified pmap's collection of idle page table pages. Returns NULL if there 1568 * is no page table page corresponding to the specified virtual address. 1569 */ 1570static vm_page_t 1571pmap_lookup_pt_page(pmap_t pmap, vm_offset_t va) 1572{ 1573 vm_page_t mpte; 1574 vm_pindex_t pindex = va >> PDRSHIFT; 1575 1576 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1577 if ((mpte = pmap->pm_root) != NULL && mpte->pindex != pindex) { 1578 mpte = vm_page_splay(pindex, mpte); 1579 if ((pmap->pm_root = mpte)->pindex != pindex) 1580 mpte = NULL; 1581 } 1582 return (mpte); 1583} 1584 1585/* 1586 * Removes the specified page table page from the specified pmap's collection 1587 * of idle page table pages. The specified page table page must be a member of 1588 * the pmap's collection. 1589 */ 1590static void 1591pmap_remove_pt_page(pmap_t pmap, vm_page_t mpte) 1592{ 1593 vm_page_t root; 1594 1595 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1596 if (mpte != pmap->pm_root) 1597 vm_page_splay(mpte->pindex, pmap->pm_root); 1598 if (mpte->left == NULL) 1599 root = mpte->right; 1600 else { 1601 root = vm_page_splay(mpte->pindex, mpte->left); 1602 root->right = mpte->right; 1603 } 1604 pmap->pm_root = root; 1605} 1606 1607/* 1608 * This routine unholds page table pages, and if the hold count 1609 * drops to zero, then it decrements the wire count. 1610 */ 1611static __inline int 1612pmap_unwire_pte_hold(pmap_t pmap, vm_page_t m, vm_page_t *free) 1613{ 1614 1615 --m->wire_count; 1616 if (m->wire_count == 0) 1617 return (_pmap_unwire_pte_hold(pmap, m, free)); 1618 else 1619 return (0); 1620} 1621 1622static int 1623_pmap_unwire_pte_hold(pmap_t pmap, vm_page_t m, vm_page_t *free) 1624{ 1625 vm_offset_t pteva; 1626 1627 /* 1628 * unmap the page table page 1629 */ 1630 pmap->pm_pdir[m->pindex] = 0; 1631 --pmap->pm_stats.resident_count; 1632 1633 /* 1634 * This is a release store so that the ordinary store unmapping 1635 * the page table page is globally performed before TLB shoot- 1636 * down is begun. 1637 */ 1638 atomic_subtract_rel_int(&cnt.v_wire_count, 1); 1639 1640 /* 1641 * Do an invltlb to make the invalidated mapping 1642 * take effect immediately. 1643 */ 1644 pteva = VM_MAXUSER_ADDRESS + i386_ptob(m->pindex); 1645 pmap_invalidate_page(pmap, pteva); 1646 1647 /* 1648 * Put page on a list so that it is released after 1649 * *ALL* TLB shootdown is done 1650 */ 1651 pmap_add_delayed_free_list(m, free, TRUE); 1652 1653 return (1); 1654} 1655 1656/* 1657 * After removing a page table entry, this routine is used to 1658 * conditionally free the page, and manage the hold/wire counts. 1659 */ 1660static int 1661pmap_unuse_pt(pmap_t pmap, vm_offset_t va, vm_page_t *free) 1662{ 1663 pd_entry_t ptepde; 1664 vm_page_t mpte; 1665 1666 if (va >= VM_MAXUSER_ADDRESS) 1667 return (0); 1668 ptepde = *pmap_pde(pmap, va); 1669 mpte = PHYS_TO_VM_PAGE(ptepde & PG_FRAME); 1670 return (pmap_unwire_pte_hold(pmap, mpte, free)); 1671} 1672 1673void 1674pmap_pinit0(pmap_t pmap) 1675{ 1676 1677 PMAP_LOCK_INIT(pmap); 1678 pmap->pm_pdir = (pd_entry_t *)(KERNBASE + (vm_offset_t)IdlePTD); 1679#ifdef PAE 1680 pmap->pm_pdpt = (pdpt_entry_t *)(KERNBASE + (vm_offset_t)IdlePDPT); 1681#endif 1682 pmap->pm_root = NULL; 1683 pmap->pm_active = 0; 1684 PCPU_SET(curpmap, pmap); 1685 TAILQ_INIT(&pmap->pm_pvchunk); 1686 bzero(&pmap->pm_stats, sizeof pmap->pm_stats); 1687 mtx_lock_spin(&allpmaps_lock); 1688 LIST_INSERT_HEAD(&allpmaps, pmap, pm_list); 1689 mtx_unlock_spin(&allpmaps_lock); 1690} 1691 1692/* 1693 * Initialize a preallocated and zeroed pmap structure, 1694 * such as one in a vmspace structure. 1695 */ 1696int 1697pmap_pinit(pmap_t pmap) 1698{ 1699 vm_page_t m, ptdpg[NPGPTD]; 1700 vm_paddr_t pa; 1701 static int color; 1702 int i; 1703 1704 PMAP_LOCK_INIT(pmap); 1705 1706 /* 1707 * No need to allocate page table space yet but we do need a valid 1708 * page directory table. 1709 */ 1710 if (pmap->pm_pdir == NULL) { 1711 pmap->pm_pdir = (pd_entry_t *)kmem_alloc_nofault(kernel_map, 1712 NBPTD); 1713 1714 if (pmap->pm_pdir == NULL) { 1715 PMAP_LOCK_DESTROY(pmap); 1716 return (0); 1717 } 1718#ifdef PAE 1719 pmap->pm_pdpt = uma_zalloc(pdptzone, M_WAITOK | M_ZERO); 1720 KASSERT(((vm_offset_t)pmap->pm_pdpt & 1721 ((NPGPTD * sizeof(pdpt_entry_t)) - 1)) == 0, 1722 ("pmap_pinit: pdpt misaligned")); 1723 KASSERT(pmap_kextract((vm_offset_t)pmap->pm_pdpt) < (4ULL<<30), 1724 ("pmap_pinit: pdpt above 4g")); 1725#endif 1726 pmap->pm_root = NULL; 1727 } 1728 KASSERT(pmap->pm_root == NULL, 1729 ("pmap_pinit: pmap has reserved page table page(s)")); 1730 1731 /* 1732 * allocate the page directory page(s) 1733 */ 1734 for (i = 0; i < NPGPTD;) { 1735 m = vm_page_alloc(NULL, color++, 1736 VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | 1737 VM_ALLOC_ZERO); 1738 if (m == NULL) 1739 VM_WAIT; 1740 else { 1741 ptdpg[i++] = m; 1742 } 1743 } 1744 1745 pmap_qenter((vm_offset_t)pmap->pm_pdir, ptdpg, NPGPTD); 1746 1747 for (i = 0; i < NPGPTD; i++) { 1748 if ((ptdpg[i]->flags & PG_ZERO) == 0) 1749 bzero(pmap->pm_pdir + (i * NPDEPG), PAGE_SIZE); 1750 } 1751 1752 mtx_lock_spin(&allpmaps_lock); 1753 LIST_INSERT_HEAD(&allpmaps, pmap, pm_list); 1754 mtx_unlock_spin(&allpmaps_lock); 1755 /* Wire in kernel global address entries. */ 1756 bcopy(PTD + KPTDI, pmap->pm_pdir + KPTDI, nkpt * sizeof(pd_entry_t)); 1757 1758 /* install self-referential address mapping entry(s) */ 1759 for (i = 0; i < NPGPTD; i++) { 1760 pa = VM_PAGE_TO_PHYS(ptdpg[i]); 1761 pmap->pm_pdir[PTDPTDI + i] = pa | PG_V | PG_RW | PG_A | PG_M; 1762#ifdef PAE 1763 pmap->pm_pdpt[i] = pa | PG_V; 1764#endif 1765 } 1766 1767 pmap->pm_active = 0; 1768 TAILQ_INIT(&pmap->pm_pvchunk); 1769 bzero(&pmap->pm_stats, sizeof pmap->pm_stats); 1770 1771 return (1); 1772} 1773 1774/* 1775 * this routine is called if the page table page is not 1776 * mapped correctly. 1777 */ 1778static vm_page_t 1779_pmap_allocpte(pmap_t pmap, unsigned ptepindex, int flags) 1780{ 1781 vm_paddr_t ptepa; 1782 vm_page_t m; 1783 1784 KASSERT((flags & (M_NOWAIT | M_WAITOK)) == M_NOWAIT || 1785 (flags & (M_NOWAIT | M_WAITOK)) == M_WAITOK, 1786 ("_pmap_allocpte: flags is neither M_NOWAIT nor M_WAITOK")); 1787 1788 /* 1789 * Allocate a page table page. 1790 */ 1791 if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ | 1792 VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) { 1793 if (flags & M_WAITOK) { 1794 PMAP_UNLOCK(pmap); 1795 vm_page_unlock_queues(); 1796 VM_WAIT; 1797 vm_page_lock_queues(); 1798 PMAP_LOCK(pmap); 1799 } 1800 1801 /* 1802 * Indicate the need to retry. While waiting, the page table 1803 * page may have been allocated. 1804 */ 1805 return (NULL); 1806 } 1807 if ((m->flags & PG_ZERO) == 0) 1808 pmap_zero_page(m); 1809 1810 /* 1811 * Map the pagetable page into the process address space, if 1812 * it isn't already there. 1813 */ 1814 1815 pmap->pm_stats.resident_count++; 1816 1817 ptepa = VM_PAGE_TO_PHYS(m); 1818 pmap->pm_pdir[ptepindex] = 1819 (pd_entry_t) (ptepa | PG_U | PG_RW | PG_V | PG_A | PG_M); 1820 1821 return (m); 1822} 1823 1824static vm_page_t 1825pmap_allocpte(pmap_t pmap, vm_offset_t va, int flags) 1826{ 1827 unsigned ptepindex; 1828 pd_entry_t ptepa; 1829 vm_page_t m; 1830 1831 KASSERT((flags & (M_NOWAIT | M_WAITOK)) == M_NOWAIT || 1832 (flags & (M_NOWAIT | M_WAITOK)) == M_WAITOK, 1833 ("pmap_allocpte: flags is neither M_NOWAIT nor M_WAITOK")); 1834 1835 /* 1836 * Calculate pagetable page index 1837 */ 1838 ptepindex = va >> PDRSHIFT; 1839retry: 1840 /* 1841 * Get the page directory entry 1842 */ 1843 ptepa = pmap->pm_pdir[ptepindex]; 1844 1845 /* 1846 * This supports switching from a 4MB page to a 1847 * normal 4K page. 1848 */ 1849 if (ptepa & PG_PS) { 1850 (void)pmap_demote_pde(pmap, &pmap->pm_pdir[ptepindex], va); 1851 ptepa = pmap->pm_pdir[ptepindex]; 1852 } 1853 1854 /* 1855 * If the page table page is mapped, we just increment the 1856 * hold count, and activate it. 1857 */ 1858 if (ptepa) { 1859 m = PHYS_TO_VM_PAGE(ptepa & PG_FRAME); 1860 m->wire_count++; 1861 } else { 1862 /* 1863 * Here if the pte page isn't mapped, or if it has 1864 * been deallocated. 1865 */ 1866 m = _pmap_allocpte(pmap, ptepindex, flags); 1867 if (m == NULL && (flags & M_WAITOK)) 1868 goto retry; 1869 } 1870 return (m); 1871} 1872 1873 1874/*************************************************** 1875* Pmap allocation/deallocation routines. 1876 ***************************************************/ 1877 1878#ifdef SMP 1879/* 1880 * Deal with a SMP shootdown of other users of the pmap that we are 1881 * trying to dispose of. This can be a bit hairy. 1882 */ 1883static cpumask_t *lazymask; 1884static u_int lazyptd; 1885static volatile u_int lazywait; 1886 1887void pmap_lazyfix_action(void); 1888 1889void 1890pmap_lazyfix_action(void) 1891{ 1892 cpumask_t mymask = PCPU_GET(cpumask); 1893 1894#ifdef COUNT_IPIS 1895 (*ipi_lazypmap_counts[PCPU_GET(cpuid)])++; 1896#endif 1897 if (rcr3() == lazyptd) 1898 load_cr3(PCPU_GET(curpcb)->pcb_cr3); 1899 atomic_clear_int(lazymask, mymask); 1900 atomic_store_rel_int(&lazywait, 1); 1901} 1902 1903static void 1904pmap_lazyfix_self(cpumask_t mymask) 1905{ 1906 1907 if (rcr3() == lazyptd) 1908 load_cr3(PCPU_GET(curpcb)->pcb_cr3); 1909 atomic_clear_int(lazymask, mymask); 1910} 1911 1912 1913static void 1914pmap_lazyfix(pmap_t pmap) 1915{ 1916 cpumask_t mymask, mask; 1917 u_int spins; 1918 1919 while ((mask = pmap->pm_active) != 0) { 1920 spins = 50000000; 1921 mask = mask & -mask; /* Find least significant set bit */ 1922 mtx_lock_spin(&smp_ipi_mtx); 1923#ifdef PAE 1924 lazyptd = vtophys(pmap->pm_pdpt); 1925#else 1926 lazyptd = vtophys(pmap->pm_pdir); 1927#endif 1928 mymask = PCPU_GET(cpumask); 1929 if (mask == mymask) { 1930 lazymask = &pmap->pm_active; 1931 pmap_lazyfix_self(mymask); 1932 } else { 1933 atomic_store_rel_int((u_int *)&lazymask, 1934 (u_int)&pmap->pm_active); 1935 atomic_store_rel_int(&lazywait, 0); 1936 ipi_selected(mask, IPI_LAZYPMAP); 1937 while (lazywait == 0) { 1938 ia32_pause(); 1939 if (--spins == 0) 1940 break; 1941 } 1942 } 1943 mtx_unlock_spin(&smp_ipi_mtx); 1944 if (spins == 0) 1945 printf("pmap_lazyfix: spun for 50000000\n"); 1946 } 1947} 1948 1949#else /* SMP */ 1950 1951/* 1952 * Cleaning up on uniprocessor is easy. For various reasons, we're 1953 * unlikely to have to even execute this code, including the fact 1954 * that the cleanup is deferred until the parent does a wait(2), which 1955 * means that another userland process has run. 1956 */ 1957static void 1958pmap_lazyfix(pmap_t pmap) 1959{ 1960 u_int cr3; 1961 1962 cr3 = vtophys(pmap->pm_pdir); 1963 if (cr3 == rcr3()) { 1964 load_cr3(PCPU_GET(curpcb)->pcb_cr3); 1965 pmap->pm_active &= ~(PCPU_GET(cpumask)); 1966 } 1967} 1968#endif /* SMP */ 1969 1970/* 1971 * Release any resources held by the given physical map. 1972 * Called when a pmap initialized by pmap_pinit is being released. 1973 * Should only be called if the map contains no valid mappings. 1974 */ 1975void 1976pmap_release(pmap_t pmap) 1977{ 1978 vm_page_t m, ptdpg[NPGPTD]; 1979 int i; 1980 1981 KASSERT(pmap->pm_stats.resident_count == 0, 1982 ("pmap_release: pmap resident count %ld != 0", 1983 pmap->pm_stats.resident_count)); 1984 KASSERT(pmap->pm_root == NULL, 1985 ("pmap_release: pmap has reserved page table page(s)")); 1986 1987 pmap_lazyfix(pmap); 1988 mtx_lock_spin(&allpmaps_lock); 1989 LIST_REMOVE(pmap, pm_list); 1990 mtx_unlock_spin(&allpmaps_lock); 1991 1992 for (i = 0; i < NPGPTD; i++) 1993 ptdpg[i] = PHYS_TO_VM_PAGE(pmap->pm_pdir[PTDPTDI + i] & 1994 PG_FRAME); 1995 1996 bzero(pmap->pm_pdir + PTDPTDI, (nkpt + NPGPTD) * 1997 sizeof(*pmap->pm_pdir)); 1998 1999 pmap_qremove((vm_offset_t)pmap->pm_pdir, NPGPTD); 2000 2001 for (i = 0; i < NPGPTD; i++) { 2002 m = ptdpg[i]; 2003#ifdef PAE 2004 KASSERT(VM_PAGE_TO_PHYS(m) == (pmap->pm_pdpt[i] & PG_FRAME), 2005 ("pmap_release: got wrong ptd page")); 2006#endif 2007 m->wire_count--; 2008 atomic_subtract_int(&cnt.v_wire_count, 1); 2009 vm_page_free_zero(m); 2010 } 2011 PMAP_LOCK_DESTROY(pmap); 2012} 2013 2014static int 2015kvm_size(SYSCTL_HANDLER_ARGS) 2016{ 2017 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - KERNBASE; 2018 2019 return (sysctl_handle_long(oidp, &ksize, 0, req)); 2020} 2021SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG|CTLFLAG_RD, 2022 0, 0, kvm_size, "IU", "Size of KVM"); 2023 2024static int 2025kvm_free(SYSCTL_HANDLER_ARGS) 2026{ 2027 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end; 2028 2029 return (sysctl_handle_long(oidp, &kfree, 0, req)); 2030} 2031SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG|CTLFLAG_RD, 2032 0, 0, kvm_free, "IU", "Amount of KVM free"); 2033 2034/* 2035 * grow the number of kernel page table entries, if needed 2036 */ 2037void 2038pmap_growkernel(vm_offset_t addr) 2039{ 2040 vm_paddr_t ptppaddr; 2041 vm_page_t nkpg; 2042 pd_entry_t newpdir; 2043 2044 mtx_assert(&kernel_map->system_mtx, MA_OWNED); 2045 addr = roundup2(addr, NBPDR); 2046 if (addr - 1 >= kernel_map->max_offset) 2047 addr = kernel_map->max_offset; 2048 while (kernel_vm_end < addr) { 2049 if (pdir_pde(PTD, kernel_vm_end)) { 2050 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK; 2051 if (kernel_vm_end - 1 >= kernel_map->max_offset) { 2052 kernel_vm_end = kernel_map->max_offset; 2053 break; 2054 } 2055 continue; 2056 } 2057 2058 nkpg = vm_page_alloc(NULL, kernel_vm_end >> PDRSHIFT, 2059 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | 2060 VM_ALLOC_ZERO); 2061 if (nkpg == NULL) 2062 panic("pmap_growkernel: no memory to grow kernel"); 2063 2064 nkpt++; 2065 2066 if ((nkpg->flags & PG_ZERO) == 0) 2067 pmap_zero_page(nkpg); 2068 ptppaddr = VM_PAGE_TO_PHYS(nkpg); 2069 newpdir = (pd_entry_t) (ptppaddr | PG_V | PG_RW | PG_A | PG_M); 2070 pdir_pde(KPTD, kernel_vm_end) = pgeflag | newpdir; 2071 2072 pmap_kenter_pde(kernel_vm_end, newpdir); 2073 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK; 2074 if (kernel_vm_end - 1 >= kernel_map->max_offset) { 2075 kernel_vm_end = kernel_map->max_offset; 2076 break; 2077 } 2078 } 2079} 2080 2081 2082/*************************************************** 2083 * page management routines. 2084 ***************************************************/ 2085 2086CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE); 2087CTASSERT(_NPCM == 11); 2088 2089static __inline struct pv_chunk * 2090pv_to_chunk(pv_entry_t pv) 2091{ 2092 2093 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK)); 2094} 2095 2096#define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap) 2097 2098#define PC_FREE0_9 0xfffffffful /* Free values for index 0 through 9 */ 2099#define PC_FREE10 0x0000fffful /* Free values for index 10 */ 2100 2101static uint32_t pc_freemask[11] = { 2102 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9, 2103 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9, 2104 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9, 2105 PC_FREE0_9, PC_FREE10 2106}; 2107 2108SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0, 2109 "Current number of pv entries"); 2110 2111#ifdef PV_STATS 2112static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail; 2113 2114SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0, 2115 "Current number of pv entry chunks"); 2116SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0, 2117 "Current number of pv entry chunks allocated"); 2118SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0, 2119 "Current number of pv entry chunks frees"); 2120SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0, 2121 "Number of times tried to get a chunk page but failed."); 2122 2123static long pv_entry_frees, pv_entry_allocs; 2124static int pv_entry_spare; 2125 2126SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0, 2127 "Current number of pv entry frees"); 2128SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0, 2129 "Current number of pv entry allocs"); 2130SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0, 2131 "Current number of spare pv entries"); 2132 2133static int pmap_collect_inactive, pmap_collect_active; 2134 2135SYSCTL_INT(_vm_pmap, OID_AUTO, pmap_collect_inactive, CTLFLAG_RD, &pmap_collect_inactive, 0, 2136 "Current number times pmap_collect called on inactive queue"); 2137SYSCTL_INT(_vm_pmap, OID_AUTO, pmap_collect_active, CTLFLAG_RD, &pmap_collect_active, 0, 2138 "Current number times pmap_collect called on active queue"); 2139#endif 2140 2141/* 2142 * We are in a serious low memory condition. Resort to 2143 * drastic measures to free some pages so we can allocate 2144 * another pv entry chunk. This is normally called to 2145 * unmap inactive pages, and if necessary, active pages. 2146 */ 2147static void 2148pmap_collect(pmap_t locked_pmap, struct vpgqueues *vpq) 2149{ 2150 struct md_page *pvh; 2151 pd_entry_t *pde; 2152 pmap_t pmap; 2153 pt_entry_t *pte, tpte; 2154 pv_entry_t next_pv, pv; 2155 vm_offset_t va; 2156 vm_page_t m, free; 2157 2158 sched_pin(); 2159 TAILQ_FOREACH(m, &vpq->pl, pageq) { 2160 if (m->hold_count || m->busy) 2161 continue; 2162 TAILQ_FOREACH_SAFE(pv, &m->md.pv_list, pv_list, next_pv) { 2163 va = pv->pv_va; 2164 pmap = PV_PMAP(pv); 2165 /* Avoid deadlock and lock recursion. */ 2166 if (pmap > locked_pmap) 2167 PMAP_LOCK(pmap); 2168 else if (pmap != locked_pmap && !PMAP_TRYLOCK(pmap)) 2169 continue; 2170 pmap->pm_stats.resident_count--; 2171 pde = pmap_pde(pmap, va); 2172 KASSERT((*pde & PG_PS) == 0, ("pmap_collect: found" 2173 " a 4mpage in page %p's pv list", m)); 2174 pte = pmap_pte_quick(pmap, va); 2175 tpte = pte_load_clear(pte); 2176 KASSERT((tpte & PG_W) == 0, 2177 ("pmap_collect: wired pte %#jx", (uintmax_t)tpte)); 2178 if (tpte & PG_A) 2179 vm_page_flag_set(m, PG_REFERENCED); 2180 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) 2181 vm_page_dirty(m); 2182 free = NULL; 2183 pmap_unuse_pt(pmap, va, &free); 2184 pmap_invalidate_page(pmap, va); 2185 pmap_free_zero_pages(free); 2186 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list); 2187 if (TAILQ_EMPTY(&m->md.pv_list)) { 2188 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 2189 if (TAILQ_EMPTY(&pvh->pv_list)) 2190 vm_page_flag_clear(m, PG_WRITEABLE); 2191 } 2192 free_pv_entry(pmap, pv); 2193 if (pmap != locked_pmap) 2194 PMAP_UNLOCK(pmap); 2195 } 2196 } 2197 sched_unpin(); 2198} 2199 2200 2201/* 2202 * free the pv_entry back to the free list 2203 */ 2204static void 2205free_pv_entry(pmap_t pmap, pv_entry_t pv) 2206{ 2207 vm_page_t m; 2208 struct pv_chunk *pc; 2209 int idx, field, bit; 2210 2211 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2212 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2213 PV_STAT(pv_entry_frees++); 2214 PV_STAT(pv_entry_spare++); 2215 pv_entry_count--; 2216 pc = pv_to_chunk(pv); 2217 idx = pv - &pc->pc_pventry[0]; 2218 field = idx / 32; 2219 bit = idx % 32; 2220 pc->pc_map[field] |= 1ul << bit; 2221 /* move to head of list */ 2222 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 2223 for (idx = 0; idx < _NPCM; idx++) 2224 if (pc->pc_map[idx] != pc_freemask[idx]) { 2225 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list); 2226 return; 2227 } 2228 PV_STAT(pv_entry_spare -= _NPCPV); 2229 PV_STAT(pc_chunk_count--); 2230 PV_STAT(pc_chunk_frees++); 2231 /* entire chunk is free, return it */ 2232 m = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc)); 2233 pmap_qremove((vm_offset_t)pc, 1); 2234 vm_page_unwire(m, 0); 2235 vm_page_free(m); 2236 pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc); 2237} 2238 2239/* 2240 * get a new pv_entry, allocating a block from the system 2241 * when needed. 2242 */ 2243static pv_entry_t 2244get_pv_entry(pmap_t pmap, int try) 2245{ 2246 static const struct timeval printinterval = { 60, 0 }; 2247 static struct timeval lastprint; 2248 static vm_pindex_t colour; 2249 struct vpgqueues *pq; 2250 int bit, field; 2251 pv_entry_t pv; 2252 struct pv_chunk *pc; 2253 vm_page_t m; 2254 2255 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2256 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2257 PV_STAT(pv_entry_allocs++); 2258 pv_entry_count++; 2259 if (pv_entry_count > pv_entry_high_water) 2260 if (ratecheck(&lastprint, &printinterval)) 2261 printf("Approaching the limit on PV entries, consider " 2262 "increasing either the vm.pmap.shpgperproc or the " 2263 "vm.pmap.pv_entry_max tunable.\n"); 2264 pq = NULL; 2265retry: 2266 pc = TAILQ_FIRST(&pmap->pm_pvchunk); 2267 if (pc != NULL) { 2268 for (field = 0; field < _NPCM; field++) { 2269 if (pc->pc_map[field]) { 2270 bit = bsfl(pc->pc_map[field]); 2271 break; 2272 } 2273 } 2274 if (field < _NPCM) { 2275 pv = &pc->pc_pventry[field * 32 + bit]; 2276 pc->pc_map[field] &= ~(1ul << bit); 2277 /* If this was the last item, move it to tail */ 2278 for (field = 0; field < _NPCM; field++) 2279 if (pc->pc_map[field] != 0) { 2280 PV_STAT(pv_entry_spare--); 2281 return (pv); /* not full, return */ 2282 } 2283 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 2284 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list); 2285 PV_STAT(pv_entry_spare--); 2286 return (pv); 2287 } 2288 } 2289 /* 2290 * Access to the ptelist "pv_vafree" is synchronized by the page 2291 * queues lock. If "pv_vafree" is currently non-empty, it will 2292 * remain non-empty until pmap_ptelist_alloc() completes. 2293 */ 2294 if (pv_vafree == 0 || (m = vm_page_alloc(NULL, colour, (pq == 2295 &vm_page_queues[PQ_ACTIVE] ? VM_ALLOC_SYSTEM : VM_ALLOC_NORMAL) | 2296 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) { 2297 if (try) { 2298 pv_entry_count--; 2299 PV_STAT(pc_chunk_tryfail++); 2300 return (NULL); 2301 } 2302 /* 2303 * Reclaim pv entries: At first, destroy mappings to 2304 * inactive pages. After that, if a pv chunk entry 2305 * is still needed, destroy mappings to active pages. 2306 */ 2307 if (pq == NULL) { 2308 PV_STAT(pmap_collect_inactive++); 2309 pq = &vm_page_queues[PQ_INACTIVE]; 2310 } else if (pq == &vm_page_queues[PQ_INACTIVE]) { 2311 PV_STAT(pmap_collect_active++); 2312 pq = &vm_page_queues[PQ_ACTIVE]; 2313 } else 2314 panic("get_pv_entry: increase vm.pmap.shpgperproc"); 2315 pmap_collect(pmap, pq); 2316 goto retry; 2317 } 2318 PV_STAT(pc_chunk_count++); 2319 PV_STAT(pc_chunk_allocs++); 2320 colour++; 2321 pc = (struct pv_chunk *)pmap_ptelist_alloc(&pv_vafree); 2322 pmap_qenter((vm_offset_t)pc, &m, 1); 2323 pc->pc_pmap = pmap; 2324 pc->pc_map[0] = pc_freemask[0] & ~1ul; /* preallocated bit 0 */ 2325 for (field = 1; field < _NPCM; field++) 2326 pc->pc_map[field] = pc_freemask[field]; 2327 pv = &pc->pc_pventry[0]; 2328 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list); 2329 PV_STAT(pv_entry_spare += _NPCPV - 1); 2330 return (pv); 2331} 2332 2333static __inline pv_entry_t 2334pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va) 2335{ 2336 pv_entry_t pv; 2337 2338 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2339 TAILQ_FOREACH(pv, &pvh->pv_list, pv_list) { 2340 if (pmap == PV_PMAP(pv) && va == pv->pv_va) { 2341 TAILQ_REMOVE(&pvh->pv_list, pv, pv_list); 2342 break; 2343 } 2344 } 2345 return (pv); 2346} 2347 2348static void 2349pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa) 2350{ 2351 struct md_page *pvh; 2352 pv_entry_t pv; 2353 vm_offset_t va_last; 2354 vm_page_t m; 2355 2356 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2357 KASSERT((pa & PDRMASK) == 0, 2358 ("pmap_pv_demote_pde: pa is not 4mpage aligned")); 2359 2360 /* 2361 * Transfer the 4mpage's pv entry for this mapping to the first 2362 * page's pv list. 2363 */ 2364 pvh = pa_to_pvh(pa); 2365 va = trunc_4mpage(va); 2366 pv = pmap_pvh_remove(pvh, pmap, va); 2367 KASSERT(pv != NULL, ("pmap_pv_demote_pde: pv not found")); 2368 m = PHYS_TO_VM_PAGE(pa); 2369 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list); 2370 /* Instantiate the remaining NPTEPG - 1 pv entries. */ 2371 va_last = va + NBPDR - PAGE_SIZE; 2372 do { 2373 m++; 2374 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 2375 ("pmap_pv_demote_pde: page %p is not managed", m)); 2376 va += PAGE_SIZE; 2377 pmap_insert_entry(pmap, va, m); 2378 } while (va < va_last); 2379} 2380 2381static void 2382pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa) 2383{ 2384 struct md_page *pvh; 2385 pv_entry_t pv; 2386 vm_offset_t va_last; 2387 vm_page_t m; 2388 2389 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2390 KASSERT((pa & PDRMASK) == 0, 2391 ("pmap_pv_promote_pde: pa is not 4mpage aligned")); 2392 2393 /* 2394 * Transfer the first page's pv entry for this mapping to the 2395 * 4mpage's pv list. Aside from avoiding the cost of a call 2396 * to get_pv_entry(), a transfer avoids the possibility that 2397 * get_pv_entry() calls pmap_collect() and that pmap_collect() 2398 * removes one of the mappings that is being promoted. 2399 */ 2400 m = PHYS_TO_VM_PAGE(pa); 2401 va = trunc_4mpage(va); 2402 pv = pmap_pvh_remove(&m->md, pmap, va); 2403 KASSERT(pv != NULL, ("pmap_pv_promote_pde: pv not found")); 2404 pvh = pa_to_pvh(pa); 2405 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_list); 2406 /* Free the remaining NPTEPG - 1 pv entries. */ 2407 va_last = va + NBPDR - PAGE_SIZE; 2408 do { 2409 m++; 2410 va += PAGE_SIZE; 2411 pmap_pvh_free(&m->md, pmap, va); 2412 } while (va < va_last); 2413} 2414 2415static void 2416pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va) 2417{ 2418 pv_entry_t pv; 2419 2420 pv = pmap_pvh_remove(pvh, pmap, va); 2421 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found")); 2422 free_pv_entry(pmap, pv); 2423} 2424 2425static void 2426pmap_remove_entry(pmap_t pmap, vm_page_t m, vm_offset_t va) 2427{ 2428 struct md_page *pvh; 2429 2430 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2431 pmap_pvh_free(&m->md, pmap, va); 2432 if (TAILQ_EMPTY(&m->md.pv_list)) { 2433 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 2434 if (TAILQ_EMPTY(&pvh->pv_list)) 2435 vm_page_flag_clear(m, PG_WRITEABLE); 2436 } 2437} 2438 2439/* 2440 * Create a pv entry for page at pa for 2441 * (pmap, va). 2442 */ 2443static void 2444pmap_insert_entry(pmap_t pmap, vm_offset_t va, vm_page_t m) 2445{ 2446 pv_entry_t pv; 2447 2448 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2449 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2450 pv = get_pv_entry(pmap, FALSE); 2451 pv->pv_va = va; 2452 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list); 2453} 2454 2455/* 2456 * Conditionally create a pv entry. 2457 */ 2458static boolean_t 2459pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m) 2460{ 2461 pv_entry_t pv; 2462 2463 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2464 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2465 if (pv_entry_count < pv_entry_high_water && 2466 (pv = get_pv_entry(pmap, TRUE)) != NULL) { 2467 pv->pv_va = va; 2468 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list); 2469 return (TRUE); 2470 } else 2471 return (FALSE); 2472} 2473 2474/* 2475 * Create the pv entries for each of the pages within a superpage. 2476 */ 2477static boolean_t 2478pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa) 2479{ 2480 struct md_page *pvh; 2481 pv_entry_t pv; 2482 2483 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2484 if (pv_entry_count < pv_entry_high_water && 2485 (pv = get_pv_entry(pmap, TRUE)) != NULL) { 2486 pv->pv_va = va; 2487 pvh = pa_to_pvh(pa); 2488 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_list); 2489 return (TRUE); 2490 } else 2491 return (FALSE); 2492} 2493 2494/* 2495 * Fills a page table page with mappings to consecutive physical pages. 2496 */ 2497static void 2498pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte) 2499{ 2500 pt_entry_t *pte; 2501 2502 for (pte = firstpte; pte < firstpte + NPTEPG; pte++) { 2503 *pte = newpte; 2504 newpte += PAGE_SIZE; 2505 } 2506} 2507 2508/* 2509 * Tries to demote a 2- or 4MB page mapping. If demotion fails, the 2510 * 2- or 4MB page mapping is invalidated. 2511 */ 2512static boolean_t 2513pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va) 2514{ 2515 pd_entry_t newpde, oldpde; 2516 pt_entry_t *firstpte, newpte; 2517 vm_paddr_t mptepa; 2518 vm_page_t free, mpte; 2519 2520 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2521 oldpde = *pde; 2522 KASSERT((oldpde & (PG_PS | PG_V)) == (PG_PS | PG_V), 2523 ("pmap_demote_pde: oldpde is missing PG_PS and/or PG_V")); 2524 mpte = pmap_lookup_pt_page(pmap, va); 2525 if (mpte != NULL) 2526 pmap_remove_pt_page(pmap, mpte); 2527 else { 2528 KASSERT((oldpde & PG_W) == 0, 2529 ("pmap_demote_pde: page table page for a wired mapping" 2530 " is missing")); 2531 2532 /* 2533 * Invalidate the 2- or 4MB page mapping and return 2534 * "failure" if the mapping was never accessed or the 2535 * allocation of the new page table page fails. 2536 */ 2537 if ((oldpde & PG_A) == 0 || (mpte = vm_page_alloc(NULL, 2538 va >> PDRSHIFT, VM_ALLOC_NOOBJ | VM_ALLOC_NORMAL | 2539 VM_ALLOC_WIRED)) == NULL) { 2540 free = NULL; 2541 pmap_remove_pde(pmap, pde, trunc_4mpage(va), &free); 2542 pmap_invalidate_page(pmap, trunc_4mpage(va)); 2543 pmap_free_zero_pages(free); 2544 CTR2(KTR_PMAP, "pmap_demote_pde: failure for va %#x" 2545 " in pmap %p", va, pmap); 2546 return (FALSE); 2547 } 2548 if (va < VM_MAXUSER_ADDRESS) 2549 pmap->pm_stats.resident_count++; 2550 } 2551 mptepa = VM_PAGE_TO_PHYS(mpte); 2552 2553 /* 2554 * If the page mapping is in the kernel's address space, then the 2555 * KPTmap can provide access to the page table page. Otherwise, 2556 * temporarily map the page table page (mpte) into the kernel's 2557 * address space at either PADDR1 or PADDR2. 2558 */ 2559 if (va >= KERNBASE) 2560 firstpte = &KPTmap[i386_btop(trunc_4mpage(va))]; 2561 else if (curthread->td_pinned > 0 && mtx_owned(&vm_page_queue_mtx)) { 2562 if ((*PMAP1 & PG_FRAME) != mptepa) { 2563 *PMAP1 = mptepa | PG_RW | PG_V | PG_A | PG_M; 2564#ifdef SMP 2565 PMAP1cpu = PCPU_GET(cpuid); 2566#endif 2567 invlcaddr(PADDR1); 2568 PMAP1changed++; 2569 } else 2570#ifdef SMP 2571 if (PMAP1cpu != PCPU_GET(cpuid)) { 2572 PMAP1cpu = PCPU_GET(cpuid); 2573 invlcaddr(PADDR1); 2574 PMAP1changedcpu++; 2575 } else 2576#endif 2577 PMAP1unchanged++; 2578 firstpte = PADDR1; 2579 } else { 2580 mtx_lock(&PMAP2mutex); 2581 if ((*PMAP2 & PG_FRAME) != mptepa) { 2582 *PMAP2 = mptepa | PG_RW | PG_V | PG_A | PG_M; 2583 pmap_invalidate_page(kernel_pmap, (vm_offset_t)PADDR2); 2584 } 2585 firstpte = PADDR2; 2586 } 2587 newpde = mptepa | PG_M | PG_A | (oldpde & PG_U) | PG_RW | PG_V; 2588 KASSERT((oldpde & PG_A) != 0, 2589 ("pmap_demote_pde: oldpde is missing PG_A")); 2590 KASSERT((oldpde & (PG_M | PG_RW)) != PG_RW, 2591 ("pmap_demote_pde: oldpde is missing PG_M")); 2592 newpte = oldpde & ~PG_PS; 2593 if ((newpte & PG_PDE_PAT) != 0) 2594 newpte ^= PG_PDE_PAT | PG_PTE_PAT; 2595 2596 /* 2597 * If the page table page is new, initialize it. 2598 */ 2599 if (mpte->wire_count == 1) { 2600 mpte->wire_count = NPTEPG; 2601 pmap_fill_ptp(firstpte, newpte); 2602 } 2603 KASSERT((*firstpte & PG_FRAME) == (newpte & PG_FRAME), 2604 ("pmap_demote_pde: firstpte and newpte map different physical" 2605 " addresses")); 2606 2607 /* 2608 * If the mapping has changed attributes, update the page table 2609 * entries. 2610 */ 2611 if ((*firstpte & PG_PTE_PROMOTE) != (newpte & PG_PTE_PROMOTE)) 2612 pmap_fill_ptp(firstpte, newpte); 2613 2614 /* 2615 * Demote the mapping. This pmap is locked. The old PDE has 2616 * PG_A set. If the old PDE has PG_RW set, it also has PG_M 2617 * set. Thus, there is no danger of a race with another 2618 * processor changing the setting of PG_A and/or PG_M between 2619 * the read above and the store below. 2620 */ 2621 if (workaround_erratum383) 2622 pmap_update_pde(pmap, va, pde, newpde); 2623 else if (pmap == kernel_pmap) 2624 pmap_kenter_pde(va, newpde); 2625 else 2626 pde_store(pde, newpde); 2627 if (firstpte == PADDR2) 2628 mtx_unlock(&PMAP2mutex); 2629 2630 /* 2631 * Invalidate the recursive mapping of the page table page. 2632 */ 2633 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va)); 2634 2635 /* 2636 * Demote the pv entry. This depends on the earlier demotion 2637 * of the mapping. Specifically, the (re)creation of a per- 2638 * page pv entry might trigger the execution of pmap_collect(), 2639 * which might reclaim a newly (re)created per-page pv entry 2640 * and destroy the associated mapping. In order to destroy 2641 * the mapping, the PDE must have already changed from mapping 2642 * the 2mpage to referencing the page table page. 2643 */ 2644 if ((oldpde & PG_MANAGED) != 0) 2645 pmap_pv_demote_pde(pmap, va, oldpde & PG_PS_FRAME); 2646 2647 pmap_pde_demotions++; 2648 CTR2(KTR_PMAP, "pmap_demote_pde: success for va %#x" 2649 " in pmap %p", va, pmap); 2650 return (TRUE); 2651} 2652 2653/* 2654 * pmap_remove_pde: do the things to unmap a superpage in a process 2655 */ 2656static void 2657pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva, 2658 vm_page_t *free) 2659{ 2660 struct md_page *pvh; 2661 pd_entry_t oldpde; 2662 vm_offset_t eva, va; 2663 vm_page_t m, mpte; 2664 2665 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2666 KASSERT((sva & PDRMASK) == 0, 2667 ("pmap_remove_pde: sva is not 4mpage aligned")); 2668 oldpde = pte_load_clear(pdq); 2669 if (oldpde & PG_W) 2670 pmap->pm_stats.wired_count -= NBPDR / PAGE_SIZE; 2671 2672 /* 2673 * Machines that don't support invlpg, also don't support 2674 * PG_G. 2675 */ 2676 if (oldpde & PG_G) 2677 pmap_invalidate_page(kernel_pmap, sva); 2678 pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE; 2679 if (oldpde & PG_MANAGED) { 2680 pvh = pa_to_pvh(oldpde & PG_PS_FRAME); 2681 pmap_pvh_free(pvh, pmap, sva); 2682 eva = sva + NBPDR; 2683 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME); 2684 va < eva; va += PAGE_SIZE, m++) { 2685 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW)) 2686 vm_page_dirty(m); 2687 if (oldpde & PG_A) 2688 vm_page_flag_set(m, PG_REFERENCED); 2689 if (TAILQ_EMPTY(&m->md.pv_list) && 2690 TAILQ_EMPTY(&pvh->pv_list)) 2691 vm_page_flag_clear(m, PG_WRITEABLE); 2692 } 2693 } 2694 if (pmap == kernel_pmap) { 2695 if (!pmap_demote_pde(pmap, pdq, sva)) 2696 panic("pmap_remove_pde: failed demotion"); 2697 } else { 2698 mpte = pmap_lookup_pt_page(pmap, sva); 2699 if (mpte != NULL) { 2700 pmap_remove_pt_page(pmap, mpte); 2701 pmap->pm_stats.resident_count--; 2702 KASSERT(mpte->wire_count == NPTEPG, 2703 ("pmap_remove_pde: pte page wire count error")); 2704 mpte->wire_count = 0; 2705 pmap_add_delayed_free_list(mpte, free, FALSE); 2706 atomic_subtract_int(&cnt.v_wire_count, 1); 2707 } 2708 } 2709} 2710 2711/* 2712 * pmap_remove_pte: do the things to unmap a page in a process 2713 */ 2714static int 2715pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t va, vm_page_t *free) 2716{ 2717 pt_entry_t oldpte; 2718 vm_page_t m; 2719 2720 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2721 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2722 oldpte = pte_load_clear(ptq); 2723 if (oldpte & PG_W) 2724 pmap->pm_stats.wired_count -= 1; 2725 /* 2726 * Machines that don't support invlpg, also don't support 2727 * PG_G. 2728 */ 2729 if (oldpte & PG_G) 2730 pmap_invalidate_page(kernel_pmap, va); 2731 pmap->pm_stats.resident_count -= 1; 2732 if (oldpte & PG_MANAGED) { 2733 m = PHYS_TO_VM_PAGE(oldpte & PG_FRAME); 2734 if ((oldpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) 2735 vm_page_dirty(m); 2736 if (oldpte & PG_A) 2737 vm_page_flag_set(m, PG_REFERENCED); 2738 pmap_remove_entry(pmap, m, va); 2739 } 2740 return (pmap_unuse_pt(pmap, va, free)); 2741} 2742 2743/* 2744 * Remove a single page from a process address space 2745 */ 2746static void 2747pmap_remove_page(pmap_t pmap, vm_offset_t va, vm_page_t *free) 2748{ 2749 pt_entry_t *pte; 2750 2751 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2752 KASSERT(curthread->td_pinned > 0, ("curthread not pinned")); 2753 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2754 if ((pte = pmap_pte_quick(pmap, va)) == NULL || *pte == 0) 2755 return; 2756 pmap_remove_pte(pmap, pte, va, free); 2757 pmap_invalidate_page(pmap, va); 2758} 2759 2760/* 2761 * Remove the given range of addresses from the specified map. 2762 * 2763 * It is assumed that the start and end are properly 2764 * rounded to the page size. 2765 */ 2766void 2767pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 2768{ 2769 vm_offset_t pdnxt; 2770 pd_entry_t ptpaddr; 2771 pt_entry_t *pte; 2772 vm_page_t free = NULL; 2773 int anyvalid; 2774 2775 /* 2776 * Perform an unsynchronized read. This is, however, safe. 2777 */ 2778 if (pmap->pm_stats.resident_count == 0) 2779 return; 2780 2781 anyvalid = 0; 2782 2783 vm_page_lock_queues(); 2784 sched_pin(); 2785 PMAP_LOCK(pmap); 2786 2787 /* 2788 * special handling of removing one page. a very 2789 * common operation and easy to short circuit some 2790 * code. 2791 */ 2792 if ((sva + PAGE_SIZE == eva) && 2793 ((pmap->pm_pdir[(sva >> PDRSHIFT)] & PG_PS) == 0)) { 2794 pmap_remove_page(pmap, sva, &free); 2795 goto out; 2796 } 2797 2798 for (; sva < eva; sva = pdnxt) { 2799 unsigned pdirindex; 2800 2801 /* 2802 * Calculate index for next page table. 2803 */ 2804 pdnxt = (sva + NBPDR) & ~PDRMASK; 2805 if (pdnxt < sva) 2806 pdnxt = eva; 2807 if (pmap->pm_stats.resident_count == 0) 2808 break; 2809 2810 pdirindex = sva >> PDRSHIFT; 2811 ptpaddr = pmap->pm_pdir[pdirindex]; 2812 2813 /* 2814 * Weed out invalid mappings. Note: we assume that the page 2815 * directory table is always allocated, and in kernel virtual. 2816 */ 2817 if (ptpaddr == 0) 2818 continue; 2819 2820 /* 2821 * Check for large page. 2822 */ 2823 if ((ptpaddr & PG_PS) != 0) { 2824 /* 2825 * Are we removing the entire large page? If not, 2826 * demote the mapping and fall through. 2827 */ 2828 if (sva + NBPDR == pdnxt && eva >= pdnxt) { 2829 /* 2830 * The TLB entry for a PG_G mapping is 2831 * invalidated by pmap_remove_pde(). 2832 */ 2833 if ((ptpaddr & PG_G) == 0) 2834 anyvalid = 1; 2835 pmap_remove_pde(pmap, 2836 &pmap->pm_pdir[pdirindex], sva, &free); 2837 continue; 2838 } else if (!pmap_demote_pde(pmap, 2839 &pmap->pm_pdir[pdirindex], sva)) { 2840 /* The large page mapping was destroyed. */ 2841 continue; 2842 } 2843 } 2844 2845 /* 2846 * Limit our scan to either the end of the va represented 2847 * by the current page table page, or to the end of the 2848 * range being removed. 2849 */ 2850 if (pdnxt > eva) 2851 pdnxt = eva; 2852 2853 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++, 2854 sva += PAGE_SIZE) { 2855 if (*pte == 0) 2856 continue; 2857 2858 /* 2859 * The TLB entry for a PG_G mapping is invalidated 2860 * by pmap_remove_pte(). 2861 */ 2862 if ((*pte & PG_G) == 0) 2863 anyvalid = 1; 2864 if (pmap_remove_pte(pmap, pte, sva, &free)) 2865 break; 2866 } 2867 } 2868out: 2869 sched_unpin(); 2870 if (anyvalid) 2871 pmap_invalidate_all(pmap); 2872 vm_page_unlock_queues(); 2873 PMAP_UNLOCK(pmap); 2874 pmap_free_zero_pages(free); 2875} 2876 2877/* 2878 * Routine: pmap_remove_all 2879 * Function: 2880 * Removes this physical page from 2881 * all physical maps in which it resides. 2882 * Reflects back modify bits to the pager. 2883 * 2884 * Notes: 2885 * Original versions of this routine were very 2886 * inefficient because they iteratively called 2887 * pmap_remove (slow...) 2888 */ 2889 2890void 2891pmap_remove_all(vm_page_t m) 2892{ 2893 struct md_page *pvh; 2894 pv_entry_t pv; 2895 pmap_t pmap; 2896 pt_entry_t *pte, tpte; 2897 pd_entry_t *pde; 2898 vm_offset_t va; 2899 vm_page_t free; 2900 2901 KASSERT((m->flags & PG_FICTITIOUS) == 0, 2902 ("pmap_remove_all: page %p is fictitious", m)); 2903 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2904 sched_pin(); 2905 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 2906 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) { 2907 va = pv->pv_va; 2908 pmap = PV_PMAP(pv); 2909 PMAP_LOCK(pmap); 2910 pde = pmap_pde(pmap, va); 2911 (void)pmap_demote_pde(pmap, pde, va); 2912 PMAP_UNLOCK(pmap); 2913 } 2914 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) { 2915 pmap = PV_PMAP(pv); 2916 PMAP_LOCK(pmap); 2917 pmap->pm_stats.resident_count--; 2918 pde = pmap_pde(pmap, pv->pv_va); 2919 KASSERT((*pde & PG_PS) == 0, ("pmap_remove_all: found" 2920 " a 4mpage in page %p's pv list", m)); 2921 pte = pmap_pte_quick(pmap, pv->pv_va); 2922 tpte = pte_load_clear(pte); 2923 if (tpte & PG_W) 2924 pmap->pm_stats.wired_count--; 2925 if (tpte & PG_A) 2926 vm_page_flag_set(m, PG_REFERENCED); 2927 2928 /* 2929 * Update the vm_page_t clean and reference bits. 2930 */ 2931 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) 2932 vm_page_dirty(m); 2933 free = NULL; 2934 pmap_unuse_pt(pmap, pv->pv_va, &free); 2935 pmap_invalidate_page(pmap, pv->pv_va); 2936 pmap_free_zero_pages(free); 2937 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list); 2938 free_pv_entry(pmap, pv); 2939 PMAP_UNLOCK(pmap); 2940 } 2941 vm_page_flag_clear(m, PG_WRITEABLE); 2942 sched_unpin(); 2943} 2944 2945/* 2946 * pmap_protect_pde: do the things to protect a 4mpage in a process 2947 */ 2948static boolean_t 2949pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva, vm_prot_t prot) 2950{ 2951 pd_entry_t newpde, oldpde; 2952 vm_offset_t eva, va; 2953 vm_page_t m; 2954 boolean_t anychanged; 2955 2956 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2957 KASSERT((sva & PDRMASK) == 0, 2958 ("pmap_protect_pde: sva is not 4mpage aligned")); 2959 anychanged = FALSE; 2960retry: 2961 oldpde = newpde = *pde; 2962 if (oldpde & PG_MANAGED) { 2963 eva = sva + NBPDR; 2964 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME); 2965 va < eva; va += PAGE_SIZE, m++) 2966 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW)) 2967 vm_page_dirty(m); 2968 } 2969 if ((prot & VM_PROT_WRITE) == 0) 2970 newpde &= ~(PG_RW | PG_M); 2971#ifdef PAE 2972 if ((prot & VM_PROT_EXECUTE) == 0) 2973 newpde |= pg_nx; 2974#endif 2975 if (newpde != oldpde) { 2976 if (!pde_cmpset(pde, oldpde, newpde)) 2977 goto retry; 2978 if (oldpde & PG_G) 2979 pmap_invalidate_page(pmap, sva); 2980 else 2981 anychanged = TRUE; 2982 } 2983 return (anychanged); 2984} 2985 2986/* 2987 * Set the physical protection on the 2988 * specified range of this map as requested. 2989 */ 2990void 2991pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot) 2992{ 2993 vm_offset_t pdnxt; 2994 pd_entry_t ptpaddr; 2995 pt_entry_t *pte; 2996 int anychanged; 2997 2998 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 2999 pmap_remove(pmap, sva, eva); 3000 return; 3001 } 3002 3003#ifdef PAE 3004 if ((prot & (VM_PROT_WRITE|VM_PROT_EXECUTE)) == 3005 (VM_PROT_WRITE|VM_PROT_EXECUTE)) 3006 return; 3007#else 3008 if (prot & VM_PROT_WRITE) 3009 return; 3010#endif 3011 3012 anychanged = 0; 3013 3014 vm_page_lock_queues(); 3015 sched_pin(); 3016 PMAP_LOCK(pmap); 3017 for (; sva < eva; sva = pdnxt) { 3018 pt_entry_t obits, pbits; 3019 unsigned pdirindex; 3020 3021 pdnxt = (sva + NBPDR) & ~PDRMASK; 3022 if (pdnxt < sva) 3023 pdnxt = eva; 3024 3025 pdirindex = sva >> PDRSHIFT; 3026 ptpaddr = pmap->pm_pdir[pdirindex]; 3027 3028 /* 3029 * Weed out invalid mappings. Note: we assume that the page 3030 * directory table is always allocated, and in kernel virtual. 3031 */ 3032 if (ptpaddr == 0) 3033 continue; 3034 3035 /* 3036 * Check for large page. 3037 */ 3038 if ((ptpaddr & PG_PS) != 0) { 3039 /* 3040 * Are we protecting the entire large page? If not, 3041 * demote the mapping and fall through. 3042 */ 3043 if (sva + NBPDR == pdnxt && eva >= pdnxt) { 3044 /* 3045 * The TLB entry for a PG_G mapping is 3046 * invalidated by pmap_protect_pde(). 3047 */ 3048 if (pmap_protect_pde(pmap, 3049 &pmap->pm_pdir[pdirindex], sva, prot)) 3050 anychanged = 1; 3051 continue; 3052 } else if (!pmap_demote_pde(pmap, 3053 &pmap->pm_pdir[pdirindex], sva)) { 3054 /* The large page mapping was destroyed. */ 3055 continue; 3056 } 3057 } 3058 3059 if (pdnxt > eva) 3060 pdnxt = eva; 3061 3062 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++, 3063 sva += PAGE_SIZE) { 3064 vm_page_t m; 3065 3066retry: 3067 /* 3068 * Regardless of whether a pte is 32 or 64 bits in 3069 * size, PG_RW, PG_A, and PG_M are among the least 3070 * significant 32 bits. 3071 */ 3072 obits = pbits = *pte; 3073 if ((pbits & PG_V) == 0) 3074 continue; 3075 3076 if ((prot & VM_PROT_WRITE) == 0) { 3077 if ((pbits & (PG_MANAGED | PG_M | PG_RW)) == 3078 (PG_MANAGED | PG_M | PG_RW)) { 3079 m = PHYS_TO_VM_PAGE(pbits & PG_FRAME); 3080 vm_page_dirty(m); 3081 } 3082 pbits &= ~(PG_RW | PG_M); 3083 } 3084#ifdef PAE 3085 if ((prot & VM_PROT_EXECUTE) == 0) 3086 pbits |= pg_nx; 3087#endif 3088 3089 if (pbits != obits) { 3090#ifdef PAE 3091 if (!atomic_cmpset_64(pte, obits, pbits)) 3092 goto retry; 3093#else 3094 if (!atomic_cmpset_int((u_int *)pte, obits, 3095 pbits)) 3096 goto retry; 3097#endif 3098 if (obits & PG_G) 3099 pmap_invalidate_page(pmap, sva); 3100 else 3101 anychanged = 1; 3102 } 3103 } 3104 } 3105 sched_unpin(); 3106 if (anychanged) 3107 pmap_invalidate_all(pmap); 3108 vm_page_unlock_queues(); 3109 PMAP_UNLOCK(pmap); 3110} 3111 3112/* 3113 * Tries to promote the 512 or 1024, contiguous 4KB page mappings that are 3114 * within a single page table page (PTP) to a single 2- or 4MB page mapping. 3115 * For promotion to occur, two conditions must be met: (1) the 4KB page 3116 * mappings must map aligned, contiguous physical memory and (2) the 4KB page 3117 * mappings must have identical characteristics. 3118 * 3119 * Managed (PG_MANAGED) mappings within the kernel address space are not 3120 * promoted. The reason is that kernel PDEs are replicated in each pmap but 3121 * pmap_clear_ptes() and pmap_ts_referenced() only read the PDE from the kernel 3122 * pmap. 3123 */ 3124static void 3125pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va) 3126{ 3127 pd_entry_t newpde; 3128 pt_entry_t *firstpte, oldpte, pa, *pte; 3129 vm_offset_t oldpteva; 3130 vm_page_t mpte; 3131 3132 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 3133 3134 /* 3135 * Examine the first PTE in the specified PTP. Abort if this PTE is 3136 * either invalid, unused, or does not map the first 4KB physical page 3137 * within a 2- or 4MB page. 3138 */ 3139 firstpte = pmap_pte_quick(pmap, trunc_4mpage(va)); 3140setpde: 3141 newpde = *firstpte; 3142 if ((newpde & ((PG_FRAME & PDRMASK) | PG_A | PG_V)) != (PG_A | PG_V)) { 3143 pmap_pde_p_failures++; 3144 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x" 3145 " in pmap %p", va, pmap); 3146 return; 3147 } 3148 if ((*firstpte & PG_MANAGED) != 0 && pmap == kernel_pmap) { 3149 pmap_pde_p_failures++; 3150 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x" 3151 " in pmap %p", va, pmap); 3152 return; 3153 } 3154 if ((newpde & (PG_M | PG_RW)) == PG_RW) { 3155 /* 3156 * When PG_M is already clear, PG_RW can be cleared without 3157 * a TLB invalidation. 3158 */ 3159 if (!atomic_cmpset_int((u_int *)firstpte, newpde, newpde & 3160 ~PG_RW)) 3161 goto setpde; 3162 newpde &= ~PG_RW; 3163 } 3164 3165 /* 3166 * Examine each of the other PTEs in the specified PTP. Abort if this 3167 * PTE maps an unexpected 4KB physical page or does not have identical 3168 * characteristics to the first PTE. 3169 */ 3170 pa = (newpde & (PG_PS_FRAME | PG_A | PG_V)) + NBPDR - PAGE_SIZE; 3171 for (pte = firstpte + NPTEPG - 1; pte > firstpte; pte--) { 3172setpte: 3173 oldpte = *pte; 3174 if ((oldpte & (PG_FRAME | PG_A | PG_V)) != pa) { 3175 pmap_pde_p_failures++; 3176 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x" 3177 " in pmap %p", va, pmap); 3178 return; 3179 } 3180 if ((oldpte & (PG_M | PG_RW)) == PG_RW) { 3181 /* 3182 * When PG_M is already clear, PG_RW can be cleared 3183 * without a TLB invalidation. 3184 */ 3185 if (!atomic_cmpset_int((u_int *)pte, oldpte, 3186 oldpte & ~PG_RW)) 3187 goto setpte; 3188 oldpte &= ~PG_RW; 3189 oldpteva = (oldpte & PG_FRAME & PDRMASK) | 3190 (va & ~PDRMASK); 3191 CTR2(KTR_PMAP, "pmap_promote_pde: protect for va %#x" 3192 " in pmap %p", oldpteva, pmap); 3193 } 3194 if ((oldpte & PG_PTE_PROMOTE) != (newpde & PG_PTE_PROMOTE)) { 3195 pmap_pde_p_failures++; 3196 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x" 3197 " in pmap %p", va, pmap); 3198 return; 3199 } 3200 pa -= PAGE_SIZE; 3201 } 3202 3203 /* 3204 * Save the page table page in its current state until the PDE 3205 * mapping the superpage is demoted by pmap_demote_pde() or 3206 * destroyed by pmap_remove_pde(). 3207 */ 3208 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME); 3209 KASSERT(mpte >= vm_page_array && 3210 mpte < &vm_page_array[vm_page_array_size], 3211 ("pmap_promote_pde: page table page is out of range")); 3212 KASSERT(mpte->pindex == va >> PDRSHIFT, 3213 ("pmap_promote_pde: page table page's pindex is wrong")); 3214 pmap_insert_pt_page(pmap, mpte); 3215 3216 /* 3217 * Promote the pv entries. 3218 */ 3219 if ((newpde & PG_MANAGED) != 0) 3220 pmap_pv_promote_pde(pmap, va, newpde & PG_PS_FRAME); 3221 3222 /* 3223 * Propagate the PAT index to its proper position. 3224 */ 3225 if ((newpde & PG_PTE_PAT) != 0) 3226 newpde ^= PG_PDE_PAT | PG_PTE_PAT; 3227 3228 /* 3229 * Map the superpage. 3230 */ 3231 if (workaround_erratum383) 3232 pmap_update_pde(pmap, va, pde, PG_PS | newpde); 3233 else if (pmap == kernel_pmap) 3234 pmap_kenter_pde(va, PG_PS | newpde); 3235 else 3236 pde_store(pde, PG_PS | newpde); 3237 3238 pmap_pde_promotions++; 3239 CTR2(KTR_PMAP, "pmap_promote_pde: success for va %#x" 3240 " in pmap %p", va, pmap); 3241} 3242 3243/* 3244 * Insert the given physical page (p) at 3245 * the specified virtual address (v) in the 3246 * target physical map with the protection requested. 3247 * 3248 * If specified, the page will be wired down, meaning 3249 * that the related pte can not be reclaimed. 3250 * 3251 * NB: This is the only routine which MAY NOT lazy-evaluate 3252 * or lose information. That is, this routine must actually 3253 * insert this page into the given map NOW. 3254 */ 3255void 3256pmap_enter(pmap_t pmap, vm_offset_t va, vm_prot_t access, vm_page_t m, 3257 vm_prot_t prot, boolean_t wired) 3258{ 3259 vm_paddr_t pa; 3260 pd_entry_t *pde; 3261 pt_entry_t *pte; 3262 vm_paddr_t opa; 3263 pt_entry_t origpte, newpte; 3264 vm_page_t mpte, om; 3265 boolean_t invlva; 3266 3267 va = trunc_page(va); 3268 KASSERT(va <= VM_MAX_KERNEL_ADDRESS, ("pmap_enter: toobig")); 3269 KASSERT(va < UPT_MIN_ADDRESS || va >= UPT_MAX_ADDRESS, 3270 ("pmap_enter: invalid to pmap_enter page table pages (va: 0x%x)", va)); 3271 3272 mpte = NULL; 3273 3274 vm_page_lock_queues(); 3275 PMAP_LOCK(pmap); 3276 sched_pin(); 3277 3278 /* 3279 * In the case that a page table page is not 3280 * resident, we are creating it here. 3281 */ 3282 if (va < VM_MAXUSER_ADDRESS) { 3283 mpte = pmap_allocpte(pmap, va, M_WAITOK); 3284 } 3285 3286 pde = pmap_pde(pmap, va); 3287 if ((*pde & PG_PS) != 0) 3288 panic("pmap_enter: attempted pmap_enter on 4MB page"); 3289 pte = pmap_pte_quick(pmap, va); 3290 3291 /* 3292 * Page Directory table entry not valid, we need a new PT page 3293 */ 3294 if (pte == NULL) { 3295 panic("pmap_enter: invalid page directory pdir=%#jx, va=%#x", 3296 (uintmax_t)pmap->pm_pdir[PTDPTDI], va); 3297 } 3298 3299 pa = VM_PAGE_TO_PHYS(m); 3300 om = NULL; 3301 origpte = *pte; 3302 opa = origpte & PG_FRAME; 3303 3304 /* 3305 * Mapping has not changed, must be protection or wiring change. 3306 */ 3307 if (origpte && (opa == pa)) { 3308 /* 3309 * Wiring change, just update stats. We don't worry about 3310 * wiring PT pages as they remain resident as long as there 3311 * are valid mappings in them. Hence, if a user page is wired, 3312 * the PT page will be also. 3313 */ 3314 if (wired && ((origpte & PG_W) == 0)) 3315 pmap->pm_stats.wired_count++; 3316 else if (!wired && (origpte & PG_W)) 3317 pmap->pm_stats.wired_count--; 3318 3319 /* 3320 * Remove extra pte reference 3321 */ 3322 if (mpte) 3323 mpte->wire_count--; 3324 3325 /* 3326 * We might be turning off write access to the page, 3327 * so we go ahead and sense modify status. 3328 */ 3329 if (origpte & PG_MANAGED) { 3330 om = m; 3331 pa |= PG_MANAGED; 3332 } 3333 goto validate; 3334 } 3335 /* 3336 * Mapping has changed, invalidate old range and fall through to 3337 * handle validating new mapping. 3338 */ 3339 if (opa) { 3340 if (origpte & PG_W) 3341 pmap->pm_stats.wired_count--; 3342 if (origpte & PG_MANAGED) { 3343 om = PHYS_TO_VM_PAGE(opa); 3344 pmap_remove_entry(pmap, om, va); 3345 } 3346 if (mpte != NULL) { 3347 mpte->wire_count--; 3348 KASSERT(mpte->wire_count > 0, 3349 ("pmap_enter: missing reference to page table page," 3350 " va: 0x%x", va)); 3351 } 3352 } else 3353 pmap->pm_stats.resident_count++; 3354 3355 /* 3356 * Enter on the PV list if part of our managed memory. 3357 */ 3358 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0) { 3359 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva, 3360 ("pmap_enter: managed mapping within the clean submap")); 3361 pmap_insert_entry(pmap, va, m); 3362 pa |= PG_MANAGED; 3363 } 3364 3365 /* 3366 * Increment counters 3367 */ 3368 if (wired) 3369 pmap->pm_stats.wired_count++; 3370 3371validate: 3372 /* 3373 * Now validate mapping with desired protection/wiring. 3374 */ 3375 newpte = (pt_entry_t)(pa | pmap_cache_bits(m->md.pat_mode, 0) | PG_V); 3376 if ((prot & VM_PROT_WRITE) != 0) { 3377 newpte |= PG_RW; 3378 vm_page_flag_set(m, PG_WRITEABLE); 3379 } 3380#ifdef PAE 3381 if ((prot & VM_PROT_EXECUTE) == 0) 3382 newpte |= pg_nx; 3383#endif 3384 if (wired) 3385 newpte |= PG_W; 3386 if (va < VM_MAXUSER_ADDRESS) 3387 newpte |= PG_U; 3388 if (pmap == kernel_pmap) 3389 newpte |= pgeflag; 3390 3391 /* 3392 * if the mapping or permission bits are different, we need 3393 * to update the pte. 3394 */ 3395 if ((origpte & ~(PG_M|PG_A)) != newpte) { 3396 newpte |= PG_A; 3397 if ((access & VM_PROT_WRITE) != 0) 3398 newpte |= PG_M; 3399 if (origpte & PG_V) { 3400 invlva = FALSE; 3401 origpte = pte_load_store(pte, newpte); 3402 if (origpte & PG_A) { 3403 if (origpte & PG_MANAGED) 3404 vm_page_flag_set(om, PG_REFERENCED); 3405 if (opa != VM_PAGE_TO_PHYS(m)) 3406 invlva = TRUE; 3407#ifdef PAE 3408 if ((origpte & PG_NX) == 0 && 3409 (newpte & PG_NX) != 0) 3410 invlva = TRUE; 3411#endif 3412 } 3413 if ((origpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) { 3414 if ((origpte & PG_MANAGED) != 0) 3415 vm_page_dirty(om); 3416 if ((prot & VM_PROT_WRITE) == 0) 3417 invlva = TRUE; 3418 } 3419 if (invlva) 3420 pmap_invalidate_page(pmap, va); 3421 } else 3422 pte_store(pte, newpte); 3423 } 3424 3425 /* 3426 * If both the page table page and the reservation are fully 3427 * populated, then attempt promotion. 3428 */ 3429 if ((mpte == NULL || mpte->wire_count == NPTEPG) && 3430 pg_ps_enabled && vm_reserv_level_iffullpop(m) == 0) 3431 pmap_promote_pde(pmap, pde, va); 3432 3433 sched_unpin(); 3434 vm_page_unlock_queues(); 3435 PMAP_UNLOCK(pmap); 3436} 3437 3438/* 3439 * Tries to create a 2- or 4MB page mapping. Returns TRUE if successful and 3440 * FALSE otherwise. Fails if (1) a page table page cannot be allocated without 3441 * blocking, (2) a mapping already exists at the specified virtual address, or 3442 * (3) a pv entry cannot be allocated without reclaiming another pv entry. 3443 */ 3444static boolean_t 3445pmap_enter_pde(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot) 3446{ 3447 pd_entry_t *pde, newpde; 3448 3449 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 3450 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 3451 pde = pmap_pde(pmap, va); 3452 if (*pde != 0) { 3453 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx" 3454 " in pmap %p", va, pmap); 3455 return (FALSE); 3456 } 3457 newpde = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(m->md.pat_mode, 1) | 3458 PG_PS | PG_V; 3459 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0) { 3460 newpde |= PG_MANAGED; 3461 3462 /* 3463 * Abort this mapping if its PV entry could not be created. 3464 */ 3465 if (!pmap_pv_insert_pde(pmap, va, VM_PAGE_TO_PHYS(m))) { 3466 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx" 3467 " in pmap %p", va, pmap); 3468 return (FALSE); 3469 } 3470 } 3471#ifdef PAE 3472 if ((prot & VM_PROT_EXECUTE) == 0) 3473 newpde |= pg_nx; 3474#endif 3475 if (va < VM_MAXUSER_ADDRESS) 3476 newpde |= PG_U; 3477 3478 /* 3479 * Increment counters. 3480 */ 3481 pmap->pm_stats.resident_count += NBPDR / PAGE_SIZE; 3482 3483 /* 3484 * Map the superpage. 3485 */ 3486 pde_store(pde, newpde); 3487 3488 pmap_pde_mappings++; 3489 CTR2(KTR_PMAP, "pmap_enter_pde: success for va %#lx" 3490 " in pmap %p", va, pmap); 3491 return (TRUE); 3492} 3493 3494/* 3495 * Maps a sequence of resident pages belonging to the same object. 3496 * The sequence begins with the given page m_start. This page is 3497 * mapped at the given virtual address start. Each subsequent page is 3498 * mapped at a virtual address that is offset from start by the same 3499 * amount as the page is offset from m_start within the object. The 3500 * last page in the sequence is the page with the largest offset from 3501 * m_start that can be mapped at a virtual address less than the given 3502 * virtual address end. Not every virtual page between start and end 3503 * is mapped; only those for which a resident page exists with the 3504 * corresponding offset from m_start are mapped. 3505 */ 3506void 3507pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end, 3508 vm_page_t m_start, vm_prot_t prot) 3509{ 3510 vm_offset_t va; 3511 vm_page_t m, mpte; 3512 vm_pindex_t diff, psize; 3513 3514 VM_OBJECT_LOCK_ASSERT(m_start->object, MA_OWNED); 3515 psize = atop(end - start); 3516 mpte = NULL; 3517 m = m_start; 3518 PMAP_LOCK(pmap); 3519 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 3520 va = start + ptoa(diff); 3521 if ((va & PDRMASK) == 0 && va + NBPDR <= end && 3522 (VM_PAGE_TO_PHYS(m) & PDRMASK) == 0 && 3523 pg_ps_enabled && vm_reserv_level_iffullpop(m) == 0 && 3524 pmap_enter_pde(pmap, va, m, prot)) 3525 m = &m[NBPDR / PAGE_SIZE - 1]; 3526 else 3527 mpte = pmap_enter_quick_locked(pmap, va, m, prot, 3528 mpte); 3529 m = TAILQ_NEXT(m, listq); 3530 } 3531 PMAP_UNLOCK(pmap); 3532} 3533 3534/* 3535 * this code makes some *MAJOR* assumptions: 3536 * 1. Current pmap & pmap exists. 3537 * 2. Not wired. 3538 * 3. Read access. 3539 * 4. No page table pages. 3540 * but is *MUCH* faster than pmap_enter... 3541 */ 3542 3543void 3544pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot) 3545{ 3546 3547 PMAP_LOCK(pmap); 3548 (void) pmap_enter_quick_locked(pmap, va, m, prot, NULL); 3549 PMAP_UNLOCK(pmap); 3550} 3551 3552static vm_page_t 3553pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m, 3554 vm_prot_t prot, vm_page_t mpte) 3555{ 3556 pt_entry_t *pte; 3557 vm_paddr_t pa; 3558 vm_page_t free; 3559 3560 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva || 3561 (m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0, 3562 ("pmap_enter_quick_locked: managed mapping within the clean submap")); 3563 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 3564 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 3565 3566 /* 3567 * In the case that a page table page is not 3568 * resident, we are creating it here. 3569 */ 3570 if (va < VM_MAXUSER_ADDRESS) { 3571 unsigned ptepindex; 3572 pd_entry_t ptepa; 3573 3574 /* 3575 * Calculate pagetable page index 3576 */ 3577 ptepindex = va >> PDRSHIFT; 3578 if (mpte && (mpte->pindex == ptepindex)) { 3579 mpte->wire_count++; 3580 } else { 3581 /* 3582 * Get the page directory entry 3583 */ 3584 ptepa = pmap->pm_pdir[ptepindex]; 3585 3586 /* 3587 * If the page table page is mapped, we just increment 3588 * the hold count, and activate it. 3589 */ 3590 if (ptepa) { 3591 if (ptepa & PG_PS) 3592 return (NULL); 3593 mpte = PHYS_TO_VM_PAGE(ptepa & PG_FRAME); 3594 mpte->wire_count++; 3595 } else { 3596 mpte = _pmap_allocpte(pmap, ptepindex, 3597 M_NOWAIT); 3598 if (mpte == NULL) 3599 return (mpte); 3600 } 3601 } 3602 } else { 3603 mpte = NULL; 3604 } 3605 3606 /* 3607 * This call to vtopte makes the assumption that we are 3608 * entering the page into the current pmap. In order to support 3609 * quick entry into any pmap, one would likely use pmap_pte_quick. 3610 * But that isn't as quick as vtopte. 3611 */ 3612 pte = vtopte(va); 3613 if (*pte) { 3614 if (mpte != NULL) { 3615 mpte->wire_count--; 3616 mpte = NULL; 3617 } 3618 return (mpte); 3619 } 3620 3621 /* 3622 * Enter on the PV list if part of our managed memory. 3623 */ 3624 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0 && 3625 !pmap_try_insert_pv_entry(pmap, va, m)) { 3626 if (mpte != NULL) { 3627 free = NULL; 3628 if (pmap_unwire_pte_hold(pmap, mpte, &free)) { 3629 pmap_invalidate_page(pmap, va); 3630 pmap_free_zero_pages(free); 3631 } 3632 3633 mpte = NULL; 3634 } 3635 return (mpte); 3636 } 3637 3638 /* 3639 * Increment counters 3640 */ 3641 pmap->pm_stats.resident_count++; 3642 3643 pa = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(m->md.pat_mode, 0); 3644#ifdef PAE 3645 if ((prot & VM_PROT_EXECUTE) == 0) 3646 pa |= pg_nx; 3647#endif 3648 3649 /* 3650 * Now validate mapping with RO protection 3651 */ 3652 if (m->flags & (PG_FICTITIOUS|PG_UNMANAGED)) 3653 pte_store(pte, pa | PG_V | PG_U); 3654 else 3655 pte_store(pte, pa | PG_V | PG_U | PG_MANAGED); 3656 return (mpte); 3657} 3658 3659/* 3660 * Make a temporary mapping for a physical address. This is only intended 3661 * to be used for panic dumps. 3662 */ 3663void * 3664pmap_kenter_temporary(vm_paddr_t pa, int i) 3665{ 3666 vm_offset_t va; 3667 3668 va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE); 3669 pmap_kenter(va, pa); 3670 invlpg(va); 3671 return ((void *)crashdumpmap); 3672} 3673 3674/* 3675 * This code maps large physical mmap regions into the 3676 * processor address space. Note that some shortcuts 3677 * are taken, but the code works. 3678 */ 3679void 3680pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object, 3681 vm_pindex_t pindex, vm_size_t size) 3682{ 3683 pd_entry_t *pde; 3684 vm_paddr_t pa, ptepa; 3685 vm_page_t p; 3686 int pat_mode; 3687 3688 VM_OBJECT_LOCK_ASSERT(object, MA_OWNED); 3689 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG, 3690 ("pmap_object_init_pt: non-device object")); 3691 if (pseflag && 3692 (addr & (NBPDR - 1)) == 0 && (size & (NBPDR - 1)) == 0) { 3693 if (!vm_object_populate(object, pindex, pindex + atop(size))) 3694 return; 3695 p = vm_page_lookup(object, pindex); 3696 KASSERT(p->valid == VM_PAGE_BITS_ALL, 3697 ("pmap_object_init_pt: invalid page %p", p)); 3698 pat_mode = p->md.pat_mode; 3699 3700 /* 3701 * Abort the mapping if the first page is not physically 3702 * aligned to a 2/4MB page boundary. 3703 */ 3704 ptepa = VM_PAGE_TO_PHYS(p); 3705 if (ptepa & (NBPDR - 1)) 3706 return; 3707 3708 /* 3709 * Skip the first page. Abort the mapping if the rest of 3710 * the pages are not physically contiguous or have differing 3711 * memory attributes. 3712 */ 3713 p = TAILQ_NEXT(p, listq); 3714 for (pa = ptepa + PAGE_SIZE; pa < ptepa + size; 3715 pa += PAGE_SIZE) { 3716 KASSERT(p->valid == VM_PAGE_BITS_ALL, 3717 ("pmap_object_init_pt: invalid page %p", p)); 3718 if (pa != VM_PAGE_TO_PHYS(p) || 3719 pat_mode != p->md.pat_mode) 3720 return; 3721 p = TAILQ_NEXT(p, listq); 3722 } 3723 3724 /* 3725 * Map using 2/4MB pages. Since "ptepa" is 2/4M aligned and 3726 * "size" is a multiple of 2/4M, adding the PAT setting to 3727 * "pa" will not affect the termination of this loop. 3728 */ 3729 PMAP_LOCK(pmap); 3730 for (pa = ptepa | pmap_cache_bits(pat_mode, 1); pa < ptepa + 3731 size; pa += NBPDR) { 3732 pde = pmap_pde(pmap, addr); 3733 if (*pde == 0) { 3734 pde_store(pde, pa | PG_PS | PG_M | PG_A | 3735 PG_U | PG_RW | PG_V); 3736 pmap->pm_stats.resident_count += NBPDR / 3737 PAGE_SIZE; 3738 pmap_pde_mappings++; 3739 } 3740 /* Else continue on if the PDE is already valid. */ 3741 addr += NBPDR; 3742 } 3743 PMAP_UNLOCK(pmap); 3744 } 3745} 3746 3747/* 3748 * Routine: pmap_change_wiring 3749 * Function: Change the wiring attribute for a map/virtual-address 3750 * pair. 3751 * In/out conditions: 3752 * The mapping must already exist in the pmap. 3753 */ 3754void 3755pmap_change_wiring(pmap_t pmap, vm_offset_t va, boolean_t wired) 3756{ 3757 pd_entry_t *pde; 3758 pt_entry_t *pte; 3759 boolean_t are_queues_locked; 3760 3761 are_queues_locked = FALSE; 3762retry: 3763 PMAP_LOCK(pmap); 3764 pde = pmap_pde(pmap, va); 3765 if ((*pde & PG_PS) != 0) { 3766 if (!wired != ((*pde & PG_W) == 0)) { 3767 if (!are_queues_locked) { 3768 are_queues_locked = TRUE; 3769 if (!mtx_trylock(&vm_page_queue_mtx)) { 3770 PMAP_UNLOCK(pmap); 3771 vm_page_lock_queues(); 3772 goto retry; 3773 } 3774 } 3775 if (!pmap_demote_pde(pmap, pde, va)) 3776 panic("pmap_change_wiring: demotion failed"); 3777 } else 3778 goto out; 3779 } 3780 pte = pmap_pte(pmap, va); 3781 3782 if (wired && !pmap_pte_w(pte)) 3783 pmap->pm_stats.wired_count++; 3784 else if (!wired && pmap_pte_w(pte)) 3785 pmap->pm_stats.wired_count--; 3786 3787 /* 3788 * Wiring is not a hardware characteristic so there is no need to 3789 * invalidate TLB. 3790 */ 3791 pmap_pte_set_w(pte, wired); 3792 pmap_pte_release(pte); 3793out: 3794 if (are_queues_locked) 3795 vm_page_unlock_queues(); 3796 PMAP_UNLOCK(pmap); 3797} 3798 3799 3800 3801/* 3802 * Copy the range specified by src_addr/len 3803 * from the source map to the range dst_addr/len 3804 * in the destination map. 3805 * 3806 * This routine is only advisory and need not do anything. 3807 */ 3808 3809void 3810pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len, 3811 vm_offset_t src_addr) 3812{ 3813 vm_page_t free; 3814 vm_offset_t addr; 3815 vm_offset_t end_addr = src_addr + len; 3816 vm_offset_t pdnxt; 3817 3818 if (dst_addr != src_addr) 3819 return; 3820 3821 if (!pmap_is_current(src_pmap)) 3822 return; 3823 3824 vm_page_lock_queues(); 3825 if (dst_pmap < src_pmap) { 3826 PMAP_LOCK(dst_pmap); 3827 PMAP_LOCK(src_pmap); 3828 } else { 3829 PMAP_LOCK(src_pmap); 3830 PMAP_LOCK(dst_pmap); 3831 } 3832 sched_pin(); 3833 for (addr = src_addr; addr < end_addr; addr = pdnxt) { 3834 pt_entry_t *src_pte, *dst_pte; 3835 vm_page_t dstmpte, srcmpte; 3836 pd_entry_t srcptepaddr; 3837 unsigned ptepindex; 3838 3839 KASSERT(addr < UPT_MIN_ADDRESS, 3840 ("pmap_copy: invalid to pmap_copy page tables")); 3841 3842 pdnxt = (addr + NBPDR) & ~PDRMASK; 3843 if (pdnxt < addr) 3844 pdnxt = end_addr; 3845 ptepindex = addr >> PDRSHIFT; 3846 3847 srcptepaddr = src_pmap->pm_pdir[ptepindex]; 3848 if (srcptepaddr == 0) 3849 continue; 3850 3851 if (srcptepaddr & PG_PS) { 3852 if (dst_pmap->pm_pdir[ptepindex] == 0 && 3853 ((srcptepaddr & PG_MANAGED) == 0 || 3854 pmap_pv_insert_pde(dst_pmap, addr, srcptepaddr & 3855 PG_PS_FRAME))) { 3856 dst_pmap->pm_pdir[ptepindex] = srcptepaddr & 3857 ~PG_W; 3858 dst_pmap->pm_stats.resident_count += 3859 NBPDR / PAGE_SIZE; 3860 } 3861 continue; 3862 } 3863 3864 srcmpte = PHYS_TO_VM_PAGE(srcptepaddr & PG_FRAME); 3865 KASSERT(srcmpte->wire_count > 0, 3866 ("pmap_copy: source page table page is unused")); 3867 3868 if (pdnxt > end_addr) 3869 pdnxt = end_addr; 3870 3871 src_pte = vtopte(addr); 3872 while (addr < pdnxt) { 3873 pt_entry_t ptetemp; 3874 ptetemp = *src_pte; 3875 /* 3876 * we only virtual copy managed pages 3877 */ 3878 if ((ptetemp & PG_MANAGED) != 0) { 3879 dstmpte = pmap_allocpte(dst_pmap, addr, 3880 M_NOWAIT); 3881 if (dstmpte == NULL) 3882 goto out; 3883 dst_pte = pmap_pte_quick(dst_pmap, addr); 3884 if (*dst_pte == 0 && 3885 pmap_try_insert_pv_entry(dst_pmap, addr, 3886 PHYS_TO_VM_PAGE(ptetemp & PG_FRAME))) { 3887 /* 3888 * Clear the wired, modified, and 3889 * accessed (referenced) bits 3890 * during the copy. 3891 */ 3892 *dst_pte = ptetemp & ~(PG_W | PG_M | 3893 PG_A); 3894 dst_pmap->pm_stats.resident_count++; 3895 } else { 3896 free = NULL; 3897 if (pmap_unwire_pte_hold(dst_pmap, 3898 dstmpte, &free)) { 3899 pmap_invalidate_page(dst_pmap, 3900 addr); 3901 pmap_free_zero_pages(free); 3902 } 3903 goto out; 3904 } 3905 if (dstmpte->wire_count >= srcmpte->wire_count) 3906 break; 3907 } 3908 addr += PAGE_SIZE; 3909 src_pte++; 3910 } 3911 } 3912out: 3913 sched_unpin(); 3914 vm_page_unlock_queues(); 3915 PMAP_UNLOCK(src_pmap); 3916 PMAP_UNLOCK(dst_pmap); 3917} 3918 3919static __inline void 3920pagezero(void *page) 3921{ 3922#if defined(I686_CPU) 3923 if (cpu_class == CPUCLASS_686) { 3924#if defined(CPU_ENABLE_SSE) 3925 if (cpu_feature & CPUID_SSE2) 3926 sse2_pagezero(page); 3927 else 3928#endif 3929 i686_pagezero(page); 3930 } else 3931#endif 3932 bzero(page, PAGE_SIZE); 3933} 3934 3935/* 3936 * pmap_zero_page zeros the specified hardware page by mapping 3937 * the page into KVM and using bzero to clear its contents. 3938 */ 3939void 3940pmap_zero_page(vm_page_t m) 3941{ 3942 struct sysmaps *sysmaps; 3943 3944 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)]; 3945 mtx_lock(&sysmaps->lock); 3946 if (*sysmaps->CMAP2) 3947 panic("pmap_zero_page: CMAP2 busy"); 3948 sched_pin(); 3949 *sysmaps->CMAP2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M | 3950 pmap_cache_bits(m->md.pat_mode, 0); 3951 invlcaddr(sysmaps->CADDR2); 3952 pagezero(sysmaps->CADDR2); 3953 *sysmaps->CMAP2 = 0; 3954 sched_unpin(); 3955 mtx_unlock(&sysmaps->lock); 3956} 3957 3958/* 3959 * pmap_zero_page_area zeros the specified hardware page by mapping 3960 * the page into KVM and using bzero to clear its contents. 3961 * 3962 * off and size may not cover an area beyond a single hardware page. 3963 */ 3964void 3965pmap_zero_page_area(vm_page_t m, int off, int size) 3966{ 3967 struct sysmaps *sysmaps; 3968 3969 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)]; 3970 mtx_lock(&sysmaps->lock); 3971 if (*sysmaps->CMAP2) 3972 panic("pmap_zero_page_area: CMAP2 busy"); 3973 sched_pin(); 3974 *sysmaps->CMAP2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M | 3975 pmap_cache_bits(m->md.pat_mode, 0); 3976 invlcaddr(sysmaps->CADDR2); 3977 if (off == 0 && size == PAGE_SIZE) 3978 pagezero(sysmaps->CADDR2); 3979 else 3980 bzero((char *)sysmaps->CADDR2 + off, size); 3981 *sysmaps->CMAP2 = 0; 3982 sched_unpin(); 3983 mtx_unlock(&sysmaps->lock); 3984} 3985 3986/* 3987 * pmap_zero_page_idle zeros the specified hardware page by mapping 3988 * the page into KVM and using bzero to clear its contents. This 3989 * is intended to be called from the vm_pagezero process only and 3990 * outside of Giant. 3991 */ 3992void 3993pmap_zero_page_idle(vm_page_t m) 3994{ 3995 3996 if (*CMAP3) 3997 panic("pmap_zero_page_idle: CMAP3 busy"); 3998 sched_pin(); 3999 *CMAP3 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M | 4000 pmap_cache_bits(m->md.pat_mode, 0); 4001 invlcaddr(CADDR3); 4002 pagezero(CADDR3); 4003 *CMAP3 = 0; 4004 sched_unpin(); 4005} 4006 4007/* 4008 * pmap_copy_page copies the specified (machine independent) 4009 * page by mapping the page into virtual memory and using 4010 * bcopy to copy the page, one machine dependent page at a 4011 * time. 4012 */ 4013void 4014pmap_copy_page(vm_page_t src, vm_page_t dst) 4015{ 4016 struct sysmaps *sysmaps; 4017 4018 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)]; 4019 mtx_lock(&sysmaps->lock); 4020 if (*sysmaps->CMAP1) 4021 panic("pmap_copy_page: CMAP1 busy"); 4022 if (*sysmaps->CMAP2) 4023 panic("pmap_copy_page: CMAP2 busy"); 4024 sched_pin(); 4025 invlpg((u_int)sysmaps->CADDR1); 4026 invlpg((u_int)sysmaps->CADDR2); 4027 *sysmaps->CMAP1 = PG_V | VM_PAGE_TO_PHYS(src) | PG_A | 4028 pmap_cache_bits(src->md.pat_mode, 0); 4029 *sysmaps->CMAP2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(dst) | PG_A | PG_M | 4030 pmap_cache_bits(dst->md.pat_mode, 0); 4031 bcopy(sysmaps->CADDR1, sysmaps->CADDR2, PAGE_SIZE); 4032 *sysmaps->CMAP1 = 0; 4033 *sysmaps->CMAP2 = 0; 4034 sched_unpin(); 4035 mtx_unlock(&sysmaps->lock); 4036} 4037 4038/* 4039 * Returns true if the pmap's pv is one of the first 4040 * 16 pvs linked to from this page. This count may 4041 * be changed upwards or downwards in the future; it 4042 * is only necessary that true be returned for a small 4043 * subset of pmaps for proper page aging. 4044 */ 4045boolean_t 4046pmap_page_exists_quick(pmap_t pmap, vm_page_t m) 4047{ 4048 struct md_page *pvh; 4049 pv_entry_t pv; 4050 int loops = 0; 4051 4052 if (m->flags & PG_FICTITIOUS) 4053 return (FALSE); 4054 4055 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 4056 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 4057 if (PV_PMAP(pv) == pmap) { 4058 return (TRUE); 4059 } 4060 loops++; 4061 if (loops >= 16) 4062 break; 4063 } 4064 if (loops < 16) { 4065 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 4066 TAILQ_FOREACH(pv, &pvh->pv_list, pv_list) { 4067 if (PV_PMAP(pv) == pmap) 4068 return (TRUE); 4069 loops++; 4070 if (loops >= 16) 4071 break; 4072 } 4073 } 4074 return (FALSE); 4075} 4076 4077/* 4078 * pmap_page_wired_mappings: 4079 * 4080 * Return the number of managed mappings to the given physical page 4081 * that are wired. 4082 */ 4083int 4084pmap_page_wired_mappings(vm_page_t m) 4085{ 4086 int count; 4087 4088 count = 0; 4089 if ((m->flags & PG_FICTITIOUS) != 0) 4090 return (count); 4091 count = pmap_pvh_wired_mappings(&m->md, count); 4092 return (pmap_pvh_wired_mappings(pa_to_pvh(VM_PAGE_TO_PHYS(m)), count)); 4093} 4094 4095/* 4096 * pmap_pvh_wired_mappings: 4097 * 4098 * Return the updated number "count" of managed mappings that are wired. 4099 */ 4100static int 4101pmap_pvh_wired_mappings(struct md_page *pvh, int count) 4102{ 4103 pmap_t pmap; 4104 pt_entry_t *pte; 4105 pv_entry_t pv; 4106 4107 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 4108 sched_pin(); 4109 TAILQ_FOREACH(pv, &pvh->pv_list, pv_list) { 4110 pmap = PV_PMAP(pv); 4111 PMAP_LOCK(pmap); 4112 pte = pmap_pte_quick(pmap, pv->pv_va); 4113 if ((*pte & PG_W) != 0) 4114 count++; 4115 PMAP_UNLOCK(pmap); 4116 } 4117 sched_unpin(); 4118 return (count); 4119} 4120 4121/* 4122 * Returns TRUE if the given page is mapped individually or as part of 4123 * a 4mpage. Otherwise, returns FALSE. 4124 */ 4125boolean_t 4126pmap_page_is_mapped(vm_page_t m) 4127{ 4128 boolean_t rv; 4129 4130 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0) 4131 return (FALSE); 4132 vm_page_lock_queues(); 4133 rv = !TAILQ_EMPTY(&m->md.pv_list) || 4134 !TAILQ_EMPTY(&pa_to_pvh(VM_PAGE_TO_PHYS(m))->pv_list); 4135 vm_page_unlock_queues(); 4136 return (rv); 4137} 4138 4139/* 4140 * Remove all pages from specified address space 4141 * this aids process exit speeds. Also, this code 4142 * is special cased for current process only, but 4143 * can have the more generic (and slightly slower) 4144 * mode enabled. This is much faster than pmap_remove 4145 * in the case of running down an entire address space. 4146 */ 4147void 4148pmap_remove_pages(pmap_t pmap) 4149{ 4150 pt_entry_t *pte, tpte; 4151 vm_page_t free = NULL; 4152 vm_page_t m, mpte, mt; 4153 pv_entry_t pv; 4154 struct md_page *pvh; 4155 struct pv_chunk *pc, *npc; 4156 int field, idx; 4157 int32_t bit; 4158 uint32_t inuse, bitmask; 4159 int allfree; 4160 4161 if (pmap != vmspace_pmap(curthread->td_proc->p_vmspace)) { 4162 printf("warning: pmap_remove_pages called with non-current pmap\n"); 4163 return; 4164 } 4165 vm_page_lock_queues(); 4166 PMAP_LOCK(pmap); 4167 sched_pin(); 4168 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) { 4169 allfree = 1; 4170 for (field = 0; field < _NPCM; field++) { 4171 inuse = (~(pc->pc_map[field])) & pc_freemask[field]; 4172 while (inuse != 0) { 4173 bit = bsfl(inuse); 4174 bitmask = 1UL << bit; 4175 idx = field * 32 + bit; 4176 pv = &pc->pc_pventry[idx]; 4177 inuse &= ~bitmask; 4178 4179 pte = pmap_pde(pmap, pv->pv_va); 4180 tpte = *pte; 4181 if ((tpte & PG_PS) == 0) { 4182 pte = vtopte(pv->pv_va); 4183 tpte = *pte & ~PG_PTE_PAT; 4184 } 4185 4186 if (tpte == 0) { 4187 printf( 4188 "TPTE at %p IS ZERO @ VA %08x\n", 4189 pte, pv->pv_va); 4190 panic("bad pte"); 4191 } 4192 4193/* 4194 * We cannot remove wired pages from a process' mapping at this time 4195 */ 4196 if (tpte & PG_W) { 4197 allfree = 0; 4198 continue; 4199 } 4200 4201 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME); 4202 KASSERT(m->phys_addr == (tpte & PG_FRAME), 4203 ("vm_page_t %p phys_addr mismatch %016jx %016jx", 4204 m, (uintmax_t)m->phys_addr, 4205 (uintmax_t)tpte)); 4206 4207 KASSERT(m < &vm_page_array[vm_page_array_size], 4208 ("pmap_remove_pages: bad tpte %#jx", 4209 (uintmax_t)tpte)); 4210 4211 pte_clear(pte); 4212 4213 /* 4214 * Update the vm_page_t clean/reference bits. 4215 */ 4216 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) { 4217 if ((tpte & PG_PS) != 0) { 4218 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++) 4219 vm_page_dirty(mt); 4220 } else 4221 vm_page_dirty(m); 4222 } 4223 4224 /* Mark free */ 4225 PV_STAT(pv_entry_frees++); 4226 PV_STAT(pv_entry_spare++); 4227 pv_entry_count--; 4228 pc->pc_map[field] |= bitmask; 4229 if ((tpte & PG_PS) != 0) { 4230 pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE; 4231 pvh = pa_to_pvh(tpte & PG_PS_FRAME); 4232 TAILQ_REMOVE(&pvh->pv_list, pv, pv_list); 4233 if (TAILQ_EMPTY(&pvh->pv_list)) { 4234 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++) 4235 if (TAILQ_EMPTY(&mt->md.pv_list)) 4236 vm_page_flag_clear(mt, PG_WRITEABLE); 4237 } 4238 mpte = pmap_lookup_pt_page(pmap, pv->pv_va); 4239 if (mpte != NULL) { 4240 pmap_remove_pt_page(pmap, mpte); 4241 pmap->pm_stats.resident_count--; 4242 KASSERT(mpte->wire_count == NPTEPG, 4243 ("pmap_remove_pages: pte page wire count error")); 4244 mpte->wire_count = 0; 4245 pmap_add_delayed_free_list(mpte, &free, FALSE); 4246 atomic_subtract_int(&cnt.v_wire_count, 1); 4247 } 4248 } else { 4249 pmap->pm_stats.resident_count--; 4250 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list); 4251 if (TAILQ_EMPTY(&m->md.pv_list)) { 4252 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 4253 if (TAILQ_EMPTY(&pvh->pv_list)) 4254 vm_page_flag_clear(m, PG_WRITEABLE); 4255 } 4256 pmap_unuse_pt(pmap, pv->pv_va, &free); 4257 } 4258 } 4259 } 4260 if (allfree) { 4261 PV_STAT(pv_entry_spare -= _NPCPV); 4262 PV_STAT(pc_chunk_count--); 4263 PV_STAT(pc_chunk_frees++); 4264 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 4265 m = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc)); 4266 pmap_qremove((vm_offset_t)pc, 1); 4267 vm_page_unwire(m, 0); 4268 vm_page_free(m); 4269 pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc); 4270 } 4271 } 4272 sched_unpin(); 4273 pmap_invalidate_all(pmap); 4274 vm_page_unlock_queues(); 4275 PMAP_UNLOCK(pmap); 4276 pmap_free_zero_pages(free); 4277} 4278 4279/* 4280 * pmap_is_modified: 4281 * 4282 * Return whether or not the specified physical page was modified 4283 * in any physical maps. 4284 */ 4285boolean_t 4286pmap_is_modified(vm_page_t m) 4287{ 4288 4289 if (m->flags & PG_FICTITIOUS) 4290 return (FALSE); 4291 if (pmap_is_modified_pvh(&m->md)) 4292 return (TRUE); 4293 return (pmap_is_modified_pvh(pa_to_pvh(VM_PAGE_TO_PHYS(m)))); 4294} 4295 4296/* 4297 * Returns TRUE if any of the given mappings were used to modify 4298 * physical memory. Otherwise, returns FALSE. Both page and 2mpage 4299 * mappings are supported. 4300 */ 4301static boolean_t 4302pmap_is_modified_pvh(struct md_page *pvh) 4303{ 4304 pv_entry_t pv; 4305 pt_entry_t *pte; 4306 pmap_t pmap; 4307 boolean_t rv; 4308 4309 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 4310 rv = FALSE; 4311 sched_pin(); 4312 TAILQ_FOREACH(pv, &pvh->pv_list, pv_list) { 4313 pmap = PV_PMAP(pv); 4314 PMAP_LOCK(pmap); 4315 pte = pmap_pte_quick(pmap, pv->pv_va); 4316 rv = (*pte & (PG_M | PG_RW)) == (PG_M | PG_RW); 4317 PMAP_UNLOCK(pmap); 4318 if (rv) 4319 break; 4320 } 4321 sched_unpin(); 4322 return (rv); 4323} 4324 4325/* 4326 * pmap_is_prefaultable: 4327 * 4328 * Return whether or not the specified virtual address is elgible 4329 * for prefault. 4330 */ 4331boolean_t 4332pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr) 4333{ 4334 pd_entry_t *pde; 4335 pt_entry_t *pte; 4336 boolean_t rv; 4337 4338 rv = FALSE; 4339 PMAP_LOCK(pmap); 4340 pde = pmap_pde(pmap, addr); 4341 if (*pde != 0 && (*pde & PG_PS) == 0) { 4342 pte = vtopte(addr); 4343 rv = *pte == 0; 4344 } 4345 PMAP_UNLOCK(pmap); 4346 return (rv); 4347} 4348 4349/* 4350 * pmap_is_referenced: 4351 * 4352 * Return whether or not the specified physical page was referenced 4353 * in any physical maps. 4354 */ 4355boolean_t 4356pmap_is_referenced(vm_page_t m) 4357{ 4358 4359 if (m->flags & PG_FICTITIOUS) 4360 return (FALSE); 4361 if (pmap_is_referenced_pvh(&m->md)) 4362 return (TRUE); 4363 return (pmap_is_referenced_pvh(pa_to_pvh(VM_PAGE_TO_PHYS(m)))); 4364} 4365 4366/* 4367 * Returns TRUE if any of the given mappings were referenced and FALSE 4368 * otherwise. Both page and 4mpage mappings are supported. 4369 */ 4370static boolean_t 4371pmap_is_referenced_pvh(struct md_page *pvh) 4372{ 4373 pv_entry_t pv; 4374 pt_entry_t *pte; 4375 pmap_t pmap; 4376 boolean_t rv; 4377 4378 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 4379 rv = FALSE; 4380 sched_pin(); 4381 TAILQ_FOREACH(pv, &pvh->pv_list, pv_list) { 4382 pmap = PV_PMAP(pv); 4383 PMAP_LOCK(pmap); 4384 pte = pmap_pte_quick(pmap, pv->pv_va); 4385 rv = (*pte & (PG_A | PG_V)) == (PG_A | PG_V); 4386 PMAP_UNLOCK(pmap); 4387 if (rv) 4388 break; 4389 } 4390 sched_unpin(); 4391 return (rv); 4392} 4393 4394/* 4395 * Clear the write and modified bits in each of the given page's mappings. 4396 */ 4397void 4398pmap_remove_write(vm_page_t m) 4399{ 4400 struct md_page *pvh; 4401 pv_entry_t next_pv, pv; 4402 pmap_t pmap; 4403 pd_entry_t *pde; 4404 pt_entry_t oldpte, *pte; 4405 vm_offset_t va; 4406 4407 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 4408 if ((m->flags & PG_FICTITIOUS) != 0 || 4409 (m->flags & PG_WRITEABLE) == 0) 4410 return; 4411 sched_pin(); 4412 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 4413 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_list, next_pv) { 4414 va = pv->pv_va; 4415 pmap = PV_PMAP(pv); 4416 PMAP_LOCK(pmap); 4417 pde = pmap_pde(pmap, va); 4418 if ((*pde & PG_RW) != 0) 4419 (void)pmap_demote_pde(pmap, pde, va); 4420 PMAP_UNLOCK(pmap); 4421 } 4422 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 4423 pmap = PV_PMAP(pv); 4424 PMAP_LOCK(pmap); 4425 pde = pmap_pde(pmap, pv->pv_va); 4426 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_write: found" 4427 " a 4mpage in page %p's pv list", m)); 4428 pte = pmap_pte_quick(pmap, pv->pv_va); 4429retry: 4430 oldpte = *pte; 4431 if ((oldpte & PG_RW) != 0) { 4432 /* 4433 * Regardless of whether a pte is 32 or 64 bits 4434 * in size, PG_RW and PG_M are among the least 4435 * significant 32 bits. 4436 */ 4437 if (!atomic_cmpset_int((u_int *)pte, oldpte, 4438 oldpte & ~(PG_RW | PG_M))) 4439 goto retry; 4440 if ((oldpte & PG_M) != 0) 4441 vm_page_dirty(m); 4442 pmap_invalidate_page(pmap, pv->pv_va); 4443 } 4444 PMAP_UNLOCK(pmap); 4445 } 4446 vm_page_flag_clear(m, PG_WRITEABLE); 4447 sched_unpin(); 4448} 4449 4450/* 4451 * pmap_ts_referenced: 4452 * 4453 * Return a count of reference bits for a page, clearing those bits. 4454 * It is not necessary for every reference bit to be cleared, but it 4455 * is necessary that 0 only be returned when there are truly no 4456 * reference bits set. 4457 * 4458 * XXX: The exact number of bits to check and clear is a matter that 4459 * should be tested and standardized at some point in the future for 4460 * optimal aging of shared pages. 4461 */ 4462int 4463pmap_ts_referenced(vm_page_t m) 4464{ 4465 struct md_page *pvh; 4466 pv_entry_t pv, pvf, pvn; 4467 pmap_t pmap; 4468 pd_entry_t oldpde, *pde; 4469 pt_entry_t *pte; 4470 vm_offset_t va; 4471 int rtval = 0; 4472 4473 if (m->flags & PG_FICTITIOUS) 4474 return (rtval); 4475 sched_pin(); 4476 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 4477 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 4478 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_list, pvn) { 4479 va = pv->pv_va; 4480 pmap = PV_PMAP(pv); 4481 PMAP_LOCK(pmap); 4482 pde = pmap_pde(pmap, va); 4483 oldpde = *pde; 4484 if ((oldpde & PG_A) != 0) { 4485 if (pmap_demote_pde(pmap, pde, va)) { 4486 if ((oldpde & PG_W) == 0) { 4487 /* 4488 * Remove the mapping to a single page 4489 * so that a subsequent access may 4490 * repromote. Since the underlying 4491 * page table page is fully populated, 4492 * this removal never frees a page 4493 * table page. 4494 */ 4495 va += VM_PAGE_TO_PHYS(m) - (oldpde & 4496 PG_PS_FRAME); 4497 pmap_remove_page(pmap, va, NULL); 4498 rtval++; 4499 if (rtval > 4) { 4500 PMAP_UNLOCK(pmap); 4501 return (rtval); 4502 } 4503 } 4504 } 4505 } 4506 PMAP_UNLOCK(pmap); 4507 } 4508 if ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) { 4509 pvf = pv; 4510 do { 4511 pvn = TAILQ_NEXT(pv, pv_list); 4512 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list); 4513 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list); 4514 pmap = PV_PMAP(pv); 4515 PMAP_LOCK(pmap); 4516 pde = pmap_pde(pmap, pv->pv_va); 4517 KASSERT((*pde & PG_PS) == 0, ("pmap_ts_referenced:" 4518 " found a 4mpage in page %p's pv list", m)); 4519 pte = pmap_pte_quick(pmap, pv->pv_va); 4520 if ((*pte & PG_A) != 0) { 4521 atomic_clear_int((u_int *)pte, PG_A); 4522 pmap_invalidate_page(pmap, pv->pv_va); 4523 rtval++; 4524 if (rtval > 4) 4525 pvn = NULL; 4526 } 4527 PMAP_UNLOCK(pmap); 4528 } while ((pv = pvn) != NULL && pv != pvf); 4529 } 4530 sched_unpin(); 4531 return (rtval); 4532} 4533 4534/* 4535 * Clear the modify bits on the specified physical page. 4536 */ 4537void 4538pmap_clear_modify(vm_page_t m) 4539{ 4540 struct md_page *pvh; 4541 pv_entry_t next_pv, pv; 4542 pmap_t pmap; 4543 pd_entry_t oldpde, *pde; 4544 pt_entry_t oldpte, *pte; 4545 vm_offset_t va; 4546 4547 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 4548 if ((m->flags & PG_FICTITIOUS) != 0) 4549 return; 4550 sched_pin(); 4551 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 4552 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_list, next_pv) { 4553 va = pv->pv_va; 4554 pmap = PV_PMAP(pv); 4555 PMAP_LOCK(pmap); 4556 pde = pmap_pde(pmap, va); 4557 oldpde = *pde; 4558 if ((oldpde & PG_RW) != 0) { 4559 if (pmap_demote_pde(pmap, pde, va)) { 4560 if ((oldpde & PG_W) == 0) { 4561 /* 4562 * Write protect the mapping to a 4563 * single page so that a subsequent 4564 * write access may repromote. 4565 */ 4566 va += VM_PAGE_TO_PHYS(m) - (oldpde & 4567 PG_PS_FRAME); 4568 pte = pmap_pte_quick(pmap, va); 4569 oldpte = *pte; 4570 if ((oldpte & PG_V) != 0) { 4571 /* 4572 * Regardless of whether a pte is 32 or 64 bits 4573 * in size, PG_RW and PG_M are among the least 4574 * significant 32 bits. 4575 */ 4576 while (!atomic_cmpset_int((u_int *)pte, 4577 oldpte, 4578 oldpte & ~(PG_M | PG_RW))) 4579 oldpte = *pte; 4580 vm_page_dirty(m); 4581 pmap_invalidate_page(pmap, va); 4582 } 4583 } 4584 } 4585 } 4586 PMAP_UNLOCK(pmap); 4587 } 4588 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 4589 pmap = PV_PMAP(pv); 4590 PMAP_LOCK(pmap); 4591 pde = pmap_pde(pmap, pv->pv_va); 4592 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_modify: found" 4593 " a 4mpage in page %p's pv list", m)); 4594 pte = pmap_pte_quick(pmap, pv->pv_va); 4595 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) { 4596 /* 4597 * Regardless of whether a pte is 32 or 64 bits 4598 * in size, PG_M is among the least significant 4599 * 32 bits. 4600 */ 4601 atomic_clear_int((u_int *)pte, PG_M); 4602 pmap_invalidate_page(pmap, pv->pv_va); 4603 } 4604 PMAP_UNLOCK(pmap); 4605 } 4606 sched_unpin(); 4607} 4608 4609/* 4610 * pmap_clear_reference: 4611 * 4612 * Clear the reference bit on the specified physical page. 4613 */ 4614void 4615pmap_clear_reference(vm_page_t m) 4616{ 4617 struct md_page *pvh; 4618 pv_entry_t next_pv, pv; 4619 pmap_t pmap; 4620 pd_entry_t oldpde, *pde; 4621 pt_entry_t *pte; 4622 vm_offset_t va; 4623 4624 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 4625 if ((m->flags & PG_FICTITIOUS) != 0) 4626 return; 4627 sched_pin(); 4628 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 4629 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_list, next_pv) { 4630 va = pv->pv_va; 4631 pmap = PV_PMAP(pv); 4632 PMAP_LOCK(pmap); 4633 pde = pmap_pde(pmap, va); 4634 oldpde = *pde; 4635 if ((oldpde & PG_A) != 0) { 4636 if (pmap_demote_pde(pmap, pde, va)) { 4637 /* 4638 * Remove the mapping to a single page so 4639 * that a subsequent access may repromote. 4640 * Since the underlying page table page is 4641 * fully populated, this removal never frees 4642 * a page table page. 4643 */ 4644 va += VM_PAGE_TO_PHYS(m) - (oldpde & 4645 PG_PS_FRAME); 4646 pmap_remove_page(pmap, va, NULL); 4647 } 4648 } 4649 PMAP_UNLOCK(pmap); 4650 } 4651 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 4652 pmap = PV_PMAP(pv); 4653 PMAP_LOCK(pmap); 4654 pde = pmap_pde(pmap, pv->pv_va); 4655 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_reference: found" 4656 " a 4mpage in page %p's pv list", m)); 4657 pte = pmap_pte_quick(pmap, pv->pv_va); 4658 if ((*pte & PG_A) != 0) { 4659 /* 4660 * Regardless of whether a pte is 32 or 64 bits 4661 * in size, PG_A is among the least significant 4662 * 32 bits. 4663 */ 4664 atomic_clear_int((u_int *)pte, PG_A); 4665 pmap_invalidate_page(pmap, pv->pv_va); 4666 } 4667 PMAP_UNLOCK(pmap); 4668 } 4669 sched_unpin(); 4670} 4671 4672/* 4673 * Miscellaneous support routines follow 4674 */ 4675 4676/* Adjust the cache mode for a 4KB page mapped via a PTE. */ 4677static __inline void 4678pmap_pte_attr(pt_entry_t *pte, int cache_bits) 4679{ 4680 u_int opte, npte; 4681 4682 /* 4683 * The cache mode bits are all in the low 32-bits of the 4684 * PTE, so we can just spin on updating the low 32-bits. 4685 */ 4686 do { 4687 opte = *(u_int *)pte; 4688 npte = opte & ~PG_PTE_CACHE; 4689 npte |= cache_bits; 4690 } while (npte != opte && !atomic_cmpset_int((u_int *)pte, opte, npte)); 4691} 4692 4693/* Adjust the cache mode for a 2/4MB page mapped via a PDE. */ 4694static __inline void 4695pmap_pde_attr(pd_entry_t *pde, int cache_bits) 4696{ 4697 u_int opde, npde; 4698 4699 /* 4700 * The cache mode bits are all in the low 32-bits of the 4701 * PDE, so we can just spin on updating the low 32-bits. 4702 */ 4703 do { 4704 opde = *(u_int *)pde; 4705 npde = opde & ~PG_PDE_CACHE; 4706 npde |= cache_bits; 4707 } while (npde != opde && !atomic_cmpset_int((u_int *)pde, opde, npde)); 4708} 4709 4710/* 4711 * Map a set of physical memory pages into the kernel virtual 4712 * address space. Return a pointer to where it is mapped. This 4713 * routine is intended to be used for mapping device memory, 4714 * NOT real memory. 4715 */ 4716void * 4717pmap_mapdev_attr(vm_paddr_t pa, vm_size_t size, int mode) 4718{ 4719 vm_offset_t va, offset; 4720 vm_size_t tmpsize; 4721 4722 offset = pa & PAGE_MASK; 4723 size = roundup(offset + size, PAGE_SIZE); 4724 pa = pa & PG_FRAME; 4725 4726 if (pa < KERNLOAD && pa + size <= KERNLOAD) 4727 va = KERNBASE + pa; 4728 else 4729 va = kmem_alloc_nofault(kernel_map, size); 4730 if (!va) 4731 panic("pmap_mapdev: Couldn't alloc kernel virtual memory"); 4732 4733 for (tmpsize = 0; tmpsize < size; tmpsize += PAGE_SIZE) 4734 pmap_kenter_attr(va + tmpsize, pa + tmpsize, mode); 4735 pmap_invalidate_range(kernel_pmap, va, va + tmpsize); 4736 pmap_invalidate_cache_range(va, va + size); 4737 return ((void *)(va + offset)); 4738} 4739 4740void * 4741pmap_mapdev(vm_paddr_t pa, vm_size_t size) 4742{ 4743 4744 return (pmap_mapdev_attr(pa, size, PAT_UNCACHEABLE)); 4745} 4746 4747void * 4748pmap_mapbios(vm_paddr_t pa, vm_size_t size) 4749{ 4750 4751 return (pmap_mapdev_attr(pa, size, PAT_WRITE_BACK)); 4752} 4753 4754void 4755pmap_unmapdev(vm_offset_t va, vm_size_t size) 4756{ 4757 vm_offset_t base, offset, tmpva; 4758 4759 if (va >= KERNBASE && va + size <= KERNBASE + KERNLOAD) 4760 return; 4761 base = trunc_page(va); 4762 offset = va & PAGE_MASK; 4763 size = roundup(offset + size, PAGE_SIZE); 4764 for (tmpva = base; tmpva < (base + size); tmpva += PAGE_SIZE) 4765 pmap_kremove(tmpva); 4766 pmap_invalidate_range(kernel_pmap, va, tmpva); 4767 kmem_free(kernel_map, base, size); 4768} 4769 4770/* 4771 * Sets the memory attribute for the specified page. 4772 */ 4773void 4774pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma) 4775{ 4776 struct sysmaps *sysmaps; 4777 vm_offset_t sva, eva; 4778 4779 m->md.pat_mode = ma; 4780 if ((m->flags & PG_FICTITIOUS) != 0) 4781 return; 4782 4783 /* 4784 * If "m" is a normal page, flush it from the cache. 4785 * See pmap_invalidate_cache_range(). 4786 * 4787 * First, try to find an existing mapping of the page by sf 4788 * buffer. sf_buf_invalidate_cache() modifies mapping and 4789 * flushes the cache. 4790 */ 4791 if (sf_buf_invalidate_cache(m)) 4792 return; 4793 4794 /* 4795 * If page is not mapped by sf buffer, but CPU does not 4796 * support self snoop, map the page transient and do 4797 * invalidation. In the worst case, whole cache is flushed by 4798 * pmap_invalidate_cache_range(). 4799 */ 4800 if ((cpu_feature & (CPUID_SS|CPUID_CLFSH)) == CPUID_CLFSH) { 4801 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)]; 4802 mtx_lock(&sysmaps->lock); 4803 if (*sysmaps->CMAP2) 4804 panic("pmap_page_set_memattr: CMAP2 busy"); 4805 sched_pin(); 4806 *sysmaps->CMAP2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | 4807 PG_A | PG_M | pmap_cache_bits(m->md.pat_mode, 0); 4808 invlcaddr(sysmaps->CADDR2); 4809 sva = (vm_offset_t)sysmaps->CADDR2; 4810 eva = sva + PAGE_SIZE; 4811 } else 4812 sva = eva = 0; /* gcc */ 4813 pmap_invalidate_cache_range(sva, eva); 4814 if (sva != 0) { 4815 *sysmaps->CMAP2 = 0; 4816 sched_unpin(); 4817 mtx_unlock(&sysmaps->lock); 4818 } 4819} 4820 4821/* 4822 * Changes the specified virtual address range's memory type to that given by 4823 * the parameter "mode". The specified virtual address range must be 4824 * completely contained within either the kernel map. 4825 * 4826 * Returns zero if the change completed successfully, and either EINVAL or 4827 * ENOMEM if the change failed. Specifically, EINVAL is returned if some part 4828 * of the virtual address range was not mapped, and ENOMEM is returned if 4829 * there was insufficient memory available to complete the change. 4830 */ 4831int 4832pmap_change_attr(vm_offset_t va, vm_size_t size, int mode) 4833{ 4834 vm_offset_t base, offset, tmpva; 4835 pd_entry_t *pde; 4836 pt_entry_t *pte; 4837 int cache_bits_pte, cache_bits_pde; 4838 boolean_t changed; 4839 4840 base = trunc_page(va); 4841 offset = va & PAGE_MASK; 4842 size = roundup(offset + size, PAGE_SIZE); 4843 4844 /* 4845 * Only supported on kernel virtual addresses above the recursive map. 4846 */ 4847 if (base < VM_MIN_KERNEL_ADDRESS) 4848 return (EINVAL); 4849 4850 cache_bits_pde = pmap_cache_bits(mode, 1); 4851 cache_bits_pte = pmap_cache_bits(mode, 0); 4852 changed = FALSE; 4853 4854 /* 4855 * Pages that aren't mapped aren't supported. Also break down 4856 * 2/4MB pages into 4KB pages if required. 4857 */ 4858 PMAP_LOCK(kernel_pmap); 4859 for (tmpva = base; tmpva < base + size; ) { 4860 pde = pmap_pde(kernel_pmap, tmpva); 4861 if (*pde == 0) { 4862 PMAP_UNLOCK(kernel_pmap); 4863 return (EINVAL); 4864 } 4865 if (*pde & PG_PS) { 4866 /* 4867 * If the current 2/4MB page already has 4868 * the required memory type, then we need not 4869 * demote this page. Just increment tmpva to 4870 * the next 2/4MB page frame. 4871 */ 4872 if ((*pde & PG_PDE_CACHE) == cache_bits_pde) { 4873 tmpva = trunc_4mpage(tmpva) + NBPDR; 4874 continue; 4875 } 4876 4877 /* 4878 * If the current offset aligns with a 2/4MB 4879 * page frame and there is at least 2/4MB left 4880 * within the range, then we need not break 4881 * down this page into 4KB pages. 4882 */ 4883 if ((tmpva & PDRMASK) == 0 && 4884 tmpva + PDRMASK < base + size) { 4885 tmpva += NBPDR; 4886 continue; 4887 } 4888 if (!pmap_demote_pde(kernel_pmap, pde, tmpva)) { 4889 PMAP_UNLOCK(kernel_pmap); 4890 return (ENOMEM); 4891 } 4892 } 4893 pte = vtopte(tmpva); 4894 if (*pte == 0) { 4895 PMAP_UNLOCK(kernel_pmap); 4896 return (EINVAL); 4897 } 4898 tmpva += PAGE_SIZE; 4899 } 4900 PMAP_UNLOCK(kernel_pmap); 4901 4902 /* 4903 * Ok, all the pages exist, so run through them updating their 4904 * cache mode if required. 4905 */ 4906 for (tmpva = base; tmpva < base + size; ) { 4907 pde = pmap_pde(kernel_pmap, tmpva); 4908 if (*pde & PG_PS) { 4909 if ((*pde & PG_PDE_CACHE) != cache_bits_pde) { 4910 pmap_pde_attr(pde, cache_bits_pde); 4911 changed = TRUE; 4912 } 4913 tmpva = trunc_4mpage(tmpva) + NBPDR; 4914 } else { 4915 pte = vtopte(tmpva); 4916 if ((*pte & PG_PTE_CACHE) != cache_bits_pte) { 4917 pmap_pte_attr(pte, cache_bits_pte); 4918 changed = TRUE; 4919 } 4920 tmpva += PAGE_SIZE; 4921 } 4922 } 4923 4924 /* 4925 * Flush CPU caches to make sure any data isn't cached that 4926 * shouldn't be, etc. 4927 */ 4928 if (changed) { 4929 pmap_invalidate_range(kernel_pmap, base, tmpva); 4930 pmap_invalidate_cache_range(base, tmpva); 4931 } 4932 return (0); 4933} 4934 4935/* 4936 * perform the pmap work for mincore 4937 */ 4938int 4939pmap_mincore(pmap_t pmap, vm_offset_t addr) 4940{ 4941 pd_entry_t *pdep; 4942 pt_entry_t *ptep, pte; 4943 vm_paddr_t pa; 4944 vm_page_t m; 4945 int val = 0; 4946 4947 PMAP_LOCK(pmap); 4948 pdep = pmap_pde(pmap, addr); 4949 if (*pdep != 0) { 4950 if (*pdep & PG_PS) { 4951 pte = *pdep; 4952 val = MINCORE_SUPER; 4953 /* Compute the physical address of the 4KB page. */ 4954 pa = ((*pdep & PG_PS_FRAME) | (addr & PDRMASK)) & 4955 PG_FRAME; 4956 } else { 4957 ptep = pmap_pte(pmap, addr); 4958 pte = *ptep; 4959 pmap_pte_release(ptep); 4960 pa = pte & PG_FRAME; 4961 } 4962 } else { 4963 pte = 0; 4964 pa = 0; 4965 } 4966 PMAP_UNLOCK(pmap); 4967 4968 if (pte != 0) { 4969 val |= MINCORE_INCORE; 4970 if ((pte & PG_MANAGED) == 0) 4971 return (val); 4972 4973 m = PHYS_TO_VM_PAGE(pa); 4974 4975 /* 4976 * Modified by us 4977 */ 4978 if ((pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) 4979 val |= MINCORE_MODIFIED|MINCORE_MODIFIED_OTHER; 4980 else { 4981 /* 4982 * Modified by someone else 4983 */ 4984 vm_page_lock_queues(); 4985 if (m->dirty || pmap_is_modified(m)) 4986 val |= MINCORE_MODIFIED_OTHER; 4987 vm_page_unlock_queues(); 4988 } 4989 /* 4990 * Referenced by us 4991 */ 4992 if (pte & PG_A) 4993 val |= MINCORE_REFERENCED|MINCORE_REFERENCED_OTHER; 4994 else { 4995 /* 4996 * Referenced by someone else 4997 */ 4998 vm_page_lock_queues(); 4999 if ((m->flags & PG_REFERENCED) || 5000 pmap_is_referenced(m)) 5001 val |= MINCORE_REFERENCED_OTHER; 5002 vm_page_unlock_queues(); 5003 } 5004 } 5005 return (val); 5006} 5007 5008void 5009pmap_activate(struct thread *td) 5010{ 5011 pmap_t pmap, oldpmap; 5012 u_int32_t cr3; 5013 5014 critical_enter(); 5015 pmap = vmspace_pmap(td->td_proc->p_vmspace); 5016 oldpmap = PCPU_GET(curpmap); 5017#if defined(SMP) 5018 atomic_clear_int(&oldpmap->pm_active, PCPU_GET(cpumask)); 5019 atomic_set_int(&pmap->pm_active, PCPU_GET(cpumask)); 5020#else 5021 oldpmap->pm_active &= ~1; 5022 pmap->pm_active |= 1; 5023#endif 5024#ifdef PAE 5025 cr3 = vtophys(pmap->pm_pdpt); 5026#else 5027 cr3 = vtophys(pmap->pm_pdir); 5028#endif 5029 /* 5030 * pmap_activate is for the current thread on the current cpu 5031 */ 5032 td->td_pcb->pcb_cr3 = cr3; 5033 load_cr3(cr3); 5034 PCPU_SET(curpmap, pmap); 5035 critical_exit(); 5036} 5037 5038void 5039pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz) 5040{ 5041} 5042 5043/* 5044 * Increase the starting virtual address of the given mapping if a 5045 * different alignment might result in more superpage mappings. 5046 */ 5047void 5048pmap_align_superpage(vm_object_t object, vm_ooffset_t offset, 5049 vm_offset_t *addr, vm_size_t size) 5050{ 5051 vm_offset_t superpage_offset; 5052 5053 if (size < NBPDR) 5054 return; 5055 if (object != NULL && (object->flags & OBJ_COLORED) != 0) 5056 offset += ptoa(object->pg_color); 5057 superpage_offset = offset & PDRMASK; 5058 if (size - ((NBPDR - superpage_offset) & PDRMASK) < NBPDR || 5059 (*addr & PDRMASK) == superpage_offset) 5060 return; 5061 if ((*addr & PDRMASK) < superpage_offset) 5062 *addr = (*addr & ~PDRMASK) + superpage_offset; 5063 else 5064 *addr = ((*addr + PDRMASK) & ~PDRMASK) + superpage_offset; 5065} 5066 5067 5068#if defined(PMAP_DEBUG) 5069pmap_pid_dump(int pid) 5070{ 5071 pmap_t pmap; 5072 struct proc *p; 5073 int npte = 0; 5074 int index; 5075 5076 sx_slock(&allproc_lock); 5077 FOREACH_PROC_IN_SYSTEM(p) { 5078 if (p->p_pid != pid) 5079 continue; 5080 5081 if (p->p_vmspace) { 5082 int i,j; 5083 index = 0; 5084 pmap = vmspace_pmap(p->p_vmspace); 5085 for (i = 0; i < NPDEPTD; i++) { 5086 pd_entry_t *pde; 5087 pt_entry_t *pte; 5088 vm_offset_t base = i << PDRSHIFT; 5089 5090 pde = &pmap->pm_pdir[i]; 5091 if (pde && pmap_pde_v(pde)) { 5092 for (j = 0; j < NPTEPG; j++) { 5093 vm_offset_t va = base + (j << PAGE_SHIFT); 5094 if (va >= (vm_offset_t) VM_MIN_KERNEL_ADDRESS) { 5095 if (index) { 5096 index = 0; 5097 printf("\n"); 5098 } 5099 sx_sunlock(&allproc_lock); 5100 return (npte); 5101 } 5102 pte = pmap_pte(pmap, va); 5103 if (pte && pmap_pte_v(pte)) { 5104 pt_entry_t pa; 5105 vm_page_t m; 5106 pa = *pte; 5107 m = PHYS_TO_VM_PAGE(pa & PG_FRAME); 5108 printf("va: 0x%x, pt: 0x%x, h: %d, w: %d, f: 0x%x", 5109 va, pa, m->hold_count, m->wire_count, m->flags); 5110 npte++; 5111 index++; 5112 if (index >= 2) { 5113 index = 0; 5114 printf("\n"); 5115 } else { 5116 printf(" "); 5117 } 5118 } 5119 } 5120 } 5121 } 5122 } 5123 } 5124 sx_sunlock(&allproc_lock); 5125 return (npte); 5126} 5127#endif 5128 5129#if defined(DEBUG) 5130 5131static void pads(pmap_t pm); 5132void pmap_pvdump(vm_offset_t pa); 5133 5134/* print address space of pmap*/ 5135static void 5136pads(pmap_t pm) 5137{ 5138 int i, j; 5139 vm_paddr_t va; 5140 pt_entry_t *ptep; 5141 5142 if (pm == kernel_pmap) 5143 return; 5144 for (i = 0; i < NPDEPTD; i++) 5145 if (pm->pm_pdir[i]) 5146 for (j = 0; j < NPTEPG; j++) { 5147 va = (i << PDRSHIFT) + (j << PAGE_SHIFT); 5148 if (pm == kernel_pmap && va < KERNBASE) 5149 continue; 5150 if (pm != kernel_pmap && va > UPT_MAX_ADDRESS) 5151 continue; 5152 ptep = pmap_pte(pm, va); 5153 if (pmap_pte_v(ptep)) 5154 printf("%x:%x ", va, *ptep); 5155 }; 5156 5157} 5158 5159void 5160pmap_pvdump(vm_paddr_t pa) 5161{ 5162 pv_entry_t pv; 5163 pmap_t pmap; 5164 vm_page_t m; 5165 5166 printf("pa %x", pa); 5167 m = PHYS_TO_VM_PAGE(pa); 5168 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 5169 pmap = PV_PMAP(pv); 5170 printf(" -> pmap %p, va %x", (void *)pmap, pv->pv_va); 5171 pads(pmap); 5172 } 5173 printf(" "); 5174} 5175#endif 5176