pmap.c revision 207163
1/*- 2 * Copyright (c) 1991 Regents of the University of California. 3 * All rights reserved. 4 * Copyright (c) 1994 John S. Dyson 5 * All rights reserved. 6 * Copyright (c) 1994 David Greenman 7 * All rights reserved. 8 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu> 9 * All rights reserved. 10 * 11 * This code is derived from software contributed to Berkeley by 12 * the Systems Programming Group of the University of Utah Computer 13 * Science Department and William Jolitz of UUNET Technologies Inc. 14 * 15 * Redistribution and use in source and binary forms, with or without 16 * modification, are permitted provided that the following conditions 17 * are met: 18 * 1. Redistributions of source code must retain the above copyright 19 * notice, this list of conditions and the following disclaimer. 20 * 2. Redistributions in binary form must reproduce the above copyright 21 * notice, this list of conditions and the following disclaimer in the 22 * documentation and/or other materials provided with the distribution. 23 * 3. All advertising materials mentioning features or use of this software 24 * must display the following acknowledgement: 25 * This product includes software developed by the University of 26 * California, Berkeley and its contributors. 27 * 4. Neither the name of the University nor the names of its contributors 28 * may be used to endorse or promote products derived from this software 29 * without specific prior written permission. 30 * 31 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 32 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 33 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 34 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 35 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 36 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 37 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 38 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 39 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 40 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 41 * SUCH DAMAGE. 42 * 43 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91 44 */ 45/*- 46 * Copyright (c) 2003 Networks Associates Technology, Inc. 47 * All rights reserved. 48 * 49 * This software was developed for the FreeBSD Project by Jake Burkholder, 50 * Safeport Network Services, and Network Associates Laboratories, the 51 * Security Research Division of Network Associates, Inc. under 52 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA 53 * CHATS research program. 54 * 55 * Redistribution and use in source and binary forms, with or without 56 * modification, are permitted provided that the following conditions 57 * are met: 58 * 1. Redistributions of source code must retain the above copyright 59 * notice, this list of conditions and the following disclaimer. 60 * 2. Redistributions in binary form must reproduce the above copyright 61 * notice, this list of conditions and the following disclaimer in the 62 * documentation and/or other materials provided with the distribution. 63 * 64 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 65 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 66 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 67 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 68 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 69 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 70 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 71 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 72 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 73 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 74 * SUCH DAMAGE. 75 */ 76 77#include <sys/cdefs.h> 78__FBSDID("$FreeBSD: head/sys/i386/i386/pmap.c 207163 2010-04-24 21:36:52Z kmacy $"); 79 80/* 81 * Manages physical address maps. 82 * 83 * In addition to hardware address maps, this 84 * module is called upon to provide software-use-only 85 * maps which may or may not be stored in the same 86 * form as hardware maps. These pseudo-maps are 87 * used to store intermediate results from copy 88 * operations to and from address spaces. 89 * 90 * Since the information managed by this module is 91 * also stored by the logical address mapping module, 92 * this module may throw away valid virtual-to-physical 93 * mappings at almost any time. However, invalidations 94 * of virtual-to-physical mappings must be done as 95 * requested. 96 * 97 * In order to cope with hardware architectures which 98 * make virtual-to-physical map invalidates expensive, 99 * this module may delay invalidate or reduced protection 100 * operations until such time as they are actually 101 * necessary. This module is given full information as 102 * to which processors are currently using which maps, 103 * and to when physical maps must be made correct. 104 */ 105 106#include "opt_cpu.h" 107#include "opt_pmap.h" 108#include "opt_msgbuf.h" 109#include "opt_smp.h" 110#include "opt_xbox.h" 111 112#include <sys/param.h> 113#include <sys/systm.h> 114#include <sys/kernel.h> 115#include <sys/ktr.h> 116#include <sys/lock.h> 117#include <sys/malloc.h> 118#include <sys/mman.h> 119#include <sys/msgbuf.h> 120#include <sys/mutex.h> 121#include <sys/proc.h> 122#include <sys/sf_buf.h> 123#include <sys/sx.h> 124#include <sys/vmmeter.h> 125#include <sys/sched.h> 126#include <sys/sysctl.h> 127#ifdef SMP 128#include <sys/smp.h> 129#endif 130 131#include <vm/vm.h> 132#include <vm/vm_param.h> 133#include <vm/vm_kern.h> 134#include <vm/vm_page.h> 135#include <vm/vm_map.h> 136#include <vm/vm_object.h> 137#include <vm/vm_extern.h> 138#include <vm/vm_pageout.h> 139#include <vm/vm_pager.h> 140#include <vm/vm_reserv.h> 141#include <vm/uma.h> 142 143#include <machine/cpu.h> 144#include <machine/cputypes.h> 145#include <machine/md_var.h> 146#include <machine/pcb.h> 147#include <machine/specialreg.h> 148#ifdef SMP 149#include <machine/smp.h> 150#endif 151 152#ifdef XBOX 153#include <machine/xbox.h> 154#endif 155 156#if !defined(CPU_DISABLE_SSE) && defined(I686_CPU) 157#define CPU_ENABLE_SSE 158#endif 159 160#ifndef PMAP_SHPGPERPROC 161#define PMAP_SHPGPERPROC 200 162#endif 163 164#if !defined(DIAGNOSTIC) 165#ifdef __GNUC_GNU_INLINE__ 166#define PMAP_INLINE __attribute__((__gnu_inline__)) inline 167#else 168#define PMAP_INLINE extern inline 169#endif 170#else 171#define PMAP_INLINE 172#endif 173 174#define PV_STATS 175#ifdef PV_STATS 176#define PV_STAT(x) do { x ; } while (0) 177#else 178#define PV_STAT(x) do { } while (0) 179#endif 180 181#define pa_index(pa) ((pa) >> PDRSHIFT) 182#define pa_to_pvh(pa) (&pv_table[pa_index(pa)]) 183 184/* 185 * Get PDEs and PTEs for user/kernel address space 186 */ 187#define pmap_pde(m, v) (&((m)->pm_pdir[(vm_offset_t)(v) >> PDRSHIFT])) 188#define pdir_pde(m, v) (m[(vm_offset_t)(v) >> PDRSHIFT]) 189 190#define pmap_pde_v(pte) ((*(int *)pte & PG_V) != 0) 191#define pmap_pte_w(pte) ((*(int *)pte & PG_W) != 0) 192#define pmap_pte_m(pte) ((*(int *)pte & PG_M) != 0) 193#define pmap_pte_u(pte) ((*(int *)pte & PG_A) != 0) 194#define pmap_pte_v(pte) ((*(int *)pte & PG_V) != 0) 195 196#define pmap_pte_set_w(pte, v) ((v) ? atomic_set_int((u_int *)(pte), PG_W) : \ 197 atomic_clear_int((u_int *)(pte), PG_W)) 198#define pmap_pte_set_prot(pte, v) ((*(int *)pte &= ~PG_PROT), (*(int *)pte |= (v))) 199 200struct pmap kernel_pmap_store; 201LIST_HEAD(pmaplist, pmap); 202static struct pmaplist allpmaps; 203static struct mtx allpmaps_lock; 204 205vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */ 206vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */ 207int pgeflag = 0; /* PG_G or-in */ 208int pseflag = 0; /* PG_PS or-in */ 209 210static int nkpt = NKPT; 211vm_offset_t kernel_vm_end = KERNBASE + NKPT * NBPDR; 212extern u_int32_t KERNend; 213extern u_int32_t KPTphys; 214 215#ifdef PAE 216pt_entry_t pg_nx; 217static uma_zone_t pdptzone; 218#endif 219 220static int pat_works = 0; /* Is page attribute table sane? */ 221 222SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD, 0, "VM/pmap parameters"); 223 224static int pg_ps_enabled = 1; 225SYSCTL_INT(_vm_pmap, OID_AUTO, pg_ps_enabled, CTLFLAG_RDTUN, &pg_ps_enabled, 0, 226 "Are large page mappings enabled?"); 227 228/* 229 * Data for the pv entry allocation mechanism 230 */ 231static int pv_entry_count = 0, pv_entry_max = 0, pv_entry_high_water = 0; 232static struct md_page *pv_table; 233static int shpgperproc = PMAP_SHPGPERPROC; 234 235struct pv_chunk *pv_chunkbase; /* KVA block for pv_chunks */ 236int pv_maxchunks; /* How many chunks we have KVA for */ 237vm_offset_t pv_vafree; /* freelist stored in the PTE */ 238 239/* 240 * All those kernel PT submaps that BSD is so fond of 241 */ 242struct sysmaps { 243 struct mtx lock; 244 pt_entry_t *CMAP1; 245 pt_entry_t *CMAP2; 246 caddr_t CADDR1; 247 caddr_t CADDR2; 248}; 249static struct sysmaps sysmaps_pcpu[MAXCPU]; 250pt_entry_t *CMAP1 = 0, *KPTmap; 251static pt_entry_t *CMAP3; 252static pd_entry_t *KPTD; 253caddr_t CADDR1 = 0, ptvmmap = 0; 254static caddr_t CADDR3; 255struct msgbuf *msgbufp = 0; 256 257/* 258 * Crashdump maps. 259 */ 260static caddr_t crashdumpmap; 261 262static pt_entry_t *PMAP1 = 0, *PMAP2; 263static pt_entry_t *PADDR1 = 0, *PADDR2; 264#ifdef SMP 265static int PMAP1cpu; 266static int PMAP1changedcpu; 267SYSCTL_INT(_debug, OID_AUTO, PMAP1changedcpu, CTLFLAG_RD, 268 &PMAP1changedcpu, 0, 269 "Number of times pmap_pte_quick changed CPU with same PMAP1"); 270#endif 271static int PMAP1changed; 272SYSCTL_INT(_debug, OID_AUTO, PMAP1changed, CTLFLAG_RD, 273 &PMAP1changed, 0, 274 "Number of times pmap_pte_quick changed PMAP1"); 275static int PMAP1unchanged; 276SYSCTL_INT(_debug, OID_AUTO, PMAP1unchanged, CTLFLAG_RD, 277 &PMAP1unchanged, 0, 278 "Number of times pmap_pte_quick didn't change PMAP1"); 279static struct mtx PMAP2mutex; 280 281static void free_pv_entry(pmap_t pmap, pv_entry_t pv); 282static pv_entry_t get_pv_entry(pmap_t locked_pmap, int try); 283static void pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa); 284static boolean_t pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa); 285static void pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa); 286static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va); 287static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, 288 vm_offset_t va); 289static int pmap_pvh_wired_mappings(struct md_page *pvh, int count); 290 291static boolean_t pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va); 292static boolean_t pmap_enter_pde(pmap_t pmap, vm_offset_t va, vm_page_t m, 293 vm_prot_t prot); 294static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, 295 vm_page_t m, vm_prot_t prot, vm_page_t mpte); 296static void pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte); 297static void pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte); 298static boolean_t pmap_is_modified_pvh(struct md_page *pvh); 299static boolean_t pmap_is_referenced_pvh(struct md_page *pvh); 300static void pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode); 301static void pmap_kenter_pde(vm_offset_t va, pd_entry_t newpde); 302static vm_page_t pmap_lookup_pt_page(pmap_t pmap, vm_offset_t va); 303static void pmap_pde_attr(pd_entry_t *pde, int cache_bits); 304static void pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va); 305static boolean_t pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva, 306 vm_prot_t prot); 307static void pmap_pte_attr(pt_entry_t *pte, int cache_bits); 308static void pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva, 309 vm_page_t *free); 310static int pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t sva, 311 vm_page_t *free); 312static void pmap_remove_pt_page(pmap_t pmap, vm_page_t mpte); 313static void pmap_remove_page(struct pmap *pmap, vm_offset_t va, 314 vm_page_t *free); 315static void pmap_remove_entry(struct pmap *pmap, vm_page_t m, 316 vm_offset_t va); 317static void pmap_insert_entry(pmap_t pmap, vm_offset_t va, vm_page_t m); 318static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, 319 vm_page_t m); 320static void pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, 321 pd_entry_t newpde); 322static void pmap_update_pde_invalidate(vm_offset_t va, pd_entry_t newpde); 323 324static vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va, int flags); 325 326static vm_page_t _pmap_allocpte(pmap_t pmap, unsigned ptepindex, int flags); 327static int _pmap_unwire_pte_hold(pmap_t pmap, vm_page_t m, vm_page_t *free); 328static pt_entry_t *pmap_pte_quick(pmap_t pmap, vm_offset_t va); 329static void pmap_pte_release(pt_entry_t *pte); 330static int pmap_unuse_pt(pmap_t, vm_offset_t, vm_page_t *); 331#ifdef PAE 332static void *pmap_pdpt_allocf(uma_zone_t zone, int bytes, u_int8_t *flags, int wait); 333#endif 334static void pmap_set_pg(void); 335 336CTASSERT(1 << PDESHIFT == sizeof(pd_entry_t)); 337CTASSERT(1 << PTESHIFT == sizeof(pt_entry_t)); 338 339/* 340 * If you get an error here, then you set KVA_PAGES wrong! See the 341 * description of KVA_PAGES in sys/i386/include/pmap.h. It must be 342 * multiple of 4 for a normal kernel, or a multiple of 8 for a PAE. 343 */ 344CTASSERT(KERNBASE % (1 << 24) == 0); 345 346/* 347 * Bootstrap the system enough to run with virtual memory. 348 * 349 * On the i386 this is called after mapping has already been enabled 350 * and just syncs the pmap module with what has already been done. 351 * [We can't call it easily with mapping off since the kernel is not 352 * mapped with PA == VA, hence we would have to relocate every address 353 * from the linked base (virtual) address "KERNBASE" to the actual 354 * (physical) address starting relative to 0] 355 */ 356void 357pmap_bootstrap(vm_paddr_t firstaddr) 358{ 359 vm_offset_t va; 360 pt_entry_t *pte, *unused; 361 struct sysmaps *sysmaps; 362 int i; 363 364 /* 365 * XXX The calculation of virtual_avail is wrong. It's NKPT*PAGE_SIZE too 366 * large. It should instead be correctly calculated in locore.s and 367 * not based on 'first' (which is a physical address, not a virtual 368 * address, for the start of unused physical memory). The kernel 369 * page tables are NOT double mapped and thus should not be included 370 * in this calculation. 371 */ 372 virtual_avail = (vm_offset_t) KERNBASE + firstaddr; 373 374 virtual_end = VM_MAX_KERNEL_ADDRESS; 375 376 /* 377 * Initialize the kernel pmap (which is statically allocated). 378 */ 379 PMAP_LOCK_INIT(kernel_pmap); 380 kernel_pmap->pm_pdir = (pd_entry_t *) (KERNBASE + (u_int)IdlePTD); 381#ifdef PAE 382 kernel_pmap->pm_pdpt = (pdpt_entry_t *) (KERNBASE + (u_int)IdlePDPT); 383#endif 384 kernel_pmap->pm_root = NULL; 385 kernel_pmap->pm_active = -1; /* don't allow deactivation */ 386 TAILQ_INIT(&kernel_pmap->pm_pvchunk); 387 LIST_INIT(&allpmaps); 388 389 /* 390 * Request a spin mutex so that changes to allpmaps cannot be 391 * preempted by smp_rendezvous_cpus(). Otherwise, 392 * pmap_update_pde_kernel() could access allpmaps while it is 393 * being changed. 394 */ 395 mtx_init(&allpmaps_lock, "allpmaps", NULL, MTX_SPIN); 396 mtx_lock_spin(&allpmaps_lock); 397 LIST_INSERT_HEAD(&allpmaps, kernel_pmap, pm_list); 398 mtx_unlock_spin(&allpmaps_lock); 399 400 /* 401 * Reserve some special page table entries/VA space for temporary 402 * mapping of pages. 403 */ 404#define SYSMAP(c, p, v, n) \ 405 v = (c)va; va += ((n)*PAGE_SIZE); p = pte; pte += (n); 406 407 va = virtual_avail; 408 pte = vtopte(va); 409 410 /* 411 * CMAP1/CMAP2 are used for zeroing and copying pages. 412 * CMAP3 is used for the idle process page zeroing. 413 */ 414 for (i = 0; i < MAXCPU; i++) { 415 sysmaps = &sysmaps_pcpu[i]; 416 mtx_init(&sysmaps->lock, "SYSMAPS", NULL, MTX_DEF); 417 SYSMAP(caddr_t, sysmaps->CMAP1, sysmaps->CADDR1, 1) 418 SYSMAP(caddr_t, sysmaps->CMAP2, sysmaps->CADDR2, 1) 419 } 420 SYSMAP(caddr_t, CMAP1, CADDR1, 1) 421 SYSMAP(caddr_t, CMAP3, CADDR3, 1) 422 423 /* 424 * Crashdump maps. 425 */ 426 SYSMAP(caddr_t, unused, crashdumpmap, MAXDUMPPGS) 427 428 /* 429 * ptvmmap is used for reading arbitrary physical pages via /dev/mem. 430 */ 431 SYSMAP(caddr_t, unused, ptvmmap, 1) 432 433 /* 434 * msgbufp is used to map the system message buffer. 435 */ 436 SYSMAP(struct msgbuf *, unused, msgbufp, atop(round_page(MSGBUF_SIZE))) 437 438 /* 439 * KPTmap is used by pmap_kextract(). 440 */ 441 SYSMAP(pt_entry_t *, KPTD, KPTmap, KVA_PAGES) 442 443 for (i = 0; i < NKPT; i++) 444 KPTD[i] = (KPTphys + (i << PAGE_SHIFT)) | pgeflag | PG_RW | PG_V; 445 446 /* 447 * Adjust the start of the KPTD and KPTmap so that the implementation 448 * of pmap_kextract() and pmap_growkernel() can be made simpler. 449 */ 450 KPTD -= KPTDI; 451 KPTmap -= i386_btop(KPTDI << PDRSHIFT); 452 453 /* 454 * ptemap is used for pmap_pte_quick 455 */ 456 SYSMAP(pt_entry_t *, PMAP1, PADDR1, 1) 457 SYSMAP(pt_entry_t *, PMAP2, PADDR2, 1) 458 459 mtx_init(&PMAP2mutex, "PMAP2", NULL, MTX_DEF); 460 461 virtual_avail = va; 462 463 /* 464 * Leave in place an identity mapping (virt == phys) for the low 1 MB 465 * physical memory region that is used by the ACPI wakeup code. This 466 * mapping must not have PG_G set. 467 */ 468#ifdef XBOX 469 /* FIXME: This is gross, but needed for the XBOX. Since we are in such 470 * an early stadium, we cannot yet neatly map video memory ... :-( 471 * Better fixes are very welcome! */ 472 if (!arch_i386_is_xbox) 473#endif 474 for (i = 1; i < NKPT; i++) 475 PTD[i] = 0; 476 477 /* Initialize the PAT MSR if present. */ 478 pmap_init_pat(); 479 480 /* Turn on PG_G on kernel page(s) */ 481 pmap_set_pg(); 482} 483 484/* 485 * Setup the PAT MSR. 486 */ 487void 488pmap_init_pat(void) 489{ 490 uint64_t pat_msr; 491 char *sysenv; 492 static int pat_tested = 0; 493 494 /* Bail if this CPU doesn't implement PAT. */ 495 if (!(cpu_feature & CPUID_PAT)) 496 return; 497 498 /* 499 * Due to some Intel errata, we can only safely use the lower 4 500 * PAT entries. 501 * 502 * Intel Pentium III Processor Specification Update 503 * Errata E.27 (Upper Four PAT Entries Not Usable With Mode B 504 * or Mode C Paging) 505 * 506 * Intel Pentium IV Processor Specification Update 507 * Errata N46 (PAT Index MSB May Be Calculated Incorrectly) 508 * 509 * Some Apple Macs based on nVidia chipsets cannot enter ACPI mode 510 * via SMI# when we use upper 4 PAT entries for unknown reason. 511 */ 512 if (!pat_tested) { 513 if (cpu_vendor_id != CPU_VENDOR_INTEL || 514 (CPUID_TO_FAMILY(cpu_id) == 6 && 515 CPUID_TO_MODEL(cpu_id) >= 0xe)) { 516 pat_works = 1; 517 sysenv = getenv("smbios.system.product"); 518 if (sysenv != NULL) { 519 if (strncmp(sysenv, "MacBook5,1", 10) == 0 || 520 strncmp(sysenv, "MacBookPro5,5", 13) == 0 || 521 strncmp(sysenv, "Macmini3,1", 10) == 0) 522 pat_works = 0; 523 freeenv(sysenv); 524 } 525 } 526 pat_tested = 1; 527 } 528 529 /* Initialize default PAT entries. */ 530 pat_msr = PAT_VALUE(0, PAT_WRITE_BACK) | 531 PAT_VALUE(1, PAT_WRITE_THROUGH) | 532 PAT_VALUE(2, PAT_UNCACHED) | 533 PAT_VALUE(3, PAT_UNCACHEABLE) | 534 PAT_VALUE(4, PAT_WRITE_BACK) | 535 PAT_VALUE(5, PAT_WRITE_THROUGH) | 536 PAT_VALUE(6, PAT_UNCACHED) | 537 PAT_VALUE(7, PAT_UNCACHEABLE); 538 539 if (pat_works) { 540 /* 541 * Leave the indices 0-3 at the default of WB, WT, UC-, and UC. 542 * Program 4 and 5 as WP and WC. 543 * Leave 6 and 7 as UC- and UC. 544 */ 545 pat_msr &= ~(PAT_MASK(4) | PAT_MASK(5)); 546 pat_msr |= PAT_VALUE(4, PAT_WRITE_PROTECTED) | 547 PAT_VALUE(5, PAT_WRITE_COMBINING); 548 } else { 549 /* 550 * Just replace PAT Index 2 with WC instead of UC-. 551 */ 552 pat_msr &= ~PAT_MASK(2); 553 pat_msr |= PAT_VALUE(2, PAT_WRITE_COMBINING); 554 } 555 wrmsr(MSR_PAT, pat_msr); 556} 557 558/* 559 * Set PG_G on kernel pages. Only the BSP calls this when SMP is turned on. 560 */ 561static void 562pmap_set_pg(void) 563{ 564 pt_entry_t *pte; 565 vm_offset_t va, endva; 566 567 if (pgeflag == 0) 568 return; 569 570 endva = KERNBASE + KERNend; 571 572 if (pseflag) { 573 va = KERNBASE + KERNLOAD; 574 while (va < endva) { 575 pdir_pde(PTD, va) |= pgeflag; 576 invltlb(); /* Play it safe, invltlb() every time */ 577 va += NBPDR; 578 } 579 } else { 580 va = (vm_offset_t)btext; 581 while (va < endva) { 582 pte = vtopte(va); 583 if (*pte) 584 *pte |= pgeflag; 585 invltlb(); /* Play it safe, invltlb() every time */ 586 va += PAGE_SIZE; 587 } 588 } 589} 590 591/* 592 * Initialize a vm_page's machine-dependent fields. 593 */ 594void 595pmap_page_init(vm_page_t m) 596{ 597 598 TAILQ_INIT(&m->md.pv_list); 599 m->md.pat_mode = PAT_WRITE_BACK; 600} 601 602#ifdef PAE 603static void * 604pmap_pdpt_allocf(uma_zone_t zone, int bytes, u_int8_t *flags, int wait) 605{ 606 607 /* Inform UMA that this allocator uses kernel_map/object. */ 608 *flags = UMA_SLAB_KERNEL; 609 return ((void *)kmem_alloc_contig(kernel_map, bytes, wait, 0x0ULL, 610 0xffffffffULL, 1, 0, VM_MEMATTR_DEFAULT)); 611} 612#endif 613 614/* 615 * ABuse the pte nodes for unmapped kva to thread a kva freelist through. 616 * Requirements: 617 * - Must deal with pages in order to ensure that none of the PG_* bits 618 * are ever set, PG_V in particular. 619 * - Assumes we can write to ptes without pte_store() atomic ops, even 620 * on PAE systems. This should be ok. 621 * - Assumes nothing will ever test these addresses for 0 to indicate 622 * no mapping instead of correctly checking PG_V. 623 * - Assumes a vm_offset_t will fit in a pte (true for i386). 624 * Because PG_V is never set, there can be no mappings to invalidate. 625 */ 626static vm_offset_t 627pmap_ptelist_alloc(vm_offset_t *head) 628{ 629 pt_entry_t *pte; 630 vm_offset_t va; 631 632 va = *head; 633 if (va == 0) 634 return (va); /* Out of memory */ 635 pte = vtopte(va); 636 *head = *pte; 637 if (*head & PG_V) 638 panic("pmap_ptelist_alloc: va with PG_V set!"); 639 *pte = 0; 640 return (va); 641} 642 643static void 644pmap_ptelist_free(vm_offset_t *head, vm_offset_t va) 645{ 646 pt_entry_t *pte; 647 648 if (va & PG_V) 649 panic("pmap_ptelist_free: freeing va with PG_V set!"); 650 pte = vtopte(va); 651 *pte = *head; /* virtual! PG_V is 0 though */ 652 *head = va; 653} 654 655static void 656pmap_ptelist_init(vm_offset_t *head, void *base, int npages) 657{ 658 int i; 659 vm_offset_t va; 660 661 *head = 0; 662 for (i = npages - 1; i >= 0; i--) { 663 va = (vm_offset_t)base + i * PAGE_SIZE; 664 pmap_ptelist_free(head, va); 665 } 666} 667 668 669/* 670 * Initialize the pmap module. 671 * Called by vm_init, to initialize any structures that the pmap 672 * system needs to map virtual memory. 673 */ 674void 675pmap_init(void) 676{ 677 vm_page_t mpte; 678 vm_size_t s; 679 int i, pv_npg; 680 681 /* 682 * Initialize the vm page array entries for the kernel pmap's 683 * page table pages. 684 */ 685 for (i = 0; i < NKPT; i++) { 686 mpte = PHYS_TO_VM_PAGE(KPTphys + (i << PAGE_SHIFT)); 687 KASSERT(mpte >= vm_page_array && 688 mpte < &vm_page_array[vm_page_array_size], 689 ("pmap_init: page table page is out of range")); 690 mpte->pindex = i + KPTDI; 691 mpte->phys_addr = KPTphys + (i << PAGE_SHIFT); 692 } 693 694 /* 695 * Initialize the address space (zone) for the pv entries. Set a 696 * high water mark so that the system can recover from excessive 697 * numbers of pv entries. 698 */ 699 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc); 700 pv_entry_max = shpgperproc * maxproc + cnt.v_page_count; 701 TUNABLE_INT_FETCH("vm.pmap.pv_entries", &pv_entry_max); 702 pv_entry_max = roundup(pv_entry_max, _NPCPV); 703 pv_entry_high_water = 9 * (pv_entry_max / 10); 704 705 /* 706 * If the kernel is running in a virtual machine on an AMD Family 10h 707 * processor, then it must assume that MCA is enabled by the virtual 708 * machine monitor. 709 */ 710 if (vm_guest == VM_GUEST_VM && cpu_vendor_id == CPU_VENDOR_AMD && 711 CPUID_TO_FAMILY(cpu_id) == 0x10) 712 workaround_erratum383 = 1; 713 714 /* 715 * Are large page mappings supported and enabled? 716 */ 717 TUNABLE_INT_FETCH("vm.pmap.pg_ps_enabled", &pg_ps_enabled); 718 if (pseflag == 0) 719 pg_ps_enabled = 0; 720 else if (pg_ps_enabled) { 721 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0, 722 ("pmap_init: can't assign to pagesizes[1]")); 723 pagesizes[1] = NBPDR; 724 } 725 726 /* 727 * Calculate the size of the pv head table for superpages. 728 */ 729 for (i = 0; phys_avail[i + 1]; i += 2); 730 pv_npg = round_4mpage(phys_avail[(i - 2) + 1]) / NBPDR; 731 732 /* 733 * Allocate memory for the pv head table for superpages. 734 */ 735 s = (vm_size_t)(pv_npg * sizeof(struct md_page)); 736 s = round_page(s); 737 pv_table = (struct md_page *)kmem_alloc(kernel_map, s); 738 for (i = 0; i < pv_npg; i++) 739 TAILQ_INIT(&pv_table[i].pv_list); 740 741 pv_maxchunks = MAX(pv_entry_max / _NPCPV, maxproc); 742 pv_chunkbase = (struct pv_chunk *)kmem_alloc_nofault(kernel_map, 743 PAGE_SIZE * pv_maxchunks); 744 if (pv_chunkbase == NULL) 745 panic("pmap_init: not enough kvm for pv chunks"); 746 pmap_ptelist_init(&pv_vafree, pv_chunkbase, pv_maxchunks); 747#ifdef PAE 748 pdptzone = uma_zcreate("PDPT", NPGPTD * sizeof(pdpt_entry_t), NULL, 749 NULL, NULL, NULL, (NPGPTD * sizeof(pdpt_entry_t)) - 1, 750 UMA_ZONE_VM | UMA_ZONE_NOFREE); 751 uma_zone_set_allocf(pdptzone, pmap_pdpt_allocf); 752#endif 753} 754 755 756SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_max, CTLFLAG_RD, &pv_entry_max, 0, 757 "Max number of PV entries"); 758SYSCTL_INT(_vm_pmap, OID_AUTO, shpgperproc, CTLFLAG_RD, &shpgperproc, 0, 759 "Page share factor per proc"); 760 761SYSCTL_NODE(_vm_pmap, OID_AUTO, pde, CTLFLAG_RD, 0, 762 "2/4MB page mapping counters"); 763 764static u_long pmap_pde_demotions; 765SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, demotions, CTLFLAG_RD, 766 &pmap_pde_demotions, 0, "2/4MB page demotions"); 767 768static u_long pmap_pde_mappings; 769SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, mappings, CTLFLAG_RD, 770 &pmap_pde_mappings, 0, "2/4MB page mappings"); 771 772static u_long pmap_pde_p_failures; 773SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, p_failures, CTLFLAG_RD, 774 &pmap_pde_p_failures, 0, "2/4MB page promotion failures"); 775 776static u_long pmap_pde_promotions; 777SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, promotions, CTLFLAG_RD, 778 &pmap_pde_promotions, 0, "2/4MB page promotions"); 779 780/*************************************************** 781 * Low level helper routines..... 782 ***************************************************/ 783 784/* 785 * Determine the appropriate bits to set in a PTE or PDE for a specified 786 * caching mode. 787 */ 788int 789pmap_cache_bits(int mode, boolean_t is_pde) 790{ 791 int pat_flag, pat_index, cache_bits; 792 793 /* The PAT bit is different for PTE's and PDE's. */ 794 pat_flag = is_pde ? PG_PDE_PAT : PG_PTE_PAT; 795 796 /* If we don't support PAT, map extended modes to older ones. */ 797 if (!(cpu_feature & CPUID_PAT)) { 798 switch (mode) { 799 case PAT_UNCACHEABLE: 800 case PAT_WRITE_THROUGH: 801 case PAT_WRITE_BACK: 802 break; 803 case PAT_UNCACHED: 804 case PAT_WRITE_COMBINING: 805 case PAT_WRITE_PROTECTED: 806 mode = PAT_UNCACHEABLE; 807 break; 808 } 809 } 810 811 /* Map the caching mode to a PAT index. */ 812 if (pat_works) { 813 switch (mode) { 814 case PAT_UNCACHEABLE: 815 pat_index = 3; 816 break; 817 case PAT_WRITE_THROUGH: 818 pat_index = 1; 819 break; 820 case PAT_WRITE_BACK: 821 pat_index = 0; 822 break; 823 case PAT_UNCACHED: 824 pat_index = 2; 825 break; 826 case PAT_WRITE_COMBINING: 827 pat_index = 5; 828 break; 829 case PAT_WRITE_PROTECTED: 830 pat_index = 4; 831 break; 832 default: 833 panic("Unknown caching mode %d\n", mode); 834 } 835 } else { 836 switch (mode) { 837 case PAT_UNCACHED: 838 case PAT_UNCACHEABLE: 839 case PAT_WRITE_PROTECTED: 840 pat_index = 3; 841 break; 842 case PAT_WRITE_THROUGH: 843 pat_index = 1; 844 break; 845 case PAT_WRITE_BACK: 846 pat_index = 0; 847 break; 848 case PAT_WRITE_COMBINING: 849 pat_index = 2; 850 break; 851 default: 852 panic("Unknown caching mode %d\n", mode); 853 } 854 } 855 856 /* Map the 3-bit index value into the PAT, PCD, and PWT bits. */ 857 cache_bits = 0; 858 if (pat_index & 0x4) 859 cache_bits |= pat_flag; 860 if (pat_index & 0x2) 861 cache_bits |= PG_NC_PCD; 862 if (pat_index & 0x1) 863 cache_bits |= PG_NC_PWT; 864 return (cache_bits); 865} 866 867/* 868 * The caller is responsible for maintaining TLB consistency. 869 */ 870static void 871pmap_kenter_pde(vm_offset_t va, pd_entry_t newpde) 872{ 873 pd_entry_t *pde; 874 pmap_t pmap; 875 boolean_t PTD_updated; 876 877 PTD_updated = FALSE; 878 mtx_lock_spin(&allpmaps_lock); 879 LIST_FOREACH(pmap, &allpmaps, pm_list) { 880 if ((pmap->pm_pdir[PTDPTDI] & PG_FRAME) == (PTDpde[0] & 881 PG_FRAME)) 882 PTD_updated = TRUE; 883 pde = pmap_pde(pmap, va); 884 pde_store(pde, newpde); 885 } 886 mtx_unlock_spin(&allpmaps_lock); 887 KASSERT(PTD_updated, 888 ("pmap_kenter_pde: current page table is not in allpmaps")); 889} 890 891/* 892 * After changing the page size for the specified virtual address in the page 893 * table, flush the corresponding entries from the processor's TLB. Only the 894 * calling processor's TLB is affected. 895 * 896 * The calling thread must be pinned to a processor. 897 */ 898static void 899pmap_update_pde_invalidate(vm_offset_t va, pd_entry_t newpde) 900{ 901 u_long cr4; 902 903 if ((newpde & PG_PS) == 0) 904 /* Demotion: flush a specific 2MB page mapping. */ 905 invlpg(va); 906 else if ((newpde & PG_G) == 0) 907 /* 908 * Promotion: flush every 4KB page mapping from the TLB 909 * because there are too many to flush individually. 910 */ 911 invltlb(); 912 else { 913 /* 914 * Promotion: flush every 4KB page mapping from the TLB, 915 * including any global (PG_G) mappings. 916 */ 917 cr4 = rcr4(); 918 load_cr4(cr4 & ~CR4_PGE); 919 /* 920 * Although preemption at this point could be detrimental to 921 * performance, it would not lead to an error. PG_G is simply 922 * ignored if CR4.PGE is clear. Moreover, in case this block 923 * is re-entered, the load_cr4() either above or below will 924 * modify CR4.PGE flushing the TLB. 925 */ 926 load_cr4(cr4 | CR4_PGE); 927 } 928} 929#ifdef SMP 930/* 931 * For SMP, these functions have to use the IPI mechanism for coherence. 932 * 933 * N.B.: Before calling any of the following TLB invalidation functions, 934 * the calling processor must ensure that all stores updating a non- 935 * kernel page table are globally performed. Otherwise, another 936 * processor could cache an old, pre-update entry without being 937 * invalidated. This can happen one of two ways: (1) The pmap becomes 938 * active on another processor after its pm_active field is checked by 939 * one of the following functions but before a store updating the page 940 * table is globally performed. (2) The pmap becomes active on another 941 * processor before its pm_active field is checked but due to 942 * speculative loads one of the following functions stills reads the 943 * pmap as inactive on the other processor. 944 * 945 * The kernel page table is exempt because its pm_active field is 946 * immutable. The kernel page table is always active on every 947 * processor. 948 */ 949void 950pmap_invalidate_page(pmap_t pmap, vm_offset_t va) 951{ 952 u_int cpumask; 953 u_int other_cpus; 954 955 sched_pin(); 956 if (pmap == kernel_pmap || pmap->pm_active == all_cpus) { 957 invlpg(va); 958 smp_invlpg(va); 959 } else { 960 cpumask = PCPU_GET(cpumask); 961 other_cpus = PCPU_GET(other_cpus); 962 if (pmap->pm_active & cpumask) 963 invlpg(va); 964 if (pmap->pm_active & other_cpus) 965 smp_masked_invlpg(pmap->pm_active & other_cpus, va); 966 } 967 sched_unpin(); 968} 969 970void 971pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 972{ 973 u_int cpumask; 974 u_int other_cpus; 975 vm_offset_t addr; 976 977 sched_pin(); 978 if (pmap == kernel_pmap || pmap->pm_active == all_cpus) { 979 for (addr = sva; addr < eva; addr += PAGE_SIZE) 980 invlpg(addr); 981 smp_invlpg_range(sva, eva); 982 } else { 983 cpumask = PCPU_GET(cpumask); 984 other_cpus = PCPU_GET(other_cpus); 985 if (pmap->pm_active & cpumask) 986 for (addr = sva; addr < eva; addr += PAGE_SIZE) 987 invlpg(addr); 988 if (pmap->pm_active & other_cpus) 989 smp_masked_invlpg_range(pmap->pm_active & other_cpus, 990 sva, eva); 991 } 992 sched_unpin(); 993} 994 995void 996pmap_invalidate_all(pmap_t pmap) 997{ 998 u_int cpumask; 999 u_int other_cpus; 1000 1001 sched_pin(); 1002 if (pmap == kernel_pmap || pmap->pm_active == all_cpus) { 1003 invltlb(); 1004 smp_invltlb(); 1005 } else { 1006 cpumask = PCPU_GET(cpumask); 1007 other_cpus = PCPU_GET(other_cpus); 1008 if (pmap->pm_active & cpumask) 1009 invltlb(); 1010 if (pmap->pm_active & other_cpus) 1011 smp_masked_invltlb(pmap->pm_active & other_cpus); 1012 } 1013 sched_unpin(); 1014} 1015 1016void 1017pmap_invalidate_cache(void) 1018{ 1019 1020 sched_pin(); 1021 wbinvd(); 1022 smp_cache_flush(); 1023 sched_unpin(); 1024} 1025 1026struct pde_action { 1027 cpumask_t store; /* processor that updates the PDE */ 1028 cpumask_t invalidate; /* processors that invalidate their TLB */ 1029 vm_offset_t va; 1030 pd_entry_t *pde; 1031 pd_entry_t newpde; 1032}; 1033 1034static void 1035pmap_update_pde_kernel(void *arg) 1036{ 1037 struct pde_action *act = arg; 1038 pd_entry_t *pde; 1039 pmap_t pmap; 1040 1041 if (act->store == PCPU_GET(cpumask)) 1042 /* 1043 * Elsewhere, this operation requires allpmaps_lock for 1044 * synchronization. Here, it does not because it is being 1045 * performed in the context of an all_cpus rendezvous. 1046 */ 1047 LIST_FOREACH(pmap, &allpmaps, pm_list) { 1048 pde = pmap_pde(pmap, act->va); 1049 pde_store(pde, act->newpde); 1050 } 1051} 1052 1053static void 1054pmap_update_pde_user(void *arg) 1055{ 1056 struct pde_action *act = arg; 1057 1058 if (act->store == PCPU_GET(cpumask)) 1059 pde_store(act->pde, act->newpde); 1060} 1061 1062static void 1063pmap_update_pde_teardown(void *arg) 1064{ 1065 struct pde_action *act = arg; 1066 1067 if ((act->invalidate & PCPU_GET(cpumask)) != 0) 1068 pmap_update_pde_invalidate(act->va, act->newpde); 1069} 1070 1071/* 1072 * Change the page size for the specified virtual address in a way that 1073 * prevents any possibility of the TLB ever having two entries that map the 1074 * same virtual address using different page sizes. This is the recommended 1075 * workaround for Erratum 383 on AMD Family 10h processors. It prevents a 1076 * machine check exception for a TLB state that is improperly diagnosed as a 1077 * hardware error. 1078 */ 1079static void 1080pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde) 1081{ 1082 struct pde_action act; 1083 cpumask_t active, cpumask; 1084 1085 sched_pin(); 1086 cpumask = PCPU_GET(cpumask); 1087 if (pmap == kernel_pmap) 1088 active = all_cpus; 1089 else 1090 active = pmap->pm_active; 1091 if ((active & PCPU_GET(other_cpus)) != 0) { 1092 act.store = cpumask; 1093 act.invalidate = active; 1094 act.va = va; 1095 act.pde = pde; 1096 act.newpde = newpde; 1097 smp_rendezvous_cpus(cpumask | active, 1098 smp_no_rendevous_barrier, pmap == kernel_pmap ? 1099 pmap_update_pde_kernel : pmap_update_pde_user, 1100 pmap_update_pde_teardown, &act); 1101 } else { 1102 if (pmap == kernel_pmap) 1103 pmap_kenter_pde(va, newpde); 1104 else 1105 pde_store(pde, newpde); 1106 if ((active & cpumask) != 0) 1107 pmap_update_pde_invalidate(va, newpde); 1108 } 1109 sched_unpin(); 1110} 1111#else /* !SMP */ 1112/* 1113 * Normal, non-SMP, 486+ invalidation functions. 1114 * We inline these within pmap.c for speed. 1115 */ 1116PMAP_INLINE void 1117pmap_invalidate_page(pmap_t pmap, vm_offset_t va) 1118{ 1119 1120 if (pmap == kernel_pmap || pmap->pm_active) 1121 invlpg(va); 1122} 1123 1124PMAP_INLINE void 1125pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 1126{ 1127 vm_offset_t addr; 1128 1129 if (pmap == kernel_pmap || pmap->pm_active) 1130 for (addr = sva; addr < eva; addr += PAGE_SIZE) 1131 invlpg(addr); 1132} 1133 1134PMAP_INLINE void 1135pmap_invalidate_all(pmap_t pmap) 1136{ 1137 1138 if (pmap == kernel_pmap || pmap->pm_active) 1139 invltlb(); 1140} 1141 1142PMAP_INLINE void 1143pmap_invalidate_cache(void) 1144{ 1145 1146 wbinvd(); 1147} 1148 1149static void 1150pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde) 1151{ 1152 1153 if (pmap == kernel_pmap) 1154 pmap_kenter_pde(va, newpde); 1155 else 1156 pde_store(pde, newpde); 1157 if (pmap == kernel_pmap || pmap->pm_active) 1158 pmap_update_pde_invalidate(va, newpde); 1159} 1160#endif /* !SMP */ 1161 1162void 1163pmap_invalidate_cache_range(vm_offset_t sva, vm_offset_t eva) 1164{ 1165 1166 KASSERT((sva & PAGE_MASK) == 0, 1167 ("pmap_invalidate_cache_range: sva not page-aligned")); 1168 KASSERT((eva & PAGE_MASK) == 0, 1169 ("pmap_invalidate_cache_range: eva not page-aligned")); 1170 1171 if (cpu_feature & CPUID_SS) 1172 ; /* If "Self Snoop" is supported, do nothing. */ 1173 else if ((cpu_feature & CPUID_CLFSH) != 0 && 1174 eva - sva < 2 * 1024 * 1024) { 1175 1176 /* 1177 * Otherwise, do per-cache line flush. Use the mfence 1178 * instruction to insure that previous stores are 1179 * included in the write-back. The processor 1180 * propagates flush to other processors in the cache 1181 * coherence domain. 1182 */ 1183 mfence(); 1184 for (; sva < eva; sva += cpu_clflush_line_size) 1185 clflush(sva); 1186 mfence(); 1187 } else { 1188 1189 /* 1190 * No targeted cache flush methods are supported by CPU, 1191 * or the supplied range is bigger than 2MB. 1192 * Globally invalidate cache. 1193 */ 1194 pmap_invalidate_cache(); 1195 } 1196} 1197 1198/* 1199 * Are we current address space or kernel? N.B. We return FALSE when 1200 * a pmap's page table is in use because a kernel thread is borrowing 1201 * it. The borrowed page table can change spontaneously, making any 1202 * dependence on its continued use subject to a race condition. 1203 */ 1204static __inline int 1205pmap_is_current(pmap_t pmap) 1206{ 1207 1208 return (pmap == kernel_pmap || 1209 (pmap == vmspace_pmap(curthread->td_proc->p_vmspace) && 1210 (pmap->pm_pdir[PTDPTDI] & PG_FRAME) == (PTDpde[0] & PG_FRAME))); 1211} 1212 1213/* 1214 * If the given pmap is not the current or kernel pmap, the returned pte must 1215 * be released by passing it to pmap_pte_release(). 1216 */ 1217pt_entry_t * 1218pmap_pte(pmap_t pmap, vm_offset_t va) 1219{ 1220 pd_entry_t newpf; 1221 pd_entry_t *pde; 1222 1223 pde = pmap_pde(pmap, va); 1224 if (*pde & PG_PS) 1225 return (pde); 1226 if (*pde != 0) { 1227 /* are we current address space or kernel? */ 1228 if (pmap_is_current(pmap)) 1229 return (vtopte(va)); 1230 mtx_lock(&PMAP2mutex); 1231 newpf = *pde & PG_FRAME; 1232 if ((*PMAP2 & PG_FRAME) != newpf) { 1233 *PMAP2 = newpf | PG_RW | PG_V | PG_A | PG_M; 1234 pmap_invalidate_page(kernel_pmap, (vm_offset_t)PADDR2); 1235 } 1236 return (PADDR2 + (i386_btop(va) & (NPTEPG - 1))); 1237 } 1238 return (0); 1239} 1240 1241/* 1242 * Releases a pte that was obtained from pmap_pte(). Be prepared for the pte 1243 * being NULL. 1244 */ 1245static __inline void 1246pmap_pte_release(pt_entry_t *pte) 1247{ 1248 1249 if ((pt_entry_t *)((vm_offset_t)pte & ~PAGE_MASK) == PADDR2) 1250 mtx_unlock(&PMAP2mutex); 1251} 1252 1253static __inline void 1254invlcaddr(void *caddr) 1255{ 1256 1257 invlpg((u_int)caddr); 1258} 1259 1260/* 1261 * Super fast pmap_pte routine best used when scanning 1262 * the pv lists. This eliminates many coarse-grained 1263 * invltlb calls. Note that many of the pv list 1264 * scans are across different pmaps. It is very wasteful 1265 * to do an entire invltlb for checking a single mapping. 1266 * 1267 * If the given pmap is not the current pmap, vm_page_queue_mtx 1268 * must be held and curthread pinned to a CPU. 1269 */ 1270static pt_entry_t * 1271pmap_pte_quick(pmap_t pmap, vm_offset_t va) 1272{ 1273 pd_entry_t newpf; 1274 pd_entry_t *pde; 1275 1276 pde = pmap_pde(pmap, va); 1277 if (*pde & PG_PS) 1278 return (pde); 1279 if (*pde != 0) { 1280 /* are we current address space or kernel? */ 1281 if (pmap_is_current(pmap)) 1282 return (vtopte(va)); 1283 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1284 KASSERT(curthread->td_pinned > 0, ("curthread not pinned")); 1285 newpf = *pde & PG_FRAME; 1286 if ((*PMAP1 & PG_FRAME) != newpf) { 1287 *PMAP1 = newpf | PG_RW | PG_V | PG_A | PG_M; 1288#ifdef SMP 1289 PMAP1cpu = PCPU_GET(cpuid); 1290#endif 1291 invlcaddr(PADDR1); 1292 PMAP1changed++; 1293 } else 1294#ifdef SMP 1295 if (PMAP1cpu != PCPU_GET(cpuid)) { 1296 PMAP1cpu = PCPU_GET(cpuid); 1297 invlcaddr(PADDR1); 1298 PMAP1changedcpu++; 1299 } else 1300#endif 1301 PMAP1unchanged++; 1302 return (PADDR1 + (i386_btop(va) & (NPTEPG - 1))); 1303 } 1304 return (0); 1305} 1306 1307/* 1308 * Routine: pmap_extract 1309 * Function: 1310 * Extract the physical page address associated 1311 * with the given map/virtual_address pair. 1312 */ 1313vm_paddr_t 1314pmap_extract(pmap_t pmap, vm_offset_t va) 1315{ 1316 vm_paddr_t rtval; 1317 pt_entry_t *pte; 1318 pd_entry_t pde; 1319 1320 rtval = 0; 1321 PMAP_LOCK(pmap); 1322 pde = pmap->pm_pdir[va >> PDRSHIFT]; 1323 if (pde != 0) { 1324 if ((pde & PG_PS) != 0) 1325 rtval = (pde & PG_PS_FRAME) | (va & PDRMASK); 1326 else { 1327 pte = pmap_pte(pmap, va); 1328 rtval = (*pte & PG_FRAME) | (va & PAGE_MASK); 1329 pmap_pte_release(pte); 1330 } 1331 } 1332 PMAP_UNLOCK(pmap); 1333 return (rtval); 1334} 1335 1336/* 1337 * Routine: pmap_extract_and_hold 1338 * Function: 1339 * Atomically extract and hold the physical page 1340 * with the given pmap and virtual address pair 1341 * if that mapping permits the given protection. 1342 */ 1343vm_page_t 1344pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot) 1345{ 1346 pd_entry_t pde; 1347 pt_entry_t pte; 1348 vm_page_t m; 1349 1350 m = NULL; 1351 vm_page_lock_queues(); 1352 PMAP_LOCK(pmap); 1353 pde = *pmap_pde(pmap, va); 1354 if (pde != 0) { 1355 if (pde & PG_PS) { 1356 if ((pde & PG_RW) || (prot & VM_PROT_WRITE) == 0) { 1357 m = PHYS_TO_VM_PAGE((pde & PG_PS_FRAME) | 1358 (va & PDRMASK)); 1359 vm_page_hold(m); 1360 } 1361 } else { 1362 sched_pin(); 1363 pte = *pmap_pte_quick(pmap, va); 1364 if (pte != 0 && 1365 ((pte & PG_RW) || (prot & VM_PROT_WRITE) == 0)) { 1366 m = PHYS_TO_VM_PAGE(pte & PG_FRAME); 1367 vm_page_hold(m); 1368 } 1369 sched_unpin(); 1370 } 1371 } 1372 vm_page_unlock_queues(); 1373 PMAP_UNLOCK(pmap); 1374 return (m); 1375} 1376 1377/*************************************************** 1378 * Low level mapping routines..... 1379 ***************************************************/ 1380 1381/* 1382 * Add a wired page to the kva. 1383 * Note: not SMP coherent. 1384 */ 1385PMAP_INLINE void 1386pmap_kenter(vm_offset_t va, vm_paddr_t pa) 1387{ 1388 pt_entry_t *pte; 1389 1390 pte = vtopte(va); 1391 pte_store(pte, pa | PG_RW | PG_V | pgeflag); 1392} 1393 1394static __inline void 1395pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode) 1396{ 1397 pt_entry_t *pte; 1398 1399 pte = vtopte(va); 1400 pte_store(pte, pa | PG_RW | PG_V | pgeflag | pmap_cache_bits(mode, 0)); 1401} 1402 1403/* 1404 * Remove a page from the kernel pagetables. 1405 * Note: not SMP coherent. 1406 */ 1407PMAP_INLINE void 1408pmap_kremove(vm_offset_t va) 1409{ 1410 pt_entry_t *pte; 1411 1412 pte = vtopte(va); 1413 pte_clear(pte); 1414} 1415 1416/* 1417 * Used to map a range of physical addresses into kernel 1418 * virtual address space. 1419 * 1420 * The value passed in '*virt' is a suggested virtual address for 1421 * the mapping. Architectures which can support a direct-mapped 1422 * physical to virtual region can return the appropriate address 1423 * within that region, leaving '*virt' unchanged. Other 1424 * architectures should map the pages starting at '*virt' and 1425 * update '*virt' with the first usable address after the mapped 1426 * region. 1427 */ 1428vm_offset_t 1429pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot) 1430{ 1431 vm_offset_t va, sva; 1432 1433 va = sva = *virt; 1434 while (start < end) { 1435 pmap_kenter(va, start); 1436 va += PAGE_SIZE; 1437 start += PAGE_SIZE; 1438 } 1439 pmap_invalidate_range(kernel_pmap, sva, va); 1440 *virt = va; 1441 return (sva); 1442} 1443 1444 1445/* 1446 * Add a list of wired pages to the kva 1447 * this routine is only used for temporary 1448 * kernel mappings that do not need to have 1449 * page modification or references recorded. 1450 * Note that old mappings are simply written 1451 * over. The page *must* be wired. 1452 * Note: SMP coherent. Uses a ranged shootdown IPI. 1453 */ 1454void 1455pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count) 1456{ 1457 pt_entry_t *endpte, oldpte, *pte; 1458 1459 oldpte = 0; 1460 pte = vtopte(sva); 1461 endpte = pte + count; 1462 while (pte < endpte) { 1463 oldpte |= *pte; 1464 pte_store(pte, VM_PAGE_TO_PHYS(*ma) | pgeflag | 1465 pmap_cache_bits((*ma)->md.pat_mode, 0) | PG_RW | PG_V); 1466 pte++; 1467 ma++; 1468 } 1469 if ((oldpte & PG_V) != 0) 1470 pmap_invalidate_range(kernel_pmap, sva, sva + count * 1471 PAGE_SIZE); 1472} 1473 1474/* 1475 * This routine tears out page mappings from the 1476 * kernel -- it is meant only for temporary mappings. 1477 * Note: SMP coherent. Uses a ranged shootdown IPI. 1478 */ 1479void 1480pmap_qremove(vm_offset_t sva, int count) 1481{ 1482 vm_offset_t va; 1483 1484 va = sva; 1485 while (count-- > 0) { 1486 pmap_kremove(va); 1487 va += PAGE_SIZE; 1488 } 1489 pmap_invalidate_range(kernel_pmap, sva, va); 1490} 1491 1492/*************************************************** 1493 * Page table page management routines..... 1494 ***************************************************/ 1495static __inline void 1496pmap_free_zero_pages(vm_page_t free) 1497{ 1498 vm_page_t m; 1499 1500 while (free != NULL) { 1501 m = free; 1502 free = m->right; 1503 /* Preserve the page's PG_ZERO setting. */ 1504 vm_page_free_toq(m); 1505 } 1506} 1507 1508/* 1509 * Schedule the specified unused page table page to be freed. Specifically, 1510 * add the page to the specified list of pages that will be released to the 1511 * physical memory manager after the TLB has been updated. 1512 */ 1513static __inline void 1514pmap_add_delayed_free_list(vm_page_t m, vm_page_t *free, boolean_t set_PG_ZERO) 1515{ 1516 1517 if (set_PG_ZERO) 1518 m->flags |= PG_ZERO; 1519 else 1520 m->flags &= ~PG_ZERO; 1521 m->right = *free; 1522 *free = m; 1523} 1524 1525/* 1526 * Inserts the specified page table page into the specified pmap's collection 1527 * of idle page table pages. Each of a pmap's page table pages is responsible 1528 * for mapping a distinct range of virtual addresses. The pmap's collection is 1529 * ordered by this virtual address range. 1530 */ 1531static void 1532pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte) 1533{ 1534 vm_page_t root; 1535 1536 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1537 root = pmap->pm_root; 1538 if (root == NULL) { 1539 mpte->left = NULL; 1540 mpte->right = NULL; 1541 } else { 1542 root = vm_page_splay(mpte->pindex, root); 1543 if (mpte->pindex < root->pindex) { 1544 mpte->left = root->left; 1545 mpte->right = root; 1546 root->left = NULL; 1547 } else if (mpte->pindex == root->pindex) 1548 panic("pmap_insert_pt_page: pindex already inserted"); 1549 else { 1550 mpte->right = root->right; 1551 mpte->left = root; 1552 root->right = NULL; 1553 } 1554 } 1555 pmap->pm_root = mpte; 1556} 1557 1558/* 1559 * Looks for a page table page mapping the specified virtual address in the 1560 * specified pmap's collection of idle page table pages. Returns NULL if there 1561 * is no page table page corresponding to the specified virtual address. 1562 */ 1563static vm_page_t 1564pmap_lookup_pt_page(pmap_t pmap, vm_offset_t va) 1565{ 1566 vm_page_t mpte; 1567 vm_pindex_t pindex = va >> PDRSHIFT; 1568 1569 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1570 if ((mpte = pmap->pm_root) != NULL && mpte->pindex != pindex) { 1571 mpte = vm_page_splay(pindex, mpte); 1572 if ((pmap->pm_root = mpte)->pindex != pindex) 1573 mpte = NULL; 1574 } 1575 return (mpte); 1576} 1577 1578/* 1579 * Removes the specified page table page from the specified pmap's collection 1580 * of idle page table pages. The specified page table page must be a member of 1581 * the pmap's collection. 1582 */ 1583static void 1584pmap_remove_pt_page(pmap_t pmap, vm_page_t mpte) 1585{ 1586 vm_page_t root; 1587 1588 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1589 if (mpte != pmap->pm_root) 1590 vm_page_splay(mpte->pindex, pmap->pm_root); 1591 if (mpte->left == NULL) 1592 root = mpte->right; 1593 else { 1594 root = vm_page_splay(mpte->pindex, mpte->left); 1595 root->right = mpte->right; 1596 } 1597 pmap->pm_root = root; 1598} 1599 1600/* 1601 * This routine unholds page table pages, and if the hold count 1602 * drops to zero, then it decrements the wire count. 1603 */ 1604static __inline int 1605pmap_unwire_pte_hold(pmap_t pmap, vm_page_t m, vm_page_t *free) 1606{ 1607 1608 --m->wire_count; 1609 if (m->wire_count == 0) 1610 return (_pmap_unwire_pte_hold(pmap, m, free)); 1611 else 1612 return (0); 1613} 1614 1615static int 1616_pmap_unwire_pte_hold(pmap_t pmap, vm_page_t m, vm_page_t *free) 1617{ 1618 vm_offset_t pteva; 1619 1620 /* 1621 * unmap the page table page 1622 */ 1623 pmap->pm_pdir[m->pindex] = 0; 1624 --pmap->pm_stats.resident_count; 1625 1626 /* 1627 * This is a release store so that the ordinary store unmapping 1628 * the page table page is globally performed before TLB shoot- 1629 * down is begun. 1630 */ 1631 atomic_subtract_rel_int(&cnt.v_wire_count, 1); 1632 1633 /* 1634 * Do an invltlb to make the invalidated mapping 1635 * take effect immediately. 1636 */ 1637 pteva = VM_MAXUSER_ADDRESS + i386_ptob(m->pindex); 1638 pmap_invalidate_page(pmap, pteva); 1639 1640 /* 1641 * Put page on a list so that it is released after 1642 * *ALL* TLB shootdown is done 1643 */ 1644 pmap_add_delayed_free_list(m, free, TRUE); 1645 1646 return (1); 1647} 1648 1649/* 1650 * After removing a page table entry, this routine is used to 1651 * conditionally free the page, and manage the hold/wire counts. 1652 */ 1653static int 1654pmap_unuse_pt(pmap_t pmap, vm_offset_t va, vm_page_t *free) 1655{ 1656 pd_entry_t ptepde; 1657 vm_page_t mpte; 1658 1659 if (va >= VM_MAXUSER_ADDRESS) 1660 return (0); 1661 ptepde = *pmap_pde(pmap, va); 1662 mpte = PHYS_TO_VM_PAGE(ptepde & PG_FRAME); 1663 return (pmap_unwire_pte_hold(pmap, mpte, free)); 1664} 1665 1666void 1667pmap_pinit0(pmap_t pmap) 1668{ 1669 1670 PMAP_LOCK_INIT(pmap); 1671 pmap->pm_pdir = (pd_entry_t *)(KERNBASE + (vm_offset_t)IdlePTD); 1672#ifdef PAE 1673 pmap->pm_pdpt = (pdpt_entry_t *)(KERNBASE + (vm_offset_t)IdlePDPT); 1674#endif 1675 pmap->pm_root = NULL; 1676 pmap->pm_active = 0; 1677 PCPU_SET(curpmap, pmap); 1678 TAILQ_INIT(&pmap->pm_pvchunk); 1679 bzero(&pmap->pm_stats, sizeof pmap->pm_stats); 1680 mtx_lock_spin(&allpmaps_lock); 1681 LIST_INSERT_HEAD(&allpmaps, pmap, pm_list); 1682 mtx_unlock_spin(&allpmaps_lock); 1683} 1684 1685/* 1686 * Initialize a preallocated and zeroed pmap structure, 1687 * such as one in a vmspace structure. 1688 */ 1689int 1690pmap_pinit(pmap_t pmap) 1691{ 1692 vm_page_t m, ptdpg[NPGPTD]; 1693 vm_paddr_t pa; 1694 static int color; 1695 int i; 1696 1697 PMAP_LOCK_INIT(pmap); 1698 1699 /* 1700 * No need to allocate page table space yet but we do need a valid 1701 * page directory table. 1702 */ 1703 if (pmap->pm_pdir == NULL) { 1704 pmap->pm_pdir = (pd_entry_t *)kmem_alloc_nofault(kernel_map, 1705 NBPTD); 1706 1707 if (pmap->pm_pdir == NULL) { 1708 PMAP_LOCK_DESTROY(pmap); 1709 return (0); 1710 } 1711#ifdef PAE 1712 pmap->pm_pdpt = uma_zalloc(pdptzone, M_WAITOK | M_ZERO); 1713 KASSERT(((vm_offset_t)pmap->pm_pdpt & 1714 ((NPGPTD * sizeof(pdpt_entry_t)) - 1)) == 0, 1715 ("pmap_pinit: pdpt misaligned")); 1716 KASSERT(pmap_kextract((vm_offset_t)pmap->pm_pdpt) < (4ULL<<30), 1717 ("pmap_pinit: pdpt above 4g")); 1718#endif 1719 pmap->pm_root = NULL; 1720 } 1721 KASSERT(pmap->pm_root == NULL, 1722 ("pmap_pinit: pmap has reserved page table page(s)")); 1723 1724 /* 1725 * allocate the page directory page(s) 1726 */ 1727 for (i = 0; i < NPGPTD;) { 1728 m = vm_page_alloc(NULL, color++, 1729 VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | 1730 VM_ALLOC_ZERO); 1731 if (m == NULL) 1732 VM_WAIT; 1733 else { 1734 ptdpg[i++] = m; 1735 } 1736 } 1737 1738 pmap_qenter((vm_offset_t)pmap->pm_pdir, ptdpg, NPGPTD); 1739 1740 for (i = 0; i < NPGPTD; i++) { 1741 if ((ptdpg[i]->flags & PG_ZERO) == 0) 1742 bzero(pmap->pm_pdir + (i * NPDEPG), PAGE_SIZE); 1743 } 1744 1745 mtx_lock_spin(&allpmaps_lock); 1746 LIST_INSERT_HEAD(&allpmaps, pmap, pm_list); 1747 mtx_unlock_spin(&allpmaps_lock); 1748 /* Wire in kernel global address entries. */ 1749 bcopy(PTD + KPTDI, pmap->pm_pdir + KPTDI, nkpt * sizeof(pd_entry_t)); 1750 1751 /* install self-referential address mapping entry(s) */ 1752 for (i = 0; i < NPGPTD; i++) { 1753 pa = VM_PAGE_TO_PHYS(ptdpg[i]); 1754 pmap->pm_pdir[PTDPTDI + i] = pa | PG_V | PG_RW | PG_A | PG_M; 1755#ifdef PAE 1756 pmap->pm_pdpt[i] = pa | PG_V; 1757#endif 1758 } 1759 1760 pmap->pm_active = 0; 1761 TAILQ_INIT(&pmap->pm_pvchunk); 1762 bzero(&pmap->pm_stats, sizeof pmap->pm_stats); 1763 1764 return (1); 1765} 1766 1767/* 1768 * this routine is called if the page table page is not 1769 * mapped correctly. 1770 */ 1771static vm_page_t 1772_pmap_allocpte(pmap_t pmap, unsigned ptepindex, int flags) 1773{ 1774 vm_paddr_t ptepa; 1775 vm_page_t m; 1776 1777 KASSERT((flags & (M_NOWAIT | M_WAITOK)) == M_NOWAIT || 1778 (flags & (M_NOWAIT | M_WAITOK)) == M_WAITOK, 1779 ("_pmap_allocpte: flags is neither M_NOWAIT nor M_WAITOK")); 1780 1781 /* 1782 * Allocate a page table page. 1783 */ 1784 if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ | 1785 VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) { 1786 if (flags & M_WAITOK) { 1787 PMAP_UNLOCK(pmap); 1788 vm_page_unlock_queues(); 1789 VM_WAIT; 1790 vm_page_lock_queues(); 1791 PMAP_LOCK(pmap); 1792 } 1793 1794 /* 1795 * Indicate the need to retry. While waiting, the page table 1796 * page may have been allocated. 1797 */ 1798 return (NULL); 1799 } 1800 if ((m->flags & PG_ZERO) == 0) 1801 pmap_zero_page(m); 1802 1803 /* 1804 * Map the pagetable page into the process address space, if 1805 * it isn't already there. 1806 */ 1807 1808 pmap->pm_stats.resident_count++; 1809 1810 ptepa = VM_PAGE_TO_PHYS(m); 1811 pmap->pm_pdir[ptepindex] = 1812 (pd_entry_t) (ptepa | PG_U | PG_RW | PG_V | PG_A | PG_M); 1813 1814 return (m); 1815} 1816 1817static vm_page_t 1818pmap_allocpte(pmap_t pmap, vm_offset_t va, int flags) 1819{ 1820 unsigned ptepindex; 1821 pd_entry_t ptepa; 1822 vm_page_t m; 1823 1824 KASSERT((flags & (M_NOWAIT | M_WAITOK)) == M_NOWAIT || 1825 (flags & (M_NOWAIT | M_WAITOK)) == M_WAITOK, 1826 ("pmap_allocpte: flags is neither M_NOWAIT nor M_WAITOK")); 1827 1828 /* 1829 * Calculate pagetable page index 1830 */ 1831 ptepindex = va >> PDRSHIFT; 1832retry: 1833 /* 1834 * Get the page directory entry 1835 */ 1836 ptepa = pmap->pm_pdir[ptepindex]; 1837 1838 /* 1839 * This supports switching from a 4MB page to a 1840 * normal 4K page. 1841 */ 1842 if (ptepa & PG_PS) { 1843 (void)pmap_demote_pde(pmap, &pmap->pm_pdir[ptepindex], va); 1844 ptepa = pmap->pm_pdir[ptepindex]; 1845 } 1846 1847 /* 1848 * If the page table page is mapped, we just increment the 1849 * hold count, and activate it. 1850 */ 1851 if (ptepa) { 1852 m = PHYS_TO_VM_PAGE(ptepa & PG_FRAME); 1853 m->wire_count++; 1854 } else { 1855 /* 1856 * Here if the pte page isn't mapped, or if it has 1857 * been deallocated. 1858 */ 1859 m = _pmap_allocpte(pmap, ptepindex, flags); 1860 if (m == NULL && (flags & M_WAITOK)) 1861 goto retry; 1862 } 1863 return (m); 1864} 1865 1866 1867/*************************************************** 1868* Pmap allocation/deallocation routines. 1869 ***************************************************/ 1870 1871#ifdef SMP 1872/* 1873 * Deal with a SMP shootdown of other users of the pmap that we are 1874 * trying to dispose of. This can be a bit hairy. 1875 */ 1876static cpumask_t *lazymask; 1877static u_int lazyptd; 1878static volatile u_int lazywait; 1879 1880void pmap_lazyfix_action(void); 1881 1882void 1883pmap_lazyfix_action(void) 1884{ 1885 cpumask_t mymask = PCPU_GET(cpumask); 1886 1887#ifdef COUNT_IPIS 1888 (*ipi_lazypmap_counts[PCPU_GET(cpuid)])++; 1889#endif 1890 if (rcr3() == lazyptd) 1891 load_cr3(PCPU_GET(curpcb)->pcb_cr3); 1892 atomic_clear_int(lazymask, mymask); 1893 atomic_store_rel_int(&lazywait, 1); 1894} 1895 1896static void 1897pmap_lazyfix_self(cpumask_t mymask) 1898{ 1899 1900 if (rcr3() == lazyptd) 1901 load_cr3(PCPU_GET(curpcb)->pcb_cr3); 1902 atomic_clear_int(lazymask, mymask); 1903} 1904 1905 1906static void 1907pmap_lazyfix(pmap_t pmap) 1908{ 1909 cpumask_t mymask, mask; 1910 u_int spins; 1911 1912 while ((mask = pmap->pm_active) != 0) { 1913 spins = 50000000; 1914 mask = mask & -mask; /* Find least significant set bit */ 1915 mtx_lock_spin(&smp_ipi_mtx); 1916#ifdef PAE 1917 lazyptd = vtophys(pmap->pm_pdpt); 1918#else 1919 lazyptd = vtophys(pmap->pm_pdir); 1920#endif 1921 mymask = PCPU_GET(cpumask); 1922 if (mask == mymask) { 1923 lazymask = &pmap->pm_active; 1924 pmap_lazyfix_self(mymask); 1925 } else { 1926 atomic_store_rel_int((u_int *)&lazymask, 1927 (u_int)&pmap->pm_active); 1928 atomic_store_rel_int(&lazywait, 0); 1929 ipi_selected(mask, IPI_LAZYPMAP); 1930 while (lazywait == 0) { 1931 ia32_pause(); 1932 if (--spins == 0) 1933 break; 1934 } 1935 } 1936 mtx_unlock_spin(&smp_ipi_mtx); 1937 if (spins == 0) 1938 printf("pmap_lazyfix: spun for 50000000\n"); 1939 } 1940} 1941 1942#else /* SMP */ 1943 1944/* 1945 * Cleaning up on uniprocessor is easy. For various reasons, we're 1946 * unlikely to have to even execute this code, including the fact 1947 * that the cleanup is deferred until the parent does a wait(2), which 1948 * means that another userland process has run. 1949 */ 1950static void 1951pmap_lazyfix(pmap_t pmap) 1952{ 1953 u_int cr3; 1954 1955 cr3 = vtophys(pmap->pm_pdir); 1956 if (cr3 == rcr3()) { 1957 load_cr3(PCPU_GET(curpcb)->pcb_cr3); 1958 pmap->pm_active &= ~(PCPU_GET(cpumask)); 1959 } 1960} 1961#endif /* SMP */ 1962 1963/* 1964 * Release any resources held by the given physical map. 1965 * Called when a pmap initialized by pmap_pinit is being released. 1966 * Should only be called if the map contains no valid mappings. 1967 */ 1968void 1969pmap_release(pmap_t pmap) 1970{ 1971 vm_page_t m, ptdpg[NPGPTD]; 1972 int i; 1973 1974 KASSERT(pmap->pm_stats.resident_count == 0, 1975 ("pmap_release: pmap resident count %ld != 0", 1976 pmap->pm_stats.resident_count)); 1977 KASSERT(pmap->pm_root == NULL, 1978 ("pmap_release: pmap has reserved page table page(s)")); 1979 1980 pmap_lazyfix(pmap); 1981 mtx_lock_spin(&allpmaps_lock); 1982 LIST_REMOVE(pmap, pm_list); 1983 mtx_unlock_spin(&allpmaps_lock); 1984 1985 for (i = 0; i < NPGPTD; i++) 1986 ptdpg[i] = PHYS_TO_VM_PAGE(pmap->pm_pdir[PTDPTDI + i] & 1987 PG_FRAME); 1988 1989 bzero(pmap->pm_pdir + PTDPTDI, (nkpt + NPGPTD) * 1990 sizeof(*pmap->pm_pdir)); 1991 1992 pmap_qremove((vm_offset_t)pmap->pm_pdir, NPGPTD); 1993 1994 for (i = 0; i < NPGPTD; i++) { 1995 m = ptdpg[i]; 1996#ifdef PAE 1997 KASSERT(VM_PAGE_TO_PHYS(m) == (pmap->pm_pdpt[i] & PG_FRAME), 1998 ("pmap_release: got wrong ptd page")); 1999#endif 2000 m->wire_count--; 2001 atomic_subtract_int(&cnt.v_wire_count, 1); 2002 vm_page_free_zero(m); 2003 } 2004 PMAP_LOCK_DESTROY(pmap); 2005} 2006 2007static int 2008kvm_size(SYSCTL_HANDLER_ARGS) 2009{ 2010 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - KERNBASE; 2011 2012 return (sysctl_handle_long(oidp, &ksize, 0, req)); 2013} 2014SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG|CTLFLAG_RD, 2015 0, 0, kvm_size, "IU", "Size of KVM"); 2016 2017static int 2018kvm_free(SYSCTL_HANDLER_ARGS) 2019{ 2020 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end; 2021 2022 return (sysctl_handle_long(oidp, &kfree, 0, req)); 2023} 2024SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG|CTLFLAG_RD, 2025 0, 0, kvm_free, "IU", "Amount of KVM free"); 2026 2027/* 2028 * grow the number of kernel page table entries, if needed 2029 */ 2030void 2031pmap_growkernel(vm_offset_t addr) 2032{ 2033 vm_paddr_t ptppaddr; 2034 vm_page_t nkpg; 2035 pd_entry_t newpdir; 2036 2037 mtx_assert(&kernel_map->system_mtx, MA_OWNED); 2038 addr = roundup2(addr, NBPDR); 2039 if (addr - 1 >= kernel_map->max_offset) 2040 addr = kernel_map->max_offset; 2041 while (kernel_vm_end < addr) { 2042 if (pdir_pde(PTD, kernel_vm_end)) { 2043 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK; 2044 if (kernel_vm_end - 1 >= kernel_map->max_offset) { 2045 kernel_vm_end = kernel_map->max_offset; 2046 break; 2047 } 2048 continue; 2049 } 2050 2051 nkpg = vm_page_alloc(NULL, kernel_vm_end >> PDRSHIFT, 2052 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | 2053 VM_ALLOC_ZERO); 2054 if (nkpg == NULL) 2055 panic("pmap_growkernel: no memory to grow kernel"); 2056 2057 nkpt++; 2058 2059 if ((nkpg->flags & PG_ZERO) == 0) 2060 pmap_zero_page(nkpg); 2061 ptppaddr = VM_PAGE_TO_PHYS(nkpg); 2062 newpdir = (pd_entry_t) (ptppaddr | PG_V | PG_RW | PG_A | PG_M); 2063 pdir_pde(KPTD, kernel_vm_end) = pgeflag | newpdir; 2064 2065 pmap_kenter_pde(kernel_vm_end, newpdir); 2066 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK; 2067 if (kernel_vm_end - 1 >= kernel_map->max_offset) { 2068 kernel_vm_end = kernel_map->max_offset; 2069 break; 2070 } 2071 } 2072} 2073 2074 2075/*************************************************** 2076 * page management routines. 2077 ***************************************************/ 2078 2079CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE); 2080CTASSERT(_NPCM == 11); 2081 2082static __inline struct pv_chunk * 2083pv_to_chunk(pv_entry_t pv) 2084{ 2085 2086 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK)); 2087} 2088 2089#define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap) 2090 2091#define PC_FREE0_9 0xfffffffful /* Free values for index 0 through 9 */ 2092#define PC_FREE10 0x0000fffful /* Free values for index 10 */ 2093 2094static uint32_t pc_freemask[11] = { 2095 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9, 2096 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9, 2097 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9, 2098 PC_FREE0_9, PC_FREE10 2099}; 2100 2101SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0, 2102 "Current number of pv entries"); 2103 2104#ifdef PV_STATS 2105static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail; 2106 2107SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0, 2108 "Current number of pv entry chunks"); 2109SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0, 2110 "Current number of pv entry chunks allocated"); 2111SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0, 2112 "Current number of pv entry chunks frees"); 2113SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0, 2114 "Number of times tried to get a chunk page but failed."); 2115 2116static long pv_entry_frees, pv_entry_allocs; 2117static int pv_entry_spare; 2118 2119SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0, 2120 "Current number of pv entry frees"); 2121SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0, 2122 "Current number of pv entry allocs"); 2123SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0, 2124 "Current number of spare pv entries"); 2125 2126static int pmap_collect_inactive, pmap_collect_active; 2127 2128SYSCTL_INT(_vm_pmap, OID_AUTO, pmap_collect_inactive, CTLFLAG_RD, &pmap_collect_inactive, 0, 2129 "Current number times pmap_collect called on inactive queue"); 2130SYSCTL_INT(_vm_pmap, OID_AUTO, pmap_collect_active, CTLFLAG_RD, &pmap_collect_active, 0, 2131 "Current number times pmap_collect called on active queue"); 2132#endif 2133 2134/* 2135 * We are in a serious low memory condition. Resort to 2136 * drastic measures to free some pages so we can allocate 2137 * another pv entry chunk. This is normally called to 2138 * unmap inactive pages, and if necessary, active pages. 2139 */ 2140static void 2141pmap_collect(pmap_t locked_pmap, struct vpgqueues *vpq) 2142{ 2143 struct md_page *pvh; 2144 pd_entry_t *pde; 2145 pmap_t pmap; 2146 pt_entry_t *pte, tpte; 2147 pv_entry_t next_pv, pv; 2148 vm_offset_t va; 2149 vm_page_t m, free; 2150 2151 sched_pin(); 2152 TAILQ_FOREACH(m, &vpq->pl, pageq) { 2153 if (m->hold_count || m->busy) 2154 continue; 2155 TAILQ_FOREACH_SAFE(pv, &m->md.pv_list, pv_list, next_pv) { 2156 va = pv->pv_va; 2157 pmap = PV_PMAP(pv); 2158 /* Avoid deadlock and lock recursion. */ 2159 if (pmap > locked_pmap) 2160 PMAP_LOCK(pmap); 2161 else if (pmap != locked_pmap && !PMAP_TRYLOCK(pmap)) 2162 continue; 2163 pmap->pm_stats.resident_count--; 2164 pde = pmap_pde(pmap, va); 2165 KASSERT((*pde & PG_PS) == 0, ("pmap_collect: found" 2166 " a 4mpage in page %p's pv list", m)); 2167 pte = pmap_pte_quick(pmap, va); 2168 tpte = pte_load_clear(pte); 2169 KASSERT((tpte & PG_W) == 0, 2170 ("pmap_collect: wired pte %#jx", (uintmax_t)tpte)); 2171 if (tpte & PG_A) 2172 vm_page_flag_set(m, PG_REFERENCED); 2173 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) 2174 vm_page_dirty(m); 2175 free = NULL; 2176 pmap_unuse_pt(pmap, va, &free); 2177 pmap_invalidate_page(pmap, va); 2178 pmap_free_zero_pages(free); 2179 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list); 2180 if (TAILQ_EMPTY(&m->md.pv_list)) { 2181 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 2182 if (TAILQ_EMPTY(&pvh->pv_list)) 2183 vm_page_flag_clear(m, PG_WRITEABLE); 2184 } 2185 free_pv_entry(pmap, pv); 2186 if (pmap != locked_pmap) 2187 PMAP_UNLOCK(pmap); 2188 } 2189 } 2190 sched_unpin(); 2191} 2192 2193 2194/* 2195 * free the pv_entry back to the free list 2196 */ 2197static void 2198free_pv_entry(pmap_t pmap, pv_entry_t pv) 2199{ 2200 vm_page_t m; 2201 struct pv_chunk *pc; 2202 int idx, field, bit; 2203 2204 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2205 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2206 PV_STAT(pv_entry_frees++); 2207 PV_STAT(pv_entry_spare++); 2208 pv_entry_count--; 2209 pc = pv_to_chunk(pv); 2210 idx = pv - &pc->pc_pventry[0]; 2211 field = idx / 32; 2212 bit = idx % 32; 2213 pc->pc_map[field] |= 1ul << bit; 2214 /* move to head of list */ 2215 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 2216 for (idx = 0; idx < _NPCM; idx++) 2217 if (pc->pc_map[idx] != pc_freemask[idx]) { 2218 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list); 2219 return; 2220 } 2221 PV_STAT(pv_entry_spare -= _NPCPV); 2222 PV_STAT(pc_chunk_count--); 2223 PV_STAT(pc_chunk_frees++); 2224 /* entire chunk is free, return it */ 2225 m = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc)); 2226 pmap_qremove((vm_offset_t)pc, 1); 2227 vm_page_unwire(m, 0); 2228 vm_page_free(m); 2229 pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc); 2230} 2231 2232/* 2233 * get a new pv_entry, allocating a block from the system 2234 * when needed. 2235 */ 2236static pv_entry_t 2237get_pv_entry(pmap_t pmap, int try) 2238{ 2239 static const struct timeval printinterval = { 60, 0 }; 2240 static struct timeval lastprint; 2241 static vm_pindex_t colour; 2242 struct vpgqueues *pq; 2243 int bit, field; 2244 pv_entry_t pv; 2245 struct pv_chunk *pc; 2246 vm_page_t m; 2247 2248 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2249 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2250 PV_STAT(pv_entry_allocs++); 2251 pv_entry_count++; 2252 if (pv_entry_count > pv_entry_high_water) 2253 if (ratecheck(&lastprint, &printinterval)) 2254 printf("Approaching the limit on PV entries, consider " 2255 "increasing either the vm.pmap.shpgperproc or the " 2256 "vm.pmap.pv_entry_max tunable.\n"); 2257 pq = NULL; 2258retry: 2259 pc = TAILQ_FIRST(&pmap->pm_pvchunk); 2260 if (pc != NULL) { 2261 for (field = 0; field < _NPCM; field++) { 2262 if (pc->pc_map[field]) { 2263 bit = bsfl(pc->pc_map[field]); 2264 break; 2265 } 2266 } 2267 if (field < _NPCM) { 2268 pv = &pc->pc_pventry[field * 32 + bit]; 2269 pc->pc_map[field] &= ~(1ul << bit); 2270 /* If this was the last item, move it to tail */ 2271 for (field = 0; field < _NPCM; field++) 2272 if (pc->pc_map[field] != 0) { 2273 PV_STAT(pv_entry_spare--); 2274 return (pv); /* not full, return */ 2275 } 2276 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 2277 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list); 2278 PV_STAT(pv_entry_spare--); 2279 return (pv); 2280 } 2281 } 2282 /* 2283 * Access to the ptelist "pv_vafree" is synchronized by the page 2284 * queues lock. If "pv_vafree" is currently non-empty, it will 2285 * remain non-empty until pmap_ptelist_alloc() completes. 2286 */ 2287 if (pv_vafree == 0 || (m = vm_page_alloc(NULL, colour, (pq == 2288 &vm_page_queues[PQ_ACTIVE] ? VM_ALLOC_SYSTEM : VM_ALLOC_NORMAL) | 2289 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) { 2290 if (try) { 2291 pv_entry_count--; 2292 PV_STAT(pc_chunk_tryfail++); 2293 return (NULL); 2294 } 2295 /* 2296 * Reclaim pv entries: At first, destroy mappings to 2297 * inactive pages. After that, if a pv chunk entry 2298 * is still needed, destroy mappings to active pages. 2299 */ 2300 if (pq == NULL) { 2301 PV_STAT(pmap_collect_inactive++); 2302 pq = &vm_page_queues[PQ_INACTIVE]; 2303 } else if (pq == &vm_page_queues[PQ_INACTIVE]) { 2304 PV_STAT(pmap_collect_active++); 2305 pq = &vm_page_queues[PQ_ACTIVE]; 2306 } else 2307 panic("get_pv_entry: increase vm.pmap.shpgperproc"); 2308 pmap_collect(pmap, pq); 2309 goto retry; 2310 } 2311 PV_STAT(pc_chunk_count++); 2312 PV_STAT(pc_chunk_allocs++); 2313 colour++; 2314 pc = (struct pv_chunk *)pmap_ptelist_alloc(&pv_vafree); 2315 pmap_qenter((vm_offset_t)pc, &m, 1); 2316 pc->pc_pmap = pmap; 2317 pc->pc_map[0] = pc_freemask[0] & ~1ul; /* preallocated bit 0 */ 2318 for (field = 1; field < _NPCM; field++) 2319 pc->pc_map[field] = pc_freemask[field]; 2320 pv = &pc->pc_pventry[0]; 2321 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list); 2322 PV_STAT(pv_entry_spare += _NPCPV - 1); 2323 return (pv); 2324} 2325 2326static __inline pv_entry_t 2327pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va) 2328{ 2329 pv_entry_t pv; 2330 2331 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2332 TAILQ_FOREACH(pv, &pvh->pv_list, pv_list) { 2333 if (pmap == PV_PMAP(pv) && va == pv->pv_va) { 2334 TAILQ_REMOVE(&pvh->pv_list, pv, pv_list); 2335 break; 2336 } 2337 } 2338 return (pv); 2339} 2340 2341static void 2342pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa) 2343{ 2344 struct md_page *pvh; 2345 pv_entry_t pv; 2346 vm_offset_t va_last; 2347 vm_page_t m; 2348 2349 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2350 KASSERT((pa & PDRMASK) == 0, 2351 ("pmap_pv_demote_pde: pa is not 4mpage aligned")); 2352 2353 /* 2354 * Transfer the 4mpage's pv entry for this mapping to the first 2355 * page's pv list. 2356 */ 2357 pvh = pa_to_pvh(pa); 2358 va = trunc_4mpage(va); 2359 pv = pmap_pvh_remove(pvh, pmap, va); 2360 KASSERT(pv != NULL, ("pmap_pv_demote_pde: pv not found")); 2361 m = PHYS_TO_VM_PAGE(pa); 2362 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list); 2363 /* Instantiate the remaining NPTEPG - 1 pv entries. */ 2364 va_last = va + NBPDR - PAGE_SIZE; 2365 do { 2366 m++; 2367 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 2368 ("pmap_pv_demote_pde: page %p is not managed", m)); 2369 va += PAGE_SIZE; 2370 pmap_insert_entry(pmap, va, m); 2371 } while (va < va_last); 2372} 2373 2374static void 2375pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa) 2376{ 2377 struct md_page *pvh; 2378 pv_entry_t pv; 2379 vm_offset_t va_last; 2380 vm_page_t m; 2381 2382 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2383 KASSERT((pa & PDRMASK) == 0, 2384 ("pmap_pv_promote_pde: pa is not 4mpage aligned")); 2385 2386 /* 2387 * Transfer the first page's pv entry for this mapping to the 2388 * 4mpage's pv list. Aside from avoiding the cost of a call 2389 * to get_pv_entry(), a transfer avoids the possibility that 2390 * get_pv_entry() calls pmap_collect() and that pmap_collect() 2391 * removes one of the mappings that is being promoted. 2392 */ 2393 m = PHYS_TO_VM_PAGE(pa); 2394 va = trunc_4mpage(va); 2395 pv = pmap_pvh_remove(&m->md, pmap, va); 2396 KASSERT(pv != NULL, ("pmap_pv_promote_pde: pv not found")); 2397 pvh = pa_to_pvh(pa); 2398 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_list); 2399 /* Free the remaining NPTEPG - 1 pv entries. */ 2400 va_last = va + NBPDR - PAGE_SIZE; 2401 do { 2402 m++; 2403 va += PAGE_SIZE; 2404 pmap_pvh_free(&m->md, pmap, va); 2405 } while (va < va_last); 2406} 2407 2408static void 2409pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va) 2410{ 2411 pv_entry_t pv; 2412 2413 pv = pmap_pvh_remove(pvh, pmap, va); 2414 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found")); 2415 free_pv_entry(pmap, pv); 2416} 2417 2418static void 2419pmap_remove_entry(pmap_t pmap, vm_page_t m, vm_offset_t va) 2420{ 2421 struct md_page *pvh; 2422 2423 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2424 pmap_pvh_free(&m->md, pmap, va); 2425 if (TAILQ_EMPTY(&m->md.pv_list)) { 2426 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 2427 if (TAILQ_EMPTY(&pvh->pv_list)) 2428 vm_page_flag_clear(m, PG_WRITEABLE); 2429 } 2430} 2431 2432/* 2433 * Create a pv entry for page at pa for 2434 * (pmap, va). 2435 */ 2436static void 2437pmap_insert_entry(pmap_t pmap, vm_offset_t va, vm_page_t m) 2438{ 2439 pv_entry_t pv; 2440 2441 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2442 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2443 pv = get_pv_entry(pmap, FALSE); 2444 pv->pv_va = va; 2445 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list); 2446} 2447 2448/* 2449 * Conditionally create a pv entry. 2450 */ 2451static boolean_t 2452pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m) 2453{ 2454 pv_entry_t pv; 2455 2456 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2457 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2458 if (pv_entry_count < pv_entry_high_water && 2459 (pv = get_pv_entry(pmap, TRUE)) != NULL) { 2460 pv->pv_va = va; 2461 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list); 2462 return (TRUE); 2463 } else 2464 return (FALSE); 2465} 2466 2467/* 2468 * Create the pv entries for each of the pages within a superpage. 2469 */ 2470static boolean_t 2471pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa) 2472{ 2473 struct md_page *pvh; 2474 pv_entry_t pv; 2475 2476 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2477 if (pv_entry_count < pv_entry_high_water && 2478 (pv = get_pv_entry(pmap, TRUE)) != NULL) { 2479 pv->pv_va = va; 2480 pvh = pa_to_pvh(pa); 2481 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_list); 2482 return (TRUE); 2483 } else 2484 return (FALSE); 2485} 2486 2487/* 2488 * Fills a page table page with mappings to consecutive physical pages. 2489 */ 2490static void 2491pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte) 2492{ 2493 pt_entry_t *pte; 2494 2495 for (pte = firstpte; pte < firstpte + NPTEPG; pte++) { 2496 *pte = newpte; 2497 newpte += PAGE_SIZE; 2498 } 2499} 2500 2501/* 2502 * Tries to demote a 2- or 4MB page mapping. If demotion fails, the 2503 * 2- or 4MB page mapping is invalidated. 2504 */ 2505static boolean_t 2506pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va) 2507{ 2508 pd_entry_t newpde, oldpde; 2509 pt_entry_t *firstpte, newpte; 2510 vm_paddr_t mptepa; 2511 vm_page_t free, mpte; 2512 2513 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2514 oldpde = *pde; 2515 KASSERT((oldpde & (PG_PS | PG_V)) == (PG_PS | PG_V), 2516 ("pmap_demote_pde: oldpde is missing PG_PS and/or PG_V")); 2517 mpte = pmap_lookup_pt_page(pmap, va); 2518 if (mpte != NULL) 2519 pmap_remove_pt_page(pmap, mpte); 2520 else { 2521 KASSERT((oldpde & PG_W) == 0, 2522 ("pmap_demote_pde: page table page for a wired mapping" 2523 " is missing")); 2524 2525 /* 2526 * Invalidate the 2- or 4MB page mapping and return 2527 * "failure" if the mapping was never accessed or the 2528 * allocation of the new page table page fails. 2529 */ 2530 if ((oldpde & PG_A) == 0 || (mpte = vm_page_alloc(NULL, 2531 va >> PDRSHIFT, VM_ALLOC_NOOBJ | VM_ALLOC_NORMAL | 2532 VM_ALLOC_WIRED)) == NULL) { 2533 free = NULL; 2534 pmap_remove_pde(pmap, pde, trunc_4mpage(va), &free); 2535 pmap_invalidate_page(pmap, trunc_4mpage(va)); 2536 pmap_free_zero_pages(free); 2537 CTR2(KTR_PMAP, "pmap_demote_pde: failure for va %#x" 2538 " in pmap %p", va, pmap); 2539 return (FALSE); 2540 } 2541 if (va < VM_MAXUSER_ADDRESS) 2542 pmap->pm_stats.resident_count++; 2543 } 2544 mptepa = VM_PAGE_TO_PHYS(mpte); 2545 2546 /* 2547 * If the page mapping is in the kernel's address space, then the 2548 * KPTmap can provide access to the page table page. Otherwise, 2549 * temporarily map the page table page (mpte) into the kernel's 2550 * address space at either PADDR1 or PADDR2. 2551 */ 2552 if (va >= KERNBASE) 2553 firstpte = &KPTmap[i386_btop(trunc_4mpage(va))]; 2554 else if (curthread->td_pinned > 0 && mtx_owned(&vm_page_queue_mtx)) { 2555 if ((*PMAP1 & PG_FRAME) != mptepa) { 2556 *PMAP1 = mptepa | PG_RW | PG_V | PG_A | PG_M; 2557#ifdef SMP 2558 PMAP1cpu = PCPU_GET(cpuid); 2559#endif 2560 invlcaddr(PADDR1); 2561 PMAP1changed++; 2562 } else 2563#ifdef SMP 2564 if (PMAP1cpu != PCPU_GET(cpuid)) { 2565 PMAP1cpu = PCPU_GET(cpuid); 2566 invlcaddr(PADDR1); 2567 PMAP1changedcpu++; 2568 } else 2569#endif 2570 PMAP1unchanged++; 2571 firstpte = PADDR1; 2572 } else { 2573 mtx_lock(&PMAP2mutex); 2574 if ((*PMAP2 & PG_FRAME) != mptepa) { 2575 *PMAP2 = mptepa | PG_RW | PG_V | PG_A | PG_M; 2576 pmap_invalidate_page(kernel_pmap, (vm_offset_t)PADDR2); 2577 } 2578 firstpte = PADDR2; 2579 } 2580 newpde = mptepa | PG_M | PG_A | (oldpde & PG_U) | PG_RW | PG_V; 2581 KASSERT((oldpde & PG_A) != 0, 2582 ("pmap_demote_pde: oldpde is missing PG_A")); 2583 KASSERT((oldpde & (PG_M | PG_RW)) != PG_RW, 2584 ("pmap_demote_pde: oldpde is missing PG_M")); 2585 newpte = oldpde & ~PG_PS; 2586 if ((newpte & PG_PDE_PAT) != 0) 2587 newpte ^= PG_PDE_PAT | PG_PTE_PAT; 2588 2589 /* 2590 * If the page table page is new, initialize it. 2591 */ 2592 if (mpte->wire_count == 1) { 2593 mpte->wire_count = NPTEPG; 2594 pmap_fill_ptp(firstpte, newpte); 2595 } 2596 KASSERT((*firstpte & PG_FRAME) == (newpte & PG_FRAME), 2597 ("pmap_demote_pde: firstpte and newpte map different physical" 2598 " addresses")); 2599 2600 /* 2601 * If the mapping has changed attributes, update the page table 2602 * entries. 2603 */ 2604 if ((*firstpte & PG_PTE_PROMOTE) != (newpte & PG_PTE_PROMOTE)) 2605 pmap_fill_ptp(firstpte, newpte); 2606 2607 /* 2608 * Demote the mapping. This pmap is locked. The old PDE has 2609 * PG_A set. If the old PDE has PG_RW set, it also has PG_M 2610 * set. Thus, there is no danger of a race with another 2611 * processor changing the setting of PG_A and/or PG_M between 2612 * the read above and the store below. 2613 */ 2614 if (workaround_erratum383) 2615 pmap_update_pde(pmap, va, pde, newpde); 2616 else if (pmap == kernel_pmap) 2617 pmap_kenter_pde(va, newpde); 2618 else 2619 pde_store(pde, newpde); 2620 if (firstpte == PADDR2) 2621 mtx_unlock(&PMAP2mutex); 2622 2623 /* 2624 * Invalidate the recursive mapping of the page table page. 2625 */ 2626 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va)); 2627 2628 /* 2629 * Demote the pv entry. This depends on the earlier demotion 2630 * of the mapping. Specifically, the (re)creation of a per- 2631 * page pv entry might trigger the execution of pmap_collect(), 2632 * which might reclaim a newly (re)created per-page pv entry 2633 * and destroy the associated mapping. In order to destroy 2634 * the mapping, the PDE must have already changed from mapping 2635 * the 2mpage to referencing the page table page. 2636 */ 2637 if ((oldpde & PG_MANAGED) != 0) 2638 pmap_pv_demote_pde(pmap, va, oldpde & PG_PS_FRAME); 2639 2640 pmap_pde_demotions++; 2641 CTR2(KTR_PMAP, "pmap_demote_pde: success for va %#x" 2642 " in pmap %p", va, pmap); 2643 return (TRUE); 2644} 2645 2646/* 2647 * pmap_remove_pde: do the things to unmap a superpage in a process 2648 */ 2649static void 2650pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva, 2651 vm_page_t *free) 2652{ 2653 struct md_page *pvh; 2654 pd_entry_t oldpde; 2655 vm_offset_t eva, va; 2656 vm_page_t m, mpte; 2657 2658 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2659 KASSERT((sva & PDRMASK) == 0, 2660 ("pmap_remove_pde: sva is not 4mpage aligned")); 2661 oldpde = pte_load_clear(pdq); 2662 if (oldpde & PG_W) 2663 pmap->pm_stats.wired_count -= NBPDR / PAGE_SIZE; 2664 2665 /* 2666 * Machines that don't support invlpg, also don't support 2667 * PG_G. 2668 */ 2669 if (oldpde & PG_G) 2670 pmap_invalidate_page(kernel_pmap, sva); 2671 pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE; 2672 if (oldpde & PG_MANAGED) { 2673 pvh = pa_to_pvh(oldpde & PG_PS_FRAME); 2674 pmap_pvh_free(pvh, pmap, sva); 2675 eva = sva + NBPDR; 2676 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME); 2677 va < eva; va += PAGE_SIZE, m++) { 2678 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW)) 2679 vm_page_dirty(m); 2680 if (oldpde & PG_A) 2681 vm_page_flag_set(m, PG_REFERENCED); 2682 if (TAILQ_EMPTY(&m->md.pv_list) && 2683 TAILQ_EMPTY(&pvh->pv_list)) 2684 vm_page_flag_clear(m, PG_WRITEABLE); 2685 } 2686 } 2687 if (pmap == kernel_pmap) { 2688 if (!pmap_demote_pde(pmap, pdq, sva)) 2689 panic("pmap_remove_pde: failed demotion"); 2690 } else { 2691 mpte = pmap_lookup_pt_page(pmap, sva); 2692 if (mpte != NULL) { 2693 pmap_remove_pt_page(pmap, mpte); 2694 pmap->pm_stats.resident_count--; 2695 KASSERT(mpte->wire_count == NPTEPG, 2696 ("pmap_remove_pde: pte page wire count error")); 2697 mpte->wire_count = 0; 2698 pmap_add_delayed_free_list(mpte, free, FALSE); 2699 atomic_subtract_int(&cnt.v_wire_count, 1); 2700 } 2701 } 2702} 2703 2704/* 2705 * pmap_remove_pte: do the things to unmap a page in a process 2706 */ 2707static int 2708pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t va, vm_page_t *free) 2709{ 2710 pt_entry_t oldpte; 2711 vm_page_t m; 2712 2713 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2714 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2715 oldpte = pte_load_clear(ptq); 2716 if (oldpte & PG_W) 2717 pmap->pm_stats.wired_count -= 1; 2718 /* 2719 * Machines that don't support invlpg, also don't support 2720 * PG_G. 2721 */ 2722 if (oldpte & PG_G) 2723 pmap_invalidate_page(kernel_pmap, va); 2724 pmap->pm_stats.resident_count -= 1; 2725 if (oldpte & PG_MANAGED) { 2726 m = PHYS_TO_VM_PAGE(oldpte & PG_FRAME); 2727 if ((oldpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) 2728 vm_page_dirty(m); 2729 if (oldpte & PG_A) 2730 vm_page_flag_set(m, PG_REFERENCED); 2731 pmap_remove_entry(pmap, m, va); 2732 } 2733 return (pmap_unuse_pt(pmap, va, free)); 2734} 2735 2736/* 2737 * Remove a single page from a process address space 2738 */ 2739static void 2740pmap_remove_page(pmap_t pmap, vm_offset_t va, vm_page_t *free) 2741{ 2742 pt_entry_t *pte; 2743 2744 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2745 KASSERT(curthread->td_pinned > 0, ("curthread not pinned")); 2746 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2747 if ((pte = pmap_pte_quick(pmap, va)) == NULL || *pte == 0) 2748 return; 2749 pmap_remove_pte(pmap, pte, va, free); 2750 pmap_invalidate_page(pmap, va); 2751} 2752 2753/* 2754 * Remove the given range of addresses from the specified map. 2755 * 2756 * It is assumed that the start and end are properly 2757 * rounded to the page size. 2758 */ 2759void 2760pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 2761{ 2762 vm_offset_t pdnxt; 2763 pd_entry_t ptpaddr; 2764 pt_entry_t *pte; 2765 vm_page_t free = NULL; 2766 int anyvalid; 2767 2768 /* 2769 * Perform an unsynchronized read. This is, however, safe. 2770 */ 2771 if (pmap->pm_stats.resident_count == 0) 2772 return; 2773 2774 anyvalid = 0; 2775 2776 vm_page_lock_queues(); 2777 sched_pin(); 2778 PMAP_LOCK(pmap); 2779 2780 /* 2781 * special handling of removing one page. a very 2782 * common operation and easy to short circuit some 2783 * code. 2784 */ 2785 if ((sva + PAGE_SIZE == eva) && 2786 ((pmap->pm_pdir[(sva >> PDRSHIFT)] & PG_PS) == 0)) { 2787 pmap_remove_page(pmap, sva, &free); 2788 goto out; 2789 } 2790 2791 for (; sva < eva; sva = pdnxt) { 2792 unsigned pdirindex; 2793 2794 /* 2795 * Calculate index for next page table. 2796 */ 2797 pdnxt = (sva + NBPDR) & ~PDRMASK; 2798 if (pdnxt < sva) 2799 pdnxt = eva; 2800 if (pmap->pm_stats.resident_count == 0) 2801 break; 2802 2803 pdirindex = sva >> PDRSHIFT; 2804 ptpaddr = pmap->pm_pdir[pdirindex]; 2805 2806 /* 2807 * Weed out invalid mappings. Note: we assume that the page 2808 * directory table is always allocated, and in kernel virtual. 2809 */ 2810 if (ptpaddr == 0) 2811 continue; 2812 2813 /* 2814 * Check for large page. 2815 */ 2816 if ((ptpaddr & PG_PS) != 0) { 2817 /* 2818 * Are we removing the entire large page? If not, 2819 * demote the mapping and fall through. 2820 */ 2821 if (sva + NBPDR == pdnxt && eva >= pdnxt) { 2822 /* 2823 * The TLB entry for a PG_G mapping is 2824 * invalidated by pmap_remove_pde(). 2825 */ 2826 if ((ptpaddr & PG_G) == 0) 2827 anyvalid = 1; 2828 pmap_remove_pde(pmap, 2829 &pmap->pm_pdir[pdirindex], sva, &free); 2830 continue; 2831 } else if (!pmap_demote_pde(pmap, 2832 &pmap->pm_pdir[pdirindex], sva)) { 2833 /* The large page mapping was destroyed. */ 2834 continue; 2835 } 2836 } 2837 2838 /* 2839 * Limit our scan to either the end of the va represented 2840 * by the current page table page, or to the end of the 2841 * range being removed. 2842 */ 2843 if (pdnxt > eva) 2844 pdnxt = eva; 2845 2846 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++, 2847 sva += PAGE_SIZE) { 2848 if (*pte == 0) 2849 continue; 2850 2851 /* 2852 * The TLB entry for a PG_G mapping is invalidated 2853 * by pmap_remove_pte(). 2854 */ 2855 if ((*pte & PG_G) == 0) 2856 anyvalid = 1; 2857 if (pmap_remove_pte(pmap, pte, sva, &free)) 2858 break; 2859 } 2860 } 2861out: 2862 sched_unpin(); 2863 if (anyvalid) 2864 pmap_invalidate_all(pmap); 2865 vm_page_unlock_queues(); 2866 PMAP_UNLOCK(pmap); 2867 pmap_free_zero_pages(free); 2868} 2869 2870/* 2871 * Routine: pmap_remove_all 2872 * Function: 2873 * Removes this physical page from 2874 * all physical maps in which it resides. 2875 * Reflects back modify bits to the pager. 2876 * 2877 * Notes: 2878 * Original versions of this routine were very 2879 * inefficient because they iteratively called 2880 * pmap_remove (slow...) 2881 */ 2882 2883void 2884pmap_remove_all(vm_page_t m) 2885{ 2886 struct md_page *pvh; 2887 pv_entry_t pv; 2888 pmap_t pmap; 2889 pt_entry_t *pte, tpte; 2890 pd_entry_t *pde; 2891 vm_offset_t va; 2892 vm_page_t free; 2893 2894 KASSERT((m->flags & PG_FICTITIOUS) == 0, 2895 ("pmap_remove_all: page %p is fictitious", m)); 2896 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2897 sched_pin(); 2898 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 2899 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) { 2900 va = pv->pv_va; 2901 pmap = PV_PMAP(pv); 2902 PMAP_LOCK(pmap); 2903 pde = pmap_pde(pmap, va); 2904 (void)pmap_demote_pde(pmap, pde, va); 2905 PMAP_UNLOCK(pmap); 2906 } 2907 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) { 2908 pmap = PV_PMAP(pv); 2909 PMAP_LOCK(pmap); 2910 pmap->pm_stats.resident_count--; 2911 pde = pmap_pde(pmap, pv->pv_va); 2912 KASSERT((*pde & PG_PS) == 0, ("pmap_remove_all: found" 2913 " a 4mpage in page %p's pv list", m)); 2914 pte = pmap_pte_quick(pmap, pv->pv_va); 2915 tpte = pte_load_clear(pte); 2916 if (tpte & PG_W) 2917 pmap->pm_stats.wired_count--; 2918 if (tpte & PG_A) 2919 vm_page_flag_set(m, PG_REFERENCED); 2920 2921 /* 2922 * Update the vm_page_t clean and reference bits. 2923 */ 2924 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) 2925 vm_page_dirty(m); 2926 free = NULL; 2927 pmap_unuse_pt(pmap, pv->pv_va, &free); 2928 pmap_invalidate_page(pmap, pv->pv_va); 2929 pmap_free_zero_pages(free); 2930 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list); 2931 free_pv_entry(pmap, pv); 2932 PMAP_UNLOCK(pmap); 2933 } 2934 vm_page_flag_clear(m, PG_WRITEABLE); 2935 sched_unpin(); 2936} 2937 2938/* 2939 * pmap_protect_pde: do the things to protect a 4mpage in a process 2940 */ 2941static boolean_t 2942pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva, vm_prot_t prot) 2943{ 2944 pd_entry_t newpde, oldpde; 2945 vm_offset_t eva, va; 2946 vm_page_t m; 2947 boolean_t anychanged; 2948 2949 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2950 KASSERT((sva & PDRMASK) == 0, 2951 ("pmap_protect_pde: sva is not 4mpage aligned")); 2952 anychanged = FALSE; 2953retry: 2954 oldpde = newpde = *pde; 2955 if (oldpde & PG_MANAGED) { 2956 eva = sva + NBPDR; 2957 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME); 2958 va < eva; va += PAGE_SIZE, m++) { 2959 /* 2960 * In contrast to the analogous operation on a 4KB page 2961 * mapping, the mapping's PG_A flag is not cleared and 2962 * the page's PG_REFERENCED flag is not set. The 2963 * reason is that pmap_demote_pde() expects that a 2/4MB 2964 * page mapping with a stored page table page has PG_A 2965 * set. 2966 */ 2967 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW)) 2968 vm_page_dirty(m); 2969 } 2970 } 2971 if ((prot & VM_PROT_WRITE) == 0) 2972 newpde &= ~(PG_RW | PG_M); 2973#ifdef PAE 2974 if ((prot & VM_PROT_EXECUTE) == 0) 2975 newpde |= pg_nx; 2976#endif 2977 if (newpde != oldpde) { 2978 if (!pde_cmpset(pde, oldpde, newpde)) 2979 goto retry; 2980 if (oldpde & PG_G) 2981 pmap_invalidate_page(pmap, sva); 2982 else 2983 anychanged = TRUE; 2984 } 2985 return (anychanged); 2986} 2987 2988/* 2989 * Set the physical protection on the 2990 * specified range of this map as requested. 2991 */ 2992void 2993pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot) 2994{ 2995 vm_offset_t pdnxt; 2996 pd_entry_t ptpaddr; 2997 pt_entry_t *pte; 2998 int anychanged; 2999 3000 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 3001 pmap_remove(pmap, sva, eva); 3002 return; 3003 } 3004 3005#ifdef PAE 3006 if ((prot & (VM_PROT_WRITE|VM_PROT_EXECUTE)) == 3007 (VM_PROT_WRITE|VM_PROT_EXECUTE)) 3008 return; 3009#else 3010 if (prot & VM_PROT_WRITE) 3011 return; 3012#endif 3013 3014 anychanged = 0; 3015 3016 vm_page_lock_queues(); 3017 sched_pin(); 3018 PMAP_LOCK(pmap); 3019 for (; sva < eva; sva = pdnxt) { 3020 pt_entry_t obits, pbits; 3021 unsigned pdirindex; 3022 3023 pdnxt = (sva + NBPDR) & ~PDRMASK; 3024 if (pdnxt < sva) 3025 pdnxt = eva; 3026 3027 pdirindex = sva >> PDRSHIFT; 3028 ptpaddr = pmap->pm_pdir[pdirindex]; 3029 3030 /* 3031 * Weed out invalid mappings. Note: we assume that the page 3032 * directory table is always allocated, and in kernel virtual. 3033 */ 3034 if (ptpaddr == 0) 3035 continue; 3036 3037 /* 3038 * Check for large page. 3039 */ 3040 if ((ptpaddr & PG_PS) != 0) { 3041 /* 3042 * Are we protecting the entire large page? If not, 3043 * demote the mapping and fall through. 3044 */ 3045 if (sva + NBPDR == pdnxt && eva >= pdnxt) { 3046 /* 3047 * The TLB entry for a PG_G mapping is 3048 * invalidated by pmap_protect_pde(). 3049 */ 3050 if (pmap_protect_pde(pmap, 3051 &pmap->pm_pdir[pdirindex], sva, prot)) 3052 anychanged = 1; 3053 continue; 3054 } else if (!pmap_demote_pde(pmap, 3055 &pmap->pm_pdir[pdirindex], sva)) { 3056 /* The large page mapping was destroyed. */ 3057 continue; 3058 } 3059 } 3060 3061 if (pdnxt > eva) 3062 pdnxt = eva; 3063 3064 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++, 3065 sva += PAGE_SIZE) { 3066 vm_page_t m; 3067 3068retry: 3069 /* 3070 * Regardless of whether a pte is 32 or 64 bits in 3071 * size, PG_RW, PG_A, and PG_M are among the least 3072 * significant 32 bits. 3073 */ 3074 obits = pbits = *pte; 3075 if ((pbits & PG_V) == 0) 3076 continue; 3077 if (pbits & PG_MANAGED) { 3078 m = NULL; 3079 if (pbits & PG_A) { 3080 m = PHYS_TO_VM_PAGE(pbits & PG_FRAME); 3081 vm_page_flag_set(m, PG_REFERENCED); 3082 pbits &= ~PG_A; 3083 } 3084 if ((pbits & (PG_M | PG_RW)) == (PG_M | PG_RW)) { 3085 if (m == NULL) 3086 m = PHYS_TO_VM_PAGE(pbits & PG_FRAME); 3087 vm_page_dirty(m); 3088 } 3089 } 3090 3091 if ((prot & VM_PROT_WRITE) == 0) 3092 pbits &= ~(PG_RW | PG_M); 3093#ifdef PAE 3094 if ((prot & VM_PROT_EXECUTE) == 0) 3095 pbits |= pg_nx; 3096#endif 3097 3098 if (pbits != obits) { 3099#ifdef PAE 3100 if (!atomic_cmpset_64(pte, obits, pbits)) 3101 goto retry; 3102#else 3103 if (!atomic_cmpset_int((u_int *)pte, obits, 3104 pbits)) 3105 goto retry; 3106#endif 3107 if (obits & PG_G) 3108 pmap_invalidate_page(pmap, sva); 3109 else 3110 anychanged = 1; 3111 } 3112 } 3113 } 3114 sched_unpin(); 3115 if (anychanged) 3116 pmap_invalidate_all(pmap); 3117 vm_page_unlock_queues(); 3118 PMAP_UNLOCK(pmap); 3119} 3120 3121/* 3122 * Tries to promote the 512 or 1024, contiguous 4KB page mappings that are 3123 * within a single page table page (PTP) to a single 2- or 4MB page mapping. 3124 * For promotion to occur, two conditions must be met: (1) the 4KB page 3125 * mappings must map aligned, contiguous physical memory and (2) the 4KB page 3126 * mappings must have identical characteristics. 3127 * 3128 * Managed (PG_MANAGED) mappings within the kernel address space are not 3129 * promoted. The reason is that kernel PDEs are replicated in each pmap but 3130 * pmap_clear_ptes() and pmap_ts_referenced() only read the PDE from the kernel 3131 * pmap. 3132 */ 3133static void 3134pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va) 3135{ 3136 pd_entry_t newpde; 3137 pt_entry_t *firstpte, oldpte, pa, *pte; 3138 vm_offset_t oldpteva; 3139 vm_page_t mpte; 3140 3141 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 3142 3143 /* 3144 * Examine the first PTE in the specified PTP. Abort if this PTE is 3145 * either invalid, unused, or does not map the first 4KB physical page 3146 * within a 2- or 4MB page. 3147 */ 3148 firstpte = pmap_pte_quick(pmap, trunc_4mpage(va)); 3149setpde: 3150 newpde = *firstpte; 3151 if ((newpde & ((PG_FRAME & PDRMASK) | PG_A | PG_V)) != (PG_A | PG_V)) { 3152 pmap_pde_p_failures++; 3153 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x" 3154 " in pmap %p", va, pmap); 3155 return; 3156 } 3157 if ((*firstpte & PG_MANAGED) != 0 && pmap == kernel_pmap) { 3158 pmap_pde_p_failures++; 3159 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x" 3160 " in pmap %p", va, pmap); 3161 return; 3162 } 3163 if ((newpde & (PG_M | PG_RW)) == PG_RW) { 3164 /* 3165 * When PG_M is already clear, PG_RW can be cleared without 3166 * a TLB invalidation. 3167 */ 3168 if (!atomic_cmpset_int((u_int *)firstpte, newpde, newpde & 3169 ~PG_RW)) 3170 goto setpde; 3171 newpde &= ~PG_RW; 3172 } 3173 3174 /* 3175 * Examine each of the other PTEs in the specified PTP. Abort if this 3176 * PTE maps an unexpected 4KB physical page or does not have identical 3177 * characteristics to the first PTE. 3178 */ 3179 pa = (newpde & (PG_PS_FRAME | PG_A | PG_V)) + NBPDR - PAGE_SIZE; 3180 for (pte = firstpte + NPTEPG - 1; pte > firstpte; pte--) { 3181setpte: 3182 oldpte = *pte; 3183 if ((oldpte & (PG_FRAME | PG_A | PG_V)) != pa) { 3184 pmap_pde_p_failures++; 3185 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x" 3186 " in pmap %p", va, pmap); 3187 return; 3188 } 3189 if ((oldpte & (PG_M | PG_RW)) == PG_RW) { 3190 /* 3191 * When PG_M is already clear, PG_RW can be cleared 3192 * without a TLB invalidation. 3193 */ 3194 if (!atomic_cmpset_int((u_int *)pte, oldpte, 3195 oldpte & ~PG_RW)) 3196 goto setpte; 3197 oldpte &= ~PG_RW; 3198 oldpteva = (oldpte & PG_FRAME & PDRMASK) | 3199 (va & ~PDRMASK); 3200 CTR2(KTR_PMAP, "pmap_promote_pde: protect for va %#x" 3201 " in pmap %p", oldpteva, pmap); 3202 } 3203 if ((oldpte & PG_PTE_PROMOTE) != (newpde & PG_PTE_PROMOTE)) { 3204 pmap_pde_p_failures++; 3205 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x" 3206 " in pmap %p", va, pmap); 3207 return; 3208 } 3209 pa -= PAGE_SIZE; 3210 } 3211 3212 /* 3213 * Save the page table page in its current state until the PDE 3214 * mapping the superpage is demoted by pmap_demote_pde() or 3215 * destroyed by pmap_remove_pde(). 3216 */ 3217 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME); 3218 KASSERT(mpte >= vm_page_array && 3219 mpte < &vm_page_array[vm_page_array_size], 3220 ("pmap_promote_pde: page table page is out of range")); 3221 KASSERT(mpte->pindex == va >> PDRSHIFT, 3222 ("pmap_promote_pde: page table page's pindex is wrong")); 3223 pmap_insert_pt_page(pmap, mpte); 3224 3225 /* 3226 * Promote the pv entries. 3227 */ 3228 if ((newpde & PG_MANAGED) != 0) 3229 pmap_pv_promote_pde(pmap, va, newpde & PG_PS_FRAME); 3230 3231 /* 3232 * Propagate the PAT index to its proper position. 3233 */ 3234 if ((newpde & PG_PTE_PAT) != 0) 3235 newpde ^= PG_PDE_PAT | PG_PTE_PAT; 3236 3237 /* 3238 * Map the superpage. 3239 */ 3240 if (workaround_erratum383) 3241 pmap_update_pde(pmap, va, pde, PG_PS | newpde); 3242 else if (pmap == kernel_pmap) 3243 pmap_kenter_pde(va, PG_PS | newpde); 3244 else 3245 pde_store(pde, PG_PS | newpde); 3246 3247 pmap_pde_promotions++; 3248 CTR2(KTR_PMAP, "pmap_promote_pde: success for va %#x" 3249 " in pmap %p", va, pmap); 3250} 3251 3252/* 3253 * Insert the given physical page (p) at 3254 * the specified virtual address (v) in the 3255 * target physical map with the protection requested. 3256 * 3257 * If specified, the page will be wired down, meaning 3258 * that the related pte can not be reclaimed. 3259 * 3260 * NB: This is the only routine which MAY NOT lazy-evaluate 3261 * or lose information. That is, this routine must actually 3262 * insert this page into the given map NOW. 3263 */ 3264void 3265pmap_enter(pmap_t pmap, vm_offset_t va, vm_prot_t access, vm_page_t m, 3266 vm_prot_t prot, boolean_t wired) 3267{ 3268 vm_paddr_t pa; 3269 pd_entry_t *pde; 3270 pt_entry_t *pte; 3271 vm_paddr_t opa; 3272 pt_entry_t origpte, newpte; 3273 vm_page_t mpte, om; 3274 boolean_t invlva; 3275 3276 va = trunc_page(va); 3277 KASSERT(va <= VM_MAX_KERNEL_ADDRESS, ("pmap_enter: toobig")); 3278 KASSERT(va < UPT_MIN_ADDRESS || va >= UPT_MAX_ADDRESS, 3279 ("pmap_enter: invalid to pmap_enter page table pages (va: 0x%x)", va)); 3280 3281 mpte = NULL; 3282 3283 vm_page_lock_queues(); 3284 PMAP_LOCK(pmap); 3285 sched_pin(); 3286 3287 /* 3288 * In the case that a page table page is not 3289 * resident, we are creating it here. 3290 */ 3291 if (va < VM_MAXUSER_ADDRESS) { 3292 mpte = pmap_allocpte(pmap, va, M_WAITOK); 3293 } 3294 3295 pde = pmap_pde(pmap, va); 3296 if ((*pde & PG_PS) != 0) 3297 panic("pmap_enter: attempted pmap_enter on 4MB page"); 3298 pte = pmap_pte_quick(pmap, va); 3299 3300 /* 3301 * Page Directory table entry not valid, we need a new PT page 3302 */ 3303 if (pte == NULL) { 3304 panic("pmap_enter: invalid page directory pdir=%#jx, va=%#x", 3305 (uintmax_t)pmap->pm_pdir[PTDPTDI], va); 3306 } 3307 3308 pa = VM_PAGE_TO_PHYS(m); 3309 om = NULL; 3310 origpte = *pte; 3311 opa = origpte & PG_FRAME; 3312 3313 /* 3314 * Mapping has not changed, must be protection or wiring change. 3315 */ 3316 if (origpte && (opa == pa)) { 3317 /* 3318 * Wiring change, just update stats. We don't worry about 3319 * wiring PT pages as they remain resident as long as there 3320 * are valid mappings in them. Hence, if a user page is wired, 3321 * the PT page will be also. 3322 */ 3323 if (wired && ((origpte & PG_W) == 0)) 3324 pmap->pm_stats.wired_count++; 3325 else if (!wired && (origpte & PG_W)) 3326 pmap->pm_stats.wired_count--; 3327 3328 /* 3329 * Remove extra pte reference 3330 */ 3331 if (mpte) 3332 mpte->wire_count--; 3333 3334 /* 3335 * We might be turning off write access to the page, 3336 * so we go ahead and sense modify status. 3337 */ 3338 if (origpte & PG_MANAGED) { 3339 om = m; 3340 pa |= PG_MANAGED; 3341 } 3342 goto validate; 3343 } 3344 /* 3345 * Mapping has changed, invalidate old range and fall through to 3346 * handle validating new mapping. 3347 */ 3348 if (opa) { 3349 if (origpte & PG_W) 3350 pmap->pm_stats.wired_count--; 3351 if (origpte & PG_MANAGED) { 3352 om = PHYS_TO_VM_PAGE(opa); 3353 pmap_remove_entry(pmap, om, va); 3354 } 3355 if (mpte != NULL) { 3356 mpte->wire_count--; 3357 KASSERT(mpte->wire_count > 0, 3358 ("pmap_enter: missing reference to page table page," 3359 " va: 0x%x", va)); 3360 } 3361 } else 3362 pmap->pm_stats.resident_count++; 3363 3364 /* 3365 * Enter on the PV list if part of our managed memory. 3366 */ 3367 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0) { 3368 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva, 3369 ("pmap_enter: managed mapping within the clean submap")); 3370 pmap_insert_entry(pmap, va, m); 3371 pa |= PG_MANAGED; 3372 } 3373 3374 /* 3375 * Increment counters 3376 */ 3377 if (wired) 3378 pmap->pm_stats.wired_count++; 3379 3380validate: 3381 /* 3382 * Now validate mapping with desired protection/wiring. 3383 */ 3384 newpte = (pt_entry_t)(pa | pmap_cache_bits(m->md.pat_mode, 0) | PG_V); 3385 if ((prot & VM_PROT_WRITE) != 0) { 3386 newpte |= PG_RW; 3387 vm_page_flag_set(m, PG_WRITEABLE); 3388 } 3389#ifdef PAE 3390 if ((prot & VM_PROT_EXECUTE) == 0) 3391 newpte |= pg_nx; 3392#endif 3393 if (wired) 3394 newpte |= PG_W; 3395 if (va < VM_MAXUSER_ADDRESS) 3396 newpte |= PG_U; 3397 if (pmap == kernel_pmap) 3398 newpte |= pgeflag; 3399 3400 /* 3401 * if the mapping or permission bits are different, we need 3402 * to update the pte. 3403 */ 3404 if ((origpte & ~(PG_M|PG_A)) != newpte) { 3405 newpte |= PG_A; 3406 if ((access & VM_PROT_WRITE) != 0) 3407 newpte |= PG_M; 3408 if (origpte & PG_V) { 3409 invlva = FALSE; 3410 origpte = pte_load_store(pte, newpte); 3411 if (origpte & PG_A) { 3412 if (origpte & PG_MANAGED) 3413 vm_page_flag_set(om, PG_REFERENCED); 3414 if (opa != VM_PAGE_TO_PHYS(m)) 3415 invlva = TRUE; 3416#ifdef PAE 3417 if ((origpte & PG_NX) == 0 && 3418 (newpte & PG_NX) != 0) 3419 invlva = TRUE; 3420#endif 3421 } 3422 if ((origpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) { 3423 if ((origpte & PG_MANAGED) != 0) 3424 vm_page_dirty(om); 3425 if ((prot & VM_PROT_WRITE) == 0) 3426 invlva = TRUE; 3427 } 3428 if (invlva) 3429 pmap_invalidate_page(pmap, va); 3430 } else 3431 pte_store(pte, newpte); 3432 } 3433 3434 /* 3435 * If both the page table page and the reservation are fully 3436 * populated, then attempt promotion. 3437 */ 3438 if ((mpte == NULL || mpte->wire_count == NPTEPG) && 3439 pg_ps_enabled && vm_reserv_level_iffullpop(m) == 0) 3440 pmap_promote_pde(pmap, pde, va); 3441 3442 sched_unpin(); 3443 vm_page_unlock_queues(); 3444 PMAP_UNLOCK(pmap); 3445} 3446 3447/* 3448 * Tries to create a 2- or 4MB page mapping. Returns TRUE if successful and 3449 * FALSE otherwise. Fails if (1) a page table page cannot be allocated without 3450 * blocking, (2) a mapping already exists at the specified virtual address, or 3451 * (3) a pv entry cannot be allocated without reclaiming another pv entry. 3452 */ 3453static boolean_t 3454pmap_enter_pde(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot) 3455{ 3456 pd_entry_t *pde, newpde; 3457 3458 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 3459 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 3460 pde = pmap_pde(pmap, va); 3461 if (*pde != 0) { 3462 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx" 3463 " in pmap %p", va, pmap); 3464 return (FALSE); 3465 } 3466 newpde = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(m->md.pat_mode, 1) | 3467 PG_PS | PG_V; 3468 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0) { 3469 newpde |= PG_MANAGED; 3470 3471 /* 3472 * Abort this mapping if its PV entry could not be created. 3473 */ 3474 if (!pmap_pv_insert_pde(pmap, va, VM_PAGE_TO_PHYS(m))) { 3475 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx" 3476 " in pmap %p", va, pmap); 3477 return (FALSE); 3478 } 3479 } 3480#ifdef PAE 3481 if ((prot & VM_PROT_EXECUTE) == 0) 3482 newpde |= pg_nx; 3483#endif 3484 if (va < VM_MAXUSER_ADDRESS) 3485 newpde |= PG_U; 3486 3487 /* 3488 * Increment counters. 3489 */ 3490 pmap->pm_stats.resident_count += NBPDR / PAGE_SIZE; 3491 3492 /* 3493 * Map the superpage. 3494 */ 3495 pde_store(pde, newpde); 3496 3497 pmap_pde_mappings++; 3498 CTR2(KTR_PMAP, "pmap_enter_pde: success for va %#lx" 3499 " in pmap %p", va, pmap); 3500 return (TRUE); 3501} 3502 3503/* 3504 * Maps a sequence of resident pages belonging to the same object. 3505 * The sequence begins with the given page m_start. This page is 3506 * mapped at the given virtual address start. Each subsequent page is 3507 * mapped at a virtual address that is offset from start by the same 3508 * amount as the page is offset from m_start within the object. The 3509 * last page in the sequence is the page with the largest offset from 3510 * m_start that can be mapped at a virtual address less than the given 3511 * virtual address end. Not every virtual page between start and end 3512 * is mapped; only those for which a resident page exists with the 3513 * corresponding offset from m_start are mapped. 3514 */ 3515void 3516pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end, 3517 vm_page_t m_start, vm_prot_t prot) 3518{ 3519 vm_offset_t va; 3520 vm_page_t m, mpte; 3521 vm_pindex_t diff, psize; 3522 3523 VM_OBJECT_LOCK_ASSERT(m_start->object, MA_OWNED); 3524 psize = atop(end - start); 3525 mpte = NULL; 3526 m = m_start; 3527 PMAP_LOCK(pmap); 3528 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 3529 va = start + ptoa(diff); 3530 if ((va & PDRMASK) == 0 && va + NBPDR <= end && 3531 (VM_PAGE_TO_PHYS(m) & PDRMASK) == 0 && 3532 pg_ps_enabled && vm_reserv_level_iffullpop(m) == 0 && 3533 pmap_enter_pde(pmap, va, m, prot)) 3534 m = &m[NBPDR / PAGE_SIZE - 1]; 3535 else 3536 mpte = pmap_enter_quick_locked(pmap, va, m, prot, 3537 mpte); 3538 m = TAILQ_NEXT(m, listq); 3539 } 3540 PMAP_UNLOCK(pmap); 3541} 3542 3543/* 3544 * this code makes some *MAJOR* assumptions: 3545 * 1. Current pmap & pmap exists. 3546 * 2. Not wired. 3547 * 3. Read access. 3548 * 4. No page table pages. 3549 * but is *MUCH* faster than pmap_enter... 3550 */ 3551 3552void 3553pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot) 3554{ 3555 3556 PMAP_LOCK(pmap); 3557 (void) pmap_enter_quick_locked(pmap, va, m, prot, NULL); 3558 PMAP_UNLOCK(pmap); 3559} 3560 3561static vm_page_t 3562pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m, 3563 vm_prot_t prot, vm_page_t mpte) 3564{ 3565 pt_entry_t *pte; 3566 vm_paddr_t pa; 3567 vm_page_t free; 3568 3569 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva || 3570 (m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0, 3571 ("pmap_enter_quick_locked: managed mapping within the clean submap")); 3572 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 3573 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 3574 3575 /* 3576 * In the case that a page table page is not 3577 * resident, we are creating it here. 3578 */ 3579 if (va < VM_MAXUSER_ADDRESS) { 3580 unsigned ptepindex; 3581 pd_entry_t ptepa; 3582 3583 /* 3584 * Calculate pagetable page index 3585 */ 3586 ptepindex = va >> PDRSHIFT; 3587 if (mpte && (mpte->pindex == ptepindex)) { 3588 mpte->wire_count++; 3589 } else { 3590 /* 3591 * Get the page directory entry 3592 */ 3593 ptepa = pmap->pm_pdir[ptepindex]; 3594 3595 /* 3596 * If the page table page is mapped, we just increment 3597 * the hold count, and activate it. 3598 */ 3599 if (ptepa) { 3600 if (ptepa & PG_PS) 3601 return (NULL); 3602 mpte = PHYS_TO_VM_PAGE(ptepa & PG_FRAME); 3603 mpte->wire_count++; 3604 } else { 3605 mpte = _pmap_allocpte(pmap, ptepindex, 3606 M_NOWAIT); 3607 if (mpte == NULL) 3608 return (mpte); 3609 } 3610 } 3611 } else { 3612 mpte = NULL; 3613 } 3614 3615 /* 3616 * This call to vtopte makes the assumption that we are 3617 * entering the page into the current pmap. In order to support 3618 * quick entry into any pmap, one would likely use pmap_pte_quick. 3619 * But that isn't as quick as vtopte. 3620 */ 3621 pte = vtopte(va); 3622 if (*pte) { 3623 if (mpte != NULL) { 3624 mpte->wire_count--; 3625 mpte = NULL; 3626 } 3627 return (mpte); 3628 } 3629 3630 /* 3631 * Enter on the PV list if part of our managed memory. 3632 */ 3633 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0 && 3634 !pmap_try_insert_pv_entry(pmap, va, m)) { 3635 if (mpte != NULL) { 3636 free = NULL; 3637 if (pmap_unwire_pte_hold(pmap, mpte, &free)) { 3638 pmap_invalidate_page(pmap, va); 3639 pmap_free_zero_pages(free); 3640 } 3641 3642 mpte = NULL; 3643 } 3644 return (mpte); 3645 } 3646 3647 /* 3648 * Increment counters 3649 */ 3650 pmap->pm_stats.resident_count++; 3651 3652 pa = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(m->md.pat_mode, 0); 3653#ifdef PAE 3654 if ((prot & VM_PROT_EXECUTE) == 0) 3655 pa |= pg_nx; 3656#endif 3657 3658 /* 3659 * Now validate mapping with RO protection 3660 */ 3661 if (m->flags & (PG_FICTITIOUS|PG_UNMANAGED)) 3662 pte_store(pte, pa | PG_V | PG_U); 3663 else 3664 pte_store(pte, pa | PG_V | PG_U | PG_MANAGED); 3665 return (mpte); 3666} 3667 3668/* 3669 * Make a temporary mapping for a physical address. This is only intended 3670 * to be used for panic dumps. 3671 */ 3672void * 3673pmap_kenter_temporary(vm_paddr_t pa, int i) 3674{ 3675 vm_offset_t va; 3676 3677 va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE); 3678 pmap_kenter(va, pa); 3679 invlpg(va); 3680 return ((void *)crashdumpmap); 3681} 3682 3683/* 3684 * This code maps large physical mmap regions into the 3685 * processor address space. Note that some shortcuts 3686 * are taken, but the code works. 3687 */ 3688void 3689pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object, 3690 vm_pindex_t pindex, vm_size_t size) 3691{ 3692 pd_entry_t *pde; 3693 vm_paddr_t pa, ptepa; 3694 vm_page_t p; 3695 int pat_mode; 3696 3697 VM_OBJECT_LOCK_ASSERT(object, MA_OWNED); 3698 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG, 3699 ("pmap_object_init_pt: non-device object")); 3700 if (pseflag && 3701 (addr & (NBPDR - 1)) == 0 && (size & (NBPDR - 1)) == 0) { 3702 if (!vm_object_populate(object, pindex, pindex + atop(size))) 3703 return; 3704 p = vm_page_lookup(object, pindex); 3705 KASSERT(p->valid == VM_PAGE_BITS_ALL, 3706 ("pmap_object_init_pt: invalid page %p", p)); 3707 pat_mode = p->md.pat_mode; 3708 3709 /* 3710 * Abort the mapping if the first page is not physically 3711 * aligned to a 2/4MB page boundary. 3712 */ 3713 ptepa = VM_PAGE_TO_PHYS(p); 3714 if (ptepa & (NBPDR - 1)) 3715 return; 3716 3717 /* 3718 * Skip the first page. Abort the mapping if the rest of 3719 * the pages are not physically contiguous or have differing 3720 * memory attributes. 3721 */ 3722 p = TAILQ_NEXT(p, listq); 3723 for (pa = ptepa + PAGE_SIZE; pa < ptepa + size; 3724 pa += PAGE_SIZE) { 3725 KASSERT(p->valid == VM_PAGE_BITS_ALL, 3726 ("pmap_object_init_pt: invalid page %p", p)); 3727 if (pa != VM_PAGE_TO_PHYS(p) || 3728 pat_mode != p->md.pat_mode) 3729 return; 3730 p = TAILQ_NEXT(p, listq); 3731 } 3732 3733 /* 3734 * Map using 2/4MB pages. Since "ptepa" is 2/4M aligned and 3735 * "size" is a multiple of 2/4M, adding the PAT setting to 3736 * "pa" will not affect the termination of this loop. 3737 */ 3738 PMAP_LOCK(pmap); 3739 for (pa = ptepa | pmap_cache_bits(pat_mode, 1); pa < ptepa + 3740 size; pa += NBPDR) { 3741 pde = pmap_pde(pmap, addr); 3742 if (*pde == 0) { 3743 pde_store(pde, pa | PG_PS | PG_M | PG_A | 3744 PG_U | PG_RW | PG_V); 3745 pmap->pm_stats.resident_count += NBPDR / 3746 PAGE_SIZE; 3747 pmap_pde_mappings++; 3748 } 3749 /* Else continue on if the PDE is already valid. */ 3750 addr += NBPDR; 3751 } 3752 PMAP_UNLOCK(pmap); 3753 } 3754} 3755 3756/* 3757 * Routine: pmap_change_wiring 3758 * Function: Change the wiring attribute for a map/virtual-address 3759 * pair. 3760 * In/out conditions: 3761 * The mapping must already exist in the pmap. 3762 */ 3763void 3764pmap_change_wiring(pmap_t pmap, vm_offset_t va, boolean_t wired) 3765{ 3766 pd_entry_t *pde; 3767 pt_entry_t *pte; 3768 boolean_t are_queues_locked; 3769 3770 are_queues_locked = FALSE; 3771retry: 3772 PMAP_LOCK(pmap); 3773 pde = pmap_pde(pmap, va); 3774 if ((*pde & PG_PS) != 0) { 3775 if (!wired != ((*pde & PG_W) == 0)) { 3776 if (!are_queues_locked) { 3777 are_queues_locked = TRUE; 3778 if (!mtx_trylock(&vm_page_queue_mtx)) { 3779 PMAP_UNLOCK(pmap); 3780 vm_page_lock_queues(); 3781 goto retry; 3782 } 3783 } 3784 if (!pmap_demote_pde(pmap, pde, va)) 3785 panic("pmap_change_wiring: demotion failed"); 3786 } else 3787 goto out; 3788 } 3789 pte = pmap_pte(pmap, va); 3790 3791 if (wired && !pmap_pte_w(pte)) 3792 pmap->pm_stats.wired_count++; 3793 else if (!wired && pmap_pte_w(pte)) 3794 pmap->pm_stats.wired_count--; 3795 3796 /* 3797 * Wiring is not a hardware characteristic so there is no need to 3798 * invalidate TLB. 3799 */ 3800 pmap_pte_set_w(pte, wired); 3801 pmap_pte_release(pte); 3802out: 3803 if (are_queues_locked) 3804 vm_page_unlock_queues(); 3805 PMAP_UNLOCK(pmap); 3806} 3807 3808 3809 3810/* 3811 * Copy the range specified by src_addr/len 3812 * from the source map to the range dst_addr/len 3813 * in the destination map. 3814 * 3815 * This routine is only advisory and need not do anything. 3816 */ 3817 3818void 3819pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len, 3820 vm_offset_t src_addr) 3821{ 3822 vm_page_t free; 3823 vm_offset_t addr; 3824 vm_offset_t end_addr = src_addr + len; 3825 vm_offset_t pdnxt; 3826 3827 if (dst_addr != src_addr) 3828 return; 3829 3830 if (!pmap_is_current(src_pmap)) 3831 return; 3832 3833 vm_page_lock_queues(); 3834 if (dst_pmap < src_pmap) { 3835 PMAP_LOCK(dst_pmap); 3836 PMAP_LOCK(src_pmap); 3837 } else { 3838 PMAP_LOCK(src_pmap); 3839 PMAP_LOCK(dst_pmap); 3840 } 3841 sched_pin(); 3842 for (addr = src_addr; addr < end_addr; addr = pdnxt) { 3843 pt_entry_t *src_pte, *dst_pte; 3844 vm_page_t dstmpte, srcmpte; 3845 pd_entry_t srcptepaddr; 3846 unsigned ptepindex; 3847 3848 KASSERT(addr < UPT_MIN_ADDRESS, 3849 ("pmap_copy: invalid to pmap_copy page tables")); 3850 3851 pdnxt = (addr + NBPDR) & ~PDRMASK; 3852 if (pdnxt < addr) 3853 pdnxt = end_addr; 3854 ptepindex = addr >> PDRSHIFT; 3855 3856 srcptepaddr = src_pmap->pm_pdir[ptepindex]; 3857 if (srcptepaddr == 0) 3858 continue; 3859 3860 if (srcptepaddr & PG_PS) { 3861 if (dst_pmap->pm_pdir[ptepindex] == 0 && 3862 ((srcptepaddr & PG_MANAGED) == 0 || 3863 pmap_pv_insert_pde(dst_pmap, addr, srcptepaddr & 3864 PG_PS_FRAME))) { 3865 dst_pmap->pm_pdir[ptepindex] = srcptepaddr & 3866 ~PG_W; 3867 dst_pmap->pm_stats.resident_count += 3868 NBPDR / PAGE_SIZE; 3869 } 3870 continue; 3871 } 3872 3873 srcmpte = PHYS_TO_VM_PAGE(srcptepaddr & PG_FRAME); 3874 KASSERT(srcmpte->wire_count > 0, 3875 ("pmap_copy: source page table page is unused")); 3876 3877 if (pdnxt > end_addr) 3878 pdnxt = end_addr; 3879 3880 src_pte = vtopte(addr); 3881 while (addr < pdnxt) { 3882 pt_entry_t ptetemp; 3883 ptetemp = *src_pte; 3884 /* 3885 * we only virtual copy managed pages 3886 */ 3887 if ((ptetemp & PG_MANAGED) != 0) { 3888 dstmpte = pmap_allocpte(dst_pmap, addr, 3889 M_NOWAIT); 3890 if (dstmpte == NULL) 3891 goto out; 3892 dst_pte = pmap_pte_quick(dst_pmap, addr); 3893 if (*dst_pte == 0 && 3894 pmap_try_insert_pv_entry(dst_pmap, addr, 3895 PHYS_TO_VM_PAGE(ptetemp & PG_FRAME))) { 3896 /* 3897 * Clear the wired, modified, and 3898 * accessed (referenced) bits 3899 * during the copy. 3900 */ 3901 *dst_pte = ptetemp & ~(PG_W | PG_M | 3902 PG_A); 3903 dst_pmap->pm_stats.resident_count++; 3904 } else { 3905 free = NULL; 3906 if (pmap_unwire_pte_hold(dst_pmap, 3907 dstmpte, &free)) { 3908 pmap_invalidate_page(dst_pmap, 3909 addr); 3910 pmap_free_zero_pages(free); 3911 } 3912 goto out; 3913 } 3914 if (dstmpte->wire_count >= srcmpte->wire_count) 3915 break; 3916 } 3917 addr += PAGE_SIZE; 3918 src_pte++; 3919 } 3920 } 3921out: 3922 sched_unpin(); 3923 vm_page_unlock_queues(); 3924 PMAP_UNLOCK(src_pmap); 3925 PMAP_UNLOCK(dst_pmap); 3926} 3927 3928static __inline void 3929pagezero(void *page) 3930{ 3931#if defined(I686_CPU) 3932 if (cpu_class == CPUCLASS_686) { 3933#if defined(CPU_ENABLE_SSE) 3934 if (cpu_feature & CPUID_SSE2) 3935 sse2_pagezero(page); 3936 else 3937#endif 3938 i686_pagezero(page); 3939 } else 3940#endif 3941 bzero(page, PAGE_SIZE); 3942} 3943 3944/* 3945 * pmap_zero_page zeros the specified hardware page by mapping 3946 * the page into KVM and using bzero to clear its contents. 3947 */ 3948void 3949pmap_zero_page(vm_page_t m) 3950{ 3951 struct sysmaps *sysmaps; 3952 3953 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)]; 3954 mtx_lock(&sysmaps->lock); 3955 if (*sysmaps->CMAP2) 3956 panic("pmap_zero_page: CMAP2 busy"); 3957 sched_pin(); 3958 *sysmaps->CMAP2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M | 3959 pmap_cache_bits(m->md.pat_mode, 0); 3960 invlcaddr(sysmaps->CADDR2); 3961 pagezero(sysmaps->CADDR2); 3962 *sysmaps->CMAP2 = 0; 3963 sched_unpin(); 3964 mtx_unlock(&sysmaps->lock); 3965} 3966 3967/* 3968 * pmap_zero_page_area zeros the specified hardware page by mapping 3969 * the page into KVM and using bzero to clear its contents. 3970 * 3971 * off and size may not cover an area beyond a single hardware page. 3972 */ 3973void 3974pmap_zero_page_area(vm_page_t m, int off, int size) 3975{ 3976 struct sysmaps *sysmaps; 3977 3978 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)]; 3979 mtx_lock(&sysmaps->lock); 3980 if (*sysmaps->CMAP2) 3981 panic("pmap_zero_page_area: CMAP2 busy"); 3982 sched_pin(); 3983 *sysmaps->CMAP2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M | 3984 pmap_cache_bits(m->md.pat_mode, 0); 3985 invlcaddr(sysmaps->CADDR2); 3986 if (off == 0 && size == PAGE_SIZE) 3987 pagezero(sysmaps->CADDR2); 3988 else 3989 bzero((char *)sysmaps->CADDR2 + off, size); 3990 *sysmaps->CMAP2 = 0; 3991 sched_unpin(); 3992 mtx_unlock(&sysmaps->lock); 3993} 3994 3995/* 3996 * pmap_zero_page_idle zeros the specified hardware page by mapping 3997 * the page into KVM and using bzero to clear its contents. This 3998 * is intended to be called from the vm_pagezero process only and 3999 * outside of Giant. 4000 */ 4001void 4002pmap_zero_page_idle(vm_page_t m) 4003{ 4004 4005 if (*CMAP3) 4006 panic("pmap_zero_page_idle: CMAP3 busy"); 4007 sched_pin(); 4008 *CMAP3 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M | 4009 pmap_cache_bits(m->md.pat_mode, 0); 4010 invlcaddr(CADDR3); 4011 pagezero(CADDR3); 4012 *CMAP3 = 0; 4013 sched_unpin(); 4014} 4015 4016/* 4017 * pmap_copy_page copies the specified (machine independent) 4018 * page by mapping the page into virtual memory and using 4019 * bcopy to copy the page, one machine dependent page at a 4020 * time. 4021 */ 4022void 4023pmap_copy_page(vm_page_t src, vm_page_t dst) 4024{ 4025 struct sysmaps *sysmaps; 4026 4027 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)]; 4028 mtx_lock(&sysmaps->lock); 4029 if (*sysmaps->CMAP1) 4030 panic("pmap_copy_page: CMAP1 busy"); 4031 if (*sysmaps->CMAP2) 4032 panic("pmap_copy_page: CMAP2 busy"); 4033 sched_pin(); 4034 invlpg((u_int)sysmaps->CADDR1); 4035 invlpg((u_int)sysmaps->CADDR2); 4036 *sysmaps->CMAP1 = PG_V | VM_PAGE_TO_PHYS(src) | PG_A | 4037 pmap_cache_bits(src->md.pat_mode, 0); 4038 *sysmaps->CMAP2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(dst) | PG_A | PG_M | 4039 pmap_cache_bits(dst->md.pat_mode, 0); 4040 bcopy(sysmaps->CADDR1, sysmaps->CADDR2, PAGE_SIZE); 4041 *sysmaps->CMAP1 = 0; 4042 *sysmaps->CMAP2 = 0; 4043 sched_unpin(); 4044 mtx_unlock(&sysmaps->lock); 4045} 4046 4047/* 4048 * Returns true if the pmap's pv is one of the first 4049 * 16 pvs linked to from this page. This count may 4050 * be changed upwards or downwards in the future; it 4051 * is only necessary that true be returned for a small 4052 * subset of pmaps for proper page aging. 4053 */ 4054boolean_t 4055pmap_page_exists_quick(pmap_t pmap, vm_page_t m) 4056{ 4057 struct md_page *pvh; 4058 pv_entry_t pv; 4059 int loops = 0; 4060 4061 if (m->flags & PG_FICTITIOUS) 4062 return (FALSE); 4063 4064 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 4065 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 4066 if (PV_PMAP(pv) == pmap) { 4067 return (TRUE); 4068 } 4069 loops++; 4070 if (loops >= 16) 4071 break; 4072 } 4073 if (loops < 16) { 4074 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 4075 TAILQ_FOREACH(pv, &pvh->pv_list, pv_list) { 4076 if (PV_PMAP(pv) == pmap) 4077 return (TRUE); 4078 loops++; 4079 if (loops >= 16) 4080 break; 4081 } 4082 } 4083 return (FALSE); 4084} 4085 4086/* 4087 * pmap_page_wired_mappings: 4088 * 4089 * Return the number of managed mappings to the given physical page 4090 * that are wired. 4091 */ 4092int 4093pmap_page_wired_mappings(vm_page_t m) 4094{ 4095 int count; 4096 4097 count = 0; 4098 if ((m->flags & PG_FICTITIOUS) != 0) 4099 return (count); 4100 count = pmap_pvh_wired_mappings(&m->md, count); 4101 return (pmap_pvh_wired_mappings(pa_to_pvh(VM_PAGE_TO_PHYS(m)), count)); 4102} 4103 4104/* 4105 * pmap_pvh_wired_mappings: 4106 * 4107 * Return the updated number "count" of managed mappings that are wired. 4108 */ 4109static int 4110pmap_pvh_wired_mappings(struct md_page *pvh, int count) 4111{ 4112 pmap_t pmap; 4113 pt_entry_t *pte; 4114 pv_entry_t pv; 4115 4116 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 4117 sched_pin(); 4118 TAILQ_FOREACH(pv, &pvh->pv_list, pv_list) { 4119 pmap = PV_PMAP(pv); 4120 PMAP_LOCK(pmap); 4121 pte = pmap_pte_quick(pmap, pv->pv_va); 4122 if ((*pte & PG_W) != 0) 4123 count++; 4124 PMAP_UNLOCK(pmap); 4125 } 4126 sched_unpin(); 4127 return (count); 4128} 4129 4130/* 4131 * Returns TRUE if the given page is mapped individually or as part of 4132 * a 4mpage. Otherwise, returns FALSE. 4133 */ 4134boolean_t 4135pmap_page_is_mapped(vm_page_t m) 4136{ 4137 struct md_page *pvh; 4138 4139 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0) 4140 return (FALSE); 4141 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 4142 if (TAILQ_EMPTY(&m->md.pv_list)) { 4143 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 4144 return (!TAILQ_EMPTY(&pvh->pv_list)); 4145 } else 4146 return (TRUE); 4147} 4148 4149/* 4150 * Remove all pages from specified address space 4151 * this aids process exit speeds. Also, this code 4152 * is special cased for current process only, but 4153 * can have the more generic (and slightly slower) 4154 * mode enabled. This is much faster than pmap_remove 4155 * in the case of running down an entire address space. 4156 */ 4157void 4158pmap_remove_pages(pmap_t pmap) 4159{ 4160 pt_entry_t *pte, tpte; 4161 vm_page_t free = NULL; 4162 vm_page_t m, mpte, mt; 4163 pv_entry_t pv; 4164 struct md_page *pvh; 4165 struct pv_chunk *pc, *npc; 4166 int field, idx; 4167 int32_t bit; 4168 uint32_t inuse, bitmask; 4169 int allfree; 4170 4171 if (pmap != vmspace_pmap(curthread->td_proc->p_vmspace)) { 4172 printf("warning: pmap_remove_pages called with non-current pmap\n"); 4173 return; 4174 } 4175 vm_page_lock_queues(); 4176 PMAP_LOCK(pmap); 4177 sched_pin(); 4178 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) { 4179 allfree = 1; 4180 for (field = 0; field < _NPCM; field++) { 4181 inuse = (~(pc->pc_map[field])) & pc_freemask[field]; 4182 while (inuse != 0) { 4183 bit = bsfl(inuse); 4184 bitmask = 1UL << bit; 4185 idx = field * 32 + bit; 4186 pv = &pc->pc_pventry[idx]; 4187 inuse &= ~bitmask; 4188 4189 pte = pmap_pde(pmap, pv->pv_va); 4190 tpte = *pte; 4191 if ((tpte & PG_PS) == 0) { 4192 pte = vtopte(pv->pv_va); 4193 tpte = *pte & ~PG_PTE_PAT; 4194 } 4195 4196 if (tpte == 0) { 4197 printf( 4198 "TPTE at %p IS ZERO @ VA %08x\n", 4199 pte, pv->pv_va); 4200 panic("bad pte"); 4201 } 4202 4203/* 4204 * We cannot remove wired pages from a process' mapping at this time 4205 */ 4206 if (tpte & PG_W) { 4207 allfree = 0; 4208 continue; 4209 } 4210 4211 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME); 4212 KASSERT(m->phys_addr == (tpte & PG_FRAME), 4213 ("vm_page_t %p phys_addr mismatch %016jx %016jx", 4214 m, (uintmax_t)m->phys_addr, 4215 (uintmax_t)tpte)); 4216 4217 KASSERT(m < &vm_page_array[vm_page_array_size], 4218 ("pmap_remove_pages: bad tpte %#jx", 4219 (uintmax_t)tpte)); 4220 4221 pte_clear(pte); 4222 4223 /* 4224 * Update the vm_page_t clean/reference bits. 4225 */ 4226 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) { 4227 if ((tpte & PG_PS) != 0) { 4228 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++) 4229 vm_page_dirty(mt); 4230 } else 4231 vm_page_dirty(m); 4232 } 4233 4234 /* Mark free */ 4235 PV_STAT(pv_entry_frees++); 4236 PV_STAT(pv_entry_spare++); 4237 pv_entry_count--; 4238 pc->pc_map[field] |= bitmask; 4239 if ((tpte & PG_PS) != 0) { 4240 pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE; 4241 pvh = pa_to_pvh(tpte & PG_PS_FRAME); 4242 TAILQ_REMOVE(&pvh->pv_list, pv, pv_list); 4243 if (TAILQ_EMPTY(&pvh->pv_list)) { 4244 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++) 4245 if (TAILQ_EMPTY(&mt->md.pv_list)) 4246 vm_page_flag_clear(mt, PG_WRITEABLE); 4247 } 4248 mpte = pmap_lookup_pt_page(pmap, pv->pv_va); 4249 if (mpte != NULL) { 4250 pmap_remove_pt_page(pmap, mpte); 4251 pmap->pm_stats.resident_count--; 4252 KASSERT(mpte->wire_count == NPTEPG, 4253 ("pmap_remove_pages: pte page wire count error")); 4254 mpte->wire_count = 0; 4255 pmap_add_delayed_free_list(mpte, &free, FALSE); 4256 atomic_subtract_int(&cnt.v_wire_count, 1); 4257 } 4258 } else { 4259 pmap->pm_stats.resident_count--; 4260 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list); 4261 if (TAILQ_EMPTY(&m->md.pv_list)) { 4262 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 4263 if (TAILQ_EMPTY(&pvh->pv_list)) 4264 vm_page_flag_clear(m, PG_WRITEABLE); 4265 } 4266 pmap_unuse_pt(pmap, pv->pv_va, &free); 4267 } 4268 } 4269 } 4270 if (allfree) { 4271 PV_STAT(pv_entry_spare -= _NPCPV); 4272 PV_STAT(pc_chunk_count--); 4273 PV_STAT(pc_chunk_frees++); 4274 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 4275 m = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc)); 4276 pmap_qremove((vm_offset_t)pc, 1); 4277 vm_page_unwire(m, 0); 4278 vm_page_free(m); 4279 pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc); 4280 } 4281 } 4282 sched_unpin(); 4283 pmap_invalidate_all(pmap); 4284 vm_page_unlock_queues(); 4285 PMAP_UNLOCK(pmap); 4286 pmap_free_zero_pages(free); 4287} 4288 4289/* 4290 * pmap_is_modified: 4291 * 4292 * Return whether or not the specified physical page was modified 4293 * in any physical maps. 4294 */ 4295boolean_t 4296pmap_is_modified(vm_page_t m) 4297{ 4298 4299 if (m->flags & PG_FICTITIOUS) 4300 return (FALSE); 4301 if (pmap_is_modified_pvh(&m->md)) 4302 return (TRUE); 4303 return (pmap_is_modified_pvh(pa_to_pvh(VM_PAGE_TO_PHYS(m)))); 4304} 4305 4306/* 4307 * Returns TRUE if any of the given mappings were used to modify 4308 * physical memory. Otherwise, returns FALSE. Both page and 2mpage 4309 * mappings are supported. 4310 */ 4311static boolean_t 4312pmap_is_modified_pvh(struct md_page *pvh) 4313{ 4314 pv_entry_t pv; 4315 pt_entry_t *pte; 4316 pmap_t pmap; 4317 boolean_t rv; 4318 4319 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 4320 rv = FALSE; 4321 sched_pin(); 4322 TAILQ_FOREACH(pv, &pvh->pv_list, pv_list) { 4323 pmap = PV_PMAP(pv); 4324 PMAP_LOCK(pmap); 4325 pte = pmap_pte_quick(pmap, pv->pv_va); 4326 rv = (*pte & (PG_M | PG_RW)) == (PG_M | PG_RW); 4327 PMAP_UNLOCK(pmap); 4328 if (rv) 4329 break; 4330 } 4331 sched_unpin(); 4332 return (rv); 4333} 4334 4335/* 4336 * pmap_is_prefaultable: 4337 * 4338 * Return whether or not the specified virtual address is elgible 4339 * for prefault. 4340 */ 4341boolean_t 4342pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr) 4343{ 4344 pd_entry_t *pde; 4345 pt_entry_t *pte; 4346 boolean_t rv; 4347 4348 rv = FALSE; 4349 PMAP_LOCK(pmap); 4350 pde = pmap_pde(pmap, addr); 4351 if (*pde != 0 && (*pde & PG_PS) == 0) { 4352 pte = vtopte(addr); 4353 rv = *pte == 0; 4354 } 4355 PMAP_UNLOCK(pmap); 4356 return (rv); 4357} 4358 4359/* 4360 * pmap_is_referenced: 4361 * 4362 * Return whether or not the specified physical page was referenced 4363 * in any physical maps. 4364 */ 4365boolean_t 4366pmap_is_referenced(vm_page_t m) 4367{ 4368 4369 if (m->flags & PG_FICTITIOUS) 4370 return (FALSE); 4371 if (pmap_is_referenced_pvh(&m->md)) 4372 return (TRUE); 4373 return (pmap_is_referenced_pvh(pa_to_pvh(VM_PAGE_TO_PHYS(m)))); 4374} 4375 4376/* 4377 * Returns TRUE if any of the given mappings were referenced and FALSE 4378 * otherwise. Both page and 4mpage mappings are supported. 4379 */ 4380static boolean_t 4381pmap_is_referenced_pvh(struct md_page *pvh) 4382{ 4383 pv_entry_t pv; 4384 pt_entry_t *pte; 4385 pmap_t pmap; 4386 boolean_t rv; 4387 4388 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 4389 rv = FALSE; 4390 sched_pin(); 4391 TAILQ_FOREACH(pv, &pvh->pv_list, pv_list) { 4392 pmap = PV_PMAP(pv); 4393 PMAP_LOCK(pmap); 4394 pte = pmap_pte_quick(pmap, pv->pv_va); 4395 rv = (*pte & (PG_A | PG_V)) == (PG_A | PG_V); 4396 PMAP_UNLOCK(pmap); 4397 if (rv) 4398 break; 4399 } 4400 sched_unpin(); 4401 return (rv); 4402} 4403 4404/* 4405 * Clear the write and modified bits in each of the given page's mappings. 4406 */ 4407void 4408pmap_remove_write(vm_page_t m) 4409{ 4410 struct md_page *pvh; 4411 pv_entry_t next_pv, pv; 4412 pmap_t pmap; 4413 pd_entry_t *pde; 4414 pt_entry_t oldpte, *pte; 4415 vm_offset_t va; 4416 4417 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 4418 if ((m->flags & PG_FICTITIOUS) != 0 || 4419 (m->flags & PG_WRITEABLE) == 0) 4420 return; 4421 sched_pin(); 4422 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 4423 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_list, next_pv) { 4424 va = pv->pv_va; 4425 pmap = PV_PMAP(pv); 4426 PMAP_LOCK(pmap); 4427 pde = pmap_pde(pmap, va); 4428 if ((*pde & PG_RW) != 0) 4429 (void)pmap_demote_pde(pmap, pde, va); 4430 PMAP_UNLOCK(pmap); 4431 } 4432 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 4433 pmap = PV_PMAP(pv); 4434 PMAP_LOCK(pmap); 4435 pde = pmap_pde(pmap, pv->pv_va); 4436 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_write: found" 4437 " a 4mpage in page %p's pv list", m)); 4438 pte = pmap_pte_quick(pmap, pv->pv_va); 4439retry: 4440 oldpte = *pte; 4441 if ((oldpte & PG_RW) != 0) { 4442 /* 4443 * Regardless of whether a pte is 32 or 64 bits 4444 * in size, PG_RW and PG_M are among the least 4445 * significant 32 bits. 4446 */ 4447 if (!atomic_cmpset_int((u_int *)pte, oldpte, 4448 oldpte & ~(PG_RW | PG_M))) 4449 goto retry; 4450 if ((oldpte & PG_M) != 0) 4451 vm_page_dirty(m); 4452 pmap_invalidate_page(pmap, pv->pv_va); 4453 } 4454 PMAP_UNLOCK(pmap); 4455 } 4456 vm_page_flag_clear(m, PG_WRITEABLE); 4457 sched_unpin(); 4458} 4459 4460/* 4461 * pmap_ts_referenced: 4462 * 4463 * Return a count of reference bits for a page, clearing those bits. 4464 * It is not necessary for every reference bit to be cleared, but it 4465 * is necessary that 0 only be returned when there are truly no 4466 * reference bits set. 4467 * 4468 * XXX: The exact number of bits to check and clear is a matter that 4469 * should be tested and standardized at some point in the future for 4470 * optimal aging of shared pages. 4471 */ 4472int 4473pmap_ts_referenced(vm_page_t m) 4474{ 4475 struct md_page *pvh; 4476 pv_entry_t pv, pvf, pvn; 4477 pmap_t pmap; 4478 pd_entry_t oldpde, *pde; 4479 pt_entry_t *pte; 4480 vm_offset_t va; 4481 int rtval = 0; 4482 4483 if (m->flags & PG_FICTITIOUS) 4484 return (rtval); 4485 sched_pin(); 4486 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 4487 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 4488 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_list, pvn) { 4489 va = pv->pv_va; 4490 pmap = PV_PMAP(pv); 4491 PMAP_LOCK(pmap); 4492 pde = pmap_pde(pmap, va); 4493 oldpde = *pde; 4494 if ((oldpde & PG_A) != 0) { 4495 if (pmap_demote_pde(pmap, pde, va)) { 4496 if ((oldpde & PG_W) == 0) { 4497 /* 4498 * Remove the mapping to a single page 4499 * so that a subsequent access may 4500 * repromote. Since the underlying 4501 * page table page is fully populated, 4502 * this removal never frees a page 4503 * table page. 4504 */ 4505 va += VM_PAGE_TO_PHYS(m) - (oldpde & 4506 PG_PS_FRAME); 4507 pmap_remove_page(pmap, va, NULL); 4508 rtval++; 4509 if (rtval > 4) { 4510 PMAP_UNLOCK(pmap); 4511 return (rtval); 4512 } 4513 } 4514 } 4515 } 4516 PMAP_UNLOCK(pmap); 4517 } 4518 if ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) { 4519 pvf = pv; 4520 do { 4521 pvn = TAILQ_NEXT(pv, pv_list); 4522 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list); 4523 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list); 4524 pmap = PV_PMAP(pv); 4525 PMAP_LOCK(pmap); 4526 pde = pmap_pde(pmap, pv->pv_va); 4527 KASSERT((*pde & PG_PS) == 0, ("pmap_ts_referenced:" 4528 " found a 4mpage in page %p's pv list", m)); 4529 pte = pmap_pte_quick(pmap, pv->pv_va); 4530 if ((*pte & PG_A) != 0) { 4531 atomic_clear_int((u_int *)pte, PG_A); 4532 pmap_invalidate_page(pmap, pv->pv_va); 4533 rtval++; 4534 if (rtval > 4) 4535 pvn = NULL; 4536 } 4537 PMAP_UNLOCK(pmap); 4538 } while ((pv = pvn) != NULL && pv != pvf); 4539 } 4540 sched_unpin(); 4541 return (rtval); 4542} 4543 4544/* 4545 * Clear the modify bits on the specified physical page. 4546 */ 4547void 4548pmap_clear_modify(vm_page_t m) 4549{ 4550 struct md_page *pvh; 4551 pv_entry_t next_pv, pv; 4552 pmap_t pmap; 4553 pd_entry_t oldpde, *pde; 4554 pt_entry_t oldpte, *pte; 4555 vm_offset_t va; 4556 4557 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 4558 if ((m->flags & PG_FICTITIOUS) != 0) 4559 return; 4560 sched_pin(); 4561 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 4562 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_list, next_pv) { 4563 va = pv->pv_va; 4564 pmap = PV_PMAP(pv); 4565 PMAP_LOCK(pmap); 4566 pde = pmap_pde(pmap, va); 4567 oldpde = *pde; 4568 if ((oldpde & PG_RW) != 0) { 4569 if (pmap_demote_pde(pmap, pde, va)) { 4570 if ((oldpde & PG_W) == 0) { 4571 /* 4572 * Write protect the mapping to a 4573 * single page so that a subsequent 4574 * write access may repromote. 4575 */ 4576 va += VM_PAGE_TO_PHYS(m) - (oldpde & 4577 PG_PS_FRAME); 4578 pte = pmap_pte_quick(pmap, va); 4579 oldpte = *pte; 4580 if ((oldpte & PG_V) != 0) { 4581 /* 4582 * Regardless of whether a pte is 32 or 64 bits 4583 * in size, PG_RW and PG_M are among the least 4584 * significant 32 bits. 4585 */ 4586 while (!atomic_cmpset_int((u_int *)pte, 4587 oldpte, 4588 oldpte & ~(PG_M | PG_RW))) 4589 oldpte = *pte; 4590 vm_page_dirty(m); 4591 pmap_invalidate_page(pmap, va); 4592 } 4593 } 4594 } 4595 } 4596 PMAP_UNLOCK(pmap); 4597 } 4598 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 4599 pmap = PV_PMAP(pv); 4600 PMAP_LOCK(pmap); 4601 pde = pmap_pde(pmap, pv->pv_va); 4602 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_modify: found" 4603 " a 4mpage in page %p's pv list", m)); 4604 pte = pmap_pte_quick(pmap, pv->pv_va); 4605 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) { 4606 /* 4607 * Regardless of whether a pte is 32 or 64 bits 4608 * in size, PG_M is among the least significant 4609 * 32 bits. 4610 */ 4611 atomic_clear_int((u_int *)pte, PG_M); 4612 pmap_invalidate_page(pmap, pv->pv_va); 4613 } 4614 PMAP_UNLOCK(pmap); 4615 } 4616 sched_unpin(); 4617} 4618 4619/* 4620 * pmap_clear_reference: 4621 * 4622 * Clear the reference bit on the specified physical page. 4623 */ 4624void 4625pmap_clear_reference(vm_page_t m) 4626{ 4627 struct md_page *pvh; 4628 pv_entry_t next_pv, pv; 4629 pmap_t pmap; 4630 pd_entry_t oldpde, *pde; 4631 pt_entry_t *pte; 4632 vm_offset_t va; 4633 4634 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 4635 if ((m->flags & PG_FICTITIOUS) != 0) 4636 return; 4637 sched_pin(); 4638 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 4639 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_list, next_pv) { 4640 va = pv->pv_va; 4641 pmap = PV_PMAP(pv); 4642 PMAP_LOCK(pmap); 4643 pde = pmap_pde(pmap, va); 4644 oldpde = *pde; 4645 if ((oldpde & PG_A) != 0) { 4646 if (pmap_demote_pde(pmap, pde, va)) { 4647 /* 4648 * Remove the mapping to a single page so 4649 * that a subsequent access may repromote. 4650 * Since the underlying page table page is 4651 * fully populated, this removal never frees 4652 * a page table page. 4653 */ 4654 va += VM_PAGE_TO_PHYS(m) - (oldpde & 4655 PG_PS_FRAME); 4656 pmap_remove_page(pmap, va, NULL); 4657 } 4658 } 4659 PMAP_UNLOCK(pmap); 4660 } 4661 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 4662 pmap = PV_PMAP(pv); 4663 PMAP_LOCK(pmap); 4664 pde = pmap_pde(pmap, pv->pv_va); 4665 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_reference: found" 4666 " a 4mpage in page %p's pv list", m)); 4667 pte = pmap_pte_quick(pmap, pv->pv_va); 4668 if ((*pte & PG_A) != 0) { 4669 /* 4670 * Regardless of whether a pte is 32 or 64 bits 4671 * in size, PG_A is among the least significant 4672 * 32 bits. 4673 */ 4674 atomic_clear_int((u_int *)pte, PG_A); 4675 pmap_invalidate_page(pmap, pv->pv_va); 4676 } 4677 PMAP_UNLOCK(pmap); 4678 } 4679 sched_unpin(); 4680} 4681 4682/* 4683 * Miscellaneous support routines follow 4684 */ 4685 4686/* Adjust the cache mode for a 4KB page mapped via a PTE. */ 4687static __inline void 4688pmap_pte_attr(pt_entry_t *pte, int cache_bits) 4689{ 4690 u_int opte, npte; 4691 4692 /* 4693 * The cache mode bits are all in the low 32-bits of the 4694 * PTE, so we can just spin on updating the low 32-bits. 4695 */ 4696 do { 4697 opte = *(u_int *)pte; 4698 npte = opte & ~PG_PTE_CACHE; 4699 npte |= cache_bits; 4700 } while (npte != opte && !atomic_cmpset_int((u_int *)pte, opte, npte)); 4701} 4702 4703/* Adjust the cache mode for a 2/4MB page mapped via a PDE. */ 4704static __inline void 4705pmap_pde_attr(pd_entry_t *pde, int cache_bits) 4706{ 4707 u_int opde, npde; 4708 4709 /* 4710 * The cache mode bits are all in the low 32-bits of the 4711 * PDE, so we can just spin on updating the low 32-bits. 4712 */ 4713 do { 4714 opde = *(u_int *)pde; 4715 npde = opde & ~PG_PDE_CACHE; 4716 npde |= cache_bits; 4717 } while (npde != opde && !atomic_cmpset_int((u_int *)pde, opde, npde)); 4718} 4719 4720/* 4721 * Map a set of physical memory pages into the kernel virtual 4722 * address space. Return a pointer to where it is mapped. This 4723 * routine is intended to be used for mapping device memory, 4724 * NOT real memory. 4725 */ 4726void * 4727pmap_mapdev_attr(vm_paddr_t pa, vm_size_t size, int mode) 4728{ 4729 vm_offset_t va, offset; 4730 vm_size_t tmpsize; 4731 4732 offset = pa & PAGE_MASK; 4733 size = roundup(offset + size, PAGE_SIZE); 4734 pa = pa & PG_FRAME; 4735 4736 if (pa < KERNLOAD && pa + size <= KERNLOAD) 4737 va = KERNBASE + pa; 4738 else 4739 va = kmem_alloc_nofault(kernel_map, size); 4740 if (!va) 4741 panic("pmap_mapdev: Couldn't alloc kernel virtual memory"); 4742 4743 for (tmpsize = 0; tmpsize < size; tmpsize += PAGE_SIZE) 4744 pmap_kenter_attr(va + tmpsize, pa + tmpsize, mode); 4745 pmap_invalidate_range(kernel_pmap, va, va + tmpsize); 4746 pmap_invalidate_cache_range(va, va + size); 4747 return ((void *)(va + offset)); 4748} 4749 4750void * 4751pmap_mapdev(vm_paddr_t pa, vm_size_t size) 4752{ 4753 4754 return (pmap_mapdev_attr(pa, size, PAT_UNCACHEABLE)); 4755} 4756 4757void * 4758pmap_mapbios(vm_paddr_t pa, vm_size_t size) 4759{ 4760 4761 return (pmap_mapdev_attr(pa, size, PAT_WRITE_BACK)); 4762} 4763 4764void 4765pmap_unmapdev(vm_offset_t va, vm_size_t size) 4766{ 4767 vm_offset_t base, offset, tmpva; 4768 4769 if (va >= KERNBASE && va + size <= KERNBASE + KERNLOAD) 4770 return; 4771 base = trunc_page(va); 4772 offset = va & PAGE_MASK; 4773 size = roundup(offset + size, PAGE_SIZE); 4774 for (tmpva = base; tmpva < (base + size); tmpva += PAGE_SIZE) 4775 pmap_kremove(tmpva); 4776 pmap_invalidate_range(kernel_pmap, va, tmpva); 4777 kmem_free(kernel_map, base, size); 4778} 4779 4780/* 4781 * Sets the memory attribute for the specified page. 4782 */ 4783void 4784pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma) 4785{ 4786 struct sysmaps *sysmaps; 4787 vm_offset_t sva, eva; 4788 4789 m->md.pat_mode = ma; 4790 if ((m->flags & PG_FICTITIOUS) != 0) 4791 return; 4792 4793 /* 4794 * If "m" is a normal page, flush it from the cache. 4795 * See pmap_invalidate_cache_range(). 4796 * 4797 * First, try to find an existing mapping of the page by sf 4798 * buffer. sf_buf_invalidate_cache() modifies mapping and 4799 * flushes the cache. 4800 */ 4801 if (sf_buf_invalidate_cache(m)) 4802 return; 4803 4804 /* 4805 * If page is not mapped by sf buffer, but CPU does not 4806 * support self snoop, map the page transient and do 4807 * invalidation. In the worst case, whole cache is flushed by 4808 * pmap_invalidate_cache_range(). 4809 */ 4810 if ((cpu_feature & (CPUID_SS|CPUID_CLFSH)) == CPUID_CLFSH) { 4811 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)]; 4812 mtx_lock(&sysmaps->lock); 4813 if (*sysmaps->CMAP2) 4814 panic("pmap_page_set_memattr: CMAP2 busy"); 4815 sched_pin(); 4816 *sysmaps->CMAP2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | 4817 PG_A | PG_M | pmap_cache_bits(m->md.pat_mode, 0); 4818 invlcaddr(sysmaps->CADDR2); 4819 sva = (vm_offset_t)sysmaps->CADDR2; 4820 eva = sva + PAGE_SIZE; 4821 } else 4822 sva = eva = 0; /* gcc */ 4823 pmap_invalidate_cache_range(sva, eva); 4824 if (sva != 0) { 4825 *sysmaps->CMAP2 = 0; 4826 sched_unpin(); 4827 mtx_unlock(&sysmaps->lock); 4828 } 4829} 4830 4831/* 4832 * Changes the specified virtual address range's memory type to that given by 4833 * the parameter "mode". The specified virtual address range must be 4834 * completely contained within either the kernel map. 4835 * 4836 * Returns zero if the change completed successfully, and either EINVAL or 4837 * ENOMEM if the change failed. Specifically, EINVAL is returned if some part 4838 * of the virtual address range was not mapped, and ENOMEM is returned if 4839 * there was insufficient memory available to complete the change. 4840 */ 4841int 4842pmap_change_attr(vm_offset_t va, vm_size_t size, int mode) 4843{ 4844 vm_offset_t base, offset, tmpva; 4845 pd_entry_t *pde; 4846 pt_entry_t *pte; 4847 int cache_bits_pte, cache_bits_pde; 4848 boolean_t changed; 4849 4850 base = trunc_page(va); 4851 offset = va & PAGE_MASK; 4852 size = roundup(offset + size, PAGE_SIZE); 4853 4854 /* 4855 * Only supported on kernel virtual addresses above the recursive map. 4856 */ 4857 if (base < VM_MIN_KERNEL_ADDRESS) 4858 return (EINVAL); 4859 4860 cache_bits_pde = pmap_cache_bits(mode, 1); 4861 cache_bits_pte = pmap_cache_bits(mode, 0); 4862 changed = FALSE; 4863 4864 /* 4865 * Pages that aren't mapped aren't supported. Also break down 4866 * 2/4MB pages into 4KB pages if required. 4867 */ 4868 PMAP_LOCK(kernel_pmap); 4869 for (tmpva = base; tmpva < base + size; ) { 4870 pde = pmap_pde(kernel_pmap, tmpva); 4871 if (*pde == 0) { 4872 PMAP_UNLOCK(kernel_pmap); 4873 return (EINVAL); 4874 } 4875 if (*pde & PG_PS) { 4876 /* 4877 * If the current 2/4MB page already has 4878 * the required memory type, then we need not 4879 * demote this page. Just increment tmpva to 4880 * the next 2/4MB page frame. 4881 */ 4882 if ((*pde & PG_PDE_CACHE) == cache_bits_pde) { 4883 tmpva = trunc_4mpage(tmpva) + NBPDR; 4884 continue; 4885 } 4886 4887 /* 4888 * If the current offset aligns with a 2/4MB 4889 * page frame and there is at least 2/4MB left 4890 * within the range, then we need not break 4891 * down this page into 4KB pages. 4892 */ 4893 if ((tmpva & PDRMASK) == 0 && 4894 tmpva + PDRMASK < base + size) { 4895 tmpva += NBPDR; 4896 continue; 4897 } 4898 if (!pmap_demote_pde(kernel_pmap, pde, tmpva)) { 4899 PMAP_UNLOCK(kernel_pmap); 4900 return (ENOMEM); 4901 } 4902 } 4903 pte = vtopte(tmpva); 4904 if (*pte == 0) { 4905 PMAP_UNLOCK(kernel_pmap); 4906 return (EINVAL); 4907 } 4908 tmpva += PAGE_SIZE; 4909 } 4910 PMAP_UNLOCK(kernel_pmap); 4911 4912 /* 4913 * Ok, all the pages exist, so run through them updating their 4914 * cache mode if required. 4915 */ 4916 for (tmpva = base; tmpva < base + size; ) { 4917 pde = pmap_pde(kernel_pmap, tmpva); 4918 if (*pde & PG_PS) { 4919 if ((*pde & PG_PDE_CACHE) != cache_bits_pde) { 4920 pmap_pde_attr(pde, cache_bits_pde); 4921 changed = TRUE; 4922 } 4923 tmpva = trunc_4mpage(tmpva) + NBPDR; 4924 } else { 4925 pte = vtopte(tmpva); 4926 if ((*pte & PG_PTE_CACHE) != cache_bits_pte) { 4927 pmap_pte_attr(pte, cache_bits_pte); 4928 changed = TRUE; 4929 } 4930 tmpva += PAGE_SIZE; 4931 } 4932 } 4933 4934 /* 4935 * Flush CPU caches to make sure any data isn't cached that 4936 * shouldn't be, etc. 4937 */ 4938 if (changed) { 4939 pmap_invalidate_range(kernel_pmap, base, tmpva); 4940 pmap_invalidate_cache_range(base, tmpva); 4941 } 4942 return (0); 4943} 4944 4945/* 4946 * perform the pmap work for mincore 4947 */ 4948int 4949pmap_mincore(pmap_t pmap, vm_offset_t addr) 4950{ 4951 pd_entry_t *pdep; 4952 pt_entry_t *ptep, pte; 4953 vm_paddr_t pa; 4954 vm_page_t m; 4955 int val = 0; 4956 4957 PMAP_LOCK(pmap); 4958 pdep = pmap_pde(pmap, addr); 4959 if (*pdep != 0) { 4960 if (*pdep & PG_PS) { 4961 pte = *pdep; 4962 val = MINCORE_SUPER; 4963 /* Compute the physical address of the 4KB page. */ 4964 pa = ((*pdep & PG_PS_FRAME) | (addr & PDRMASK)) & 4965 PG_FRAME; 4966 } else { 4967 ptep = pmap_pte(pmap, addr); 4968 pte = *ptep; 4969 pmap_pte_release(ptep); 4970 pa = pte & PG_FRAME; 4971 } 4972 } else { 4973 pte = 0; 4974 pa = 0; 4975 } 4976 PMAP_UNLOCK(pmap); 4977 4978 if (pte != 0) { 4979 val |= MINCORE_INCORE; 4980 if ((pte & PG_MANAGED) == 0) 4981 return (val); 4982 4983 m = PHYS_TO_VM_PAGE(pa); 4984 4985 /* 4986 * Modified by us 4987 */ 4988 if ((pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) 4989 val |= MINCORE_MODIFIED|MINCORE_MODIFIED_OTHER; 4990 else { 4991 /* 4992 * Modified by someone else 4993 */ 4994 vm_page_lock_queues(); 4995 if (m->dirty || pmap_is_modified(m)) 4996 val |= MINCORE_MODIFIED_OTHER; 4997 vm_page_unlock_queues(); 4998 } 4999 /* 5000 * Referenced by us 5001 */ 5002 if (pte & PG_A) 5003 val |= MINCORE_REFERENCED|MINCORE_REFERENCED_OTHER; 5004 else { 5005 /* 5006 * Referenced by someone else 5007 */ 5008 vm_page_lock_queues(); 5009 if ((m->flags & PG_REFERENCED) || 5010 pmap_is_referenced(m)) 5011 val |= MINCORE_REFERENCED_OTHER; 5012 vm_page_unlock_queues(); 5013 } 5014 } 5015 return (val); 5016} 5017 5018void 5019pmap_activate(struct thread *td) 5020{ 5021 pmap_t pmap, oldpmap; 5022 u_int32_t cr3; 5023 5024 critical_enter(); 5025 pmap = vmspace_pmap(td->td_proc->p_vmspace); 5026 oldpmap = PCPU_GET(curpmap); 5027#if defined(SMP) 5028 atomic_clear_int(&oldpmap->pm_active, PCPU_GET(cpumask)); 5029 atomic_set_int(&pmap->pm_active, PCPU_GET(cpumask)); 5030#else 5031 oldpmap->pm_active &= ~1; 5032 pmap->pm_active |= 1; 5033#endif 5034#ifdef PAE 5035 cr3 = vtophys(pmap->pm_pdpt); 5036#else 5037 cr3 = vtophys(pmap->pm_pdir); 5038#endif 5039 /* 5040 * pmap_activate is for the current thread on the current cpu 5041 */ 5042 td->td_pcb->pcb_cr3 = cr3; 5043 load_cr3(cr3); 5044 PCPU_SET(curpmap, pmap); 5045 critical_exit(); 5046} 5047 5048void 5049pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz) 5050{ 5051} 5052 5053/* 5054 * Increase the starting virtual address of the given mapping if a 5055 * different alignment might result in more superpage mappings. 5056 */ 5057void 5058pmap_align_superpage(vm_object_t object, vm_ooffset_t offset, 5059 vm_offset_t *addr, vm_size_t size) 5060{ 5061 vm_offset_t superpage_offset; 5062 5063 if (size < NBPDR) 5064 return; 5065 if (object != NULL && (object->flags & OBJ_COLORED) != 0) 5066 offset += ptoa(object->pg_color); 5067 superpage_offset = offset & PDRMASK; 5068 if (size - ((NBPDR - superpage_offset) & PDRMASK) < NBPDR || 5069 (*addr & PDRMASK) == superpage_offset) 5070 return; 5071 if ((*addr & PDRMASK) < superpage_offset) 5072 *addr = (*addr & ~PDRMASK) + superpage_offset; 5073 else 5074 *addr = ((*addr + PDRMASK) & ~PDRMASK) + superpage_offset; 5075} 5076 5077 5078#if defined(PMAP_DEBUG) 5079pmap_pid_dump(int pid) 5080{ 5081 pmap_t pmap; 5082 struct proc *p; 5083 int npte = 0; 5084 int index; 5085 5086 sx_slock(&allproc_lock); 5087 FOREACH_PROC_IN_SYSTEM(p) { 5088 if (p->p_pid != pid) 5089 continue; 5090 5091 if (p->p_vmspace) { 5092 int i,j; 5093 index = 0; 5094 pmap = vmspace_pmap(p->p_vmspace); 5095 for (i = 0; i < NPDEPTD; i++) { 5096 pd_entry_t *pde; 5097 pt_entry_t *pte; 5098 vm_offset_t base = i << PDRSHIFT; 5099 5100 pde = &pmap->pm_pdir[i]; 5101 if (pde && pmap_pde_v(pde)) { 5102 for (j = 0; j < NPTEPG; j++) { 5103 vm_offset_t va = base + (j << PAGE_SHIFT); 5104 if (va >= (vm_offset_t) VM_MIN_KERNEL_ADDRESS) { 5105 if (index) { 5106 index = 0; 5107 printf("\n"); 5108 } 5109 sx_sunlock(&allproc_lock); 5110 return (npte); 5111 } 5112 pte = pmap_pte(pmap, va); 5113 if (pte && pmap_pte_v(pte)) { 5114 pt_entry_t pa; 5115 vm_page_t m; 5116 pa = *pte; 5117 m = PHYS_TO_VM_PAGE(pa & PG_FRAME); 5118 printf("va: 0x%x, pt: 0x%x, h: %d, w: %d, f: 0x%x", 5119 va, pa, m->hold_count, m->wire_count, m->flags); 5120 npte++; 5121 index++; 5122 if (index >= 2) { 5123 index = 0; 5124 printf("\n"); 5125 } else { 5126 printf(" "); 5127 } 5128 } 5129 } 5130 } 5131 } 5132 } 5133 } 5134 sx_sunlock(&allproc_lock); 5135 return (npte); 5136} 5137#endif 5138 5139#if defined(DEBUG) 5140 5141static void pads(pmap_t pm); 5142void pmap_pvdump(vm_offset_t pa); 5143 5144/* print address space of pmap*/ 5145static void 5146pads(pmap_t pm) 5147{ 5148 int i, j; 5149 vm_paddr_t va; 5150 pt_entry_t *ptep; 5151 5152 if (pm == kernel_pmap) 5153 return; 5154 for (i = 0; i < NPDEPTD; i++) 5155 if (pm->pm_pdir[i]) 5156 for (j = 0; j < NPTEPG; j++) { 5157 va = (i << PDRSHIFT) + (j << PAGE_SHIFT); 5158 if (pm == kernel_pmap && va < KERNBASE) 5159 continue; 5160 if (pm != kernel_pmap && va > UPT_MAX_ADDRESS) 5161 continue; 5162 ptep = pmap_pte(pm, va); 5163 if (pmap_pte_v(ptep)) 5164 printf("%x:%x ", va, *ptep); 5165 }; 5166 5167} 5168 5169void 5170pmap_pvdump(vm_paddr_t pa) 5171{ 5172 pv_entry_t pv; 5173 pmap_t pmap; 5174 vm_page_t m; 5175 5176 printf("pa %x", pa); 5177 m = PHYS_TO_VM_PAGE(pa); 5178 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 5179 pmap = PV_PMAP(pv); 5180 printf(" -> pmap %p, va %x", (void *)pmap, pv->pv_va); 5181 pads(pmap); 5182 } 5183 printf(" "); 5184} 5185#endif 5186