pmap.c revision 205063
1/*- 2 * Copyright (c) 1991 Regents of the University of California. 3 * All rights reserved. 4 * Copyright (c) 1994 John S. Dyson 5 * All rights reserved. 6 * Copyright (c) 1994 David Greenman 7 * All rights reserved. 8 * Copyright (c) 2005-2008 Alan L. Cox <alc@cs.rice.edu> 9 * All rights reserved. 10 * 11 * This code is derived from software contributed to Berkeley by 12 * the Systems Programming Group of the University of Utah Computer 13 * Science Department and William Jolitz of UUNET Technologies Inc. 14 * 15 * Redistribution and use in source and binary forms, with or without 16 * modification, are permitted provided that the following conditions 17 * are met: 18 * 1. Redistributions of source code must retain the above copyright 19 * notice, this list of conditions and the following disclaimer. 20 * 2. Redistributions in binary form must reproduce the above copyright 21 * notice, this list of conditions and the following disclaimer in the 22 * documentation and/or other materials provided with the distribution. 23 * 3. All advertising materials mentioning features or use of this software 24 * must display the following acknowledgement: 25 * This product includes software developed by the University of 26 * California, Berkeley and its contributors. 27 * 4. Neither the name of the University nor the names of its contributors 28 * may be used to endorse or promote products derived from this software 29 * without specific prior written permission. 30 * 31 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 32 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 33 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 34 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 35 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 36 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 37 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 38 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 39 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 40 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 41 * SUCH DAMAGE. 42 * 43 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91 44 */ 45/*- 46 * Copyright (c) 2003 Networks Associates Technology, Inc. 47 * All rights reserved. 48 * 49 * This software was developed for the FreeBSD Project by Jake Burkholder, 50 * Safeport Network Services, and Network Associates Laboratories, the 51 * Security Research Division of Network Associates, Inc. under 52 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA 53 * CHATS research program. 54 * 55 * Redistribution and use in source and binary forms, with or without 56 * modification, are permitted provided that the following conditions 57 * are met: 58 * 1. Redistributions of source code must retain the above copyright 59 * notice, this list of conditions and the following disclaimer. 60 * 2. Redistributions in binary form must reproduce the above copyright 61 * notice, this list of conditions and the following disclaimer in the 62 * documentation and/or other materials provided with the distribution. 63 * 64 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 65 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 66 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 67 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 68 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 69 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 70 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 71 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 72 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 73 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 74 * SUCH DAMAGE. 75 */ 76 77#include <sys/cdefs.h> 78__FBSDID("$FreeBSD: head/sys/i386/i386/pmap.c 205063 2010-03-12 03:08:47Z jhb $"); 79 80/* 81 * Manages physical address maps. 82 * 83 * In addition to hardware address maps, this 84 * module is called upon to provide software-use-only 85 * maps which may or may not be stored in the same 86 * form as hardware maps. These pseudo-maps are 87 * used to store intermediate results from copy 88 * operations to and from address spaces. 89 * 90 * Since the information managed by this module is 91 * also stored by the logical address mapping module, 92 * this module may throw away valid virtual-to-physical 93 * mappings at almost any time. However, invalidations 94 * of virtual-to-physical mappings must be done as 95 * requested. 96 * 97 * In order to cope with hardware architectures which 98 * make virtual-to-physical map invalidates expensive, 99 * this module may delay invalidate or reduced protection 100 * operations until such time as they are actually 101 * necessary. This module is given full information as 102 * to which processors are currently using which maps, 103 * and to when physical maps must be made correct. 104 */ 105 106#include "opt_cpu.h" 107#include "opt_pmap.h" 108#include "opt_msgbuf.h" 109#include "opt_smp.h" 110#include "opt_xbox.h" 111 112#include <sys/param.h> 113#include <sys/systm.h> 114#include <sys/kernel.h> 115#include <sys/ktr.h> 116#include <sys/lock.h> 117#include <sys/malloc.h> 118#include <sys/mman.h> 119#include <sys/msgbuf.h> 120#include <sys/mutex.h> 121#include <sys/proc.h> 122#include <sys/sf_buf.h> 123#include <sys/sx.h> 124#include <sys/vmmeter.h> 125#include <sys/sched.h> 126#include <sys/sysctl.h> 127#ifdef SMP 128#include <sys/smp.h> 129#endif 130 131#include <vm/vm.h> 132#include <vm/vm_param.h> 133#include <vm/vm_kern.h> 134#include <vm/vm_page.h> 135#include <vm/vm_map.h> 136#include <vm/vm_object.h> 137#include <vm/vm_extern.h> 138#include <vm/vm_pageout.h> 139#include <vm/vm_pager.h> 140#include <vm/vm_reserv.h> 141#include <vm/uma.h> 142 143#include <machine/cpu.h> 144#include <machine/cputypes.h> 145#include <machine/md_var.h> 146#include <machine/pcb.h> 147#include <machine/specialreg.h> 148#ifdef SMP 149#include <machine/smp.h> 150#endif 151 152#ifdef XBOX 153#include <machine/xbox.h> 154#endif 155 156#if !defined(CPU_DISABLE_SSE) && defined(I686_CPU) 157#define CPU_ENABLE_SSE 158#endif 159 160#ifndef PMAP_SHPGPERPROC 161#define PMAP_SHPGPERPROC 200 162#endif 163 164#if !defined(DIAGNOSTIC) 165#ifdef __GNUC_GNU_INLINE__ 166#define PMAP_INLINE __attribute__((__gnu_inline__)) inline 167#else 168#define PMAP_INLINE extern inline 169#endif 170#else 171#define PMAP_INLINE 172#endif 173 174#define PV_STATS 175#ifdef PV_STATS 176#define PV_STAT(x) do { x ; } while (0) 177#else 178#define PV_STAT(x) do { } while (0) 179#endif 180 181#define pa_index(pa) ((pa) >> PDRSHIFT) 182#define pa_to_pvh(pa) (&pv_table[pa_index(pa)]) 183 184/* 185 * Get PDEs and PTEs for user/kernel address space 186 */ 187#define pmap_pde(m, v) (&((m)->pm_pdir[(vm_offset_t)(v) >> PDRSHIFT])) 188#define pdir_pde(m, v) (m[(vm_offset_t)(v) >> PDRSHIFT]) 189 190#define pmap_pde_v(pte) ((*(int *)pte & PG_V) != 0) 191#define pmap_pte_w(pte) ((*(int *)pte & PG_W) != 0) 192#define pmap_pte_m(pte) ((*(int *)pte & PG_M) != 0) 193#define pmap_pte_u(pte) ((*(int *)pte & PG_A) != 0) 194#define pmap_pte_v(pte) ((*(int *)pte & PG_V) != 0) 195 196#define pmap_pte_set_w(pte, v) ((v) ? atomic_set_int((u_int *)(pte), PG_W) : \ 197 atomic_clear_int((u_int *)(pte), PG_W)) 198#define pmap_pte_set_prot(pte, v) ((*(int *)pte &= ~PG_PROT), (*(int *)pte |= (v))) 199 200struct pmap kernel_pmap_store; 201LIST_HEAD(pmaplist, pmap); 202static struct pmaplist allpmaps; 203static struct mtx allpmaps_lock; 204 205vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */ 206vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */ 207int pgeflag = 0; /* PG_G or-in */ 208int pseflag = 0; /* PG_PS or-in */ 209 210static int nkpt; 211vm_offset_t kernel_vm_end; 212extern u_int32_t KERNend; 213extern u_int32_t KPTphys; 214 215#ifdef PAE 216pt_entry_t pg_nx; 217static uma_zone_t pdptzone; 218#endif 219 220static int pat_works = 0; /* Is page attribute table sane? */ 221 222SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD, 0, "VM/pmap parameters"); 223 224static int pg_ps_enabled = 1; 225SYSCTL_INT(_vm_pmap, OID_AUTO, pg_ps_enabled, CTLFLAG_RDTUN, &pg_ps_enabled, 0, 226 "Are large page mappings enabled?"); 227 228/* 229 * Data for the pv entry allocation mechanism 230 */ 231static int pv_entry_count = 0, pv_entry_max = 0, pv_entry_high_water = 0; 232static struct md_page *pv_table; 233static int shpgperproc = PMAP_SHPGPERPROC; 234 235struct pv_chunk *pv_chunkbase; /* KVA block for pv_chunks */ 236int pv_maxchunks; /* How many chunks we have KVA for */ 237vm_offset_t pv_vafree; /* freelist stored in the PTE */ 238 239/* 240 * All those kernel PT submaps that BSD is so fond of 241 */ 242struct sysmaps { 243 struct mtx lock; 244 pt_entry_t *CMAP1; 245 pt_entry_t *CMAP2; 246 caddr_t CADDR1; 247 caddr_t CADDR2; 248}; 249static struct sysmaps sysmaps_pcpu[MAXCPU]; 250pt_entry_t *CMAP1 = 0, *KPTmap; 251static pt_entry_t *CMAP3; 252static pd_entry_t *KPTD; 253caddr_t CADDR1 = 0, ptvmmap = 0; 254static caddr_t CADDR3; 255struct msgbuf *msgbufp = 0; 256 257/* 258 * Crashdump maps. 259 */ 260static caddr_t crashdumpmap; 261 262static pt_entry_t *PMAP1 = 0, *PMAP2; 263static pt_entry_t *PADDR1 = 0, *PADDR2; 264#ifdef SMP 265static int PMAP1cpu; 266static int PMAP1changedcpu; 267SYSCTL_INT(_debug, OID_AUTO, PMAP1changedcpu, CTLFLAG_RD, 268 &PMAP1changedcpu, 0, 269 "Number of times pmap_pte_quick changed CPU with same PMAP1"); 270#endif 271static int PMAP1changed; 272SYSCTL_INT(_debug, OID_AUTO, PMAP1changed, CTLFLAG_RD, 273 &PMAP1changed, 0, 274 "Number of times pmap_pte_quick changed PMAP1"); 275static int PMAP1unchanged; 276SYSCTL_INT(_debug, OID_AUTO, PMAP1unchanged, CTLFLAG_RD, 277 &PMAP1unchanged, 0, 278 "Number of times pmap_pte_quick didn't change PMAP1"); 279static struct mtx PMAP2mutex; 280 281static void free_pv_entry(pmap_t pmap, pv_entry_t pv); 282static pv_entry_t get_pv_entry(pmap_t locked_pmap, int try); 283static void pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa); 284static boolean_t pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa); 285static void pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa); 286static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va); 287static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, 288 vm_offset_t va); 289static int pmap_pvh_wired_mappings(struct md_page *pvh, int count); 290 291static boolean_t pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va); 292static boolean_t pmap_enter_pde(pmap_t pmap, vm_offset_t va, vm_page_t m, 293 vm_prot_t prot); 294static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, 295 vm_page_t m, vm_prot_t prot, vm_page_t mpte); 296static void pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte); 297static void pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte); 298static boolean_t pmap_is_modified_pvh(struct md_page *pvh); 299static void pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode); 300static vm_page_t pmap_lookup_pt_page(pmap_t pmap, vm_offset_t va); 301static void pmap_pde_attr(pd_entry_t *pde, int cache_bits); 302static void pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va); 303static boolean_t pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva, 304 vm_prot_t prot); 305static void pmap_pte_attr(pt_entry_t *pte, int cache_bits); 306static void pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva, 307 vm_page_t *free); 308static int pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t sva, 309 vm_page_t *free); 310static void pmap_remove_pt_page(pmap_t pmap, vm_page_t mpte); 311static void pmap_remove_page(struct pmap *pmap, vm_offset_t va, 312 vm_page_t *free); 313static void pmap_remove_entry(struct pmap *pmap, vm_page_t m, 314 vm_offset_t va); 315static void pmap_insert_entry(pmap_t pmap, vm_offset_t va, vm_page_t m); 316static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, 317 vm_page_t m); 318 319static vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va, int flags); 320 321static vm_page_t _pmap_allocpte(pmap_t pmap, unsigned ptepindex, int flags); 322static int _pmap_unwire_pte_hold(pmap_t pmap, vm_page_t m, vm_page_t *free); 323static pt_entry_t *pmap_pte_quick(pmap_t pmap, vm_offset_t va); 324static void pmap_pte_release(pt_entry_t *pte); 325static int pmap_unuse_pt(pmap_t, vm_offset_t, vm_page_t *); 326#ifdef PAE 327static void *pmap_pdpt_allocf(uma_zone_t zone, int bytes, u_int8_t *flags, int wait); 328#endif 329static void pmap_set_pg(void); 330 331CTASSERT(1 << PDESHIFT == sizeof(pd_entry_t)); 332CTASSERT(1 << PTESHIFT == sizeof(pt_entry_t)); 333 334/* 335 * If you get an error here, then you set KVA_PAGES wrong! See the 336 * description of KVA_PAGES in sys/i386/include/pmap.h. It must be 337 * multiple of 4 for a normal kernel, or a multiple of 8 for a PAE. 338 */ 339CTASSERT(KERNBASE % (1 << 24) == 0); 340 341/* 342 * Bootstrap the system enough to run with virtual memory. 343 * 344 * On the i386 this is called after mapping has already been enabled 345 * and just syncs the pmap module with what has already been done. 346 * [We can't call it easily with mapping off since the kernel is not 347 * mapped with PA == VA, hence we would have to relocate every address 348 * from the linked base (virtual) address "KERNBASE" to the actual 349 * (physical) address starting relative to 0] 350 */ 351void 352pmap_bootstrap(vm_paddr_t firstaddr) 353{ 354 vm_offset_t va; 355 pt_entry_t *pte, *unused; 356 struct sysmaps *sysmaps; 357 int i; 358 359 /* 360 * XXX The calculation of virtual_avail is wrong. It's NKPT*PAGE_SIZE too 361 * large. It should instead be correctly calculated in locore.s and 362 * not based on 'first' (which is a physical address, not a virtual 363 * address, for the start of unused physical memory). The kernel 364 * page tables are NOT double mapped and thus should not be included 365 * in this calculation. 366 */ 367 virtual_avail = (vm_offset_t) KERNBASE + firstaddr; 368 369 virtual_end = VM_MAX_KERNEL_ADDRESS; 370 371 /* 372 * Initialize the kernel pmap (which is statically allocated). 373 */ 374 PMAP_LOCK_INIT(kernel_pmap); 375 kernel_pmap->pm_pdir = (pd_entry_t *) (KERNBASE + (u_int)IdlePTD); 376#ifdef PAE 377 kernel_pmap->pm_pdpt = (pdpt_entry_t *) (KERNBASE + (u_int)IdlePDPT); 378#endif 379 kernel_pmap->pm_root = NULL; 380 kernel_pmap->pm_active = -1; /* don't allow deactivation */ 381 TAILQ_INIT(&kernel_pmap->pm_pvchunk); 382 LIST_INIT(&allpmaps); 383 mtx_init(&allpmaps_lock, "allpmaps", NULL, MTX_SPIN); 384 mtx_lock_spin(&allpmaps_lock); 385 LIST_INSERT_HEAD(&allpmaps, kernel_pmap, pm_list); 386 mtx_unlock_spin(&allpmaps_lock); 387 nkpt = NKPT; 388 389 /* 390 * Reserve some special page table entries/VA space for temporary 391 * mapping of pages. 392 */ 393#define SYSMAP(c, p, v, n) \ 394 v = (c)va; va += ((n)*PAGE_SIZE); p = pte; pte += (n); 395 396 va = virtual_avail; 397 pte = vtopte(va); 398 399 /* 400 * CMAP1/CMAP2 are used for zeroing and copying pages. 401 * CMAP3 is used for the idle process page zeroing. 402 */ 403 for (i = 0; i < MAXCPU; i++) { 404 sysmaps = &sysmaps_pcpu[i]; 405 mtx_init(&sysmaps->lock, "SYSMAPS", NULL, MTX_DEF); 406 SYSMAP(caddr_t, sysmaps->CMAP1, sysmaps->CADDR1, 1) 407 SYSMAP(caddr_t, sysmaps->CMAP2, sysmaps->CADDR2, 1) 408 } 409 SYSMAP(caddr_t, CMAP1, CADDR1, 1) 410 SYSMAP(caddr_t, CMAP3, CADDR3, 1) 411 412 /* 413 * Crashdump maps. 414 */ 415 SYSMAP(caddr_t, unused, crashdumpmap, MAXDUMPPGS) 416 417 /* 418 * ptvmmap is used for reading arbitrary physical pages via /dev/mem. 419 */ 420 SYSMAP(caddr_t, unused, ptvmmap, 1) 421 422 /* 423 * msgbufp is used to map the system message buffer. 424 */ 425 SYSMAP(struct msgbuf *, unused, msgbufp, atop(round_page(MSGBUF_SIZE))) 426 427 /* 428 * KPTmap is used by pmap_kextract(). 429 */ 430 SYSMAP(pt_entry_t *, KPTD, KPTmap, KVA_PAGES) 431 432 for (i = 0; i < NKPT; i++) 433 KPTD[i] = (KPTphys + (i << PAGE_SHIFT)) | pgeflag | PG_RW | PG_V; 434 435 /* 436 * Adjust the start of the KPTD and KPTmap so that the implementation 437 * of pmap_kextract() and pmap_growkernel() can be made simpler. 438 */ 439 KPTD -= KPTDI; 440 KPTmap -= i386_btop(KPTDI << PDRSHIFT); 441 442 /* 443 * ptemap is used for pmap_pte_quick 444 */ 445 SYSMAP(pt_entry_t *, PMAP1, PADDR1, 1) 446 SYSMAP(pt_entry_t *, PMAP2, PADDR2, 1) 447 448 mtx_init(&PMAP2mutex, "PMAP2", NULL, MTX_DEF); 449 450 virtual_avail = va; 451 452 /* 453 * Leave in place an identity mapping (virt == phys) for the low 1 MB 454 * physical memory region that is used by the ACPI wakeup code. This 455 * mapping must not have PG_G set. 456 */ 457#ifdef XBOX 458 /* FIXME: This is gross, but needed for the XBOX. Since we are in such 459 * an early stadium, we cannot yet neatly map video memory ... :-( 460 * Better fixes are very welcome! */ 461 if (!arch_i386_is_xbox) 462#endif 463 for (i = 1; i < NKPT; i++) 464 PTD[i] = 0; 465 466 /* Initialize the PAT MSR if present. */ 467 pmap_init_pat(); 468 469 /* Turn on PG_G on kernel page(s) */ 470 pmap_set_pg(); 471} 472 473/* 474 * Setup the PAT MSR. 475 */ 476void 477pmap_init_pat(void) 478{ 479 uint64_t pat_msr; 480 char *sysenv; 481 static int pat_tested = 0; 482 483 /* Bail if this CPU doesn't implement PAT. */ 484 if (!(cpu_feature & CPUID_PAT)) 485 return; 486 487 /* 488 * Due to some Intel errata, we can only safely use the lower 4 489 * PAT entries. 490 * 491 * Intel Pentium III Processor Specification Update 492 * Errata E.27 (Upper Four PAT Entries Not Usable With Mode B 493 * or Mode C Paging) 494 * 495 * Intel Pentium IV Processor Specification Update 496 * Errata N46 (PAT Index MSB May Be Calculated Incorrectly) 497 * 498 * Some Apple Macs based on nVidia chipsets cannot enter ACPI mode 499 * via SMI# when we use upper 4 PAT entries for unknown reason. 500 */ 501 if (!pat_tested) { 502 if (cpu_vendor_id != CPU_VENDOR_INTEL || 503 (CPUID_TO_FAMILY(cpu_id) == 6 && 504 CPUID_TO_MODEL(cpu_id) >= 0xe)) { 505 pat_works = 1; 506 sysenv = getenv("smbios.system.product"); 507 if (sysenv != NULL) { 508 if (strncmp(sysenv, "MacBook5,1", 10) == 0 || 509 strncmp(sysenv, "MacBookPro5,5", 13) == 0 || 510 strncmp(sysenv, "Macmini3,1", 10) == 0) 511 pat_works = 0; 512 freeenv(sysenv); 513 } 514 } 515 pat_tested = 1; 516 } 517 518 /* Initialize default PAT entries. */ 519 pat_msr = PAT_VALUE(0, PAT_WRITE_BACK) | 520 PAT_VALUE(1, PAT_WRITE_THROUGH) | 521 PAT_VALUE(2, PAT_UNCACHED) | 522 PAT_VALUE(3, PAT_UNCACHEABLE) | 523 PAT_VALUE(4, PAT_WRITE_BACK) | 524 PAT_VALUE(5, PAT_WRITE_THROUGH) | 525 PAT_VALUE(6, PAT_UNCACHED) | 526 PAT_VALUE(7, PAT_UNCACHEABLE); 527 528 if (pat_works) { 529 /* 530 * Leave the indices 0-3 at the default of WB, WT, UC-, and UC. 531 * Program 4 and 5 as WP and WC. 532 * Leave 6 and 7 as UC- and UC. 533 */ 534 pat_msr &= ~(PAT_MASK(4) | PAT_MASK(5)); 535 pat_msr |= PAT_VALUE(4, PAT_WRITE_PROTECTED) | 536 PAT_VALUE(5, PAT_WRITE_COMBINING); 537 } else { 538 /* 539 * Just replace PAT Index 2 with WC instead of UC-. 540 */ 541 pat_msr &= ~PAT_MASK(2); 542 pat_msr |= PAT_VALUE(2, PAT_WRITE_COMBINING); 543 } 544 wrmsr(MSR_PAT, pat_msr); 545} 546 547/* 548 * Set PG_G on kernel pages. Only the BSP calls this when SMP is turned on. 549 */ 550static void 551pmap_set_pg(void) 552{ 553 pt_entry_t *pte; 554 vm_offset_t va, endva; 555 556 if (pgeflag == 0) 557 return; 558 559 endva = KERNBASE + KERNend; 560 561 if (pseflag) { 562 va = KERNBASE + KERNLOAD; 563 while (va < endva) { 564 pdir_pde(PTD, va) |= pgeflag; 565 invltlb(); /* Play it safe, invltlb() every time */ 566 va += NBPDR; 567 } 568 } else { 569 va = (vm_offset_t)btext; 570 while (va < endva) { 571 pte = vtopte(va); 572 if (*pte) 573 *pte |= pgeflag; 574 invltlb(); /* Play it safe, invltlb() every time */ 575 va += PAGE_SIZE; 576 } 577 } 578} 579 580/* 581 * Initialize a vm_page's machine-dependent fields. 582 */ 583void 584pmap_page_init(vm_page_t m) 585{ 586 587 TAILQ_INIT(&m->md.pv_list); 588 m->md.pat_mode = PAT_WRITE_BACK; 589} 590 591#ifdef PAE 592static void * 593pmap_pdpt_allocf(uma_zone_t zone, int bytes, u_int8_t *flags, int wait) 594{ 595 596 /* Inform UMA that this allocator uses kernel_map/object. */ 597 *flags = UMA_SLAB_KERNEL; 598 return ((void *)kmem_alloc_contig(kernel_map, bytes, wait, 0x0ULL, 599 0xffffffffULL, 1, 0, VM_MEMATTR_DEFAULT)); 600} 601#endif 602 603/* 604 * ABuse the pte nodes for unmapped kva to thread a kva freelist through. 605 * Requirements: 606 * - Must deal with pages in order to ensure that none of the PG_* bits 607 * are ever set, PG_V in particular. 608 * - Assumes we can write to ptes without pte_store() atomic ops, even 609 * on PAE systems. This should be ok. 610 * - Assumes nothing will ever test these addresses for 0 to indicate 611 * no mapping instead of correctly checking PG_V. 612 * - Assumes a vm_offset_t will fit in a pte (true for i386). 613 * Because PG_V is never set, there can be no mappings to invalidate. 614 */ 615static vm_offset_t 616pmap_ptelist_alloc(vm_offset_t *head) 617{ 618 pt_entry_t *pte; 619 vm_offset_t va; 620 621 va = *head; 622 if (va == 0) 623 return (va); /* Out of memory */ 624 pte = vtopte(va); 625 *head = *pte; 626 if (*head & PG_V) 627 panic("pmap_ptelist_alloc: va with PG_V set!"); 628 *pte = 0; 629 return (va); 630} 631 632static void 633pmap_ptelist_free(vm_offset_t *head, vm_offset_t va) 634{ 635 pt_entry_t *pte; 636 637 if (va & PG_V) 638 panic("pmap_ptelist_free: freeing va with PG_V set!"); 639 pte = vtopte(va); 640 *pte = *head; /* virtual! PG_V is 0 though */ 641 *head = va; 642} 643 644static void 645pmap_ptelist_init(vm_offset_t *head, void *base, int npages) 646{ 647 int i; 648 vm_offset_t va; 649 650 *head = 0; 651 for (i = npages - 1; i >= 0; i--) { 652 va = (vm_offset_t)base + i * PAGE_SIZE; 653 pmap_ptelist_free(head, va); 654 } 655} 656 657 658/* 659 * Initialize the pmap module. 660 * Called by vm_init, to initialize any structures that the pmap 661 * system needs to map virtual memory. 662 */ 663void 664pmap_init(void) 665{ 666 vm_page_t mpte; 667 vm_size_t s; 668 int i, pv_npg; 669 670 /* 671 * Initialize the vm page array entries for the kernel pmap's 672 * page table pages. 673 */ 674 for (i = 0; i < NKPT; i++) { 675 mpte = PHYS_TO_VM_PAGE(KPTphys + (i << PAGE_SHIFT)); 676 KASSERT(mpte >= vm_page_array && 677 mpte < &vm_page_array[vm_page_array_size], 678 ("pmap_init: page table page is out of range")); 679 mpte->pindex = i + KPTDI; 680 mpte->phys_addr = KPTphys + (i << PAGE_SHIFT); 681 } 682 683 /* 684 * Initialize the address space (zone) for the pv entries. Set a 685 * high water mark so that the system can recover from excessive 686 * numbers of pv entries. 687 */ 688 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc); 689 pv_entry_max = shpgperproc * maxproc + cnt.v_page_count; 690 TUNABLE_INT_FETCH("vm.pmap.pv_entries", &pv_entry_max); 691 pv_entry_max = roundup(pv_entry_max, _NPCPV); 692 pv_entry_high_water = 9 * (pv_entry_max / 10); 693 694 /* 695 * Disable large page mappings by default if the kernel is running in 696 * a virtual machine on an AMD Family 10h processor. This is a work- 697 * around for Erratum 383. 698 */ 699 if (vm_guest == VM_GUEST_VM && cpu_vendor_id == CPU_VENDOR_AMD && 700 CPUID_TO_FAMILY(cpu_id) == 0x10) 701 pg_ps_enabled = 0; 702 703 /* 704 * Are large page mappings enabled? 705 */ 706 TUNABLE_INT_FETCH("vm.pmap.pg_ps_enabled", &pg_ps_enabled); 707 if (pg_ps_enabled) { 708 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0, 709 ("pmap_init: can't assign to pagesizes[1]")); 710 pagesizes[1] = NBPDR; 711 } 712 713 /* 714 * Calculate the size of the pv head table for superpages. 715 */ 716 for (i = 0; phys_avail[i + 1]; i += 2); 717 pv_npg = round_4mpage(phys_avail[(i - 2) + 1]) / NBPDR; 718 719 /* 720 * Allocate memory for the pv head table for superpages. 721 */ 722 s = (vm_size_t)(pv_npg * sizeof(struct md_page)); 723 s = round_page(s); 724 pv_table = (struct md_page *)kmem_alloc(kernel_map, s); 725 for (i = 0; i < pv_npg; i++) 726 TAILQ_INIT(&pv_table[i].pv_list); 727 728 pv_maxchunks = MAX(pv_entry_max / _NPCPV, maxproc); 729 pv_chunkbase = (struct pv_chunk *)kmem_alloc_nofault(kernel_map, 730 PAGE_SIZE * pv_maxchunks); 731 if (pv_chunkbase == NULL) 732 panic("pmap_init: not enough kvm for pv chunks"); 733 pmap_ptelist_init(&pv_vafree, pv_chunkbase, pv_maxchunks); 734#ifdef PAE 735 pdptzone = uma_zcreate("PDPT", NPGPTD * sizeof(pdpt_entry_t), NULL, 736 NULL, NULL, NULL, (NPGPTD * sizeof(pdpt_entry_t)) - 1, 737 UMA_ZONE_VM | UMA_ZONE_NOFREE); 738 uma_zone_set_allocf(pdptzone, pmap_pdpt_allocf); 739#endif 740} 741 742 743SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_max, CTLFLAG_RD, &pv_entry_max, 0, 744 "Max number of PV entries"); 745SYSCTL_INT(_vm_pmap, OID_AUTO, shpgperproc, CTLFLAG_RD, &shpgperproc, 0, 746 "Page share factor per proc"); 747 748SYSCTL_NODE(_vm_pmap, OID_AUTO, pde, CTLFLAG_RD, 0, 749 "2/4MB page mapping counters"); 750 751static u_long pmap_pde_demotions; 752SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, demotions, CTLFLAG_RD, 753 &pmap_pde_demotions, 0, "2/4MB page demotions"); 754 755static u_long pmap_pde_mappings; 756SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, mappings, CTLFLAG_RD, 757 &pmap_pde_mappings, 0, "2/4MB page mappings"); 758 759static u_long pmap_pde_p_failures; 760SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, p_failures, CTLFLAG_RD, 761 &pmap_pde_p_failures, 0, "2/4MB page promotion failures"); 762 763static u_long pmap_pde_promotions; 764SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, promotions, CTLFLAG_RD, 765 &pmap_pde_promotions, 0, "2/4MB page promotions"); 766 767/*************************************************** 768 * Low level helper routines..... 769 ***************************************************/ 770 771/* 772 * Determine the appropriate bits to set in a PTE or PDE for a specified 773 * caching mode. 774 */ 775int 776pmap_cache_bits(int mode, boolean_t is_pde) 777{ 778 int pat_flag, pat_index, cache_bits; 779 780 /* The PAT bit is different for PTE's and PDE's. */ 781 pat_flag = is_pde ? PG_PDE_PAT : PG_PTE_PAT; 782 783 /* If we don't support PAT, map extended modes to older ones. */ 784 if (!(cpu_feature & CPUID_PAT)) { 785 switch (mode) { 786 case PAT_UNCACHEABLE: 787 case PAT_WRITE_THROUGH: 788 case PAT_WRITE_BACK: 789 break; 790 case PAT_UNCACHED: 791 case PAT_WRITE_COMBINING: 792 case PAT_WRITE_PROTECTED: 793 mode = PAT_UNCACHEABLE; 794 break; 795 } 796 } 797 798 /* Map the caching mode to a PAT index. */ 799 if (pat_works) { 800 switch (mode) { 801 case PAT_UNCACHEABLE: 802 pat_index = 3; 803 break; 804 case PAT_WRITE_THROUGH: 805 pat_index = 1; 806 break; 807 case PAT_WRITE_BACK: 808 pat_index = 0; 809 break; 810 case PAT_UNCACHED: 811 pat_index = 2; 812 break; 813 case PAT_WRITE_COMBINING: 814 pat_index = 5; 815 break; 816 case PAT_WRITE_PROTECTED: 817 pat_index = 4; 818 break; 819 default: 820 panic("Unknown caching mode %d\n", mode); 821 } 822 } else { 823 switch (mode) { 824 case PAT_UNCACHED: 825 case PAT_UNCACHEABLE: 826 case PAT_WRITE_PROTECTED: 827 pat_index = 3; 828 break; 829 case PAT_WRITE_THROUGH: 830 pat_index = 1; 831 break; 832 case PAT_WRITE_BACK: 833 pat_index = 0; 834 break; 835 case PAT_WRITE_COMBINING: 836 pat_index = 2; 837 break; 838 default: 839 panic("Unknown caching mode %d\n", mode); 840 } 841 } 842 843 /* Map the 3-bit index value into the PAT, PCD, and PWT bits. */ 844 cache_bits = 0; 845 if (pat_index & 0x4) 846 cache_bits |= pat_flag; 847 if (pat_index & 0x2) 848 cache_bits |= PG_NC_PCD; 849 if (pat_index & 0x1) 850 cache_bits |= PG_NC_PWT; 851 return (cache_bits); 852} 853#ifdef SMP 854/* 855 * For SMP, these functions have to use the IPI mechanism for coherence. 856 * 857 * N.B.: Before calling any of the following TLB invalidation functions, 858 * the calling processor must ensure that all stores updating a non- 859 * kernel page table are globally performed. Otherwise, another 860 * processor could cache an old, pre-update entry without being 861 * invalidated. This can happen one of two ways: (1) The pmap becomes 862 * active on another processor after its pm_active field is checked by 863 * one of the following functions but before a store updating the page 864 * table is globally performed. (2) The pmap becomes active on another 865 * processor before its pm_active field is checked but due to 866 * speculative loads one of the following functions stills reads the 867 * pmap as inactive on the other processor. 868 * 869 * The kernel page table is exempt because its pm_active field is 870 * immutable. The kernel page table is always active on every 871 * processor. 872 */ 873void 874pmap_invalidate_page(pmap_t pmap, vm_offset_t va) 875{ 876 u_int cpumask; 877 u_int other_cpus; 878 879 sched_pin(); 880 if (pmap == kernel_pmap || pmap->pm_active == all_cpus) { 881 invlpg(va); 882 smp_invlpg(va); 883 } else { 884 cpumask = PCPU_GET(cpumask); 885 other_cpus = PCPU_GET(other_cpus); 886 if (pmap->pm_active & cpumask) 887 invlpg(va); 888 if (pmap->pm_active & other_cpus) 889 smp_masked_invlpg(pmap->pm_active & other_cpus, va); 890 } 891 sched_unpin(); 892} 893 894void 895pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 896{ 897 u_int cpumask; 898 u_int other_cpus; 899 vm_offset_t addr; 900 901 sched_pin(); 902 if (pmap == kernel_pmap || pmap->pm_active == all_cpus) { 903 for (addr = sva; addr < eva; addr += PAGE_SIZE) 904 invlpg(addr); 905 smp_invlpg_range(sva, eva); 906 } else { 907 cpumask = PCPU_GET(cpumask); 908 other_cpus = PCPU_GET(other_cpus); 909 if (pmap->pm_active & cpumask) 910 for (addr = sva; addr < eva; addr += PAGE_SIZE) 911 invlpg(addr); 912 if (pmap->pm_active & other_cpus) 913 smp_masked_invlpg_range(pmap->pm_active & other_cpus, 914 sva, eva); 915 } 916 sched_unpin(); 917} 918 919void 920pmap_invalidate_all(pmap_t pmap) 921{ 922 u_int cpumask; 923 u_int other_cpus; 924 925 sched_pin(); 926 if (pmap == kernel_pmap || pmap->pm_active == all_cpus) { 927 invltlb(); 928 smp_invltlb(); 929 } else { 930 cpumask = PCPU_GET(cpumask); 931 other_cpus = PCPU_GET(other_cpus); 932 if (pmap->pm_active & cpumask) 933 invltlb(); 934 if (pmap->pm_active & other_cpus) 935 smp_masked_invltlb(pmap->pm_active & other_cpus); 936 } 937 sched_unpin(); 938} 939 940void 941pmap_invalidate_cache(void) 942{ 943 944 sched_pin(); 945 wbinvd(); 946 smp_cache_flush(); 947 sched_unpin(); 948} 949#else /* !SMP */ 950/* 951 * Normal, non-SMP, 486+ invalidation functions. 952 * We inline these within pmap.c for speed. 953 */ 954PMAP_INLINE void 955pmap_invalidate_page(pmap_t pmap, vm_offset_t va) 956{ 957 958 if (pmap == kernel_pmap || pmap->pm_active) 959 invlpg(va); 960} 961 962PMAP_INLINE void 963pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 964{ 965 vm_offset_t addr; 966 967 if (pmap == kernel_pmap || pmap->pm_active) 968 for (addr = sva; addr < eva; addr += PAGE_SIZE) 969 invlpg(addr); 970} 971 972PMAP_INLINE void 973pmap_invalidate_all(pmap_t pmap) 974{ 975 976 if (pmap == kernel_pmap || pmap->pm_active) 977 invltlb(); 978} 979 980PMAP_INLINE void 981pmap_invalidate_cache(void) 982{ 983 984 wbinvd(); 985} 986#endif /* !SMP */ 987 988void 989pmap_invalidate_cache_range(vm_offset_t sva, vm_offset_t eva) 990{ 991 992 KASSERT((sva & PAGE_MASK) == 0, 993 ("pmap_invalidate_cache_range: sva not page-aligned")); 994 KASSERT((eva & PAGE_MASK) == 0, 995 ("pmap_invalidate_cache_range: eva not page-aligned")); 996 997 if (cpu_feature & CPUID_SS) 998 ; /* If "Self Snoop" is supported, do nothing. */ 999 else if ((cpu_feature & CPUID_CLFSH) != 0 && 1000 eva - sva < 2 * 1024 * 1024) { 1001 1002 /* 1003 * Otherwise, do per-cache line flush. Use the mfence 1004 * instruction to insure that previous stores are 1005 * included in the write-back. The processor 1006 * propagates flush to other processors in the cache 1007 * coherence domain. 1008 */ 1009 mfence(); 1010 for (; sva < eva; sva += cpu_clflush_line_size) 1011 clflush(sva); 1012 mfence(); 1013 } else { 1014 1015 /* 1016 * No targeted cache flush methods are supported by CPU, 1017 * or the supplied range is bigger then 2MB. 1018 * Globally invalidate cache. 1019 */ 1020 pmap_invalidate_cache(); 1021 } 1022} 1023 1024/* 1025 * Are we current address space or kernel? N.B. We return FALSE when 1026 * a pmap's page table is in use because a kernel thread is borrowing 1027 * it. The borrowed page table can change spontaneously, making any 1028 * dependence on its continued use subject to a race condition. 1029 */ 1030static __inline int 1031pmap_is_current(pmap_t pmap) 1032{ 1033 1034 return (pmap == kernel_pmap || 1035 (pmap == vmspace_pmap(curthread->td_proc->p_vmspace) && 1036 (pmap->pm_pdir[PTDPTDI] & PG_FRAME) == (PTDpde[0] & PG_FRAME))); 1037} 1038 1039/* 1040 * If the given pmap is not the current or kernel pmap, the returned pte must 1041 * be released by passing it to pmap_pte_release(). 1042 */ 1043pt_entry_t * 1044pmap_pte(pmap_t pmap, vm_offset_t va) 1045{ 1046 pd_entry_t newpf; 1047 pd_entry_t *pde; 1048 1049 pde = pmap_pde(pmap, va); 1050 if (*pde & PG_PS) 1051 return (pde); 1052 if (*pde != 0) { 1053 /* are we current address space or kernel? */ 1054 if (pmap_is_current(pmap)) 1055 return (vtopte(va)); 1056 mtx_lock(&PMAP2mutex); 1057 newpf = *pde & PG_FRAME; 1058 if ((*PMAP2 & PG_FRAME) != newpf) { 1059 *PMAP2 = newpf | PG_RW | PG_V | PG_A | PG_M; 1060 pmap_invalidate_page(kernel_pmap, (vm_offset_t)PADDR2); 1061 } 1062 return (PADDR2 + (i386_btop(va) & (NPTEPG - 1))); 1063 } 1064 return (0); 1065} 1066 1067/* 1068 * Releases a pte that was obtained from pmap_pte(). Be prepared for the pte 1069 * being NULL. 1070 */ 1071static __inline void 1072pmap_pte_release(pt_entry_t *pte) 1073{ 1074 1075 if ((pt_entry_t *)((vm_offset_t)pte & ~PAGE_MASK) == PADDR2) 1076 mtx_unlock(&PMAP2mutex); 1077} 1078 1079static __inline void 1080invlcaddr(void *caddr) 1081{ 1082 1083 invlpg((u_int)caddr); 1084} 1085 1086/* 1087 * Super fast pmap_pte routine best used when scanning 1088 * the pv lists. This eliminates many coarse-grained 1089 * invltlb calls. Note that many of the pv list 1090 * scans are across different pmaps. It is very wasteful 1091 * to do an entire invltlb for checking a single mapping. 1092 * 1093 * If the given pmap is not the current pmap, vm_page_queue_mtx 1094 * must be held and curthread pinned to a CPU. 1095 */ 1096static pt_entry_t * 1097pmap_pte_quick(pmap_t pmap, vm_offset_t va) 1098{ 1099 pd_entry_t newpf; 1100 pd_entry_t *pde; 1101 1102 pde = pmap_pde(pmap, va); 1103 if (*pde & PG_PS) 1104 return (pde); 1105 if (*pde != 0) { 1106 /* are we current address space or kernel? */ 1107 if (pmap_is_current(pmap)) 1108 return (vtopte(va)); 1109 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1110 KASSERT(curthread->td_pinned > 0, ("curthread not pinned")); 1111 newpf = *pde & PG_FRAME; 1112 if ((*PMAP1 & PG_FRAME) != newpf) { 1113 *PMAP1 = newpf | PG_RW | PG_V | PG_A | PG_M; 1114#ifdef SMP 1115 PMAP1cpu = PCPU_GET(cpuid); 1116#endif 1117 invlcaddr(PADDR1); 1118 PMAP1changed++; 1119 } else 1120#ifdef SMP 1121 if (PMAP1cpu != PCPU_GET(cpuid)) { 1122 PMAP1cpu = PCPU_GET(cpuid); 1123 invlcaddr(PADDR1); 1124 PMAP1changedcpu++; 1125 } else 1126#endif 1127 PMAP1unchanged++; 1128 return (PADDR1 + (i386_btop(va) & (NPTEPG - 1))); 1129 } 1130 return (0); 1131} 1132 1133/* 1134 * Routine: pmap_extract 1135 * Function: 1136 * Extract the physical page address associated 1137 * with the given map/virtual_address pair. 1138 */ 1139vm_paddr_t 1140pmap_extract(pmap_t pmap, vm_offset_t va) 1141{ 1142 vm_paddr_t rtval; 1143 pt_entry_t *pte; 1144 pd_entry_t pde; 1145 1146 rtval = 0; 1147 PMAP_LOCK(pmap); 1148 pde = pmap->pm_pdir[va >> PDRSHIFT]; 1149 if (pde != 0) { 1150 if ((pde & PG_PS) != 0) 1151 rtval = (pde & PG_PS_FRAME) | (va & PDRMASK); 1152 else { 1153 pte = pmap_pte(pmap, va); 1154 rtval = (*pte & PG_FRAME) | (va & PAGE_MASK); 1155 pmap_pte_release(pte); 1156 } 1157 } 1158 PMAP_UNLOCK(pmap); 1159 return (rtval); 1160} 1161 1162/* 1163 * Routine: pmap_extract_and_hold 1164 * Function: 1165 * Atomically extract and hold the physical page 1166 * with the given pmap and virtual address pair 1167 * if that mapping permits the given protection. 1168 */ 1169vm_page_t 1170pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot) 1171{ 1172 pd_entry_t pde; 1173 pt_entry_t pte; 1174 vm_page_t m; 1175 1176 m = NULL; 1177 vm_page_lock_queues(); 1178 PMAP_LOCK(pmap); 1179 pde = *pmap_pde(pmap, va); 1180 if (pde != 0) { 1181 if (pde & PG_PS) { 1182 if ((pde & PG_RW) || (prot & VM_PROT_WRITE) == 0) { 1183 m = PHYS_TO_VM_PAGE((pde & PG_PS_FRAME) | 1184 (va & PDRMASK)); 1185 vm_page_hold(m); 1186 } 1187 } else { 1188 sched_pin(); 1189 pte = *pmap_pte_quick(pmap, va); 1190 if (pte != 0 && 1191 ((pte & PG_RW) || (prot & VM_PROT_WRITE) == 0)) { 1192 m = PHYS_TO_VM_PAGE(pte & PG_FRAME); 1193 vm_page_hold(m); 1194 } 1195 sched_unpin(); 1196 } 1197 } 1198 vm_page_unlock_queues(); 1199 PMAP_UNLOCK(pmap); 1200 return (m); 1201} 1202 1203/*************************************************** 1204 * Low level mapping routines..... 1205 ***************************************************/ 1206 1207/* 1208 * Add a wired page to the kva. 1209 * Note: not SMP coherent. 1210 */ 1211PMAP_INLINE void 1212pmap_kenter(vm_offset_t va, vm_paddr_t pa) 1213{ 1214 pt_entry_t *pte; 1215 1216 pte = vtopte(va); 1217 pte_store(pte, pa | PG_RW | PG_V | pgeflag); 1218} 1219 1220static __inline void 1221pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode) 1222{ 1223 pt_entry_t *pte; 1224 1225 pte = vtopte(va); 1226 pte_store(pte, pa | PG_RW | PG_V | pgeflag | pmap_cache_bits(mode, 0)); 1227} 1228 1229/* 1230 * Remove a page from the kernel pagetables. 1231 * Note: not SMP coherent. 1232 */ 1233PMAP_INLINE void 1234pmap_kremove(vm_offset_t va) 1235{ 1236 pt_entry_t *pte; 1237 1238 pte = vtopte(va); 1239 pte_clear(pte); 1240} 1241 1242/* 1243 * Used to map a range of physical addresses into kernel 1244 * virtual address space. 1245 * 1246 * The value passed in '*virt' is a suggested virtual address for 1247 * the mapping. Architectures which can support a direct-mapped 1248 * physical to virtual region can return the appropriate address 1249 * within that region, leaving '*virt' unchanged. Other 1250 * architectures should map the pages starting at '*virt' and 1251 * update '*virt' with the first usable address after the mapped 1252 * region. 1253 */ 1254vm_offset_t 1255pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot) 1256{ 1257 vm_offset_t va, sva; 1258 1259 va = sva = *virt; 1260 while (start < end) { 1261 pmap_kenter(va, start); 1262 va += PAGE_SIZE; 1263 start += PAGE_SIZE; 1264 } 1265 pmap_invalidate_range(kernel_pmap, sva, va); 1266 *virt = va; 1267 return (sva); 1268} 1269 1270 1271/* 1272 * Add a list of wired pages to the kva 1273 * this routine is only used for temporary 1274 * kernel mappings that do not need to have 1275 * page modification or references recorded. 1276 * Note that old mappings are simply written 1277 * over. The page *must* be wired. 1278 * Note: SMP coherent. Uses a ranged shootdown IPI. 1279 */ 1280void 1281pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count) 1282{ 1283 pt_entry_t *endpte, oldpte, *pte; 1284 1285 oldpte = 0; 1286 pte = vtopte(sva); 1287 endpte = pte + count; 1288 while (pte < endpte) { 1289 oldpte |= *pte; 1290 pte_store(pte, VM_PAGE_TO_PHYS(*ma) | pgeflag | 1291 pmap_cache_bits((*ma)->md.pat_mode, 0) | PG_RW | PG_V); 1292 pte++; 1293 ma++; 1294 } 1295 if ((oldpte & PG_V) != 0) 1296 pmap_invalidate_range(kernel_pmap, sva, sva + count * 1297 PAGE_SIZE); 1298} 1299 1300/* 1301 * This routine tears out page mappings from the 1302 * kernel -- it is meant only for temporary mappings. 1303 * Note: SMP coherent. Uses a ranged shootdown IPI. 1304 */ 1305void 1306pmap_qremove(vm_offset_t sva, int count) 1307{ 1308 vm_offset_t va; 1309 1310 va = sva; 1311 while (count-- > 0) { 1312 pmap_kremove(va); 1313 va += PAGE_SIZE; 1314 } 1315 pmap_invalidate_range(kernel_pmap, sva, va); 1316} 1317 1318/*************************************************** 1319 * Page table page management routines..... 1320 ***************************************************/ 1321static __inline void 1322pmap_free_zero_pages(vm_page_t free) 1323{ 1324 vm_page_t m; 1325 1326 while (free != NULL) { 1327 m = free; 1328 free = m->right; 1329 /* Preserve the page's PG_ZERO setting. */ 1330 vm_page_free_toq(m); 1331 } 1332} 1333 1334/* 1335 * Schedule the specified unused page table page to be freed. Specifically, 1336 * add the page to the specified list of pages that will be released to the 1337 * physical memory manager after the TLB has been updated. 1338 */ 1339static __inline void 1340pmap_add_delayed_free_list(vm_page_t m, vm_page_t *free, boolean_t set_PG_ZERO) 1341{ 1342 1343 if (set_PG_ZERO) 1344 m->flags |= PG_ZERO; 1345 else 1346 m->flags &= ~PG_ZERO; 1347 m->right = *free; 1348 *free = m; 1349} 1350 1351/* 1352 * Inserts the specified page table page into the specified pmap's collection 1353 * of idle page table pages. Each of a pmap's page table pages is responsible 1354 * for mapping a distinct range of virtual addresses. The pmap's collection is 1355 * ordered by this virtual address range. 1356 */ 1357static void 1358pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte) 1359{ 1360 vm_page_t root; 1361 1362 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1363 root = pmap->pm_root; 1364 if (root == NULL) { 1365 mpte->left = NULL; 1366 mpte->right = NULL; 1367 } else { 1368 root = vm_page_splay(mpte->pindex, root); 1369 if (mpte->pindex < root->pindex) { 1370 mpte->left = root->left; 1371 mpte->right = root; 1372 root->left = NULL; 1373 } else if (mpte->pindex == root->pindex) 1374 panic("pmap_insert_pt_page: pindex already inserted"); 1375 else { 1376 mpte->right = root->right; 1377 mpte->left = root; 1378 root->right = NULL; 1379 } 1380 } 1381 pmap->pm_root = mpte; 1382} 1383 1384/* 1385 * Looks for a page table page mapping the specified virtual address in the 1386 * specified pmap's collection of idle page table pages. Returns NULL if there 1387 * is no page table page corresponding to the specified virtual address. 1388 */ 1389static vm_page_t 1390pmap_lookup_pt_page(pmap_t pmap, vm_offset_t va) 1391{ 1392 vm_page_t mpte; 1393 vm_pindex_t pindex = va >> PDRSHIFT; 1394 1395 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1396 if ((mpte = pmap->pm_root) != NULL && mpte->pindex != pindex) { 1397 mpte = vm_page_splay(pindex, mpte); 1398 if ((pmap->pm_root = mpte)->pindex != pindex) 1399 mpte = NULL; 1400 } 1401 return (mpte); 1402} 1403 1404/* 1405 * Removes the specified page table page from the specified pmap's collection 1406 * of idle page table pages. The specified page table page must be a member of 1407 * the pmap's collection. 1408 */ 1409static void 1410pmap_remove_pt_page(pmap_t pmap, vm_page_t mpte) 1411{ 1412 vm_page_t root; 1413 1414 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1415 if (mpte != pmap->pm_root) 1416 vm_page_splay(mpte->pindex, pmap->pm_root); 1417 if (mpte->left == NULL) 1418 root = mpte->right; 1419 else { 1420 root = vm_page_splay(mpte->pindex, mpte->left); 1421 root->right = mpte->right; 1422 } 1423 pmap->pm_root = root; 1424} 1425 1426/* 1427 * This routine unholds page table pages, and if the hold count 1428 * drops to zero, then it decrements the wire count. 1429 */ 1430static __inline int 1431pmap_unwire_pte_hold(pmap_t pmap, vm_page_t m, vm_page_t *free) 1432{ 1433 1434 --m->wire_count; 1435 if (m->wire_count == 0) 1436 return _pmap_unwire_pte_hold(pmap, m, free); 1437 else 1438 return 0; 1439} 1440 1441static int 1442_pmap_unwire_pte_hold(pmap_t pmap, vm_page_t m, vm_page_t *free) 1443{ 1444 vm_offset_t pteva; 1445 1446 /* 1447 * unmap the page table page 1448 */ 1449 pmap->pm_pdir[m->pindex] = 0; 1450 --pmap->pm_stats.resident_count; 1451 1452 /* 1453 * This is a release store so that the ordinary store unmapping 1454 * the page table page is globally performed before TLB shoot- 1455 * down is begun. 1456 */ 1457 atomic_subtract_rel_int(&cnt.v_wire_count, 1); 1458 1459 /* 1460 * Do an invltlb to make the invalidated mapping 1461 * take effect immediately. 1462 */ 1463 pteva = VM_MAXUSER_ADDRESS + i386_ptob(m->pindex); 1464 pmap_invalidate_page(pmap, pteva); 1465 1466 /* 1467 * Put page on a list so that it is released after 1468 * *ALL* TLB shootdown is done 1469 */ 1470 pmap_add_delayed_free_list(m, free, TRUE); 1471 1472 return 1; 1473} 1474 1475/* 1476 * After removing a page table entry, this routine is used to 1477 * conditionally free the page, and manage the hold/wire counts. 1478 */ 1479static int 1480pmap_unuse_pt(pmap_t pmap, vm_offset_t va, vm_page_t *free) 1481{ 1482 pd_entry_t ptepde; 1483 vm_page_t mpte; 1484 1485 if (va >= VM_MAXUSER_ADDRESS) 1486 return 0; 1487 ptepde = *pmap_pde(pmap, va); 1488 mpte = PHYS_TO_VM_PAGE(ptepde & PG_FRAME); 1489 return pmap_unwire_pte_hold(pmap, mpte, free); 1490} 1491 1492void 1493pmap_pinit0(pmap_t pmap) 1494{ 1495 1496 PMAP_LOCK_INIT(pmap); 1497 pmap->pm_pdir = (pd_entry_t *)(KERNBASE + (vm_offset_t)IdlePTD); 1498#ifdef PAE 1499 pmap->pm_pdpt = (pdpt_entry_t *)(KERNBASE + (vm_offset_t)IdlePDPT); 1500#endif 1501 pmap->pm_root = NULL; 1502 pmap->pm_active = 0; 1503 PCPU_SET(curpmap, pmap); 1504 TAILQ_INIT(&pmap->pm_pvchunk); 1505 bzero(&pmap->pm_stats, sizeof pmap->pm_stats); 1506 mtx_lock_spin(&allpmaps_lock); 1507 LIST_INSERT_HEAD(&allpmaps, pmap, pm_list); 1508 mtx_unlock_spin(&allpmaps_lock); 1509} 1510 1511/* 1512 * Initialize a preallocated and zeroed pmap structure, 1513 * such as one in a vmspace structure. 1514 */ 1515int 1516pmap_pinit(pmap_t pmap) 1517{ 1518 vm_page_t m, ptdpg[NPGPTD]; 1519 vm_paddr_t pa; 1520 static int color; 1521 int i; 1522 1523 PMAP_LOCK_INIT(pmap); 1524 1525 /* 1526 * No need to allocate page table space yet but we do need a valid 1527 * page directory table. 1528 */ 1529 if (pmap->pm_pdir == NULL) { 1530 pmap->pm_pdir = (pd_entry_t *)kmem_alloc_nofault(kernel_map, 1531 NBPTD); 1532 1533 if (pmap->pm_pdir == NULL) { 1534 PMAP_LOCK_DESTROY(pmap); 1535 return (0); 1536 } 1537#ifdef PAE 1538 pmap->pm_pdpt = uma_zalloc(pdptzone, M_WAITOK | M_ZERO); 1539 KASSERT(((vm_offset_t)pmap->pm_pdpt & 1540 ((NPGPTD * sizeof(pdpt_entry_t)) - 1)) == 0, 1541 ("pmap_pinit: pdpt misaligned")); 1542 KASSERT(pmap_kextract((vm_offset_t)pmap->pm_pdpt) < (4ULL<<30), 1543 ("pmap_pinit: pdpt above 4g")); 1544#endif 1545 pmap->pm_root = NULL; 1546 } 1547 KASSERT(pmap->pm_root == NULL, 1548 ("pmap_pinit: pmap has reserved page table page(s)")); 1549 1550 /* 1551 * allocate the page directory page(s) 1552 */ 1553 for (i = 0; i < NPGPTD;) { 1554 m = vm_page_alloc(NULL, color++, 1555 VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | 1556 VM_ALLOC_ZERO); 1557 if (m == NULL) 1558 VM_WAIT; 1559 else { 1560 ptdpg[i++] = m; 1561 } 1562 } 1563 1564 pmap_qenter((vm_offset_t)pmap->pm_pdir, ptdpg, NPGPTD); 1565 1566 for (i = 0; i < NPGPTD; i++) { 1567 if ((ptdpg[i]->flags & PG_ZERO) == 0) 1568 bzero(pmap->pm_pdir + (i * NPDEPG), PAGE_SIZE); 1569 } 1570 1571 mtx_lock_spin(&allpmaps_lock); 1572 LIST_INSERT_HEAD(&allpmaps, pmap, pm_list); 1573 mtx_unlock_spin(&allpmaps_lock); 1574 /* Wire in kernel global address entries. */ 1575 bcopy(PTD + KPTDI, pmap->pm_pdir + KPTDI, nkpt * sizeof(pd_entry_t)); 1576 1577 /* install self-referential address mapping entry(s) */ 1578 for (i = 0; i < NPGPTD; i++) { 1579 pa = VM_PAGE_TO_PHYS(ptdpg[i]); 1580 pmap->pm_pdir[PTDPTDI + i] = pa | PG_V | PG_RW | PG_A | PG_M; 1581#ifdef PAE 1582 pmap->pm_pdpt[i] = pa | PG_V; 1583#endif 1584 } 1585 1586 pmap->pm_active = 0; 1587 TAILQ_INIT(&pmap->pm_pvchunk); 1588 bzero(&pmap->pm_stats, sizeof pmap->pm_stats); 1589 1590 return (1); 1591} 1592 1593/* 1594 * this routine is called if the page table page is not 1595 * mapped correctly. 1596 */ 1597static vm_page_t 1598_pmap_allocpte(pmap_t pmap, unsigned ptepindex, int flags) 1599{ 1600 vm_paddr_t ptepa; 1601 vm_page_t m; 1602 1603 KASSERT((flags & (M_NOWAIT | M_WAITOK)) == M_NOWAIT || 1604 (flags & (M_NOWAIT | M_WAITOK)) == M_WAITOK, 1605 ("_pmap_allocpte: flags is neither M_NOWAIT nor M_WAITOK")); 1606 1607 /* 1608 * Allocate a page table page. 1609 */ 1610 if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ | 1611 VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) { 1612 if (flags & M_WAITOK) { 1613 PMAP_UNLOCK(pmap); 1614 vm_page_unlock_queues(); 1615 VM_WAIT; 1616 vm_page_lock_queues(); 1617 PMAP_LOCK(pmap); 1618 } 1619 1620 /* 1621 * Indicate the need to retry. While waiting, the page table 1622 * page may have been allocated. 1623 */ 1624 return (NULL); 1625 } 1626 if ((m->flags & PG_ZERO) == 0) 1627 pmap_zero_page(m); 1628 1629 /* 1630 * Map the pagetable page into the process address space, if 1631 * it isn't already there. 1632 */ 1633 1634 pmap->pm_stats.resident_count++; 1635 1636 ptepa = VM_PAGE_TO_PHYS(m); 1637 pmap->pm_pdir[ptepindex] = 1638 (pd_entry_t) (ptepa | PG_U | PG_RW | PG_V | PG_A | PG_M); 1639 1640 return m; 1641} 1642 1643static vm_page_t 1644pmap_allocpte(pmap_t pmap, vm_offset_t va, int flags) 1645{ 1646 unsigned ptepindex; 1647 pd_entry_t ptepa; 1648 vm_page_t m; 1649 1650 KASSERT((flags & (M_NOWAIT | M_WAITOK)) == M_NOWAIT || 1651 (flags & (M_NOWAIT | M_WAITOK)) == M_WAITOK, 1652 ("pmap_allocpte: flags is neither M_NOWAIT nor M_WAITOK")); 1653 1654 /* 1655 * Calculate pagetable page index 1656 */ 1657 ptepindex = va >> PDRSHIFT; 1658retry: 1659 /* 1660 * Get the page directory entry 1661 */ 1662 ptepa = pmap->pm_pdir[ptepindex]; 1663 1664 /* 1665 * This supports switching from a 4MB page to a 1666 * normal 4K page. 1667 */ 1668 if (ptepa & PG_PS) { 1669 (void)pmap_demote_pde(pmap, &pmap->pm_pdir[ptepindex], va); 1670 ptepa = pmap->pm_pdir[ptepindex]; 1671 } 1672 1673 /* 1674 * If the page table page is mapped, we just increment the 1675 * hold count, and activate it. 1676 */ 1677 if (ptepa) { 1678 m = PHYS_TO_VM_PAGE(ptepa & PG_FRAME); 1679 m->wire_count++; 1680 } else { 1681 /* 1682 * Here if the pte page isn't mapped, or if it has 1683 * been deallocated. 1684 */ 1685 m = _pmap_allocpte(pmap, ptepindex, flags); 1686 if (m == NULL && (flags & M_WAITOK)) 1687 goto retry; 1688 } 1689 return (m); 1690} 1691 1692 1693/*************************************************** 1694* Pmap allocation/deallocation routines. 1695 ***************************************************/ 1696 1697#ifdef SMP 1698/* 1699 * Deal with a SMP shootdown of other users of the pmap that we are 1700 * trying to dispose of. This can be a bit hairy. 1701 */ 1702static cpumask_t *lazymask; 1703static u_int lazyptd; 1704static volatile u_int lazywait; 1705 1706void pmap_lazyfix_action(void); 1707 1708void 1709pmap_lazyfix_action(void) 1710{ 1711 cpumask_t mymask = PCPU_GET(cpumask); 1712 1713#ifdef COUNT_IPIS 1714 (*ipi_lazypmap_counts[PCPU_GET(cpuid)])++; 1715#endif 1716 if (rcr3() == lazyptd) 1717 load_cr3(PCPU_GET(curpcb)->pcb_cr3); 1718 atomic_clear_int(lazymask, mymask); 1719 atomic_store_rel_int(&lazywait, 1); 1720} 1721 1722static void 1723pmap_lazyfix_self(cpumask_t mymask) 1724{ 1725 1726 if (rcr3() == lazyptd) 1727 load_cr3(PCPU_GET(curpcb)->pcb_cr3); 1728 atomic_clear_int(lazymask, mymask); 1729} 1730 1731 1732static void 1733pmap_lazyfix(pmap_t pmap) 1734{ 1735 cpumask_t mymask, mask; 1736 u_int spins; 1737 1738 while ((mask = pmap->pm_active) != 0) { 1739 spins = 50000000; 1740 mask = mask & -mask; /* Find least significant set bit */ 1741 mtx_lock_spin(&smp_ipi_mtx); 1742#ifdef PAE 1743 lazyptd = vtophys(pmap->pm_pdpt); 1744#else 1745 lazyptd = vtophys(pmap->pm_pdir); 1746#endif 1747 mymask = PCPU_GET(cpumask); 1748 if (mask == mymask) { 1749 lazymask = &pmap->pm_active; 1750 pmap_lazyfix_self(mymask); 1751 } else { 1752 atomic_store_rel_int((u_int *)&lazymask, 1753 (u_int)&pmap->pm_active); 1754 atomic_store_rel_int(&lazywait, 0); 1755 ipi_selected(mask, IPI_LAZYPMAP); 1756 while (lazywait == 0) { 1757 ia32_pause(); 1758 if (--spins == 0) 1759 break; 1760 } 1761 } 1762 mtx_unlock_spin(&smp_ipi_mtx); 1763 if (spins == 0) 1764 printf("pmap_lazyfix: spun for 50000000\n"); 1765 } 1766} 1767 1768#else /* SMP */ 1769 1770/* 1771 * Cleaning up on uniprocessor is easy. For various reasons, we're 1772 * unlikely to have to even execute this code, including the fact 1773 * that the cleanup is deferred until the parent does a wait(2), which 1774 * means that another userland process has run. 1775 */ 1776static void 1777pmap_lazyfix(pmap_t pmap) 1778{ 1779 u_int cr3; 1780 1781 cr3 = vtophys(pmap->pm_pdir); 1782 if (cr3 == rcr3()) { 1783 load_cr3(PCPU_GET(curpcb)->pcb_cr3); 1784 pmap->pm_active &= ~(PCPU_GET(cpumask)); 1785 } 1786} 1787#endif /* SMP */ 1788 1789/* 1790 * Release any resources held by the given physical map. 1791 * Called when a pmap initialized by pmap_pinit is being released. 1792 * Should only be called if the map contains no valid mappings. 1793 */ 1794void 1795pmap_release(pmap_t pmap) 1796{ 1797 vm_page_t m, ptdpg[NPGPTD]; 1798 int i; 1799 1800 KASSERT(pmap->pm_stats.resident_count == 0, 1801 ("pmap_release: pmap resident count %ld != 0", 1802 pmap->pm_stats.resident_count)); 1803 KASSERT(pmap->pm_root == NULL, 1804 ("pmap_release: pmap has reserved page table page(s)")); 1805 1806 pmap_lazyfix(pmap); 1807 mtx_lock_spin(&allpmaps_lock); 1808 LIST_REMOVE(pmap, pm_list); 1809 mtx_unlock_spin(&allpmaps_lock); 1810 1811 for (i = 0; i < NPGPTD; i++) 1812 ptdpg[i] = PHYS_TO_VM_PAGE(pmap->pm_pdir[PTDPTDI + i] & 1813 PG_FRAME); 1814 1815 bzero(pmap->pm_pdir + PTDPTDI, (nkpt + NPGPTD) * 1816 sizeof(*pmap->pm_pdir)); 1817 1818 pmap_qremove((vm_offset_t)pmap->pm_pdir, NPGPTD); 1819 1820 for (i = 0; i < NPGPTD; i++) { 1821 m = ptdpg[i]; 1822#ifdef PAE 1823 KASSERT(VM_PAGE_TO_PHYS(m) == (pmap->pm_pdpt[i] & PG_FRAME), 1824 ("pmap_release: got wrong ptd page")); 1825#endif 1826 m->wire_count--; 1827 atomic_subtract_int(&cnt.v_wire_count, 1); 1828 vm_page_free_zero(m); 1829 } 1830 PMAP_LOCK_DESTROY(pmap); 1831} 1832 1833static int 1834kvm_size(SYSCTL_HANDLER_ARGS) 1835{ 1836 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - KERNBASE; 1837 1838 return sysctl_handle_long(oidp, &ksize, 0, req); 1839} 1840SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG|CTLFLAG_RD, 1841 0, 0, kvm_size, "IU", "Size of KVM"); 1842 1843static int 1844kvm_free(SYSCTL_HANDLER_ARGS) 1845{ 1846 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end; 1847 1848 return sysctl_handle_long(oidp, &kfree, 0, req); 1849} 1850SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG|CTLFLAG_RD, 1851 0, 0, kvm_free, "IU", "Amount of KVM free"); 1852 1853/* 1854 * grow the number of kernel page table entries, if needed 1855 */ 1856void 1857pmap_growkernel(vm_offset_t addr) 1858{ 1859 struct pmap *pmap; 1860 vm_paddr_t ptppaddr; 1861 vm_page_t nkpg; 1862 pd_entry_t newpdir; 1863 pt_entry_t *pde; 1864 boolean_t updated_PTD; 1865 1866 mtx_assert(&kernel_map->system_mtx, MA_OWNED); 1867 if (kernel_vm_end == 0) { 1868 kernel_vm_end = KERNBASE; 1869 nkpt = 0; 1870 while (pdir_pde(PTD, kernel_vm_end)) { 1871 kernel_vm_end = (kernel_vm_end + PAGE_SIZE * NPTEPG) & ~(PAGE_SIZE * NPTEPG - 1); 1872 nkpt++; 1873 if (kernel_vm_end - 1 >= kernel_map->max_offset) { 1874 kernel_vm_end = kernel_map->max_offset; 1875 break; 1876 } 1877 } 1878 } 1879 addr = roundup2(addr, PAGE_SIZE * NPTEPG); 1880 if (addr - 1 >= kernel_map->max_offset) 1881 addr = kernel_map->max_offset; 1882 while (kernel_vm_end < addr) { 1883 if (pdir_pde(PTD, kernel_vm_end)) { 1884 kernel_vm_end = (kernel_vm_end + PAGE_SIZE * NPTEPG) & ~(PAGE_SIZE * NPTEPG - 1); 1885 if (kernel_vm_end - 1 >= kernel_map->max_offset) { 1886 kernel_vm_end = kernel_map->max_offset; 1887 break; 1888 } 1889 continue; 1890 } 1891 1892 nkpg = vm_page_alloc(NULL, kernel_vm_end >> PDRSHIFT, 1893 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | 1894 VM_ALLOC_ZERO); 1895 if (nkpg == NULL) 1896 panic("pmap_growkernel: no memory to grow kernel"); 1897 1898 nkpt++; 1899 1900 if ((nkpg->flags & PG_ZERO) == 0) 1901 pmap_zero_page(nkpg); 1902 ptppaddr = VM_PAGE_TO_PHYS(nkpg); 1903 newpdir = (pd_entry_t) (ptppaddr | PG_V | PG_RW | PG_A | PG_M); 1904 pdir_pde(KPTD, kernel_vm_end) = pgeflag | newpdir; 1905 1906 updated_PTD = FALSE; 1907 mtx_lock_spin(&allpmaps_lock); 1908 LIST_FOREACH(pmap, &allpmaps, pm_list) { 1909 if ((pmap->pm_pdir[PTDPTDI] & PG_FRAME) == (PTDpde[0] & 1910 PG_FRAME)) 1911 updated_PTD = TRUE; 1912 pde = pmap_pde(pmap, kernel_vm_end); 1913 pde_store(pde, newpdir); 1914 } 1915 mtx_unlock_spin(&allpmaps_lock); 1916 KASSERT(updated_PTD, 1917 ("pmap_growkernel: current page table is not in allpmaps")); 1918 kernel_vm_end = (kernel_vm_end + PAGE_SIZE * NPTEPG) & ~(PAGE_SIZE * NPTEPG - 1); 1919 if (kernel_vm_end - 1 >= kernel_map->max_offset) { 1920 kernel_vm_end = kernel_map->max_offset; 1921 break; 1922 } 1923 } 1924} 1925 1926 1927/*************************************************** 1928 * page management routines. 1929 ***************************************************/ 1930 1931CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE); 1932CTASSERT(_NPCM == 11); 1933 1934static __inline struct pv_chunk * 1935pv_to_chunk(pv_entry_t pv) 1936{ 1937 1938 return (struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK); 1939} 1940 1941#define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap) 1942 1943#define PC_FREE0_9 0xfffffffful /* Free values for index 0 through 9 */ 1944#define PC_FREE10 0x0000fffful /* Free values for index 10 */ 1945 1946static uint32_t pc_freemask[11] = { 1947 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9, 1948 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9, 1949 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9, 1950 PC_FREE0_9, PC_FREE10 1951}; 1952 1953SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0, 1954 "Current number of pv entries"); 1955 1956#ifdef PV_STATS 1957static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail; 1958 1959SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0, 1960 "Current number of pv entry chunks"); 1961SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0, 1962 "Current number of pv entry chunks allocated"); 1963SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0, 1964 "Current number of pv entry chunks frees"); 1965SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0, 1966 "Number of times tried to get a chunk page but failed."); 1967 1968static long pv_entry_frees, pv_entry_allocs; 1969static int pv_entry_spare; 1970 1971SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0, 1972 "Current number of pv entry frees"); 1973SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0, 1974 "Current number of pv entry allocs"); 1975SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0, 1976 "Current number of spare pv entries"); 1977 1978static int pmap_collect_inactive, pmap_collect_active; 1979 1980SYSCTL_INT(_vm_pmap, OID_AUTO, pmap_collect_inactive, CTLFLAG_RD, &pmap_collect_inactive, 0, 1981 "Current number times pmap_collect called on inactive queue"); 1982SYSCTL_INT(_vm_pmap, OID_AUTO, pmap_collect_active, CTLFLAG_RD, &pmap_collect_active, 0, 1983 "Current number times pmap_collect called on active queue"); 1984#endif 1985 1986/* 1987 * We are in a serious low memory condition. Resort to 1988 * drastic measures to free some pages so we can allocate 1989 * another pv entry chunk. This is normally called to 1990 * unmap inactive pages, and if necessary, active pages. 1991 */ 1992static void 1993pmap_collect(pmap_t locked_pmap, struct vpgqueues *vpq) 1994{ 1995 struct md_page *pvh; 1996 pd_entry_t *pde; 1997 pmap_t pmap; 1998 pt_entry_t *pte, tpte; 1999 pv_entry_t next_pv, pv; 2000 vm_offset_t va; 2001 vm_page_t m, free; 2002 2003 sched_pin(); 2004 TAILQ_FOREACH(m, &vpq->pl, pageq) { 2005 if (m->hold_count || m->busy) 2006 continue; 2007 TAILQ_FOREACH_SAFE(pv, &m->md.pv_list, pv_list, next_pv) { 2008 va = pv->pv_va; 2009 pmap = PV_PMAP(pv); 2010 /* Avoid deadlock and lock recursion. */ 2011 if (pmap > locked_pmap) 2012 PMAP_LOCK(pmap); 2013 else if (pmap != locked_pmap && !PMAP_TRYLOCK(pmap)) 2014 continue; 2015 pmap->pm_stats.resident_count--; 2016 pde = pmap_pde(pmap, va); 2017 KASSERT((*pde & PG_PS) == 0, ("pmap_collect: found" 2018 " a 4mpage in page %p's pv list", m)); 2019 pte = pmap_pte_quick(pmap, va); 2020 tpte = pte_load_clear(pte); 2021 KASSERT((tpte & PG_W) == 0, 2022 ("pmap_collect: wired pte %#jx", (uintmax_t)tpte)); 2023 if (tpte & PG_A) 2024 vm_page_flag_set(m, PG_REFERENCED); 2025 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) 2026 vm_page_dirty(m); 2027 free = NULL; 2028 pmap_unuse_pt(pmap, va, &free); 2029 pmap_invalidate_page(pmap, va); 2030 pmap_free_zero_pages(free); 2031 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list); 2032 if (TAILQ_EMPTY(&m->md.pv_list)) { 2033 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 2034 if (TAILQ_EMPTY(&pvh->pv_list)) 2035 vm_page_flag_clear(m, PG_WRITEABLE); 2036 } 2037 free_pv_entry(pmap, pv); 2038 if (pmap != locked_pmap) 2039 PMAP_UNLOCK(pmap); 2040 } 2041 } 2042 sched_unpin(); 2043} 2044 2045 2046/* 2047 * free the pv_entry back to the free list 2048 */ 2049static void 2050free_pv_entry(pmap_t pmap, pv_entry_t pv) 2051{ 2052 vm_page_t m; 2053 struct pv_chunk *pc; 2054 int idx, field, bit; 2055 2056 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2057 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2058 PV_STAT(pv_entry_frees++); 2059 PV_STAT(pv_entry_spare++); 2060 pv_entry_count--; 2061 pc = pv_to_chunk(pv); 2062 idx = pv - &pc->pc_pventry[0]; 2063 field = idx / 32; 2064 bit = idx % 32; 2065 pc->pc_map[field] |= 1ul << bit; 2066 /* move to head of list */ 2067 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 2068 for (idx = 0; idx < _NPCM; idx++) 2069 if (pc->pc_map[idx] != pc_freemask[idx]) { 2070 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list); 2071 return; 2072 } 2073 PV_STAT(pv_entry_spare -= _NPCPV); 2074 PV_STAT(pc_chunk_count--); 2075 PV_STAT(pc_chunk_frees++); 2076 /* entire chunk is free, return it */ 2077 m = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc)); 2078 pmap_qremove((vm_offset_t)pc, 1); 2079 vm_page_unwire(m, 0); 2080 vm_page_free(m); 2081 pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc); 2082} 2083 2084/* 2085 * get a new pv_entry, allocating a block from the system 2086 * when needed. 2087 */ 2088static pv_entry_t 2089get_pv_entry(pmap_t pmap, int try) 2090{ 2091 static const struct timeval printinterval = { 60, 0 }; 2092 static struct timeval lastprint; 2093 static vm_pindex_t colour; 2094 struct vpgqueues *pq; 2095 int bit, field; 2096 pv_entry_t pv; 2097 struct pv_chunk *pc; 2098 vm_page_t m; 2099 2100 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2101 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2102 PV_STAT(pv_entry_allocs++); 2103 pv_entry_count++; 2104 if (pv_entry_count > pv_entry_high_water) 2105 if (ratecheck(&lastprint, &printinterval)) 2106 printf("Approaching the limit on PV entries, consider " 2107 "increasing either the vm.pmap.shpgperproc or the " 2108 "vm.pmap.pv_entry_max tunable.\n"); 2109 pq = NULL; 2110retry: 2111 pc = TAILQ_FIRST(&pmap->pm_pvchunk); 2112 if (pc != NULL) { 2113 for (field = 0; field < _NPCM; field++) { 2114 if (pc->pc_map[field]) { 2115 bit = bsfl(pc->pc_map[field]); 2116 break; 2117 } 2118 } 2119 if (field < _NPCM) { 2120 pv = &pc->pc_pventry[field * 32 + bit]; 2121 pc->pc_map[field] &= ~(1ul << bit); 2122 /* If this was the last item, move it to tail */ 2123 for (field = 0; field < _NPCM; field++) 2124 if (pc->pc_map[field] != 0) { 2125 PV_STAT(pv_entry_spare--); 2126 return (pv); /* not full, return */ 2127 } 2128 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 2129 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list); 2130 PV_STAT(pv_entry_spare--); 2131 return (pv); 2132 } 2133 } 2134 /* 2135 * Access to the ptelist "pv_vafree" is synchronized by the page 2136 * queues lock. If "pv_vafree" is currently non-empty, it will 2137 * remain non-empty until pmap_ptelist_alloc() completes. 2138 */ 2139 if (pv_vafree == 0 || (m = vm_page_alloc(NULL, colour, (pq == 2140 &vm_page_queues[PQ_ACTIVE] ? VM_ALLOC_SYSTEM : VM_ALLOC_NORMAL) | 2141 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) { 2142 if (try) { 2143 pv_entry_count--; 2144 PV_STAT(pc_chunk_tryfail++); 2145 return (NULL); 2146 } 2147 /* 2148 * Reclaim pv entries: At first, destroy mappings to 2149 * inactive pages. After that, if a pv chunk entry 2150 * is still needed, destroy mappings to active pages. 2151 */ 2152 if (pq == NULL) { 2153 PV_STAT(pmap_collect_inactive++); 2154 pq = &vm_page_queues[PQ_INACTIVE]; 2155 } else if (pq == &vm_page_queues[PQ_INACTIVE]) { 2156 PV_STAT(pmap_collect_active++); 2157 pq = &vm_page_queues[PQ_ACTIVE]; 2158 } else 2159 panic("get_pv_entry: increase vm.pmap.shpgperproc"); 2160 pmap_collect(pmap, pq); 2161 goto retry; 2162 } 2163 PV_STAT(pc_chunk_count++); 2164 PV_STAT(pc_chunk_allocs++); 2165 colour++; 2166 pc = (struct pv_chunk *)pmap_ptelist_alloc(&pv_vafree); 2167 pmap_qenter((vm_offset_t)pc, &m, 1); 2168 pc->pc_pmap = pmap; 2169 pc->pc_map[0] = pc_freemask[0] & ~1ul; /* preallocated bit 0 */ 2170 for (field = 1; field < _NPCM; field++) 2171 pc->pc_map[field] = pc_freemask[field]; 2172 pv = &pc->pc_pventry[0]; 2173 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list); 2174 PV_STAT(pv_entry_spare += _NPCPV - 1); 2175 return (pv); 2176} 2177 2178static __inline pv_entry_t 2179pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va) 2180{ 2181 pv_entry_t pv; 2182 2183 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2184 TAILQ_FOREACH(pv, &pvh->pv_list, pv_list) { 2185 if (pmap == PV_PMAP(pv) && va == pv->pv_va) { 2186 TAILQ_REMOVE(&pvh->pv_list, pv, pv_list); 2187 break; 2188 } 2189 } 2190 return (pv); 2191} 2192 2193static void 2194pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa) 2195{ 2196 struct md_page *pvh; 2197 pv_entry_t pv; 2198 vm_offset_t va_last; 2199 vm_page_t m; 2200 2201 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2202 KASSERT((pa & PDRMASK) == 0, 2203 ("pmap_pv_demote_pde: pa is not 4mpage aligned")); 2204 2205 /* 2206 * Transfer the 4mpage's pv entry for this mapping to the first 2207 * page's pv list. 2208 */ 2209 pvh = pa_to_pvh(pa); 2210 va = trunc_4mpage(va); 2211 pv = pmap_pvh_remove(pvh, pmap, va); 2212 KASSERT(pv != NULL, ("pmap_pv_demote_pde: pv not found")); 2213 m = PHYS_TO_VM_PAGE(pa); 2214 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list); 2215 /* Instantiate the remaining NPTEPG - 1 pv entries. */ 2216 va_last = va + NBPDR - PAGE_SIZE; 2217 do { 2218 m++; 2219 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 2220 ("pmap_pv_demote_pde: page %p is not managed", m)); 2221 va += PAGE_SIZE; 2222 pmap_insert_entry(pmap, va, m); 2223 } while (va < va_last); 2224} 2225 2226static void 2227pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa) 2228{ 2229 struct md_page *pvh; 2230 pv_entry_t pv; 2231 vm_offset_t va_last; 2232 vm_page_t m; 2233 2234 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2235 KASSERT((pa & PDRMASK) == 0, 2236 ("pmap_pv_promote_pde: pa is not 4mpage aligned")); 2237 2238 /* 2239 * Transfer the first page's pv entry for this mapping to the 2240 * 4mpage's pv list. Aside from avoiding the cost of a call 2241 * to get_pv_entry(), a transfer avoids the possibility that 2242 * get_pv_entry() calls pmap_collect() and that pmap_collect() 2243 * removes one of the mappings that is being promoted. 2244 */ 2245 m = PHYS_TO_VM_PAGE(pa); 2246 va = trunc_4mpage(va); 2247 pv = pmap_pvh_remove(&m->md, pmap, va); 2248 KASSERT(pv != NULL, ("pmap_pv_promote_pde: pv not found")); 2249 pvh = pa_to_pvh(pa); 2250 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_list); 2251 /* Free the remaining NPTEPG - 1 pv entries. */ 2252 va_last = va + NBPDR - PAGE_SIZE; 2253 do { 2254 m++; 2255 va += PAGE_SIZE; 2256 pmap_pvh_free(&m->md, pmap, va); 2257 } while (va < va_last); 2258} 2259 2260static void 2261pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va) 2262{ 2263 pv_entry_t pv; 2264 2265 pv = pmap_pvh_remove(pvh, pmap, va); 2266 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found")); 2267 free_pv_entry(pmap, pv); 2268} 2269 2270static void 2271pmap_remove_entry(pmap_t pmap, vm_page_t m, vm_offset_t va) 2272{ 2273 struct md_page *pvh; 2274 2275 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2276 pmap_pvh_free(&m->md, pmap, va); 2277 if (TAILQ_EMPTY(&m->md.pv_list)) { 2278 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 2279 if (TAILQ_EMPTY(&pvh->pv_list)) 2280 vm_page_flag_clear(m, PG_WRITEABLE); 2281 } 2282} 2283 2284/* 2285 * Create a pv entry for page at pa for 2286 * (pmap, va). 2287 */ 2288static void 2289pmap_insert_entry(pmap_t pmap, vm_offset_t va, vm_page_t m) 2290{ 2291 pv_entry_t pv; 2292 2293 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2294 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2295 pv = get_pv_entry(pmap, FALSE); 2296 pv->pv_va = va; 2297 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list); 2298} 2299 2300/* 2301 * Conditionally create a pv entry. 2302 */ 2303static boolean_t 2304pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m) 2305{ 2306 pv_entry_t pv; 2307 2308 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2309 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2310 if (pv_entry_count < pv_entry_high_water && 2311 (pv = get_pv_entry(pmap, TRUE)) != NULL) { 2312 pv->pv_va = va; 2313 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list); 2314 return (TRUE); 2315 } else 2316 return (FALSE); 2317} 2318 2319/* 2320 * Create the pv entries for each of the pages within a superpage. 2321 */ 2322static boolean_t 2323pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa) 2324{ 2325 struct md_page *pvh; 2326 pv_entry_t pv; 2327 2328 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2329 if (pv_entry_count < pv_entry_high_water && 2330 (pv = get_pv_entry(pmap, TRUE)) != NULL) { 2331 pv->pv_va = va; 2332 pvh = pa_to_pvh(pa); 2333 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_list); 2334 return (TRUE); 2335 } else 2336 return (FALSE); 2337} 2338 2339/* 2340 * Fills a page table page with mappings to consecutive physical pages. 2341 */ 2342static void 2343pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte) 2344{ 2345 pt_entry_t *pte; 2346 2347 for (pte = firstpte; pte < firstpte + NPTEPG; pte++) { 2348 *pte = newpte; 2349 newpte += PAGE_SIZE; 2350 } 2351} 2352 2353/* 2354 * Tries to demote a 2- or 4MB page mapping. If demotion fails, the 2355 * 2- or 4MB page mapping is invalidated. 2356 */ 2357static boolean_t 2358pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va) 2359{ 2360 pd_entry_t newpde, oldpde; 2361 pmap_t allpmaps_entry; 2362 pt_entry_t *firstpte, newpte; 2363 vm_paddr_t mptepa; 2364 vm_page_t free, mpte; 2365 2366 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2367 oldpde = *pde; 2368 KASSERT((oldpde & (PG_PS | PG_V)) == (PG_PS | PG_V), 2369 ("pmap_demote_pde: oldpde is missing PG_PS and/or PG_V")); 2370 mpte = pmap_lookup_pt_page(pmap, va); 2371 if (mpte != NULL) 2372 pmap_remove_pt_page(pmap, mpte); 2373 else { 2374 KASSERT((oldpde & PG_W) == 0, 2375 ("pmap_demote_pde: page table page for a wired mapping" 2376 " is missing")); 2377 2378 /* 2379 * Invalidate the 2- or 4MB page mapping and return 2380 * "failure" if the mapping was never accessed or the 2381 * allocation of the new page table page fails. 2382 */ 2383 if ((oldpde & PG_A) == 0 || (mpte = vm_page_alloc(NULL, 2384 va >> PDRSHIFT, VM_ALLOC_NOOBJ | VM_ALLOC_NORMAL | 2385 VM_ALLOC_WIRED)) == NULL) { 2386 free = NULL; 2387 pmap_remove_pde(pmap, pde, trunc_4mpage(va), &free); 2388 pmap_invalidate_page(pmap, trunc_4mpage(va)); 2389 pmap_free_zero_pages(free); 2390 CTR2(KTR_PMAP, "pmap_demote_pde: failure for va %#x" 2391 " in pmap %p", va, pmap); 2392 return (FALSE); 2393 } 2394 if (va < VM_MAXUSER_ADDRESS) 2395 pmap->pm_stats.resident_count++; 2396 } 2397 mptepa = VM_PAGE_TO_PHYS(mpte); 2398 2399 /* 2400 * If the page mapping is in the kernel's address space, then the 2401 * KPTmap can provide access to the page table page. Otherwise, 2402 * temporarily map the page table page (mpte) into the kernel's 2403 * address space at either PADDR1 or PADDR2. 2404 */ 2405 if (va >= KERNBASE) 2406 firstpte = &KPTmap[i386_btop(trunc_4mpage(va))]; 2407 else if (curthread->td_pinned > 0 && mtx_owned(&vm_page_queue_mtx)) { 2408 if ((*PMAP1 & PG_FRAME) != mptepa) { 2409 *PMAP1 = mptepa | PG_RW | PG_V | PG_A | PG_M; 2410#ifdef SMP 2411 PMAP1cpu = PCPU_GET(cpuid); 2412#endif 2413 invlcaddr(PADDR1); 2414 PMAP1changed++; 2415 } else 2416#ifdef SMP 2417 if (PMAP1cpu != PCPU_GET(cpuid)) { 2418 PMAP1cpu = PCPU_GET(cpuid); 2419 invlcaddr(PADDR1); 2420 PMAP1changedcpu++; 2421 } else 2422#endif 2423 PMAP1unchanged++; 2424 firstpte = PADDR1; 2425 } else { 2426 mtx_lock(&PMAP2mutex); 2427 if ((*PMAP2 & PG_FRAME) != mptepa) { 2428 *PMAP2 = mptepa | PG_RW | PG_V | PG_A | PG_M; 2429 pmap_invalidate_page(kernel_pmap, (vm_offset_t)PADDR2); 2430 } 2431 firstpte = PADDR2; 2432 } 2433 newpde = mptepa | PG_M | PG_A | (oldpde & PG_U) | PG_RW | PG_V; 2434 KASSERT((oldpde & PG_A) != 0, 2435 ("pmap_demote_pde: oldpde is missing PG_A")); 2436 KASSERT((oldpde & (PG_M | PG_RW)) != PG_RW, 2437 ("pmap_demote_pde: oldpde is missing PG_M")); 2438 newpte = oldpde & ~PG_PS; 2439 if ((newpte & PG_PDE_PAT) != 0) 2440 newpte ^= PG_PDE_PAT | PG_PTE_PAT; 2441 2442 /* 2443 * If the page table page is new, initialize it. 2444 */ 2445 if (mpte->wire_count == 1) { 2446 mpte->wire_count = NPTEPG; 2447 pmap_fill_ptp(firstpte, newpte); 2448 } 2449 KASSERT((*firstpte & PG_FRAME) == (newpte & PG_FRAME), 2450 ("pmap_demote_pde: firstpte and newpte map different physical" 2451 " addresses")); 2452 2453 /* 2454 * If the mapping has changed attributes, update the page table 2455 * entries. 2456 */ 2457 if ((*firstpte & PG_PTE_PROMOTE) != (newpte & PG_PTE_PROMOTE)) 2458 pmap_fill_ptp(firstpte, newpte); 2459 2460 /* 2461 * Demote the mapping. This pmap is locked. The old PDE has 2462 * PG_A set. If the old PDE has PG_RW set, it also has PG_M 2463 * set. Thus, there is no danger of a race with another 2464 * processor changing the setting of PG_A and/or PG_M between 2465 * the read above and the store below. 2466 */ 2467 if (pmap == kernel_pmap) { 2468 /* 2469 * A harmless race exists between this loop and the bcopy() 2470 * in pmap_pinit() that initializes the kernel segment of 2471 * the new page table directory. Specifically, that bcopy() 2472 * may copy the new PDE from the PTD to the new page table 2473 * before this loop updates that new page table. 2474 */ 2475 mtx_lock_spin(&allpmaps_lock); 2476 LIST_FOREACH(allpmaps_entry, &allpmaps, pm_list) { 2477 pde = pmap_pde(allpmaps_entry, va); 2478 KASSERT(*pde == newpde || (*pde & PG_PTE_PROMOTE) == 2479 (oldpde & PG_PTE_PROMOTE), 2480 ("pmap_demote_pde: pde was %#jx, expected %#jx", 2481 (uintmax_t)*pde, (uintmax_t)oldpde)); 2482 pde_store(pde, newpde); 2483 } 2484 mtx_unlock_spin(&allpmaps_lock); 2485 } else 2486 pde_store(pde, newpde); 2487 if (firstpte == PADDR2) 2488 mtx_unlock(&PMAP2mutex); 2489 2490 /* 2491 * Invalidate the recursive mapping of the page table page. 2492 */ 2493 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va)); 2494 2495 /* 2496 * Demote the pv entry. This depends on the earlier demotion 2497 * of the mapping. Specifically, the (re)creation of a per- 2498 * page pv entry might trigger the execution of pmap_collect(), 2499 * which might reclaim a newly (re)created per-page pv entry 2500 * and destroy the associated mapping. In order to destroy 2501 * the mapping, the PDE must have already changed from mapping 2502 * the 2mpage to referencing the page table page. 2503 */ 2504 if ((oldpde & PG_MANAGED) != 0) 2505 pmap_pv_demote_pde(pmap, va, oldpde & PG_PS_FRAME); 2506 2507 pmap_pde_demotions++; 2508 CTR2(KTR_PMAP, "pmap_demote_pde: success for va %#x" 2509 " in pmap %p", va, pmap); 2510 return (TRUE); 2511} 2512 2513/* 2514 * pmap_remove_pde: do the things to unmap a superpage in a process 2515 */ 2516static void 2517pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva, 2518 vm_page_t *free) 2519{ 2520 struct md_page *pvh; 2521 pd_entry_t oldpde; 2522 vm_offset_t eva, va; 2523 vm_page_t m, mpte; 2524 2525 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2526 KASSERT((sva & PDRMASK) == 0, 2527 ("pmap_remove_pde: sva is not 4mpage aligned")); 2528 oldpde = pte_load_clear(pdq); 2529 if (oldpde & PG_W) 2530 pmap->pm_stats.wired_count -= NBPDR / PAGE_SIZE; 2531 2532 /* 2533 * Machines that don't support invlpg, also don't support 2534 * PG_G. 2535 */ 2536 if (oldpde & PG_G) 2537 pmap_invalidate_page(kernel_pmap, sva); 2538 pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE; 2539 if (oldpde & PG_MANAGED) { 2540 pvh = pa_to_pvh(oldpde & PG_PS_FRAME); 2541 pmap_pvh_free(pvh, pmap, sva); 2542 eva = sva + NBPDR; 2543 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME); 2544 va < eva; va += PAGE_SIZE, m++) { 2545 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW)) 2546 vm_page_dirty(m); 2547 if (oldpde & PG_A) 2548 vm_page_flag_set(m, PG_REFERENCED); 2549 if (TAILQ_EMPTY(&m->md.pv_list) && 2550 TAILQ_EMPTY(&pvh->pv_list)) 2551 vm_page_flag_clear(m, PG_WRITEABLE); 2552 } 2553 } 2554 if (pmap == kernel_pmap) { 2555 if (!pmap_demote_pde(pmap, pdq, sva)) 2556 panic("pmap_remove_pde: failed demotion"); 2557 } else { 2558 mpte = pmap_lookup_pt_page(pmap, sva); 2559 if (mpte != NULL) { 2560 pmap_remove_pt_page(pmap, mpte); 2561 pmap->pm_stats.resident_count--; 2562 KASSERT(mpte->wire_count == NPTEPG, 2563 ("pmap_remove_pde: pte page wire count error")); 2564 mpte->wire_count = 0; 2565 pmap_add_delayed_free_list(mpte, free, FALSE); 2566 atomic_subtract_int(&cnt.v_wire_count, 1); 2567 } 2568 } 2569} 2570 2571/* 2572 * pmap_remove_pte: do the things to unmap a page in a process 2573 */ 2574static int 2575pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t va, vm_page_t *free) 2576{ 2577 pt_entry_t oldpte; 2578 vm_page_t m; 2579 2580 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2581 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2582 oldpte = pte_load_clear(ptq); 2583 if (oldpte & PG_W) 2584 pmap->pm_stats.wired_count -= 1; 2585 /* 2586 * Machines that don't support invlpg, also don't support 2587 * PG_G. 2588 */ 2589 if (oldpte & PG_G) 2590 pmap_invalidate_page(kernel_pmap, va); 2591 pmap->pm_stats.resident_count -= 1; 2592 if (oldpte & PG_MANAGED) { 2593 m = PHYS_TO_VM_PAGE(oldpte & PG_FRAME); 2594 if ((oldpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) 2595 vm_page_dirty(m); 2596 if (oldpte & PG_A) 2597 vm_page_flag_set(m, PG_REFERENCED); 2598 pmap_remove_entry(pmap, m, va); 2599 } 2600 return (pmap_unuse_pt(pmap, va, free)); 2601} 2602 2603/* 2604 * Remove a single page from a process address space 2605 */ 2606static void 2607pmap_remove_page(pmap_t pmap, vm_offset_t va, vm_page_t *free) 2608{ 2609 pt_entry_t *pte; 2610 2611 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2612 KASSERT(curthread->td_pinned > 0, ("curthread not pinned")); 2613 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2614 if ((pte = pmap_pte_quick(pmap, va)) == NULL || *pte == 0) 2615 return; 2616 pmap_remove_pte(pmap, pte, va, free); 2617 pmap_invalidate_page(pmap, va); 2618} 2619 2620/* 2621 * Remove the given range of addresses from the specified map. 2622 * 2623 * It is assumed that the start and end are properly 2624 * rounded to the page size. 2625 */ 2626void 2627pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 2628{ 2629 vm_offset_t pdnxt; 2630 pd_entry_t ptpaddr; 2631 pt_entry_t *pte; 2632 vm_page_t free = NULL; 2633 int anyvalid; 2634 2635 /* 2636 * Perform an unsynchronized read. This is, however, safe. 2637 */ 2638 if (pmap->pm_stats.resident_count == 0) 2639 return; 2640 2641 anyvalid = 0; 2642 2643 vm_page_lock_queues(); 2644 sched_pin(); 2645 PMAP_LOCK(pmap); 2646 2647 /* 2648 * special handling of removing one page. a very 2649 * common operation and easy to short circuit some 2650 * code. 2651 */ 2652 if ((sva + PAGE_SIZE == eva) && 2653 ((pmap->pm_pdir[(sva >> PDRSHIFT)] & PG_PS) == 0)) { 2654 pmap_remove_page(pmap, sva, &free); 2655 goto out; 2656 } 2657 2658 for (; sva < eva; sva = pdnxt) { 2659 unsigned pdirindex; 2660 2661 /* 2662 * Calculate index for next page table. 2663 */ 2664 pdnxt = (sva + NBPDR) & ~PDRMASK; 2665 if (pdnxt < sva) 2666 pdnxt = eva; 2667 if (pmap->pm_stats.resident_count == 0) 2668 break; 2669 2670 pdirindex = sva >> PDRSHIFT; 2671 ptpaddr = pmap->pm_pdir[pdirindex]; 2672 2673 /* 2674 * Weed out invalid mappings. Note: we assume that the page 2675 * directory table is always allocated, and in kernel virtual. 2676 */ 2677 if (ptpaddr == 0) 2678 continue; 2679 2680 /* 2681 * Check for large page. 2682 */ 2683 if ((ptpaddr & PG_PS) != 0) { 2684 /* 2685 * Are we removing the entire large page? If not, 2686 * demote the mapping and fall through. 2687 */ 2688 if (sva + NBPDR == pdnxt && eva >= pdnxt) { 2689 /* 2690 * The TLB entry for a PG_G mapping is 2691 * invalidated by pmap_remove_pde(). 2692 */ 2693 if ((ptpaddr & PG_G) == 0) 2694 anyvalid = 1; 2695 pmap_remove_pde(pmap, 2696 &pmap->pm_pdir[pdirindex], sva, &free); 2697 continue; 2698 } else if (!pmap_demote_pde(pmap, 2699 &pmap->pm_pdir[pdirindex], sva)) { 2700 /* The large page mapping was destroyed. */ 2701 continue; 2702 } 2703 } 2704 2705 /* 2706 * Limit our scan to either the end of the va represented 2707 * by the current page table page, or to the end of the 2708 * range being removed. 2709 */ 2710 if (pdnxt > eva) 2711 pdnxt = eva; 2712 2713 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++, 2714 sva += PAGE_SIZE) { 2715 if (*pte == 0) 2716 continue; 2717 2718 /* 2719 * The TLB entry for a PG_G mapping is invalidated 2720 * by pmap_remove_pte(). 2721 */ 2722 if ((*pte & PG_G) == 0) 2723 anyvalid = 1; 2724 if (pmap_remove_pte(pmap, pte, sva, &free)) 2725 break; 2726 } 2727 } 2728out: 2729 sched_unpin(); 2730 if (anyvalid) 2731 pmap_invalidate_all(pmap); 2732 vm_page_unlock_queues(); 2733 PMAP_UNLOCK(pmap); 2734 pmap_free_zero_pages(free); 2735} 2736 2737/* 2738 * Routine: pmap_remove_all 2739 * Function: 2740 * Removes this physical page from 2741 * all physical maps in which it resides. 2742 * Reflects back modify bits to the pager. 2743 * 2744 * Notes: 2745 * Original versions of this routine were very 2746 * inefficient because they iteratively called 2747 * pmap_remove (slow...) 2748 */ 2749 2750void 2751pmap_remove_all(vm_page_t m) 2752{ 2753 struct md_page *pvh; 2754 pv_entry_t pv; 2755 pmap_t pmap; 2756 pt_entry_t *pte, tpte; 2757 pd_entry_t *pde; 2758 vm_offset_t va; 2759 vm_page_t free; 2760 2761 KASSERT((m->flags & PG_FICTITIOUS) == 0, 2762 ("pmap_remove_all: page %p is fictitious", m)); 2763 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2764 sched_pin(); 2765 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 2766 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) { 2767 va = pv->pv_va; 2768 pmap = PV_PMAP(pv); 2769 PMAP_LOCK(pmap); 2770 pde = pmap_pde(pmap, va); 2771 (void)pmap_demote_pde(pmap, pde, va); 2772 PMAP_UNLOCK(pmap); 2773 } 2774 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) { 2775 pmap = PV_PMAP(pv); 2776 PMAP_LOCK(pmap); 2777 pmap->pm_stats.resident_count--; 2778 pde = pmap_pde(pmap, pv->pv_va); 2779 KASSERT((*pde & PG_PS) == 0, ("pmap_remove_all: found" 2780 " a 4mpage in page %p's pv list", m)); 2781 pte = pmap_pte_quick(pmap, pv->pv_va); 2782 tpte = pte_load_clear(pte); 2783 if (tpte & PG_W) 2784 pmap->pm_stats.wired_count--; 2785 if (tpte & PG_A) 2786 vm_page_flag_set(m, PG_REFERENCED); 2787 2788 /* 2789 * Update the vm_page_t clean and reference bits. 2790 */ 2791 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) 2792 vm_page_dirty(m); 2793 free = NULL; 2794 pmap_unuse_pt(pmap, pv->pv_va, &free); 2795 pmap_invalidate_page(pmap, pv->pv_va); 2796 pmap_free_zero_pages(free); 2797 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list); 2798 free_pv_entry(pmap, pv); 2799 PMAP_UNLOCK(pmap); 2800 } 2801 vm_page_flag_clear(m, PG_WRITEABLE); 2802 sched_unpin(); 2803} 2804 2805/* 2806 * pmap_protect_pde: do the things to protect a 4mpage in a process 2807 */ 2808static boolean_t 2809pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva, vm_prot_t prot) 2810{ 2811 pd_entry_t newpde, oldpde; 2812 vm_offset_t eva, va; 2813 vm_page_t m; 2814 boolean_t anychanged; 2815 2816 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2817 KASSERT((sva & PDRMASK) == 0, 2818 ("pmap_protect_pde: sva is not 4mpage aligned")); 2819 anychanged = FALSE; 2820retry: 2821 oldpde = newpde = *pde; 2822 if (oldpde & PG_MANAGED) { 2823 eva = sva + NBPDR; 2824 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME); 2825 va < eva; va += PAGE_SIZE, m++) { 2826 /* 2827 * In contrast to the analogous operation on a 4KB page 2828 * mapping, the mapping's PG_A flag is not cleared and 2829 * the page's PG_REFERENCED flag is not set. The 2830 * reason is that pmap_demote_pde() expects that a 2/4MB 2831 * page mapping with a stored page table page has PG_A 2832 * set. 2833 */ 2834 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW)) 2835 vm_page_dirty(m); 2836 } 2837 } 2838 if ((prot & VM_PROT_WRITE) == 0) 2839 newpde &= ~(PG_RW | PG_M); 2840#ifdef PAE 2841 if ((prot & VM_PROT_EXECUTE) == 0) 2842 newpde |= pg_nx; 2843#endif 2844 if (newpde != oldpde) { 2845 if (!pde_cmpset(pde, oldpde, newpde)) 2846 goto retry; 2847 if (oldpde & PG_G) 2848 pmap_invalidate_page(pmap, sva); 2849 else 2850 anychanged = TRUE; 2851 } 2852 return (anychanged); 2853} 2854 2855/* 2856 * Set the physical protection on the 2857 * specified range of this map as requested. 2858 */ 2859void 2860pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot) 2861{ 2862 vm_offset_t pdnxt; 2863 pd_entry_t ptpaddr; 2864 pt_entry_t *pte; 2865 int anychanged; 2866 2867 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 2868 pmap_remove(pmap, sva, eva); 2869 return; 2870 } 2871 2872#ifdef PAE 2873 if ((prot & (VM_PROT_WRITE|VM_PROT_EXECUTE)) == 2874 (VM_PROT_WRITE|VM_PROT_EXECUTE)) 2875 return; 2876#else 2877 if (prot & VM_PROT_WRITE) 2878 return; 2879#endif 2880 2881 anychanged = 0; 2882 2883 vm_page_lock_queues(); 2884 sched_pin(); 2885 PMAP_LOCK(pmap); 2886 for (; sva < eva; sva = pdnxt) { 2887 pt_entry_t obits, pbits; 2888 unsigned pdirindex; 2889 2890 pdnxt = (sva + NBPDR) & ~PDRMASK; 2891 if (pdnxt < sva) 2892 pdnxt = eva; 2893 2894 pdirindex = sva >> PDRSHIFT; 2895 ptpaddr = pmap->pm_pdir[pdirindex]; 2896 2897 /* 2898 * Weed out invalid mappings. Note: we assume that the page 2899 * directory table is always allocated, and in kernel virtual. 2900 */ 2901 if (ptpaddr == 0) 2902 continue; 2903 2904 /* 2905 * Check for large page. 2906 */ 2907 if ((ptpaddr & PG_PS) != 0) { 2908 /* 2909 * Are we protecting the entire large page? If not, 2910 * demote the mapping and fall through. 2911 */ 2912 if (sva + NBPDR == pdnxt && eva >= pdnxt) { 2913 /* 2914 * The TLB entry for a PG_G mapping is 2915 * invalidated by pmap_protect_pde(). 2916 */ 2917 if (pmap_protect_pde(pmap, 2918 &pmap->pm_pdir[pdirindex], sva, prot)) 2919 anychanged = 1; 2920 continue; 2921 } else if (!pmap_demote_pde(pmap, 2922 &pmap->pm_pdir[pdirindex], sva)) { 2923 /* The large page mapping was destroyed. */ 2924 continue; 2925 } 2926 } 2927 2928 if (pdnxt > eva) 2929 pdnxt = eva; 2930 2931 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++, 2932 sva += PAGE_SIZE) { 2933 vm_page_t m; 2934 2935retry: 2936 /* 2937 * Regardless of whether a pte is 32 or 64 bits in 2938 * size, PG_RW, PG_A, and PG_M are among the least 2939 * significant 32 bits. 2940 */ 2941 obits = pbits = *pte; 2942 if ((pbits & PG_V) == 0) 2943 continue; 2944 if (pbits & PG_MANAGED) { 2945 m = NULL; 2946 if (pbits & PG_A) { 2947 m = PHYS_TO_VM_PAGE(pbits & PG_FRAME); 2948 vm_page_flag_set(m, PG_REFERENCED); 2949 pbits &= ~PG_A; 2950 } 2951 if ((pbits & (PG_M | PG_RW)) == (PG_M | PG_RW)) { 2952 if (m == NULL) 2953 m = PHYS_TO_VM_PAGE(pbits & PG_FRAME); 2954 vm_page_dirty(m); 2955 } 2956 } 2957 2958 if ((prot & VM_PROT_WRITE) == 0) 2959 pbits &= ~(PG_RW | PG_M); 2960#ifdef PAE 2961 if ((prot & VM_PROT_EXECUTE) == 0) 2962 pbits |= pg_nx; 2963#endif 2964 2965 if (pbits != obits) { 2966#ifdef PAE 2967 if (!atomic_cmpset_64(pte, obits, pbits)) 2968 goto retry; 2969#else 2970 if (!atomic_cmpset_int((u_int *)pte, obits, 2971 pbits)) 2972 goto retry; 2973#endif 2974 if (obits & PG_G) 2975 pmap_invalidate_page(pmap, sva); 2976 else 2977 anychanged = 1; 2978 } 2979 } 2980 } 2981 sched_unpin(); 2982 if (anychanged) 2983 pmap_invalidate_all(pmap); 2984 vm_page_unlock_queues(); 2985 PMAP_UNLOCK(pmap); 2986} 2987 2988/* 2989 * Tries to promote the 512 or 1024, contiguous 4KB page mappings that are 2990 * within a single page table page (PTP) to a single 2- or 4MB page mapping. 2991 * For promotion to occur, two conditions must be met: (1) the 4KB page 2992 * mappings must map aligned, contiguous physical memory and (2) the 4KB page 2993 * mappings must have identical characteristics. 2994 * 2995 * Managed (PG_MANAGED) mappings within the kernel address space are not 2996 * promoted. The reason is that kernel PDEs are replicated in each pmap but 2997 * pmap_clear_ptes() and pmap_ts_referenced() only read the PDE from the kernel 2998 * pmap. 2999 */ 3000static void 3001pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va) 3002{ 3003 pd_entry_t newpde; 3004 pmap_t allpmaps_entry; 3005 pt_entry_t *firstpte, oldpte, pa, *pte; 3006 vm_offset_t oldpteva; 3007 vm_page_t mpte; 3008 3009 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 3010 3011 /* 3012 * Examine the first PTE in the specified PTP. Abort if this PTE is 3013 * either invalid, unused, or does not map the first 4KB physical page 3014 * within a 2- or 4MB page. 3015 */ 3016 firstpte = vtopte(trunc_4mpage(va)); 3017setpde: 3018 newpde = *firstpte; 3019 if ((newpde & ((PG_FRAME & PDRMASK) | PG_A | PG_V)) != (PG_A | PG_V)) { 3020 pmap_pde_p_failures++; 3021 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x" 3022 " in pmap %p", va, pmap); 3023 return; 3024 } 3025 if ((*firstpte & PG_MANAGED) != 0 && pmap == kernel_pmap) { 3026 pmap_pde_p_failures++; 3027 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x" 3028 " in pmap %p", va, pmap); 3029 return; 3030 } 3031 if ((newpde & (PG_M | PG_RW)) == PG_RW) { 3032 /* 3033 * When PG_M is already clear, PG_RW can be cleared without 3034 * a TLB invalidation. 3035 */ 3036 if (!atomic_cmpset_int((u_int *)firstpte, newpde, newpde & 3037 ~PG_RW)) 3038 goto setpde; 3039 newpde &= ~PG_RW; 3040 } 3041 3042 /* 3043 * Examine each of the other PTEs in the specified PTP. Abort if this 3044 * PTE maps an unexpected 4KB physical page or does not have identical 3045 * characteristics to the first PTE. 3046 */ 3047 pa = (newpde & (PG_PS_FRAME | PG_A | PG_V)) + NBPDR - PAGE_SIZE; 3048 for (pte = firstpte + NPTEPG - 1; pte > firstpte; pte--) { 3049setpte: 3050 oldpte = *pte; 3051 if ((oldpte & (PG_FRAME | PG_A | PG_V)) != pa) { 3052 pmap_pde_p_failures++; 3053 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x" 3054 " in pmap %p", va, pmap); 3055 return; 3056 } 3057 if ((oldpte & (PG_M | PG_RW)) == PG_RW) { 3058 /* 3059 * When PG_M is already clear, PG_RW can be cleared 3060 * without a TLB invalidation. 3061 */ 3062 if (!atomic_cmpset_int((u_int *)pte, oldpte, 3063 oldpte & ~PG_RW)) 3064 goto setpte; 3065 oldpte &= ~PG_RW; 3066 oldpteva = (oldpte & PG_FRAME & PDRMASK) | 3067 (va & ~PDRMASK); 3068 CTR2(KTR_PMAP, "pmap_promote_pde: protect for va %#x" 3069 " in pmap %p", oldpteva, pmap); 3070 } 3071 if ((oldpte & PG_PTE_PROMOTE) != (newpde & PG_PTE_PROMOTE)) { 3072 pmap_pde_p_failures++; 3073 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x" 3074 " in pmap %p", va, pmap); 3075 return; 3076 } 3077 pa -= PAGE_SIZE; 3078 } 3079 3080 /* 3081 * Save the page table page in its current state until the PDE 3082 * mapping the superpage is demoted by pmap_demote_pde() or 3083 * destroyed by pmap_remove_pde(). 3084 */ 3085 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME); 3086 KASSERT(mpte >= vm_page_array && 3087 mpte < &vm_page_array[vm_page_array_size], 3088 ("pmap_promote_pde: page table page is out of range")); 3089 KASSERT(mpte->pindex == va >> PDRSHIFT, 3090 ("pmap_promote_pde: page table page's pindex is wrong")); 3091 pmap_insert_pt_page(pmap, mpte); 3092 3093 /* 3094 * Promote the pv entries. 3095 */ 3096 if ((newpde & PG_MANAGED) != 0) 3097 pmap_pv_promote_pde(pmap, va, newpde & PG_PS_FRAME); 3098 3099 /* 3100 * Propagate the PAT index to its proper position. 3101 */ 3102 if ((newpde & PG_PTE_PAT) != 0) 3103 newpde ^= PG_PDE_PAT | PG_PTE_PAT; 3104 3105 /* 3106 * Map the superpage. 3107 */ 3108 if (pmap == kernel_pmap) { 3109 mtx_lock_spin(&allpmaps_lock); 3110 LIST_FOREACH(allpmaps_entry, &allpmaps, pm_list) { 3111 pde = pmap_pde(allpmaps_entry, va); 3112 pde_store(pde, PG_PS | newpde); 3113 } 3114 mtx_unlock_spin(&allpmaps_lock); 3115 } else 3116 pde_store(pde, PG_PS | newpde); 3117 3118 pmap_pde_promotions++; 3119 CTR2(KTR_PMAP, "pmap_promote_pde: success for va %#x" 3120 " in pmap %p", va, pmap); 3121} 3122 3123/* 3124 * Insert the given physical page (p) at 3125 * the specified virtual address (v) in the 3126 * target physical map with the protection requested. 3127 * 3128 * If specified, the page will be wired down, meaning 3129 * that the related pte can not be reclaimed. 3130 * 3131 * NB: This is the only routine which MAY NOT lazy-evaluate 3132 * or lose information. That is, this routine must actually 3133 * insert this page into the given map NOW. 3134 */ 3135void 3136pmap_enter(pmap_t pmap, vm_offset_t va, vm_prot_t access, vm_page_t m, 3137 vm_prot_t prot, boolean_t wired) 3138{ 3139 vm_paddr_t pa; 3140 pd_entry_t *pde; 3141 pt_entry_t *pte; 3142 vm_paddr_t opa; 3143 pt_entry_t origpte, newpte; 3144 vm_page_t mpte, om; 3145 boolean_t invlva; 3146 3147 va = trunc_page(va); 3148 KASSERT(va <= VM_MAX_KERNEL_ADDRESS, ("pmap_enter: toobig")); 3149 KASSERT(va < UPT_MIN_ADDRESS || va >= UPT_MAX_ADDRESS, 3150 ("pmap_enter: invalid to pmap_enter page table pages (va: 0x%x)", va)); 3151 3152 mpte = NULL; 3153 3154 vm_page_lock_queues(); 3155 PMAP_LOCK(pmap); 3156 sched_pin(); 3157 3158 /* 3159 * In the case that a page table page is not 3160 * resident, we are creating it here. 3161 */ 3162 if (va < VM_MAXUSER_ADDRESS) { 3163 mpte = pmap_allocpte(pmap, va, M_WAITOK); 3164 } 3165 3166 pde = pmap_pde(pmap, va); 3167 if ((*pde & PG_PS) != 0) 3168 panic("pmap_enter: attempted pmap_enter on 4MB page"); 3169 pte = pmap_pte_quick(pmap, va); 3170 3171 /* 3172 * Page Directory table entry not valid, we need a new PT page 3173 */ 3174 if (pte == NULL) { 3175 panic("pmap_enter: invalid page directory pdir=%#jx, va=%#x", 3176 (uintmax_t)pmap->pm_pdir[PTDPTDI], va); 3177 } 3178 3179 pa = VM_PAGE_TO_PHYS(m); 3180 om = NULL; 3181 origpte = *pte; 3182 opa = origpte & PG_FRAME; 3183 3184 /* 3185 * Mapping has not changed, must be protection or wiring change. 3186 */ 3187 if (origpte && (opa == pa)) { 3188 /* 3189 * Wiring change, just update stats. We don't worry about 3190 * wiring PT pages as they remain resident as long as there 3191 * are valid mappings in them. Hence, if a user page is wired, 3192 * the PT page will be also. 3193 */ 3194 if (wired && ((origpte & PG_W) == 0)) 3195 pmap->pm_stats.wired_count++; 3196 else if (!wired && (origpte & PG_W)) 3197 pmap->pm_stats.wired_count--; 3198 3199 /* 3200 * Remove extra pte reference 3201 */ 3202 if (mpte) 3203 mpte->wire_count--; 3204 3205 /* 3206 * We might be turning off write access to the page, 3207 * so we go ahead and sense modify status. 3208 */ 3209 if (origpte & PG_MANAGED) { 3210 om = m; 3211 pa |= PG_MANAGED; 3212 } 3213 goto validate; 3214 } 3215 /* 3216 * Mapping has changed, invalidate old range and fall through to 3217 * handle validating new mapping. 3218 */ 3219 if (opa) { 3220 if (origpte & PG_W) 3221 pmap->pm_stats.wired_count--; 3222 if (origpte & PG_MANAGED) { 3223 om = PHYS_TO_VM_PAGE(opa); 3224 pmap_remove_entry(pmap, om, va); 3225 } 3226 if (mpte != NULL) { 3227 mpte->wire_count--; 3228 KASSERT(mpte->wire_count > 0, 3229 ("pmap_enter: missing reference to page table page," 3230 " va: 0x%x", va)); 3231 } 3232 } else 3233 pmap->pm_stats.resident_count++; 3234 3235 /* 3236 * Enter on the PV list if part of our managed memory. 3237 */ 3238 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0) { 3239 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva, 3240 ("pmap_enter: managed mapping within the clean submap")); 3241 pmap_insert_entry(pmap, va, m); 3242 pa |= PG_MANAGED; 3243 } 3244 3245 /* 3246 * Increment counters 3247 */ 3248 if (wired) 3249 pmap->pm_stats.wired_count++; 3250 3251validate: 3252 /* 3253 * Now validate mapping with desired protection/wiring. 3254 */ 3255 newpte = (pt_entry_t)(pa | pmap_cache_bits(m->md.pat_mode, 0) | PG_V); 3256 if ((prot & VM_PROT_WRITE) != 0) { 3257 newpte |= PG_RW; 3258 vm_page_flag_set(m, PG_WRITEABLE); 3259 } 3260#ifdef PAE 3261 if ((prot & VM_PROT_EXECUTE) == 0) 3262 newpte |= pg_nx; 3263#endif 3264 if (wired) 3265 newpte |= PG_W; 3266 if (va < VM_MAXUSER_ADDRESS) 3267 newpte |= PG_U; 3268 if (pmap == kernel_pmap) 3269 newpte |= pgeflag; 3270 3271 /* 3272 * if the mapping or permission bits are different, we need 3273 * to update the pte. 3274 */ 3275 if ((origpte & ~(PG_M|PG_A)) != newpte) { 3276 newpte |= PG_A; 3277 if ((access & VM_PROT_WRITE) != 0) 3278 newpte |= PG_M; 3279 if (origpte & PG_V) { 3280 invlva = FALSE; 3281 origpte = pte_load_store(pte, newpte); 3282 if (origpte & PG_A) { 3283 if (origpte & PG_MANAGED) 3284 vm_page_flag_set(om, PG_REFERENCED); 3285 if (opa != VM_PAGE_TO_PHYS(m)) 3286 invlva = TRUE; 3287#ifdef PAE 3288 if ((origpte & PG_NX) == 0 && 3289 (newpte & PG_NX) != 0) 3290 invlva = TRUE; 3291#endif 3292 } 3293 if ((origpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) { 3294 if ((origpte & PG_MANAGED) != 0) 3295 vm_page_dirty(om); 3296 if ((prot & VM_PROT_WRITE) == 0) 3297 invlva = TRUE; 3298 } 3299 if (invlva) 3300 pmap_invalidate_page(pmap, va); 3301 } else 3302 pte_store(pte, newpte); 3303 } 3304 3305 /* 3306 * If both the page table page and the reservation are fully 3307 * populated, then attempt promotion. 3308 */ 3309 if ((mpte == NULL || mpte->wire_count == NPTEPG) && 3310 pg_ps_enabled && vm_reserv_level_iffullpop(m) == 0) 3311 pmap_promote_pde(pmap, pde, va); 3312 3313 sched_unpin(); 3314 vm_page_unlock_queues(); 3315 PMAP_UNLOCK(pmap); 3316} 3317 3318/* 3319 * Tries to create a 2- or 4MB page mapping. Returns TRUE if successful and 3320 * FALSE otherwise. Fails if (1) a page table page cannot be allocated without 3321 * blocking, (2) a mapping already exists at the specified virtual address, or 3322 * (3) a pv entry cannot be allocated without reclaiming another pv entry. 3323 */ 3324static boolean_t 3325pmap_enter_pde(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot) 3326{ 3327 pd_entry_t *pde, newpde; 3328 3329 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 3330 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 3331 pde = pmap_pde(pmap, va); 3332 if (*pde != 0) { 3333 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx" 3334 " in pmap %p", va, pmap); 3335 return (FALSE); 3336 } 3337 newpde = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(m->md.pat_mode, 1) | 3338 PG_PS | PG_V; 3339 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0) { 3340 newpde |= PG_MANAGED; 3341 3342 /* 3343 * Abort this mapping if its PV entry could not be created. 3344 */ 3345 if (!pmap_pv_insert_pde(pmap, va, VM_PAGE_TO_PHYS(m))) { 3346 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx" 3347 " in pmap %p", va, pmap); 3348 return (FALSE); 3349 } 3350 } 3351#ifdef PAE 3352 if ((prot & VM_PROT_EXECUTE) == 0) 3353 newpde |= pg_nx; 3354#endif 3355 if (va < VM_MAXUSER_ADDRESS) 3356 newpde |= PG_U; 3357 3358 /* 3359 * Increment counters. 3360 */ 3361 pmap->pm_stats.resident_count += NBPDR / PAGE_SIZE; 3362 3363 /* 3364 * Map the superpage. 3365 */ 3366 pde_store(pde, newpde); 3367 3368 pmap_pde_mappings++; 3369 CTR2(KTR_PMAP, "pmap_enter_pde: success for va %#lx" 3370 " in pmap %p", va, pmap); 3371 return (TRUE); 3372} 3373 3374/* 3375 * Maps a sequence of resident pages belonging to the same object. 3376 * The sequence begins with the given page m_start. This page is 3377 * mapped at the given virtual address start. Each subsequent page is 3378 * mapped at a virtual address that is offset from start by the same 3379 * amount as the page is offset from m_start within the object. The 3380 * last page in the sequence is the page with the largest offset from 3381 * m_start that can be mapped at a virtual address less than the given 3382 * virtual address end. Not every virtual page between start and end 3383 * is mapped; only those for which a resident page exists with the 3384 * corresponding offset from m_start are mapped. 3385 */ 3386void 3387pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end, 3388 vm_page_t m_start, vm_prot_t prot) 3389{ 3390 vm_offset_t va; 3391 vm_page_t m, mpte; 3392 vm_pindex_t diff, psize; 3393 3394 VM_OBJECT_LOCK_ASSERT(m_start->object, MA_OWNED); 3395 psize = atop(end - start); 3396 mpte = NULL; 3397 m = m_start; 3398 PMAP_LOCK(pmap); 3399 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 3400 va = start + ptoa(diff); 3401 if ((va & PDRMASK) == 0 && va + NBPDR <= end && 3402 (VM_PAGE_TO_PHYS(m) & PDRMASK) == 0 && 3403 pg_ps_enabled && vm_reserv_level_iffullpop(m) == 0 && 3404 pmap_enter_pde(pmap, va, m, prot)) 3405 m = &m[NBPDR / PAGE_SIZE - 1]; 3406 else 3407 mpte = pmap_enter_quick_locked(pmap, va, m, prot, 3408 mpte); 3409 m = TAILQ_NEXT(m, listq); 3410 } 3411 PMAP_UNLOCK(pmap); 3412} 3413 3414/* 3415 * this code makes some *MAJOR* assumptions: 3416 * 1. Current pmap & pmap exists. 3417 * 2. Not wired. 3418 * 3. Read access. 3419 * 4. No page table pages. 3420 * but is *MUCH* faster than pmap_enter... 3421 */ 3422 3423void 3424pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot) 3425{ 3426 3427 PMAP_LOCK(pmap); 3428 (void) pmap_enter_quick_locked(pmap, va, m, prot, NULL); 3429 PMAP_UNLOCK(pmap); 3430} 3431 3432static vm_page_t 3433pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m, 3434 vm_prot_t prot, vm_page_t mpte) 3435{ 3436 pt_entry_t *pte; 3437 vm_paddr_t pa; 3438 vm_page_t free; 3439 3440 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva || 3441 (m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0, 3442 ("pmap_enter_quick_locked: managed mapping within the clean submap")); 3443 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 3444 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 3445 3446 /* 3447 * In the case that a page table page is not 3448 * resident, we are creating it here. 3449 */ 3450 if (va < VM_MAXUSER_ADDRESS) { 3451 unsigned ptepindex; 3452 pd_entry_t ptepa; 3453 3454 /* 3455 * Calculate pagetable page index 3456 */ 3457 ptepindex = va >> PDRSHIFT; 3458 if (mpte && (mpte->pindex == ptepindex)) { 3459 mpte->wire_count++; 3460 } else { 3461 /* 3462 * Get the page directory entry 3463 */ 3464 ptepa = pmap->pm_pdir[ptepindex]; 3465 3466 /* 3467 * If the page table page is mapped, we just increment 3468 * the hold count, and activate it. 3469 */ 3470 if (ptepa) { 3471 if (ptepa & PG_PS) 3472 return (NULL); 3473 mpte = PHYS_TO_VM_PAGE(ptepa & PG_FRAME); 3474 mpte->wire_count++; 3475 } else { 3476 mpte = _pmap_allocpte(pmap, ptepindex, 3477 M_NOWAIT); 3478 if (mpte == NULL) 3479 return (mpte); 3480 } 3481 } 3482 } else { 3483 mpte = NULL; 3484 } 3485 3486 /* 3487 * This call to vtopte makes the assumption that we are 3488 * entering the page into the current pmap. In order to support 3489 * quick entry into any pmap, one would likely use pmap_pte_quick. 3490 * But that isn't as quick as vtopte. 3491 */ 3492 pte = vtopte(va); 3493 if (*pte) { 3494 if (mpte != NULL) { 3495 mpte->wire_count--; 3496 mpte = NULL; 3497 } 3498 return (mpte); 3499 } 3500 3501 /* 3502 * Enter on the PV list if part of our managed memory. 3503 */ 3504 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0 && 3505 !pmap_try_insert_pv_entry(pmap, va, m)) { 3506 if (mpte != NULL) { 3507 free = NULL; 3508 if (pmap_unwire_pte_hold(pmap, mpte, &free)) { 3509 pmap_invalidate_page(pmap, va); 3510 pmap_free_zero_pages(free); 3511 } 3512 3513 mpte = NULL; 3514 } 3515 return (mpte); 3516 } 3517 3518 /* 3519 * Increment counters 3520 */ 3521 pmap->pm_stats.resident_count++; 3522 3523 pa = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(m->md.pat_mode, 0); 3524#ifdef PAE 3525 if ((prot & VM_PROT_EXECUTE) == 0) 3526 pa |= pg_nx; 3527#endif 3528 3529 /* 3530 * Now validate mapping with RO protection 3531 */ 3532 if (m->flags & (PG_FICTITIOUS|PG_UNMANAGED)) 3533 pte_store(pte, pa | PG_V | PG_U); 3534 else 3535 pte_store(pte, pa | PG_V | PG_U | PG_MANAGED); 3536 return mpte; 3537} 3538 3539/* 3540 * Make a temporary mapping for a physical address. This is only intended 3541 * to be used for panic dumps. 3542 */ 3543void * 3544pmap_kenter_temporary(vm_paddr_t pa, int i) 3545{ 3546 vm_offset_t va; 3547 3548 va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE); 3549 pmap_kenter(va, pa); 3550 invlpg(va); 3551 return ((void *)crashdumpmap); 3552} 3553 3554/* 3555 * This code maps large physical mmap regions into the 3556 * processor address space. Note that some shortcuts 3557 * are taken, but the code works. 3558 */ 3559void 3560pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object, 3561 vm_pindex_t pindex, vm_size_t size) 3562{ 3563 pd_entry_t *pde; 3564 vm_paddr_t pa, ptepa; 3565 vm_page_t p; 3566 int pat_mode; 3567 3568 VM_OBJECT_LOCK_ASSERT(object, MA_OWNED); 3569 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG, 3570 ("pmap_object_init_pt: non-device object")); 3571 if (pseflag && 3572 (addr & (NBPDR - 1)) == 0 && (size & (NBPDR - 1)) == 0) { 3573 if (!vm_object_populate(object, pindex, pindex + atop(size))) 3574 return; 3575 p = vm_page_lookup(object, pindex); 3576 KASSERT(p->valid == VM_PAGE_BITS_ALL, 3577 ("pmap_object_init_pt: invalid page %p", p)); 3578 pat_mode = p->md.pat_mode; 3579 3580 /* 3581 * Abort the mapping if the first page is not physically 3582 * aligned to a 2/4MB page boundary. 3583 */ 3584 ptepa = VM_PAGE_TO_PHYS(p); 3585 if (ptepa & (NBPDR - 1)) 3586 return; 3587 3588 /* 3589 * Skip the first page. Abort the mapping if the rest of 3590 * the pages are not physically contiguous or have differing 3591 * memory attributes. 3592 */ 3593 p = TAILQ_NEXT(p, listq); 3594 for (pa = ptepa + PAGE_SIZE; pa < ptepa + size; 3595 pa += PAGE_SIZE) { 3596 KASSERT(p->valid == VM_PAGE_BITS_ALL, 3597 ("pmap_object_init_pt: invalid page %p", p)); 3598 if (pa != VM_PAGE_TO_PHYS(p) || 3599 pat_mode != p->md.pat_mode) 3600 return; 3601 p = TAILQ_NEXT(p, listq); 3602 } 3603 3604 /* 3605 * Map using 2/4MB pages. Since "ptepa" is 2/4M aligned and 3606 * "size" is a multiple of 2/4M, adding the PAT setting to 3607 * "pa" will not affect the termination of this loop. 3608 */ 3609 PMAP_LOCK(pmap); 3610 for (pa = ptepa | pmap_cache_bits(pat_mode, 1); pa < ptepa + 3611 size; pa += NBPDR) { 3612 pde = pmap_pde(pmap, addr); 3613 if (*pde == 0) { 3614 pde_store(pde, pa | PG_PS | PG_M | PG_A | 3615 PG_U | PG_RW | PG_V); 3616 pmap->pm_stats.resident_count += NBPDR / 3617 PAGE_SIZE; 3618 pmap_pde_mappings++; 3619 } 3620 /* Else continue on if the PDE is already valid. */ 3621 addr += NBPDR; 3622 } 3623 PMAP_UNLOCK(pmap); 3624 } 3625} 3626 3627/* 3628 * Routine: pmap_change_wiring 3629 * Function: Change the wiring attribute for a map/virtual-address 3630 * pair. 3631 * In/out conditions: 3632 * The mapping must already exist in the pmap. 3633 */ 3634void 3635pmap_change_wiring(pmap_t pmap, vm_offset_t va, boolean_t wired) 3636{ 3637 pd_entry_t *pde; 3638 pt_entry_t *pte; 3639 boolean_t are_queues_locked; 3640 3641 are_queues_locked = FALSE; 3642retry: 3643 PMAP_LOCK(pmap); 3644 pde = pmap_pde(pmap, va); 3645 if ((*pde & PG_PS) != 0) { 3646 if (!wired != ((*pde & PG_W) == 0)) { 3647 if (!are_queues_locked) { 3648 are_queues_locked = TRUE; 3649 if (!mtx_trylock(&vm_page_queue_mtx)) { 3650 PMAP_UNLOCK(pmap); 3651 vm_page_lock_queues(); 3652 goto retry; 3653 } 3654 } 3655 if (!pmap_demote_pde(pmap, pde, va)) 3656 panic("pmap_change_wiring: demotion failed"); 3657 } else 3658 goto out; 3659 } 3660 pte = pmap_pte(pmap, va); 3661 3662 if (wired && !pmap_pte_w(pte)) 3663 pmap->pm_stats.wired_count++; 3664 else if (!wired && pmap_pte_w(pte)) 3665 pmap->pm_stats.wired_count--; 3666 3667 /* 3668 * Wiring is not a hardware characteristic so there is no need to 3669 * invalidate TLB. 3670 */ 3671 pmap_pte_set_w(pte, wired); 3672 pmap_pte_release(pte); 3673out: 3674 if (are_queues_locked) 3675 vm_page_unlock_queues(); 3676 PMAP_UNLOCK(pmap); 3677} 3678 3679 3680 3681/* 3682 * Copy the range specified by src_addr/len 3683 * from the source map to the range dst_addr/len 3684 * in the destination map. 3685 * 3686 * This routine is only advisory and need not do anything. 3687 */ 3688 3689void 3690pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len, 3691 vm_offset_t src_addr) 3692{ 3693 vm_page_t free; 3694 vm_offset_t addr; 3695 vm_offset_t end_addr = src_addr + len; 3696 vm_offset_t pdnxt; 3697 3698 if (dst_addr != src_addr) 3699 return; 3700 3701 if (!pmap_is_current(src_pmap)) 3702 return; 3703 3704 vm_page_lock_queues(); 3705 if (dst_pmap < src_pmap) { 3706 PMAP_LOCK(dst_pmap); 3707 PMAP_LOCK(src_pmap); 3708 } else { 3709 PMAP_LOCK(src_pmap); 3710 PMAP_LOCK(dst_pmap); 3711 } 3712 sched_pin(); 3713 for (addr = src_addr; addr < end_addr; addr = pdnxt) { 3714 pt_entry_t *src_pte, *dst_pte; 3715 vm_page_t dstmpte, srcmpte; 3716 pd_entry_t srcptepaddr; 3717 unsigned ptepindex; 3718 3719 KASSERT(addr < UPT_MIN_ADDRESS, 3720 ("pmap_copy: invalid to pmap_copy page tables")); 3721 3722 pdnxt = (addr + NBPDR) & ~PDRMASK; 3723 if (pdnxt < addr) 3724 pdnxt = end_addr; 3725 ptepindex = addr >> PDRSHIFT; 3726 3727 srcptepaddr = src_pmap->pm_pdir[ptepindex]; 3728 if (srcptepaddr == 0) 3729 continue; 3730 3731 if (srcptepaddr & PG_PS) { 3732 if (dst_pmap->pm_pdir[ptepindex] == 0 && 3733 ((srcptepaddr & PG_MANAGED) == 0 || 3734 pmap_pv_insert_pde(dst_pmap, addr, srcptepaddr & 3735 PG_PS_FRAME))) { 3736 dst_pmap->pm_pdir[ptepindex] = srcptepaddr & 3737 ~PG_W; 3738 dst_pmap->pm_stats.resident_count += 3739 NBPDR / PAGE_SIZE; 3740 } 3741 continue; 3742 } 3743 3744 srcmpte = PHYS_TO_VM_PAGE(srcptepaddr & PG_FRAME); 3745 KASSERT(srcmpte->wire_count > 0, 3746 ("pmap_copy: source page table page is unused")); 3747 3748 if (pdnxt > end_addr) 3749 pdnxt = end_addr; 3750 3751 src_pte = vtopte(addr); 3752 while (addr < pdnxt) { 3753 pt_entry_t ptetemp; 3754 ptetemp = *src_pte; 3755 /* 3756 * we only virtual copy managed pages 3757 */ 3758 if ((ptetemp & PG_MANAGED) != 0) { 3759 dstmpte = pmap_allocpte(dst_pmap, addr, 3760 M_NOWAIT); 3761 if (dstmpte == NULL) 3762 goto out; 3763 dst_pte = pmap_pte_quick(dst_pmap, addr); 3764 if (*dst_pte == 0 && 3765 pmap_try_insert_pv_entry(dst_pmap, addr, 3766 PHYS_TO_VM_PAGE(ptetemp & PG_FRAME))) { 3767 /* 3768 * Clear the wired, modified, and 3769 * accessed (referenced) bits 3770 * during the copy. 3771 */ 3772 *dst_pte = ptetemp & ~(PG_W | PG_M | 3773 PG_A); 3774 dst_pmap->pm_stats.resident_count++; 3775 } else { 3776 free = NULL; 3777 if (pmap_unwire_pte_hold(dst_pmap, 3778 dstmpte, &free)) { 3779 pmap_invalidate_page(dst_pmap, 3780 addr); 3781 pmap_free_zero_pages(free); 3782 } 3783 goto out; 3784 } 3785 if (dstmpte->wire_count >= srcmpte->wire_count) 3786 break; 3787 } 3788 addr += PAGE_SIZE; 3789 src_pte++; 3790 } 3791 } 3792out: 3793 sched_unpin(); 3794 vm_page_unlock_queues(); 3795 PMAP_UNLOCK(src_pmap); 3796 PMAP_UNLOCK(dst_pmap); 3797} 3798 3799static __inline void 3800pagezero(void *page) 3801{ 3802#if defined(I686_CPU) 3803 if (cpu_class == CPUCLASS_686) { 3804#if defined(CPU_ENABLE_SSE) 3805 if (cpu_feature & CPUID_SSE2) 3806 sse2_pagezero(page); 3807 else 3808#endif 3809 i686_pagezero(page); 3810 } else 3811#endif 3812 bzero(page, PAGE_SIZE); 3813} 3814 3815/* 3816 * pmap_zero_page zeros the specified hardware page by mapping 3817 * the page into KVM and using bzero to clear its contents. 3818 */ 3819void 3820pmap_zero_page(vm_page_t m) 3821{ 3822 struct sysmaps *sysmaps; 3823 3824 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)]; 3825 mtx_lock(&sysmaps->lock); 3826 if (*sysmaps->CMAP2) 3827 panic("pmap_zero_page: CMAP2 busy"); 3828 sched_pin(); 3829 *sysmaps->CMAP2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M | 3830 pmap_cache_bits(m->md.pat_mode, 0); 3831 invlcaddr(sysmaps->CADDR2); 3832 pagezero(sysmaps->CADDR2); 3833 *sysmaps->CMAP2 = 0; 3834 sched_unpin(); 3835 mtx_unlock(&sysmaps->lock); 3836} 3837 3838/* 3839 * pmap_zero_page_area zeros the specified hardware page by mapping 3840 * the page into KVM and using bzero to clear its contents. 3841 * 3842 * off and size may not cover an area beyond a single hardware page. 3843 */ 3844void 3845pmap_zero_page_area(vm_page_t m, int off, int size) 3846{ 3847 struct sysmaps *sysmaps; 3848 3849 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)]; 3850 mtx_lock(&sysmaps->lock); 3851 if (*sysmaps->CMAP2) 3852 panic("pmap_zero_page_area: CMAP2 busy"); 3853 sched_pin(); 3854 *sysmaps->CMAP2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M | 3855 pmap_cache_bits(m->md.pat_mode, 0); 3856 invlcaddr(sysmaps->CADDR2); 3857 if (off == 0 && size == PAGE_SIZE) 3858 pagezero(sysmaps->CADDR2); 3859 else 3860 bzero((char *)sysmaps->CADDR2 + off, size); 3861 *sysmaps->CMAP2 = 0; 3862 sched_unpin(); 3863 mtx_unlock(&sysmaps->lock); 3864} 3865 3866/* 3867 * pmap_zero_page_idle zeros the specified hardware page by mapping 3868 * the page into KVM and using bzero to clear its contents. This 3869 * is intended to be called from the vm_pagezero process only and 3870 * outside of Giant. 3871 */ 3872void 3873pmap_zero_page_idle(vm_page_t m) 3874{ 3875 3876 if (*CMAP3) 3877 panic("pmap_zero_page_idle: CMAP3 busy"); 3878 sched_pin(); 3879 *CMAP3 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M | 3880 pmap_cache_bits(m->md.pat_mode, 0); 3881 invlcaddr(CADDR3); 3882 pagezero(CADDR3); 3883 *CMAP3 = 0; 3884 sched_unpin(); 3885} 3886 3887/* 3888 * pmap_copy_page copies the specified (machine independent) 3889 * page by mapping the page into virtual memory and using 3890 * bcopy to copy the page, one machine dependent page at a 3891 * time. 3892 */ 3893void 3894pmap_copy_page(vm_page_t src, vm_page_t dst) 3895{ 3896 struct sysmaps *sysmaps; 3897 3898 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)]; 3899 mtx_lock(&sysmaps->lock); 3900 if (*sysmaps->CMAP1) 3901 panic("pmap_copy_page: CMAP1 busy"); 3902 if (*sysmaps->CMAP2) 3903 panic("pmap_copy_page: CMAP2 busy"); 3904 sched_pin(); 3905 invlpg((u_int)sysmaps->CADDR1); 3906 invlpg((u_int)sysmaps->CADDR2); 3907 *sysmaps->CMAP1 = PG_V | VM_PAGE_TO_PHYS(src) | PG_A | 3908 pmap_cache_bits(src->md.pat_mode, 0); 3909 *sysmaps->CMAP2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(dst) | PG_A | PG_M | 3910 pmap_cache_bits(dst->md.pat_mode, 0); 3911 bcopy(sysmaps->CADDR1, sysmaps->CADDR2, PAGE_SIZE); 3912 *sysmaps->CMAP1 = 0; 3913 *sysmaps->CMAP2 = 0; 3914 sched_unpin(); 3915 mtx_unlock(&sysmaps->lock); 3916} 3917 3918/* 3919 * Returns true if the pmap's pv is one of the first 3920 * 16 pvs linked to from this page. This count may 3921 * be changed upwards or downwards in the future; it 3922 * is only necessary that true be returned for a small 3923 * subset of pmaps for proper page aging. 3924 */ 3925boolean_t 3926pmap_page_exists_quick(pmap_t pmap, vm_page_t m) 3927{ 3928 struct md_page *pvh; 3929 pv_entry_t pv; 3930 int loops = 0; 3931 3932 if (m->flags & PG_FICTITIOUS) 3933 return FALSE; 3934 3935 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 3936 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 3937 if (PV_PMAP(pv) == pmap) { 3938 return TRUE; 3939 } 3940 loops++; 3941 if (loops >= 16) 3942 break; 3943 } 3944 if (loops < 16) { 3945 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 3946 TAILQ_FOREACH(pv, &pvh->pv_list, pv_list) { 3947 if (PV_PMAP(pv) == pmap) 3948 return (TRUE); 3949 loops++; 3950 if (loops >= 16) 3951 break; 3952 } 3953 } 3954 return (FALSE); 3955} 3956 3957/* 3958 * pmap_page_wired_mappings: 3959 * 3960 * Return the number of managed mappings to the given physical page 3961 * that are wired. 3962 */ 3963int 3964pmap_page_wired_mappings(vm_page_t m) 3965{ 3966 int count; 3967 3968 count = 0; 3969 if ((m->flags & PG_FICTITIOUS) != 0) 3970 return (count); 3971 count = pmap_pvh_wired_mappings(&m->md, count); 3972 return (pmap_pvh_wired_mappings(pa_to_pvh(VM_PAGE_TO_PHYS(m)), count)); 3973} 3974 3975/* 3976 * pmap_pvh_wired_mappings: 3977 * 3978 * Return the updated number "count" of managed mappings that are wired. 3979 */ 3980static int 3981pmap_pvh_wired_mappings(struct md_page *pvh, int count) 3982{ 3983 pmap_t pmap; 3984 pt_entry_t *pte; 3985 pv_entry_t pv; 3986 3987 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 3988 sched_pin(); 3989 TAILQ_FOREACH(pv, &pvh->pv_list, pv_list) { 3990 pmap = PV_PMAP(pv); 3991 PMAP_LOCK(pmap); 3992 pte = pmap_pte_quick(pmap, pv->pv_va); 3993 if ((*pte & PG_W) != 0) 3994 count++; 3995 PMAP_UNLOCK(pmap); 3996 } 3997 sched_unpin(); 3998 return (count); 3999} 4000 4001/* 4002 * Returns TRUE if the given page is mapped individually or as part of 4003 * a 4mpage. Otherwise, returns FALSE. 4004 */ 4005boolean_t 4006pmap_page_is_mapped(vm_page_t m) 4007{ 4008 struct md_page *pvh; 4009 4010 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0) 4011 return (FALSE); 4012 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 4013 if (TAILQ_EMPTY(&m->md.pv_list)) { 4014 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 4015 return (!TAILQ_EMPTY(&pvh->pv_list)); 4016 } else 4017 return (TRUE); 4018} 4019 4020/* 4021 * Remove all pages from specified address space 4022 * this aids process exit speeds. Also, this code 4023 * is special cased for current process only, but 4024 * can have the more generic (and slightly slower) 4025 * mode enabled. This is much faster than pmap_remove 4026 * in the case of running down an entire address space. 4027 */ 4028void 4029pmap_remove_pages(pmap_t pmap) 4030{ 4031 pt_entry_t *pte, tpte; 4032 vm_page_t free = NULL; 4033 vm_page_t m, mpte, mt; 4034 pv_entry_t pv; 4035 struct md_page *pvh; 4036 struct pv_chunk *pc, *npc; 4037 int field, idx; 4038 int32_t bit; 4039 uint32_t inuse, bitmask; 4040 int allfree; 4041 4042 if (pmap != vmspace_pmap(curthread->td_proc->p_vmspace)) { 4043 printf("warning: pmap_remove_pages called with non-current pmap\n"); 4044 return; 4045 } 4046 vm_page_lock_queues(); 4047 PMAP_LOCK(pmap); 4048 sched_pin(); 4049 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) { 4050 allfree = 1; 4051 for (field = 0; field < _NPCM; field++) { 4052 inuse = (~(pc->pc_map[field])) & pc_freemask[field]; 4053 while (inuse != 0) { 4054 bit = bsfl(inuse); 4055 bitmask = 1UL << bit; 4056 idx = field * 32 + bit; 4057 pv = &pc->pc_pventry[idx]; 4058 inuse &= ~bitmask; 4059 4060 pte = pmap_pde(pmap, pv->pv_va); 4061 tpte = *pte; 4062 if ((tpte & PG_PS) == 0) { 4063 pte = vtopte(pv->pv_va); 4064 tpte = *pte & ~PG_PTE_PAT; 4065 } 4066 4067 if (tpte == 0) { 4068 printf( 4069 "TPTE at %p IS ZERO @ VA %08x\n", 4070 pte, pv->pv_va); 4071 panic("bad pte"); 4072 } 4073 4074/* 4075 * We cannot remove wired pages from a process' mapping at this time 4076 */ 4077 if (tpte & PG_W) { 4078 allfree = 0; 4079 continue; 4080 } 4081 4082 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME); 4083 KASSERT(m->phys_addr == (tpte & PG_FRAME), 4084 ("vm_page_t %p phys_addr mismatch %016jx %016jx", 4085 m, (uintmax_t)m->phys_addr, 4086 (uintmax_t)tpte)); 4087 4088 KASSERT(m < &vm_page_array[vm_page_array_size], 4089 ("pmap_remove_pages: bad tpte %#jx", 4090 (uintmax_t)tpte)); 4091 4092 pte_clear(pte); 4093 4094 /* 4095 * Update the vm_page_t clean/reference bits. 4096 */ 4097 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) { 4098 if ((tpte & PG_PS) != 0) { 4099 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++) 4100 vm_page_dirty(mt); 4101 } else 4102 vm_page_dirty(m); 4103 } 4104 4105 /* Mark free */ 4106 PV_STAT(pv_entry_frees++); 4107 PV_STAT(pv_entry_spare++); 4108 pv_entry_count--; 4109 pc->pc_map[field] |= bitmask; 4110 if ((tpte & PG_PS) != 0) { 4111 pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE; 4112 pvh = pa_to_pvh(tpte & PG_PS_FRAME); 4113 TAILQ_REMOVE(&pvh->pv_list, pv, pv_list); 4114 if (TAILQ_EMPTY(&pvh->pv_list)) { 4115 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++) 4116 if (TAILQ_EMPTY(&mt->md.pv_list)) 4117 vm_page_flag_clear(mt, PG_WRITEABLE); 4118 } 4119 mpte = pmap_lookup_pt_page(pmap, pv->pv_va); 4120 if (mpte != NULL) { 4121 pmap_remove_pt_page(pmap, mpte); 4122 pmap->pm_stats.resident_count--; 4123 KASSERT(mpte->wire_count == NPTEPG, 4124 ("pmap_remove_pages: pte page wire count error")); 4125 mpte->wire_count = 0; 4126 pmap_add_delayed_free_list(mpte, &free, FALSE); 4127 atomic_subtract_int(&cnt.v_wire_count, 1); 4128 } 4129 } else { 4130 pmap->pm_stats.resident_count--; 4131 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list); 4132 if (TAILQ_EMPTY(&m->md.pv_list)) { 4133 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 4134 if (TAILQ_EMPTY(&pvh->pv_list)) 4135 vm_page_flag_clear(m, PG_WRITEABLE); 4136 } 4137 pmap_unuse_pt(pmap, pv->pv_va, &free); 4138 } 4139 } 4140 } 4141 if (allfree) { 4142 PV_STAT(pv_entry_spare -= _NPCPV); 4143 PV_STAT(pc_chunk_count--); 4144 PV_STAT(pc_chunk_frees++); 4145 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 4146 m = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc)); 4147 pmap_qremove((vm_offset_t)pc, 1); 4148 vm_page_unwire(m, 0); 4149 vm_page_free(m); 4150 pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc); 4151 } 4152 } 4153 sched_unpin(); 4154 pmap_invalidate_all(pmap); 4155 vm_page_unlock_queues(); 4156 PMAP_UNLOCK(pmap); 4157 pmap_free_zero_pages(free); 4158} 4159 4160/* 4161 * pmap_is_modified: 4162 * 4163 * Return whether or not the specified physical page was modified 4164 * in any physical maps. 4165 */ 4166boolean_t 4167pmap_is_modified(vm_page_t m) 4168{ 4169 4170 if (m->flags & PG_FICTITIOUS) 4171 return (FALSE); 4172 if (pmap_is_modified_pvh(&m->md)) 4173 return (TRUE); 4174 return (pmap_is_modified_pvh(pa_to_pvh(VM_PAGE_TO_PHYS(m)))); 4175} 4176 4177/* 4178 * Returns TRUE if any of the given mappings were used to modify 4179 * physical memory. Otherwise, returns FALSE. Both page and 2mpage 4180 * mappings are supported. 4181 */ 4182static boolean_t 4183pmap_is_modified_pvh(struct md_page *pvh) 4184{ 4185 pv_entry_t pv; 4186 pt_entry_t *pte; 4187 pmap_t pmap; 4188 boolean_t rv; 4189 4190 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 4191 rv = FALSE; 4192 sched_pin(); 4193 TAILQ_FOREACH(pv, &pvh->pv_list, pv_list) { 4194 pmap = PV_PMAP(pv); 4195 PMAP_LOCK(pmap); 4196 pte = pmap_pte_quick(pmap, pv->pv_va); 4197 rv = (*pte & (PG_M | PG_RW)) == (PG_M | PG_RW); 4198 PMAP_UNLOCK(pmap); 4199 if (rv) 4200 break; 4201 } 4202 sched_unpin(); 4203 return (rv); 4204} 4205 4206/* 4207 * pmap_is_prefaultable: 4208 * 4209 * Return whether or not the specified virtual address is elgible 4210 * for prefault. 4211 */ 4212boolean_t 4213pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr) 4214{ 4215 pd_entry_t *pde; 4216 pt_entry_t *pte; 4217 boolean_t rv; 4218 4219 rv = FALSE; 4220 PMAP_LOCK(pmap); 4221 pde = pmap_pde(pmap, addr); 4222 if (*pde != 0 && (*pde & PG_PS) == 0) { 4223 pte = vtopte(addr); 4224 rv = *pte == 0; 4225 } 4226 PMAP_UNLOCK(pmap); 4227 return (rv); 4228} 4229 4230/* 4231 * Clear the write and modified bits in each of the given page's mappings. 4232 */ 4233void 4234pmap_remove_write(vm_page_t m) 4235{ 4236 struct md_page *pvh; 4237 pv_entry_t next_pv, pv; 4238 pmap_t pmap; 4239 pd_entry_t *pde; 4240 pt_entry_t oldpte, *pte; 4241 vm_offset_t va; 4242 4243 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 4244 if ((m->flags & PG_FICTITIOUS) != 0 || 4245 (m->flags & PG_WRITEABLE) == 0) 4246 return; 4247 sched_pin(); 4248 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 4249 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_list, next_pv) { 4250 va = pv->pv_va; 4251 pmap = PV_PMAP(pv); 4252 PMAP_LOCK(pmap); 4253 pde = pmap_pde(pmap, va); 4254 if ((*pde & PG_RW) != 0) 4255 (void)pmap_demote_pde(pmap, pde, va); 4256 PMAP_UNLOCK(pmap); 4257 } 4258 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 4259 pmap = PV_PMAP(pv); 4260 PMAP_LOCK(pmap); 4261 pde = pmap_pde(pmap, pv->pv_va); 4262 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_write: found" 4263 " a 4mpage in page %p's pv list", m)); 4264 pte = pmap_pte_quick(pmap, pv->pv_va); 4265retry: 4266 oldpte = *pte; 4267 if ((oldpte & PG_RW) != 0) { 4268 /* 4269 * Regardless of whether a pte is 32 or 64 bits 4270 * in size, PG_RW and PG_M are among the least 4271 * significant 32 bits. 4272 */ 4273 if (!atomic_cmpset_int((u_int *)pte, oldpte, 4274 oldpte & ~(PG_RW | PG_M))) 4275 goto retry; 4276 if ((oldpte & PG_M) != 0) 4277 vm_page_dirty(m); 4278 pmap_invalidate_page(pmap, pv->pv_va); 4279 } 4280 PMAP_UNLOCK(pmap); 4281 } 4282 vm_page_flag_clear(m, PG_WRITEABLE); 4283 sched_unpin(); 4284} 4285 4286/* 4287 * pmap_ts_referenced: 4288 * 4289 * Return a count of reference bits for a page, clearing those bits. 4290 * It is not necessary for every reference bit to be cleared, but it 4291 * is necessary that 0 only be returned when there are truly no 4292 * reference bits set. 4293 * 4294 * XXX: The exact number of bits to check and clear is a matter that 4295 * should be tested and standardized at some point in the future for 4296 * optimal aging of shared pages. 4297 */ 4298int 4299pmap_ts_referenced(vm_page_t m) 4300{ 4301 struct md_page *pvh; 4302 pv_entry_t pv, pvf, pvn; 4303 pmap_t pmap; 4304 pd_entry_t oldpde, *pde; 4305 pt_entry_t *pte; 4306 vm_offset_t va; 4307 int rtval = 0; 4308 4309 if (m->flags & PG_FICTITIOUS) 4310 return (rtval); 4311 sched_pin(); 4312 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 4313 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 4314 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_list, pvn) { 4315 va = pv->pv_va; 4316 pmap = PV_PMAP(pv); 4317 PMAP_LOCK(pmap); 4318 pde = pmap_pde(pmap, va); 4319 oldpde = *pde; 4320 if ((oldpde & PG_A) != 0) { 4321 if (pmap_demote_pde(pmap, pde, va)) { 4322 if ((oldpde & PG_W) == 0) { 4323 /* 4324 * Remove the mapping to a single page 4325 * so that a subsequent access may 4326 * repromote. Since the underlying 4327 * page table page is fully populated, 4328 * this removal never frees a page 4329 * table page. 4330 */ 4331 va += VM_PAGE_TO_PHYS(m) - (oldpde & 4332 PG_PS_FRAME); 4333 pmap_remove_page(pmap, va, NULL); 4334 rtval++; 4335 if (rtval > 4) { 4336 PMAP_UNLOCK(pmap); 4337 return (rtval); 4338 } 4339 } 4340 } 4341 } 4342 PMAP_UNLOCK(pmap); 4343 } 4344 if ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) { 4345 pvf = pv; 4346 do { 4347 pvn = TAILQ_NEXT(pv, pv_list); 4348 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list); 4349 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list); 4350 pmap = PV_PMAP(pv); 4351 PMAP_LOCK(pmap); 4352 pde = pmap_pde(pmap, pv->pv_va); 4353 KASSERT((*pde & PG_PS) == 0, ("pmap_ts_referenced:" 4354 " found a 4mpage in page %p's pv list", m)); 4355 pte = pmap_pte_quick(pmap, pv->pv_va); 4356 if ((*pte & PG_A) != 0) { 4357 atomic_clear_int((u_int *)pte, PG_A); 4358 pmap_invalidate_page(pmap, pv->pv_va); 4359 rtval++; 4360 if (rtval > 4) 4361 pvn = NULL; 4362 } 4363 PMAP_UNLOCK(pmap); 4364 } while ((pv = pvn) != NULL && pv != pvf); 4365 } 4366 sched_unpin(); 4367 return (rtval); 4368} 4369 4370/* 4371 * Clear the modify bits on the specified physical page. 4372 */ 4373void 4374pmap_clear_modify(vm_page_t m) 4375{ 4376 struct md_page *pvh; 4377 pv_entry_t next_pv, pv; 4378 pmap_t pmap; 4379 pd_entry_t oldpde, *pde; 4380 pt_entry_t oldpte, *pte; 4381 vm_offset_t va; 4382 4383 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 4384 if ((m->flags & PG_FICTITIOUS) != 0) 4385 return; 4386 sched_pin(); 4387 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 4388 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_list, next_pv) { 4389 va = pv->pv_va; 4390 pmap = PV_PMAP(pv); 4391 PMAP_LOCK(pmap); 4392 pde = pmap_pde(pmap, va); 4393 oldpde = *pde; 4394 if ((oldpde & PG_RW) != 0) { 4395 if (pmap_demote_pde(pmap, pde, va)) { 4396 if ((oldpde & PG_W) == 0) { 4397 /* 4398 * Write protect the mapping to a 4399 * single page so that a subsequent 4400 * write access may repromote. 4401 */ 4402 va += VM_PAGE_TO_PHYS(m) - (oldpde & 4403 PG_PS_FRAME); 4404 pte = pmap_pte_quick(pmap, va); 4405 oldpte = *pte; 4406 if ((oldpte & PG_V) != 0) { 4407 /* 4408 * Regardless of whether a pte is 32 or 64 bits 4409 * in size, PG_RW and PG_M are among the least 4410 * significant 32 bits. 4411 */ 4412 while (!atomic_cmpset_int((u_int *)pte, 4413 oldpte, 4414 oldpte & ~(PG_M | PG_RW))) 4415 oldpte = *pte; 4416 vm_page_dirty(m); 4417 pmap_invalidate_page(pmap, va); 4418 } 4419 } 4420 } 4421 } 4422 PMAP_UNLOCK(pmap); 4423 } 4424 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 4425 pmap = PV_PMAP(pv); 4426 PMAP_LOCK(pmap); 4427 pde = pmap_pde(pmap, pv->pv_va); 4428 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_modify: found" 4429 " a 4mpage in page %p's pv list", m)); 4430 pte = pmap_pte_quick(pmap, pv->pv_va); 4431 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) { 4432 /* 4433 * Regardless of whether a pte is 32 or 64 bits 4434 * in size, PG_M is among the least significant 4435 * 32 bits. 4436 */ 4437 atomic_clear_int((u_int *)pte, PG_M); 4438 pmap_invalidate_page(pmap, pv->pv_va); 4439 } 4440 PMAP_UNLOCK(pmap); 4441 } 4442 sched_unpin(); 4443} 4444 4445/* 4446 * pmap_clear_reference: 4447 * 4448 * Clear the reference bit on the specified physical page. 4449 */ 4450void 4451pmap_clear_reference(vm_page_t m) 4452{ 4453 struct md_page *pvh; 4454 pv_entry_t next_pv, pv; 4455 pmap_t pmap; 4456 pd_entry_t oldpde, *pde; 4457 pt_entry_t *pte; 4458 vm_offset_t va; 4459 4460 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 4461 if ((m->flags & PG_FICTITIOUS) != 0) 4462 return; 4463 sched_pin(); 4464 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 4465 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_list, next_pv) { 4466 va = pv->pv_va; 4467 pmap = PV_PMAP(pv); 4468 PMAP_LOCK(pmap); 4469 pde = pmap_pde(pmap, va); 4470 oldpde = *pde; 4471 if ((oldpde & PG_A) != 0) { 4472 if (pmap_demote_pde(pmap, pde, va)) { 4473 /* 4474 * Remove the mapping to a single page so 4475 * that a subsequent access may repromote. 4476 * Since the underlying page table page is 4477 * fully populated, this removal never frees 4478 * a page table page. 4479 */ 4480 va += VM_PAGE_TO_PHYS(m) - (oldpde & 4481 PG_PS_FRAME); 4482 pmap_remove_page(pmap, va, NULL); 4483 } 4484 } 4485 PMAP_UNLOCK(pmap); 4486 } 4487 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 4488 pmap = PV_PMAP(pv); 4489 PMAP_LOCK(pmap); 4490 pde = pmap_pde(pmap, pv->pv_va); 4491 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_reference: found" 4492 " a 4mpage in page %p's pv list", m)); 4493 pte = pmap_pte_quick(pmap, pv->pv_va); 4494 if ((*pte & PG_A) != 0) { 4495 /* 4496 * Regardless of whether a pte is 32 or 64 bits 4497 * in size, PG_A is among the least significant 4498 * 32 bits. 4499 */ 4500 atomic_clear_int((u_int *)pte, PG_A); 4501 pmap_invalidate_page(pmap, pv->pv_va); 4502 } 4503 PMAP_UNLOCK(pmap); 4504 } 4505 sched_unpin(); 4506} 4507 4508/* 4509 * Miscellaneous support routines follow 4510 */ 4511 4512/* Adjust the cache mode for a 4KB page mapped via a PTE. */ 4513static __inline void 4514pmap_pte_attr(pt_entry_t *pte, int cache_bits) 4515{ 4516 u_int opte, npte; 4517 4518 /* 4519 * The cache mode bits are all in the low 32-bits of the 4520 * PTE, so we can just spin on updating the low 32-bits. 4521 */ 4522 do { 4523 opte = *(u_int *)pte; 4524 npte = opte & ~PG_PTE_CACHE; 4525 npte |= cache_bits; 4526 } while (npte != opte && !atomic_cmpset_int((u_int *)pte, opte, npte)); 4527} 4528 4529/* Adjust the cache mode for a 2/4MB page mapped via a PDE. */ 4530static __inline void 4531pmap_pde_attr(pd_entry_t *pde, int cache_bits) 4532{ 4533 u_int opde, npde; 4534 4535 /* 4536 * The cache mode bits are all in the low 32-bits of the 4537 * PDE, so we can just spin on updating the low 32-bits. 4538 */ 4539 do { 4540 opde = *(u_int *)pde; 4541 npde = opde & ~PG_PDE_CACHE; 4542 npde |= cache_bits; 4543 } while (npde != opde && !atomic_cmpset_int((u_int *)pde, opde, npde)); 4544} 4545 4546/* 4547 * Map a set of physical memory pages into the kernel virtual 4548 * address space. Return a pointer to where it is mapped. This 4549 * routine is intended to be used for mapping device memory, 4550 * NOT real memory. 4551 */ 4552void * 4553pmap_mapdev_attr(vm_paddr_t pa, vm_size_t size, int mode) 4554{ 4555 vm_offset_t va, offset; 4556 vm_size_t tmpsize; 4557 4558 offset = pa & PAGE_MASK; 4559 size = roundup(offset + size, PAGE_SIZE); 4560 pa = pa & PG_FRAME; 4561 4562 if (pa < KERNLOAD && pa + size <= KERNLOAD) 4563 va = KERNBASE + pa; 4564 else 4565 va = kmem_alloc_nofault(kernel_map, size); 4566 if (!va) 4567 panic("pmap_mapdev: Couldn't alloc kernel virtual memory"); 4568 4569 for (tmpsize = 0; tmpsize < size; tmpsize += PAGE_SIZE) 4570 pmap_kenter_attr(va + tmpsize, pa + tmpsize, mode); 4571 pmap_invalidate_range(kernel_pmap, va, va + tmpsize); 4572 pmap_invalidate_cache_range(va, va + size); 4573 return ((void *)(va + offset)); 4574} 4575 4576void * 4577pmap_mapdev(vm_paddr_t pa, vm_size_t size) 4578{ 4579 4580 return (pmap_mapdev_attr(pa, size, PAT_UNCACHEABLE)); 4581} 4582 4583void * 4584pmap_mapbios(vm_paddr_t pa, vm_size_t size) 4585{ 4586 4587 return (pmap_mapdev_attr(pa, size, PAT_WRITE_BACK)); 4588} 4589 4590void 4591pmap_unmapdev(vm_offset_t va, vm_size_t size) 4592{ 4593 vm_offset_t base, offset, tmpva; 4594 4595 if (va >= KERNBASE && va + size <= KERNBASE + KERNLOAD) 4596 return; 4597 base = trunc_page(va); 4598 offset = va & PAGE_MASK; 4599 size = roundup(offset + size, PAGE_SIZE); 4600 for (tmpva = base; tmpva < (base + size); tmpva += PAGE_SIZE) 4601 pmap_kremove(tmpva); 4602 pmap_invalidate_range(kernel_pmap, va, tmpva); 4603 kmem_free(kernel_map, base, size); 4604} 4605 4606/* 4607 * Sets the memory attribute for the specified page. 4608 */ 4609void 4610pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma) 4611{ 4612 struct sysmaps *sysmaps; 4613 vm_offset_t sva, eva; 4614 4615 m->md.pat_mode = ma; 4616 if ((m->flags & PG_FICTITIOUS) != 0) 4617 return; 4618 4619 /* 4620 * If "m" is a normal page, flush it from the cache. 4621 * See pmap_invalidate_cache_range(). 4622 * 4623 * First, try to find an existing mapping of the page by sf 4624 * buffer. sf_buf_invalidate_cache() modifies mapping and 4625 * flushes the cache. 4626 */ 4627 if (sf_buf_invalidate_cache(m)) 4628 return; 4629 4630 /* 4631 * If page is not mapped by sf buffer, but CPU does not 4632 * support self snoop, map the page transient and do 4633 * invalidation. In the worst case, whole cache is flushed by 4634 * pmap_invalidate_cache_range(). 4635 */ 4636 if ((cpu_feature & (CPUID_SS|CPUID_CLFSH)) == CPUID_CLFSH) { 4637 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)]; 4638 mtx_lock(&sysmaps->lock); 4639 if (*sysmaps->CMAP2) 4640 panic("pmap_page_set_memattr: CMAP2 busy"); 4641 sched_pin(); 4642 *sysmaps->CMAP2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | 4643 PG_A | PG_M | pmap_cache_bits(m->md.pat_mode, 0); 4644 invlcaddr(sysmaps->CADDR2); 4645 sva = (vm_offset_t)sysmaps->CADDR2; 4646 eva = sva + PAGE_SIZE; 4647 } else 4648 sva = eva = 0; /* gcc */ 4649 pmap_invalidate_cache_range(sva, eva); 4650 if (sva != 0) { 4651 *sysmaps->CMAP2 = 0; 4652 sched_unpin(); 4653 mtx_unlock(&sysmaps->lock); 4654 } 4655} 4656 4657/* 4658 * Changes the specified virtual address range's memory type to that given by 4659 * the parameter "mode". The specified virtual address range must be 4660 * completely contained within either the kernel map. 4661 * 4662 * Returns zero if the change completed successfully, and either EINVAL or 4663 * ENOMEM if the change failed. Specifically, EINVAL is returned if some part 4664 * of the virtual address range was not mapped, and ENOMEM is returned if 4665 * there was insufficient memory available to complete the change. 4666 */ 4667int 4668pmap_change_attr(vm_offset_t va, vm_size_t size, int mode) 4669{ 4670 vm_offset_t base, offset, tmpva; 4671 pd_entry_t *pde; 4672 pt_entry_t *pte; 4673 int cache_bits_pte, cache_bits_pde; 4674 boolean_t changed; 4675 4676 base = trunc_page(va); 4677 offset = va & PAGE_MASK; 4678 size = roundup(offset + size, PAGE_SIZE); 4679 4680 /* 4681 * Only supported on kernel virtual addresses above the recursive map. 4682 */ 4683 if (base < VM_MIN_KERNEL_ADDRESS) 4684 return (EINVAL); 4685 4686 cache_bits_pde = pmap_cache_bits(mode, 1); 4687 cache_bits_pte = pmap_cache_bits(mode, 0); 4688 changed = FALSE; 4689 4690 /* 4691 * Pages that aren't mapped aren't supported. Also break down 4692 * 2/4MB pages into 4KB pages if required. 4693 */ 4694 PMAP_LOCK(kernel_pmap); 4695 for (tmpva = base; tmpva < base + size; ) { 4696 pde = pmap_pde(kernel_pmap, tmpva); 4697 if (*pde == 0) { 4698 PMAP_UNLOCK(kernel_pmap); 4699 return (EINVAL); 4700 } 4701 if (*pde & PG_PS) { 4702 /* 4703 * If the current 2/4MB page already has 4704 * the required memory type, then we need not 4705 * demote this page. Just increment tmpva to 4706 * the next 2/4MB page frame. 4707 */ 4708 if ((*pde & PG_PDE_CACHE) == cache_bits_pde) { 4709 tmpva = trunc_4mpage(tmpva) + NBPDR; 4710 continue; 4711 } 4712 4713 /* 4714 * If the current offset aligns with a 2/4MB 4715 * page frame and there is at least 2/4MB left 4716 * within the range, then we need not break 4717 * down this page into 4KB pages. 4718 */ 4719 if ((tmpva & PDRMASK) == 0 && 4720 tmpva + PDRMASK < base + size) { 4721 tmpva += NBPDR; 4722 continue; 4723 } 4724 if (!pmap_demote_pde(kernel_pmap, pde, tmpva)) { 4725 PMAP_UNLOCK(kernel_pmap); 4726 return (ENOMEM); 4727 } 4728 } 4729 pte = vtopte(tmpva); 4730 if (*pte == 0) { 4731 PMAP_UNLOCK(kernel_pmap); 4732 return (EINVAL); 4733 } 4734 tmpva += PAGE_SIZE; 4735 } 4736 PMAP_UNLOCK(kernel_pmap); 4737 4738 /* 4739 * Ok, all the pages exist, so run through them updating their 4740 * cache mode if required. 4741 */ 4742 for (tmpva = base; tmpva < base + size; ) { 4743 pde = pmap_pde(kernel_pmap, tmpva); 4744 if (*pde & PG_PS) { 4745 if ((*pde & PG_PDE_CACHE) != cache_bits_pde) { 4746 pmap_pde_attr(pde, cache_bits_pde); 4747 changed = TRUE; 4748 } 4749 tmpva = trunc_4mpage(tmpva) + NBPDR; 4750 } else { 4751 pte = vtopte(tmpva); 4752 if ((*pte & PG_PTE_CACHE) != cache_bits_pte) { 4753 pmap_pte_attr(pte, cache_bits_pte); 4754 changed = TRUE; 4755 } 4756 tmpva += PAGE_SIZE; 4757 } 4758 } 4759 4760 /* 4761 * Flush CPU caches to make sure any data isn't cached that 4762 * shouldn't be, etc. 4763 */ 4764 if (changed) { 4765 pmap_invalidate_range(kernel_pmap, base, tmpva); 4766 pmap_invalidate_cache_range(base, tmpva); 4767 } 4768 return (0); 4769} 4770 4771/* 4772 * perform the pmap work for mincore 4773 */ 4774int 4775pmap_mincore(pmap_t pmap, vm_offset_t addr) 4776{ 4777 pd_entry_t *pdep; 4778 pt_entry_t *ptep, pte; 4779 vm_paddr_t pa; 4780 vm_page_t m; 4781 int val = 0; 4782 4783 PMAP_LOCK(pmap); 4784 pdep = pmap_pde(pmap, addr); 4785 if (*pdep != 0) { 4786 if (*pdep & PG_PS) { 4787 pte = *pdep; 4788 val = MINCORE_SUPER; 4789 /* Compute the physical address of the 4KB page. */ 4790 pa = ((*pdep & PG_PS_FRAME) | (addr & PDRMASK)) & 4791 PG_FRAME; 4792 } else { 4793 ptep = pmap_pte(pmap, addr); 4794 pte = *ptep; 4795 pmap_pte_release(ptep); 4796 pa = pte & PG_FRAME; 4797 } 4798 } else { 4799 pte = 0; 4800 pa = 0; 4801 } 4802 PMAP_UNLOCK(pmap); 4803 4804 if (pte != 0) { 4805 val |= MINCORE_INCORE; 4806 if ((pte & PG_MANAGED) == 0) 4807 return val; 4808 4809 m = PHYS_TO_VM_PAGE(pa); 4810 4811 /* 4812 * Modified by us 4813 */ 4814 if ((pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) 4815 val |= MINCORE_MODIFIED|MINCORE_MODIFIED_OTHER; 4816 else { 4817 /* 4818 * Modified by someone else 4819 */ 4820 vm_page_lock_queues(); 4821 if (m->dirty || pmap_is_modified(m)) 4822 val |= MINCORE_MODIFIED_OTHER; 4823 vm_page_unlock_queues(); 4824 } 4825 /* 4826 * Referenced by us 4827 */ 4828 if (pte & PG_A) 4829 val |= MINCORE_REFERENCED|MINCORE_REFERENCED_OTHER; 4830 else { 4831 /* 4832 * Referenced by someone else 4833 */ 4834 vm_page_lock_queues(); 4835 if ((m->flags & PG_REFERENCED) || 4836 pmap_ts_referenced(m)) { 4837 val |= MINCORE_REFERENCED_OTHER; 4838 vm_page_flag_set(m, PG_REFERENCED); 4839 } 4840 vm_page_unlock_queues(); 4841 } 4842 } 4843 return val; 4844} 4845 4846void 4847pmap_activate(struct thread *td) 4848{ 4849 pmap_t pmap, oldpmap; 4850 u_int32_t cr3; 4851 4852 critical_enter(); 4853 pmap = vmspace_pmap(td->td_proc->p_vmspace); 4854 oldpmap = PCPU_GET(curpmap); 4855#if defined(SMP) 4856 atomic_clear_int(&oldpmap->pm_active, PCPU_GET(cpumask)); 4857 atomic_set_int(&pmap->pm_active, PCPU_GET(cpumask)); 4858#else 4859 oldpmap->pm_active &= ~1; 4860 pmap->pm_active |= 1; 4861#endif 4862#ifdef PAE 4863 cr3 = vtophys(pmap->pm_pdpt); 4864#else 4865 cr3 = vtophys(pmap->pm_pdir); 4866#endif 4867 /* 4868 * pmap_activate is for the current thread on the current cpu 4869 */ 4870 td->td_pcb->pcb_cr3 = cr3; 4871 load_cr3(cr3); 4872 PCPU_SET(curpmap, pmap); 4873 critical_exit(); 4874} 4875 4876void 4877pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz) 4878{ 4879} 4880 4881/* 4882 * Increase the starting virtual address of the given mapping if a 4883 * different alignment might result in more superpage mappings. 4884 */ 4885void 4886pmap_align_superpage(vm_object_t object, vm_ooffset_t offset, 4887 vm_offset_t *addr, vm_size_t size) 4888{ 4889 vm_offset_t superpage_offset; 4890 4891 if (size < NBPDR) 4892 return; 4893 if (object != NULL && (object->flags & OBJ_COLORED) != 0) 4894 offset += ptoa(object->pg_color); 4895 superpage_offset = offset & PDRMASK; 4896 if (size - ((NBPDR - superpage_offset) & PDRMASK) < NBPDR || 4897 (*addr & PDRMASK) == superpage_offset) 4898 return; 4899 if ((*addr & PDRMASK) < superpage_offset) 4900 *addr = (*addr & ~PDRMASK) + superpage_offset; 4901 else 4902 *addr = ((*addr + PDRMASK) & ~PDRMASK) + superpage_offset; 4903} 4904 4905 4906#if defined(PMAP_DEBUG) 4907pmap_pid_dump(int pid) 4908{ 4909 pmap_t pmap; 4910 struct proc *p; 4911 int npte = 0; 4912 int index; 4913 4914 sx_slock(&allproc_lock); 4915 FOREACH_PROC_IN_SYSTEM(p) { 4916 if (p->p_pid != pid) 4917 continue; 4918 4919 if (p->p_vmspace) { 4920 int i,j; 4921 index = 0; 4922 pmap = vmspace_pmap(p->p_vmspace); 4923 for (i = 0; i < NPDEPTD; i++) { 4924 pd_entry_t *pde; 4925 pt_entry_t *pte; 4926 vm_offset_t base = i << PDRSHIFT; 4927 4928 pde = &pmap->pm_pdir[i]; 4929 if (pde && pmap_pde_v(pde)) { 4930 for (j = 0; j < NPTEPG; j++) { 4931 vm_offset_t va = base + (j << PAGE_SHIFT); 4932 if (va >= (vm_offset_t) VM_MIN_KERNEL_ADDRESS) { 4933 if (index) { 4934 index = 0; 4935 printf("\n"); 4936 } 4937 sx_sunlock(&allproc_lock); 4938 return npte; 4939 } 4940 pte = pmap_pte(pmap, va); 4941 if (pte && pmap_pte_v(pte)) { 4942 pt_entry_t pa; 4943 vm_page_t m; 4944 pa = *pte; 4945 m = PHYS_TO_VM_PAGE(pa & PG_FRAME); 4946 printf("va: 0x%x, pt: 0x%x, h: %d, w: %d, f: 0x%x", 4947 va, pa, m->hold_count, m->wire_count, m->flags); 4948 npte++; 4949 index++; 4950 if (index >= 2) { 4951 index = 0; 4952 printf("\n"); 4953 } else { 4954 printf(" "); 4955 } 4956 } 4957 } 4958 } 4959 } 4960 } 4961 } 4962 sx_sunlock(&allproc_lock); 4963 return npte; 4964} 4965#endif 4966 4967#if defined(DEBUG) 4968 4969static void pads(pmap_t pm); 4970void pmap_pvdump(vm_offset_t pa); 4971 4972/* print address space of pmap*/ 4973static void 4974pads(pmap_t pm) 4975{ 4976 int i, j; 4977 vm_paddr_t va; 4978 pt_entry_t *ptep; 4979 4980 if (pm == kernel_pmap) 4981 return; 4982 for (i = 0; i < NPDEPTD; i++) 4983 if (pm->pm_pdir[i]) 4984 for (j = 0; j < NPTEPG; j++) { 4985 va = (i << PDRSHIFT) + (j << PAGE_SHIFT); 4986 if (pm == kernel_pmap && va < KERNBASE) 4987 continue; 4988 if (pm != kernel_pmap && va > UPT_MAX_ADDRESS) 4989 continue; 4990 ptep = pmap_pte(pm, va); 4991 if (pmap_pte_v(ptep)) 4992 printf("%x:%x ", va, *ptep); 4993 }; 4994 4995} 4996 4997void 4998pmap_pvdump(vm_paddr_t pa) 4999{ 5000 pv_entry_t pv; 5001 pmap_t pmap; 5002 vm_page_t m; 5003 5004 printf("pa %x", pa); 5005 m = PHYS_TO_VM_PAGE(pa); 5006 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 5007 pmap = PV_PMAP(pv); 5008 printf(" -> pmap %p, va %x", (void *)pmap, pv->pv_va); 5009 pads(pmap); 5010 } 5011 printf(" "); 5012} 5013#endif 5014