pmap.c revision 204041
1/*- 2 * Copyright (c) 1991 Regents of the University of California. 3 * All rights reserved. 4 * Copyright (c) 1994 John S. Dyson 5 * All rights reserved. 6 * Copyright (c) 1994 David Greenman 7 * All rights reserved. 8 * Copyright (c) 2005-2008 Alan L. Cox <alc@cs.rice.edu> 9 * All rights reserved. 10 * 11 * This code is derived from software contributed to Berkeley by 12 * the Systems Programming Group of the University of Utah Computer 13 * Science Department and William Jolitz of UUNET Technologies Inc. 14 * 15 * Redistribution and use in source and binary forms, with or without 16 * modification, are permitted provided that the following conditions 17 * are met: 18 * 1. Redistributions of source code must retain the above copyright 19 * notice, this list of conditions and the following disclaimer. 20 * 2. Redistributions in binary form must reproduce the above copyright 21 * notice, this list of conditions and the following disclaimer in the 22 * documentation and/or other materials provided with the distribution. 23 * 3. All advertising materials mentioning features or use of this software 24 * must display the following acknowledgement: 25 * This product includes software developed by the University of 26 * California, Berkeley and its contributors. 27 * 4. Neither the name of the University nor the names of its contributors 28 * may be used to endorse or promote products derived from this software 29 * without specific prior written permission. 30 * 31 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 32 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 33 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 34 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 35 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 36 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 37 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 38 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 39 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 40 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 41 * SUCH DAMAGE. 42 * 43 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91 44 */ 45/*- 46 * Copyright (c) 2003 Networks Associates Technology, Inc. 47 * All rights reserved. 48 * 49 * This software was developed for the FreeBSD Project by Jake Burkholder, 50 * Safeport Network Services, and Network Associates Laboratories, the 51 * Security Research Division of Network Associates, Inc. under 52 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA 53 * CHATS research program. 54 * 55 * Redistribution and use in source and binary forms, with or without 56 * modification, are permitted provided that the following conditions 57 * are met: 58 * 1. Redistributions of source code must retain the above copyright 59 * notice, this list of conditions and the following disclaimer. 60 * 2. Redistributions in binary form must reproduce the above copyright 61 * notice, this list of conditions and the following disclaimer in the 62 * documentation and/or other materials provided with the distribution. 63 * 64 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 65 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 66 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 67 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 68 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 69 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 70 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 71 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 72 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 73 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 74 * SUCH DAMAGE. 75 */ 76 77#include <sys/cdefs.h> 78__FBSDID("$FreeBSD: head/sys/i386/i386/pmap.c 204041 2010-02-18 14:28:38Z ed $"); 79 80/* 81 * Manages physical address maps. 82 * 83 * In addition to hardware address maps, this 84 * module is called upon to provide software-use-only 85 * maps which may or may not be stored in the same 86 * form as hardware maps. These pseudo-maps are 87 * used to store intermediate results from copy 88 * operations to and from address spaces. 89 * 90 * Since the information managed by this module is 91 * also stored by the logical address mapping module, 92 * this module may throw away valid virtual-to-physical 93 * mappings at almost any time. However, invalidations 94 * of virtual-to-physical mappings must be done as 95 * requested. 96 * 97 * In order to cope with hardware architectures which 98 * make virtual-to-physical map invalidates expensive, 99 * this module may delay invalidate or reduced protection 100 * operations until such time as they are actually 101 * necessary. This module is given full information as 102 * to which processors are currently using which maps, 103 * and to when physical maps must be made correct. 104 */ 105 106#include "opt_cpu.h" 107#include "opt_pmap.h" 108#include "opt_msgbuf.h" 109#include "opt_smp.h" 110#include "opt_xbox.h" 111 112#include <sys/param.h> 113#include <sys/systm.h> 114#include <sys/kernel.h> 115#include <sys/ktr.h> 116#include <sys/lock.h> 117#include <sys/malloc.h> 118#include <sys/mman.h> 119#include <sys/msgbuf.h> 120#include <sys/mutex.h> 121#include <sys/proc.h> 122#include <sys/sf_buf.h> 123#include <sys/sx.h> 124#include <sys/vmmeter.h> 125#include <sys/sched.h> 126#include <sys/sysctl.h> 127#ifdef SMP 128#include <sys/smp.h> 129#endif 130 131#include <vm/vm.h> 132#include <vm/vm_param.h> 133#include <vm/vm_kern.h> 134#include <vm/vm_page.h> 135#include <vm/vm_map.h> 136#include <vm/vm_object.h> 137#include <vm/vm_extern.h> 138#include <vm/vm_pageout.h> 139#include <vm/vm_pager.h> 140#include <vm/vm_reserv.h> 141#include <vm/uma.h> 142 143#include <machine/cpu.h> 144#include <machine/cputypes.h> 145#include <machine/md_var.h> 146#include <machine/pcb.h> 147#include <machine/specialreg.h> 148#ifdef SMP 149#include <machine/smp.h> 150#endif 151 152#ifdef XBOX 153#include <machine/xbox.h> 154#endif 155 156#if !defined(CPU_DISABLE_SSE) && defined(I686_CPU) 157#define CPU_ENABLE_SSE 158#endif 159 160#ifndef PMAP_SHPGPERPROC 161#define PMAP_SHPGPERPROC 200 162#endif 163 164#if !defined(DIAGNOSTIC) 165#ifdef __GNUC_GNU_INLINE__ 166#define PMAP_INLINE inline 167#else 168#define PMAP_INLINE extern inline 169#endif 170#else 171#define PMAP_INLINE 172#endif 173 174#define PV_STATS 175#ifdef PV_STATS 176#define PV_STAT(x) do { x ; } while (0) 177#else 178#define PV_STAT(x) do { } while (0) 179#endif 180 181#define pa_index(pa) ((pa) >> PDRSHIFT) 182#define pa_to_pvh(pa) (&pv_table[pa_index(pa)]) 183 184/* 185 * Get PDEs and PTEs for user/kernel address space 186 */ 187#define pmap_pde(m, v) (&((m)->pm_pdir[(vm_offset_t)(v) >> PDRSHIFT])) 188#define pdir_pde(m, v) (m[(vm_offset_t)(v) >> PDRSHIFT]) 189 190#define pmap_pde_v(pte) ((*(int *)pte & PG_V) != 0) 191#define pmap_pte_w(pte) ((*(int *)pte & PG_W) != 0) 192#define pmap_pte_m(pte) ((*(int *)pte & PG_M) != 0) 193#define pmap_pte_u(pte) ((*(int *)pte & PG_A) != 0) 194#define pmap_pte_v(pte) ((*(int *)pte & PG_V) != 0) 195 196#define pmap_pte_set_w(pte, v) ((v) ? atomic_set_int((u_int *)(pte), PG_W) : \ 197 atomic_clear_int((u_int *)(pte), PG_W)) 198#define pmap_pte_set_prot(pte, v) ((*(int *)pte &= ~PG_PROT), (*(int *)pte |= (v))) 199 200struct pmap kernel_pmap_store; 201LIST_HEAD(pmaplist, pmap); 202static struct pmaplist allpmaps; 203static struct mtx allpmaps_lock; 204 205vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */ 206vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */ 207int pgeflag = 0; /* PG_G or-in */ 208int pseflag = 0; /* PG_PS or-in */ 209 210static int nkpt; 211vm_offset_t kernel_vm_end; 212extern u_int32_t KERNend; 213extern u_int32_t KPTphys; 214 215#ifdef PAE 216pt_entry_t pg_nx; 217static uma_zone_t pdptzone; 218#endif 219 220static int pat_works = 0; /* Is page attribute table sane? */ 221 222SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD, 0, "VM/pmap parameters"); 223 224static int pg_ps_enabled = 1; 225SYSCTL_INT(_vm_pmap, OID_AUTO, pg_ps_enabled, CTLFLAG_RDTUN, &pg_ps_enabled, 0, 226 "Are large page mappings enabled?"); 227 228/* 229 * Data for the pv entry allocation mechanism 230 */ 231static int pv_entry_count = 0, pv_entry_max = 0, pv_entry_high_water = 0; 232static struct md_page *pv_table; 233static int shpgperproc = PMAP_SHPGPERPROC; 234 235struct pv_chunk *pv_chunkbase; /* KVA block for pv_chunks */ 236int pv_maxchunks; /* How many chunks we have KVA for */ 237vm_offset_t pv_vafree; /* freelist stored in the PTE */ 238 239/* 240 * All those kernel PT submaps that BSD is so fond of 241 */ 242struct sysmaps { 243 struct mtx lock; 244 pt_entry_t *CMAP1; 245 pt_entry_t *CMAP2; 246 caddr_t CADDR1; 247 caddr_t CADDR2; 248}; 249static struct sysmaps sysmaps_pcpu[MAXCPU]; 250pt_entry_t *CMAP1 = 0, *KPTmap; 251static pt_entry_t *CMAP3; 252static pd_entry_t *KPTD; 253caddr_t CADDR1 = 0, ptvmmap = 0; 254static caddr_t CADDR3; 255struct msgbuf *msgbufp = 0; 256 257/* 258 * Crashdump maps. 259 */ 260static caddr_t crashdumpmap; 261 262static pt_entry_t *PMAP1 = 0, *PMAP2; 263static pt_entry_t *PADDR1 = 0, *PADDR2; 264#ifdef SMP 265static int PMAP1cpu; 266static int PMAP1changedcpu; 267SYSCTL_INT(_debug, OID_AUTO, PMAP1changedcpu, CTLFLAG_RD, 268 &PMAP1changedcpu, 0, 269 "Number of times pmap_pte_quick changed CPU with same PMAP1"); 270#endif 271static int PMAP1changed; 272SYSCTL_INT(_debug, OID_AUTO, PMAP1changed, CTLFLAG_RD, 273 &PMAP1changed, 0, 274 "Number of times pmap_pte_quick changed PMAP1"); 275static int PMAP1unchanged; 276SYSCTL_INT(_debug, OID_AUTO, PMAP1unchanged, CTLFLAG_RD, 277 &PMAP1unchanged, 0, 278 "Number of times pmap_pte_quick didn't change PMAP1"); 279static struct mtx PMAP2mutex; 280 281static void free_pv_entry(pmap_t pmap, pv_entry_t pv); 282static pv_entry_t get_pv_entry(pmap_t locked_pmap, int try); 283static void pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa); 284static boolean_t pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa); 285static void pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa); 286static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va); 287static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, 288 vm_offset_t va); 289static int pmap_pvh_wired_mappings(struct md_page *pvh, int count); 290 291static boolean_t pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va); 292static boolean_t pmap_enter_pde(pmap_t pmap, vm_offset_t va, vm_page_t m, 293 vm_prot_t prot); 294static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, 295 vm_page_t m, vm_prot_t prot, vm_page_t mpte); 296static void pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte); 297static void pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte); 298static boolean_t pmap_is_modified_pvh(struct md_page *pvh); 299static void pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode); 300static vm_page_t pmap_lookup_pt_page(pmap_t pmap, vm_offset_t va); 301static void pmap_pde_attr(pd_entry_t *pde, int cache_bits); 302static void pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va); 303static boolean_t pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva, 304 vm_prot_t prot); 305static void pmap_pte_attr(pt_entry_t *pte, int cache_bits); 306static void pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva, 307 vm_page_t *free); 308static int pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t sva, 309 vm_page_t *free); 310static void pmap_remove_pt_page(pmap_t pmap, vm_page_t mpte); 311static void pmap_remove_page(struct pmap *pmap, vm_offset_t va, 312 vm_page_t *free); 313static void pmap_remove_entry(struct pmap *pmap, vm_page_t m, 314 vm_offset_t va); 315static void pmap_insert_entry(pmap_t pmap, vm_offset_t va, vm_page_t m); 316static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, 317 vm_page_t m); 318 319static vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va, int flags); 320 321static vm_page_t _pmap_allocpte(pmap_t pmap, unsigned ptepindex, int flags); 322static int _pmap_unwire_pte_hold(pmap_t pmap, vm_page_t m, vm_page_t *free); 323static pt_entry_t *pmap_pte_quick(pmap_t pmap, vm_offset_t va); 324static void pmap_pte_release(pt_entry_t *pte); 325static int pmap_unuse_pt(pmap_t, vm_offset_t, vm_page_t *); 326#ifdef PAE 327static void *pmap_pdpt_allocf(uma_zone_t zone, int bytes, u_int8_t *flags, int wait); 328#endif 329static void pmap_set_pg(void); 330 331CTASSERT(1 << PDESHIFT == sizeof(pd_entry_t)); 332CTASSERT(1 << PTESHIFT == sizeof(pt_entry_t)); 333 334/* 335 * If you get an error here, then you set KVA_PAGES wrong! See the 336 * description of KVA_PAGES in sys/i386/include/pmap.h. It must be 337 * multiple of 4 for a normal kernel, or a multiple of 8 for a PAE. 338 */ 339CTASSERT(KERNBASE % (1 << 24) == 0); 340 341/* 342 * Bootstrap the system enough to run with virtual memory. 343 * 344 * On the i386 this is called after mapping has already been enabled 345 * and just syncs the pmap module with what has already been done. 346 * [We can't call it easily with mapping off since the kernel is not 347 * mapped with PA == VA, hence we would have to relocate every address 348 * from the linked base (virtual) address "KERNBASE" to the actual 349 * (physical) address starting relative to 0] 350 */ 351void 352pmap_bootstrap(vm_paddr_t firstaddr) 353{ 354 vm_offset_t va; 355 pt_entry_t *pte, *unused; 356 struct sysmaps *sysmaps; 357 int i; 358 359 /* 360 * XXX The calculation of virtual_avail is wrong. It's NKPT*PAGE_SIZE too 361 * large. It should instead be correctly calculated in locore.s and 362 * not based on 'first' (which is a physical address, not a virtual 363 * address, for the start of unused physical memory). The kernel 364 * page tables are NOT double mapped and thus should not be included 365 * in this calculation. 366 */ 367 virtual_avail = (vm_offset_t) KERNBASE + firstaddr; 368 369 virtual_end = VM_MAX_KERNEL_ADDRESS; 370 371 /* 372 * Initialize the kernel pmap (which is statically allocated). 373 */ 374 PMAP_LOCK_INIT(kernel_pmap); 375 kernel_pmap->pm_pdir = (pd_entry_t *) (KERNBASE + (u_int)IdlePTD); 376#ifdef PAE 377 kernel_pmap->pm_pdpt = (pdpt_entry_t *) (KERNBASE + (u_int)IdlePDPT); 378#endif 379 kernel_pmap->pm_root = NULL; 380 kernel_pmap->pm_active = -1; /* don't allow deactivation */ 381 TAILQ_INIT(&kernel_pmap->pm_pvchunk); 382 LIST_INIT(&allpmaps); 383 mtx_init(&allpmaps_lock, "allpmaps", NULL, MTX_SPIN); 384 mtx_lock_spin(&allpmaps_lock); 385 LIST_INSERT_HEAD(&allpmaps, kernel_pmap, pm_list); 386 mtx_unlock_spin(&allpmaps_lock); 387 nkpt = NKPT; 388 389 /* 390 * Reserve some special page table entries/VA space for temporary 391 * mapping of pages. 392 */ 393#define SYSMAP(c, p, v, n) \ 394 v = (c)va; va += ((n)*PAGE_SIZE); p = pte; pte += (n); 395 396 va = virtual_avail; 397 pte = vtopte(va); 398 399 /* 400 * CMAP1/CMAP2 are used for zeroing and copying pages. 401 * CMAP3 is used for the idle process page zeroing. 402 */ 403 for (i = 0; i < MAXCPU; i++) { 404 sysmaps = &sysmaps_pcpu[i]; 405 mtx_init(&sysmaps->lock, "SYSMAPS", NULL, MTX_DEF); 406 SYSMAP(caddr_t, sysmaps->CMAP1, sysmaps->CADDR1, 1) 407 SYSMAP(caddr_t, sysmaps->CMAP2, sysmaps->CADDR2, 1) 408 } 409 SYSMAP(caddr_t, CMAP1, CADDR1, 1) 410 SYSMAP(caddr_t, CMAP3, CADDR3, 1) 411 412 /* 413 * Crashdump maps. 414 */ 415 SYSMAP(caddr_t, unused, crashdumpmap, MAXDUMPPGS) 416 417 /* 418 * ptvmmap is used for reading arbitrary physical pages via /dev/mem. 419 */ 420 SYSMAP(caddr_t, unused, ptvmmap, 1) 421 422 /* 423 * msgbufp is used to map the system message buffer. 424 */ 425 SYSMAP(struct msgbuf *, unused, msgbufp, atop(round_page(MSGBUF_SIZE))) 426 427 /* 428 * KPTmap is used by pmap_kextract(). 429 */ 430 SYSMAP(pt_entry_t *, KPTD, KPTmap, KVA_PAGES) 431 432 for (i = 0; i < NKPT; i++) 433 KPTD[i] = (KPTphys + (i << PAGE_SHIFT)) | pgeflag | PG_RW | PG_V; 434 435 /* 436 * Adjust the start of the KPTD and KPTmap so that the implementation 437 * of pmap_kextract() and pmap_growkernel() can be made simpler. 438 */ 439 KPTD -= KPTDI; 440 KPTmap -= i386_btop(KPTDI << PDRSHIFT); 441 442 /* 443 * ptemap is used for pmap_pte_quick 444 */ 445 SYSMAP(pt_entry_t *, PMAP1, PADDR1, 1) 446 SYSMAP(pt_entry_t *, PMAP2, PADDR2, 1) 447 448 mtx_init(&PMAP2mutex, "PMAP2", NULL, MTX_DEF); 449 450 virtual_avail = va; 451 452 /* 453 * Leave in place an identity mapping (virt == phys) for the low 1 MB 454 * physical memory region that is used by the ACPI wakeup code. This 455 * mapping must not have PG_G set. 456 */ 457#ifdef XBOX 458 /* FIXME: This is gross, but needed for the XBOX. Since we are in such 459 * an early stadium, we cannot yet neatly map video memory ... :-( 460 * Better fixes are very welcome! */ 461 if (!arch_i386_is_xbox) 462#endif 463 for (i = 1; i < NKPT; i++) 464 PTD[i] = 0; 465 466 /* Initialize the PAT MSR if present. */ 467 pmap_init_pat(); 468 469 /* Turn on PG_G on kernel page(s) */ 470 pmap_set_pg(); 471} 472 473/* 474 * Setup the PAT MSR. 475 */ 476void 477pmap_init_pat(void) 478{ 479 uint64_t pat_msr; 480 char *sysenv; 481 static int pat_tested = 0; 482 483 /* Bail if this CPU doesn't implement PAT. */ 484 if (!(cpu_feature & CPUID_PAT)) 485 return; 486 487 /* 488 * Due to some Intel errata, we can only safely use the lower 4 489 * PAT entries. 490 * 491 * Intel Pentium III Processor Specification Update 492 * Errata E.27 (Upper Four PAT Entries Not Usable With Mode B 493 * or Mode C Paging) 494 * 495 * Intel Pentium IV Processor Specification Update 496 * Errata N46 (PAT Index MSB May Be Calculated Incorrectly) 497 * 498 * Some Apple Macs based on nVidia chipsets cannot enter ACPI mode 499 * via SMI# when we use upper 4 PAT entries for unknown reason. 500 */ 501 if (!pat_tested) { 502 if (cpu_vendor_id != CPU_VENDOR_INTEL || 503 (CPUID_TO_FAMILY(cpu_id) == 6 && 504 CPUID_TO_MODEL(cpu_id) >= 0xe)) { 505 pat_works = 1; 506 sysenv = getenv("smbios.system.product"); 507 if (sysenv != NULL) { 508 if (strncmp(sysenv, "MacBook5,1", 10) == 0 || 509 strncmp(sysenv, "MacBookPro5,5", 13) == 0 || 510 strncmp(sysenv, "Macmini3,1", 10) == 0) 511 pat_works = 0; 512 freeenv(sysenv); 513 } 514 } 515 pat_tested = 1; 516 } 517 518 /* Initialize default PAT entries. */ 519 pat_msr = PAT_VALUE(0, PAT_WRITE_BACK) | 520 PAT_VALUE(1, PAT_WRITE_THROUGH) | 521 PAT_VALUE(2, PAT_UNCACHED) | 522 PAT_VALUE(3, PAT_UNCACHEABLE) | 523 PAT_VALUE(4, PAT_WRITE_BACK) | 524 PAT_VALUE(5, PAT_WRITE_THROUGH) | 525 PAT_VALUE(6, PAT_UNCACHED) | 526 PAT_VALUE(7, PAT_UNCACHEABLE); 527 528 if (pat_works) { 529 /* 530 * Leave the indices 0-3 at the default of WB, WT, UC-, and UC. 531 * Program 4 and 5 as WP and WC. 532 * Leave 6 and 7 as UC- and UC. 533 */ 534 pat_msr &= ~(PAT_MASK(4) | PAT_MASK(5)); 535 pat_msr |= PAT_VALUE(4, PAT_WRITE_PROTECTED) | 536 PAT_VALUE(5, PAT_WRITE_COMBINING); 537 } else { 538 /* 539 * Just replace PAT Index 2 with WC instead of UC-. 540 */ 541 pat_msr &= ~PAT_MASK(2); 542 pat_msr |= PAT_VALUE(2, PAT_WRITE_COMBINING); 543 } 544 wrmsr(MSR_PAT, pat_msr); 545} 546 547/* 548 * Set PG_G on kernel pages. Only the BSP calls this when SMP is turned on. 549 */ 550static void 551pmap_set_pg(void) 552{ 553 pt_entry_t *pte; 554 vm_offset_t va, endva; 555 556 if (pgeflag == 0) 557 return; 558 559 endva = KERNBASE + KERNend; 560 561 if (pseflag) { 562 va = KERNBASE + KERNLOAD; 563 while (va < endva) { 564 pdir_pde(PTD, va) |= pgeflag; 565 invltlb(); /* Play it safe, invltlb() every time */ 566 va += NBPDR; 567 } 568 } else { 569 va = (vm_offset_t)btext; 570 while (va < endva) { 571 pte = vtopte(va); 572 if (*pte) 573 *pte |= pgeflag; 574 invltlb(); /* Play it safe, invltlb() every time */ 575 va += PAGE_SIZE; 576 } 577 } 578} 579 580/* 581 * Initialize a vm_page's machine-dependent fields. 582 */ 583void 584pmap_page_init(vm_page_t m) 585{ 586 587 TAILQ_INIT(&m->md.pv_list); 588 m->md.pat_mode = PAT_WRITE_BACK; 589} 590 591#ifdef PAE 592static void * 593pmap_pdpt_allocf(uma_zone_t zone, int bytes, u_int8_t *flags, int wait) 594{ 595 596 /* Inform UMA that this allocator uses kernel_map/object. */ 597 *flags = UMA_SLAB_KERNEL; 598 return ((void *)kmem_alloc_contig(kernel_map, bytes, wait, 0x0ULL, 599 0xffffffffULL, 1, 0, VM_MEMATTR_DEFAULT)); 600} 601#endif 602 603/* 604 * ABuse the pte nodes for unmapped kva to thread a kva freelist through. 605 * Requirements: 606 * - Must deal with pages in order to ensure that none of the PG_* bits 607 * are ever set, PG_V in particular. 608 * - Assumes we can write to ptes without pte_store() atomic ops, even 609 * on PAE systems. This should be ok. 610 * - Assumes nothing will ever test these addresses for 0 to indicate 611 * no mapping instead of correctly checking PG_V. 612 * - Assumes a vm_offset_t will fit in a pte (true for i386). 613 * Because PG_V is never set, there can be no mappings to invalidate. 614 */ 615static vm_offset_t 616pmap_ptelist_alloc(vm_offset_t *head) 617{ 618 pt_entry_t *pte; 619 vm_offset_t va; 620 621 va = *head; 622 if (va == 0) 623 return (va); /* Out of memory */ 624 pte = vtopte(va); 625 *head = *pte; 626 if (*head & PG_V) 627 panic("pmap_ptelist_alloc: va with PG_V set!"); 628 *pte = 0; 629 return (va); 630} 631 632static void 633pmap_ptelist_free(vm_offset_t *head, vm_offset_t va) 634{ 635 pt_entry_t *pte; 636 637 if (va & PG_V) 638 panic("pmap_ptelist_free: freeing va with PG_V set!"); 639 pte = vtopte(va); 640 *pte = *head; /* virtual! PG_V is 0 though */ 641 *head = va; 642} 643 644static void 645pmap_ptelist_init(vm_offset_t *head, void *base, int npages) 646{ 647 int i; 648 vm_offset_t va; 649 650 *head = 0; 651 for (i = npages - 1; i >= 0; i--) { 652 va = (vm_offset_t)base + i * PAGE_SIZE; 653 pmap_ptelist_free(head, va); 654 } 655} 656 657 658/* 659 * Initialize the pmap module. 660 * Called by vm_init, to initialize any structures that the pmap 661 * system needs to map virtual memory. 662 */ 663void 664pmap_init(void) 665{ 666 vm_page_t mpte; 667 vm_size_t s; 668 int i, pv_npg; 669 670 /* 671 * Initialize the vm page array entries for the kernel pmap's 672 * page table pages. 673 */ 674 for (i = 0; i < NKPT; i++) { 675 mpte = PHYS_TO_VM_PAGE(KPTphys + (i << PAGE_SHIFT)); 676 KASSERT(mpte >= vm_page_array && 677 mpte < &vm_page_array[vm_page_array_size], 678 ("pmap_init: page table page is out of range")); 679 mpte->pindex = i + KPTDI; 680 mpte->phys_addr = KPTphys + (i << PAGE_SHIFT); 681 } 682 683 /* 684 * Initialize the address space (zone) for the pv entries. Set a 685 * high water mark so that the system can recover from excessive 686 * numbers of pv entries. 687 */ 688 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc); 689 pv_entry_max = shpgperproc * maxproc + cnt.v_page_count; 690 TUNABLE_INT_FETCH("vm.pmap.pv_entries", &pv_entry_max); 691 pv_entry_max = roundup(pv_entry_max, _NPCPV); 692 pv_entry_high_water = 9 * (pv_entry_max / 10); 693 694 /* 695 * Are large page mappings enabled? 696 */ 697 TUNABLE_INT_FETCH("vm.pmap.pg_ps_enabled", &pg_ps_enabled); 698 if (pg_ps_enabled) { 699 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0, 700 ("pmap_init: can't assign to pagesizes[1]")); 701 pagesizes[1] = NBPDR; 702 } 703 704 /* 705 * Calculate the size of the pv head table for superpages. 706 */ 707 for (i = 0; phys_avail[i + 1]; i += 2); 708 pv_npg = round_4mpage(phys_avail[(i - 2) + 1]) / NBPDR; 709 710 /* 711 * Allocate memory for the pv head table for superpages. 712 */ 713 s = (vm_size_t)(pv_npg * sizeof(struct md_page)); 714 s = round_page(s); 715 pv_table = (struct md_page *)kmem_alloc(kernel_map, s); 716 for (i = 0; i < pv_npg; i++) 717 TAILQ_INIT(&pv_table[i].pv_list); 718 719 pv_maxchunks = MAX(pv_entry_max / _NPCPV, maxproc); 720 pv_chunkbase = (struct pv_chunk *)kmem_alloc_nofault(kernel_map, 721 PAGE_SIZE * pv_maxchunks); 722 if (pv_chunkbase == NULL) 723 panic("pmap_init: not enough kvm for pv chunks"); 724 pmap_ptelist_init(&pv_vafree, pv_chunkbase, pv_maxchunks); 725#ifdef PAE 726 pdptzone = uma_zcreate("PDPT", NPGPTD * sizeof(pdpt_entry_t), NULL, 727 NULL, NULL, NULL, (NPGPTD * sizeof(pdpt_entry_t)) - 1, 728 UMA_ZONE_VM | UMA_ZONE_NOFREE); 729 uma_zone_set_allocf(pdptzone, pmap_pdpt_allocf); 730#endif 731} 732 733 734SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_max, CTLFLAG_RD, &pv_entry_max, 0, 735 "Max number of PV entries"); 736SYSCTL_INT(_vm_pmap, OID_AUTO, shpgperproc, CTLFLAG_RD, &shpgperproc, 0, 737 "Page share factor per proc"); 738 739SYSCTL_NODE(_vm_pmap, OID_AUTO, pde, CTLFLAG_RD, 0, 740 "2/4MB page mapping counters"); 741 742static u_long pmap_pde_demotions; 743SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, demotions, CTLFLAG_RD, 744 &pmap_pde_demotions, 0, "2/4MB page demotions"); 745 746static u_long pmap_pde_mappings; 747SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, mappings, CTLFLAG_RD, 748 &pmap_pde_mappings, 0, "2/4MB page mappings"); 749 750static u_long pmap_pde_p_failures; 751SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, p_failures, CTLFLAG_RD, 752 &pmap_pde_p_failures, 0, "2/4MB page promotion failures"); 753 754static u_long pmap_pde_promotions; 755SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, promotions, CTLFLAG_RD, 756 &pmap_pde_promotions, 0, "2/4MB page promotions"); 757 758/*************************************************** 759 * Low level helper routines..... 760 ***************************************************/ 761 762/* 763 * Determine the appropriate bits to set in a PTE or PDE for a specified 764 * caching mode. 765 */ 766int 767pmap_cache_bits(int mode, boolean_t is_pde) 768{ 769 int pat_flag, pat_index, cache_bits; 770 771 /* The PAT bit is different for PTE's and PDE's. */ 772 pat_flag = is_pde ? PG_PDE_PAT : PG_PTE_PAT; 773 774 /* If we don't support PAT, map extended modes to older ones. */ 775 if (!(cpu_feature & CPUID_PAT)) { 776 switch (mode) { 777 case PAT_UNCACHEABLE: 778 case PAT_WRITE_THROUGH: 779 case PAT_WRITE_BACK: 780 break; 781 case PAT_UNCACHED: 782 case PAT_WRITE_COMBINING: 783 case PAT_WRITE_PROTECTED: 784 mode = PAT_UNCACHEABLE; 785 break; 786 } 787 } 788 789 /* Map the caching mode to a PAT index. */ 790 if (pat_works) { 791 switch (mode) { 792 case PAT_UNCACHEABLE: 793 pat_index = 3; 794 break; 795 case PAT_WRITE_THROUGH: 796 pat_index = 1; 797 break; 798 case PAT_WRITE_BACK: 799 pat_index = 0; 800 break; 801 case PAT_UNCACHED: 802 pat_index = 2; 803 break; 804 case PAT_WRITE_COMBINING: 805 pat_index = 5; 806 break; 807 case PAT_WRITE_PROTECTED: 808 pat_index = 4; 809 break; 810 default: 811 panic("Unknown caching mode %d\n", mode); 812 } 813 } else { 814 switch (mode) { 815 case PAT_UNCACHED: 816 case PAT_UNCACHEABLE: 817 case PAT_WRITE_PROTECTED: 818 pat_index = 3; 819 break; 820 case PAT_WRITE_THROUGH: 821 pat_index = 1; 822 break; 823 case PAT_WRITE_BACK: 824 pat_index = 0; 825 break; 826 case PAT_WRITE_COMBINING: 827 pat_index = 2; 828 break; 829 default: 830 panic("Unknown caching mode %d\n", mode); 831 } 832 } 833 834 /* Map the 3-bit index value into the PAT, PCD, and PWT bits. */ 835 cache_bits = 0; 836 if (pat_index & 0x4) 837 cache_bits |= pat_flag; 838 if (pat_index & 0x2) 839 cache_bits |= PG_NC_PCD; 840 if (pat_index & 0x1) 841 cache_bits |= PG_NC_PWT; 842 return (cache_bits); 843} 844#ifdef SMP 845/* 846 * For SMP, these functions have to use the IPI mechanism for coherence. 847 * 848 * N.B.: Before calling any of the following TLB invalidation functions, 849 * the calling processor must ensure that all stores updating a non- 850 * kernel page table are globally performed. Otherwise, another 851 * processor could cache an old, pre-update entry without being 852 * invalidated. This can happen one of two ways: (1) The pmap becomes 853 * active on another processor after its pm_active field is checked by 854 * one of the following functions but before a store updating the page 855 * table is globally performed. (2) The pmap becomes active on another 856 * processor before its pm_active field is checked but due to 857 * speculative loads one of the following functions stills reads the 858 * pmap as inactive on the other processor. 859 * 860 * The kernel page table is exempt because its pm_active field is 861 * immutable. The kernel page table is always active on every 862 * processor. 863 */ 864void 865pmap_invalidate_page(pmap_t pmap, vm_offset_t va) 866{ 867 u_int cpumask; 868 u_int other_cpus; 869 870 sched_pin(); 871 if (pmap == kernel_pmap || pmap->pm_active == all_cpus) { 872 invlpg(va); 873 smp_invlpg(va); 874 } else { 875 cpumask = PCPU_GET(cpumask); 876 other_cpus = PCPU_GET(other_cpus); 877 if (pmap->pm_active & cpumask) 878 invlpg(va); 879 if (pmap->pm_active & other_cpus) 880 smp_masked_invlpg(pmap->pm_active & other_cpus, va); 881 } 882 sched_unpin(); 883} 884 885void 886pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 887{ 888 u_int cpumask; 889 u_int other_cpus; 890 vm_offset_t addr; 891 892 sched_pin(); 893 if (pmap == kernel_pmap || pmap->pm_active == all_cpus) { 894 for (addr = sva; addr < eva; addr += PAGE_SIZE) 895 invlpg(addr); 896 smp_invlpg_range(sva, eva); 897 } else { 898 cpumask = PCPU_GET(cpumask); 899 other_cpus = PCPU_GET(other_cpus); 900 if (pmap->pm_active & cpumask) 901 for (addr = sva; addr < eva; addr += PAGE_SIZE) 902 invlpg(addr); 903 if (pmap->pm_active & other_cpus) 904 smp_masked_invlpg_range(pmap->pm_active & other_cpus, 905 sva, eva); 906 } 907 sched_unpin(); 908} 909 910void 911pmap_invalidate_all(pmap_t pmap) 912{ 913 u_int cpumask; 914 u_int other_cpus; 915 916 sched_pin(); 917 if (pmap == kernel_pmap || pmap->pm_active == all_cpus) { 918 invltlb(); 919 smp_invltlb(); 920 } else { 921 cpumask = PCPU_GET(cpumask); 922 other_cpus = PCPU_GET(other_cpus); 923 if (pmap->pm_active & cpumask) 924 invltlb(); 925 if (pmap->pm_active & other_cpus) 926 smp_masked_invltlb(pmap->pm_active & other_cpus); 927 } 928 sched_unpin(); 929} 930 931void 932pmap_invalidate_cache(void) 933{ 934 935 sched_pin(); 936 wbinvd(); 937 smp_cache_flush(); 938 sched_unpin(); 939} 940#else /* !SMP */ 941/* 942 * Normal, non-SMP, 486+ invalidation functions. 943 * We inline these within pmap.c for speed. 944 */ 945PMAP_INLINE void 946pmap_invalidate_page(pmap_t pmap, vm_offset_t va) 947{ 948 949 if (pmap == kernel_pmap || pmap->pm_active) 950 invlpg(va); 951} 952 953PMAP_INLINE void 954pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 955{ 956 vm_offset_t addr; 957 958 if (pmap == kernel_pmap || pmap->pm_active) 959 for (addr = sva; addr < eva; addr += PAGE_SIZE) 960 invlpg(addr); 961} 962 963PMAP_INLINE void 964pmap_invalidate_all(pmap_t pmap) 965{ 966 967 if (pmap == kernel_pmap || pmap->pm_active) 968 invltlb(); 969} 970 971PMAP_INLINE void 972pmap_invalidate_cache(void) 973{ 974 975 wbinvd(); 976} 977#endif /* !SMP */ 978 979void 980pmap_invalidate_cache_range(vm_offset_t sva, vm_offset_t eva) 981{ 982 983 KASSERT((sva & PAGE_MASK) == 0, 984 ("pmap_invalidate_cache_range: sva not page-aligned")); 985 KASSERT((eva & PAGE_MASK) == 0, 986 ("pmap_invalidate_cache_range: eva not page-aligned")); 987 988 if (cpu_feature & CPUID_SS) 989 ; /* If "Self Snoop" is supported, do nothing. */ 990 else if (cpu_feature & CPUID_CLFSH) { 991 992 /* 993 * Otherwise, do per-cache line flush. Use the mfence 994 * instruction to insure that previous stores are 995 * included in the write-back. The processor 996 * propagates flush to other processors in the cache 997 * coherence domain. 998 */ 999 mfence(); 1000 for (; sva < eva; sva += cpu_clflush_line_size) 1001 clflush(sva); 1002 mfence(); 1003 } else { 1004 1005 /* 1006 * No targeted cache flush methods are supported by CPU, 1007 * globally invalidate cache as a last resort. 1008 */ 1009 pmap_invalidate_cache(); 1010 } 1011} 1012 1013/* 1014 * Are we current address space or kernel? N.B. We return FALSE when 1015 * a pmap's page table is in use because a kernel thread is borrowing 1016 * it. The borrowed page table can change spontaneously, making any 1017 * dependence on its continued use subject to a race condition. 1018 */ 1019static __inline int 1020pmap_is_current(pmap_t pmap) 1021{ 1022 1023 return (pmap == kernel_pmap || 1024 (pmap == vmspace_pmap(curthread->td_proc->p_vmspace) && 1025 (pmap->pm_pdir[PTDPTDI] & PG_FRAME) == (PTDpde[0] & PG_FRAME))); 1026} 1027 1028/* 1029 * If the given pmap is not the current or kernel pmap, the returned pte must 1030 * be released by passing it to pmap_pte_release(). 1031 */ 1032pt_entry_t * 1033pmap_pte(pmap_t pmap, vm_offset_t va) 1034{ 1035 pd_entry_t newpf; 1036 pd_entry_t *pde; 1037 1038 pde = pmap_pde(pmap, va); 1039 if (*pde & PG_PS) 1040 return (pde); 1041 if (*pde != 0) { 1042 /* are we current address space or kernel? */ 1043 if (pmap_is_current(pmap)) 1044 return (vtopte(va)); 1045 mtx_lock(&PMAP2mutex); 1046 newpf = *pde & PG_FRAME; 1047 if ((*PMAP2 & PG_FRAME) != newpf) { 1048 *PMAP2 = newpf | PG_RW | PG_V | PG_A | PG_M; 1049 pmap_invalidate_page(kernel_pmap, (vm_offset_t)PADDR2); 1050 } 1051 return (PADDR2 + (i386_btop(va) & (NPTEPG - 1))); 1052 } 1053 return (0); 1054} 1055 1056/* 1057 * Releases a pte that was obtained from pmap_pte(). Be prepared for the pte 1058 * being NULL. 1059 */ 1060static __inline void 1061pmap_pte_release(pt_entry_t *pte) 1062{ 1063 1064 if ((pt_entry_t *)((vm_offset_t)pte & ~PAGE_MASK) == PADDR2) 1065 mtx_unlock(&PMAP2mutex); 1066} 1067 1068static __inline void 1069invlcaddr(void *caddr) 1070{ 1071 1072 invlpg((u_int)caddr); 1073} 1074 1075/* 1076 * Super fast pmap_pte routine best used when scanning 1077 * the pv lists. This eliminates many coarse-grained 1078 * invltlb calls. Note that many of the pv list 1079 * scans are across different pmaps. It is very wasteful 1080 * to do an entire invltlb for checking a single mapping. 1081 * 1082 * If the given pmap is not the current pmap, vm_page_queue_mtx 1083 * must be held and curthread pinned to a CPU. 1084 */ 1085static pt_entry_t * 1086pmap_pte_quick(pmap_t pmap, vm_offset_t va) 1087{ 1088 pd_entry_t newpf; 1089 pd_entry_t *pde; 1090 1091 pde = pmap_pde(pmap, va); 1092 if (*pde & PG_PS) 1093 return (pde); 1094 if (*pde != 0) { 1095 /* are we current address space or kernel? */ 1096 if (pmap_is_current(pmap)) 1097 return (vtopte(va)); 1098 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1099 KASSERT(curthread->td_pinned > 0, ("curthread not pinned")); 1100 newpf = *pde & PG_FRAME; 1101 if ((*PMAP1 & PG_FRAME) != newpf) { 1102 *PMAP1 = newpf | PG_RW | PG_V | PG_A | PG_M; 1103#ifdef SMP 1104 PMAP1cpu = PCPU_GET(cpuid); 1105#endif 1106 invlcaddr(PADDR1); 1107 PMAP1changed++; 1108 } else 1109#ifdef SMP 1110 if (PMAP1cpu != PCPU_GET(cpuid)) { 1111 PMAP1cpu = PCPU_GET(cpuid); 1112 invlcaddr(PADDR1); 1113 PMAP1changedcpu++; 1114 } else 1115#endif 1116 PMAP1unchanged++; 1117 return (PADDR1 + (i386_btop(va) & (NPTEPG - 1))); 1118 } 1119 return (0); 1120} 1121 1122/* 1123 * Routine: pmap_extract 1124 * Function: 1125 * Extract the physical page address associated 1126 * with the given map/virtual_address pair. 1127 */ 1128vm_paddr_t 1129pmap_extract(pmap_t pmap, vm_offset_t va) 1130{ 1131 vm_paddr_t rtval; 1132 pt_entry_t *pte; 1133 pd_entry_t pde; 1134 1135 rtval = 0; 1136 PMAP_LOCK(pmap); 1137 pde = pmap->pm_pdir[va >> PDRSHIFT]; 1138 if (pde != 0) { 1139 if ((pde & PG_PS) != 0) 1140 rtval = (pde & PG_PS_FRAME) | (va & PDRMASK); 1141 else { 1142 pte = pmap_pte(pmap, va); 1143 rtval = (*pte & PG_FRAME) | (va & PAGE_MASK); 1144 pmap_pte_release(pte); 1145 } 1146 } 1147 PMAP_UNLOCK(pmap); 1148 return (rtval); 1149} 1150 1151/* 1152 * Routine: pmap_extract_and_hold 1153 * Function: 1154 * Atomically extract and hold the physical page 1155 * with the given pmap and virtual address pair 1156 * if that mapping permits the given protection. 1157 */ 1158vm_page_t 1159pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot) 1160{ 1161 pd_entry_t pde; 1162 pt_entry_t pte; 1163 vm_page_t m; 1164 1165 m = NULL; 1166 vm_page_lock_queues(); 1167 PMAP_LOCK(pmap); 1168 pde = *pmap_pde(pmap, va); 1169 if (pde != 0) { 1170 if (pde & PG_PS) { 1171 if ((pde & PG_RW) || (prot & VM_PROT_WRITE) == 0) { 1172 m = PHYS_TO_VM_PAGE((pde & PG_PS_FRAME) | 1173 (va & PDRMASK)); 1174 vm_page_hold(m); 1175 } 1176 } else { 1177 sched_pin(); 1178 pte = *pmap_pte_quick(pmap, va); 1179 if (pte != 0 && 1180 ((pte & PG_RW) || (prot & VM_PROT_WRITE) == 0)) { 1181 m = PHYS_TO_VM_PAGE(pte & PG_FRAME); 1182 vm_page_hold(m); 1183 } 1184 sched_unpin(); 1185 } 1186 } 1187 vm_page_unlock_queues(); 1188 PMAP_UNLOCK(pmap); 1189 return (m); 1190} 1191 1192/*************************************************** 1193 * Low level mapping routines..... 1194 ***************************************************/ 1195 1196/* 1197 * Add a wired page to the kva. 1198 * Note: not SMP coherent. 1199 */ 1200PMAP_INLINE void 1201pmap_kenter(vm_offset_t va, vm_paddr_t pa) 1202{ 1203 pt_entry_t *pte; 1204 1205 pte = vtopte(va); 1206 pte_store(pte, pa | PG_RW | PG_V | pgeflag); 1207} 1208 1209static __inline void 1210pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode) 1211{ 1212 pt_entry_t *pte; 1213 1214 pte = vtopte(va); 1215 pte_store(pte, pa | PG_RW | PG_V | pgeflag | pmap_cache_bits(mode, 0)); 1216} 1217 1218/* 1219 * Remove a page from the kernel pagetables. 1220 * Note: not SMP coherent. 1221 */ 1222PMAP_INLINE void 1223pmap_kremove(vm_offset_t va) 1224{ 1225 pt_entry_t *pte; 1226 1227 pte = vtopte(va); 1228 pte_clear(pte); 1229} 1230 1231/* 1232 * Used to map a range of physical addresses into kernel 1233 * virtual address space. 1234 * 1235 * The value passed in '*virt' is a suggested virtual address for 1236 * the mapping. Architectures which can support a direct-mapped 1237 * physical to virtual region can return the appropriate address 1238 * within that region, leaving '*virt' unchanged. Other 1239 * architectures should map the pages starting at '*virt' and 1240 * update '*virt' with the first usable address after the mapped 1241 * region. 1242 */ 1243vm_offset_t 1244pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot) 1245{ 1246 vm_offset_t va, sva; 1247 1248 va = sva = *virt; 1249 while (start < end) { 1250 pmap_kenter(va, start); 1251 va += PAGE_SIZE; 1252 start += PAGE_SIZE; 1253 } 1254 pmap_invalidate_range(kernel_pmap, sva, va); 1255 *virt = va; 1256 return (sva); 1257} 1258 1259 1260/* 1261 * Add a list of wired pages to the kva 1262 * this routine is only used for temporary 1263 * kernel mappings that do not need to have 1264 * page modification or references recorded. 1265 * Note that old mappings are simply written 1266 * over. The page *must* be wired. 1267 * Note: SMP coherent. Uses a ranged shootdown IPI. 1268 */ 1269void 1270pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count) 1271{ 1272 pt_entry_t *endpte, oldpte, *pte; 1273 1274 oldpte = 0; 1275 pte = vtopte(sva); 1276 endpte = pte + count; 1277 while (pte < endpte) { 1278 oldpte |= *pte; 1279 pte_store(pte, VM_PAGE_TO_PHYS(*ma) | pgeflag | 1280 pmap_cache_bits((*ma)->md.pat_mode, 0) | PG_RW | PG_V); 1281 pte++; 1282 ma++; 1283 } 1284 if ((oldpte & PG_V) != 0) 1285 pmap_invalidate_range(kernel_pmap, sva, sva + count * 1286 PAGE_SIZE); 1287} 1288 1289/* 1290 * This routine tears out page mappings from the 1291 * kernel -- it is meant only for temporary mappings. 1292 * Note: SMP coherent. Uses a ranged shootdown IPI. 1293 */ 1294void 1295pmap_qremove(vm_offset_t sva, int count) 1296{ 1297 vm_offset_t va; 1298 1299 va = sva; 1300 while (count-- > 0) { 1301 pmap_kremove(va); 1302 va += PAGE_SIZE; 1303 } 1304 pmap_invalidate_range(kernel_pmap, sva, va); 1305} 1306 1307/*************************************************** 1308 * Page table page management routines..... 1309 ***************************************************/ 1310static __inline void 1311pmap_free_zero_pages(vm_page_t free) 1312{ 1313 vm_page_t m; 1314 1315 while (free != NULL) { 1316 m = free; 1317 free = m->right; 1318 /* Preserve the page's PG_ZERO setting. */ 1319 vm_page_free_toq(m); 1320 } 1321} 1322 1323/* 1324 * Schedule the specified unused page table page to be freed. Specifically, 1325 * add the page to the specified list of pages that will be released to the 1326 * physical memory manager after the TLB has been updated. 1327 */ 1328static __inline void 1329pmap_add_delayed_free_list(vm_page_t m, vm_page_t *free, boolean_t set_PG_ZERO) 1330{ 1331 1332 if (set_PG_ZERO) 1333 m->flags |= PG_ZERO; 1334 else 1335 m->flags &= ~PG_ZERO; 1336 m->right = *free; 1337 *free = m; 1338} 1339 1340/* 1341 * Inserts the specified page table page into the specified pmap's collection 1342 * of idle page table pages. Each of a pmap's page table pages is responsible 1343 * for mapping a distinct range of virtual addresses. The pmap's collection is 1344 * ordered by this virtual address range. 1345 */ 1346static void 1347pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte) 1348{ 1349 vm_page_t root; 1350 1351 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1352 root = pmap->pm_root; 1353 if (root == NULL) { 1354 mpte->left = NULL; 1355 mpte->right = NULL; 1356 } else { 1357 root = vm_page_splay(mpte->pindex, root); 1358 if (mpte->pindex < root->pindex) { 1359 mpte->left = root->left; 1360 mpte->right = root; 1361 root->left = NULL; 1362 } else if (mpte->pindex == root->pindex) 1363 panic("pmap_insert_pt_page: pindex already inserted"); 1364 else { 1365 mpte->right = root->right; 1366 mpte->left = root; 1367 root->right = NULL; 1368 } 1369 } 1370 pmap->pm_root = mpte; 1371} 1372 1373/* 1374 * Looks for a page table page mapping the specified virtual address in the 1375 * specified pmap's collection of idle page table pages. Returns NULL if there 1376 * is no page table page corresponding to the specified virtual address. 1377 */ 1378static vm_page_t 1379pmap_lookup_pt_page(pmap_t pmap, vm_offset_t va) 1380{ 1381 vm_page_t mpte; 1382 vm_pindex_t pindex = va >> PDRSHIFT; 1383 1384 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1385 if ((mpte = pmap->pm_root) != NULL && mpte->pindex != pindex) { 1386 mpte = vm_page_splay(pindex, mpte); 1387 if ((pmap->pm_root = mpte)->pindex != pindex) 1388 mpte = NULL; 1389 } 1390 return (mpte); 1391} 1392 1393/* 1394 * Removes the specified page table page from the specified pmap's collection 1395 * of idle page table pages. The specified page table page must be a member of 1396 * the pmap's collection. 1397 */ 1398static void 1399pmap_remove_pt_page(pmap_t pmap, vm_page_t mpte) 1400{ 1401 vm_page_t root; 1402 1403 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1404 if (mpte != pmap->pm_root) 1405 vm_page_splay(mpte->pindex, pmap->pm_root); 1406 if (mpte->left == NULL) 1407 root = mpte->right; 1408 else { 1409 root = vm_page_splay(mpte->pindex, mpte->left); 1410 root->right = mpte->right; 1411 } 1412 pmap->pm_root = root; 1413} 1414 1415/* 1416 * This routine unholds page table pages, and if the hold count 1417 * drops to zero, then it decrements the wire count. 1418 */ 1419static __inline int 1420pmap_unwire_pte_hold(pmap_t pmap, vm_page_t m, vm_page_t *free) 1421{ 1422 1423 --m->wire_count; 1424 if (m->wire_count == 0) 1425 return _pmap_unwire_pte_hold(pmap, m, free); 1426 else 1427 return 0; 1428} 1429 1430static int 1431_pmap_unwire_pte_hold(pmap_t pmap, vm_page_t m, vm_page_t *free) 1432{ 1433 vm_offset_t pteva; 1434 1435 /* 1436 * unmap the page table page 1437 */ 1438 pmap->pm_pdir[m->pindex] = 0; 1439 --pmap->pm_stats.resident_count; 1440 1441 /* 1442 * This is a release store so that the ordinary store unmapping 1443 * the page table page is globally performed before TLB shoot- 1444 * down is begun. 1445 */ 1446 atomic_subtract_rel_int(&cnt.v_wire_count, 1); 1447 1448 /* 1449 * Do an invltlb to make the invalidated mapping 1450 * take effect immediately. 1451 */ 1452 pteva = VM_MAXUSER_ADDRESS + i386_ptob(m->pindex); 1453 pmap_invalidate_page(pmap, pteva); 1454 1455 /* 1456 * Put page on a list so that it is released after 1457 * *ALL* TLB shootdown is done 1458 */ 1459 pmap_add_delayed_free_list(m, free, TRUE); 1460 1461 return 1; 1462} 1463 1464/* 1465 * After removing a page table entry, this routine is used to 1466 * conditionally free the page, and manage the hold/wire counts. 1467 */ 1468static int 1469pmap_unuse_pt(pmap_t pmap, vm_offset_t va, vm_page_t *free) 1470{ 1471 pd_entry_t ptepde; 1472 vm_page_t mpte; 1473 1474 if (va >= VM_MAXUSER_ADDRESS) 1475 return 0; 1476 ptepde = *pmap_pde(pmap, va); 1477 mpte = PHYS_TO_VM_PAGE(ptepde & PG_FRAME); 1478 return pmap_unwire_pte_hold(pmap, mpte, free); 1479} 1480 1481void 1482pmap_pinit0(pmap_t pmap) 1483{ 1484 1485 PMAP_LOCK_INIT(pmap); 1486 pmap->pm_pdir = (pd_entry_t *)(KERNBASE + (vm_offset_t)IdlePTD); 1487#ifdef PAE 1488 pmap->pm_pdpt = (pdpt_entry_t *)(KERNBASE + (vm_offset_t)IdlePDPT); 1489#endif 1490 pmap->pm_root = NULL; 1491 pmap->pm_active = 0; 1492 PCPU_SET(curpmap, pmap); 1493 TAILQ_INIT(&pmap->pm_pvchunk); 1494 bzero(&pmap->pm_stats, sizeof pmap->pm_stats); 1495 mtx_lock_spin(&allpmaps_lock); 1496 LIST_INSERT_HEAD(&allpmaps, pmap, pm_list); 1497 mtx_unlock_spin(&allpmaps_lock); 1498} 1499 1500/* 1501 * Initialize a preallocated and zeroed pmap structure, 1502 * such as one in a vmspace structure. 1503 */ 1504int 1505pmap_pinit(pmap_t pmap) 1506{ 1507 vm_page_t m, ptdpg[NPGPTD]; 1508 vm_paddr_t pa; 1509 static int color; 1510 int i; 1511 1512 PMAP_LOCK_INIT(pmap); 1513 1514 /* 1515 * No need to allocate page table space yet but we do need a valid 1516 * page directory table. 1517 */ 1518 if (pmap->pm_pdir == NULL) { 1519 pmap->pm_pdir = (pd_entry_t *)kmem_alloc_nofault(kernel_map, 1520 NBPTD); 1521 1522 if (pmap->pm_pdir == NULL) { 1523 PMAP_LOCK_DESTROY(pmap); 1524 return (0); 1525 } 1526#ifdef PAE 1527 pmap->pm_pdpt = uma_zalloc(pdptzone, M_WAITOK | M_ZERO); 1528 KASSERT(((vm_offset_t)pmap->pm_pdpt & 1529 ((NPGPTD * sizeof(pdpt_entry_t)) - 1)) == 0, 1530 ("pmap_pinit: pdpt misaligned")); 1531 KASSERT(pmap_kextract((vm_offset_t)pmap->pm_pdpt) < (4ULL<<30), 1532 ("pmap_pinit: pdpt above 4g")); 1533#endif 1534 pmap->pm_root = NULL; 1535 } 1536 KASSERT(pmap->pm_root == NULL, 1537 ("pmap_pinit: pmap has reserved page table page(s)")); 1538 1539 /* 1540 * allocate the page directory page(s) 1541 */ 1542 for (i = 0; i < NPGPTD;) { 1543 m = vm_page_alloc(NULL, color++, 1544 VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | 1545 VM_ALLOC_ZERO); 1546 if (m == NULL) 1547 VM_WAIT; 1548 else { 1549 ptdpg[i++] = m; 1550 } 1551 } 1552 1553 pmap_qenter((vm_offset_t)pmap->pm_pdir, ptdpg, NPGPTD); 1554 1555 for (i = 0; i < NPGPTD; i++) { 1556 if ((ptdpg[i]->flags & PG_ZERO) == 0) 1557 bzero(pmap->pm_pdir + (i * NPDEPG), PAGE_SIZE); 1558 } 1559 1560 mtx_lock_spin(&allpmaps_lock); 1561 LIST_INSERT_HEAD(&allpmaps, pmap, pm_list); 1562 mtx_unlock_spin(&allpmaps_lock); 1563 /* Wire in kernel global address entries. */ 1564 bcopy(PTD + KPTDI, pmap->pm_pdir + KPTDI, nkpt * sizeof(pd_entry_t)); 1565 1566 /* install self-referential address mapping entry(s) */ 1567 for (i = 0; i < NPGPTD; i++) { 1568 pa = VM_PAGE_TO_PHYS(ptdpg[i]); 1569 pmap->pm_pdir[PTDPTDI + i] = pa | PG_V | PG_RW | PG_A | PG_M; 1570#ifdef PAE 1571 pmap->pm_pdpt[i] = pa | PG_V; 1572#endif 1573 } 1574 1575 pmap->pm_active = 0; 1576 TAILQ_INIT(&pmap->pm_pvchunk); 1577 bzero(&pmap->pm_stats, sizeof pmap->pm_stats); 1578 1579 return (1); 1580} 1581 1582/* 1583 * this routine is called if the page table page is not 1584 * mapped correctly. 1585 */ 1586static vm_page_t 1587_pmap_allocpte(pmap_t pmap, unsigned ptepindex, int flags) 1588{ 1589 vm_paddr_t ptepa; 1590 vm_page_t m; 1591 1592 KASSERT((flags & (M_NOWAIT | M_WAITOK)) == M_NOWAIT || 1593 (flags & (M_NOWAIT | M_WAITOK)) == M_WAITOK, 1594 ("_pmap_allocpte: flags is neither M_NOWAIT nor M_WAITOK")); 1595 1596 /* 1597 * Allocate a page table page. 1598 */ 1599 if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ | 1600 VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) { 1601 if (flags & M_WAITOK) { 1602 PMAP_UNLOCK(pmap); 1603 vm_page_unlock_queues(); 1604 VM_WAIT; 1605 vm_page_lock_queues(); 1606 PMAP_LOCK(pmap); 1607 } 1608 1609 /* 1610 * Indicate the need to retry. While waiting, the page table 1611 * page may have been allocated. 1612 */ 1613 return (NULL); 1614 } 1615 if ((m->flags & PG_ZERO) == 0) 1616 pmap_zero_page(m); 1617 1618 /* 1619 * Map the pagetable page into the process address space, if 1620 * it isn't already there. 1621 */ 1622 1623 pmap->pm_stats.resident_count++; 1624 1625 ptepa = VM_PAGE_TO_PHYS(m); 1626 pmap->pm_pdir[ptepindex] = 1627 (pd_entry_t) (ptepa | PG_U | PG_RW | PG_V | PG_A | PG_M); 1628 1629 return m; 1630} 1631 1632static vm_page_t 1633pmap_allocpte(pmap_t pmap, vm_offset_t va, int flags) 1634{ 1635 unsigned ptepindex; 1636 pd_entry_t ptepa; 1637 vm_page_t m; 1638 1639 KASSERT((flags & (M_NOWAIT | M_WAITOK)) == M_NOWAIT || 1640 (flags & (M_NOWAIT | M_WAITOK)) == M_WAITOK, 1641 ("pmap_allocpte: flags is neither M_NOWAIT nor M_WAITOK")); 1642 1643 /* 1644 * Calculate pagetable page index 1645 */ 1646 ptepindex = va >> PDRSHIFT; 1647retry: 1648 /* 1649 * Get the page directory entry 1650 */ 1651 ptepa = pmap->pm_pdir[ptepindex]; 1652 1653 /* 1654 * This supports switching from a 4MB page to a 1655 * normal 4K page. 1656 */ 1657 if (ptepa & PG_PS) { 1658 (void)pmap_demote_pde(pmap, &pmap->pm_pdir[ptepindex], va); 1659 ptepa = pmap->pm_pdir[ptepindex]; 1660 } 1661 1662 /* 1663 * If the page table page is mapped, we just increment the 1664 * hold count, and activate it. 1665 */ 1666 if (ptepa) { 1667 m = PHYS_TO_VM_PAGE(ptepa & PG_FRAME); 1668 m->wire_count++; 1669 } else { 1670 /* 1671 * Here if the pte page isn't mapped, or if it has 1672 * been deallocated. 1673 */ 1674 m = _pmap_allocpte(pmap, ptepindex, flags); 1675 if (m == NULL && (flags & M_WAITOK)) 1676 goto retry; 1677 } 1678 return (m); 1679} 1680 1681 1682/*************************************************** 1683* Pmap allocation/deallocation routines. 1684 ***************************************************/ 1685 1686#ifdef SMP 1687/* 1688 * Deal with a SMP shootdown of other users of the pmap that we are 1689 * trying to dispose of. This can be a bit hairy. 1690 */ 1691static cpumask_t *lazymask; 1692static u_int lazyptd; 1693static volatile u_int lazywait; 1694 1695void pmap_lazyfix_action(void); 1696 1697void 1698pmap_lazyfix_action(void) 1699{ 1700 cpumask_t mymask = PCPU_GET(cpumask); 1701 1702#ifdef COUNT_IPIS 1703 (*ipi_lazypmap_counts[PCPU_GET(cpuid)])++; 1704#endif 1705 if (rcr3() == lazyptd) 1706 load_cr3(PCPU_GET(curpcb)->pcb_cr3); 1707 atomic_clear_int(lazymask, mymask); 1708 atomic_store_rel_int(&lazywait, 1); 1709} 1710 1711static void 1712pmap_lazyfix_self(cpumask_t mymask) 1713{ 1714 1715 if (rcr3() == lazyptd) 1716 load_cr3(PCPU_GET(curpcb)->pcb_cr3); 1717 atomic_clear_int(lazymask, mymask); 1718} 1719 1720 1721static void 1722pmap_lazyfix(pmap_t pmap) 1723{ 1724 cpumask_t mymask, mask; 1725 u_int spins; 1726 1727 while ((mask = pmap->pm_active) != 0) { 1728 spins = 50000000; 1729 mask = mask & -mask; /* Find least significant set bit */ 1730 mtx_lock_spin(&smp_ipi_mtx); 1731#ifdef PAE 1732 lazyptd = vtophys(pmap->pm_pdpt); 1733#else 1734 lazyptd = vtophys(pmap->pm_pdir); 1735#endif 1736 mymask = PCPU_GET(cpumask); 1737 if (mask == mymask) { 1738 lazymask = &pmap->pm_active; 1739 pmap_lazyfix_self(mymask); 1740 } else { 1741 atomic_store_rel_int((u_int *)&lazymask, 1742 (u_int)&pmap->pm_active); 1743 atomic_store_rel_int(&lazywait, 0); 1744 ipi_selected(mask, IPI_LAZYPMAP); 1745 while (lazywait == 0) { 1746 ia32_pause(); 1747 if (--spins == 0) 1748 break; 1749 } 1750 } 1751 mtx_unlock_spin(&smp_ipi_mtx); 1752 if (spins == 0) 1753 printf("pmap_lazyfix: spun for 50000000\n"); 1754 } 1755} 1756 1757#else /* SMP */ 1758 1759/* 1760 * Cleaning up on uniprocessor is easy. For various reasons, we're 1761 * unlikely to have to even execute this code, including the fact 1762 * that the cleanup is deferred until the parent does a wait(2), which 1763 * means that another userland process has run. 1764 */ 1765static void 1766pmap_lazyfix(pmap_t pmap) 1767{ 1768 u_int cr3; 1769 1770 cr3 = vtophys(pmap->pm_pdir); 1771 if (cr3 == rcr3()) { 1772 load_cr3(PCPU_GET(curpcb)->pcb_cr3); 1773 pmap->pm_active &= ~(PCPU_GET(cpumask)); 1774 } 1775} 1776#endif /* SMP */ 1777 1778/* 1779 * Release any resources held by the given physical map. 1780 * Called when a pmap initialized by pmap_pinit is being released. 1781 * Should only be called if the map contains no valid mappings. 1782 */ 1783void 1784pmap_release(pmap_t pmap) 1785{ 1786 vm_page_t m, ptdpg[NPGPTD]; 1787 int i; 1788 1789 KASSERT(pmap->pm_stats.resident_count == 0, 1790 ("pmap_release: pmap resident count %ld != 0", 1791 pmap->pm_stats.resident_count)); 1792 KASSERT(pmap->pm_root == NULL, 1793 ("pmap_release: pmap has reserved page table page(s)")); 1794 1795 pmap_lazyfix(pmap); 1796 mtx_lock_spin(&allpmaps_lock); 1797 LIST_REMOVE(pmap, pm_list); 1798 mtx_unlock_spin(&allpmaps_lock); 1799 1800 for (i = 0; i < NPGPTD; i++) 1801 ptdpg[i] = PHYS_TO_VM_PAGE(pmap->pm_pdir[PTDPTDI + i] & 1802 PG_FRAME); 1803 1804 bzero(pmap->pm_pdir + PTDPTDI, (nkpt + NPGPTD) * 1805 sizeof(*pmap->pm_pdir)); 1806 1807 pmap_qremove((vm_offset_t)pmap->pm_pdir, NPGPTD); 1808 1809 for (i = 0; i < NPGPTD; i++) { 1810 m = ptdpg[i]; 1811#ifdef PAE 1812 KASSERT(VM_PAGE_TO_PHYS(m) == (pmap->pm_pdpt[i] & PG_FRAME), 1813 ("pmap_release: got wrong ptd page")); 1814#endif 1815 m->wire_count--; 1816 atomic_subtract_int(&cnt.v_wire_count, 1); 1817 vm_page_free_zero(m); 1818 } 1819 PMAP_LOCK_DESTROY(pmap); 1820} 1821 1822static int 1823kvm_size(SYSCTL_HANDLER_ARGS) 1824{ 1825 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - KERNBASE; 1826 1827 return sysctl_handle_long(oidp, &ksize, 0, req); 1828} 1829SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG|CTLFLAG_RD, 1830 0, 0, kvm_size, "IU", "Size of KVM"); 1831 1832static int 1833kvm_free(SYSCTL_HANDLER_ARGS) 1834{ 1835 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end; 1836 1837 return sysctl_handle_long(oidp, &kfree, 0, req); 1838} 1839SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG|CTLFLAG_RD, 1840 0, 0, kvm_free, "IU", "Amount of KVM free"); 1841 1842/* 1843 * grow the number of kernel page table entries, if needed 1844 */ 1845void 1846pmap_growkernel(vm_offset_t addr) 1847{ 1848 struct pmap *pmap; 1849 vm_paddr_t ptppaddr; 1850 vm_page_t nkpg; 1851 pd_entry_t newpdir; 1852 pt_entry_t *pde; 1853 boolean_t updated_PTD; 1854 1855 mtx_assert(&kernel_map->system_mtx, MA_OWNED); 1856 if (kernel_vm_end == 0) { 1857 kernel_vm_end = KERNBASE; 1858 nkpt = 0; 1859 while (pdir_pde(PTD, kernel_vm_end)) { 1860 kernel_vm_end = (kernel_vm_end + PAGE_SIZE * NPTEPG) & ~(PAGE_SIZE * NPTEPG - 1); 1861 nkpt++; 1862 if (kernel_vm_end - 1 >= kernel_map->max_offset) { 1863 kernel_vm_end = kernel_map->max_offset; 1864 break; 1865 } 1866 } 1867 } 1868 addr = roundup2(addr, PAGE_SIZE * NPTEPG); 1869 if (addr - 1 >= kernel_map->max_offset) 1870 addr = kernel_map->max_offset; 1871 while (kernel_vm_end < addr) { 1872 if (pdir_pde(PTD, kernel_vm_end)) { 1873 kernel_vm_end = (kernel_vm_end + PAGE_SIZE * NPTEPG) & ~(PAGE_SIZE * NPTEPG - 1); 1874 if (kernel_vm_end - 1 >= kernel_map->max_offset) { 1875 kernel_vm_end = kernel_map->max_offset; 1876 break; 1877 } 1878 continue; 1879 } 1880 1881 nkpg = vm_page_alloc(NULL, kernel_vm_end >> PDRSHIFT, 1882 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | 1883 VM_ALLOC_ZERO); 1884 if (nkpg == NULL) 1885 panic("pmap_growkernel: no memory to grow kernel"); 1886 1887 nkpt++; 1888 1889 if ((nkpg->flags & PG_ZERO) == 0) 1890 pmap_zero_page(nkpg); 1891 ptppaddr = VM_PAGE_TO_PHYS(nkpg); 1892 newpdir = (pd_entry_t) (ptppaddr | PG_V | PG_RW | PG_A | PG_M); 1893 pdir_pde(KPTD, kernel_vm_end) = pgeflag | newpdir; 1894 1895 updated_PTD = FALSE; 1896 mtx_lock_spin(&allpmaps_lock); 1897 LIST_FOREACH(pmap, &allpmaps, pm_list) { 1898 if ((pmap->pm_pdir[PTDPTDI] & PG_FRAME) == (PTDpde[0] & 1899 PG_FRAME)) 1900 updated_PTD = TRUE; 1901 pde = pmap_pde(pmap, kernel_vm_end); 1902 pde_store(pde, newpdir); 1903 } 1904 mtx_unlock_spin(&allpmaps_lock); 1905 KASSERT(updated_PTD, 1906 ("pmap_growkernel: current page table is not in allpmaps")); 1907 kernel_vm_end = (kernel_vm_end + PAGE_SIZE * NPTEPG) & ~(PAGE_SIZE * NPTEPG - 1); 1908 if (kernel_vm_end - 1 >= kernel_map->max_offset) { 1909 kernel_vm_end = kernel_map->max_offset; 1910 break; 1911 } 1912 } 1913} 1914 1915 1916/*************************************************** 1917 * page management routines. 1918 ***************************************************/ 1919 1920CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE); 1921CTASSERT(_NPCM == 11); 1922 1923static __inline struct pv_chunk * 1924pv_to_chunk(pv_entry_t pv) 1925{ 1926 1927 return (struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK); 1928} 1929 1930#define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap) 1931 1932#define PC_FREE0_9 0xfffffffful /* Free values for index 0 through 9 */ 1933#define PC_FREE10 0x0000fffful /* Free values for index 10 */ 1934 1935static uint32_t pc_freemask[11] = { 1936 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9, 1937 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9, 1938 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9, 1939 PC_FREE0_9, PC_FREE10 1940}; 1941 1942SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0, 1943 "Current number of pv entries"); 1944 1945#ifdef PV_STATS 1946static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail; 1947 1948SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0, 1949 "Current number of pv entry chunks"); 1950SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0, 1951 "Current number of pv entry chunks allocated"); 1952SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0, 1953 "Current number of pv entry chunks frees"); 1954SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0, 1955 "Number of times tried to get a chunk page but failed."); 1956 1957static long pv_entry_frees, pv_entry_allocs; 1958static int pv_entry_spare; 1959 1960SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0, 1961 "Current number of pv entry frees"); 1962SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0, 1963 "Current number of pv entry allocs"); 1964SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0, 1965 "Current number of spare pv entries"); 1966 1967static int pmap_collect_inactive, pmap_collect_active; 1968 1969SYSCTL_INT(_vm_pmap, OID_AUTO, pmap_collect_inactive, CTLFLAG_RD, &pmap_collect_inactive, 0, 1970 "Current number times pmap_collect called on inactive queue"); 1971SYSCTL_INT(_vm_pmap, OID_AUTO, pmap_collect_active, CTLFLAG_RD, &pmap_collect_active, 0, 1972 "Current number times pmap_collect called on active queue"); 1973#endif 1974 1975/* 1976 * We are in a serious low memory condition. Resort to 1977 * drastic measures to free some pages so we can allocate 1978 * another pv entry chunk. This is normally called to 1979 * unmap inactive pages, and if necessary, active pages. 1980 */ 1981static void 1982pmap_collect(pmap_t locked_pmap, struct vpgqueues *vpq) 1983{ 1984 struct md_page *pvh; 1985 pd_entry_t *pde; 1986 pmap_t pmap; 1987 pt_entry_t *pte, tpte; 1988 pv_entry_t next_pv, pv; 1989 vm_offset_t va; 1990 vm_page_t m, free; 1991 1992 sched_pin(); 1993 TAILQ_FOREACH(m, &vpq->pl, pageq) { 1994 if (m->hold_count || m->busy) 1995 continue; 1996 TAILQ_FOREACH_SAFE(pv, &m->md.pv_list, pv_list, next_pv) { 1997 va = pv->pv_va; 1998 pmap = PV_PMAP(pv); 1999 /* Avoid deadlock and lock recursion. */ 2000 if (pmap > locked_pmap) 2001 PMAP_LOCK(pmap); 2002 else if (pmap != locked_pmap && !PMAP_TRYLOCK(pmap)) 2003 continue; 2004 pmap->pm_stats.resident_count--; 2005 pde = pmap_pde(pmap, va); 2006 KASSERT((*pde & PG_PS) == 0, ("pmap_collect: found" 2007 " a 4mpage in page %p's pv list", m)); 2008 pte = pmap_pte_quick(pmap, va); 2009 tpte = pte_load_clear(pte); 2010 KASSERT((tpte & PG_W) == 0, 2011 ("pmap_collect: wired pte %#jx", (uintmax_t)tpte)); 2012 if (tpte & PG_A) 2013 vm_page_flag_set(m, PG_REFERENCED); 2014 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) 2015 vm_page_dirty(m); 2016 free = NULL; 2017 pmap_unuse_pt(pmap, va, &free); 2018 pmap_invalidate_page(pmap, va); 2019 pmap_free_zero_pages(free); 2020 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list); 2021 if (TAILQ_EMPTY(&m->md.pv_list)) { 2022 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 2023 if (TAILQ_EMPTY(&pvh->pv_list)) 2024 vm_page_flag_clear(m, PG_WRITEABLE); 2025 } 2026 free_pv_entry(pmap, pv); 2027 if (pmap != locked_pmap) 2028 PMAP_UNLOCK(pmap); 2029 } 2030 } 2031 sched_unpin(); 2032} 2033 2034 2035/* 2036 * free the pv_entry back to the free list 2037 */ 2038static void 2039free_pv_entry(pmap_t pmap, pv_entry_t pv) 2040{ 2041 vm_page_t m; 2042 struct pv_chunk *pc; 2043 int idx, field, bit; 2044 2045 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2046 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2047 PV_STAT(pv_entry_frees++); 2048 PV_STAT(pv_entry_spare++); 2049 pv_entry_count--; 2050 pc = pv_to_chunk(pv); 2051 idx = pv - &pc->pc_pventry[0]; 2052 field = idx / 32; 2053 bit = idx % 32; 2054 pc->pc_map[field] |= 1ul << bit; 2055 /* move to head of list */ 2056 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 2057 for (idx = 0; idx < _NPCM; idx++) 2058 if (pc->pc_map[idx] != pc_freemask[idx]) { 2059 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list); 2060 return; 2061 } 2062 PV_STAT(pv_entry_spare -= _NPCPV); 2063 PV_STAT(pc_chunk_count--); 2064 PV_STAT(pc_chunk_frees++); 2065 /* entire chunk is free, return it */ 2066 m = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc)); 2067 pmap_qremove((vm_offset_t)pc, 1); 2068 vm_page_unwire(m, 0); 2069 vm_page_free(m); 2070 pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc); 2071} 2072 2073/* 2074 * get a new pv_entry, allocating a block from the system 2075 * when needed. 2076 */ 2077static pv_entry_t 2078get_pv_entry(pmap_t pmap, int try) 2079{ 2080 static const struct timeval printinterval = { 60, 0 }; 2081 static struct timeval lastprint; 2082 static vm_pindex_t colour; 2083 struct vpgqueues *pq; 2084 int bit, field; 2085 pv_entry_t pv; 2086 struct pv_chunk *pc; 2087 vm_page_t m; 2088 2089 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2090 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2091 PV_STAT(pv_entry_allocs++); 2092 pv_entry_count++; 2093 if (pv_entry_count > pv_entry_high_water) 2094 if (ratecheck(&lastprint, &printinterval)) 2095 printf("Approaching the limit on PV entries, consider " 2096 "increasing either the vm.pmap.shpgperproc or the " 2097 "vm.pmap.pv_entry_max tunable.\n"); 2098 pq = NULL; 2099retry: 2100 pc = TAILQ_FIRST(&pmap->pm_pvchunk); 2101 if (pc != NULL) { 2102 for (field = 0; field < _NPCM; field++) { 2103 if (pc->pc_map[field]) { 2104 bit = bsfl(pc->pc_map[field]); 2105 break; 2106 } 2107 } 2108 if (field < _NPCM) { 2109 pv = &pc->pc_pventry[field * 32 + bit]; 2110 pc->pc_map[field] &= ~(1ul << bit); 2111 /* If this was the last item, move it to tail */ 2112 for (field = 0; field < _NPCM; field++) 2113 if (pc->pc_map[field] != 0) { 2114 PV_STAT(pv_entry_spare--); 2115 return (pv); /* not full, return */ 2116 } 2117 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 2118 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list); 2119 PV_STAT(pv_entry_spare--); 2120 return (pv); 2121 } 2122 } 2123 /* 2124 * Access to the ptelist "pv_vafree" is synchronized by the page 2125 * queues lock. If "pv_vafree" is currently non-empty, it will 2126 * remain non-empty until pmap_ptelist_alloc() completes. 2127 */ 2128 if (pv_vafree == 0 || (m = vm_page_alloc(NULL, colour, (pq == 2129 &vm_page_queues[PQ_ACTIVE] ? VM_ALLOC_SYSTEM : VM_ALLOC_NORMAL) | 2130 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) { 2131 if (try) { 2132 pv_entry_count--; 2133 PV_STAT(pc_chunk_tryfail++); 2134 return (NULL); 2135 } 2136 /* 2137 * Reclaim pv entries: At first, destroy mappings to 2138 * inactive pages. After that, if a pv chunk entry 2139 * is still needed, destroy mappings to active pages. 2140 */ 2141 if (pq == NULL) { 2142 PV_STAT(pmap_collect_inactive++); 2143 pq = &vm_page_queues[PQ_INACTIVE]; 2144 } else if (pq == &vm_page_queues[PQ_INACTIVE]) { 2145 PV_STAT(pmap_collect_active++); 2146 pq = &vm_page_queues[PQ_ACTIVE]; 2147 } else 2148 panic("get_pv_entry: increase vm.pmap.shpgperproc"); 2149 pmap_collect(pmap, pq); 2150 goto retry; 2151 } 2152 PV_STAT(pc_chunk_count++); 2153 PV_STAT(pc_chunk_allocs++); 2154 colour++; 2155 pc = (struct pv_chunk *)pmap_ptelist_alloc(&pv_vafree); 2156 pmap_qenter((vm_offset_t)pc, &m, 1); 2157 pc->pc_pmap = pmap; 2158 pc->pc_map[0] = pc_freemask[0] & ~1ul; /* preallocated bit 0 */ 2159 for (field = 1; field < _NPCM; field++) 2160 pc->pc_map[field] = pc_freemask[field]; 2161 pv = &pc->pc_pventry[0]; 2162 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list); 2163 PV_STAT(pv_entry_spare += _NPCPV - 1); 2164 return (pv); 2165} 2166 2167static __inline pv_entry_t 2168pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va) 2169{ 2170 pv_entry_t pv; 2171 2172 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2173 TAILQ_FOREACH(pv, &pvh->pv_list, pv_list) { 2174 if (pmap == PV_PMAP(pv) && va == pv->pv_va) { 2175 TAILQ_REMOVE(&pvh->pv_list, pv, pv_list); 2176 break; 2177 } 2178 } 2179 return (pv); 2180} 2181 2182static void 2183pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa) 2184{ 2185 struct md_page *pvh; 2186 pv_entry_t pv; 2187 vm_offset_t va_last; 2188 vm_page_t m; 2189 2190 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2191 KASSERT((pa & PDRMASK) == 0, 2192 ("pmap_pv_demote_pde: pa is not 4mpage aligned")); 2193 2194 /* 2195 * Transfer the 4mpage's pv entry for this mapping to the first 2196 * page's pv list. 2197 */ 2198 pvh = pa_to_pvh(pa); 2199 va = trunc_4mpage(va); 2200 pv = pmap_pvh_remove(pvh, pmap, va); 2201 KASSERT(pv != NULL, ("pmap_pv_demote_pde: pv not found")); 2202 m = PHYS_TO_VM_PAGE(pa); 2203 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list); 2204 /* Instantiate the remaining NPTEPG - 1 pv entries. */ 2205 va_last = va + NBPDR - PAGE_SIZE; 2206 do { 2207 m++; 2208 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 2209 ("pmap_pv_demote_pde: page %p is not managed", m)); 2210 va += PAGE_SIZE; 2211 pmap_insert_entry(pmap, va, m); 2212 } while (va < va_last); 2213} 2214 2215static void 2216pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa) 2217{ 2218 struct md_page *pvh; 2219 pv_entry_t pv; 2220 vm_offset_t va_last; 2221 vm_page_t m; 2222 2223 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2224 KASSERT((pa & PDRMASK) == 0, 2225 ("pmap_pv_promote_pde: pa is not 4mpage aligned")); 2226 2227 /* 2228 * Transfer the first page's pv entry for this mapping to the 2229 * 4mpage's pv list. Aside from avoiding the cost of a call 2230 * to get_pv_entry(), a transfer avoids the possibility that 2231 * get_pv_entry() calls pmap_collect() and that pmap_collect() 2232 * removes one of the mappings that is being promoted. 2233 */ 2234 m = PHYS_TO_VM_PAGE(pa); 2235 va = trunc_4mpage(va); 2236 pv = pmap_pvh_remove(&m->md, pmap, va); 2237 KASSERT(pv != NULL, ("pmap_pv_promote_pde: pv not found")); 2238 pvh = pa_to_pvh(pa); 2239 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_list); 2240 /* Free the remaining NPTEPG - 1 pv entries. */ 2241 va_last = va + NBPDR - PAGE_SIZE; 2242 do { 2243 m++; 2244 va += PAGE_SIZE; 2245 pmap_pvh_free(&m->md, pmap, va); 2246 } while (va < va_last); 2247} 2248 2249static void 2250pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va) 2251{ 2252 pv_entry_t pv; 2253 2254 pv = pmap_pvh_remove(pvh, pmap, va); 2255 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found")); 2256 free_pv_entry(pmap, pv); 2257} 2258 2259static void 2260pmap_remove_entry(pmap_t pmap, vm_page_t m, vm_offset_t va) 2261{ 2262 struct md_page *pvh; 2263 2264 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2265 pmap_pvh_free(&m->md, pmap, va); 2266 if (TAILQ_EMPTY(&m->md.pv_list)) { 2267 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 2268 if (TAILQ_EMPTY(&pvh->pv_list)) 2269 vm_page_flag_clear(m, PG_WRITEABLE); 2270 } 2271} 2272 2273/* 2274 * Create a pv entry for page at pa for 2275 * (pmap, va). 2276 */ 2277static void 2278pmap_insert_entry(pmap_t pmap, vm_offset_t va, vm_page_t m) 2279{ 2280 pv_entry_t pv; 2281 2282 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2283 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2284 pv = get_pv_entry(pmap, FALSE); 2285 pv->pv_va = va; 2286 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list); 2287} 2288 2289/* 2290 * Conditionally create a pv entry. 2291 */ 2292static boolean_t 2293pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m) 2294{ 2295 pv_entry_t pv; 2296 2297 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2298 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2299 if (pv_entry_count < pv_entry_high_water && 2300 (pv = get_pv_entry(pmap, TRUE)) != NULL) { 2301 pv->pv_va = va; 2302 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list); 2303 return (TRUE); 2304 } else 2305 return (FALSE); 2306} 2307 2308/* 2309 * Create the pv entries for each of the pages within a superpage. 2310 */ 2311static boolean_t 2312pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa) 2313{ 2314 struct md_page *pvh; 2315 pv_entry_t pv; 2316 2317 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2318 if (pv_entry_count < pv_entry_high_water && 2319 (pv = get_pv_entry(pmap, TRUE)) != NULL) { 2320 pv->pv_va = va; 2321 pvh = pa_to_pvh(pa); 2322 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_list); 2323 return (TRUE); 2324 } else 2325 return (FALSE); 2326} 2327 2328/* 2329 * Fills a page table page with mappings to consecutive physical pages. 2330 */ 2331static void 2332pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte) 2333{ 2334 pt_entry_t *pte; 2335 2336 for (pte = firstpte; pte < firstpte + NPTEPG; pte++) { 2337 *pte = newpte; 2338 newpte += PAGE_SIZE; 2339 } 2340} 2341 2342/* 2343 * Tries to demote a 2- or 4MB page mapping. If demotion fails, the 2344 * 2- or 4MB page mapping is invalidated. 2345 */ 2346static boolean_t 2347pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va) 2348{ 2349 pd_entry_t newpde, oldpde; 2350 pmap_t allpmaps_entry; 2351 pt_entry_t *firstpte, newpte; 2352 vm_paddr_t mptepa; 2353 vm_page_t free, mpte; 2354 2355 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2356 oldpde = *pde; 2357 KASSERT((oldpde & (PG_PS | PG_V)) == (PG_PS | PG_V), 2358 ("pmap_demote_pde: oldpde is missing PG_PS and/or PG_V")); 2359 mpte = pmap_lookup_pt_page(pmap, va); 2360 if (mpte != NULL) 2361 pmap_remove_pt_page(pmap, mpte); 2362 else { 2363 KASSERT((oldpde & PG_W) == 0, 2364 ("pmap_demote_pde: page table page for a wired mapping" 2365 " is missing")); 2366 2367 /* 2368 * Invalidate the 2- or 4MB page mapping and return 2369 * "failure" if the mapping was never accessed or the 2370 * allocation of the new page table page fails. 2371 */ 2372 if ((oldpde & PG_A) == 0 || (mpte = vm_page_alloc(NULL, 2373 va >> PDRSHIFT, VM_ALLOC_NOOBJ | VM_ALLOC_NORMAL | 2374 VM_ALLOC_WIRED)) == NULL) { 2375 free = NULL; 2376 pmap_remove_pde(pmap, pde, trunc_4mpage(va), &free); 2377 pmap_invalidate_page(pmap, trunc_4mpage(va)); 2378 pmap_free_zero_pages(free); 2379 CTR2(KTR_PMAP, "pmap_demote_pde: failure for va %#x" 2380 " in pmap %p", va, pmap); 2381 return (FALSE); 2382 } 2383 if (va < VM_MAXUSER_ADDRESS) 2384 pmap->pm_stats.resident_count++; 2385 } 2386 mptepa = VM_PAGE_TO_PHYS(mpte); 2387 2388 /* 2389 * If the page mapping is in the kernel's address space, then the 2390 * KPTmap can provide access to the page table page. Otherwise, 2391 * temporarily map the page table page (mpte) into the kernel's 2392 * address space at either PADDR1 or PADDR2. 2393 */ 2394 if (va >= KERNBASE) 2395 firstpte = &KPTmap[i386_btop(trunc_4mpage(va))]; 2396 else if (curthread->td_pinned > 0 && mtx_owned(&vm_page_queue_mtx)) { 2397 if ((*PMAP1 & PG_FRAME) != mptepa) { 2398 *PMAP1 = mptepa | PG_RW | PG_V | PG_A | PG_M; 2399#ifdef SMP 2400 PMAP1cpu = PCPU_GET(cpuid); 2401#endif 2402 invlcaddr(PADDR1); 2403 PMAP1changed++; 2404 } else 2405#ifdef SMP 2406 if (PMAP1cpu != PCPU_GET(cpuid)) { 2407 PMAP1cpu = PCPU_GET(cpuid); 2408 invlcaddr(PADDR1); 2409 PMAP1changedcpu++; 2410 } else 2411#endif 2412 PMAP1unchanged++; 2413 firstpte = PADDR1; 2414 } else { 2415 mtx_lock(&PMAP2mutex); 2416 if ((*PMAP2 & PG_FRAME) != mptepa) { 2417 *PMAP2 = mptepa | PG_RW | PG_V | PG_A | PG_M; 2418 pmap_invalidate_page(kernel_pmap, (vm_offset_t)PADDR2); 2419 } 2420 firstpte = PADDR2; 2421 } 2422 newpde = mptepa | PG_M | PG_A | (oldpde & PG_U) | PG_RW | PG_V; 2423 KASSERT((oldpde & PG_A) != 0, 2424 ("pmap_demote_pde: oldpde is missing PG_A")); 2425 KASSERT((oldpde & (PG_M | PG_RW)) != PG_RW, 2426 ("pmap_demote_pde: oldpde is missing PG_M")); 2427 newpte = oldpde & ~PG_PS; 2428 if ((newpte & PG_PDE_PAT) != 0) 2429 newpte ^= PG_PDE_PAT | PG_PTE_PAT; 2430 2431 /* 2432 * If the page table page is new, initialize it. 2433 */ 2434 if (mpte->wire_count == 1) { 2435 mpte->wire_count = NPTEPG; 2436 pmap_fill_ptp(firstpte, newpte); 2437 } 2438 KASSERT((*firstpte & PG_FRAME) == (newpte & PG_FRAME), 2439 ("pmap_demote_pde: firstpte and newpte map different physical" 2440 " addresses")); 2441 2442 /* 2443 * If the mapping has changed attributes, update the page table 2444 * entries. 2445 */ 2446 if ((*firstpte & PG_PTE_PROMOTE) != (newpte & PG_PTE_PROMOTE)) 2447 pmap_fill_ptp(firstpte, newpte); 2448 2449 /* 2450 * Demote the mapping. This pmap is locked. The old PDE has 2451 * PG_A set. If the old PDE has PG_RW set, it also has PG_M 2452 * set. Thus, there is no danger of a race with another 2453 * processor changing the setting of PG_A and/or PG_M between 2454 * the read above and the store below. 2455 */ 2456 if (pmap == kernel_pmap) { 2457 /* 2458 * A harmless race exists between this loop and the bcopy() 2459 * in pmap_pinit() that initializes the kernel segment of 2460 * the new page table directory. Specifically, that bcopy() 2461 * may copy the new PDE from the PTD to the new page table 2462 * before this loop updates that new page table. 2463 */ 2464 mtx_lock_spin(&allpmaps_lock); 2465 LIST_FOREACH(allpmaps_entry, &allpmaps, pm_list) { 2466 pde = pmap_pde(allpmaps_entry, va); 2467 KASSERT(*pde == newpde || (*pde & PG_PTE_PROMOTE) == 2468 (oldpde & PG_PTE_PROMOTE), 2469 ("pmap_demote_pde: pde was %#jx, expected %#jx", 2470 (uintmax_t)*pde, (uintmax_t)oldpde)); 2471 pde_store(pde, newpde); 2472 } 2473 mtx_unlock_spin(&allpmaps_lock); 2474 } else 2475 pde_store(pde, newpde); 2476 if (firstpte == PADDR2) 2477 mtx_unlock(&PMAP2mutex); 2478 2479 /* 2480 * Invalidate the recursive mapping of the page table page. 2481 */ 2482 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va)); 2483 2484 /* 2485 * Demote the pv entry. This depends on the earlier demotion 2486 * of the mapping. Specifically, the (re)creation of a per- 2487 * page pv entry might trigger the execution of pmap_collect(), 2488 * which might reclaim a newly (re)created per-page pv entry 2489 * and destroy the associated mapping. In order to destroy 2490 * the mapping, the PDE must have already changed from mapping 2491 * the 2mpage to referencing the page table page. 2492 */ 2493 if ((oldpde & PG_MANAGED) != 0) 2494 pmap_pv_demote_pde(pmap, va, oldpde & PG_PS_FRAME); 2495 2496 pmap_pde_demotions++; 2497 CTR2(KTR_PMAP, "pmap_demote_pde: success for va %#x" 2498 " in pmap %p", va, pmap); 2499 return (TRUE); 2500} 2501 2502/* 2503 * pmap_remove_pde: do the things to unmap a superpage in a process 2504 */ 2505static void 2506pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva, 2507 vm_page_t *free) 2508{ 2509 struct md_page *pvh; 2510 pd_entry_t oldpde; 2511 vm_offset_t eva, va; 2512 vm_page_t m, mpte; 2513 2514 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2515 KASSERT((sva & PDRMASK) == 0, 2516 ("pmap_remove_pde: sva is not 4mpage aligned")); 2517 oldpde = pte_load_clear(pdq); 2518 if (oldpde & PG_W) 2519 pmap->pm_stats.wired_count -= NBPDR / PAGE_SIZE; 2520 2521 /* 2522 * Machines that don't support invlpg, also don't support 2523 * PG_G. 2524 */ 2525 if (oldpde & PG_G) 2526 pmap_invalidate_page(kernel_pmap, sva); 2527 pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE; 2528 if (oldpde & PG_MANAGED) { 2529 pvh = pa_to_pvh(oldpde & PG_PS_FRAME); 2530 pmap_pvh_free(pvh, pmap, sva); 2531 eva = sva + NBPDR; 2532 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME); 2533 va < eva; va += PAGE_SIZE, m++) { 2534 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW)) 2535 vm_page_dirty(m); 2536 if (oldpde & PG_A) 2537 vm_page_flag_set(m, PG_REFERENCED); 2538 if (TAILQ_EMPTY(&m->md.pv_list) && 2539 TAILQ_EMPTY(&pvh->pv_list)) 2540 vm_page_flag_clear(m, PG_WRITEABLE); 2541 } 2542 } 2543 if (pmap == kernel_pmap) { 2544 if (!pmap_demote_pde(pmap, pdq, sva)) 2545 panic("pmap_remove_pde: failed demotion"); 2546 } else { 2547 mpte = pmap_lookup_pt_page(pmap, sva); 2548 if (mpte != NULL) { 2549 pmap_remove_pt_page(pmap, mpte); 2550 pmap->pm_stats.resident_count--; 2551 KASSERT(mpte->wire_count == NPTEPG, 2552 ("pmap_remove_pde: pte page wire count error")); 2553 mpte->wire_count = 0; 2554 pmap_add_delayed_free_list(mpte, free, FALSE); 2555 atomic_subtract_int(&cnt.v_wire_count, 1); 2556 } 2557 } 2558} 2559 2560/* 2561 * pmap_remove_pte: do the things to unmap a page in a process 2562 */ 2563static int 2564pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t va, vm_page_t *free) 2565{ 2566 pt_entry_t oldpte; 2567 vm_page_t m; 2568 2569 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2570 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2571 oldpte = pte_load_clear(ptq); 2572 if (oldpte & PG_W) 2573 pmap->pm_stats.wired_count -= 1; 2574 /* 2575 * Machines that don't support invlpg, also don't support 2576 * PG_G. 2577 */ 2578 if (oldpte & PG_G) 2579 pmap_invalidate_page(kernel_pmap, va); 2580 pmap->pm_stats.resident_count -= 1; 2581 if (oldpte & PG_MANAGED) { 2582 m = PHYS_TO_VM_PAGE(oldpte & PG_FRAME); 2583 if ((oldpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) 2584 vm_page_dirty(m); 2585 if (oldpte & PG_A) 2586 vm_page_flag_set(m, PG_REFERENCED); 2587 pmap_remove_entry(pmap, m, va); 2588 } 2589 return (pmap_unuse_pt(pmap, va, free)); 2590} 2591 2592/* 2593 * Remove a single page from a process address space 2594 */ 2595static void 2596pmap_remove_page(pmap_t pmap, vm_offset_t va, vm_page_t *free) 2597{ 2598 pt_entry_t *pte; 2599 2600 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2601 KASSERT(curthread->td_pinned > 0, ("curthread not pinned")); 2602 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2603 if ((pte = pmap_pte_quick(pmap, va)) == NULL || *pte == 0) 2604 return; 2605 pmap_remove_pte(pmap, pte, va, free); 2606 pmap_invalidate_page(pmap, va); 2607} 2608 2609/* 2610 * Remove the given range of addresses from the specified map. 2611 * 2612 * It is assumed that the start and end are properly 2613 * rounded to the page size. 2614 */ 2615void 2616pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 2617{ 2618 vm_offset_t pdnxt; 2619 pd_entry_t ptpaddr; 2620 pt_entry_t *pte; 2621 vm_page_t free = NULL; 2622 int anyvalid; 2623 2624 /* 2625 * Perform an unsynchronized read. This is, however, safe. 2626 */ 2627 if (pmap->pm_stats.resident_count == 0) 2628 return; 2629 2630 anyvalid = 0; 2631 2632 vm_page_lock_queues(); 2633 sched_pin(); 2634 PMAP_LOCK(pmap); 2635 2636 /* 2637 * special handling of removing one page. a very 2638 * common operation and easy to short circuit some 2639 * code. 2640 */ 2641 if ((sva + PAGE_SIZE == eva) && 2642 ((pmap->pm_pdir[(sva >> PDRSHIFT)] & PG_PS) == 0)) { 2643 pmap_remove_page(pmap, sva, &free); 2644 goto out; 2645 } 2646 2647 for (; sva < eva; sva = pdnxt) { 2648 unsigned pdirindex; 2649 2650 /* 2651 * Calculate index for next page table. 2652 */ 2653 pdnxt = (sva + NBPDR) & ~PDRMASK; 2654 if (pdnxt < sva) 2655 pdnxt = eva; 2656 if (pmap->pm_stats.resident_count == 0) 2657 break; 2658 2659 pdirindex = sva >> PDRSHIFT; 2660 ptpaddr = pmap->pm_pdir[pdirindex]; 2661 2662 /* 2663 * Weed out invalid mappings. Note: we assume that the page 2664 * directory table is always allocated, and in kernel virtual. 2665 */ 2666 if (ptpaddr == 0) 2667 continue; 2668 2669 /* 2670 * Check for large page. 2671 */ 2672 if ((ptpaddr & PG_PS) != 0) { 2673 /* 2674 * Are we removing the entire large page? If not, 2675 * demote the mapping and fall through. 2676 */ 2677 if (sva + NBPDR == pdnxt && eva >= pdnxt) { 2678 /* 2679 * The TLB entry for a PG_G mapping is 2680 * invalidated by pmap_remove_pde(). 2681 */ 2682 if ((ptpaddr & PG_G) == 0) 2683 anyvalid = 1; 2684 pmap_remove_pde(pmap, 2685 &pmap->pm_pdir[pdirindex], sva, &free); 2686 continue; 2687 } else if (!pmap_demote_pde(pmap, 2688 &pmap->pm_pdir[pdirindex], sva)) { 2689 /* The large page mapping was destroyed. */ 2690 continue; 2691 } 2692 } 2693 2694 /* 2695 * Limit our scan to either the end of the va represented 2696 * by the current page table page, or to the end of the 2697 * range being removed. 2698 */ 2699 if (pdnxt > eva) 2700 pdnxt = eva; 2701 2702 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++, 2703 sva += PAGE_SIZE) { 2704 if (*pte == 0) 2705 continue; 2706 2707 /* 2708 * The TLB entry for a PG_G mapping is invalidated 2709 * by pmap_remove_pte(). 2710 */ 2711 if ((*pte & PG_G) == 0) 2712 anyvalid = 1; 2713 if (pmap_remove_pte(pmap, pte, sva, &free)) 2714 break; 2715 } 2716 } 2717out: 2718 sched_unpin(); 2719 if (anyvalid) 2720 pmap_invalidate_all(pmap); 2721 vm_page_unlock_queues(); 2722 PMAP_UNLOCK(pmap); 2723 pmap_free_zero_pages(free); 2724} 2725 2726/* 2727 * Routine: pmap_remove_all 2728 * Function: 2729 * Removes this physical page from 2730 * all physical maps in which it resides. 2731 * Reflects back modify bits to the pager. 2732 * 2733 * Notes: 2734 * Original versions of this routine were very 2735 * inefficient because they iteratively called 2736 * pmap_remove (slow...) 2737 */ 2738 2739void 2740pmap_remove_all(vm_page_t m) 2741{ 2742 struct md_page *pvh; 2743 pv_entry_t pv; 2744 pmap_t pmap; 2745 pt_entry_t *pte, tpte; 2746 pd_entry_t *pde; 2747 vm_offset_t va; 2748 vm_page_t free; 2749 2750 KASSERT((m->flags & PG_FICTITIOUS) == 0, 2751 ("pmap_remove_all: page %p is fictitious", m)); 2752 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2753 sched_pin(); 2754 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 2755 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) { 2756 va = pv->pv_va; 2757 pmap = PV_PMAP(pv); 2758 PMAP_LOCK(pmap); 2759 pde = pmap_pde(pmap, va); 2760 (void)pmap_demote_pde(pmap, pde, va); 2761 PMAP_UNLOCK(pmap); 2762 } 2763 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) { 2764 pmap = PV_PMAP(pv); 2765 PMAP_LOCK(pmap); 2766 pmap->pm_stats.resident_count--; 2767 pde = pmap_pde(pmap, pv->pv_va); 2768 KASSERT((*pde & PG_PS) == 0, ("pmap_remove_all: found" 2769 " a 4mpage in page %p's pv list", m)); 2770 pte = pmap_pte_quick(pmap, pv->pv_va); 2771 tpte = pte_load_clear(pte); 2772 if (tpte & PG_W) 2773 pmap->pm_stats.wired_count--; 2774 if (tpte & PG_A) 2775 vm_page_flag_set(m, PG_REFERENCED); 2776 2777 /* 2778 * Update the vm_page_t clean and reference bits. 2779 */ 2780 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) 2781 vm_page_dirty(m); 2782 free = NULL; 2783 pmap_unuse_pt(pmap, pv->pv_va, &free); 2784 pmap_invalidate_page(pmap, pv->pv_va); 2785 pmap_free_zero_pages(free); 2786 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list); 2787 free_pv_entry(pmap, pv); 2788 PMAP_UNLOCK(pmap); 2789 } 2790 vm_page_flag_clear(m, PG_WRITEABLE); 2791 sched_unpin(); 2792} 2793 2794/* 2795 * pmap_protect_pde: do the things to protect a 4mpage in a process 2796 */ 2797static boolean_t 2798pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva, vm_prot_t prot) 2799{ 2800 pd_entry_t newpde, oldpde; 2801 vm_offset_t eva, va; 2802 vm_page_t m; 2803 boolean_t anychanged; 2804 2805 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2806 KASSERT((sva & PDRMASK) == 0, 2807 ("pmap_protect_pde: sva is not 4mpage aligned")); 2808 anychanged = FALSE; 2809retry: 2810 oldpde = newpde = *pde; 2811 if (oldpde & PG_MANAGED) { 2812 eva = sva + NBPDR; 2813 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME); 2814 va < eva; va += PAGE_SIZE, m++) { 2815 /* 2816 * In contrast to the analogous operation on a 4KB page 2817 * mapping, the mapping's PG_A flag is not cleared and 2818 * the page's PG_REFERENCED flag is not set. The 2819 * reason is that pmap_demote_pde() expects that a 2/4MB 2820 * page mapping with a stored page table page has PG_A 2821 * set. 2822 */ 2823 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW)) 2824 vm_page_dirty(m); 2825 } 2826 } 2827 if ((prot & VM_PROT_WRITE) == 0) 2828 newpde &= ~(PG_RW | PG_M); 2829#ifdef PAE 2830 if ((prot & VM_PROT_EXECUTE) == 0) 2831 newpde |= pg_nx; 2832#endif 2833 if (newpde != oldpde) { 2834 if (!pde_cmpset(pde, oldpde, newpde)) 2835 goto retry; 2836 if (oldpde & PG_G) 2837 pmap_invalidate_page(pmap, sva); 2838 else 2839 anychanged = TRUE; 2840 } 2841 return (anychanged); 2842} 2843 2844/* 2845 * Set the physical protection on the 2846 * specified range of this map as requested. 2847 */ 2848void 2849pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot) 2850{ 2851 vm_offset_t pdnxt; 2852 pd_entry_t ptpaddr; 2853 pt_entry_t *pte; 2854 int anychanged; 2855 2856 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 2857 pmap_remove(pmap, sva, eva); 2858 return; 2859 } 2860 2861#ifdef PAE 2862 if ((prot & (VM_PROT_WRITE|VM_PROT_EXECUTE)) == 2863 (VM_PROT_WRITE|VM_PROT_EXECUTE)) 2864 return; 2865#else 2866 if (prot & VM_PROT_WRITE) 2867 return; 2868#endif 2869 2870 anychanged = 0; 2871 2872 vm_page_lock_queues(); 2873 sched_pin(); 2874 PMAP_LOCK(pmap); 2875 for (; sva < eva; sva = pdnxt) { 2876 pt_entry_t obits, pbits; 2877 unsigned pdirindex; 2878 2879 pdnxt = (sva + NBPDR) & ~PDRMASK; 2880 if (pdnxt < sva) 2881 pdnxt = eva; 2882 2883 pdirindex = sva >> PDRSHIFT; 2884 ptpaddr = pmap->pm_pdir[pdirindex]; 2885 2886 /* 2887 * Weed out invalid mappings. Note: we assume that the page 2888 * directory table is always allocated, and in kernel virtual. 2889 */ 2890 if (ptpaddr == 0) 2891 continue; 2892 2893 /* 2894 * Check for large page. 2895 */ 2896 if ((ptpaddr & PG_PS) != 0) { 2897 /* 2898 * Are we protecting the entire large page? If not, 2899 * demote the mapping and fall through. 2900 */ 2901 if (sva + NBPDR == pdnxt && eva >= pdnxt) { 2902 /* 2903 * The TLB entry for a PG_G mapping is 2904 * invalidated by pmap_protect_pde(). 2905 */ 2906 if (pmap_protect_pde(pmap, 2907 &pmap->pm_pdir[pdirindex], sva, prot)) 2908 anychanged = 1; 2909 continue; 2910 } else if (!pmap_demote_pde(pmap, 2911 &pmap->pm_pdir[pdirindex], sva)) { 2912 /* The large page mapping was destroyed. */ 2913 continue; 2914 } 2915 } 2916 2917 if (pdnxt > eva) 2918 pdnxt = eva; 2919 2920 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++, 2921 sva += PAGE_SIZE) { 2922 vm_page_t m; 2923 2924retry: 2925 /* 2926 * Regardless of whether a pte is 32 or 64 bits in 2927 * size, PG_RW, PG_A, and PG_M are among the least 2928 * significant 32 bits. 2929 */ 2930 obits = pbits = *pte; 2931 if ((pbits & PG_V) == 0) 2932 continue; 2933 if (pbits & PG_MANAGED) { 2934 m = NULL; 2935 if (pbits & PG_A) { 2936 m = PHYS_TO_VM_PAGE(pbits & PG_FRAME); 2937 vm_page_flag_set(m, PG_REFERENCED); 2938 pbits &= ~PG_A; 2939 } 2940 if ((pbits & (PG_M | PG_RW)) == (PG_M | PG_RW)) { 2941 if (m == NULL) 2942 m = PHYS_TO_VM_PAGE(pbits & PG_FRAME); 2943 vm_page_dirty(m); 2944 } 2945 } 2946 2947 if ((prot & VM_PROT_WRITE) == 0) 2948 pbits &= ~(PG_RW | PG_M); 2949#ifdef PAE 2950 if ((prot & VM_PROT_EXECUTE) == 0) 2951 pbits |= pg_nx; 2952#endif 2953 2954 if (pbits != obits) { 2955#ifdef PAE 2956 if (!atomic_cmpset_64(pte, obits, pbits)) 2957 goto retry; 2958#else 2959 if (!atomic_cmpset_int((u_int *)pte, obits, 2960 pbits)) 2961 goto retry; 2962#endif 2963 if (obits & PG_G) 2964 pmap_invalidate_page(pmap, sva); 2965 else 2966 anychanged = 1; 2967 } 2968 } 2969 } 2970 sched_unpin(); 2971 if (anychanged) 2972 pmap_invalidate_all(pmap); 2973 vm_page_unlock_queues(); 2974 PMAP_UNLOCK(pmap); 2975} 2976 2977/* 2978 * Tries to promote the 512 or 1024, contiguous 4KB page mappings that are 2979 * within a single page table page (PTP) to a single 2- or 4MB page mapping. 2980 * For promotion to occur, two conditions must be met: (1) the 4KB page 2981 * mappings must map aligned, contiguous physical memory and (2) the 4KB page 2982 * mappings must have identical characteristics. 2983 * 2984 * Managed (PG_MANAGED) mappings within the kernel address space are not 2985 * promoted. The reason is that kernel PDEs are replicated in each pmap but 2986 * pmap_clear_ptes() and pmap_ts_referenced() only read the PDE from the kernel 2987 * pmap. 2988 */ 2989static void 2990pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va) 2991{ 2992 pd_entry_t newpde; 2993 pmap_t allpmaps_entry; 2994 pt_entry_t *firstpte, oldpte, pa, *pte; 2995 vm_offset_t oldpteva; 2996 vm_page_t mpte; 2997 2998 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2999 3000 /* 3001 * Examine the first PTE in the specified PTP. Abort if this PTE is 3002 * either invalid, unused, or does not map the first 4KB physical page 3003 * within a 2- or 4MB page. 3004 */ 3005 firstpte = vtopte(trunc_4mpage(va)); 3006setpde: 3007 newpde = *firstpte; 3008 if ((newpde & ((PG_FRAME & PDRMASK) | PG_A | PG_V)) != (PG_A | PG_V)) { 3009 pmap_pde_p_failures++; 3010 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x" 3011 " in pmap %p", va, pmap); 3012 return; 3013 } 3014 if ((*firstpte & PG_MANAGED) != 0 && pmap == kernel_pmap) { 3015 pmap_pde_p_failures++; 3016 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x" 3017 " in pmap %p", va, pmap); 3018 return; 3019 } 3020 if ((newpde & (PG_M | PG_RW)) == PG_RW) { 3021 /* 3022 * When PG_M is already clear, PG_RW can be cleared without 3023 * a TLB invalidation. 3024 */ 3025 if (!atomic_cmpset_int((u_int *)firstpte, newpde, newpde & 3026 ~PG_RW)) 3027 goto setpde; 3028 newpde &= ~PG_RW; 3029 } 3030 3031 /* 3032 * Examine each of the other PTEs in the specified PTP. Abort if this 3033 * PTE maps an unexpected 4KB physical page or does not have identical 3034 * characteristics to the first PTE. 3035 */ 3036 pa = (newpde & (PG_PS_FRAME | PG_A | PG_V)) + NBPDR - PAGE_SIZE; 3037 for (pte = firstpte + NPTEPG - 1; pte > firstpte; pte--) { 3038setpte: 3039 oldpte = *pte; 3040 if ((oldpte & (PG_FRAME | PG_A | PG_V)) != pa) { 3041 pmap_pde_p_failures++; 3042 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x" 3043 " in pmap %p", va, pmap); 3044 return; 3045 } 3046 if ((oldpte & (PG_M | PG_RW)) == PG_RW) { 3047 /* 3048 * When PG_M is already clear, PG_RW can be cleared 3049 * without a TLB invalidation. 3050 */ 3051 if (!atomic_cmpset_int((u_int *)pte, oldpte, 3052 oldpte & ~PG_RW)) 3053 goto setpte; 3054 oldpte &= ~PG_RW; 3055 oldpteva = (oldpte & PG_FRAME & PDRMASK) | 3056 (va & ~PDRMASK); 3057 CTR2(KTR_PMAP, "pmap_promote_pde: protect for va %#x" 3058 " in pmap %p", oldpteva, pmap); 3059 } 3060 if ((oldpte & PG_PTE_PROMOTE) != (newpde & PG_PTE_PROMOTE)) { 3061 pmap_pde_p_failures++; 3062 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x" 3063 " in pmap %p", va, pmap); 3064 return; 3065 } 3066 pa -= PAGE_SIZE; 3067 } 3068 3069 /* 3070 * Save the page table page in its current state until the PDE 3071 * mapping the superpage is demoted by pmap_demote_pde() or 3072 * destroyed by pmap_remove_pde(). 3073 */ 3074 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME); 3075 KASSERT(mpte >= vm_page_array && 3076 mpte < &vm_page_array[vm_page_array_size], 3077 ("pmap_promote_pde: page table page is out of range")); 3078 KASSERT(mpte->pindex == va >> PDRSHIFT, 3079 ("pmap_promote_pde: page table page's pindex is wrong")); 3080 pmap_insert_pt_page(pmap, mpte); 3081 3082 /* 3083 * Promote the pv entries. 3084 */ 3085 if ((newpde & PG_MANAGED) != 0) 3086 pmap_pv_promote_pde(pmap, va, newpde & PG_PS_FRAME); 3087 3088 /* 3089 * Propagate the PAT index to its proper position. 3090 */ 3091 if ((newpde & PG_PTE_PAT) != 0) 3092 newpde ^= PG_PDE_PAT | PG_PTE_PAT; 3093 3094 /* 3095 * Map the superpage. 3096 */ 3097 if (pmap == kernel_pmap) { 3098 mtx_lock_spin(&allpmaps_lock); 3099 LIST_FOREACH(allpmaps_entry, &allpmaps, pm_list) { 3100 pde = pmap_pde(allpmaps_entry, va); 3101 pde_store(pde, PG_PS | newpde); 3102 } 3103 mtx_unlock_spin(&allpmaps_lock); 3104 } else 3105 pde_store(pde, PG_PS | newpde); 3106 3107 pmap_pde_promotions++; 3108 CTR2(KTR_PMAP, "pmap_promote_pde: success for va %#x" 3109 " in pmap %p", va, pmap); 3110} 3111 3112/* 3113 * Insert the given physical page (p) at 3114 * the specified virtual address (v) in the 3115 * target physical map with the protection requested. 3116 * 3117 * If specified, the page will be wired down, meaning 3118 * that the related pte can not be reclaimed. 3119 * 3120 * NB: This is the only routine which MAY NOT lazy-evaluate 3121 * or lose information. That is, this routine must actually 3122 * insert this page into the given map NOW. 3123 */ 3124void 3125pmap_enter(pmap_t pmap, vm_offset_t va, vm_prot_t access, vm_page_t m, 3126 vm_prot_t prot, boolean_t wired) 3127{ 3128 vm_paddr_t pa; 3129 pd_entry_t *pde; 3130 pt_entry_t *pte; 3131 vm_paddr_t opa; 3132 pt_entry_t origpte, newpte; 3133 vm_page_t mpte, om; 3134 boolean_t invlva; 3135 3136 va = trunc_page(va); 3137 KASSERT(va <= VM_MAX_KERNEL_ADDRESS, ("pmap_enter: toobig")); 3138 KASSERT(va < UPT_MIN_ADDRESS || va >= UPT_MAX_ADDRESS, 3139 ("pmap_enter: invalid to pmap_enter page table pages (va: 0x%x)", va)); 3140 3141 mpte = NULL; 3142 3143 vm_page_lock_queues(); 3144 PMAP_LOCK(pmap); 3145 sched_pin(); 3146 3147 /* 3148 * In the case that a page table page is not 3149 * resident, we are creating it here. 3150 */ 3151 if (va < VM_MAXUSER_ADDRESS) { 3152 mpte = pmap_allocpte(pmap, va, M_WAITOK); 3153 } 3154 3155 pde = pmap_pde(pmap, va); 3156 if ((*pde & PG_PS) != 0) 3157 panic("pmap_enter: attempted pmap_enter on 4MB page"); 3158 pte = pmap_pte_quick(pmap, va); 3159 3160 /* 3161 * Page Directory table entry not valid, we need a new PT page 3162 */ 3163 if (pte == NULL) { 3164 panic("pmap_enter: invalid page directory pdir=%#jx, va=%#x", 3165 (uintmax_t)pmap->pm_pdir[PTDPTDI], va); 3166 } 3167 3168 pa = VM_PAGE_TO_PHYS(m); 3169 om = NULL; 3170 origpte = *pte; 3171 opa = origpte & PG_FRAME; 3172 3173 /* 3174 * Mapping has not changed, must be protection or wiring change. 3175 */ 3176 if (origpte && (opa == pa)) { 3177 /* 3178 * Wiring change, just update stats. We don't worry about 3179 * wiring PT pages as they remain resident as long as there 3180 * are valid mappings in them. Hence, if a user page is wired, 3181 * the PT page will be also. 3182 */ 3183 if (wired && ((origpte & PG_W) == 0)) 3184 pmap->pm_stats.wired_count++; 3185 else if (!wired && (origpte & PG_W)) 3186 pmap->pm_stats.wired_count--; 3187 3188 /* 3189 * Remove extra pte reference 3190 */ 3191 if (mpte) 3192 mpte->wire_count--; 3193 3194 /* 3195 * We might be turning off write access to the page, 3196 * so we go ahead and sense modify status. 3197 */ 3198 if (origpte & PG_MANAGED) { 3199 om = m; 3200 pa |= PG_MANAGED; 3201 } 3202 goto validate; 3203 } 3204 /* 3205 * Mapping has changed, invalidate old range and fall through to 3206 * handle validating new mapping. 3207 */ 3208 if (opa) { 3209 if (origpte & PG_W) 3210 pmap->pm_stats.wired_count--; 3211 if (origpte & PG_MANAGED) { 3212 om = PHYS_TO_VM_PAGE(opa); 3213 pmap_remove_entry(pmap, om, va); 3214 } 3215 if (mpte != NULL) { 3216 mpte->wire_count--; 3217 KASSERT(mpte->wire_count > 0, 3218 ("pmap_enter: missing reference to page table page," 3219 " va: 0x%x", va)); 3220 } 3221 } else 3222 pmap->pm_stats.resident_count++; 3223 3224 /* 3225 * Enter on the PV list if part of our managed memory. 3226 */ 3227 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0) { 3228 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva, 3229 ("pmap_enter: managed mapping within the clean submap")); 3230 pmap_insert_entry(pmap, va, m); 3231 pa |= PG_MANAGED; 3232 } 3233 3234 /* 3235 * Increment counters 3236 */ 3237 if (wired) 3238 pmap->pm_stats.wired_count++; 3239 3240validate: 3241 /* 3242 * Now validate mapping with desired protection/wiring. 3243 */ 3244 newpte = (pt_entry_t)(pa | pmap_cache_bits(m->md.pat_mode, 0) | PG_V); 3245 if ((prot & VM_PROT_WRITE) != 0) { 3246 newpte |= PG_RW; 3247 vm_page_flag_set(m, PG_WRITEABLE); 3248 } 3249#ifdef PAE 3250 if ((prot & VM_PROT_EXECUTE) == 0) 3251 newpte |= pg_nx; 3252#endif 3253 if (wired) 3254 newpte |= PG_W; 3255 if (va < VM_MAXUSER_ADDRESS) 3256 newpte |= PG_U; 3257 if (pmap == kernel_pmap) 3258 newpte |= pgeflag; 3259 3260 /* 3261 * if the mapping or permission bits are different, we need 3262 * to update the pte. 3263 */ 3264 if ((origpte & ~(PG_M|PG_A)) != newpte) { 3265 newpte |= PG_A; 3266 if ((access & VM_PROT_WRITE) != 0) 3267 newpte |= PG_M; 3268 if (origpte & PG_V) { 3269 invlva = FALSE; 3270 origpte = pte_load_store(pte, newpte); 3271 if (origpte & PG_A) { 3272 if (origpte & PG_MANAGED) 3273 vm_page_flag_set(om, PG_REFERENCED); 3274 if (opa != VM_PAGE_TO_PHYS(m)) 3275 invlva = TRUE; 3276#ifdef PAE 3277 if ((origpte & PG_NX) == 0 && 3278 (newpte & PG_NX) != 0) 3279 invlva = TRUE; 3280#endif 3281 } 3282 if ((origpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) { 3283 if ((origpte & PG_MANAGED) != 0) 3284 vm_page_dirty(om); 3285 if ((prot & VM_PROT_WRITE) == 0) 3286 invlva = TRUE; 3287 } 3288 if (invlva) 3289 pmap_invalidate_page(pmap, va); 3290 } else 3291 pte_store(pte, newpte); 3292 } 3293 3294 /* 3295 * If both the page table page and the reservation are fully 3296 * populated, then attempt promotion. 3297 */ 3298 if ((mpte == NULL || mpte->wire_count == NPTEPG) && 3299 pg_ps_enabled && vm_reserv_level_iffullpop(m) == 0) 3300 pmap_promote_pde(pmap, pde, va); 3301 3302 sched_unpin(); 3303 vm_page_unlock_queues(); 3304 PMAP_UNLOCK(pmap); 3305} 3306 3307/* 3308 * Tries to create a 2- or 4MB page mapping. Returns TRUE if successful and 3309 * FALSE otherwise. Fails if (1) a page table page cannot be allocated without 3310 * blocking, (2) a mapping already exists at the specified virtual address, or 3311 * (3) a pv entry cannot be allocated without reclaiming another pv entry. 3312 */ 3313static boolean_t 3314pmap_enter_pde(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot) 3315{ 3316 pd_entry_t *pde, newpde; 3317 3318 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 3319 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 3320 pde = pmap_pde(pmap, va); 3321 if (*pde != 0) { 3322 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx" 3323 " in pmap %p", va, pmap); 3324 return (FALSE); 3325 } 3326 newpde = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(m->md.pat_mode, 1) | 3327 PG_PS | PG_V; 3328 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0) { 3329 newpde |= PG_MANAGED; 3330 3331 /* 3332 * Abort this mapping if its PV entry could not be created. 3333 */ 3334 if (!pmap_pv_insert_pde(pmap, va, VM_PAGE_TO_PHYS(m))) { 3335 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx" 3336 " in pmap %p", va, pmap); 3337 return (FALSE); 3338 } 3339 } 3340#ifdef PAE 3341 if ((prot & VM_PROT_EXECUTE) == 0) 3342 newpde |= pg_nx; 3343#endif 3344 if (va < VM_MAXUSER_ADDRESS) 3345 newpde |= PG_U; 3346 3347 /* 3348 * Increment counters. 3349 */ 3350 pmap->pm_stats.resident_count += NBPDR / PAGE_SIZE; 3351 3352 /* 3353 * Map the superpage. 3354 */ 3355 pde_store(pde, newpde); 3356 3357 pmap_pde_mappings++; 3358 CTR2(KTR_PMAP, "pmap_enter_pde: success for va %#lx" 3359 " in pmap %p", va, pmap); 3360 return (TRUE); 3361} 3362 3363/* 3364 * Maps a sequence of resident pages belonging to the same object. 3365 * The sequence begins with the given page m_start. This page is 3366 * mapped at the given virtual address start. Each subsequent page is 3367 * mapped at a virtual address that is offset from start by the same 3368 * amount as the page is offset from m_start within the object. The 3369 * last page in the sequence is the page with the largest offset from 3370 * m_start that can be mapped at a virtual address less than the given 3371 * virtual address end. Not every virtual page between start and end 3372 * is mapped; only those for which a resident page exists with the 3373 * corresponding offset from m_start are mapped. 3374 */ 3375void 3376pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end, 3377 vm_page_t m_start, vm_prot_t prot) 3378{ 3379 vm_offset_t va; 3380 vm_page_t m, mpte; 3381 vm_pindex_t diff, psize; 3382 3383 VM_OBJECT_LOCK_ASSERT(m_start->object, MA_OWNED); 3384 psize = atop(end - start); 3385 mpte = NULL; 3386 m = m_start; 3387 PMAP_LOCK(pmap); 3388 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 3389 va = start + ptoa(diff); 3390 if ((va & PDRMASK) == 0 && va + NBPDR <= end && 3391 (VM_PAGE_TO_PHYS(m) & PDRMASK) == 0 && 3392 pg_ps_enabled && vm_reserv_level_iffullpop(m) == 0 && 3393 pmap_enter_pde(pmap, va, m, prot)) 3394 m = &m[NBPDR / PAGE_SIZE - 1]; 3395 else 3396 mpte = pmap_enter_quick_locked(pmap, va, m, prot, 3397 mpte); 3398 m = TAILQ_NEXT(m, listq); 3399 } 3400 PMAP_UNLOCK(pmap); 3401} 3402 3403/* 3404 * this code makes some *MAJOR* assumptions: 3405 * 1. Current pmap & pmap exists. 3406 * 2. Not wired. 3407 * 3. Read access. 3408 * 4. No page table pages. 3409 * but is *MUCH* faster than pmap_enter... 3410 */ 3411 3412void 3413pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot) 3414{ 3415 3416 PMAP_LOCK(pmap); 3417 (void) pmap_enter_quick_locked(pmap, va, m, prot, NULL); 3418 PMAP_UNLOCK(pmap); 3419} 3420 3421static vm_page_t 3422pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m, 3423 vm_prot_t prot, vm_page_t mpte) 3424{ 3425 pt_entry_t *pte; 3426 vm_paddr_t pa; 3427 vm_page_t free; 3428 3429 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva || 3430 (m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0, 3431 ("pmap_enter_quick_locked: managed mapping within the clean submap")); 3432 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 3433 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 3434 3435 /* 3436 * In the case that a page table page is not 3437 * resident, we are creating it here. 3438 */ 3439 if (va < VM_MAXUSER_ADDRESS) { 3440 unsigned ptepindex; 3441 pd_entry_t ptepa; 3442 3443 /* 3444 * Calculate pagetable page index 3445 */ 3446 ptepindex = va >> PDRSHIFT; 3447 if (mpte && (mpte->pindex == ptepindex)) { 3448 mpte->wire_count++; 3449 } else { 3450 /* 3451 * Get the page directory entry 3452 */ 3453 ptepa = pmap->pm_pdir[ptepindex]; 3454 3455 /* 3456 * If the page table page is mapped, we just increment 3457 * the hold count, and activate it. 3458 */ 3459 if (ptepa) { 3460 if (ptepa & PG_PS) 3461 return (NULL); 3462 mpte = PHYS_TO_VM_PAGE(ptepa & PG_FRAME); 3463 mpte->wire_count++; 3464 } else { 3465 mpte = _pmap_allocpte(pmap, ptepindex, 3466 M_NOWAIT); 3467 if (mpte == NULL) 3468 return (mpte); 3469 } 3470 } 3471 } else { 3472 mpte = NULL; 3473 } 3474 3475 /* 3476 * This call to vtopte makes the assumption that we are 3477 * entering the page into the current pmap. In order to support 3478 * quick entry into any pmap, one would likely use pmap_pte_quick. 3479 * But that isn't as quick as vtopte. 3480 */ 3481 pte = vtopte(va); 3482 if (*pte) { 3483 if (mpte != NULL) { 3484 mpte->wire_count--; 3485 mpte = NULL; 3486 } 3487 return (mpte); 3488 } 3489 3490 /* 3491 * Enter on the PV list if part of our managed memory. 3492 */ 3493 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0 && 3494 !pmap_try_insert_pv_entry(pmap, va, m)) { 3495 if (mpte != NULL) { 3496 free = NULL; 3497 if (pmap_unwire_pte_hold(pmap, mpte, &free)) { 3498 pmap_invalidate_page(pmap, va); 3499 pmap_free_zero_pages(free); 3500 } 3501 3502 mpte = NULL; 3503 } 3504 return (mpte); 3505 } 3506 3507 /* 3508 * Increment counters 3509 */ 3510 pmap->pm_stats.resident_count++; 3511 3512 pa = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(m->md.pat_mode, 0); 3513#ifdef PAE 3514 if ((prot & VM_PROT_EXECUTE) == 0) 3515 pa |= pg_nx; 3516#endif 3517 3518 /* 3519 * Now validate mapping with RO protection 3520 */ 3521 if (m->flags & (PG_FICTITIOUS|PG_UNMANAGED)) 3522 pte_store(pte, pa | PG_V | PG_U); 3523 else 3524 pte_store(pte, pa | PG_V | PG_U | PG_MANAGED); 3525 return mpte; 3526} 3527 3528/* 3529 * Make a temporary mapping for a physical address. This is only intended 3530 * to be used for panic dumps. 3531 */ 3532void * 3533pmap_kenter_temporary(vm_paddr_t pa, int i) 3534{ 3535 vm_offset_t va; 3536 3537 va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE); 3538 pmap_kenter(va, pa); 3539 invlpg(va); 3540 return ((void *)crashdumpmap); 3541} 3542 3543/* 3544 * This code maps large physical mmap regions into the 3545 * processor address space. Note that some shortcuts 3546 * are taken, but the code works. 3547 */ 3548void 3549pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object, 3550 vm_pindex_t pindex, vm_size_t size) 3551{ 3552 pd_entry_t *pde; 3553 vm_paddr_t pa, ptepa; 3554 vm_page_t p; 3555 int pat_mode; 3556 3557 VM_OBJECT_LOCK_ASSERT(object, MA_OWNED); 3558 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG, 3559 ("pmap_object_init_pt: non-device object")); 3560 if (pseflag && 3561 (addr & (NBPDR - 1)) == 0 && (size & (NBPDR - 1)) == 0) { 3562 if (!vm_object_populate(object, pindex, pindex + atop(size))) 3563 return; 3564 p = vm_page_lookup(object, pindex); 3565 KASSERT(p->valid == VM_PAGE_BITS_ALL, 3566 ("pmap_object_init_pt: invalid page %p", p)); 3567 pat_mode = p->md.pat_mode; 3568 3569 /* 3570 * Abort the mapping if the first page is not physically 3571 * aligned to a 2/4MB page boundary. 3572 */ 3573 ptepa = VM_PAGE_TO_PHYS(p); 3574 if (ptepa & (NBPDR - 1)) 3575 return; 3576 3577 /* 3578 * Skip the first page. Abort the mapping if the rest of 3579 * the pages are not physically contiguous or have differing 3580 * memory attributes. 3581 */ 3582 p = TAILQ_NEXT(p, listq); 3583 for (pa = ptepa + PAGE_SIZE; pa < ptepa + size; 3584 pa += PAGE_SIZE) { 3585 KASSERT(p->valid == VM_PAGE_BITS_ALL, 3586 ("pmap_object_init_pt: invalid page %p", p)); 3587 if (pa != VM_PAGE_TO_PHYS(p) || 3588 pat_mode != p->md.pat_mode) 3589 return; 3590 p = TAILQ_NEXT(p, listq); 3591 } 3592 3593 /* 3594 * Map using 2/4MB pages. Since "ptepa" is 2/4M aligned and 3595 * "size" is a multiple of 2/4M, adding the PAT setting to 3596 * "pa" will not affect the termination of this loop. 3597 */ 3598 PMAP_LOCK(pmap); 3599 for (pa = ptepa | pmap_cache_bits(pat_mode, 1); pa < ptepa + 3600 size; pa += NBPDR) { 3601 pde = pmap_pde(pmap, addr); 3602 if (*pde == 0) { 3603 pde_store(pde, pa | PG_PS | PG_M | PG_A | 3604 PG_U | PG_RW | PG_V); 3605 pmap->pm_stats.resident_count += NBPDR / 3606 PAGE_SIZE; 3607 pmap_pde_mappings++; 3608 } 3609 /* Else continue on if the PDE is already valid. */ 3610 addr += NBPDR; 3611 } 3612 PMAP_UNLOCK(pmap); 3613 } 3614} 3615 3616/* 3617 * Routine: pmap_change_wiring 3618 * Function: Change the wiring attribute for a map/virtual-address 3619 * pair. 3620 * In/out conditions: 3621 * The mapping must already exist in the pmap. 3622 */ 3623void 3624pmap_change_wiring(pmap_t pmap, vm_offset_t va, boolean_t wired) 3625{ 3626 pd_entry_t *pde; 3627 pt_entry_t *pte; 3628 boolean_t are_queues_locked; 3629 3630 are_queues_locked = FALSE; 3631retry: 3632 PMAP_LOCK(pmap); 3633 pde = pmap_pde(pmap, va); 3634 if ((*pde & PG_PS) != 0) { 3635 if (!wired != ((*pde & PG_W) == 0)) { 3636 if (!are_queues_locked) { 3637 are_queues_locked = TRUE; 3638 if (!mtx_trylock(&vm_page_queue_mtx)) { 3639 PMAP_UNLOCK(pmap); 3640 vm_page_lock_queues(); 3641 goto retry; 3642 } 3643 } 3644 if (!pmap_demote_pde(pmap, pde, va)) 3645 panic("pmap_change_wiring: demotion failed"); 3646 } else 3647 goto out; 3648 } 3649 pte = pmap_pte(pmap, va); 3650 3651 if (wired && !pmap_pte_w(pte)) 3652 pmap->pm_stats.wired_count++; 3653 else if (!wired && pmap_pte_w(pte)) 3654 pmap->pm_stats.wired_count--; 3655 3656 /* 3657 * Wiring is not a hardware characteristic so there is no need to 3658 * invalidate TLB. 3659 */ 3660 pmap_pte_set_w(pte, wired); 3661 pmap_pte_release(pte); 3662out: 3663 if (are_queues_locked) 3664 vm_page_unlock_queues(); 3665 PMAP_UNLOCK(pmap); 3666} 3667 3668 3669 3670/* 3671 * Copy the range specified by src_addr/len 3672 * from the source map to the range dst_addr/len 3673 * in the destination map. 3674 * 3675 * This routine is only advisory and need not do anything. 3676 */ 3677 3678void 3679pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len, 3680 vm_offset_t src_addr) 3681{ 3682 vm_page_t free; 3683 vm_offset_t addr; 3684 vm_offset_t end_addr = src_addr + len; 3685 vm_offset_t pdnxt; 3686 3687 if (dst_addr != src_addr) 3688 return; 3689 3690 if (!pmap_is_current(src_pmap)) 3691 return; 3692 3693 vm_page_lock_queues(); 3694 if (dst_pmap < src_pmap) { 3695 PMAP_LOCK(dst_pmap); 3696 PMAP_LOCK(src_pmap); 3697 } else { 3698 PMAP_LOCK(src_pmap); 3699 PMAP_LOCK(dst_pmap); 3700 } 3701 sched_pin(); 3702 for (addr = src_addr; addr < end_addr; addr = pdnxt) { 3703 pt_entry_t *src_pte, *dst_pte; 3704 vm_page_t dstmpte, srcmpte; 3705 pd_entry_t srcptepaddr; 3706 unsigned ptepindex; 3707 3708 KASSERT(addr < UPT_MIN_ADDRESS, 3709 ("pmap_copy: invalid to pmap_copy page tables")); 3710 3711 pdnxt = (addr + NBPDR) & ~PDRMASK; 3712 if (pdnxt < addr) 3713 pdnxt = end_addr; 3714 ptepindex = addr >> PDRSHIFT; 3715 3716 srcptepaddr = src_pmap->pm_pdir[ptepindex]; 3717 if (srcptepaddr == 0) 3718 continue; 3719 3720 if (srcptepaddr & PG_PS) { 3721 if (dst_pmap->pm_pdir[ptepindex] == 0 && 3722 ((srcptepaddr & PG_MANAGED) == 0 || 3723 pmap_pv_insert_pde(dst_pmap, addr, srcptepaddr & 3724 PG_PS_FRAME))) { 3725 dst_pmap->pm_pdir[ptepindex] = srcptepaddr & 3726 ~PG_W; 3727 dst_pmap->pm_stats.resident_count += 3728 NBPDR / PAGE_SIZE; 3729 } 3730 continue; 3731 } 3732 3733 srcmpte = PHYS_TO_VM_PAGE(srcptepaddr & PG_FRAME); 3734 KASSERT(srcmpte->wire_count > 0, 3735 ("pmap_copy: source page table page is unused")); 3736 3737 if (pdnxt > end_addr) 3738 pdnxt = end_addr; 3739 3740 src_pte = vtopte(addr); 3741 while (addr < pdnxt) { 3742 pt_entry_t ptetemp; 3743 ptetemp = *src_pte; 3744 /* 3745 * we only virtual copy managed pages 3746 */ 3747 if ((ptetemp & PG_MANAGED) != 0) { 3748 dstmpte = pmap_allocpte(dst_pmap, addr, 3749 M_NOWAIT); 3750 if (dstmpte == NULL) 3751 goto out; 3752 dst_pte = pmap_pte_quick(dst_pmap, addr); 3753 if (*dst_pte == 0 && 3754 pmap_try_insert_pv_entry(dst_pmap, addr, 3755 PHYS_TO_VM_PAGE(ptetemp & PG_FRAME))) { 3756 /* 3757 * Clear the wired, modified, and 3758 * accessed (referenced) bits 3759 * during the copy. 3760 */ 3761 *dst_pte = ptetemp & ~(PG_W | PG_M | 3762 PG_A); 3763 dst_pmap->pm_stats.resident_count++; 3764 } else { 3765 free = NULL; 3766 if (pmap_unwire_pte_hold(dst_pmap, 3767 dstmpte, &free)) { 3768 pmap_invalidate_page(dst_pmap, 3769 addr); 3770 pmap_free_zero_pages(free); 3771 } 3772 goto out; 3773 } 3774 if (dstmpte->wire_count >= srcmpte->wire_count) 3775 break; 3776 } 3777 addr += PAGE_SIZE; 3778 src_pte++; 3779 } 3780 } 3781out: 3782 sched_unpin(); 3783 vm_page_unlock_queues(); 3784 PMAP_UNLOCK(src_pmap); 3785 PMAP_UNLOCK(dst_pmap); 3786} 3787 3788static __inline void 3789pagezero(void *page) 3790{ 3791#if defined(I686_CPU) 3792 if (cpu_class == CPUCLASS_686) { 3793#if defined(CPU_ENABLE_SSE) 3794 if (cpu_feature & CPUID_SSE2) 3795 sse2_pagezero(page); 3796 else 3797#endif 3798 i686_pagezero(page); 3799 } else 3800#endif 3801 bzero(page, PAGE_SIZE); 3802} 3803 3804/* 3805 * pmap_zero_page zeros the specified hardware page by mapping 3806 * the page into KVM and using bzero to clear its contents. 3807 */ 3808void 3809pmap_zero_page(vm_page_t m) 3810{ 3811 struct sysmaps *sysmaps; 3812 3813 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)]; 3814 mtx_lock(&sysmaps->lock); 3815 if (*sysmaps->CMAP2) 3816 panic("pmap_zero_page: CMAP2 busy"); 3817 sched_pin(); 3818 *sysmaps->CMAP2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M | 3819 pmap_cache_bits(m->md.pat_mode, 0); 3820 invlcaddr(sysmaps->CADDR2); 3821 pagezero(sysmaps->CADDR2); 3822 *sysmaps->CMAP2 = 0; 3823 sched_unpin(); 3824 mtx_unlock(&sysmaps->lock); 3825} 3826 3827/* 3828 * pmap_zero_page_area zeros the specified hardware page by mapping 3829 * the page into KVM and using bzero to clear its contents. 3830 * 3831 * off and size may not cover an area beyond a single hardware page. 3832 */ 3833void 3834pmap_zero_page_area(vm_page_t m, int off, int size) 3835{ 3836 struct sysmaps *sysmaps; 3837 3838 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)]; 3839 mtx_lock(&sysmaps->lock); 3840 if (*sysmaps->CMAP2) 3841 panic("pmap_zero_page_area: CMAP2 busy"); 3842 sched_pin(); 3843 *sysmaps->CMAP2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M | 3844 pmap_cache_bits(m->md.pat_mode, 0); 3845 invlcaddr(sysmaps->CADDR2); 3846 if (off == 0 && size == PAGE_SIZE) 3847 pagezero(sysmaps->CADDR2); 3848 else 3849 bzero((char *)sysmaps->CADDR2 + off, size); 3850 *sysmaps->CMAP2 = 0; 3851 sched_unpin(); 3852 mtx_unlock(&sysmaps->lock); 3853} 3854 3855/* 3856 * pmap_zero_page_idle zeros the specified hardware page by mapping 3857 * the page into KVM and using bzero to clear its contents. This 3858 * is intended to be called from the vm_pagezero process only and 3859 * outside of Giant. 3860 */ 3861void 3862pmap_zero_page_idle(vm_page_t m) 3863{ 3864 3865 if (*CMAP3) 3866 panic("pmap_zero_page_idle: CMAP3 busy"); 3867 sched_pin(); 3868 *CMAP3 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M | 3869 pmap_cache_bits(m->md.pat_mode, 0); 3870 invlcaddr(CADDR3); 3871 pagezero(CADDR3); 3872 *CMAP3 = 0; 3873 sched_unpin(); 3874} 3875 3876/* 3877 * pmap_copy_page copies the specified (machine independent) 3878 * page by mapping the page into virtual memory and using 3879 * bcopy to copy the page, one machine dependent page at a 3880 * time. 3881 */ 3882void 3883pmap_copy_page(vm_page_t src, vm_page_t dst) 3884{ 3885 struct sysmaps *sysmaps; 3886 3887 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)]; 3888 mtx_lock(&sysmaps->lock); 3889 if (*sysmaps->CMAP1) 3890 panic("pmap_copy_page: CMAP1 busy"); 3891 if (*sysmaps->CMAP2) 3892 panic("pmap_copy_page: CMAP2 busy"); 3893 sched_pin(); 3894 invlpg((u_int)sysmaps->CADDR1); 3895 invlpg((u_int)sysmaps->CADDR2); 3896 *sysmaps->CMAP1 = PG_V | VM_PAGE_TO_PHYS(src) | PG_A | 3897 pmap_cache_bits(src->md.pat_mode, 0); 3898 *sysmaps->CMAP2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(dst) | PG_A | PG_M | 3899 pmap_cache_bits(dst->md.pat_mode, 0); 3900 bcopy(sysmaps->CADDR1, sysmaps->CADDR2, PAGE_SIZE); 3901 *sysmaps->CMAP1 = 0; 3902 *sysmaps->CMAP2 = 0; 3903 sched_unpin(); 3904 mtx_unlock(&sysmaps->lock); 3905} 3906 3907/* 3908 * Returns true if the pmap's pv is one of the first 3909 * 16 pvs linked to from this page. This count may 3910 * be changed upwards or downwards in the future; it 3911 * is only necessary that true be returned for a small 3912 * subset of pmaps for proper page aging. 3913 */ 3914boolean_t 3915pmap_page_exists_quick(pmap_t pmap, vm_page_t m) 3916{ 3917 struct md_page *pvh; 3918 pv_entry_t pv; 3919 int loops = 0; 3920 3921 if (m->flags & PG_FICTITIOUS) 3922 return FALSE; 3923 3924 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 3925 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 3926 if (PV_PMAP(pv) == pmap) { 3927 return TRUE; 3928 } 3929 loops++; 3930 if (loops >= 16) 3931 break; 3932 } 3933 if (loops < 16) { 3934 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 3935 TAILQ_FOREACH(pv, &pvh->pv_list, pv_list) { 3936 if (PV_PMAP(pv) == pmap) 3937 return (TRUE); 3938 loops++; 3939 if (loops >= 16) 3940 break; 3941 } 3942 } 3943 return (FALSE); 3944} 3945 3946/* 3947 * pmap_page_wired_mappings: 3948 * 3949 * Return the number of managed mappings to the given physical page 3950 * that are wired. 3951 */ 3952int 3953pmap_page_wired_mappings(vm_page_t m) 3954{ 3955 int count; 3956 3957 count = 0; 3958 if ((m->flags & PG_FICTITIOUS) != 0) 3959 return (count); 3960 count = pmap_pvh_wired_mappings(&m->md, count); 3961 return (pmap_pvh_wired_mappings(pa_to_pvh(VM_PAGE_TO_PHYS(m)), count)); 3962} 3963 3964/* 3965 * pmap_pvh_wired_mappings: 3966 * 3967 * Return the updated number "count" of managed mappings that are wired. 3968 */ 3969static int 3970pmap_pvh_wired_mappings(struct md_page *pvh, int count) 3971{ 3972 pmap_t pmap; 3973 pt_entry_t *pte; 3974 pv_entry_t pv; 3975 3976 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 3977 sched_pin(); 3978 TAILQ_FOREACH(pv, &pvh->pv_list, pv_list) { 3979 pmap = PV_PMAP(pv); 3980 PMAP_LOCK(pmap); 3981 pte = pmap_pte_quick(pmap, pv->pv_va); 3982 if ((*pte & PG_W) != 0) 3983 count++; 3984 PMAP_UNLOCK(pmap); 3985 } 3986 sched_unpin(); 3987 return (count); 3988} 3989 3990/* 3991 * Returns TRUE if the given page is mapped individually or as part of 3992 * a 4mpage. Otherwise, returns FALSE. 3993 */ 3994boolean_t 3995pmap_page_is_mapped(vm_page_t m) 3996{ 3997 struct md_page *pvh; 3998 3999 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0) 4000 return (FALSE); 4001 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 4002 if (TAILQ_EMPTY(&m->md.pv_list)) { 4003 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 4004 return (!TAILQ_EMPTY(&pvh->pv_list)); 4005 } else 4006 return (TRUE); 4007} 4008 4009/* 4010 * Remove all pages from specified address space 4011 * this aids process exit speeds. Also, this code 4012 * is special cased for current process only, but 4013 * can have the more generic (and slightly slower) 4014 * mode enabled. This is much faster than pmap_remove 4015 * in the case of running down an entire address space. 4016 */ 4017void 4018pmap_remove_pages(pmap_t pmap) 4019{ 4020 pt_entry_t *pte, tpte; 4021 vm_page_t free = NULL; 4022 vm_page_t m, mpte, mt; 4023 pv_entry_t pv; 4024 struct md_page *pvh; 4025 struct pv_chunk *pc, *npc; 4026 int field, idx; 4027 int32_t bit; 4028 uint32_t inuse, bitmask; 4029 int allfree; 4030 4031 if (pmap != vmspace_pmap(curthread->td_proc->p_vmspace)) { 4032 printf("warning: pmap_remove_pages called with non-current pmap\n"); 4033 return; 4034 } 4035 vm_page_lock_queues(); 4036 PMAP_LOCK(pmap); 4037 sched_pin(); 4038 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) { 4039 allfree = 1; 4040 for (field = 0; field < _NPCM; field++) { 4041 inuse = (~(pc->pc_map[field])) & pc_freemask[field]; 4042 while (inuse != 0) { 4043 bit = bsfl(inuse); 4044 bitmask = 1UL << bit; 4045 idx = field * 32 + bit; 4046 pv = &pc->pc_pventry[idx]; 4047 inuse &= ~bitmask; 4048 4049 pte = pmap_pde(pmap, pv->pv_va); 4050 tpte = *pte; 4051 if ((tpte & PG_PS) == 0) { 4052 pte = vtopte(pv->pv_va); 4053 tpte = *pte & ~PG_PTE_PAT; 4054 } 4055 4056 if (tpte == 0) { 4057 printf( 4058 "TPTE at %p IS ZERO @ VA %08x\n", 4059 pte, pv->pv_va); 4060 panic("bad pte"); 4061 } 4062 4063/* 4064 * We cannot remove wired pages from a process' mapping at this time 4065 */ 4066 if (tpte & PG_W) { 4067 allfree = 0; 4068 continue; 4069 } 4070 4071 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME); 4072 KASSERT(m->phys_addr == (tpte & PG_FRAME), 4073 ("vm_page_t %p phys_addr mismatch %016jx %016jx", 4074 m, (uintmax_t)m->phys_addr, 4075 (uintmax_t)tpte)); 4076 4077 KASSERT(m < &vm_page_array[vm_page_array_size], 4078 ("pmap_remove_pages: bad tpte %#jx", 4079 (uintmax_t)tpte)); 4080 4081 pte_clear(pte); 4082 4083 /* 4084 * Update the vm_page_t clean/reference bits. 4085 */ 4086 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) { 4087 if ((tpte & PG_PS) != 0) { 4088 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++) 4089 vm_page_dirty(mt); 4090 } else 4091 vm_page_dirty(m); 4092 } 4093 4094 /* Mark free */ 4095 PV_STAT(pv_entry_frees++); 4096 PV_STAT(pv_entry_spare++); 4097 pv_entry_count--; 4098 pc->pc_map[field] |= bitmask; 4099 if ((tpte & PG_PS) != 0) { 4100 pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE; 4101 pvh = pa_to_pvh(tpte & PG_PS_FRAME); 4102 TAILQ_REMOVE(&pvh->pv_list, pv, pv_list); 4103 if (TAILQ_EMPTY(&pvh->pv_list)) { 4104 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++) 4105 if (TAILQ_EMPTY(&mt->md.pv_list)) 4106 vm_page_flag_clear(mt, PG_WRITEABLE); 4107 } 4108 mpte = pmap_lookup_pt_page(pmap, pv->pv_va); 4109 if (mpte != NULL) { 4110 pmap_remove_pt_page(pmap, mpte); 4111 pmap->pm_stats.resident_count--; 4112 KASSERT(mpte->wire_count == NPTEPG, 4113 ("pmap_remove_pages: pte page wire count error")); 4114 mpte->wire_count = 0; 4115 pmap_add_delayed_free_list(mpte, &free, FALSE); 4116 atomic_subtract_int(&cnt.v_wire_count, 1); 4117 } 4118 } else { 4119 pmap->pm_stats.resident_count--; 4120 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list); 4121 if (TAILQ_EMPTY(&m->md.pv_list)) { 4122 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 4123 if (TAILQ_EMPTY(&pvh->pv_list)) 4124 vm_page_flag_clear(m, PG_WRITEABLE); 4125 } 4126 pmap_unuse_pt(pmap, pv->pv_va, &free); 4127 } 4128 } 4129 } 4130 if (allfree) { 4131 PV_STAT(pv_entry_spare -= _NPCPV); 4132 PV_STAT(pc_chunk_count--); 4133 PV_STAT(pc_chunk_frees++); 4134 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 4135 m = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc)); 4136 pmap_qremove((vm_offset_t)pc, 1); 4137 vm_page_unwire(m, 0); 4138 vm_page_free(m); 4139 pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc); 4140 } 4141 } 4142 sched_unpin(); 4143 pmap_invalidate_all(pmap); 4144 vm_page_unlock_queues(); 4145 PMAP_UNLOCK(pmap); 4146 pmap_free_zero_pages(free); 4147} 4148 4149/* 4150 * pmap_is_modified: 4151 * 4152 * Return whether or not the specified physical page was modified 4153 * in any physical maps. 4154 */ 4155boolean_t 4156pmap_is_modified(vm_page_t m) 4157{ 4158 4159 if (m->flags & PG_FICTITIOUS) 4160 return (FALSE); 4161 if (pmap_is_modified_pvh(&m->md)) 4162 return (TRUE); 4163 return (pmap_is_modified_pvh(pa_to_pvh(VM_PAGE_TO_PHYS(m)))); 4164} 4165 4166/* 4167 * Returns TRUE if any of the given mappings were used to modify 4168 * physical memory. Otherwise, returns FALSE. Both page and 2mpage 4169 * mappings are supported. 4170 */ 4171static boolean_t 4172pmap_is_modified_pvh(struct md_page *pvh) 4173{ 4174 pv_entry_t pv; 4175 pt_entry_t *pte; 4176 pmap_t pmap; 4177 boolean_t rv; 4178 4179 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 4180 rv = FALSE; 4181 sched_pin(); 4182 TAILQ_FOREACH(pv, &pvh->pv_list, pv_list) { 4183 pmap = PV_PMAP(pv); 4184 PMAP_LOCK(pmap); 4185 pte = pmap_pte_quick(pmap, pv->pv_va); 4186 rv = (*pte & (PG_M | PG_RW)) == (PG_M | PG_RW); 4187 PMAP_UNLOCK(pmap); 4188 if (rv) 4189 break; 4190 } 4191 sched_unpin(); 4192 return (rv); 4193} 4194 4195/* 4196 * pmap_is_prefaultable: 4197 * 4198 * Return whether or not the specified virtual address is elgible 4199 * for prefault. 4200 */ 4201boolean_t 4202pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr) 4203{ 4204 pd_entry_t *pde; 4205 pt_entry_t *pte; 4206 boolean_t rv; 4207 4208 rv = FALSE; 4209 PMAP_LOCK(pmap); 4210 pde = pmap_pde(pmap, addr); 4211 if (*pde != 0 && (*pde & PG_PS) == 0) { 4212 pte = vtopte(addr); 4213 rv = *pte == 0; 4214 } 4215 PMAP_UNLOCK(pmap); 4216 return (rv); 4217} 4218 4219/* 4220 * Clear the write and modified bits in each of the given page's mappings. 4221 */ 4222void 4223pmap_remove_write(vm_page_t m) 4224{ 4225 struct md_page *pvh; 4226 pv_entry_t next_pv, pv; 4227 pmap_t pmap; 4228 pd_entry_t *pde; 4229 pt_entry_t oldpte, *pte; 4230 vm_offset_t va; 4231 4232 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 4233 if ((m->flags & PG_FICTITIOUS) != 0 || 4234 (m->flags & PG_WRITEABLE) == 0) 4235 return; 4236 sched_pin(); 4237 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 4238 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_list, next_pv) { 4239 va = pv->pv_va; 4240 pmap = PV_PMAP(pv); 4241 PMAP_LOCK(pmap); 4242 pde = pmap_pde(pmap, va); 4243 if ((*pde & PG_RW) != 0) 4244 (void)pmap_demote_pde(pmap, pde, va); 4245 PMAP_UNLOCK(pmap); 4246 } 4247 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 4248 pmap = PV_PMAP(pv); 4249 PMAP_LOCK(pmap); 4250 pde = pmap_pde(pmap, pv->pv_va); 4251 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_write: found" 4252 " a 4mpage in page %p's pv list", m)); 4253 pte = pmap_pte_quick(pmap, pv->pv_va); 4254retry: 4255 oldpte = *pte; 4256 if ((oldpte & PG_RW) != 0) { 4257 /* 4258 * Regardless of whether a pte is 32 or 64 bits 4259 * in size, PG_RW and PG_M are among the least 4260 * significant 32 bits. 4261 */ 4262 if (!atomic_cmpset_int((u_int *)pte, oldpte, 4263 oldpte & ~(PG_RW | PG_M))) 4264 goto retry; 4265 if ((oldpte & PG_M) != 0) 4266 vm_page_dirty(m); 4267 pmap_invalidate_page(pmap, pv->pv_va); 4268 } 4269 PMAP_UNLOCK(pmap); 4270 } 4271 vm_page_flag_clear(m, PG_WRITEABLE); 4272 sched_unpin(); 4273} 4274 4275/* 4276 * pmap_ts_referenced: 4277 * 4278 * Return a count of reference bits for a page, clearing those bits. 4279 * It is not necessary for every reference bit to be cleared, but it 4280 * is necessary that 0 only be returned when there are truly no 4281 * reference bits set. 4282 * 4283 * XXX: The exact number of bits to check and clear is a matter that 4284 * should be tested and standardized at some point in the future for 4285 * optimal aging of shared pages. 4286 */ 4287int 4288pmap_ts_referenced(vm_page_t m) 4289{ 4290 struct md_page *pvh; 4291 pv_entry_t pv, pvf, pvn; 4292 pmap_t pmap; 4293 pd_entry_t oldpde, *pde; 4294 pt_entry_t *pte; 4295 vm_offset_t va; 4296 int rtval = 0; 4297 4298 if (m->flags & PG_FICTITIOUS) 4299 return (rtval); 4300 sched_pin(); 4301 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 4302 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 4303 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_list, pvn) { 4304 va = pv->pv_va; 4305 pmap = PV_PMAP(pv); 4306 PMAP_LOCK(pmap); 4307 pde = pmap_pde(pmap, va); 4308 oldpde = *pde; 4309 if ((oldpde & PG_A) != 0) { 4310 if (pmap_demote_pde(pmap, pde, va)) { 4311 if ((oldpde & PG_W) == 0) { 4312 /* 4313 * Remove the mapping to a single page 4314 * so that a subsequent access may 4315 * repromote. Since the underlying 4316 * page table page is fully populated, 4317 * this removal never frees a page 4318 * table page. 4319 */ 4320 va += VM_PAGE_TO_PHYS(m) - (oldpde & 4321 PG_PS_FRAME); 4322 pmap_remove_page(pmap, va, NULL); 4323 rtval++; 4324 if (rtval > 4) { 4325 PMAP_UNLOCK(pmap); 4326 return (rtval); 4327 } 4328 } 4329 } 4330 } 4331 PMAP_UNLOCK(pmap); 4332 } 4333 if ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) { 4334 pvf = pv; 4335 do { 4336 pvn = TAILQ_NEXT(pv, pv_list); 4337 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list); 4338 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list); 4339 pmap = PV_PMAP(pv); 4340 PMAP_LOCK(pmap); 4341 pde = pmap_pde(pmap, pv->pv_va); 4342 KASSERT((*pde & PG_PS) == 0, ("pmap_ts_referenced:" 4343 " found a 4mpage in page %p's pv list", m)); 4344 pte = pmap_pte_quick(pmap, pv->pv_va); 4345 if ((*pte & PG_A) != 0) { 4346 atomic_clear_int((u_int *)pte, PG_A); 4347 pmap_invalidate_page(pmap, pv->pv_va); 4348 rtval++; 4349 if (rtval > 4) 4350 pvn = NULL; 4351 } 4352 PMAP_UNLOCK(pmap); 4353 } while ((pv = pvn) != NULL && pv != pvf); 4354 } 4355 sched_unpin(); 4356 return (rtval); 4357} 4358 4359/* 4360 * Clear the modify bits on the specified physical page. 4361 */ 4362void 4363pmap_clear_modify(vm_page_t m) 4364{ 4365 struct md_page *pvh; 4366 pv_entry_t next_pv, pv; 4367 pmap_t pmap; 4368 pd_entry_t oldpde, *pde; 4369 pt_entry_t oldpte, *pte; 4370 vm_offset_t va; 4371 4372 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 4373 if ((m->flags & PG_FICTITIOUS) != 0) 4374 return; 4375 sched_pin(); 4376 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 4377 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_list, next_pv) { 4378 va = pv->pv_va; 4379 pmap = PV_PMAP(pv); 4380 PMAP_LOCK(pmap); 4381 pde = pmap_pde(pmap, va); 4382 oldpde = *pde; 4383 if ((oldpde & PG_RW) != 0) { 4384 if (pmap_demote_pde(pmap, pde, va)) { 4385 if ((oldpde & PG_W) == 0) { 4386 /* 4387 * Write protect the mapping to a 4388 * single page so that a subsequent 4389 * write access may repromote. 4390 */ 4391 va += VM_PAGE_TO_PHYS(m) - (oldpde & 4392 PG_PS_FRAME); 4393 pte = pmap_pte_quick(pmap, va); 4394 oldpte = *pte; 4395 if ((oldpte & PG_V) != 0) { 4396 /* 4397 * Regardless of whether a pte is 32 or 64 bits 4398 * in size, PG_RW and PG_M are among the least 4399 * significant 32 bits. 4400 */ 4401 while (!atomic_cmpset_int((u_int *)pte, 4402 oldpte, 4403 oldpte & ~(PG_M | PG_RW))) 4404 oldpte = *pte; 4405 vm_page_dirty(m); 4406 pmap_invalidate_page(pmap, va); 4407 } 4408 } 4409 } 4410 } 4411 PMAP_UNLOCK(pmap); 4412 } 4413 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 4414 pmap = PV_PMAP(pv); 4415 PMAP_LOCK(pmap); 4416 pde = pmap_pde(pmap, pv->pv_va); 4417 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_modify: found" 4418 " a 4mpage in page %p's pv list", m)); 4419 pte = pmap_pte_quick(pmap, pv->pv_va); 4420 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) { 4421 /* 4422 * Regardless of whether a pte is 32 or 64 bits 4423 * in size, PG_M is among the least significant 4424 * 32 bits. 4425 */ 4426 atomic_clear_int((u_int *)pte, PG_M); 4427 pmap_invalidate_page(pmap, pv->pv_va); 4428 } 4429 PMAP_UNLOCK(pmap); 4430 } 4431 sched_unpin(); 4432} 4433 4434/* 4435 * pmap_clear_reference: 4436 * 4437 * Clear the reference bit on the specified physical page. 4438 */ 4439void 4440pmap_clear_reference(vm_page_t m) 4441{ 4442 struct md_page *pvh; 4443 pv_entry_t next_pv, pv; 4444 pmap_t pmap; 4445 pd_entry_t oldpde, *pde; 4446 pt_entry_t *pte; 4447 vm_offset_t va; 4448 4449 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 4450 if ((m->flags & PG_FICTITIOUS) != 0) 4451 return; 4452 sched_pin(); 4453 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 4454 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_list, next_pv) { 4455 va = pv->pv_va; 4456 pmap = PV_PMAP(pv); 4457 PMAP_LOCK(pmap); 4458 pde = pmap_pde(pmap, va); 4459 oldpde = *pde; 4460 if ((oldpde & PG_A) != 0) { 4461 if (pmap_demote_pde(pmap, pde, va)) { 4462 /* 4463 * Remove the mapping to a single page so 4464 * that a subsequent access may repromote. 4465 * Since the underlying page table page is 4466 * fully populated, this removal never frees 4467 * a page table page. 4468 */ 4469 va += VM_PAGE_TO_PHYS(m) - (oldpde & 4470 PG_PS_FRAME); 4471 pmap_remove_page(pmap, va, NULL); 4472 } 4473 } 4474 PMAP_UNLOCK(pmap); 4475 } 4476 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 4477 pmap = PV_PMAP(pv); 4478 PMAP_LOCK(pmap); 4479 pde = pmap_pde(pmap, pv->pv_va); 4480 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_reference: found" 4481 " a 4mpage in page %p's pv list", m)); 4482 pte = pmap_pte_quick(pmap, pv->pv_va); 4483 if ((*pte & PG_A) != 0) { 4484 /* 4485 * Regardless of whether a pte is 32 or 64 bits 4486 * in size, PG_A is among the least significant 4487 * 32 bits. 4488 */ 4489 atomic_clear_int((u_int *)pte, PG_A); 4490 pmap_invalidate_page(pmap, pv->pv_va); 4491 } 4492 PMAP_UNLOCK(pmap); 4493 } 4494 sched_unpin(); 4495} 4496 4497/* 4498 * Miscellaneous support routines follow 4499 */ 4500 4501/* Adjust the cache mode for a 4KB page mapped via a PTE. */ 4502static __inline void 4503pmap_pte_attr(pt_entry_t *pte, int cache_bits) 4504{ 4505 u_int opte, npte; 4506 4507 /* 4508 * The cache mode bits are all in the low 32-bits of the 4509 * PTE, so we can just spin on updating the low 32-bits. 4510 */ 4511 do { 4512 opte = *(u_int *)pte; 4513 npte = opte & ~PG_PTE_CACHE; 4514 npte |= cache_bits; 4515 } while (npte != opte && !atomic_cmpset_int((u_int *)pte, opte, npte)); 4516} 4517 4518/* Adjust the cache mode for a 2/4MB page mapped via a PDE. */ 4519static __inline void 4520pmap_pde_attr(pd_entry_t *pde, int cache_bits) 4521{ 4522 u_int opde, npde; 4523 4524 /* 4525 * The cache mode bits are all in the low 32-bits of the 4526 * PDE, so we can just spin on updating the low 32-bits. 4527 */ 4528 do { 4529 opde = *(u_int *)pde; 4530 npde = opde & ~PG_PDE_CACHE; 4531 npde |= cache_bits; 4532 } while (npde != opde && !atomic_cmpset_int((u_int *)pde, opde, npde)); 4533} 4534 4535/* 4536 * Map a set of physical memory pages into the kernel virtual 4537 * address space. Return a pointer to where it is mapped. This 4538 * routine is intended to be used for mapping device memory, 4539 * NOT real memory. 4540 */ 4541void * 4542pmap_mapdev_attr(vm_paddr_t pa, vm_size_t size, int mode) 4543{ 4544 vm_offset_t va, offset; 4545 vm_size_t tmpsize; 4546 4547 offset = pa & PAGE_MASK; 4548 size = roundup(offset + size, PAGE_SIZE); 4549 pa = pa & PG_FRAME; 4550 4551 if (pa < KERNLOAD && pa + size <= KERNLOAD) 4552 va = KERNBASE + pa; 4553 else 4554 va = kmem_alloc_nofault(kernel_map, size); 4555 if (!va) 4556 panic("pmap_mapdev: Couldn't alloc kernel virtual memory"); 4557 4558 for (tmpsize = 0; tmpsize < size; tmpsize += PAGE_SIZE) 4559 pmap_kenter_attr(va + tmpsize, pa + tmpsize, mode); 4560 pmap_invalidate_range(kernel_pmap, va, va + tmpsize); 4561 pmap_invalidate_cache_range(va, va + size); 4562 return ((void *)(va + offset)); 4563} 4564 4565void * 4566pmap_mapdev(vm_paddr_t pa, vm_size_t size) 4567{ 4568 4569 return (pmap_mapdev_attr(pa, size, PAT_UNCACHEABLE)); 4570} 4571 4572void * 4573pmap_mapbios(vm_paddr_t pa, vm_size_t size) 4574{ 4575 4576 return (pmap_mapdev_attr(pa, size, PAT_WRITE_BACK)); 4577} 4578 4579void 4580pmap_unmapdev(vm_offset_t va, vm_size_t size) 4581{ 4582 vm_offset_t base, offset, tmpva; 4583 4584 if (va >= KERNBASE && va + size <= KERNBASE + KERNLOAD) 4585 return; 4586 base = trunc_page(va); 4587 offset = va & PAGE_MASK; 4588 size = roundup(offset + size, PAGE_SIZE); 4589 for (tmpva = base; tmpva < (base + size); tmpva += PAGE_SIZE) 4590 pmap_kremove(tmpva); 4591 pmap_invalidate_range(kernel_pmap, va, tmpva); 4592 kmem_free(kernel_map, base, size); 4593} 4594 4595/* 4596 * Sets the memory attribute for the specified page. 4597 */ 4598void 4599pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma) 4600{ 4601 struct sysmaps *sysmaps; 4602 vm_offset_t sva, eva; 4603 4604 m->md.pat_mode = ma; 4605 if ((m->flags & PG_FICTITIOUS) != 0) 4606 return; 4607 4608 /* 4609 * If "m" is a normal page, flush it from the cache. 4610 * See pmap_invalidate_cache_range(). 4611 * 4612 * First, try to find an existing mapping of the page by sf 4613 * buffer. sf_buf_invalidate_cache() modifies mapping and 4614 * flushes the cache. 4615 */ 4616 if (sf_buf_invalidate_cache(m)) 4617 return; 4618 4619 /* 4620 * If page is not mapped by sf buffer, but CPU does not 4621 * support self snoop, map the page transient and do 4622 * invalidation. In the worst case, whole cache is flushed by 4623 * pmap_invalidate_cache_range(). 4624 */ 4625 if ((cpu_feature & (CPUID_SS|CPUID_CLFSH)) == CPUID_CLFSH) { 4626 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)]; 4627 mtx_lock(&sysmaps->lock); 4628 if (*sysmaps->CMAP2) 4629 panic("pmap_page_set_memattr: CMAP2 busy"); 4630 sched_pin(); 4631 *sysmaps->CMAP2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | 4632 PG_A | PG_M | pmap_cache_bits(m->md.pat_mode, 0); 4633 invlcaddr(sysmaps->CADDR2); 4634 sva = (vm_offset_t)sysmaps->CADDR2; 4635 eva = sva + PAGE_SIZE; 4636 } else 4637 sva = eva = 0; /* gcc */ 4638 pmap_invalidate_cache_range(sva, eva); 4639 if (sva != 0) { 4640 *sysmaps->CMAP2 = 0; 4641 sched_unpin(); 4642 mtx_unlock(&sysmaps->lock); 4643 } 4644} 4645 4646/* 4647 * Changes the specified virtual address range's memory type to that given by 4648 * the parameter "mode". The specified virtual address range must be 4649 * completely contained within either the kernel map. 4650 * 4651 * Returns zero if the change completed successfully, and either EINVAL or 4652 * ENOMEM if the change failed. Specifically, EINVAL is returned if some part 4653 * of the virtual address range was not mapped, and ENOMEM is returned if 4654 * there was insufficient memory available to complete the change. 4655 */ 4656int 4657pmap_change_attr(vm_offset_t va, vm_size_t size, int mode) 4658{ 4659 vm_offset_t base, offset, tmpva; 4660 pd_entry_t *pde; 4661 pt_entry_t *pte; 4662 int cache_bits_pte, cache_bits_pde; 4663 boolean_t changed; 4664 4665 base = trunc_page(va); 4666 offset = va & PAGE_MASK; 4667 size = roundup(offset + size, PAGE_SIZE); 4668 4669 /* 4670 * Only supported on kernel virtual addresses above the recursive map. 4671 */ 4672 if (base < VM_MIN_KERNEL_ADDRESS) 4673 return (EINVAL); 4674 4675 cache_bits_pde = pmap_cache_bits(mode, 1); 4676 cache_bits_pte = pmap_cache_bits(mode, 0); 4677 changed = FALSE; 4678 4679 /* 4680 * Pages that aren't mapped aren't supported. Also break down 4681 * 2/4MB pages into 4KB pages if required. 4682 */ 4683 PMAP_LOCK(kernel_pmap); 4684 for (tmpva = base; tmpva < base + size; ) { 4685 pde = pmap_pde(kernel_pmap, tmpva); 4686 if (*pde == 0) { 4687 PMAP_UNLOCK(kernel_pmap); 4688 return (EINVAL); 4689 } 4690 if (*pde & PG_PS) { 4691 /* 4692 * If the current 2/4MB page already has 4693 * the required memory type, then we need not 4694 * demote this page. Just increment tmpva to 4695 * the next 2/4MB page frame. 4696 */ 4697 if ((*pde & PG_PDE_CACHE) == cache_bits_pde) { 4698 tmpva = trunc_4mpage(tmpva) + NBPDR; 4699 continue; 4700 } 4701 4702 /* 4703 * If the current offset aligns with a 2/4MB 4704 * page frame and there is at least 2/4MB left 4705 * within the range, then we need not break 4706 * down this page into 4KB pages. 4707 */ 4708 if ((tmpva & PDRMASK) == 0 && 4709 tmpva + PDRMASK < base + size) { 4710 tmpva += NBPDR; 4711 continue; 4712 } 4713 if (!pmap_demote_pde(kernel_pmap, pde, tmpva)) { 4714 PMAP_UNLOCK(kernel_pmap); 4715 return (ENOMEM); 4716 } 4717 } 4718 pte = vtopte(tmpva); 4719 if (*pte == 0) { 4720 PMAP_UNLOCK(kernel_pmap); 4721 return (EINVAL); 4722 } 4723 tmpva += PAGE_SIZE; 4724 } 4725 PMAP_UNLOCK(kernel_pmap); 4726 4727 /* 4728 * Ok, all the pages exist, so run through them updating their 4729 * cache mode if required. 4730 */ 4731 for (tmpva = base; tmpva < base + size; ) { 4732 pde = pmap_pde(kernel_pmap, tmpva); 4733 if (*pde & PG_PS) { 4734 if ((*pde & PG_PDE_CACHE) != cache_bits_pde) { 4735 pmap_pde_attr(pde, cache_bits_pde); 4736 changed = TRUE; 4737 } 4738 tmpva = trunc_4mpage(tmpva) + NBPDR; 4739 } else { 4740 pte = vtopte(tmpva); 4741 if ((*pte & PG_PTE_CACHE) != cache_bits_pte) { 4742 pmap_pte_attr(pte, cache_bits_pte); 4743 changed = TRUE; 4744 } 4745 tmpva += PAGE_SIZE; 4746 } 4747 } 4748 4749 /* 4750 * Flush CPU caches to make sure any data isn't cached that 4751 * shouldn't be, etc. 4752 */ 4753 if (changed) { 4754 pmap_invalidate_range(kernel_pmap, base, tmpva); 4755 pmap_invalidate_cache_range(base, tmpva); 4756 } 4757 return (0); 4758} 4759 4760/* 4761 * perform the pmap work for mincore 4762 */ 4763int 4764pmap_mincore(pmap_t pmap, vm_offset_t addr) 4765{ 4766 pd_entry_t *pdep; 4767 pt_entry_t *ptep, pte; 4768 vm_paddr_t pa; 4769 vm_page_t m; 4770 int val = 0; 4771 4772 PMAP_LOCK(pmap); 4773 pdep = pmap_pde(pmap, addr); 4774 if (*pdep != 0) { 4775 if (*pdep & PG_PS) { 4776 pte = *pdep; 4777 val = MINCORE_SUPER; 4778 /* Compute the physical address of the 4KB page. */ 4779 pa = ((*pdep & PG_PS_FRAME) | (addr & PDRMASK)) & 4780 PG_FRAME; 4781 } else { 4782 ptep = pmap_pte(pmap, addr); 4783 pte = *ptep; 4784 pmap_pte_release(ptep); 4785 pa = pte & PG_FRAME; 4786 } 4787 } else { 4788 pte = 0; 4789 pa = 0; 4790 } 4791 PMAP_UNLOCK(pmap); 4792 4793 if (pte != 0) { 4794 val |= MINCORE_INCORE; 4795 if ((pte & PG_MANAGED) == 0) 4796 return val; 4797 4798 m = PHYS_TO_VM_PAGE(pa); 4799 4800 /* 4801 * Modified by us 4802 */ 4803 if ((pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) 4804 val |= MINCORE_MODIFIED|MINCORE_MODIFIED_OTHER; 4805 else { 4806 /* 4807 * Modified by someone else 4808 */ 4809 vm_page_lock_queues(); 4810 if (m->dirty || pmap_is_modified(m)) 4811 val |= MINCORE_MODIFIED_OTHER; 4812 vm_page_unlock_queues(); 4813 } 4814 /* 4815 * Referenced by us 4816 */ 4817 if (pte & PG_A) 4818 val |= MINCORE_REFERENCED|MINCORE_REFERENCED_OTHER; 4819 else { 4820 /* 4821 * Referenced by someone else 4822 */ 4823 vm_page_lock_queues(); 4824 if ((m->flags & PG_REFERENCED) || 4825 pmap_ts_referenced(m)) { 4826 val |= MINCORE_REFERENCED_OTHER; 4827 vm_page_flag_set(m, PG_REFERENCED); 4828 } 4829 vm_page_unlock_queues(); 4830 } 4831 } 4832 return val; 4833} 4834 4835void 4836pmap_activate(struct thread *td) 4837{ 4838 pmap_t pmap, oldpmap; 4839 u_int32_t cr3; 4840 4841 critical_enter(); 4842 pmap = vmspace_pmap(td->td_proc->p_vmspace); 4843 oldpmap = PCPU_GET(curpmap); 4844#if defined(SMP) 4845 atomic_clear_int(&oldpmap->pm_active, PCPU_GET(cpumask)); 4846 atomic_set_int(&pmap->pm_active, PCPU_GET(cpumask)); 4847#else 4848 oldpmap->pm_active &= ~1; 4849 pmap->pm_active |= 1; 4850#endif 4851#ifdef PAE 4852 cr3 = vtophys(pmap->pm_pdpt); 4853#else 4854 cr3 = vtophys(pmap->pm_pdir); 4855#endif 4856 /* 4857 * pmap_activate is for the current thread on the current cpu 4858 */ 4859 td->td_pcb->pcb_cr3 = cr3; 4860 load_cr3(cr3); 4861 PCPU_SET(curpmap, pmap); 4862 critical_exit(); 4863} 4864 4865void 4866pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz) 4867{ 4868} 4869 4870/* 4871 * Increase the starting virtual address of the given mapping if a 4872 * different alignment might result in more superpage mappings. 4873 */ 4874void 4875pmap_align_superpage(vm_object_t object, vm_ooffset_t offset, 4876 vm_offset_t *addr, vm_size_t size) 4877{ 4878 vm_offset_t superpage_offset; 4879 4880 if (size < NBPDR) 4881 return; 4882 if (object != NULL && (object->flags & OBJ_COLORED) != 0) 4883 offset += ptoa(object->pg_color); 4884 superpage_offset = offset & PDRMASK; 4885 if (size - ((NBPDR - superpage_offset) & PDRMASK) < NBPDR || 4886 (*addr & PDRMASK) == superpage_offset) 4887 return; 4888 if ((*addr & PDRMASK) < superpage_offset) 4889 *addr = (*addr & ~PDRMASK) + superpage_offset; 4890 else 4891 *addr = ((*addr + PDRMASK) & ~PDRMASK) + superpage_offset; 4892} 4893 4894 4895#if defined(PMAP_DEBUG) 4896pmap_pid_dump(int pid) 4897{ 4898 pmap_t pmap; 4899 struct proc *p; 4900 int npte = 0; 4901 int index; 4902 4903 sx_slock(&allproc_lock); 4904 FOREACH_PROC_IN_SYSTEM(p) { 4905 if (p->p_pid != pid) 4906 continue; 4907 4908 if (p->p_vmspace) { 4909 int i,j; 4910 index = 0; 4911 pmap = vmspace_pmap(p->p_vmspace); 4912 for (i = 0; i < NPDEPTD; i++) { 4913 pd_entry_t *pde; 4914 pt_entry_t *pte; 4915 vm_offset_t base = i << PDRSHIFT; 4916 4917 pde = &pmap->pm_pdir[i]; 4918 if (pde && pmap_pde_v(pde)) { 4919 for (j = 0; j < NPTEPG; j++) { 4920 vm_offset_t va = base + (j << PAGE_SHIFT); 4921 if (va >= (vm_offset_t) VM_MIN_KERNEL_ADDRESS) { 4922 if (index) { 4923 index = 0; 4924 printf("\n"); 4925 } 4926 sx_sunlock(&allproc_lock); 4927 return npte; 4928 } 4929 pte = pmap_pte(pmap, va); 4930 if (pte && pmap_pte_v(pte)) { 4931 pt_entry_t pa; 4932 vm_page_t m; 4933 pa = *pte; 4934 m = PHYS_TO_VM_PAGE(pa & PG_FRAME); 4935 printf("va: 0x%x, pt: 0x%x, h: %d, w: %d, f: 0x%x", 4936 va, pa, m->hold_count, m->wire_count, m->flags); 4937 npte++; 4938 index++; 4939 if (index >= 2) { 4940 index = 0; 4941 printf("\n"); 4942 } else { 4943 printf(" "); 4944 } 4945 } 4946 } 4947 } 4948 } 4949 } 4950 } 4951 sx_sunlock(&allproc_lock); 4952 return npte; 4953} 4954#endif 4955 4956#if defined(DEBUG) 4957 4958static void pads(pmap_t pm); 4959void pmap_pvdump(vm_offset_t pa); 4960 4961/* print address space of pmap*/ 4962static void 4963pads(pmap_t pm) 4964{ 4965 int i, j; 4966 vm_paddr_t va; 4967 pt_entry_t *ptep; 4968 4969 if (pm == kernel_pmap) 4970 return; 4971 for (i = 0; i < NPDEPTD; i++) 4972 if (pm->pm_pdir[i]) 4973 for (j = 0; j < NPTEPG; j++) { 4974 va = (i << PDRSHIFT) + (j << PAGE_SHIFT); 4975 if (pm == kernel_pmap && va < KERNBASE) 4976 continue; 4977 if (pm != kernel_pmap && va > UPT_MAX_ADDRESS) 4978 continue; 4979 ptep = pmap_pte(pm, va); 4980 if (pmap_pte_v(ptep)) 4981 printf("%x:%x ", va, *ptep); 4982 }; 4983 4984} 4985 4986void 4987pmap_pvdump(vm_paddr_t pa) 4988{ 4989 pv_entry_t pv; 4990 pmap_t pmap; 4991 vm_page_t m; 4992 4993 printf("pa %x", pa); 4994 m = PHYS_TO_VM_PAGE(pa); 4995 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 4996 pmap = PV_PMAP(pv); 4997 printf(" -> pmap %p, va %x", (void *)pmap, pv->pv_va); 4998 pads(pmap); 4999 } 5000 printf(" "); 5001} 5002#endif 5003