pmap.c revision 188608
1/*- 2 * Copyright (c) 1991 Regents of the University of California. 3 * All rights reserved. 4 * Copyright (c) 1994 John S. Dyson 5 * All rights reserved. 6 * Copyright (c) 1994 David Greenman 7 * All rights reserved. 8 * Copyright (c) 2005-2008 Alan L. Cox <alc@cs.rice.edu> 9 * All rights reserved. 10 * 11 * This code is derived from software contributed to Berkeley by 12 * the Systems Programming Group of the University of Utah Computer 13 * Science Department and William Jolitz of UUNET Technologies Inc. 14 * 15 * Redistribution and use in source and binary forms, with or without 16 * modification, are permitted provided that the following conditions 17 * are met: 18 * 1. Redistributions of source code must retain the above copyright 19 * notice, this list of conditions and the following disclaimer. 20 * 2. Redistributions in binary form must reproduce the above copyright 21 * notice, this list of conditions and the following disclaimer in the 22 * documentation and/or other materials provided with the distribution. 23 * 3. All advertising materials mentioning features or use of this software 24 * must display the following acknowledgement: 25 * This product includes software developed by the University of 26 * California, Berkeley and its contributors. 27 * 4. Neither the name of the University nor the names of its contributors 28 * may be used to endorse or promote products derived from this software 29 * without specific prior written permission. 30 * 31 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 32 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 33 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 34 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 35 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 36 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 37 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 38 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 39 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 40 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 41 * SUCH DAMAGE. 42 * 43 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91 44 */ 45/*- 46 * Copyright (c) 2003 Networks Associates Technology, Inc. 47 * All rights reserved. 48 * 49 * This software was developed for the FreeBSD Project by Jake Burkholder, 50 * Safeport Network Services, and Network Associates Laboratories, the 51 * Security Research Division of Network Associates, Inc. under 52 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA 53 * CHATS research program. 54 * 55 * Redistribution and use in source and binary forms, with or without 56 * modification, are permitted provided that the following conditions 57 * are met: 58 * 1. Redistributions of source code must retain the above copyright 59 * notice, this list of conditions and the following disclaimer. 60 * 2. Redistributions in binary form must reproduce the above copyright 61 * notice, this list of conditions and the following disclaimer in the 62 * documentation and/or other materials provided with the distribution. 63 * 64 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 65 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 66 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 67 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 68 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 69 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 70 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 71 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 72 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 73 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 74 * SUCH DAMAGE. 75 */ 76 77#include <sys/cdefs.h> 78__FBSDID("$FreeBSD: head/sys/i386/i386/pmap.c 188608 2009-02-14 18:23:52Z alc $"); 79 80/* 81 * Manages physical address maps. 82 * 83 * In addition to hardware address maps, this 84 * module is called upon to provide software-use-only 85 * maps which may or may not be stored in the same 86 * form as hardware maps. These pseudo-maps are 87 * used to store intermediate results from copy 88 * operations to and from address spaces. 89 * 90 * Since the information managed by this module is 91 * also stored by the logical address mapping module, 92 * this module may throw away valid virtual-to-physical 93 * mappings at almost any time. However, invalidations 94 * of virtual-to-physical mappings must be done as 95 * requested. 96 * 97 * In order to cope with hardware architectures which 98 * make virtual-to-physical map invalidates expensive, 99 * this module may delay invalidate or reduced protection 100 * operations until such time as they are actually 101 * necessary. This module is given full information as 102 * to which processors are currently using which maps, 103 * and to when physical maps must be made correct. 104 */ 105 106#include "opt_cpu.h" 107#include "opt_pmap.h" 108#include "opt_msgbuf.h" 109#include "opt_smp.h" 110#include "opt_xbox.h" 111 112#include <sys/param.h> 113#include <sys/systm.h> 114#include <sys/kernel.h> 115#include <sys/ktr.h> 116#include <sys/lock.h> 117#include <sys/malloc.h> 118#include <sys/mman.h> 119#include <sys/msgbuf.h> 120#include <sys/mutex.h> 121#include <sys/proc.h> 122#include <sys/sx.h> 123#include <sys/vmmeter.h> 124#include <sys/sched.h> 125#include <sys/sysctl.h> 126#ifdef SMP 127#include <sys/smp.h> 128#endif 129 130#include <vm/vm.h> 131#include <vm/vm_param.h> 132#include <vm/vm_kern.h> 133#include <vm/vm_page.h> 134#include <vm/vm_map.h> 135#include <vm/vm_object.h> 136#include <vm/vm_extern.h> 137#include <vm/vm_pageout.h> 138#include <vm/vm_pager.h> 139#include <vm/vm_reserv.h> 140#include <vm/uma.h> 141 142#include <machine/cpu.h> 143#include <machine/cputypes.h> 144#include <machine/md_var.h> 145#include <machine/pcb.h> 146#include <machine/specialreg.h> 147#ifdef SMP 148#include <machine/smp.h> 149#endif 150 151#ifdef XBOX 152#include <machine/xbox.h> 153#endif 154 155#if !defined(CPU_DISABLE_SSE) && defined(I686_CPU) 156#define CPU_ENABLE_SSE 157#endif 158 159#ifndef PMAP_SHPGPERPROC 160#define PMAP_SHPGPERPROC 200 161#endif 162 163#if !defined(DIAGNOSTIC) 164#define PMAP_INLINE __gnu89_inline 165#else 166#define PMAP_INLINE 167#endif 168 169#define PV_STATS 170#ifdef PV_STATS 171#define PV_STAT(x) do { x ; } while (0) 172#else 173#define PV_STAT(x) do { } while (0) 174#endif 175 176#define pa_index(pa) ((pa) >> PDRSHIFT) 177#define pa_to_pvh(pa) (&pv_table[pa_index(pa)]) 178 179/* 180 * Get PDEs and PTEs for user/kernel address space 181 */ 182#define pmap_pde(m, v) (&((m)->pm_pdir[(vm_offset_t)(v) >> PDRSHIFT])) 183#define pdir_pde(m, v) (m[(vm_offset_t)(v) >> PDRSHIFT]) 184 185#define pmap_pde_v(pte) ((*(int *)pte & PG_V) != 0) 186#define pmap_pte_w(pte) ((*(int *)pte & PG_W) != 0) 187#define pmap_pte_m(pte) ((*(int *)pte & PG_M) != 0) 188#define pmap_pte_u(pte) ((*(int *)pte & PG_A) != 0) 189#define pmap_pte_v(pte) ((*(int *)pte & PG_V) != 0) 190 191#define pmap_pte_set_w(pte, v) ((v) ? atomic_set_int((u_int *)(pte), PG_W) : \ 192 atomic_clear_int((u_int *)(pte), PG_W)) 193#define pmap_pte_set_prot(pte, v) ((*(int *)pte &= ~PG_PROT), (*(int *)pte |= (v))) 194 195struct pmap kernel_pmap_store; 196LIST_HEAD(pmaplist, pmap); 197static struct pmaplist allpmaps; 198static struct mtx allpmaps_lock; 199 200vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */ 201vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */ 202int pgeflag = 0; /* PG_G or-in */ 203int pseflag = 0; /* PG_PS or-in */ 204 205static int nkpt; 206vm_offset_t kernel_vm_end; 207extern u_int32_t KERNend; 208 209#ifdef PAE 210pt_entry_t pg_nx; 211static uma_zone_t pdptzone; 212#endif 213 214SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD, 0, "VM/pmap parameters"); 215 216static int pg_ps_enabled; 217SYSCTL_INT(_vm_pmap, OID_AUTO, pg_ps_enabled, CTLFLAG_RD, &pg_ps_enabled, 0, 218 "Are large page mappings enabled?"); 219 220/* 221 * Data for the pv entry allocation mechanism 222 */ 223static int pv_entry_count = 0, pv_entry_max = 0, pv_entry_high_water = 0; 224static struct md_page *pv_table; 225static int shpgperproc = PMAP_SHPGPERPROC; 226 227struct pv_chunk *pv_chunkbase; /* KVA block for pv_chunks */ 228int pv_maxchunks; /* How many chunks we have KVA for */ 229vm_offset_t pv_vafree; /* freelist stored in the PTE */ 230 231/* 232 * All those kernel PT submaps that BSD is so fond of 233 */ 234struct sysmaps { 235 struct mtx lock; 236 pt_entry_t *CMAP1; 237 pt_entry_t *CMAP2; 238 caddr_t CADDR1; 239 caddr_t CADDR2; 240}; 241static struct sysmaps sysmaps_pcpu[MAXCPU]; 242pt_entry_t *CMAP1 = 0; 243static pt_entry_t *CMAP3; 244caddr_t CADDR1 = 0, ptvmmap = 0; 245static caddr_t CADDR3; 246struct msgbuf *msgbufp = 0; 247 248/* 249 * Crashdump maps. 250 */ 251static caddr_t crashdumpmap; 252 253static pt_entry_t *PMAP1 = 0, *PMAP2; 254static pt_entry_t *PADDR1 = 0, *PADDR2; 255#ifdef SMP 256static int PMAP1cpu; 257static int PMAP1changedcpu; 258SYSCTL_INT(_debug, OID_AUTO, PMAP1changedcpu, CTLFLAG_RD, 259 &PMAP1changedcpu, 0, 260 "Number of times pmap_pte_quick changed CPU with same PMAP1"); 261#endif 262static int PMAP1changed; 263SYSCTL_INT(_debug, OID_AUTO, PMAP1changed, CTLFLAG_RD, 264 &PMAP1changed, 0, 265 "Number of times pmap_pte_quick changed PMAP1"); 266static int PMAP1unchanged; 267SYSCTL_INT(_debug, OID_AUTO, PMAP1unchanged, CTLFLAG_RD, 268 &PMAP1unchanged, 0, 269 "Number of times pmap_pte_quick didn't change PMAP1"); 270static struct mtx PMAP2mutex; 271 272static void free_pv_entry(pmap_t pmap, pv_entry_t pv); 273static pv_entry_t get_pv_entry(pmap_t locked_pmap, int try); 274static void pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa); 275static boolean_t pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa); 276static void pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa); 277static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va); 278static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, 279 vm_offset_t va); 280static int pmap_pvh_wired_mappings(struct md_page *pvh, int count); 281 282static boolean_t pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va); 283static boolean_t pmap_enter_pde(pmap_t pmap, vm_offset_t va, vm_page_t m, 284 vm_prot_t prot); 285static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, 286 vm_page_t m, vm_prot_t prot, vm_page_t mpte); 287static void pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte); 288static boolean_t pmap_is_modified_pvh(struct md_page *pvh); 289static void pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode); 290static vm_page_t pmap_lookup_pt_page(pmap_t pmap, vm_offset_t va); 291static void pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va); 292static boolean_t pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva, 293 vm_prot_t prot); 294static void pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva, 295 vm_page_t *free); 296static int pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t sva, 297 vm_page_t *free); 298static void pmap_remove_pt_page(pmap_t pmap, vm_page_t mpte); 299static void pmap_remove_page(struct pmap *pmap, vm_offset_t va, 300 vm_page_t *free); 301static void pmap_remove_entry(struct pmap *pmap, vm_page_t m, 302 vm_offset_t va); 303static void pmap_insert_entry(pmap_t pmap, vm_offset_t va, vm_page_t m); 304static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, 305 vm_page_t m); 306 307static vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va, int flags); 308 309static vm_page_t _pmap_allocpte(pmap_t pmap, unsigned ptepindex, int flags); 310static int _pmap_unwire_pte_hold(pmap_t pmap, vm_page_t m, vm_page_t *free); 311static pt_entry_t *pmap_pte_quick(pmap_t pmap, vm_offset_t va); 312static void pmap_pte_release(pt_entry_t *pte); 313static int pmap_unuse_pt(pmap_t, vm_offset_t, vm_page_t *); 314static vm_offset_t pmap_kmem_choose(vm_offset_t addr); 315#ifdef PAE 316static void *pmap_pdpt_allocf(uma_zone_t zone, int bytes, u_int8_t *flags, int wait); 317#endif 318 319CTASSERT(1 << PDESHIFT == sizeof(pd_entry_t)); 320CTASSERT(1 << PTESHIFT == sizeof(pt_entry_t)); 321 322/* 323 * If you get an error here, then you set KVA_PAGES wrong! See the 324 * description of KVA_PAGES in sys/i386/include/pmap.h. It must be 325 * multiple of 4 for a normal kernel, or a multiple of 8 for a PAE. 326 */ 327CTASSERT(KERNBASE % (1 << 24) == 0); 328 329/* 330 * Move the kernel virtual free pointer to the next 331 * 4MB. This is used to help improve performance 332 * by using a large (4MB) page for much of the kernel 333 * (.text, .data, .bss) 334 */ 335static vm_offset_t 336pmap_kmem_choose(vm_offset_t addr) 337{ 338 vm_offset_t newaddr = addr; 339 340#ifndef DISABLE_PSE 341 if (cpu_feature & CPUID_PSE) 342 newaddr = (addr + PDRMASK) & ~PDRMASK; 343#endif 344 return newaddr; 345} 346 347/* 348 * Bootstrap the system enough to run with virtual memory. 349 * 350 * On the i386 this is called after mapping has already been enabled 351 * and just syncs the pmap module with what has already been done. 352 * [We can't call it easily with mapping off since the kernel is not 353 * mapped with PA == VA, hence we would have to relocate every address 354 * from the linked base (virtual) address "KERNBASE" to the actual 355 * (physical) address starting relative to 0] 356 */ 357void 358pmap_bootstrap(vm_paddr_t firstaddr) 359{ 360 vm_offset_t va; 361 pt_entry_t *pte, *unused; 362 struct sysmaps *sysmaps; 363 int i; 364 365 /* 366 * XXX The calculation of virtual_avail is wrong. It's NKPT*PAGE_SIZE too 367 * large. It should instead be correctly calculated in locore.s and 368 * not based on 'first' (which is a physical address, not a virtual 369 * address, for the start of unused physical memory). The kernel 370 * page tables are NOT double mapped and thus should not be included 371 * in this calculation. 372 */ 373 virtual_avail = (vm_offset_t) KERNBASE + firstaddr; 374 virtual_avail = pmap_kmem_choose(virtual_avail); 375 376 virtual_end = VM_MAX_KERNEL_ADDRESS; 377 378 /* 379 * Initialize the kernel pmap (which is statically allocated). 380 */ 381 PMAP_LOCK_INIT(kernel_pmap); 382 kernel_pmap->pm_pdir = (pd_entry_t *) (KERNBASE + (u_int)IdlePTD); 383#ifdef PAE 384 kernel_pmap->pm_pdpt = (pdpt_entry_t *) (KERNBASE + (u_int)IdlePDPT); 385#endif 386 kernel_pmap->pm_root = NULL; 387 kernel_pmap->pm_active = -1; /* don't allow deactivation */ 388 TAILQ_INIT(&kernel_pmap->pm_pvchunk); 389 LIST_INIT(&allpmaps); 390 mtx_init(&allpmaps_lock, "allpmaps", NULL, MTX_SPIN); 391 mtx_lock_spin(&allpmaps_lock); 392 LIST_INSERT_HEAD(&allpmaps, kernel_pmap, pm_list); 393 mtx_unlock_spin(&allpmaps_lock); 394 nkpt = NKPT; 395 396 /* 397 * Reserve some special page table entries/VA space for temporary 398 * mapping of pages. 399 */ 400#define SYSMAP(c, p, v, n) \ 401 v = (c)va; va += ((n)*PAGE_SIZE); p = pte; pte += (n); 402 403 va = virtual_avail; 404 pte = vtopte(va); 405 406 /* 407 * CMAP1/CMAP2 are used for zeroing and copying pages. 408 * CMAP3 is used for the idle process page zeroing. 409 */ 410 for (i = 0; i < MAXCPU; i++) { 411 sysmaps = &sysmaps_pcpu[i]; 412 mtx_init(&sysmaps->lock, "SYSMAPS", NULL, MTX_DEF); 413 SYSMAP(caddr_t, sysmaps->CMAP1, sysmaps->CADDR1, 1) 414 SYSMAP(caddr_t, sysmaps->CMAP2, sysmaps->CADDR2, 1) 415 } 416 SYSMAP(caddr_t, CMAP1, CADDR1, 1) 417 SYSMAP(caddr_t, CMAP3, CADDR3, 1) 418 *CMAP3 = 0; 419 420 /* 421 * Crashdump maps. 422 */ 423 SYSMAP(caddr_t, unused, crashdumpmap, MAXDUMPPGS) 424 425 /* 426 * ptvmmap is used for reading arbitrary physical pages via /dev/mem. 427 */ 428 SYSMAP(caddr_t, unused, ptvmmap, 1) 429 430 /* 431 * msgbufp is used to map the system message buffer. 432 */ 433 SYSMAP(struct msgbuf *, unused, msgbufp, atop(round_page(MSGBUF_SIZE))) 434 435 /* 436 * ptemap is used for pmap_pte_quick 437 */ 438 SYSMAP(pt_entry_t *, PMAP1, PADDR1, 1); 439 SYSMAP(pt_entry_t *, PMAP2, PADDR2, 1); 440 441 mtx_init(&PMAP2mutex, "PMAP2", NULL, MTX_DEF); 442 443 virtual_avail = va; 444 445 *CMAP1 = 0; 446 447 /* 448 * Leave in place an identity mapping (virt == phys) for the low 1 MB 449 * physical memory region that is used by the ACPI wakeup code. This 450 * mapping must not have PG_G set. 451 */ 452#ifdef XBOX 453 /* FIXME: This is gross, but needed for the XBOX. Since we are in such 454 * an early stadium, we cannot yet neatly map video memory ... :-( 455 * Better fixes are very welcome! */ 456 if (!arch_i386_is_xbox) 457#endif 458 for (i = 1; i < NKPT; i++) 459 PTD[i] = 0; 460 461 /* Initialize the PAT MSR if present. */ 462 pmap_init_pat(); 463 464 /* Turn on PG_G on kernel page(s) */ 465 pmap_set_pg(); 466} 467 468/* 469 * Setup the PAT MSR. 470 */ 471void 472pmap_init_pat(void) 473{ 474 uint64_t pat_msr; 475 476 /* Bail if this CPU doesn't implement PAT. */ 477 if (!(cpu_feature & CPUID_PAT)) 478 return; 479 480#ifdef PAT_WORKS 481 /* 482 * Leave the indices 0-3 at the default of WB, WT, UC, and UC-. 483 * Program 4 and 5 as WP and WC. 484 * Leave 6 and 7 as UC and UC-. 485 */ 486 pat_msr = rdmsr(MSR_PAT); 487 pat_msr &= ~(PAT_MASK(4) | PAT_MASK(5)); 488 pat_msr |= PAT_VALUE(4, PAT_WRITE_PROTECTED) | 489 PAT_VALUE(5, PAT_WRITE_COMBINING); 490#else 491 /* 492 * Due to some Intel errata, we can only safely use the lower 4 493 * PAT entries. Thus, just replace PAT Index 2 with WC instead 494 * of UC-. 495 * 496 * Intel Pentium III Processor Specification Update 497 * Errata E.27 (Upper Four PAT Entries Not Usable With Mode B 498 * or Mode C Paging) 499 * 500 * Intel Pentium IV Processor Specification Update 501 * Errata N46 (PAT Index MSB May Be Calculated Incorrectly) 502 */ 503 pat_msr = rdmsr(MSR_PAT); 504 pat_msr &= ~PAT_MASK(2); 505 pat_msr |= PAT_VALUE(2, PAT_WRITE_COMBINING); 506#endif 507 wrmsr(MSR_PAT, pat_msr); 508} 509 510/* 511 * Set PG_G on kernel pages. Only the BSP calls this when SMP is turned on. 512 */ 513void 514pmap_set_pg(void) 515{ 516 pd_entry_t pdir; 517 pt_entry_t *pte; 518 vm_offset_t va, endva; 519 int i; 520 521 if (pgeflag == 0) 522 return; 523 524 i = KERNLOAD/NBPDR; 525 endva = KERNBASE + KERNend; 526 527 if (pseflag) { 528 va = KERNBASE + KERNLOAD; 529 while (va < endva) { 530 pdir = kernel_pmap->pm_pdir[KPTDI+i]; 531 pdir |= pgeflag; 532 kernel_pmap->pm_pdir[KPTDI+i] = PTD[KPTDI+i] = pdir; 533 invltlb(); /* Play it safe, invltlb() every time */ 534 i++; 535 va += NBPDR; 536 } 537 } else { 538 va = (vm_offset_t)btext; 539 while (va < endva) { 540 pte = vtopte(va); 541 if (*pte) 542 *pte |= pgeflag; 543 invltlb(); /* Play it safe, invltlb() every time */ 544 va += PAGE_SIZE; 545 } 546 } 547} 548 549/* 550 * Initialize a vm_page's machine-dependent fields. 551 */ 552void 553pmap_page_init(vm_page_t m) 554{ 555 556 TAILQ_INIT(&m->md.pv_list); 557} 558 559#ifdef PAE 560 561static MALLOC_DEFINE(M_PMAPPDPT, "pmap", "pmap pdpt"); 562 563static void * 564pmap_pdpt_allocf(uma_zone_t zone, int bytes, u_int8_t *flags, int wait) 565{ 566 567 /* Inform UMA that this allocator uses kernel_map/object. */ 568 *flags = UMA_SLAB_KERNEL; 569 return (contigmalloc(PAGE_SIZE, M_PMAPPDPT, 0, 0x0ULL, 0xffffffffULL, 570 1, 0)); 571} 572#endif 573 574/* 575 * ABuse the pte nodes for unmapped kva to thread a kva freelist through. 576 * Requirements: 577 * - Must deal with pages in order to ensure that none of the PG_* bits 578 * are ever set, PG_V in particular. 579 * - Assumes we can write to ptes without pte_store() atomic ops, even 580 * on PAE systems. This should be ok. 581 * - Assumes nothing will ever test these addresses for 0 to indicate 582 * no mapping instead of correctly checking PG_V. 583 * - Assumes a vm_offset_t will fit in a pte (true for i386). 584 * Because PG_V is never set, there can be no mappings to invalidate. 585 */ 586static vm_offset_t 587pmap_ptelist_alloc(vm_offset_t *head) 588{ 589 pt_entry_t *pte; 590 vm_offset_t va; 591 592 va = *head; 593 if (va == 0) 594 return (va); /* Out of memory */ 595 pte = vtopte(va); 596 *head = *pte; 597 if (*head & PG_V) 598 panic("pmap_ptelist_alloc: va with PG_V set!"); 599 *pte = 0; 600 return (va); 601} 602 603static void 604pmap_ptelist_free(vm_offset_t *head, vm_offset_t va) 605{ 606 pt_entry_t *pte; 607 608 if (va & PG_V) 609 panic("pmap_ptelist_free: freeing va with PG_V set!"); 610 pte = vtopte(va); 611 *pte = *head; /* virtual! PG_V is 0 though */ 612 *head = va; 613} 614 615static void 616pmap_ptelist_init(vm_offset_t *head, void *base, int npages) 617{ 618 int i; 619 vm_offset_t va; 620 621 *head = 0; 622 for (i = npages - 1; i >= 0; i--) { 623 va = (vm_offset_t)base + i * PAGE_SIZE; 624 pmap_ptelist_free(head, va); 625 } 626} 627 628 629/* 630 * Initialize the pmap module. 631 * Called by vm_init, to initialize any structures that the pmap 632 * system needs to map virtual memory. 633 */ 634void 635pmap_init(void) 636{ 637 vm_page_t mpte; 638 vm_size_t s; 639 int i, pv_npg; 640 641 /* 642 * Initialize the vm page array entries for the kernel pmap's 643 * page table pages. 644 */ 645 for (i = 0; i < nkpt; i++) { 646 mpte = PHYS_TO_VM_PAGE(PTD[i + KPTDI] & PG_FRAME); 647 KASSERT(mpte >= vm_page_array && 648 mpte < &vm_page_array[vm_page_array_size], 649 ("pmap_init: page table page is out of range")); 650 mpte->pindex = i + KPTDI; 651 mpte->phys_addr = PTD[i + KPTDI] & PG_FRAME; 652 } 653 654 /* 655 * Initialize the address space (zone) for the pv entries. Set a 656 * high water mark so that the system can recover from excessive 657 * numbers of pv entries. 658 */ 659 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc); 660 pv_entry_max = shpgperproc * maxproc + cnt.v_page_count; 661 TUNABLE_INT_FETCH("vm.pmap.pv_entries", &pv_entry_max); 662 pv_entry_max = roundup(pv_entry_max, _NPCPV); 663 pv_entry_high_water = 9 * (pv_entry_max / 10); 664 665 /* 666 * Are large page mappings enabled? 667 */ 668 TUNABLE_INT_FETCH("vm.pmap.pg_ps_enabled", &pg_ps_enabled); 669 670 /* 671 * Calculate the size of the pv head table for superpages. 672 */ 673 for (i = 0; phys_avail[i + 1]; i += 2); 674 pv_npg = round_4mpage(phys_avail[(i - 2) + 1]) / NBPDR; 675 676 /* 677 * Allocate memory for the pv head table for superpages. 678 */ 679 s = (vm_size_t)(pv_npg * sizeof(struct md_page)); 680 s = round_page(s); 681 pv_table = (struct md_page *)kmem_alloc(kernel_map, s); 682 for (i = 0; i < pv_npg; i++) 683 TAILQ_INIT(&pv_table[i].pv_list); 684 685 pv_maxchunks = MAX(pv_entry_max / _NPCPV, maxproc); 686 pv_chunkbase = (struct pv_chunk *)kmem_alloc_nofault(kernel_map, 687 PAGE_SIZE * pv_maxchunks); 688 if (pv_chunkbase == NULL) 689 panic("pmap_init: not enough kvm for pv chunks"); 690 pmap_ptelist_init(&pv_vafree, pv_chunkbase, pv_maxchunks); 691#ifdef PAE 692 pdptzone = uma_zcreate("PDPT", NPGPTD * sizeof(pdpt_entry_t), NULL, 693 NULL, NULL, NULL, (NPGPTD * sizeof(pdpt_entry_t)) - 1, 694 UMA_ZONE_VM | UMA_ZONE_NOFREE); 695 uma_zone_set_allocf(pdptzone, pmap_pdpt_allocf); 696#endif 697} 698 699 700SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_max, CTLFLAG_RD, &pv_entry_max, 0, 701 "Max number of PV entries"); 702SYSCTL_INT(_vm_pmap, OID_AUTO, shpgperproc, CTLFLAG_RD, &shpgperproc, 0, 703 "Page share factor per proc"); 704 705SYSCTL_NODE(_vm_pmap, OID_AUTO, pde, CTLFLAG_RD, 0, 706 "2/4MB page mapping counters"); 707 708static u_long pmap_pde_demotions; 709SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, demotions, CTLFLAG_RD, 710 &pmap_pde_demotions, 0, "2/4MB page demotions"); 711 712static u_long pmap_pde_mappings; 713SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, mappings, CTLFLAG_RD, 714 &pmap_pde_mappings, 0, "2/4MB page mappings"); 715 716static u_long pmap_pde_p_failures; 717SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, p_failures, CTLFLAG_RD, 718 &pmap_pde_p_failures, 0, "2/4MB page promotion failures"); 719 720static u_long pmap_pde_promotions; 721SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, promotions, CTLFLAG_RD, 722 &pmap_pde_promotions, 0, "2/4MB page promotions"); 723 724/*************************************************** 725 * Low level helper routines..... 726 ***************************************************/ 727 728/* 729 * Determine the appropriate bits to set in a PTE or PDE for a specified 730 * caching mode. 731 */ 732static int 733pmap_cache_bits(int mode, boolean_t is_pde) 734{ 735 int pat_flag, pat_index, cache_bits; 736 737 /* The PAT bit is different for PTE's and PDE's. */ 738 pat_flag = is_pde ? PG_PDE_PAT : PG_PTE_PAT; 739 740 /* If we don't support PAT, map extended modes to older ones. */ 741 if (!(cpu_feature & CPUID_PAT)) { 742 switch (mode) { 743 case PAT_UNCACHEABLE: 744 case PAT_WRITE_THROUGH: 745 case PAT_WRITE_BACK: 746 break; 747 case PAT_UNCACHED: 748 case PAT_WRITE_COMBINING: 749 case PAT_WRITE_PROTECTED: 750 mode = PAT_UNCACHEABLE; 751 break; 752 } 753 } 754 755 /* Map the caching mode to a PAT index. */ 756 switch (mode) { 757#ifdef PAT_WORKS 758 case PAT_UNCACHEABLE: 759 pat_index = 3; 760 break; 761 case PAT_WRITE_THROUGH: 762 pat_index = 1; 763 break; 764 case PAT_WRITE_BACK: 765 pat_index = 0; 766 break; 767 case PAT_UNCACHED: 768 pat_index = 2; 769 break; 770 case PAT_WRITE_COMBINING: 771 pat_index = 5; 772 break; 773 case PAT_WRITE_PROTECTED: 774 pat_index = 4; 775 break; 776#else 777 case PAT_UNCACHED: 778 case PAT_UNCACHEABLE: 779 case PAT_WRITE_PROTECTED: 780 pat_index = 3; 781 break; 782 case PAT_WRITE_THROUGH: 783 pat_index = 1; 784 break; 785 case PAT_WRITE_BACK: 786 pat_index = 0; 787 break; 788 case PAT_WRITE_COMBINING: 789 pat_index = 2; 790 break; 791#endif 792 default: 793 panic("Unknown caching mode %d\n", mode); 794 } 795 796 /* Map the 3-bit index value into the PAT, PCD, and PWT bits. */ 797 cache_bits = 0; 798 if (pat_index & 0x4) 799 cache_bits |= pat_flag; 800 if (pat_index & 0x2) 801 cache_bits |= PG_NC_PCD; 802 if (pat_index & 0x1) 803 cache_bits |= PG_NC_PWT; 804 return (cache_bits); 805} 806#ifdef SMP 807/* 808 * For SMP, these functions have to use the IPI mechanism for coherence. 809 * 810 * N.B.: Before calling any of the following TLB invalidation functions, 811 * the calling processor must ensure that all stores updating a non- 812 * kernel page table are globally performed. Otherwise, another 813 * processor could cache an old, pre-update entry without being 814 * invalidated. This can happen one of two ways: (1) The pmap becomes 815 * active on another processor after its pm_active field is checked by 816 * one of the following functions but before a store updating the page 817 * table is globally performed. (2) The pmap becomes active on another 818 * processor before its pm_active field is checked but due to 819 * speculative loads one of the following functions stills reads the 820 * pmap as inactive on the other processor. 821 * 822 * The kernel page table is exempt because its pm_active field is 823 * immutable. The kernel page table is always active on every 824 * processor. 825 */ 826void 827pmap_invalidate_page(pmap_t pmap, vm_offset_t va) 828{ 829 u_int cpumask; 830 u_int other_cpus; 831 832 sched_pin(); 833 if (pmap == kernel_pmap || pmap->pm_active == all_cpus) { 834 invlpg(va); 835 smp_invlpg(va); 836 } else { 837 cpumask = PCPU_GET(cpumask); 838 other_cpus = PCPU_GET(other_cpus); 839 if (pmap->pm_active & cpumask) 840 invlpg(va); 841 if (pmap->pm_active & other_cpus) 842 smp_masked_invlpg(pmap->pm_active & other_cpus, va); 843 } 844 sched_unpin(); 845} 846 847void 848pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 849{ 850 u_int cpumask; 851 u_int other_cpus; 852 vm_offset_t addr; 853 854 sched_pin(); 855 if (pmap == kernel_pmap || pmap->pm_active == all_cpus) { 856 for (addr = sva; addr < eva; addr += PAGE_SIZE) 857 invlpg(addr); 858 smp_invlpg_range(sva, eva); 859 } else { 860 cpumask = PCPU_GET(cpumask); 861 other_cpus = PCPU_GET(other_cpus); 862 if (pmap->pm_active & cpumask) 863 for (addr = sva; addr < eva; addr += PAGE_SIZE) 864 invlpg(addr); 865 if (pmap->pm_active & other_cpus) 866 smp_masked_invlpg_range(pmap->pm_active & other_cpus, 867 sva, eva); 868 } 869 sched_unpin(); 870} 871 872void 873pmap_invalidate_all(pmap_t pmap) 874{ 875 u_int cpumask; 876 u_int other_cpus; 877 878 sched_pin(); 879 if (pmap == kernel_pmap || pmap->pm_active == all_cpus) { 880 invltlb(); 881 smp_invltlb(); 882 } else { 883 cpumask = PCPU_GET(cpumask); 884 other_cpus = PCPU_GET(other_cpus); 885 if (pmap->pm_active & cpumask) 886 invltlb(); 887 if (pmap->pm_active & other_cpus) 888 smp_masked_invltlb(pmap->pm_active & other_cpus); 889 } 890 sched_unpin(); 891} 892 893void 894pmap_invalidate_cache(void) 895{ 896 897 sched_pin(); 898 wbinvd(); 899 smp_cache_flush(); 900 sched_unpin(); 901} 902#else /* !SMP */ 903/* 904 * Normal, non-SMP, 486+ invalidation functions. 905 * We inline these within pmap.c for speed. 906 */ 907PMAP_INLINE void 908pmap_invalidate_page(pmap_t pmap, vm_offset_t va) 909{ 910 911 if (pmap == kernel_pmap || pmap->pm_active) 912 invlpg(va); 913} 914 915PMAP_INLINE void 916pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 917{ 918 vm_offset_t addr; 919 920 if (pmap == kernel_pmap || pmap->pm_active) 921 for (addr = sva; addr < eva; addr += PAGE_SIZE) 922 invlpg(addr); 923} 924 925PMAP_INLINE void 926pmap_invalidate_all(pmap_t pmap) 927{ 928 929 if (pmap == kernel_pmap || pmap->pm_active) 930 invltlb(); 931} 932 933PMAP_INLINE void 934pmap_invalidate_cache(void) 935{ 936 937 wbinvd(); 938} 939#endif /* !SMP */ 940 941/* 942 * Are we current address space or kernel? N.B. We return FALSE when 943 * a pmap's page table is in use because a kernel thread is borrowing 944 * it. The borrowed page table can change spontaneously, making any 945 * dependence on its continued use subject to a race condition. 946 */ 947static __inline int 948pmap_is_current(pmap_t pmap) 949{ 950 951 return (pmap == kernel_pmap || 952 (pmap == vmspace_pmap(curthread->td_proc->p_vmspace) && 953 (pmap->pm_pdir[PTDPTDI] & PG_FRAME) == (PTDpde[0] & PG_FRAME))); 954} 955 956/* 957 * If the given pmap is not the current or kernel pmap, the returned pte must 958 * be released by passing it to pmap_pte_release(). 959 */ 960pt_entry_t * 961pmap_pte(pmap_t pmap, vm_offset_t va) 962{ 963 pd_entry_t newpf; 964 pd_entry_t *pde; 965 966 pde = pmap_pde(pmap, va); 967 if (*pde & PG_PS) 968 return (pde); 969 if (*pde != 0) { 970 /* are we current address space or kernel? */ 971 if (pmap_is_current(pmap)) 972 return (vtopte(va)); 973 mtx_lock(&PMAP2mutex); 974 newpf = *pde & PG_FRAME; 975 if ((*PMAP2 & PG_FRAME) != newpf) { 976 *PMAP2 = newpf | PG_RW | PG_V | PG_A | PG_M; 977 pmap_invalidate_page(kernel_pmap, (vm_offset_t)PADDR2); 978 } 979 return (PADDR2 + (i386_btop(va) & (NPTEPG - 1))); 980 } 981 return (0); 982} 983 984/* 985 * Releases a pte that was obtained from pmap_pte(). Be prepared for the pte 986 * being NULL. 987 */ 988static __inline void 989pmap_pte_release(pt_entry_t *pte) 990{ 991 992 if ((pt_entry_t *)((vm_offset_t)pte & ~PAGE_MASK) == PADDR2) 993 mtx_unlock(&PMAP2mutex); 994} 995 996static __inline void 997invlcaddr(void *caddr) 998{ 999 1000 invlpg((u_int)caddr); 1001} 1002 1003/* 1004 * Super fast pmap_pte routine best used when scanning 1005 * the pv lists. This eliminates many coarse-grained 1006 * invltlb calls. Note that many of the pv list 1007 * scans are across different pmaps. It is very wasteful 1008 * to do an entire invltlb for checking a single mapping. 1009 * 1010 * If the given pmap is not the current pmap, vm_page_queue_mtx 1011 * must be held and curthread pinned to a CPU. 1012 */ 1013static pt_entry_t * 1014pmap_pte_quick(pmap_t pmap, vm_offset_t va) 1015{ 1016 pd_entry_t newpf; 1017 pd_entry_t *pde; 1018 1019 pde = pmap_pde(pmap, va); 1020 if (*pde & PG_PS) 1021 return (pde); 1022 if (*pde != 0) { 1023 /* are we current address space or kernel? */ 1024 if (pmap_is_current(pmap)) 1025 return (vtopte(va)); 1026 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1027 KASSERT(curthread->td_pinned > 0, ("curthread not pinned")); 1028 newpf = *pde & PG_FRAME; 1029 if ((*PMAP1 & PG_FRAME) != newpf) { 1030 *PMAP1 = newpf | PG_RW | PG_V | PG_A | PG_M; 1031#ifdef SMP 1032 PMAP1cpu = PCPU_GET(cpuid); 1033#endif 1034 invlcaddr(PADDR1); 1035 PMAP1changed++; 1036 } else 1037#ifdef SMP 1038 if (PMAP1cpu != PCPU_GET(cpuid)) { 1039 PMAP1cpu = PCPU_GET(cpuid); 1040 invlcaddr(PADDR1); 1041 PMAP1changedcpu++; 1042 } else 1043#endif 1044 PMAP1unchanged++; 1045 return (PADDR1 + (i386_btop(va) & (NPTEPG - 1))); 1046 } 1047 return (0); 1048} 1049 1050/* 1051 * Routine: pmap_extract 1052 * Function: 1053 * Extract the physical page address associated 1054 * with the given map/virtual_address pair. 1055 */ 1056vm_paddr_t 1057pmap_extract(pmap_t pmap, vm_offset_t va) 1058{ 1059 vm_paddr_t rtval; 1060 pt_entry_t *pte; 1061 pd_entry_t pde; 1062 1063 rtval = 0; 1064 PMAP_LOCK(pmap); 1065 pde = pmap->pm_pdir[va >> PDRSHIFT]; 1066 if (pde != 0) { 1067 if ((pde & PG_PS) != 0) 1068 rtval = (pde & PG_PS_FRAME) | (va & PDRMASK); 1069 else { 1070 pte = pmap_pte(pmap, va); 1071 rtval = (*pte & PG_FRAME) | (va & PAGE_MASK); 1072 pmap_pte_release(pte); 1073 } 1074 } 1075 PMAP_UNLOCK(pmap); 1076 return (rtval); 1077} 1078 1079/* 1080 * Routine: pmap_extract_and_hold 1081 * Function: 1082 * Atomically extract and hold the physical page 1083 * with the given pmap and virtual address pair 1084 * if that mapping permits the given protection. 1085 */ 1086vm_page_t 1087pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot) 1088{ 1089 pd_entry_t pde; 1090 pt_entry_t pte; 1091 vm_page_t m; 1092 1093 m = NULL; 1094 vm_page_lock_queues(); 1095 PMAP_LOCK(pmap); 1096 pde = *pmap_pde(pmap, va); 1097 if (pde != 0) { 1098 if (pde & PG_PS) { 1099 if ((pde & PG_RW) || (prot & VM_PROT_WRITE) == 0) { 1100 m = PHYS_TO_VM_PAGE((pde & PG_PS_FRAME) | 1101 (va & PDRMASK)); 1102 vm_page_hold(m); 1103 } 1104 } else { 1105 sched_pin(); 1106 pte = *pmap_pte_quick(pmap, va); 1107 if (pte != 0 && 1108 ((pte & PG_RW) || (prot & VM_PROT_WRITE) == 0)) { 1109 m = PHYS_TO_VM_PAGE(pte & PG_FRAME); 1110 vm_page_hold(m); 1111 } 1112 sched_unpin(); 1113 } 1114 } 1115 vm_page_unlock_queues(); 1116 PMAP_UNLOCK(pmap); 1117 return (m); 1118} 1119 1120/*************************************************** 1121 * Low level mapping routines..... 1122 ***************************************************/ 1123 1124/* 1125 * Add a wired page to the kva. 1126 * Note: not SMP coherent. 1127 */ 1128PMAP_INLINE void 1129pmap_kenter(vm_offset_t va, vm_paddr_t pa) 1130{ 1131 pt_entry_t *pte; 1132 1133 pte = vtopte(va); 1134 pte_store(pte, pa | PG_RW | PG_V | pgeflag); 1135} 1136 1137static __inline void 1138pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode) 1139{ 1140 pt_entry_t *pte; 1141 1142 pte = vtopte(va); 1143 pte_store(pte, pa | PG_RW | PG_V | pgeflag | pmap_cache_bits(mode, 0)); 1144} 1145 1146/* 1147 * Remove a page from the kernel pagetables. 1148 * Note: not SMP coherent. 1149 */ 1150PMAP_INLINE void 1151pmap_kremove(vm_offset_t va) 1152{ 1153 pt_entry_t *pte; 1154 1155 pte = vtopte(va); 1156 pte_clear(pte); 1157} 1158 1159/* 1160 * Used to map a range of physical addresses into kernel 1161 * virtual address space. 1162 * 1163 * The value passed in '*virt' is a suggested virtual address for 1164 * the mapping. Architectures which can support a direct-mapped 1165 * physical to virtual region can return the appropriate address 1166 * within that region, leaving '*virt' unchanged. Other 1167 * architectures should map the pages starting at '*virt' and 1168 * update '*virt' with the first usable address after the mapped 1169 * region. 1170 */ 1171vm_offset_t 1172pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot) 1173{ 1174 vm_offset_t va, sva; 1175 1176 va = sva = *virt; 1177 while (start < end) { 1178 pmap_kenter(va, start); 1179 va += PAGE_SIZE; 1180 start += PAGE_SIZE; 1181 } 1182 pmap_invalidate_range(kernel_pmap, sva, va); 1183 *virt = va; 1184 return (sva); 1185} 1186 1187 1188/* 1189 * Add a list of wired pages to the kva 1190 * this routine is only used for temporary 1191 * kernel mappings that do not need to have 1192 * page modification or references recorded. 1193 * Note that old mappings are simply written 1194 * over. The page *must* be wired. 1195 * Note: SMP coherent. Uses a ranged shootdown IPI. 1196 */ 1197void 1198pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count) 1199{ 1200 pt_entry_t *endpte, oldpte, *pte; 1201 1202 oldpte = 0; 1203 pte = vtopte(sva); 1204 endpte = pte + count; 1205 while (pte < endpte) { 1206 oldpte |= *pte; 1207 pte_store(pte, VM_PAGE_TO_PHYS(*ma) | pgeflag | PG_RW | PG_V); 1208 pte++; 1209 ma++; 1210 } 1211 if ((oldpte & PG_V) != 0) 1212 pmap_invalidate_range(kernel_pmap, sva, sva + count * 1213 PAGE_SIZE); 1214} 1215 1216/* 1217 * This routine tears out page mappings from the 1218 * kernel -- it is meant only for temporary mappings. 1219 * Note: SMP coherent. Uses a ranged shootdown IPI. 1220 */ 1221void 1222pmap_qremove(vm_offset_t sva, int count) 1223{ 1224 vm_offset_t va; 1225 1226 va = sva; 1227 while (count-- > 0) { 1228 pmap_kremove(va); 1229 va += PAGE_SIZE; 1230 } 1231 pmap_invalidate_range(kernel_pmap, sva, va); 1232} 1233 1234/*************************************************** 1235 * Page table page management routines..... 1236 ***************************************************/ 1237static __inline void 1238pmap_free_zero_pages(vm_page_t free) 1239{ 1240 vm_page_t m; 1241 1242 while (free != NULL) { 1243 m = free; 1244 free = m->right; 1245 /* Preserve the page's PG_ZERO setting. */ 1246 vm_page_free_toq(m); 1247 } 1248} 1249 1250/* 1251 * Schedule the specified unused page table page to be freed. Specifically, 1252 * add the page to the specified list of pages that will be released to the 1253 * physical memory manager after the TLB has been updated. 1254 */ 1255static __inline void 1256pmap_add_delayed_free_list(vm_page_t m, vm_page_t *free, boolean_t set_PG_ZERO) 1257{ 1258 1259 if (set_PG_ZERO) 1260 m->flags |= PG_ZERO; 1261 else 1262 m->flags &= ~PG_ZERO; 1263 m->right = *free; 1264 *free = m; 1265} 1266 1267/* 1268 * Inserts the specified page table page into the specified pmap's collection 1269 * of idle page table pages. Each of a pmap's page table pages is responsible 1270 * for mapping a distinct range of virtual addresses. The pmap's collection is 1271 * ordered by this virtual address range. 1272 */ 1273static void 1274pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte) 1275{ 1276 vm_page_t root; 1277 1278 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1279 root = pmap->pm_root; 1280 if (root == NULL) { 1281 mpte->left = NULL; 1282 mpte->right = NULL; 1283 } else { 1284 root = vm_page_splay(mpte->pindex, root); 1285 if (mpte->pindex < root->pindex) { 1286 mpte->left = root->left; 1287 mpte->right = root; 1288 root->left = NULL; 1289 } else if (mpte->pindex == root->pindex) 1290 panic("pmap_insert_pt_page: pindex already inserted"); 1291 else { 1292 mpte->right = root->right; 1293 mpte->left = root; 1294 root->right = NULL; 1295 } 1296 } 1297 pmap->pm_root = mpte; 1298} 1299 1300/* 1301 * Looks for a page table page mapping the specified virtual address in the 1302 * specified pmap's collection of idle page table pages. Returns NULL if there 1303 * is no page table page corresponding to the specified virtual address. 1304 */ 1305static vm_page_t 1306pmap_lookup_pt_page(pmap_t pmap, vm_offset_t va) 1307{ 1308 vm_page_t mpte; 1309 vm_pindex_t pindex = va >> PDRSHIFT; 1310 1311 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1312 if ((mpte = pmap->pm_root) != NULL && mpte->pindex != pindex) { 1313 mpte = vm_page_splay(pindex, mpte); 1314 if ((pmap->pm_root = mpte)->pindex != pindex) 1315 mpte = NULL; 1316 } 1317 return (mpte); 1318} 1319 1320/* 1321 * Removes the specified page table page from the specified pmap's collection 1322 * of idle page table pages. The specified page table page must be a member of 1323 * the pmap's collection. 1324 */ 1325static void 1326pmap_remove_pt_page(pmap_t pmap, vm_page_t mpte) 1327{ 1328 vm_page_t root; 1329 1330 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1331 if (mpte != pmap->pm_root) 1332 vm_page_splay(mpte->pindex, pmap->pm_root); 1333 if (mpte->left == NULL) 1334 root = mpte->right; 1335 else { 1336 root = vm_page_splay(mpte->pindex, mpte->left); 1337 root->right = mpte->right; 1338 } 1339 pmap->pm_root = root; 1340} 1341 1342/* 1343 * This routine unholds page table pages, and if the hold count 1344 * drops to zero, then it decrements the wire count. 1345 */ 1346static __inline int 1347pmap_unwire_pte_hold(pmap_t pmap, vm_page_t m, vm_page_t *free) 1348{ 1349 1350 --m->wire_count; 1351 if (m->wire_count == 0) 1352 return _pmap_unwire_pte_hold(pmap, m, free); 1353 else 1354 return 0; 1355} 1356 1357static int 1358_pmap_unwire_pte_hold(pmap_t pmap, vm_page_t m, vm_page_t *free) 1359{ 1360 vm_offset_t pteva; 1361 1362 /* 1363 * unmap the page table page 1364 */ 1365 pmap->pm_pdir[m->pindex] = 0; 1366 --pmap->pm_stats.resident_count; 1367 1368 /* 1369 * This is a release store so that the ordinary store unmapping 1370 * the page table page is globally performed before TLB shoot- 1371 * down is begun. 1372 */ 1373 atomic_subtract_rel_int(&cnt.v_wire_count, 1); 1374 1375 /* 1376 * Do an invltlb to make the invalidated mapping 1377 * take effect immediately. 1378 */ 1379 pteva = VM_MAXUSER_ADDRESS + i386_ptob(m->pindex); 1380 pmap_invalidate_page(pmap, pteva); 1381 1382 /* 1383 * Put page on a list so that it is released after 1384 * *ALL* TLB shootdown is done 1385 */ 1386 pmap_add_delayed_free_list(m, free, TRUE); 1387 1388 return 1; 1389} 1390 1391/* 1392 * After removing a page table entry, this routine is used to 1393 * conditionally free the page, and manage the hold/wire counts. 1394 */ 1395static int 1396pmap_unuse_pt(pmap_t pmap, vm_offset_t va, vm_page_t *free) 1397{ 1398 pd_entry_t ptepde; 1399 vm_page_t mpte; 1400 1401 if (va >= VM_MAXUSER_ADDRESS) 1402 return 0; 1403 ptepde = *pmap_pde(pmap, va); 1404 mpte = PHYS_TO_VM_PAGE(ptepde & PG_FRAME); 1405 return pmap_unwire_pte_hold(pmap, mpte, free); 1406} 1407 1408void 1409pmap_pinit0(pmap_t pmap) 1410{ 1411 1412 PMAP_LOCK_INIT(pmap); 1413 pmap->pm_pdir = (pd_entry_t *)(KERNBASE + (vm_offset_t)IdlePTD); 1414#ifdef PAE 1415 pmap->pm_pdpt = (pdpt_entry_t *)(KERNBASE + (vm_offset_t)IdlePDPT); 1416#endif 1417 pmap->pm_root = NULL; 1418 pmap->pm_active = 0; 1419 PCPU_SET(curpmap, pmap); 1420 TAILQ_INIT(&pmap->pm_pvchunk); 1421 bzero(&pmap->pm_stats, sizeof pmap->pm_stats); 1422 mtx_lock_spin(&allpmaps_lock); 1423 LIST_INSERT_HEAD(&allpmaps, pmap, pm_list); 1424 mtx_unlock_spin(&allpmaps_lock); 1425} 1426 1427/* 1428 * Initialize a preallocated and zeroed pmap structure, 1429 * such as one in a vmspace structure. 1430 */ 1431int 1432pmap_pinit(pmap_t pmap) 1433{ 1434 vm_page_t m, ptdpg[NPGPTD]; 1435 vm_paddr_t pa; 1436 static int color; 1437 int i; 1438 1439 PMAP_LOCK_INIT(pmap); 1440 1441 /* 1442 * No need to allocate page table space yet but we do need a valid 1443 * page directory table. 1444 */ 1445 if (pmap->pm_pdir == NULL) { 1446 pmap->pm_pdir = (pd_entry_t *)kmem_alloc_nofault(kernel_map, 1447 NBPTD); 1448 1449 if (pmap->pm_pdir == NULL) { 1450 PMAP_LOCK_DESTROY(pmap); 1451 return (0); 1452 } 1453#ifdef PAE 1454 pmap->pm_pdpt = uma_zalloc(pdptzone, M_WAITOK | M_ZERO); 1455 KASSERT(((vm_offset_t)pmap->pm_pdpt & 1456 ((NPGPTD * sizeof(pdpt_entry_t)) - 1)) == 0, 1457 ("pmap_pinit: pdpt misaligned")); 1458 KASSERT(pmap_kextract((vm_offset_t)pmap->pm_pdpt) < (4ULL<<30), 1459 ("pmap_pinit: pdpt above 4g")); 1460#endif 1461 pmap->pm_root = NULL; 1462 } 1463 KASSERT(pmap->pm_root == NULL, 1464 ("pmap_pinit: pmap has reserved page table page(s)")); 1465 1466 /* 1467 * allocate the page directory page(s) 1468 */ 1469 for (i = 0; i < NPGPTD;) { 1470 m = vm_page_alloc(NULL, color++, 1471 VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | 1472 VM_ALLOC_ZERO); 1473 if (m == NULL) 1474 VM_WAIT; 1475 else { 1476 ptdpg[i++] = m; 1477 } 1478 } 1479 1480 pmap_qenter((vm_offset_t)pmap->pm_pdir, ptdpg, NPGPTD); 1481 1482 for (i = 0; i < NPGPTD; i++) { 1483 if ((ptdpg[i]->flags & PG_ZERO) == 0) 1484 bzero(pmap->pm_pdir + (i * NPDEPG), PAGE_SIZE); 1485 } 1486 1487 mtx_lock_spin(&allpmaps_lock); 1488 LIST_INSERT_HEAD(&allpmaps, pmap, pm_list); 1489 mtx_unlock_spin(&allpmaps_lock); 1490 /* Wire in kernel global address entries. */ 1491 bcopy(PTD + KPTDI, pmap->pm_pdir + KPTDI, nkpt * sizeof(pd_entry_t)); 1492 1493 /* install self-referential address mapping entry(s) */ 1494 for (i = 0; i < NPGPTD; i++) { 1495 pa = VM_PAGE_TO_PHYS(ptdpg[i]); 1496 pmap->pm_pdir[PTDPTDI + i] = pa | PG_V | PG_RW | PG_A | PG_M; 1497#ifdef PAE 1498 pmap->pm_pdpt[i] = pa | PG_V; 1499#endif 1500 } 1501 1502 pmap->pm_active = 0; 1503 TAILQ_INIT(&pmap->pm_pvchunk); 1504 bzero(&pmap->pm_stats, sizeof pmap->pm_stats); 1505 1506 return (1); 1507} 1508 1509/* 1510 * this routine is called if the page table page is not 1511 * mapped correctly. 1512 */ 1513static vm_page_t 1514_pmap_allocpte(pmap_t pmap, unsigned ptepindex, int flags) 1515{ 1516 vm_paddr_t ptepa; 1517 vm_page_t m; 1518 1519 KASSERT((flags & (M_NOWAIT | M_WAITOK)) == M_NOWAIT || 1520 (flags & (M_NOWAIT | M_WAITOK)) == M_WAITOK, 1521 ("_pmap_allocpte: flags is neither M_NOWAIT nor M_WAITOK")); 1522 1523 /* 1524 * Allocate a page table page. 1525 */ 1526 if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ | 1527 VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) { 1528 if (flags & M_WAITOK) { 1529 PMAP_UNLOCK(pmap); 1530 vm_page_unlock_queues(); 1531 VM_WAIT; 1532 vm_page_lock_queues(); 1533 PMAP_LOCK(pmap); 1534 } 1535 1536 /* 1537 * Indicate the need to retry. While waiting, the page table 1538 * page may have been allocated. 1539 */ 1540 return (NULL); 1541 } 1542 if ((m->flags & PG_ZERO) == 0) 1543 pmap_zero_page(m); 1544 1545 /* 1546 * Map the pagetable page into the process address space, if 1547 * it isn't already there. 1548 */ 1549 1550 pmap->pm_stats.resident_count++; 1551 1552 ptepa = VM_PAGE_TO_PHYS(m); 1553 pmap->pm_pdir[ptepindex] = 1554 (pd_entry_t) (ptepa | PG_U | PG_RW | PG_V | PG_A | PG_M); 1555 1556 return m; 1557} 1558 1559static vm_page_t 1560pmap_allocpte(pmap_t pmap, vm_offset_t va, int flags) 1561{ 1562 unsigned ptepindex; 1563 pd_entry_t ptepa; 1564 vm_page_t m; 1565 1566 KASSERT((flags & (M_NOWAIT | M_WAITOK)) == M_NOWAIT || 1567 (flags & (M_NOWAIT | M_WAITOK)) == M_WAITOK, 1568 ("pmap_allocpte: flags is neither M_NOWAIT nor M_WAITOK")); 1569 1570 /* 1571 * Calculate pagetable page index 1572 */ 1573 ptepindex = va >> PDRSHIFT; 1574retry: 1575 /* 1576 * Get the page directory entry 1577 */ 1578 ptepa = pmap->pm_pdir[ptepindex]; 1579 1580 /* 1581 * This supports switching from a 4MB page to a 1582 * normal 4K page. 1583 */ 1584 if (ptepa & PG_PS) { 1585 (void)pmap_demote_pde(pmap, &pmap->pm_pdir[ptepindex], va); 1586 ptepa = pmap->pm_pdir[ptepindex]; 1587 } 1588 1589 /* 1590 * If the page table page is mapped, we just increment the 1591 * hold count, and activate it. 1592 */ 1593 if (ptepa) { 1594 m = PHYS_TO_VM_PAGE(ptepa & PG_FRAME); 1595 m->wire_count++; 1596 } else { 1597 /* 1598 * Here if the pte page isn't mapped, or if it has 1599 * been deallocated. 1600 */ 1601 m = _pmap_allocpte(pmap, ptepindex, flags); 1602 if (m == NULL && (flags & M_WAITOK)) 1603 goto retry; 1604 } 1605 return (m); 1606} 1607 1608 1609/*************************************************** 1610* Pmap allocation/deallocation routines. 1611 ***************************************************/ 1612 1613#ifdef SMP 1614/* 1615 * Deal with a SMP shootdown of other users of the pmap that we are 1616 * trying to dispose of. This can be a bit hairy. 1617 */ 1618static u_int *lazymask; 1619static u_int lazyptd; 1620static volatile u_int lazywait; 1621 1622void pmap_lazyfix_action(void); 1623 1624void 1625pmap_lazyfix_action(void) 1626{ 1627 u_int mymask = PCPU_GET(cpumask); 1628 1629#ifdef COUNT_IPIS 1630 (*ipi_lazypmap_counts[PCPU_GET(cpuid)])++; 1631#endif 1632 if (rcr3() == lazyptd) 1633 load_cr3(PCPU_GET(curpcb)->pcb_cr3); 1634 atomic_clear_int(lazymask, mymask); 1635 atomic_store_rel_int(&lazywait, 1); 1636} 1637 1638static void 1639pmap_lazyfix_self(u_int mymask) 1640{ 1641 1642 if (rcr3() == lazyptd) 1643 load_cr3(PCPU_GET(curpcb)->pcb_cr3); 1644 atomic_clear_int(lazymask, mymask); 1645} 1646 1647 1648static void 1649pmap_lazyfix(pmap_t pmap) 1650{ 1651 u_int mymask; 1652 u_int mask; 1653 u_int spins; 1654 1655 while ((mask = pmap->pm_active) != 0) { 1656 spins = 50000000; 1657 mask = mask & -mask; /* Find least significant set bit */ 1658 mtx_lock_spin(&smp_ipi_mtx); 1659#ifdef PAE 1660 lazyptd = vtophys(pmap->pm_pdpt); 1661#else 1662 lazyptd = vtophys(pmap->pm_pdir); 1663#endif 1664 mymask = PCPU_GET(cpumask); 1665 if (mask == mymask) { 1666 lazymask = &pmap->pm_active; 1667 pmap_lazyfix_self(mymask); 1668 } else { 1669 atomic_store_rel_int((u_int *)&lazymask, 1670 (u_int)&pmap->pm_active); 1671 atomic_store_rel_int(&lazywait, 0); 1672 ipi_selected(mask, IPI_LAZYPMAP); 1673 while (lazywait == 0) { 1674 ia32_pause(); 1675 if (--spins == 0) 1676 break; 1677 } 1678 } 1679 mtx_unlock_spin(&smp_ipi_mtx); 1680 if (spins == 0) 1681 printf("pmap_lazyfix: spun for 50000000\n"); 1682 } 1683} 1684 1685#else /* SMP */ 1686 1687/* 1688 * Cleaning up on uniprocessor is easy. For various reasons, we're 1689 * unlikely to have to even execute this code, including the fact 1690 * that the cleanup is deferred until the parent does a wait(2), which 1691 * means that another userland process has run. 1692 */ 1693static void 1694pmap_lazyfix(pmap_t pmap) 1695{ 1696 u_int cr3; 1697 1698 cr3 = vtophys(pmap->pm_pdir); 1699 if (cr3 == rcr3()) { 1700 load_cr3(PCPU_GET(curpcb)->pcb_cr3); 1701 pmap->pm_active &= ~(PCPU_GET(cpumask)); 1702 } 1703} 1704#endif /* SMP */ 1705 1706/* 1707 * Release any resources held by the given physical map. 1708 * Called when a pmap initialized by pmap_pinit is being released. 1709 * Should only be called if the map contains no valid mappings. 1710 */ 1711void 1712pmap_release(pmap_t pmap) 1713{ 1714 vm_page_t m, ptdpg[NPGPTD]; 1715 int i; 1716 1717 KASSERT(pmap->pm_stats.resident_count == 0, 1718 ("pmap_release: pmap resident count %ld != 0", 1719 pmap->pm_stats.resident_count)); 1720 KASSERT(pmap->pm_root == NULL, 1721 ("pmap_release: pmap has reserved page table page(s)")); 1722 1723 pmap_lazyfix(pmap); 1724 mtx_lock_spin(&allpmaps_lock); 1725 LIST_REMOVE(pmap, pm_list); 1726 mtx_unlock_spin(&allpmaps_lock); 1727 1728 for (i = 0; i < NPGPTD; i++) 1729 ptdpg[i] = PHYS_TO_VM_PAGE(pmap->pm_pdir[PTDPTDI + i] & 1730 PG_FRAME); 1731 1732 bzero(pmap->pm_pdir + PTDPTDI, (nkpt + NPGPTD) * 1733 sizeof(*pmap->pm_pdir)); 1734 1735 pmap_qremove((vm_offset_t)pmap->pm_pdir, NPGPTD); 1736 1737 for (i = 0; i < NPGPTD; i++) { 1738 m = ptdpg[i]; 1739#ifdef PAE 1740 KASSERT(VM_PAGE_TO_PHYS(m) == (pmap->pm_pdpt[i] & PG_FRAME), 1741 ("pmap_release: got wrong ptd page")); 1742#endif 1743 m->wire_count--; 1744 atomic_subtract_int(&cnt.v_wire_count, 1); 1745 vm_page_free_zero(m); 1746 } 1747 PMAP_LOCK_DESTROY(pmap); 1748} 1749 1750static int 1751kvm_size(SYSCTL_HANDLER_ARGS) 1752{ 1753 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - KERNBASE; 1754 1755 return sysctl_handle_long(oidp, &ksize, 0, req); 1756} 1757SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG|CTLFLAG_RD, 1758 0, 0, kvm_size, "IU", "Size of KVM"); 1759 1760static int 1761kvm_free(SYSCTL_HANDLER_ARGS) 1762{ 1763 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end; 1764 1765 return sysctl_handle_long(oidp, &kfree, 0, req); 1766} 1767SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG|CTLFLAG_RD, 1768 0, 0, kvm_free, "IU", "Amount of KVM free"); 1769 1770/* 1771 * grow the number of kernel page table entries, if needed 1772 */ 1773void 1774pmap_growkernel(vm_offset_t addr) 1775{ 1776 struct pmap *pmap; 1777 vm_paddr_t ptppaddr; 1778 vm_page_t nkpg; 1779 pd_entry_t newpdir; 1780 pt_entry_t *pde; 1781 1782 mtx_assert(&kernel_map->system_mtx, MA_OWNED); 1783 if (kernel_vm_end == 0) { 1784 kernel_vm_end = KERNBASE; 1785 nkpt = 0; 1786 while (pdir_pde(PTD, kernel_vm_end)) { 1787 kernel_vm_end = (kernel_vm_end + PAGE_SIZE * NPTEPG) & ~(PAGE_SIZE * NPTEPG - 1); 1788 nkpt++; 1789 if (kernel_vm_end - 1 >= kernel_map->max_offset) { 1790 kernel_vm_end = kernel_map->max_offset; 1791 break; 1792 } 1793 } 1794 } 1795 addr = roundup2(addr, PAGE_SIZE * NPTEPG); 1796 if (addr - 1 >= kernel_map->max_offset) 1797 addr = kernel_map->max_offset; 1798 while (kernel_vm_end < addr) { 1799 if (pdir_pde(PTD, kernel_vm_end)) { 1800 kernel_vm_end = (kernel_vm_end + PAGE_SIZE * NPTEPG) & ~(PAGE_SIZE * NPTEPG - 1); 1801 if (kernel_vm_end - 1 >= kernel_map->max_offset) { 1802 kernel_vm_end = kernel_map->max_offset; 1803 break; 1804 } 1805 continue; 1806 } 1807 1808 nkpg = vm_page_alloc(NULL, kernel_vm_end >> PDRSHIFT, 1809 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | 1810 VM_ALLOC_ZERO); 1811 if (nkpg == NULL) 1812 panic("pmap_growkernel: no memory to grow kernel"); 1813 1814 nkpt++; 1815 1816 if ((nkpg->flags & PG_ZERO) == 0) 1817 pmap_zero_page(nkpg); 1818 ptppaddr = VM_PAGE_TO_PHYS(nkpg); 1819 newpdir = (pd_entry_t) (ptppaddr | PG_V | PG_RW | PG_A | PG_M); 1820 pdir_pde(PTD, kernel_vm_end) = newpdir; 1821 1822 mtx_lock_spin(&allpmaps_lock); 1823 LIST_FOREACH(pmap, &allpmaps, pm_list) { 1824 pde = pmap_pde(pmap, kernel_vm_end); 1825 pde_store(pde, newpdir); 1826 } 1827 mtx_unlock_spin(&allpmaps_lock); 1828 kernel_vm_end = (kernel_vm_end + PAGE_SIZE * NPTEPG) & ~(PAGE_SIZE * NPTEPG - 1); 1829 if (kernel_vm_end - 1 >= kernel_map->max_offset) { 1830 kernel_vm_end = kernel_map->max_offset; 1831 break; 1832 } 1833 } 1834} 1835 1836 1837/*************************************************** 1838 * page management routines. 1839 ***************************************************/ 1840 1841CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE); 1842CTASSERT(_NPCM == 11); 1843 1844static __inline struct pv_chunk * 1845pv_to_chunk(pv_entry_t pv) 1846{ 1847 1848 return (struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK); 1849} 1850 1851#define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap) 1852 1853#define PC_FREE0_9 0xfffffffful /* Free values for index 0 through 9 */ 1854#define PC_FREE10 0x0000fffful /* Free values for index 10 */ 1855 1856static uint32_t pc_freemask[11] = { 1857 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9, 1858 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9, 1859 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9, 1860 PC_FREE0_9, PC_FREE10 1861}; 1862 1863SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0, 1864 "Current number of pv entries"); 1865 1866#ifdef PV_STATS 1867static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail; 1868 1869SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0, 1870 "Current number of pv entry chunks"); 1871SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0, 1872 "Current number of pv entry chunks allocated"); 1873SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0, 1874 "Current number of pv entry chunks frees"); 1875SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0, 1876 "Number of times tried to get a chunk page but failed."); 1877 1878static long pv_entry_frees, pv_entry_allocs; 1879static int pv_entry_spare; 1880 1881SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0, 1882 "Current number of pv entry frees"); 1883SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0, 1884 "Current number of pv entry allocs"); 1885SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0, 1886 "Current number of spare pv entries"); 1887 1888static int pmap_collect_inactive, pmap_collect_active; 1889 1890SYSCTL_INT(_vm_pmap, OID_AUTO, pmap_collect_inactive, CTLFLAG_RD, &pmap_collect_inactive, 0, 1891 "Current number times pmap_collect called on inactive queue"); 1892SYSCTL_INT(_vm_pmap, OID_AUTO, pmap_collect_active, CTLFLAG_RD, &pmap_collect_active, 0, 1893 "Current number times pmap_collect called on active queue"); 1894#endif 1895 1896/* 1897 * We are in a serious low memory condition. Resort to 1898 * drastic measures to free some pages so we can allocate 1899 * another pv entry chunk. This is normally called to 1900 * unmap inactive pages, and if necessary, active pages. 1901 */ 1902static void 1903pmap_collect(pmap_t locked_pmap, struct vpgqueues *vpq) 1904{ 1905 struct md_page *pvh; 1906 pd_entry_t *pde; 1907 pmap_t pmap; 1908 pt_entry_t *pte, tpte; 1909 pv_entry_t next_pv, pv; 1910 vm_offset_t va; 1911 vm_page_t m, free; 1912 1913 sched_pin(); 1914 TAILQ_FOREACH(m, &vpq->pl, pageq) { 1915 if (m->hold_count || m->busy) 1916 continue; 1917 TAILQ_FOREACH_SAFE(pv, &m->md.pv_list, pv_list, next_pv) { 1918 va = pv->pv_va; 1919 pmap = PV_PMAP(pv); 1920 /* Avoid deadlock and lock recursion. */ 1921 if (pmap > locked_pmap) 1922 PMAP_LOCK(pmap); 1923 else if (pmap != locked_pmap && !PMAP_TRYLOCK(pmap)) 1924 continue; 1925 pmap->pm_stats.resident_count--; 1926 pde = pmap_pde(pmap, va); 1927 KASSERT((*pde & PG_PS) == 0, ("pmap_collect: found" 1928 " a 4mpage in page %p's pv list", m)); 1929 pte = pmap_pte_quick(pmap, va); 1930 tpte = pte_load_clear(pte); 1931 KASSERT((tpte & PG_W) == 0, 1932 ("pmap_collect: wired pte %#jx", (uintmax_t)tpte)); 1933 if (tpte & PG_A) 1934 vm_page_flag_set(m, PG_REFERENCED); 1935 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) 1936 vm_page_dirty(m); 1937 free = NULL; 1938 pmap_unuse_pt(pmap, va, &free); 1939 pmap_invalidate_page(pmap, va); 1940 pmap_free_zero_pages(free); 1941 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list); 1942 if (TAILQ_EMPTY(&m->md.pv_list)) { 1943 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 1944 if (TAILQ_EMPTY(&pvh->pv_list)) 1945 vm_page_flag_clear(m, PG_WRITEABLE); 1946 } 1947 free_pv_entry(pmap, pv); 1948 if (pmap != locked_pmap) 1949 PMAP_UNLOCK(pmap); 1950 } 1951 } 1952 sched_unpin(); 1953} 1954 1955 1956/* 1957 * free the pv_entry back to the free list 1958 */ 1959static void 1960free_pv_entry(pmap_t pmap, pv_entry_t pv) 1961{ 1962 vm_page_t m; 1963 struct pv_chunk *pc; 1964 int idx, field, bit; 1965 1966 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1967 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1968 PV_STAT(pv_entry_frees++); 1969 PV_STAT(pv_entry_spare++); 1970 pv_entry_count--; 1971 pc = pv_to_chunk(pv); 1972 idx = pv - &pc->pc_pventry[0]; 1973 field = idx / 32; 1974 bit = idx % 32; 1975 pc->pc_map[field] |= 1ul << bit; 1976 /* move to head of list */ 1977 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 1978 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list); 1979 for (idx = 0; idx < _NPCM; idx++) 1980 if (pc->pc_map[idx] != pc_freemask[idx]) 1981 return; 1982 PV_STAT(pv_entry_spare -= _NPCPV); 1983 PV_STAT(pc_chunk_count--); 1984 PV_STAT(pc_chunk_frees++); 1985 /* entire chunk is free, return it */ 1986 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 1987 m = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc)); 1988 pmap_qremove((vm_offset_t)pc, 1); 1989 vm_page_unwire(m, 0); 1990 vm_page_free(m); 1991 pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc); 1992} 1993 1994/* 1995 * get a new pv_entry, allocating a block from the system 1996 * when needed. 1997 */ 1998static pv_entry_t 1999get_pv_entry(pmap_t pmap, int try) 2000{ 2001 static const struct timeval printinterval = { 60, 0 }; 2002 static struct timeval lastprint; 2003 static vm_pindex_t colour; 2004 struct vpgqueues *pq; 2005 int bit, field; 2006 pv_entry_t pv; 2007 struct pv_chunk *pc; 2008 vm_page_t m; 2009 2010 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2011 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2012 PV_STAT(pv_entry_allocs++); 2013 pv_entry_count++; 2014 if (pv_entry_count > pv_entry_high_water) 2015 if (ratecheck(&lastprint, &printinterval)) 2016 printf("Approaching the limit on PV entries, consider " 2017 "increasing either the vm.pmap.shpgperproc or the " 2018 "vm.pmap.pv_entry_max tunable.\n"); 2019 pq = NULL; 2020retry: 2021 pc = TAILQ_FIRST(&pmap->pm_pvchunk); 2022 if (pc != NULL) { 2023 for (field = 0; field < _NPCM; field++) { 2024 if (pc->pc_map[field]) { 2025 bit = bsfl(pc->pc_map[field]); 2026 break; 2027 } 2028 } 2029 if (field < _NPCM) { 2030 pv = &pc->pc_pventry[field * 32 + bit]; 2031 pc->pc_map[field] &= ~(1ul << bit); 2032 /* If this was the last item, move it to tail */ 2033 for (field = 0; field < _NPCM; field++) 2034 if (pc->pc_map[field] != 0) { 2035 PV_STAT(pv_entry_spare--); 2036 return (pv); /* not full, return */ 2037 } 2038 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 2039 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list); 2040 PV_STAT(pv_entry_spare--); 2041 return (pv); 2042 } 2043 } 2044 /* 2045 * Access to the ptelist "pv_vafree" is synchronized by the page 2046 * queues lock. If "pv_vafree" is currently non-empty, it will 2047 * remain non-empty until pmap_ptelist_alloc() completes. 2048 */ 2049 if (pv_vafree == 0 || (m = vm_page_alloc(NULL, colour, (pq == 2050 &vm_page_queues[PQ_ACTIVE] ? VM_ALLOC_SYSTEM : VM_ALLOC_NORMAL) | 2051 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) { 2052 if (try) { 2053 pv_entry_count--; 2054 PV_STAT(pc_chunk_tryfail++); 2055 return (NULL); 2056 } 2057 /* 2058 * Reclaim pv entries: At first, destroy mappings to 2059 * inactive pages. After that, if a pv chunk entry 2060 * is still needed, destroy mappings to active pages. 2061 */ 2062 if (pq == NULL) { 2063 PV_STAT(pmap_collect_inactive++); 2064 pq = &vm_page_queues[PQ_INACTIVE]; 2065 } else if (pq == &vm_page_queues[PQ_INACTIVE]) { 2066 PV_STAT(pmap_collect_active++); 2067 pq = &vm_page_queues[PQ_ACTIVE]; 2068 } else 2069 panic("get_pv_entry: increase vm.pmap.shpgperproc"); 2070 pmap_collect(pmap, pq); 2071 goto retry; 2072 } 2073 PV_STAT(pc_chunk_count++); 2074 PV_STAT(pc_chunk_allocs++); 2075 colour++; 2076 pc = (struct pv_chunk *)pmap_ptelist_alloc(&pv_vafree); 2077 pmap_qenter((vm_offset_t)pc, &m, 1); 2078 pc->pc_pmap = pmap; 2079 pc->pc_map[0] = pc_freemask[0] & ~1ul; /* preallocated bit 0 */ 2080 for (field = 1; field < _NPCM; field++) 2081 pc->pc_map[field] = pc_freemask[field]; 2082 pv = &pc->pc_pventry[0]; 2083 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list); 2084 PV_STAT(pv_entry_spare += _NPCPV - 1); 2085 return (pv); 2086} 2087 2088static __inline pv_entry_t 2089pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va) 2090{ 2091 pv_entry_t pv; 2092 2093 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2094 TAILQ_FOREACH(pv, &pvh->pv_list, pv_list) { 2095 if (pmap == PV_PMAP(pv) && va == pv->pv_va) { 2096 TAILQ_REMOVE(&pvh->pv_list, pv, pv_list); 2097 break; 2098 } 2099 } 2100 return (pv); 2101} 2102 2103static void 2104pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa) 2105{ 2106 struct md_page *pvh; 2107 pv_entry_t pv; 2108 vm_offset_t va_last; 2109 vm_page_t m; 2110 2111 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2112 KASSERT((pa & PDRMASK) == 0, 2113 ("pmap_pv_demote_pde: pa is not 4mpage aligned")); 2114 2115 /* 2116 * Transfer the 4mpage's pv entry for this mapping to the first 2117 * page's pv list. 2118 */ 2119 pvh = pa_to_pvh(pa); 2120 va = trunc_4mpage(va); 2121 pv = pmap_pvh_remove(pvh, pmap, va); 2122 KASSERT(pv != NULL, ("pmap_pv_demote_pde: pv not found")); 2123 m = PHYS_TO_VM_PAGE(pa); 2124 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list); 2125 /* Instantiate the remaining NPTEPG - 1 pv entries. */ 2126 va_last = va + NBPDR - PAGE_SIZE; 2127 do { 2128 m++; 2129 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 2130 ("pmap_pv_demote_pde: page %p is not managed", m)); 2131 va += PAGE_SIZE; 2132 pmap_insert_entry(pmap, va, m); 2133 } while (va < va_last); 2134} 2135 2136static void 2137pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa) 2138{ 2139 struct md_page *pvh; 2140 pv_entry_t pv; 2141 vm_offset_t va_last; 2142 vm_page_t m; 2143 2144 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2145 KASSERT((pa & PDRMASK) == 0, 2146 ("pmap_pv_promote_pde: pa is not 4mpage aligned")); 2147 2148 /* 2149 * Transfer the first page's pv entry for this mapping to the 2150 * 4mpage's pv list. Aside from avoiding the cost of a call 2151 * to get_pv_entry(), a transfer avoids the possibility that 2152 * get_pv_entry() calls pmap_collect() and that pmap_collect() 2153 * removes one of the mappings that is being promoted. 2154 */ 2155 m = PHYS_TO_VM_PAGE(pa); 2156 va = trunc_4mpage(va); 2157 pv = pmap_pvh_remove(&m->md, pmap, va); 2158 KASSERT(pv != NULL, ("pmap_pv_promote_pde: pv not found")); 2159 pvh = pa_to_pvh(pa); 2160 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_list); 2161 /* Free the remaining NPTEPG - 1 pv entries. */ 2162 va_last = va + NBPDR - PAGE_SIZE; 2163 do { 2164 m++; 2165 va += PAGE_SIZE; 2166 pmap_pvh_free(&m->md, pmap, va); 2167 } while (va < va_last); 2168} 2169 2170static void 2171pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va) 2172{ 2173 pv_entry_t pv; 2174 2175 pv = pmap_pvh_remove(pvh, pmap, va); 2176 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found")); 2177 free_pv_entry(pmap, pv); 2178} 2179 2180static void 2181pmap_remove_entry(pmap_t pmap, vm_page_t m, vm_offset_t va) 2182{ 2183 struct md_page *pvh; 2184 2185 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2186 pmap_pvh_free(&m->md, pmap, va); 2187 if (TAILQ_EMPTY(&m->md.pv_list)) { 2188 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 2189 if (TAILQ_EMPTY(&pvh->pv_list)) 2190 vm_page_flag_clear(m, PG_WRITEABLE); 2191 } 2192} 2193 2194/* 2195 * Create a pv entry for page at pa for 2196 * (pmap, va). 2197 */ 2198static void 2199pmap_insert_entry(pmap_t pmap, vm_offset_t va, vm_page_t m) 2200{ 2201 pv_entry_t pv; 2202 2203 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2204 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2205 pv = get_pv_entry(pmap, FALSE); 2206 pv->pv_va = va; 2207 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list); 2208} 2209 2210/* 2211 * Conditionally create a pv entry. 2212 */ 2213static boolean_t 2214pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m) 2215{ 2216 pv_entry_t pv; 2217 2218 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2219 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2220 if (pv_entry_count < pv_entry_high_water && 2221 (pv = get_pv_entry(pmap, TRUE)) != NULL) { 2222 pv->pv_va = va; 2223 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list); 2224 return (TRUE); 2225 } else 2226 return (FALSE); 2227} 2228 2229/* 2230 * Create the pv entries for each of the pages within a superpage. 2231 */ 2232static boolean_t 2233pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa) 2234{ 2235 struct md_page *pvh; 2236 pv_entry_t pv; 2237 2238 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2239 if (pv_entry_count < pv_entry_high_water && 2240 (pv = get_pv_entry(pmap, TRUE)) != NULL) { 2241 pv->pv_va = va; 2242 pvh = pa_to_pvh(pa); 2243 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_list); 2244 return (TRUE); 2245 } else 2246 return (FALSE); 2247} 2248 2249/* 2250 * Tries to demote a 2- or 4MB page mapping. 2251 */ 2252static boolean_t 2253pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va) 2254{ 2255 pd_entry_t newpde, oldpde; 2256 pmap_t allpmaps_entry; 2257 pt_entry_t *firstpte, newpte, *pte; 2258 vm_paddr_t mptepa; 2259 vm_page_t free, mpte; 2260 2261 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2262 mpte = pmap_lookup_pt_page(pmap, va); 2263 if (mpte != NULL) 2264 pmap_remove_pt_page(pmap, mpte); 2265 else { 2266 KASSERT((*pde & PG_W) == 0, 2267 ("pmap_demote_pde: page table page for a wired mapping" 2268 " is missing")); 2269 free = NULL; 2270 pmap_remove_pde(pmap, pde, trunc_4mpage(va), &free); 2271 pmap_invalidate_page(pmap, trunc_4mpage(va)); 2272 pmap_free_zero_pages(free); 2273 CTR2(KTR_PMAP, "pmap_demote_pde: failure for va %#x" 2274 " in pmap %p", va, pmap); 2275 return (FALSE); 2276 } 2277 mptepa = VM_PAGE_TO_PHYS(mpte); 2278 2279 /* 2280 * Temporarily map the page table page (mpte) into the kernel's 2281 * address space at either PADDR1 or PADDR2. 2282 */ 2283 if (curthread->td_pinned > 0 && mtx_owned(&vm_page_queue_mtx)) { 2284 if ((*PMAP1 & PG_FRAME) != mptepa) { 2285 *PMAP1 = mptepa | PG_RW | PG_V | PG_A | PG_M; 2286#ifdef SMP 2287 PMAP1cpu = PCPU_GET(cpuid); 2288#endif 2289 invlcaddr(PADDR1); 2290 PMAP1changed++; 2291 } else 2292#ifdef SMP 2293 if (PMAP1cpu != PCPU_GET(cpuid)) { 2294 PMAP1cpu = PCPU_GET(cpuid); 2295 invlcaddr(PADDR1); 2296 PMAP1changedcpu++; 2297 } else 2298#endif 2299 PMAP1unchanged++; 2300 firstpte = PADDR1; 2301 } else { 2302 mtx_lock(&PMAP2mutex); 2303 if ((*PMAP2 & PG_FRAME) != mptepa) { 2304 *PMAP2 = mptepa | PG_RW | PG_V | PG_A | PG_M; 2305 pmap_invalidate_page(kernel_pmap, (vm_offset_t)PADDR2); 2306 } 2307 firstpte = PADDR2; 2308 } 2309 oldpde = *pde; 2310 newpde = mptepa | PG_M | PG_A | (oldpde & PG_U) | PG_RW | PG_V; 2311 KASSERT((oldpde & (PG_A | PG_V)) == (PG_A | PG_V), 2312 ("pmap_demote_pde: oldpde is missing PG_A and/or PG_V")); 2313 KASSERT((oldpde & (PG_M | PG_RW)) != PG_RW, 2314 ("pmap_demote_pde: oldpde is missing PG_M")); 2315 KASSERT((oldpde & PG_PS) != 0, 2316 ("pmap_demote_pde: oldpde is missing PG_PS")); 2317 newpte = oldpde & ~PG_PS; 2318 if ((newpte & PG_PDE_PAT) != 0) 2319 newpte ^= PG_PDE_PAT | PG_PTE_PAT; 2320 2321 /* 2322 * If the mapping has changed attributes, update the page table 2323 * entries. 2324 */ 2325 KASSERT((*firstpte & PG_FRAME) == (newpte & PG_FRAME), 2326 ("pmap_demote_pde: firstpte and newpte map different physical" 2327 " addresses")); 2328 if ((*firstpte & PG_PTE_PROMOTE) != (newpte & PG_PTE_PROMOTE)) 2329 for (pte = firstpte; pte < firstpte + NPTEPG; pte++) { 2330 *pte = newpte; 2331 newpte += PAGE_SIZE; 2332 } 2333 2334 /* 2335 * Demote the mapping. This pmap is locked. The old PDE has 2336 * PG_A set. If the old PDE has PG_RW set, it also has PG_M 2337 * set. Thus, there is no danger of a race with another 2338 * processor changing the setting of PG_A and/or PG_M between 2339 * the read above and the store below. 2340 */ 2341 if (pmap == kernel_pmap) { 2342 /* 2343 * A harmless race exists between this loop and the bcopy() 2344 * in pmap_pinit() that initializes the kernel segment of 2345 * the new page table. Specifically, that bcopy() may copy 2346 * the new PDE from the PTD, which is first in allpmaps, to 2347 * the new page table before this loop updates that new 2348 * page table. 2349 */ 2350 mtx_lock_spin(&allpmaps_lock); 2351 LIST_FOREACH(allpmaps_entry, &allpmaps, pm_list) { 2352 pde = pmap_pde(allpmaps_entry, va); 2353 KASSERT(*pde == newpde || (*pde & PG_PTE_PROMOTE) == 2354 (oldpde & PG_PTE_PROMOTE), 2355 ("pmap_demote_pde: pde was %#jx, expected %#jx", 2356 (uintmax_t)*pde, (uintmax_t)oldpde)); 2357 pde_store(pde, newpde); 2358 } 2359 mtx_unlock_spin(&allpmaps_lock); 2360 } else 2361 pde_store(pde, newpde); 2362 if (firstpte == PADDR2) 2363 mtx_unlock(&PMAP2mutex); 2364 2365 /* 2366 * Invalidate the recursive mapping of the page table page. 2367 */ 2368 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va)); 2369 2370 /* 2371 * Demote the pv entry. This depends on the earlier demotion 2372 * of the mapping. Specifically, the (re)creation of a per- 2373 * page pv entry might trigger the execution of pmap_collect(), 2374 * which might reclaim a newly (re)created per-page pv entry 2375 * and destroy the associated mapping. In order to destroy 2376 * the mapping, the PDE must have already changed from mapping 2377 * the 2mpage to referencing the page table page. 2378 */ 2379 if ((oldpde & PG_MANAGED) != 0) 2380 pmap_pv_demote_pde(pmap, va, oldpde & PG_PS_FRAME); 2381 2382 pmap_pde_demotions++; 2383 CTR2(KTR_PMAP, "pmap_demote_pde: success for va %#x" 2384 " in pmap %p", va, pmap); 2385 return (TRUE); 2386} 2387 2388/* 2389 * pmap_remove_pde: do the things to unmap a superpage in a process 2390 */ 2391static void 2392pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva, 2393 vm_page_t *free) 2394{ 2395 struct md_page *pvh; 2396 pd_entry_t oldpde; 2397 vm_offset_t eva, va; 2398 vm_page_t m, mpte; 2399 2400 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2401 KASSERT((sva & PDRMASK) == 0, 2402 ("pmap_remove_pde: sva is not 4mpage aligned")); 2403 oldpde = pte_load_clear(pdq); 2404 if (oldpde & PG_W) 2405 pmap->pm_stats.wired_count -= NBPDR / PAGE_SIZE; 2406 2407 /* 2408 * Machines that don't support invlpg, also don't support 2409 * PG_G. 2410 */ 2411 if (oldpde & PG_G) 2412 pmap_invalidate_page(kernel_pmap, sva); 2413 pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE; 2414 if (oldpde & PG_MANAGED) { 2415 pvh = pa_to_pvh(oldpde & PG_PS_FRAME); 2416 pmap_pvh_free(pvh, pmap, sva); 2417 eva = sva + NBPDR; 2418 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME); 2419 va < eva; va += PAGE_SIZE, m++) { 2420 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW)) 2421 vm_page_dirty(m); 2422 if (oldpde & PG_A) 2423 vm_page_flag_set(m, PG_REFERENCED); 2424 if (TAILQ_EMPTY(&m->md.pv_list) && 2425 TAILQ_EMPTY(&pvh->pv_list)) 2426 vm_page_flag_clear(m, PG_WRITEABLE); 2427 } 2428 } 2429 if (pmap == kernel_pmap) { 2430 if (!pmap_demote_pde(pmap, pdq, sva)) 2431 panic("pmap_remove_pde: failed demotion"); 2432 } else { 2433 mpte = pmap_lookup_pt_page(pmap, sva); 2434 if (mpte != NULL) { 2435 pmap_remove_pt_page(pmap, mpte); 2436 KASSERT(mpte->wire_count == NPTEPG, 2437 ("pmap_remove_pde: pte page wire count error")); 2438 mpte->wire_count = 0; 2439 pmap_add_delayed_free_list(mpte, free, FALSE); 2440 atomic_subtract_int(&cnt.v_wire_count, 1); 2441 } 2442 } 2443} 2444 2445/* 2446 * pmap_remove_pte: do the things to unmap a page in a process 2447 */ 2448static int 2449pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t va, vm_page_t *free) 2450{ 2451 pt_entry_t oldpte; 2452 vm_page_t m; 2453 2454 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2455 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2456 oldpte = pte_load_clear(ptq); 2457 if (oldpte & PG_W) 2458 pmap->pm_stats.wired_count -= 1; 2459 /* 2460 * Machines that don't support invlpg, also don't support 2461 * PG_G. 2462 */ 2463 if (oldpte & PG_G) 2464 pmap_invalidate_page(kernel_pmap, va); 2465 pmap->pm_stats.resident_count -= 1; 2466 if (oldpte & PG_MANAGED) { 2467 m = PHYS_TO_VM_PAGE(oldpte & PG_FRAME); 2468 if ((oldpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) 2469 vm_page_dirty(m); 2470 if (oldpte & PG_A) 2471 vm_page_flag_set(m, PG_REFERENCED); 2472 pmap_remove_entry(pmap, m, va); 2473 } 2474 return (pmap_unuse_pt(pmap, va, free)); 2475} 2476 2477/* 2478 * Remove a single page from a process address space 2479 */ 2480static void 2481pmap_remove_page(pmap_t pmap, vm_offset_t va, vm_page_t *free) 2482{ 2483 pt_entry_t *pte; 2484 2485 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2486 KASSERT(curthread->td_pinned > 0, ("curthread not pinned")); 2487 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2488 if ((pte = pmap_pte_quick(pmap, va)) == NULL || *pte == 0) 2489 return; 2490 pmap_remove_pte(pmap, pte, va, free); 2491 pmap_invalidate_page(pmap, va); 2492} 2493 2494/* 2495 * Remove the given range of addresses from the specified map. 2496 * 2497 * It is assumed that the start and end are properly 2498 * rounded to the page size. 2499 */ 2500void 2501pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 2502{ 2503 vm_offset_t pdnxt; 2504 pd_entry_t ptpaddr; 2505 pt_entry_t *pte; 2506 vm_page_t free = NULL; 2507 int anyvalid; 2508 2509 /* 2510 * Perform an unsynchronized read. This is, however, safe. 2511 */ 2512 if (pmap->pm_stats.resident_count == 0) 2513 return; 2514 2515 anyvalid = 0; 2516 2517 vm_page_lock_queues(); 2518 sched_pin(); 2519 PMAP_LOCK(pmap); 2520 2521 /* 2522 * special handling of removing one page. a very 2523 * common operation and easy to short circuit some 2524 * code. 2525 */ 2526 if ((sva + PAGE_SIZE == eva) && 2527 ((pmap->pm_pdir[(sva >> PDRSHIFT)] & PG_PS) == 0)) { 2528 pmap_remove_page(pmap, sva, &free); 2529 goto out; 2530 } 2531 2532 for (; sva < eva; sva = pdnxt) { 2533 unsigned pdirindex; 2534 2535 /* 2536 * Calculate index for next page table. 2537 */ 2538 pdnxt = (sva + NBPDR) & ~PDRMASK; 2539 if (pdnxt < sva) 2540 pdnxt = eva; 2541 if (pmap->pm_stats.resident_count == 0) 2542 break; 2543 2544 pdirindex = sva >> PDRSHIFT; 2545 ptpaddr = pmap->pm_pdir[pdirindex]; 2546 2547 /* 2548 * Weed out invalid mappings. Note: we assume that the page 2549 * directory table is always allocated, and in kernel virtual. 2550 */ 2551 if (ptpaddr == 0) 2552 continue; 2553 2554 /* 2555 * Check for large page. 2556 */ 2557 if ((ptpaddr & PG_PS) != 0) { 2558 /* 2559 * Are we removing the entire large page? If not, 2560 * demote the mapping and fall through. 2561 */ 2562 if (sva + NBPDR == pdnxt && eva >= pdnxt) { 2563 /* 2564 * The TLB entry for a PG_G mapping is 2565 * invalidated by pmap_remove_pde(). 2566 */ 2567 if ((ptpaddr & PG_G) == 0) 2568 anyvalid = 1; 2569 pmap_remove_pde(pmap, 2570 &pmap->pm_pdir[pdirindex], sva, &free); 2571 continue; 2572 } else if (!pmap_demote_pde(pmap, 2573 &pmap->pm_pdir[pdirindex], sva)) { 2574 /* The large page mapping was destroyed. */ 2575 continue; 2576 } 2577 } 2578 2579 /* 2580 * Limit our scan to either the end of the va represented 2581 * by the current page table page, or to the end of the 2582 * range being removed. 2583 */ 2584 if (pdnxt > eva) 2585 pdnxt = eva; 2586 2587 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++, 2588 sva += PAGE_SIZE) { 2589 if (*pte == 0) 2590 continue; 2591 2592 /* 2593 * The TLB entry for a PG_G mapping is invalidated 2594 * by pmap_remove_pte(). 2595 */ 2596 if ((*pte & PG_G) == 0) 2597 anyvalid = 1; 2598 if (pmap_remove_pte(pmap, pte, sva, &free)) 2599 break; 2600 } 2601 } 2602out: 2603 sched_unpin(); 2604 if (anyvalid) 2605 pmap_invalidate_all(pmap); 2606 vm_page_unlock_queues(); 2607 PMAP_UNLOCK(pmap); 2608 pmap_free_zero_pages(free); 2609} 2610 2611/* 2612 * Routine: pmap_remove_all 2613 * Function: 2614 * Removes this physical page from 2615 * all physical maps in which it resides. 2616 * Reflects back modify bits to the pager. 2617 * 2618 * Notes: 2619 * Original versions of this routine were very 2620 * inefficient because they iteratively called 2621 * pmap_remove (slow...) 2622 */ 2623 2624void 2625pmap_remove_all(vm_page_t m) 2626{ 2627 struct md_page *pvh; 2628 pv_entry_t pv; 2629 pmap_t pmap; 2630 pt_entry_t *pte, tpte; 2631 pd_entry_t *pde; 2632 vm_offset_t va; 2633 vm_page_t free; 2634 2635 KASSERT((m->flags & PG_FICTITIOUS) == 0, 2636 ("pmap_remove_all: page %p is fictitious", m)); 2637 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2638 sched_pin(); 2639 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 2640 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) { 2641 va = pv->pv_va; 2642 pmap = PV_PMAP(pv); 2643 PMAP_LOCK(pmap); 2644 pde = pmap_pde(pmap, va); 2645 (void)pmap_demote_pde(pmap, pde, va); 2646 PMAP_UNLOCK(pmap); 2647 } 2648 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) { 2649 pmap = PV_PMAP(pv); 2650 PMAP_LOCK(pmap); 2651 pmap->pm_stats.resident_count--; 2652 pde = pmap_pde(pmap, pv->pv_va); 2653 KASSERT((*pde & PG_PS) == 0, ("pmap_remove_all: found" 2654 " a 4mpage in page %p's pv list", m)); 2655 pte = pmap_pte_quick(pmap, pv->pv_va); 2656 tpte = pte_load_clear(pte); 2657 if (tpte & PG_W) 2658 pmap->pm_stats.wired_count--; 2659 if (tpte & PG_A) 2660 vm_page_flag_set(m, PG_REFERENCED); 2661 2662 /* 2663 * Update the vm_page_t clean and reference bits. 2664 */ 2665 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) 2666 vm_page_dirty(m); 2667 free = NULL; 2668 pmap_unuse_pt(pmap, pv->pv_va, &free); 2669 pmap_invalidate_page(pmap, pv->pv_va); 2670 pmap_free_zero_pages(free); 2671 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list); 2672 free_pv_entry(pmap, pv); 2673 PMAP_UNLOCK(pmap); 2674 } 2675 vm_page_flag_clear(m, PG_WRITEABLE); 2676 sched_unpin(); 2677} 2678 2679/* 2680 * pmap_protect_pde: do the things to protect a 4mpage in a process 2681 */ 2682static boolean_t 2683pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva, vm_prot_t prot) 2684{ 2685 pd_entry_t newpde, oldpde; 2686 vm_offset_t eva, va; 2687 vm_page_t m; 2688 boolean_t anychanged; 2689 2690 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2691 KASSERT((sva & PDRMASK) == 0, 2692 ("pmap_protect_pde: sva is not 4mpage aligned")); 2693 anychanged = FALSE; 2694retry: 2695 oldpde = newpde = *pde; 2696 if (oldpde & PG_MANAGED) { 2697 eva = sva + NBPDR; 2698 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME); 2699 va < eva; va += PAGE_SIZE, m++) { 2700 /* 2701 * In contrast to the analogous operation on a 4KB page 2702 * mapping, the mapping's PG_A flag is not cleared and 2703 * the page's PG_REFERENCED flag is not set. The 2704 * reason is that pmap_demote_pde() expects that a 2/4MB 2705 * page mapping with a stored page table page has PG_A 2706 * set. 2707 */ 2708 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW)) 2709 vm_page_dirty(m); 2710 } 2711 } 2712 if ((prot & VM_PROT_WRITE) == 0) 2713 newpde &= ~(PG_RW | PG_M); 2714#ifdef PAE 2715 if ((prot & VM_PROT_EXECUTE) == 0) 2716 newpde |= pg_nx; 2717#endif 2718 if (newpde != oldpde) { 2719 if (!pde_cmpset(pde, oldpde, newpde)) 2720 goto retry; 2721 if (oldpde & PG_G) 2722 pmap_invalidate_page(pmap, sva); 2723 else 2724 anychanged = TRUE; 2725 } 2726 return (anychanged); 2727} 2728 2729/* 2730 * Set the physical protection on the 2731 * specified range of this map as requested. 2732 */ 2733void 2734pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot) 2735{ 2736 vm_offset_t pdnxt; 2737 pd_entry_t ptpaddr; 2738 pt_entry_t *pte; 2739 int anychanged; 2740 2741 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 2742 pmap_remove(pmap, sva, eva); 2743 return; 2744 } 2745 2746#ifdef PAE 2747 if ((prot & (VM_PROT_WRITE|VM_PROT_EXECUTE)) == 2748 (VM_PROT_WRITE|VM_PROT_EXECUTE)) 2749 return; 2750#else 2751 if (prot & VM_PROT_WRITE) 2752 return; 2753#endif 2754 2755 anychanged = 0; 2756 2757 vm_page_lock_queues(); 2758 sched_pin(); 2759 PMAP_LOCK(pmap); 2760 for (; sva < eva; sva = pdnxt) { 2761 pt_entry_t obits, pbits; 2762 unsigned pdirindex; 2763 2764 pdnxt = (sva + NBPDR) & ~PDRMASK; 2765 if (pdnxt < sva) 2766 pdnxt = eva; 2767 2768 pdirindex = sva >> PDRSHIFT; 2769 ptpaddr = pmap->pm_pdir[pdirindex]; 2770 2771 /* 2772 * Weed out invalid mappings. Note: we assume that the page 2773 * directory table is always allocated, and in kernel virtual. 2774 */ 2775 if (ptpaddr == 0) 2776 continue; 2777 2778 /* 2779 * Check for large page. 2780 */ 2781 if ((ptpaddr & PG_PS) != 0) { 2782 /* 2783 * Are we protecting the entire large page? If not, 2784 * demote the mapping and fall through. 2785 */ 2786 if (sva + NBPDR == pdnxt && eva >= pdnxt) { 2787 /* 2788 * The TLB entry for a PG_G mapping is 2789 * invalidated by pmap_protect_pde(). 2790 */ 2791 if (pmap_protect_pde(pmap, 2792 &pmap->pm_pdir[pdirindex], sva, prot)) 2793 anychanged = 1; 2794 continue; 2795 } else if (!pmap_demote_pde(pmap, 2796 &pmap->pm_pdir[pdirindex], sva)) { 2797 /* The large page mapping was destroyed. */ 2798 continue; 2799 } 2800 } 2801 2802 if (pdnxt > eva) 2803 pdnxt = eva; 2804 2805 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++, 2806 sva += PAGE_SIZE) { 2807 vm_page_t m; 2808 2809retry: 2810 /* 2811 * Regardless of whether a pte is 32 or 64 bits in 2812 * size, PG_RW, PG_A, and PG_M are among the least 2813 * significant 32 bits. 2814 */ 2815 obits = pbits = *pte; 2816 if ((pbits & PG_V) == 0) 2817 continue; 2818 if (pbits & PG_MANAGED) { 2819 m = NULL; 2820 if (pbits & PG_A) { 2821 m = PHYS_TO_VM_PAGE(pbits & PG_FRAME); 2822 vm_page_flag_set(m, PG_REFERENCED); 2823 pbits &= ~PG_A; 2824 } 2825 if ((pbits & (PG_M | PG_RW)) == (PG_M | PG_RW)) { 2826 if (m == NULL) 2827 m = PHYS_TO_VM_PAGE(pbits & PG_FRAME); 2828 vm_page_dirty(m); 2829 } 2830 } 2831 2832 if ((prot & VM_PROT_WRITE) == 0) 2833 pbits &= ~(PG_RW | PG_M); 2834#ifdef PAE 2835 if ((prot & VM_PROT_EXECUTE) == 0) 2836 pbits |= pg_nx; 2837#endif 2838 2839 if (pbits != obits) { 2840#ifdef PAE 2841 if (!atomic_cmpset_64(pte, obits, pbits)) 2842 goto retry; 2843#else 2844 if (!atomic_cmpset_int((u_int *)pte, obits, 2845 pbits)) 2846 goto retry; 2847#endif 2848 if (obits & PG_G) 2849 pmap_invalidate_page(pmap, sva); 2850 else 2851 anychanged = 1; 2852 } 2853 } 2854 } 2855 sched_unpin(); 2856 if (anychanged) 2857 pmap_invalidate_all(pmap); 2858 vm_page_unlock_queues(); 2859 PMAP_UNLOCK(pmap); 2860} 2861 2862/* 2863 * Tries to promote the 512 or 1024, contiguous 4KB page mappings that are 2864 * within a single page table page (PTP) to a single 2- or 4MB page mapping. 2865 * For promotion to occur, two conditions must be met: (1) the 4KB page 2866 * mappings must map aligned, contiguous physical memory and (2) the 4KB page 2867 * mappings must have identical characteristics. 2868 * 2869 * Managed (PG_MANAGED) mappings within the kernel address space are not 2870 * promoted. The reason is that kernel PDEs are replicated in each pmap but 2871 * pmap_clear_ptes() and pmap_ts_referenced() only read the PDE from the kernel 2872 * pmap. 2873 */ 2874static void 2875pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va) 2876{ 2877 pd_entry_t newpde; 2878 pmap_t allpmaps_entry; 2879 pt_entry_t *firstpte, oldpte, pa, *pte; 2880 vm_offset_t oldpteva; 2881 vm_page_t mpte; 2882 2883 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2884 2885 /* 2886 * Examine the first PTE in the specified PTP. Abort if this PTE is 2887 * either invalid, unused, or does not map the first 4KB physical page 2888 * within a 2- or 4MB page. 2889 */ 2890 firstpte = vtopte(trunc_4mpage(va)); 2891setpde: 2892 newpde = *firstpte; 2893 if ((newpde & ((PG_FRAME & PDRMASK) | PG_A | PG_V)) != (PG_A | PG_V)) { 2894 pmap_pde_p_failures++; 2895 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x" 2896 " in pmap %p", va, pmap); 2897 return; 2898 } 2899 if ((*firstpte & PG_MANAGED) != 0 && pmap == kernel_pmap) { 2900 pmap_pde_p_failures++; 2901 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x" 2902 " in pmap %p", va, pmap); 2903 return; 2904 } 2905 if ((newpde & (PG_M | PG_RW)) == PG_RW) { 2906 /* 2907 * When PG_M is already clear, PG_RW can be cleared without 2908 * a TLB invalidation. 2909 */ 2910 if (!atomic_cmpset_int((u_int *)firstpte, newpde, newpde & 2911 ~PG_RW)) 2912 goto setpde; 2913 newpde &= ~PG_RW; 2914 } 2915 2916 /* 2917 * Examine each of the other PTEs in the specified PTP. Abort if this 2918 * PTE maps an unexpected 4KB physical page or does not have identical 2919 * characteristics to the first PTE. 2920 */ 2921 pa = (newpde & (PG_PS_FRAME | PG_A | PG_V)) + NBPDR - PAGE_SIZE; 2922 for (pte = firstpte + NPTEPG - 1; pte > firstpte; pte--) { 2923setpte: 2924 oldpte = *pte; 2925 if ((oldpte & (PG_FRAME | PG_A | PG_V)) != pa) { 2926 pmap_pde_p_failures++; 2927 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x" 2928 " in pmap %p", va, pmap); 2929 return; 2930 } 2931 if ((oldpte & (PG_M | PG_RW)) == PG_RW) { 2932 /* 2933 * When PG_M is already clear, PG_RW can be cleared 2934 * without a TLB invalidation. 2935 */ 2936 if (!atomic_cmpset_int((u_int *)pte, oldpte, 2937 oldpte & ~PG_RW)) 2938 goto setpte; 2939 oldpte &= ~PG_RW; 2940 oldpteva = (oldpte & PG_FRAME & PDRMASK) | 2941 (va & ~PDRMASK); 2942 CTR2(KTR_PMAP, "pmap_promote_pde: protect for va %#x" 2943 " in pmap %p", oldpteva, pmap); 2944 } 2945 if ((oldpte & PG_PTE_PROMOTE) != (newpde & PG_PTE_PROMOTE)) { 2946 pmap_pde_p_failures++; 2947 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x" 2948 " in pmap %p", va, pmap); 2949 return; 2950 } 2951 pa -= PAGE_SIZE; 2952 } 2953 2954 /* 2955 * Save the page table page in its current state until the PDE 2956 * mapping the superpage is demoted by pmap_demote_pde() or 2957 * destroyed by pmap_remove_pde(). 2958 */ 2959 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME); 2960 KASSERT(mpte >= vm_page_array && 2961 mpte < &vm_page_array[vm_page_array_size], 2962 ("pmap_promote_pde: page table page is out of range")); 2963 KASSERT(mpte->pindex == va >> PDRSHIFT, 2964 ("pmap_promote_pde: page table page's pindex is wrong")); 2965 pmap_insert_pt_page(pmap, mpte); 2966 2967 /* 2968 * Promote the pv entries. 2969 */ 2970 if ((newpde & PG_MANAGED) != 0) 2971 pmap_pv_promote_pde(pmap, va, newpde & PG_PS_FRAME); 2972 2973 /* 2974 * Propagate the PAT index to its proper position. 2975 */ 2976 if ((newpde & PG_PTE_PAT) != 0) 2977 newpde ^= PG_PDE_PAT | PG_PTE_PAT; 2978 2979 /* 2980 * Map the superpage. 2981 */ 2982 if (pmap == kernel_pmap) { 2983 mtx_lock_spin(&allpmaps_lock); 2984 LIST_FOREACH(allpmaps_entry, &allpmaps, pm_list) { 2985 pde = pmap_pde(allpmaps_entry, va); 2986 pde_store(pde, PG_PS | newpde); 2987 } 2988 mtx_unlock_spin(&allpmaps_lock); 2989 } else 2990 pde_store(pde, PG_PS | newpde); 2991 2992 pmap_pde_promotions++; 2993 CTR2(KTR_PMAP, "pmap_promote_pde: success for va %#x" 2994 " in pmap %p", va, pmap); 2995} 2996 2997/* 2998 * Insert the given physical page (p) at 2999 * the specified virtual address (v) in the 3000 * target physical map with the protection requested. 3001 * 3002 * If specified, the page will be wired down, meaning 3003 * that the related pte can not be reclaimed. 3004 * 3005 * NB: This is the only routine which MAY NOT lazy-evaluate 3006 * or lose information. That is, this routine must actually 3007 * insert this page into the given map NOW. 3008 */ 3009void 3010pmap_enter(pmap_t pmap, vm_offset_t va, vm_prot_t access, vm_page_t m, 3011 vm_prot_t prot, boolean_t wired) 3012{ 3013 vm_paddr_t pa; 3014 pd_entry_t *pde; 3015 pt_entry_t *pte; 3016 vm_paddr_t opa; 3017 pt_entry_t origpte, newpte; 3018 vm_page_t mpte, om; 3019 boolean_t invlva; 3020 3021 va = trunc_page(va); 3022 KASSERT(va <= VM_MAX_KERNEL_ADDRESS, ("pmap_enter: toobig")); 3023 KASSERT(va < UPT_MIN_ADDRESS || va >= UPT_MAX_ADDRESS, 3024 ("pmap_enter: invalid to pmap_enter page table pages (va: 0x%x)", va)); 3025 3026 mpte = NULL; 3027 3028 vm_page_lock_queues(); 3029 PMAP_LOCK(pmap); 3030 sched_pin(); 3031 3032 /* 3033 * In the case that a page table page is not 3034 * resident, we are creating it here. 3035 */ 3036 if (va < VM_MAXUSER_ADDRESS) { 3037 mpte = pmap_allocpte(pmap, va, M_WAITOK); 3038 } 3039 3040 pde = pmap_pde(pmap, va); 3041 if ((*pde & PG_PS) != 0) 3042 panic("pmap_enter: attempted pmap_enter on 4MB page"); 3043 pte = pmap_pte_quick(pmap, va); 3044 3045 /* 3046 * Page Directory table entry not valid, we need a new PT page 3047 */ 3048 if (pte == NULL) { 3049 panic("pmap_enter: invalid page directory pdir=%#jx, va=%#x", 3050 (uintmax_t)pmap->pm_pdir[PTDPTDI], va); 3051 } 3052 3053 pa = VM_PAGE_TO_PHYS(m); 3054 om = NULL; 3055 origpte = *pte; 3056 opa = origpte & PG_FRAME; 3057 3058 /* 3059 * Mapping has not changed, must be protection or wiring change. 3060 */ 3061 if (origpte && (opa == pa)) { 3062 /* 3063 * Wiring change, just update stats. We don't worry about 3064 * wiring PT pages as they remain resident as long as there 3065 * are valid mappings in them. Hence, if a user page is wired, 3066 * the PT page will be also. 3067 */ 3068 if (wired && ((origpte & PG_W) == 0)) 3069 pmap->pm_stats.wired_count++; 3070 else if (!wired && (origpte & PG_W)) 3071 pmap->pm_stats.wired_count--; 3072 3073 /* 3074 * Remove extra pte reference 3075 */ 3076 if (mpte) 3077 mpte->wire_count--; 3078 3079 /* 3080 * We might be turning off write access to the page, 3081 * so we go ahead and sense modify status. 3082 */ 3083 if (origpte & PG_MANAGED) { 3084 om = m; 3085 pa |= PG_MANAGED; 3086 } 3087 goto validate; 3088 } 3089 /* 3090 * Mapping has changed, invalidate old range and fall through to 3091 * handle validating new mapping. 3092 */ 3093 if (opa) { 3094 if (origpte & PG_W) 3095 pmap->pm_stats.wired_count--; 3096 if (origpte & PG_MANAGED) { 3097 om = PHYS_TO_VM_PAGE(opa); 3098 pmap_remove_entry(pmap, om, va); 3099 } 3100 if (mpte != NULL) { 3101 mpte->wire_count--; 3102 KASSERT(mpte->wire_count > 0, 3103 ("pmap_enter: missing reference to page table page," 3104 " va: 0x%x", va)); 3105 } 3106 } else 3107 pmap->pm_stats.resident_count++; 3108 3109 /* 3110 * Enter on the PV list if part of our managed memory. 3111 */ 3112 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0) { 3113 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva, 3114 ("pmap_enter: managed mapping within the clean submap")); 3115 pmap_insert_entry(pmap, va, m); 3116 pa |= PG_MANAGED; 3117 } 3118 3119 /* 3120 * Increment counters 3121 */ 3122 if (wired) 3123 pmap->pm_stats.wired_count++; 3124 3125validate: 3126 /* 3127 * Now validate mapping with desired protection/wiring. 3128 */ 3129 newpte = (pt_entry_t)(pa | PG_V); 3130 if ((prot & VM_PROT_WRITE) != 0) { 3131 newpte |= PG_RW; 3132 vm_page_flag_set(m, PG_WRITEABLE); 3133 } 3134#ifdef PAE 3135 if ((prot & VM_PROT_EXECUTE) == 0) 3136 newpte |= pg_nx; 3137#endif 3138 if (wired) 3139 newpte |= PG_W; 3140 if (va < VM_MAXUSER_ADDRESS) 3141 newpte |= PG_U; 3142 if (pmap == kernel_pmap) 3143 newpte |= pgeflag; 3144 3145 /* 3146 * if the mapping or permission bits are different, we need 3147 * to update the pte. 3148 */ 3149 if ((origpte & ~(PG_M|PG_A)) != newpte) { 3150 newpte |= PG_A; 3151 if ((access & VM_PROT_WRITE) != 0) 3152 newpte |= PG_M; 3153 if (origpte & PG_V) { 3154 invlva = FALSE; 3155 origpte = pte_load_store(pte, newpte); 3156 if (origpte & PG_A) { 3157 if (origpte & PG_MANAGED) 3158 vm_page_flag_set(om, PG_REFERENCED); 3159 if (opa != VM_PAGE_TO_PHYS(m)) 3160 invlva = TRUE; 3161#ifdef PAE 3162 if ((origpte & PG_NX) == 0 && 3163 (newpte & PG_NX) != 0) 3164 invlva = TRUE; 3165#endif 3166 } 3167 if ((origpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) { 3168 if ((origpte & PG_MANAGED) != 0) 3169 vm_page_dirty(om); 3170 if ((prot & VM_PROT_WRITE) == 0) 3171 invlva = TRUE; 3172 } 3173 if (invlva) 3174 pmap_invalidate_page(pmap, va); 3175 } else 3176 pte_store(pte, newpte); 3177 } 3178 3179 /* 3180 * If both the page table page and the reservation are fully 3181 * populated, then attempt promotion. 3182 */ 3183 if ((mpte == NULL || mpte->wire_count == NPTEPG) && 3184 pg_ps_enabled && vm_reserv_level_iffullpop(m) == 0) 3185 pmap_promote_pde(pmap, pde, va); 3186 3187 sched_unpin(); 3188 vm_page_unlock_queues(); 3189 PMAP_UNLOCK(pmap); 3190} 3191 3192/* 3193 * Tries to create a 2- or 4MB page mapping. Returns TRUE if successful and 3194 * FALSE otherwise. Fails if (1) a page table page cannot be allocated without 3195 * blocking, (2) a mapping already exists at the specified virtual address, or 3196 * (3) a pv entry cannot be allocated without reclaiming another pv entry. 3197 */ 3198static boolean_t 3199pmap_enter_pde(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot) 3200{ 3201 pd_entry_t *pde, newpde; 3202 3203 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 3204 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 3205 pde = pmap_pde(pmap, va); 3206 if (*pde != 0) { 3207 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx" 3208 " in pmap %p", va, pmap); 3209 return (FALSE); 3210 } 3211 newpde = VM_PAGE_TO_PHYS(m) | PG_PS | PG_V; 3212 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0) { 3213 newpde |= PG_MANAGED; 3214 3215 /* 3216 * Abort this mapping if its PV entry could not be created. 3217 */ 3218 if (!pmap_pv_insert_pde(pmap, va, VM_PAGE_TO_PHYS(m))) { 3219 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx" 3220 " in pmap %p", va, pmap); 3221 return (FALSE); 3222 } 3223 } 3224#ifdef PAE 3225 if ((prot & VM_PROT_EXECUTE) == 0) 3226 newpde |= pg_nx; 3227#endif 3228 if (va < VM_MAXUSER_ADDRESS) 3229 newpde |= PG_U; 3230 3231 /* 3232 * Increment counters. 3233 */ 3234 pmap->pm_stats.resident_count += NBPDR / PAGE_SIZE; 3235 3236 /* 3237 * Map the superpage. 3238 */ 3239 pde_store(pde, newpde); 3240 3241 pmap_pde_mappings++; 3242 CTR2(KTR_PMAP, "pmap_enter_pde: success for va %#lx" 3243 " in pmap %p", va, pmap); 3244 return (TRUE); 3245} 3246 3247/* 3248 * Maps a sequence of resident pages belonging to the same object. 3249 * The sequence begins with the given page m_start. This page is 3250 * mapped at the given virtual address start. Each subsequent page is 3251 * mapped at a virtual address that is offset from start by the same 3252 * amount as the page is offset from m_start within the object. The 3253 * last page in the sequence is the page with the largest offset from 3254 * m_start that can be mapped at a virtual address less than the given 3255 * virtual address end. Not every virtual page between start and end 3256 * is mapped; only those for which a resident page exists with the 3257 * corresponding offset from m_start are mapped. 3258 */ 3259void 3260pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end, 3261 vm_page_t m_start, vm_prot_t prot) 3262{ 3263 vm_offset_t va; 3264 vm_page_t m, mpte; 3265 vm_pindex_t diff, psize; 3266 3267 VM_OBJECT_LOCK_ASSERT(m_start->object, MA_OWNED); 3268 psize = atop(end - start); 3269 mpte = NULL; 3270 m = m_start; 3271 PMAP_LOCK(pmap); 3272 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 3273 va = start + ptoa(diff); 3274 if ((va & PDRMASK) == 0 && va + NBPDR <= end && 3275 (VM_PAGE_TO_PHYS(m) & PDRMASK) == 0 && 3276 pg_ps_enabled && vm_reserv_level_iffullpop(m) == 0 && 3277 pmap_enter_pde(pmap, va, m, prot)) 3278 m = &m[NBPDR / PAGE_SIZE - 1]; 3279 else 3280 mpte = pmap_enter_quick_locked(pmap, va, m, prot, 3281 mpte); 3282 m = TAILQ_NEXT(m, listq); 3283 } 3284 PMAP_UNLOCK(pmap); 3285} 3286 3287/* 3288 * this code makes some *MAJOR* assumptions: 3289 * 1. Current pmap & pmap exists. 3290 * 2. Not wired. 3291 * 3. Read access. 3292 * 4. No page table pages. 3293 * but is *MUCH* faster than pmap_enter... 3294 */ 3295 3296void 3297pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot) 3298{ 3299 3300 PMAP_LOCK(pmap); 3301 (void) pmap_enter_quick_locked(pmap, va, m, prot, NULL); 3302 PMAP_UNLOCK(pmap); 3303} 3304 3305static vm_page_t 3306pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m, 3307 vm_prot_t prot, vm_page_t mpte) 3308{ 3309 pt_entry_t *pte; 3310 vm_paddr_t pa; 3311 vm_page_t free; 3312 3313 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva || 3314 (m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0, 3315 ("pmap_enter_quick_locked: managed mapping within the clean submap")); 3316 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 3317 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 3318 3319 /* 3320 * In the case that a page table page is not 3321 * resident, we are creating it here. 3322 */ 3323 if (va < VM_MAXUSER_ADDRESS) { 3324 unsigned ptepindex; 3325 pd_entry_t ptepa; 3326 3327 /* 3328 * Calculate pagetable page index 3329 */ 3330 ptepindex = va >> PDRSHIFT; 3331 if (mpte && (mpte->pindex == ptepindex)) { 3332 mpte->wire_count++; 3333 } else { 3334 /* 3335 * Get the page directory entry 3336 */ 3337 ptepa = pmap->pm_pdir[ptepindex]; 3338 3339 /* 3340 * If the page table page is mapped, we just increment 3341 * the hold count, and activate it. 3342 */ 3343 if (ptepa) { 3344 if (ptepa & PG_PS) 3345 return (NULL); 3346 mpte = PHYS_TO_VM_PAGE(ptepa & PG_FRAME); 3347 mpte->wire_count++; 3348 } else { 3349 mpte = _pmap_allocpte(pmap, ptepindex, 3350 M_NOWAIT); 3351 if (mpte == NULL) 3352 return (mpte); 3353 } 3354 } 3355 } else { 3356 mpte = NULL; 3357 } 3358 3359 /* 3360 * This call to vtopte makes the assumption that we are 3361 * entering the page into the current pmap. In order to support 3362 * quick entry into any pmap, one would likely use pmap_pte_quick. 3363 * But that isn't as quick as vtopte. 3364 */ 3365 pte = vtopte(va); 3366 if (*pte) { 3367 if (mpte != NULL) { 3368 mpte->wire_count--; 3369 mpte = NULL; 3370 } 3371 return (mpte); 3372 } 3373 3374 /* 3375 * Enter on the PV list if part of our managed memory. 3376 */ 3377 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0 && 3378 !pmap_try_insert_pv_entry(pmap, va, m)) { 3379 if (mpte != NULL) { 3380 free = NULL; 3381 if (pmap_unwire_pte_hold(pmap, mpte, &free)) { 3382 pmap_invalidate_page(pmap, va); 3383 pmap_free_zero_pages(free); 3384 } 3385 3386 mpte = NULL; 3387 } 3388 return (mpte); 3389 } 3390 3391 /* 3392 * Increment counters 3393 */ 3394 pmap->pm_stats.resident_count++; 3395 3396 pa = VM_PAGE_TO_PHYS(m); 3397#ifdef PAE 3398 if ((prot & VM_PROT_EXECUTE) == 0) 3399 pa |= pg_nx; 3400#endif 3401 3402 /* 3403 * Now validate mapping with RO protection 3404 */ 3405 if (m->flags & (PG_FICTITIOUS|PG_UNMANAGED)) 3406 pte_store(pte, pa | PG_V | PG_U); 3407 else 3408 pte_store(pte, pa | PG_V | PG_U | PG_MANAGED); 3409 return mpte; 3410} 3411 3412/* 3413 * Make a temporary mapping for a physical address. This is only intended 3414 * to be used for panic dumps. 3415 */ 3416void * 3417pmap_kenter_temporary(vm_paddr_t pa, int i) 3418{ 3419 vm_offset_t va; 3420 3421 va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE); 3422 pmap_kenter(va, pa); 3423 invlpg(va); 3424 return ((void *)crashdumpmap); 3425} 3426 3427/* 3428 * This code maps large physical mmap regions into the 3429 * processor address space. Note that some shortcuts 3430 * are taken, but the code works. 3431 */ 3432void 3433pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object, 3434 vm_pindex_t pindex, vm_size_t size) 3435{ 3436 vm_page_t p; 3437 3438 VM_OBJECT_LOCK_ASSERT(object, MA_OWNED); 3439 KASSERT(object->type == OBJT_DEVICE, 3440 ("pmap_object_init_pt: non-device object")); 3441 if (pseflag && 3442 ((addr & (NBPDR - 1)) == 0) && ((size & (NBPDR - 1)) == 0)) { 3443 int i; 3444 vm_page_t m[1]; 3445 unsigned int ptepindex; 3446 int npdes; 3447 pd_entry_t ptepa; 3448 3449 PMAP_LOCK(pmap); 3450 if (pmap->pm_pdir[ptepindex = (addr >> PDRSHIFT)]) 3451 goto out; 3452 PMAP_UNLOCK(pmap); 3453retry: 3454 p = vm_page_lookup(object, pindex); 3455 if (p != NULL) { 3456 if (vm_page_sleep_if_busy(p, FALSE, "init4p")) 3457 goto retry; 3458 } else { 3459 p = vm_page_alloc(object, pindex, VM_ALLOC_NORMAL); 3460 if (p == NULL) 3461 return; 3462 m[0] = p; 3463 3464 if (vm_pager_get_pages(object, m, 1, 0) != VM_PAGER_OK) { 3465 vm_page_lock_queues(); 3466 vm_page_free(p); 3467 vm_page_unlock_queues(); 3468 return; 3469 } 3470 3471 p = vm_page_lookup(object, pindex); 3472 vm_page_wakeup(p); 3473 } 3474 3475 ptepa = VM_PAGE_TO_PHYS(p); 3476 if (ptepa & (NBPDR - 1)) 3477 return; 3478 3479 p->valid = VM_PAGE_BITS_ALL; 3480 3481 PMAP_LOCK(pmap); 3482 pmap->pm_stats.resident_count += size >> PAGE_SHIFT; 3483 npdes = size >> PDRSHIFT; 3484 for(i = 0; i < npdes; i++) { 3485 pde_store(&pmap->pm_pdir[ptepindex], 3486 ptepa | PG_U | PG_RW | PG_V | PG_PS); 3487 ptepa += NBPDR; 3488 ptepindex += 1; 3489 } 3490 pmap_invalidate_all(pmap); 3491out: 3492 PMAP_UNLOCK(pmap); 3493 } 3494} 3495 3496/* 3497 * Routine: pmap_change_wiring 3498 * Function: Change the wiring attribute for a map/virtual-address 3499 * pair. 3500 * In/out conditions: 3501 * The mapping must already exist in the pmap. 3502 */ 3503void 3504pmap_change_wiring(pmap_t pmap, vm_offset_t va, boolean_t wired) 3505{ 3506 pd_entry_t *pde; 3507 pt_entry_t *pte; 3508 boolean_t are_queues_locked; 3509 3510 are_queues_locked = FALSE; 3511retry: 3512 PMAP_LOCK(pmap); 3513 pde = pmap_pde(pmap, va); 3514 if ((*pde & PG_PS) != 0) { 3515 if (!wired != ((*pde & PG_W) == 0)) { 3516 if (!are_queues_locked) { 3517 are_queues_locked = TRUE; 3518 if (!mtx_trylock(&vm_page_queue_mtx)) { 3519 PMAP_UNLOCK(pmap); 3520 vm_page_lock_queues(); 3521 goto retry; 3522 } 3523 } 3524 if (!pmap_demote_pde(pmap, pde, va)) 3525 panic("pmap_change_wiring: demotion failed"); 3526 } else 3527 goto out; 3528 } 3529 pte = pmap_pte(pmap, va); 3530 3531 if (wired && !pmap_pte_w(pte)) 3532 pmap->pm_stats.wired_count++; 3533 else if (!wired && pmap_pte_w(pte)) 3534 pmap->pm_stats.wired_count--; 3535 3536 /* 3537 * Wiring is not a hardware characteristic so there is no need to 3538 * invalidate TLB. 3539 */ 3540 pmap_pte_set_w(pte, wired); 3541 pmap_pte_release(pte); 3542out: 3543 if (are_queues_locked) 3544 vm_page_unlock_queues(); 3545 PMAP_UNLOCK(pmap); 3546} 3547 3548 3549 3550/* 3551 * Copy the range specified by src_addr/len 3552 * from the source map to the range dst_addr/len 3553 * in the destination map. 3554 * 3555 * This routine is only advisory and need not do anything. 3556 */ 3557 3558void 3559pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len, 3560 vm_offset_t src_addr) 3561{ 3562 vm_page_t free; 3563 vm_offset_t addr; 3564 vm_offset_t end_addr = src_addr + len; 3565 vm_offset_t pdnxt; 3566 3567 if (dst_addr != src_addr) 3568 return; 3569 3570 if (!pmap_is_current(src_pmap)) 3571 return; 3572 3573 vm_page_lock_queues(); 3574 if (dst_pmap < src_pmap) { 3575 PMAP_LOCK(dst_pmap); 3576 PMAP_LOCK(src_pmap); 3577 } else { 3578 PMAP_LOCK(src_pmap); 3579 PMAP_LOCK(dst_pmap); 3580 } 3581 sched_pin(); 3582 for (addr = src_addr; addr < end_addr; addr = pdnxt) { 3583 pt_entry_t *src_pte, *dst_pte; 3584 vm_page_t dstmpte, srcmpte; 3585 pd_entry_t srcptepaddr; 3586 unsigned ptepindex; 3587 3588 KASSERT(addr < UPT_MIN_ADDRESS, 3589 ("pmap_copy: invalid to pmap_copy page tables")); 3590 3591 pdnxt = (addr + NBPDR) & ~PDRMASK; 3592 if (pdnxt < addr) 3593 pdnxt = end_addr; 3594 ptepindex = addr >> PDRSHIFT; 3595 3596 srcptepaddr = src_pmap->pm_pdir[ptepindex]; 3597 if (srcptepaddr == 0) 3598 continue; 3599 3600 if (srcptepaddr & PG_PS) { 3601 if (dst_pmap->pm_pdir[ptepindex] == 0 && 3602 ((srcptepaddr & PG_MANAGED) == 0 || 3603 pmap_pv_insert_pde(dst_pmap, addr, srcptepaddr & 3604 PG_PS_FRAME))) { 3605 dst_pmap->pm_pdir[ptepindex] = srcptepaddr & 3606 ~PG_W; 3607 dst_pmap->pm_stats.resident_count += 3608 NBPDR / PAGE_SIZE; 3609 } 3610 continue; 3611 } 3612 3613 srcmpte = PHYS_TO_VM_PAGE(srcptepaddr & PG_FRAME); 3614 KASSERT(srcmpte->wire_count > 0, 3615 ("pmap_copy: source page table page is unused")); 3616 3617 if (pdnxt > end_addr) 3618 pdnxt = end_addr; 3619 3620 src_pte = vtopte(addr); 3621 while (addr < pdnxt) { 3622 pt_entry_t ptetemp; 3623 ptetemp = *src_pte; 3624 /* 3625 * we only virtual copy managed pages 3626 */ 3627 if ((ptetemp & PG_MANAGED) != 0) { 3628 dstmpte = pmap_allocpte(dst_pmap, addr, 3629 M_NOWAIT); 3630 if (dstmpte == NULL) 3631 break; 3632 dst_pte = pmap_pte_quick(dst_pmap, addr); 3633 if (*dst_pte == 0 && 3634 pmap_try_insert_pv_entry(dst_pmap, addr, 3635 PHYS_TO_VM_PAGE(ptetemp & PG_FRAME))) { 3636 /* 3637 * Clear the wired, modified, and 3638 * accessed (referenced) bits 3639 * during the copy. 3640 */ 3641 *dst_pte = ptetemp & ~(PG_W | PG_M | 3642 PG_A); 3643 dst_pmap->pm_stats.resident_count++; 3644 } else { 3645 free = NULL; 3646 if (pmap_unwire_pte_hold( dst_pmap, 3647 dstmpte, &free)) { 3648 pmap_invalidate_page(dst_pmap, 3649 addr); 3650 pmap_free_zero_pages(free); 3651 } 3652 } 3653 if (dstmpte->wire_count >= srcmpte->wire_count) 3654 break; 3655 } 3656 addr += PAGE_SIZE; 3657 src_pte++; 3658 } 3659 } 3660 sched_unpin(); 3661 vm_page_unlock_queues(); 3662 PMAP_UNLOCK(src_pmap); 3663 PMAP_UNLOCK(dst_pmap); 3664} 3665 3666static __inline void 3667pagezero(void *page) 3668{ 3669#if defined(I686_CPU) 3670 if (cpu_class == CPUCLASS_686) { 3671#if defined(CPU_ENABLE_SSE) 3672 if (cpu_feature & CPUID_SSE2) 3673 sse2_pagezero(page); 3674 else 3675#endif 3676 i686_pagezero(page); 3677 } else 3678#endif 3679 bzero(page, PAGE_SIZE); 3680} 3681 3682/* 3683 * pmap_zero_page zeros the specified hardware page by mapping 3684 * the page into KVM and using bzero to clear its contents. 3685 */ 3686void 3687pmap_zero_page(vm_page_t m) 3688{ 3689 struct sysmaps *sysmaps; 3690 3691 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)]; 3692 mtx_lock(&sysmaps->lock); 3693 if (*sysmaps->CMAP2) 3694 panic("pmap_zero_page: CMAP2 busy"); 3695 sched_pin(); 3696 *sysmaps->CMAP2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M; 3697 invlcaddr(sysmaps->CADDR2); 3698 pagezero(sysmaps->CADDR2); 3699 *sysmaps->CMAP2 = 0; 3700 sched_unpin(); 3701 mtx_unlock(&sysmaps->lock); 3702} 3703 3704/* 3705 * pmap_zero_page_area zeros the specified hardware page by mapping 3706 * the page into KVM and using bzero to clear its contents. 3707 * 3708 * off and size may not cover an area beyond a single hardware page. 3709 */ 3710void 3711pmap_zero_page_area(vm_page_t m, int off, int size) 3712{ 3713 struct sysmaps *sysmaps; 3714 3715 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)]; 3716 mtx_lock(&sysmaps->lock); 3717 if (*sysmaps->CMAP2) 3718 panic("pmap_zero_page: CMAP2 busy"); 3719 sched_pin(); 3720 *sysmaps->CMAP2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M; 3721 invlcaddr(sysmaps->CADDR2); 3722 if (off == 0 && size == PAGE_SIZE) 3723 pagezero(sysmaps->CADDR2); 3724 else 3725 bzero((char *)sysmaps->CADDR2 + off, size); 3726 *sysmaps->CMAP2 = 0; 3727 sched_unpin(); 3728 mtx_unlock(&sysmaps->lock); 3729} 3730 3731/* 3732 * pmap_zero_page_idle zeros the specified hardware page by mapping 3733 * the page into KVM and using bzero to clear its contents. This 3734 * is intended to be called from the vm_pagezero process only and 3735 * outside of Giant. 3736 */ 3737void 3738pmap_zero_page_idle(vm_page_t m) 3739{ 3740 3741 if (*CMAP3) 3742 panic("pmap_zero_page: CMAP3 busy"); 3743 sched_pin(); 3744 *CMAP3 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M; 3745 invlcaddr(CADDR3); 3746 pagezero(CADDR3); 3747 *CMAP3 = 0; 3748 sched_unpin(); 3749} 3750 3751/* 3752 * pmap_copy_page copies the specified (machine independent) 3753 * page by mapping the page into virtual memory and using 3754 * bcopy to copy the page, one machine dependent page at a 3755 * time. 3756 */ 3757void 3758pmap_copy_page(vm_page_t src, vm_page_t dst) 3759{ 3760 struct sysmaps *sysmaps; 3761 3762 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)]; 3763 mtx_lock(&sysmaps->lock); 3764 if (*sysmaps->CMAP1) 3765 panic("pmap_copy_page: CMAP1 busy"); 3766 if (*sysmaps->CMAP2) 3767 panic("pmap_copy_page: CMAP2 busy"); 3768 sched_pin(); 3769 invlpg((u_int)sysmaps->CADDR1); 3770 invlpg((u_int)sysmaps->CADDR2); 3771 *sysmaps->CMAP1 = PG_V | VM_PAGE_TO_PHYS(src) | PG_A; 3772 *sysmaps->CMAP2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(dst) | PG_A | PG_M; 3773 bcopy(sysmaps->CADDR1, sysmaps->CADDR2, PAGE_SIZE); 3774 *sysmaps->CMAP1 = 0; 3775 *sysmaps->CMAP2 = 0; 3776 sched_unpin(); 3777 mtx_unlock(&sysmaps->lock); 3778} 3779 3780/* 3781 * Returns true if the pmap's pv is one of the first 3782 * 16 pvs linked to from this page. This count may 3783 * be changed upwards or downwards in the future; it 3784 * is only necessary that true be returned for a small 3785 * subset of pmaps for proper page aging. 3786 */ 3787boolean_t 3788pmap_page_exists_quick(pmap_t pmap, vm_page_t m) 3789{ 3790 struct md_page *pvh; 3791 pv_entry_t pv; 3792 int loops = 0; 3793 3794 if (m->flags & PG_FICTITIOUS) 3795 return FALSE; 3796 3797 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 3798 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 3799 if (PV_PMAP(pv) == pmap) { 3800 return TRUE; 3801 } 3802 loops++; 3803 if (loops >= 16) 3804 break; 3805 } 3806 if (loops < 16) { 3807 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 3808 TAILQ_FOREACH(pv, &pvh->pv_list, pv_list) { 3809 if (PV_PMAP(pv) == pmap) 3810 return (TRUE); 3811 loops++; 3812 if (loops >= 16) 3813 break; 3814 } 3815 } 3816 return (FALSE); 3817} 3818 3819/* 3820 * pmap_page_wired_mappings: 3821 * 3822 * Return the number of managed mappings to the given physical page 3823 * that are wired. 3824 */ 3825int 3826pmap_page_wired_mappings(vm_page_t m) 3827{ 3828 int count; 3829 3830 count = 0; 3831 if ((m->flags & PG_FICTITIOUS) != 0) 3832 return (count); 3833 count = pmap_pvh_wired_mappings(&m->md, count); 3834 return (pmap_pvh_wired_mappings(pa_to_pvh(VM_PAGE_TO_PHYS(m)), count)); 3835} 3836 3837/* 3838 * pmap_pvh_wired_mappings: 3839 * 3840 * Return the updated number "count" of managed mappings that are wired. 3841 */ 3842static int 3843pmap_pvh_wired_mappings(struct md_page *pvh, int count) 3844{ 3845 pmap_t pmap; 3846 pt_entry_t *pte; 3847 pv_entry_t pv; 3848 3849 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 3850 sched_pin(); 3851 TAILQ_FOREACH(pv, &pvh->pv_list, pv_list) { 3852 pmap = PV_PMAP(pv); 3853 PMAP_LOCK(pmap); 3854 pte = pmap_pte_quick(pmap, pv->pv_va); 3855 if ((*pte & PG_W) != 0) 3856 count++; 3857 PMAP_UNLOCK(pmap); 3858 } 3859 sched_unpin(); 3860 return (count); 3861} 3862 3863/* 3864 * Returns TRUE if the given page is mapped individually or as part of 3865 * a 4mpage. Otherwise, returns FALSE. 3866 */ 3867boolean_t 3868pmap_page_is_mapped(vm_page_t m) 3869{ 3870 struct md_page *pvh; 3871 3872 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0) 3873 return (FALSE); 3874 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 3875 if (TAILQ_EMPTY(&m->md.pv_list)) { 3876 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 3877 return (!TAILQ_EMPTY(&pvh->pv_list)); 3878 } else 3879 return (TRUE); 3880} 3881 3882/* 3883 * Remove all pages from specified address space 3884 * this aids process exit speeds. Also, this code 3885 * is special cased for current process only, but 3886 * can have the more generic (and slightly slower) 3887 * mode enabled. This is much faster than pmap_remove 3888 * in the case of running down an entire address space. 3889 */ 3890void 3891pmap_remove_pages(pmap_t pmap) 3892{ 3893 pt_entry_t *pte, tpte; 3894 vm_page_t free = NULL; 3895 vm_page_t m, mpte, mt; 3896 pv_entry_t pv; 3897 struct md_page *pvh; 3898 struct pv_chunk *pc, *npc; 3899 int field, idx; 3900 int32_t bit; 3901 uint32_t inuse, bitmask; 3902 int allfree; 3903 3904 if (pmap != vmspace_pmap(curthread->td_proc->p_vmspace)) { 3905 printf("warning: pmap_remove_pages called with non-current pmap\n"); 3906 return; 3907 } 3908 vm_page_lock_queues(); 3909 PMAP_LOCK(pmap); 3910 sched_pin(); 3911 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) { 3912 allfree = 1; 3913 for (field = 0; field < _NPCM; field++) { 3914 inuse = (~(pc->pc_map[field])) & pc_freemask[field]; 3915 while (inuse != 0) { 3916 bit = bsfl(inuse); 3917 bitmask = 1UL << bit; 3918 idx = field * 32 + bit; 3919 pv = &pc->pc_pventry[idx]; 3920 inuse &= ~bitmask; 3921 3922 pte = pmap_pde(pmap, pv->pv_va); 3923 tpte = *pte; 3924 if ((tpte & PG_PS) == 0) { 3925 pte = vtopte(pv->pv_va); 3926 tpte = *pte & ~PG_PTE_PAT; 3927 } 3928 3929 if (tpte == 0) { 3930 printf( 3931 "TPTE at %p IS ZERO @ VA %08x\n", 3932 pte, pv->pv_va); 3933 panic("bad pte"); 3934 } 3935 3936/* 3937 * We cannot remove wired pages from a process' mapping at this time 3938 */ 3939 if (tpte & PG_W) { 3940 allfree = 0; 3941 continue; 3942 } 3943 3944 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME); 3945 KASSERT(m->phys_addr == (tpte & PG_FRAME), 3946 ("vm_page_t %p phys_addr mismatch %016jx %016jx", 3947 m, (uintmax_t)m->phys_addr, 3948 (uintmax_t)tpte)); 3949 3950 KASSERT(m < &vm_page_array[vm_page_array_size], 3951 ("pmap_remove_pages: bad tpte %#jx", 3952 (uintmax_t)tpte)); 3953 3954 pte_clear(pte); 3955 3956 /* 3957 * Update the vm_page_t clean/reference bits. 3958 */ 3959 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) { 3960 if ((tpte & PG_PS) != 0) { 3961 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++) 3962 vm_page_dirty(mt); 3963 } else 3964 vm_page_dirty(m); 3965 } 3966 3967 /* Mark free */ 3968 PV_STAT(pv_entry_frees++); 3969 PV_STAT(pv_entry_spare++); 3970 pv_entry_count--; 3971 pc->pc_map[field] |= bitmask; 3972 if ((tpte & PG_PS) != 0) { 3973 pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE; 3974 pvh = pa_to_pvh(tpte & PG_PS_FRAME); 3975 TAILQ_REMOVE(&pvh->pv_list, pv, pv_list); 3976 if (TAILQ_EMPTY(&pvh->pv_list)) { 3977 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++) 3978 if (TAILQ_EMPTY(&mt->md.pv_list)) 3979 vm_page_flag_clear(mt, PG_WRITEABLE); 3980 } 3981 mpte = pmap_lookup_pt_page(pmap, pv->pv_va); 3982 if (mpte != NULL) { 3983 pmap_remove_pt_page(pmap, mpte); 3984 KASSERT(mpte->wire_count == NPTEPG, 3985 ("pmap_remove_pages: pte page wire count error")); 3986 mpte->wire_count = 0; 3987 pmap_add_delayed_free_list(mpte, &free, FALSE); 3988 atomic_subtract_int(&cnt.v_wire_count, 1); 3989 } 3990 } else { 3991 pmap->pm_stats.resident_count--; 3992 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list); 3993 if (TAILQ_EMPTY(&m->md.pv_list)) { 3994 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 3995 if (TAILQ_EMPTY(&pvh->pv_list)) 3996 vm_page_flag_clear(m, PG_WRITEABLE); 3997 } 3998 pmap_unuse_pt(pmap, pv->pv_va, &free); 3999 } 4000 } 4001 } 4002 if (allfree) { 4003 PV_STAT(pv_entry_spare -= _NPCPV); 4004 PV_STAT(pc_chunk_count--); 4005 PV_STAT(pc_chunk_frees++); 4006 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 4007 m = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc)); 4008 pmap_qremove((vm_offset_t)pc, 1); 4009 vm_page_unwire(m, 0); 4010 vm_page_free(m); 4011 pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc); 4012 } 4013 } 4014 sched_unpin(); 4015 pmap_invalidate_all(pmap); 4016 vm_page_unlock_queues(); 4017 PMAP_UNLOCK(pmap); 4018 pmap_free_zero_pages(free); 4019} 4020 4021/* 4022 * pmap_is_modified: 4023 * 4024 * Return whether or not the specified physical page was modified 4025 * in any physical maps. 4026 */ 4027boolean_t 4028pmap_is_modified(vm_page_t m) 4029{ 4030 4031 if (m->flags & PG_FICTITIOUS) 4032 return (FALSE); 4033 if (pmap_is_modified_pvh(&m->md)) 4034 return (TRUE); 4035 return (pmap_is_modified_pvh(pa_to_pvh(VM_PAGE_TO_PHYS(m)))); 4036} 4037 4038/* 4039 * Returns TRUE if any of the given mappings were used to modify 4040 * physical memory. Otherwise, returns FALSE. Both page and 2mpage 4041 * mappings are supported. 4042 */ 4043static boolean_t 4044pmap_is_modified_pvh(struct md_page *pvh) 4045{ 4046 pv_entry_t pv; 4047 pt_entry_t *pte; 4048 pmap_t pmap; 4049 boolean_t rv; 4050 4051 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 4052 rv = FALSE; 4053 sched_pin(); 4054 TAILQ_FOREACH(pv, &pvh->pv_list, pv_list) { 4055 pmap = PV_PMAP(pv); 4056 PMAP_LOCK(pmap); 4057 pte = pmap_pte_quick(pmap, pv->pv_va); 4058 rv = (*pte & (PG_M | PG_RW)) == (PG_M | PG_RW); 4059 PMAP_UNLOCK(pmap); 4060 if (rv) 4061 break; 4062 } 4063 sched_unpin(); 4064 return (rv); 4065} 4066 4067/* 4068 * pmap_is_prefaultable: 4069 * 4070 * Return whether or not the specified virtual address is elgible 4071 * for prefault. 4072 */ 4073boolean_t 4074pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr) 4075{ 4076 pd_entry_t *pde; 4077 pt_entry_t *pte; 4078 boolean_t rv; 4079 4080 rv = FALSE; 4081 PMAP_LOCK(pmap); 4082 pde = pmap_pde(pmap, addr); 4083 if (*pde != 0 && (*pde & PG_PS) == 0) { 4084 pte = vtopte(addr); 4085 rv = *pte == 0; 4086 } 4087 PMAP_UNLOCK(pmap); 4088 return (rv); 4089} 4090 4091/* 4092 * Clear the write and modified bits in each of the given page's mappings. 4093 */ 4094void 4095pmap_remove_write(vm_page_t m) 4096{ 4097 struct md_page *pvh; 4098 pv_entry_t next_pv, pv; 4099 pmap_t pmap; 4100 pd_entry_t *pde; 4101 pt_entry_t oldpte, *pte; 4102 vm_offset_t va; 4103 4104 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 4105 if ((m->flags & PG_FICTITIOUS) != 0 || 4106 (m->flags & PG_WRITEABLE) == 0) 4107 return; 4108 sched_pin(); 4109 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 4110 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_list, next_pv) { 4111 va = pv->pv_va; 4112 pmap = PV_PMAP(pv); 4113 PMAP_LOCK(pmap); 4114 pde = pmap_pde(pmap, va); 4115 if ((*pde & PG_RW) != 0) 4116 (void)pmap_demote_pde(pmap, pde, va); 4117 PMAP_UNLOCK(pmap); 4118 } 4119 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 4120 pmap = PV_PMAP(pv); 4121 PMAP_LOCK(pmap); 4122 pde = pmap_pde(pmap, pv->pv_va); 4123 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_write: found" 4124 " a 4mpage in page %p's pv list", m)); 4125 pte = pmap_pte_quick(pmap, pv->pv_va); 4126retry: 4127 oldpte = *pte; 4128 if ((oldpte & PG_RW) != 0) { 4129 /* 4130 * Regardless of whether a pte is 32 or 64 bits 4131 * in size, PG_RW and PG_M are among the least 4132 * significant 32 bits. 4133 */ 4134 if (!atomic_cmpset_int((u_int *)pte, oldpte, 4135 oldpte & ~(PG_RW | PG_M))) 4136 goto retry; 4137 if ((oldpte & PG_M) != 0) 4138 vm_page_dirty(m); 4139 pmap_invalidate_page(pmap, pv->pv_va); 4140 } 4141 PMAP_UNLOCK(pmap); 4142 } 4143 vm_page_flag_clear(m, PG_WRITEABLE); 4144 sched_unpin(); 4145} 4146 4147/* 4148 * pmap_ts_referenced: 4149 * 4150 * Return a count of reference bits for a page, clearing those bits. 4151 * It is not necessary for every reference bit to be cleared, but it 4152 * is necessary that 0 only be returned when there are truly no 4153 * reference bits set. 4154 * 4155 * XXX: The exact number of bits to check and clear is a matter that 4156 * should be tested and standardized at some point in the future for 4157 * optimal aging of shared pages. 4158 */ 4159int 4160pmap_ts_referenced(vm_page_t m) 4161{ 4162 struct md_page *pvh; 4163 pv_entry_t pv, pvf, pvn; 4164 pmap_t pmap; 4165 pd_entry_t oldpde, *pde; 4166 pt_entry_t *pte; 4167 vm_offset_t va; 4168 int rtval = 0; 4169 4170 if (m->flags & PG_FICTITIOUS) 4171 return (rtval); 4172 sched_pin(); 4173 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 4174 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 4175 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_list, pvn) { 4176 va = pv->pv_va; 4177 pmap = PV_PMAP(pv); 4178 PMAP_LOCK(pmap); 4179 pde = pmap_pde(pmap, va); 4180 oldpde = *pde; 4181 if ((oldpde & PG_A) != 0) { 4182 if (pmap_demote_pde(pmap, pde, va)) { 4183 if ((oldpde & PG_W) == 0) { 4184 /* 4185 * Remove the mapping to a single page 4186 * so that a subsequent access may 4187 * repromote. Since the underlying 4188 * page table page is fully populated, 4189 * this removal never frees a page 4190 * table page. 4191 */ 4192 va += VM_PAGE_TO_PHYS(m) - (oldpde & 4193 PG_PS_FRAME); 4194 pmap_remove_page(pmap, va, NULL); 4195 rtval++; 4196 if (rtval > 4) { 4197 PMAP_UNLOCK(pmap); 4198 return (rtval); 4199 } 4200 } 4201 } 4202 } 4203 PMAP_UNLOCK(pmap); 4204 } 4205 if ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) { 4206 pvf = pv; 4207 do { 4208 pvn = TAILQ_NEXT(pv, pv_list); 4209 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list); 4210 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list); 4211 pmap = PV_PMAP(pv); 4212 PMAP_LOCK(pmap); 4213 pde = pmap_pde(pmap, pv->pv_va); 4214 KASSERT((*pde & PG_PS) == 0, ("pmap_ts_referenced:" 4215 " found a 4mpage in page %p's pv list", m)); 4216 pte = pmap_pte_quick(pmap, pv->pv_va); 4217 if ((*pte & PG_A) != 0) { 4218 atomic_clear_int((u_int *)pte, PG_A); 4219 pmap_invalidate_page(pmap, pv->pv_va); 4220 rtval++; 4221 if (rtval > 4) 4222 pvn = NULL; 4223 } 4224 PMAP_UNLOCK(pmap); 4225 } while ((pv = pvn) != NULL && pv != pvf); 4226 } 4227 sched_unpin(); 4228 return (rtval); 4229} 4230 4231/* 4232 * Clear the modify bits on the specified physical page. 4233 */ 4234void 4235pmap_clear_modify(vm_page_t m) 4236{ 4237 struct md_page *pvh; 4238 pv_entry_t next_pv, pv; 4239 pmap_t pmap; 4240 pd_entry_t oldpde, *pde; 4241 pt_entry_t oldpte, *pte; 4242 vm_offset_t va; 4243 4244 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 4245 if ((m->flags & PG_FICTITIOUS) != 0) 4246 return; 4247 sched_pin(); 4248 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 4249 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_list, next_pv) { 4250 va = pv->pv_va; 4251 pmap = PV_PMAP(pv); 4252 PMAP_LOCK(pmap); 4253 pde = pmap_pde(pmap, va); 4254 oldpde = *pde; 4255 if ((oldpde & PG_RW) != 0) { 4256 if (pmap_demote_pde(pmap, pde, va)) { 4257 if ((oldpde & PG_W) == 0) { 4258 /* 4259 * Write protect the mapping to a 4260 * single page so that a subsequent 4261 * write access may repromote. 4262 */ 4263 va += VM_PAGE_TO_PHYS(m) - (oldpde & 4264 PG_PS_FRAME); 4265 pte = pmap_pte_quick(pmap, va); 4266 oldpte = *pte; 4267 if ((oldpte & PG_V) != 0) { 4268 /* 4269 * Regardless of whether a pte is 32 or 64 bits 4270 * in size, PG_RW and PG_M are among the least 4271 * significant 32 bits. 4272 */ 4273 while (!atomic_cmpset_int((u_int *)pte, 4274 oldpte, 4275 oldpte & ~(PG_M | PG_RW))) 4276 oldpte = *pte; 4277 vm_page_dirty(m); 4278 pmap_invalidate_page(pmap, va); 4279 } 4280 } 4281 } 4282 } 4283 PMAP_UNLOCK(pmap); 4284 } 4285 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 4286 pmap = PV_PMAP(pv); 4287 PMAP_LOCK(pmap); 4288 pde = pmap_pde(pmap, pv->pv_va); 4289 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_modify: found" 4290 " a 4mpage in page %p's pv list", m)); 4291 pte = pmap_pte_quick(pmap, pv->pv_va); 4292 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) { 4293 /* 4294 * Regardless of whether a pte is 32 or 64 bits 4295 * in size, PG_M is among the least significant 4296 * 32 bits. 4297 */ 4298 atomic_clear_int((u_int *)pte, PG_M); 4299 pmap_invalidate_page(pmap, pv->pv_va); 4300 } 4301 PMAP_UNLOCK(pmap); 4302 } 4303 sched_unpin(); 4304} 4305 4306/* 4307 * pmap_clear_reference: 4308 * 4309 * Clear the reference bit on the specified physical page. 4310 */ 4311void 4312pmap_clear_reference(vm_page_t m) 4313{ 4314 struct md_page *pvh; 4315 pv_entry_t next_pv, pv; 4316 pmap_t pmap; 4317 pd_entry_t oldpde, *pde; 4318 pt_entry_t *pte; 4319 vm_offset_t va; 4320 4321 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 4322 if ((m->flags & PG_FICTITIOUS) != 0) 4323 return; 4324 sched_pin(); 4325 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 4326 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_list, next_pv) { 4327 va = pv->pv_va; 4328 pmap = PV_PMAP(pv); 4329 PMAP_LOCK(pmap); 4330 pde = pmap_pde(pmap, va); 4331 oldpde = *pde; 4332 if ((oldpde & PG_A) != 0) { 4333 if (pmap_demote_pde(pmap, pde, va)) { 4334 /* 4335 * Remove the mapping to a single page so 4336 * that a subsequent access may repromote. 4337 * Since the underlying page table page is 4338 * fully populated, this removal never frees 4339 * a page table page. 4340 */ 4341 va += VM_PAGE_TO_PHYS(m) - (oldpde & 4342 PG_PS_FRAME); 4343 pmap_remove_page(pmap, va, NULL); 4344 } 4345 } 4346 PMAP_UNLOCK(pmap); 4347 } 4348 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 4349 pmap = PV_PMAP(pv); 4350 PMAP_LOCK(pmap); 4351 pde = pmap_pde(pmap, pv->pv_va); 4352 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_reference: found" 4353 " a 4mpage in page %p's pv list", m)); 4354 pte = pmap_pte_quick(pmap, pv->pv_va); 4355 if ((*pte & PG_A) != 0) { 4356 /* 4357 * Regardless of whether a pte is 32 or 64 bits 4358 * in size, PG_A is among the least significant 4359 * 32 bits. 4360 */ 4361 atomic_clear_int((u_int *)pte, PG_A); 4362 pmap_invalidate_page(pmap, pv->pv_va); 4363 } 4364 PMAP_UNLOCK(pmap); 4365 } 4366 sched_unpin(); 4367} 4368 4369/* 4370 * Miscellaneous support routines follow 4371 */ 4372 4373/* 4374 * Map a set of physical memory pages into the kernel virtual 4375 * address space. Return a pointer to where it is mapped. This 4376 * routine is intended to be used for mapping device memory, 4377 * NOT real memory. 4378 */ 4379void * 4380pmap_mapdev_attr(vm_paddr_t pa, vm_size_t size, int mode) 4381{ 4382 vm_offset_t va, tmpva, offset; 4383 4384 offset = pa & PAGE_MASK; 4385 size = roundup(offset + size, PAGE_SIZE); 4386 pa = pa & PG_FRAME; 4387 4388 if (pa < KERNLOAD && pa + size <= KERNLOAD) 4389 va = KERNBASE + pa; 4390 else 4391 va = kmem_alloc_nofault(kernel_map, size); 4392 if (!va) 4393 panic("pmap_mapdev: Couldn't alloc kernel virtual memory"); 4394 4395 for (tmpva = va; size > 0; ) { 4396 pmap_kenter_attr(tmpva, pa, mode); 4397 size -= PAGE_SIZE; 4398 tmpva += PAGE_SIZE; 4399 pa += PAGE_SIZE; 4400 } 4401 pmap_invalidate_range(kernel_pmap, va, tmpva); 4402 pmap_invalidate_cache(); 4403 return ((void *)(va + offset)); 4404} 4405 4406void * 4407pmap_mapdev(vm_paddr_t pa, vm_size_t size) 4408{ 4409 4410 return (pmap_mapdev_attr(pa, size, PAT_UNCACHEABLE)); 4411} 4412 4413void * 4414pmap_mapbios(vm_paddr_t pa, vm_size_t size) 4415{ 4416 4417 return (pmap_mapdev_attr(pa, size, PAT_WRITE_BACK)); 4418} 4419 4420void 4421pmap_unmapdev(vm_offset_t va, vm_size_t size) 4422{ 4423 vm_offset_t base, offset, tmpva; 4424 4425 if (va >= KERNBASE && va + size <= KERNBASE + KERNLOAD) 4426 return; 4427 base = trunc_page(va); 4428 offset = va & PAGE_MASK; 4429 size = roundup(offset + size, PAGE_SIZE); 4430 for (tmpva = base; tmpva < (base + size); tmpva += PAGE_SIZE) 4431 pmap_kremove(tmpva); 4432 pmap_invalidate_range(kernel_pmap, va, tmpva); 4433 kmem_free(kernel_map, base, size); 4434} 4435 4436int 4437pmap_change_attr(vm_offset_t va, vm_size_t size, int mode) 4438{ 4439 vm_offset_t base, offset, tmpva; 4440 pt_entry_t *pte; 4441 u_int opte, npte; 4442 pd_entry_t *pde; 4443 4444 base = trunc_page(va); 4445 offset = va & PAGE_MASK; 4446 size = roundup(offset + size, PAGE_SIZE); 4447 4448 /* 4449 * Only supported on kernel virtual addresses above the recursive map. 4450 */ 4451 if (base < VM_MIN_KERNEL_ADDRESS) 4452 return (EINVAL); 4453 4454 /* 4MB pages and pages that aren't mapped aren't supported. */ 4455 for (tmpva = base; tmpva < (base + size); tmpva += PAGE_SIZE) { 4456 pde = pmap_pde(kernel_pmap, tmpva); 4457 if (*pde & PG_PS) 4458 return (EINVAL); 4459 if (*pde == 0) 4460 return (EINVAL); 4461 pte = vtopte(tmpva); 4462 if (*pte == 0) 4463 return (EINVAL); 4464 } 4465 4466 /* 4467 * Ok, all the pages exist and are 4k, so run through them updating 4468 * their cache mode. 4469 */ 4470 for (tmpva = base; size > 0; ) { 4471 pte = vtopte(tmpva); 4472 4473 /* 4474 * The cache mode bits are all in the low 32-bits of the 4475 * PTE, so we can just spin on updating the low 32-bits. 4476 */ 4477 do { 4478 opte = *(u_int *)pte; 4479 npte = opte & ~(PG_PTE_PAT | PG_NC_PCD | PG_NC_PWT); 4480 npte |= pmap_cache_bits(mode, 0); 4481 } while (npte != opte && 4482 !atomic_cmpset_int((u_int *)pte, opte, npte)); 4483 tmpva += PAGE_SIZE; 4484 size -= PAGE_SIZE; 4485 } 4486 4487 /* 4488 * Flush CPU caches to make sure any data isn't cached that shouldn't 4489 * be, etc. 4490 */ 4491 pmap_invalidate_range(kernel_pmap, base, tmpva); 4492 pmap_invalidate_cache(); 4493 return (0); 4494} 4495 4496/* 4497 * perform the pmap work for mincore 4498 */ 4499int 4500pmap_mincore(pmap_t pmap, vm_offset_t addr) 4501{ 4502 pd_entry_t *pdep; 4503 pt_entry_t *ptep, pte; 4504 vm_paddr_t pa; 4505 vm_page_t m; 4506 int val = 0; 4507 4508 PMAP_LOCK(pmap); 4509 pdep = pmap_pde(pmap, addr); 4510 if (*pdep != 0) { 4511 if (*pdep & PG_PS) { 4512 pte = *pdep; 4513 val = MINCORE_SUPER; 4514 /* Compute the physical address of the 4KB page. */ 4515 pa = ((*pdep & PG_PS_FRAME) | (addr & PDRMASK)) & 4516 PG_FRAME; 4517 } else { 4518 ptep = pmap_pte(pmap, addr); 4519 pte = *ptep; 4520 pmap_pte_release(ptep); 4521 pa = pte & PG_FRAME; 4522 } 4523 } else { 4524 pte = 0; 4525 pa = 0; 4526 } 4527 PMAP_UNLOCK(pmap); 4528 4529 if (pte != 0) { 4530 val |= MINCORE_INCORE; 4531 if ((pte & PG_MANAGED) == 0) 4532 return val; 4533 4534 m = PHYS_TO_VM_PAGE(pa); 4535 4536 /* 4537 * Modified by us 4538 */ 4539 if ((pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) 4540 val |= MINCORE_MODIFIED|MINCORE_MODIFIED_OTHER; 4541 else { 4542 /* 4543 * Modified by someone else 4544 */ 4545 vm_page_lock_queues(); 4546 if (m->dirty || pmap_is_modified(m)) 4547 val |= MINCORE_MODIFIED_OTHER; 4548 vm_page_unlock_queues(); 4549 } 4550 /* 4551 * Referenced by us 4552 */ 4553 if (pte & PG_A) 4554 val |= MINCORE_REFERENCED|MINCORE_REFERENCED_OTHER; 4555 else { 4556 /* 4557 * Referenced by someone else 4558 */ 4559 vm_page_lock_queues(); 4560 if ((m->flags & PG_REFERENCED) || 4561 pmap_ts_referenced(m)) { 4562 val |= MINCORE_REFERENCED_OTHER; 4563 vm_page_flag_set(m, PG_REFERENCED); 4564 } 4565 vm_page_unlock_queues(); 4566 } 4567 } 4568 return val; 4569} 4570 4571void 4572pmap_activate(struct thread *td) 4573{ 4574 pmap_t pmap, oldpmap; 4575 u_int32_t cr3; 4576 4577 critical_enter(); 4578 pmap = vmspace_pmap(td->td_proc->p_vmspace); 4579 oldpmap = PCPU_GET(curpmap); 4580#if defined(SMP) 4581 atomic_clear_int(&oldpmap->pm_active, PCPU_GET(cpumask)); 4582 atomic_set_int(&pmap->pm_active, PCPU_GET(cpumask)); 4583#else 4584 oldpmap->pm_active &= ~1; 4585 pmap->pm_active |= 1; 4586#endif 4587#ifdef PAE 4588 cr3 = vtophys(pmap->pm_pdpt); 4589#else 4590 cr3 = vtophys(pmap->pm_pdir); 4591#endif 4592 /* 4593 * pmap_activate is for the current thread on the current cpu 4594 */ 4595 td->td_pcb->pcb_cr3 = cr3; 4596 load_cr3(cr3); 4597 PCPU_SET(curpmap, pmap); 4598 critical_exit(); 4599} 4600 4601/* 4602 * Increase the starting virtual address of the given mapping if a 4603 * different alignment might result in more superpage mappings. 4604 */ 4605void 4606pmap_align_superpage(vm_object_t object, vm_ooffset_t offset, 4607 vm_offset_t *addr, vm_size_t size) 4608{ 4609 vm_offset_t superpage_offset; 4610 4611 if (size < NBPDR) 4612 return; 4613 if (object != NULL && (object->flags & OBJ_COLORED) != 0) 4614 offset += ptoa(object->pg_color); 4615 superpage_offset = offset & PDRMASK; 4616 if (size - ((NBPDR - superpage_offset) & PDRMASK) < NBPDR || 4617 (*addr & PDRMASK) == superpage_offset) 4618 return; 4619 if ((*addr & PDRMASK) < superpage_offset) 4620 *addr = (*addr & ~PDRMASK) + superpage_offset; 4621 else 4622 *addr = ((*addr + PDRMASK) & ~PDRMASK) + superpage_offset; 4623} 4624 4625 4626#if defined(PMAP_DEBUG) 4627pmap_pid_dump(int pid) 4628{ 4629 pmap_t pmap; 4630 struct proc *p; 4631 int npte = 0; 4632 int index; 4633 4634 sx_slock(&allproc_lock); 4635 FOREACH_PROC_IN_SYSTEM(p) { 4636 if (p->p_pid != pid) 4637 continue; 4638 4639 if (p->p_vmspace) { 4640 int i,j; 4641 index = 0; 4642 pmap = vmspace_pmap(p->p_vmspace); 4643 for (i = 0; i < NPDEPTD; i++) { 4644 pd_entry_t *pde; 4645 pt_entry_t *pte; 4646 vm_offset_t base = i << PDRSHIFT; 4647 4648 pde = &pmap->pm_pdir[i]; 4649 if (pde && pmap_pde_v(pde)) { 4650 for (j = 0; j < NPTEPG; j++) { 4651 vm_offset_t va = base + (j << PAGE_SHIFT); 4652 if (va >= (vm_offset_t) VM_MIN_KERNEL_ADDRESS) { 4653 if (index) { 4654 index = 0; 4655 printf("\n"); 4656 } 4657 sx_sunlock(&allproc_lock); 4658 return npte; 4659 } 4660 pte = pmap_pte(pmap, va); 4661 if (pte && pmap_pte_v(pte)) { 4662 pt_entry_t pa; 4663 vm_page_t m; 4664 pa = *pte; 4665 m = PHYS_TO_VM_PAGE(pa & PG_FRAME); 4666 printf("va: 0x%x, pt: 0x%x, h: %d, w: %d, f: 0x%x", 4667 va, pa, m->hold_count, m->wire_count, m->flags); 4668 npte++; 4669 index++; 4670 if (index >= 2) { 4671 index = 0; 4672 printf("\n"); 4673 } else { 4674 printf(" "); 4675 } 4676 } 4677 } 4678 } 4679 } 4680 } 4681 } 4682 sx_sunlock(&allproc_lock); 4683 return npte; 4684} 4685#endif 4686 4687#if defined(DEBUG) 4688 4689static void pads(pmap_t pm); 4690void pmap_pvdump(vm_offset_t pa); 4691 4692/* print address space of pmap*/ 4693static void 4694pads(pmap_t pm) 4695{ 4696 int i, j; 4697 vm_paddr_t va; 4698 pt_entry_t *ptep; 4699 4700 if (pm == kernel_pmap) 4701 return; 4702 for (i = 0; i < NPDEPTD; i++) 4703 if (pm->pm_pdir[i]) 4704 for (j = 0; j < NPTEPG; j++) { 4705 va = (i << PDRSHIFT) + (j << PAGE_SHIFT); 4706 if (pm == kernel_pmap && va < KERNBASE) 4707 continue; 4708 if (pm != kernel_pmap && va > UPT_MAX_ADDRESS) 4709 continue; 4710 ptep = pmap_pte(pm, va); 4711 if (pmap_pte_v(ptep)) 4712 printf("%x:%x ", va, *ptep); 4713 }; 4714 4715} 4716 4717void 4718pmap_pvdump(vm_paddr_t pa) 4719{ 4720 pv_entry_t pv; 4721 pmap_t pmap; 4722 vm_page_t m; 4723 4724 printf("pa %x", pa); 4725 m = PHYS_TO_VM_PAGE(pa); 4726 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 4727 pmap = PV_PMAP(pv); 4728 printf(" -> pmap %p, va %x", (void *)pmap, pv->pv_va); 4729 pads(pmap); 4730 } 4731 printf(" "); 4732} 4733#endif 4734