pmap.c revision 177684
1/*- 2 * Copyright (c) 1991 Regents of the University of California. 3 * All rights reserved. 4 * Copyright (c) 1994 John S. Dyson 5 * All rights reserved. 6 * Copyright (c) 1994 David Greenman 7 * All rights reserved. 8 * Copyright (c) 2005-2008 Alan L. Cox <alc@cs.rice.edu> 9 * All rights reserved. 10 * 11 * This code is derived from software contributed to Berkeley by 12 * the Systems Programming Group of the University of Utah Computer 13 * Science Department and William Jolitz of UUNET Technologies Inc. 14 * 15 * Redistribution and use in source and binary forms, with or without 16 * modification, are permitted provided that the following conditions 17 * are met: 18 * 1. Redistributions of source code must retain the above copyright 19 * notice, this list of conditions and the following disclaimer. 20 * 2. Redistributions in binary form must reproduce the above copyright 21 * notice, this list of conditions and the following disclaimer in the 22 * documentation and/or other materials provided with the distribution. 23 * 3. All advertising materials mentioning features or use of this software 24 * must display the following acknowledgement: 25 * This product includes software developed by the University of 26 * California, Berkeley and its contributors. 27 * 4. Neither the name of the University nor the names of its contributors 28 * may be used to endorse or promote products derived from this software 29 * without specific prior written permission. 30 * 31 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 32 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 33 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 34 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 35 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 36 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 37 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 38 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 39 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 40 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 41 * SUCH DAMAGE. 42 * 43 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91 44 */ 45/*- 46 * Copyright (c) 2003 Networks Associates Technology, Inc. 47 * All rights reserved. 48 * 49 * This software was developed for the FreeBSD Project by Jake Burkholder, 50 * Safeport Network Services, and Network Associates Laboratories, the 51 * Security Research Division of Network Associates, Inc. under 52 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA 53 * CHATS research program. 54 * 55 * Redistribution and use in source and binary forms, with or without 56 * modification, are permitted provided that the following conditions 57 * are met: 58 * 1. Redistributions of source code must retain the above copyright 59 * notice, this list of conditions and the following disclaimer. 60 * 2. Redistributions in binary form must reproduce the above copyright 61 * notice, this list of conditions and the following disclaimer in the 62 * documentation and/or other materials provided with the distribution. 63 * 64 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 65 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 66 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 67 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 68 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 69 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 70 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 71 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 72 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 73 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 74 * SUCH DAMAGE. 75 */ 76 77#include <sys/cdefs.h> 78__FBSDID("$FreeBSD: head/sys/i386/i386/pmap.c 177684 2008-03-28 08:19:03Z brooks $"); 79 80/* 81 * Manages physical address maps. 82 * 83 * In addition to hardware address maps, this 84 * module is called upon to provide software-use-only 85 * maps which may or may not be stored in the same 86 * form as hardware maps. These pseudo-maps are 87 * used to store intermediate results from copy 88 * operations to and from address spaces. 89 * 90 * Since the information managed by this module is 91 * also stored by the logical address mapping module, 92 * this module may throw away valid virtual-to-physical 93 * mappings at almost any time. However, invalidations 94 * of virtual-to-physical mappings must be done as 95 * requested. 96 * 97 * In order to cope with hardware architectures which 98 * make virtual-to-physical map invalidates expensive, 99 * this module may delay invalidate or reduced protection 100 * operations until such time as they are actually 101 * necessary. This module is given full information as 102 * to which processors are currently using which maps, 103 * and to when physical maps must be made correct. 104 */ 105 106#include "opt_cpu.h" 107#include "opt_pmap.h" 108#include "opt_msgbuf.h" 109#include "opt_smp.h" 110#include "opt_xbox.h" 111 112#include <sys/param.h> 113#include <sys/systm.h> 114#include <sys/kernel.h> 115#include <sys/ktr.h> 116#include <sys/lock.h> 117#include <sys/malloc.h> 118#include <sys/mman.h> 119#include <sys/msgbuf.h> 120#include <sys/mutex.h> 121#include <sys/proc.h> 122#include <sys/sx.h> 123#include <sys/vmmeter.h> 124#include <sys/sched.h> 125#include <sys/sysctl.h> 126#ifdef SMP 127#include <sys/smp.h> 128#endif 129 130#include <vm/vm.h> 131#include <vm/vm_param.h> 132#include <vm/vm_kern.h> 133#include <vm/vm_page.h> 134#include <vm/vm_map.h> 135#include <vm/vm_object.h> 136#include <vm/vm_extern.h> 137#include <vm/vm_pageout.h> 138#include <vm/vm_pager.h> 139#include <vm/vm_reserv.h> 140#include <vm/uma.h> 141 142#include <machine/cpu.h> 143#include <machine/cputypes.h> 144#include <machine/md_var.h> 145#include <machine/pcb.h> 146#include <machine/specialreg.h> 147#ifdef SMP 148#include <machine/smp.h> 149#endif 150 151#ifdef XBOX 152#include <machine/xbox.h> 153#endif 154 155#if !defined(CPU_DISABLE_SSE) && defined(I686_CPU) 156#define CPU_ENABLE_SSE 157#endif 158 159#ifndef PMAP_SHPGPERPROC 160#define PMAP_SHPGPERPROC 200 161#endif 162 163#if !defined(DIAGNOSTIC) 164#define PMAP_INLINE __gnu89_inline 165#else 166#define PMAP_INLINE 167#endif 168 169#define PV_STATS 170#ifdef PV_STATS 171#define PV_STAT(x) do { x ; } while (0) 172#else 173#define PV_STAT(x) do { } while (0) 174#endif 175 176#define pa_index(pa) ((pa) >> PDRSHIFT) 177#define pa_to_pvh(pa) (&pv_table[pa_index(pa)]) 178 179/* 180 * Get PDEs and PTEs for user/kernel address space 181 */ 182#define pmap_pde(m, v) (&((m)->pm_pdir[(vm_offset_t)(v) >> PDRSHIFT])) 183#define pdir_pde(m, v) (m[(vm_offset_t)(v) >> PDRSHIFT]) 184 185#define pmap_pde_v(pte) ((*(int *)pte & PG_V) != 0) 186#define pmap_pte_w(pte) ((*(int *)pte & PG_W) != 0) 187#define pmap_pte_m(pte) ((*(int *)pte & PG_M) != 0) 188#define pmap_pte_u(pte) ((*(int *)pte & PG_A) != 0) 189#define pmap_pte_v(pte) ((*(int *)pte & PG_V) != 0) 190 191#define pmap_pte_set_w(pte, v) ((v) ? atomic_set_int((u_int *)(pte), PG_W) : \ 192 atomic_clear_int((u_int *)(pte), PG_W)) 193#define pmap_pte_set_prot(pte, v) ((*(int *)pte &= ~PG_PROT), (*(int *)pte |= (v))) 194 195struct pmap kernel_pmap_store; 196LIST_HEAD(pmaplist, pmap); 197static struct pmaplist allpmaps; 198static struct mtx allpmaps_lock; 199 200vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */ 201vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */ 202int pgeflag = 0; /* PG_G or-in */ 203int pseflag = 0; /* PG_PS or-in */ 204 205static int nkpt; 206vm_offset_t kernel_vm_end; 207extern u_int32_t KERNend; 208 209#ifdef PAE 210pt_entry_t pg_nx; 211static uma_zone_t pdptzone; 212#endif 213 214SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD, 0, "VM/pmap parameters"); 215 216static int pg_ps_enabled; 217SYSCTL_INT(_vm_pmap, OID_AUTO, pg_ps_enabled, CTLFLAG_RD, &pg_ps_enabled, 0, 218 "Are large page mappings enabled?"); 219 220/* 221 * Data for the pv entry allocation mechanism 222 */ 223static int pv_entry_count = 0, pv_entry_max = 0, pv_entry_high_water = 0; 224static struct md_page *pv_table; 225static int shpgperproc = PMAP_SHPGPERPROC; 226 227struct pv_chunk *pv_chunkbase; /* KVA block for pv_chunks */ 228int pv_maxchunks; /* How many chunks we have KVA for */ 229vm_offset_t pv_vafree; /* freelist stored in the PTE */ 230 231/* 232 * All those kernel PT submaps that BSD is so fond of 233 */ 234struct sysmaps { 235 struct mtx lock; 236 pt_entry_t *CMAP1; 237 pt_entry_t *CMAP2; 238 caddr_t CADDR1; 239 caddr_t CADDR2; 240}; 241static struct sysmaps sysmaps_pcpu[MAXCPU]; 242pt_entry_t *CMAP1 = 0; 243static pt_entry_t *CMAP3; 244caddr_t CADDR1 = 0, ptvmmap = 0; 245static caddr_t CADDR3; 246struct msgbuf *msgbufp = 0; 247 248/* 249 * Crashdump maps. 250 */ 251static caddr_t crashdumpmap; 252 253static pt_entry_t *PMAP1 = 0, *PMAP2; 254static pt_entry_t *PADDR1 = 0, *PADDR2; 255#ifdef SMP 256static int PMAP1cpu; 257static int PMAP1changedcpu; 258SYSCTL_INT(_debug, OID_AUTO, PMAP1changedcpu, CTLFLAG_RD, 259 &PMAP1changedcpu, 0, 260 "Number of times pmap_pte_quick changed CPU with same PMAP1"); 261#endif 262static int PMAP1changed; 263SYSCTL_INT(_debug, OID_AUTO, PMAP1changed, CTLFLAG_RD, 264 &PMAP1changed, 0, 265 "Number of times pmap_pte_quick changed PMAP1"); 266static int PMAP1unchanged; 267SYSCTL_INT(_debug, OID_AUTO, PMAP1unchanged, CTLFLAG_RD, 268 &PMAP1unchanged, 0, 269 "Number of times pmap_pte_quick didn't change PMAP1"); 270static struct mtx PMAP2mutex; 271 272static void free_pv_entry(pmap_t pmap, pv_entry_t pv); 273static pv_entry_t get_pv_entry(pmap_t locked_pmap, int try); 274static void pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa); 275static boolean_t pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, vm_page_t m); 276static void pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa); 277static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va); 278static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, 279 vm_offset_t va); 280 281static boolean_t pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va); 282static boolean_t pmap_enter_pde(pmap_t pmap, vm_offset_t va, vm_page_t m, 283 vm_prot_t prot); 284static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, 285 vm_page_t m, vm_prot_t prot, vm_page_t mpte); 286static void pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte); 287static boolean_t pmap_is_modified_pvh(struct md_page *pvh); 288static vm_page_t pmap_lookup_pt_page(pmap_t pmap, vm_offset_t va); 289static void pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va); 290static boolean_t pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva, 291 vm_prot_t prot); 292static void pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva, 293 vm_page_t *free); 294static int pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t sva, 295 vm_page_t *free); 296static void pmap_remove_pt_page(pmap_t pmap, vm_page_t mpte); 297static void pmap_remove_page(struct pmap *pmap, vm_offset_t va, 298 vm_page_t *free); 299static void pmap_remove_entry(struct pmap *pmap, vm_page_t m, 300 vm_offset_t va); 301static void pmap_insert_entry(pmap_t pmap, vm_offset_t va, vm_page_t m); 302static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, 303 vm_page_t m); 304 305static vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va, int flags); 306 307static vm_page_t _pmap_allocpte(pmap_t pmap, unsigned ptepindex, int flags); 308static int _pmap_unwire_pte_hold(pmap_t pmap, vm_page_t m, vm_page_t *free); 309static pt_entry_t *pmap_pte_quick(pmap_t pmap, vm_offset_t va); 310static void pmap_pte_release(pt_entry_t *pte); 311static int pmap_unuse_pt(pmap_t, vm_offset_t, vm_page_t *); 312static vm_offset_t pmap_kmem_choose(vm_offset_t addr); 313#ifdef PAE 314static void *pmap_pdpt_allocf(uma_zone_t zone, int bytes, u_int8_t *flags, int wait); 315#endif 316 317CTASSERT(1 << PDESHIFT == sizeof(pd_entry_t)); 318CTASSERT(1 << PTESHIFT == sizeof(pt_entry_t)); 319 320/* 321 * If you get an error here, then you set KVA_PAGES wrong! See the 322 * description of KVA_PAGES in sys/i386/include/pmap.h. It must be 323 * multiple of 4 for a normal kernel, or a multiple of 8 for a PAE. 324 */ 325CTASSERT(KERNBASE % (1 << 24) == 0); 326 327/* 328 * Move the kernel virtual free pointer to the next 329 * 4MB. This is used to help improve performance 330 * by using a large (4MB) page for much of the kernel 331 * (.text, .data, .bss) 332 */ 333static vm_offset_t 334pmap_kmem_choose(vm_offset_t addr) 335{ 336 vm_offset_t newaddr = addr; 337 338#ifndef DISABLE_PSE 339 if (cpu_feature & CPUID_PSE) 340 newaddr = (addr + PDRMASK) & ~PDRMASK; 341#endif 342 return newaddr; 343} 344 345/* 346 * Bootstrap the system enough to run with virtual memory. 347 * 348 * On the i386 this is called after mapping has already been enabled 349 * and just syncs the pmap module with what has already been done. 350 * [We can't call it easily with mapping off since the kernel is not 351 * mapped with PA == VA, hence we would have to relocate every address 352 * from the linked base (virtual) address "KERNBASE" to the actual 353 * (physical) address starting relative to 0] 354 */ 355void 356pmap_bootstrap(vm_paddr_t firstaddr) 357{ 358 vm_offset_t va; 359 pt_entry_t *pte, *unused; 360 struct sysmaps *sysmaps; 361 int i; 362 363 /* 364 * XXX The calculation of virtual_avail is wrong. It's NKPT*PAGE_SIZE too 365 * large. It should instead be correctly calculated in locore.s and 366 * not based on 'first' (which is a physical address, not a virtual 367 * address, for the start of unused physical memory). The kernel 368 * page tables are NOT double mapped and thus should not be included 369 * in this calculation. 370 */ 371 virtual_avail = (vm_offset_t) KERNBASE + firstaddr; 372 virtual_avail = pmap_kmem_choose(virtual_avail); 373 374 virtual_end = VM_MAX_KERNEL_ADDRESS; 375 376 /* 377 * Initialize the kernel pmap (which is statically allocated). 378 */ 379 PMAP_LOCK_INIT(kernel_pmap); 380 kernel_pmap->pm_pdir = (pd_entry_t *) (KERNBASE + (u_int)IdlePTD); 381#ifdef PAE 382 kernel_pmap->pm_pdpt = (pdpt_entry_t *) (KERNBASE + (u_int)IdlePDPT); 383#endif 384 kernel_pmap->pm_root = NULL; 385 kernel_pmap->pm_active = -1; /* don't allow deactivation */ 386 TAILQ_INIT(&kernel_pmap->pm_pvchunk); 387 LIST_INIT(&allpmaps); 388 mtx_init(&allpmaps_lock, "allpmaps", NULL, MTX_SPIN); 389 mtx_lock_spin(&allpmaps_lock); 390 LIST_INSERT_HEAD(&allpmaps, kernel_pmap, pm_list); 391 mtx_unlock_spin(&allpmaps_lock); 392 nkpt = NKPT; 393 394 /* 395 * Reserve some special page table entries/VA space for temporary 396 * mapping of pages. 397 */ 398#define SYSMAP(c, p, v, n) \ 399 v = (c)va; va += ((n)*PAGE_SIZE); p = pte; pte += (n); 400 401 va = virtual_avail; 402 pte = vtopte(va); 403 404 /* 405 * CMAP1/CMAP2 are used for zeroing and copying pages. 406 * CMAP3 is used for the idle process page zeroing. 407 */ 408 for (i = 0; i < MAXCPU; i++) { 409 sysmaps = &sysmaps_pcpu[i]; 410 mtx_init(&sysmaps->lock, "SYSMAPS", NULL, MTX_DEF); 411 SYSMAP(caddr_t, sysmaps->CMAP1, sysmaps->CADDR1, 1) 412 SYSMAP(caddr_t, sysmaps->CMAP2, sysmaps->CADDR2, 1) 413 } 414 SYSMAP(caddr_t, CMAP1, CADDR1, 1) 415 SYSMAP(caddr_t, CMAP3, CADDR3, 1) 416 *CMAP3 = 0; 417 418 /* 419 * Crashdump maps. 420 */ 421 SYSMAP(caddr_t, unused, crashdumpmap, MAXDUMPPGS) 422 423 /* 424 * ptvmmap is used for reading arbitrary physical pages via /dev/mem. 425 */ 426 SYSMAP(caddr_t, unused, ptvmmap, 1) 427 428 /* 429 * msgbufp is used to map the system message buffer. 430 */ 431 SYSMAP(struct msgbuf *, unused, msgbufp, atop(round_page(MSGBUF_SIZE))) 432 433 /* 434 * ptemap is used for pmap_pte_quick 435 */ 436 SYSMAP(pt_entry_t *, PMAP1, PADDR1, 1); 437 SYSMAP(pt_entry_t *, PMAP2, PADDR2, 1); 438 439 mtx_init(&PMAP2mutex, "PMAP2", NULL, MTX_DEF); 440 441 virtual_avail = va; 442 443 *CMAP1 = 0; 444 445 /* 446 * Leave in place an identity mapping (virt == phys) for the low 1 MB 447 * physical memory region that is used by the ACPI wakeup code. This 448 * mapping must not have PG_G set. 449 */ 450#ifdef XBOX 451 /* FIXME: This is gross, but needed for the XBOX. Since we are in such 452 * an early stadium, we cannot yet neatly map video memory ... :-( 453 * Better fixes are very welcome! */ 454 if (!arch_i386_is_xbox) 455#endif 456 for (i = 1; i < NKPT; i++) 457 PTD[i] = 0; 458 459 /* Initialize the PAT MSR if present. */ 460 pmap_init_pat(); 461 462 /* Turn on PG_G on kernel page(s) */ 463 pmap_set_pg(); 464} 465 466/* 467 * Setup the PAT MSR. 468 */ 469void 470pmap_init_pat(void) 471{ 472 uint64_t pat_msr; 473 474 /* Bail if this CPU doesn't implement PAT. */ 475 if (!(cpu_feature & CPUID_PAT)) 476 return; 477 478#ifdef PAT_WORKS 479 /* 480 * Leave the indices 0-3 at the default of WB, WT, UC, and UC-. 481 * Program 4 and 5 as WP and WC. 482 * Leave 6 and 7 as UC and UC-. 483 */ 484 pat_msr = rdmsr(MSR_PAT); 485 pat_msr &= ~(PAT_MASK(4) | PAT_MASK(5)); 486 pat_msr |= PAT_VALUE(4, PAT_WRITE_PROTECTED) | 487 PAT_VALUE(5, PAT_WRITE_COMBINING); 488#else 489 /* 490 * Due to some Intel errata, we can only safely use the lower 4 491 * PAT entries. Thus, just replace PAT Index 2 with WC instead 492 * of UC-. 493 * 494 * Intel Pentium III Processor Specification Update 495 * Errata E.27 (Upper Four PAT Entries Not Usable With Mode B 496 * or Mode C Paging) 497 * 498 * Intel Pentium IV Processor Specification Update 499 * Errata N46 (PAT Index MSB May Be Calculated Incorrectly) 500 */ 501 pat_msr = rdmsr(MSR_PAT); 502 pat_msr &= ~PAT_MASK(2); 503 pat_msr |= PAT_VALUE(2, PAT_WRITE_COMBINING); 504#endif 505 wrmsr(MSR_PAT, pat_msr); 506} 507 508/* 509 * Set PG_G on kernel pages. Only the BSP calls this when SMP is turned on. 510 */ 511void 512pmap_set_pg(void) 513{ 514 pd_entry_t pdir; 515 pt_entry_t *pte; 516 vm_offset_t va, endva; 517 int i; 518 519 if (pgeflag == 0) 520 return; 521 522 i = KERNLOAD/NBPDR; 523 endva = KERNBASE + KERNend; 524 525 if (pseflag) { 526 va = KERNBASE + KERNLOAD; 527 while (va < endva) { 528 pdir = kernel_pmap->pm_pdir[KPTDI+i]; 529 pdir |= pgeflag; 530 kernel_pmap->pm_pdir[KPTDI+i] = PTD[KPTDI+i] = pdir; 531 invltlb(); /* Play it safe, invltlb() every time */ 532 i++; 533 va += NBPDR; 534 } 535 } else { 536 va = (vm_offset_t)btext; 537 while (va < endva) { 538 pte = vtopte(va); 539 if (*pte) 540 *pte |= pgeflag; 541 invltlb(); /* Play it safe, invltlb() every time */ 542 va += PAGE_SIZE; 543 } 544 } 545} 546 547/* 548 * Initialize a vm_page's machine-dependent fields. 549 */ 550void 551pmap_page_init(vm_page_t m) 552{ 553 554 TAILQ_INIT(&m->md.pv_list); 555} 556 557#ifdef PAE 558 559static MALLOC_DEFINE(M_PMAPPDPT, "pmap", "pmap pdpt"); 560 561static void * 562pmap_pdpt_allocf(uma_zone_t zone, int bytes, u_int8_t *flags, int wait) 563{ 564 *flags = UMA_SLAB_PRIV; 565 return (contigmalloc(PAGE_SIZE, M_PMAPPDPT, 0, 0x0ULL, 0xffffffffULL, 566 1, 0)); 567} 568#endif 569 570/* 571 * ABuse the pte nodes for unmapped kva to thread a kva freelist through. 572 * Requirements: 573 * - Must deal with pages in order to ensure that none of the PG_* bits 574 * are ever set, PG_V in particular. 575 * - Assumes we can write to ptes without pte_store() atomic ops, even 576 * on PAE systems. This should be ok. 577 * - Assumes nothing will ever test these addresses for 0 to indicate 578 * no mapping instead of correctly checking PG_V. 579 * - Assumes a vm_offset_t will fit in a pte (true for i386). 580 * Because PG_V is never set, there can be no mappings to invalidate. 581 */ 582static vm_offset_t 583pmap_ptelist_alloc(vm_offset_t *head) 584{ 585 pt_entry_t *pte; 586 vm_offset_t va; 587 588 va = *head; 589 if (va == 0) 590 return (va); /* Out of memory */ 591 pte = vtopte(va); 592 *head = *pte; 593 if (*head & PG_V) 594 panic("pmap_ptelist_alloc: va with PG_V set!"); 595 *pte = 0; 596 return (va); 597} 598 599static void 600pmap_ptelist_free(vm_offset_t *head, vm_offset_t va) 601{ 602 pt_entry_t *pte; 603 604 if (va & PG_V) 605 panic("pmap_ptelist_free: freeing va with PG_V set!"); 606 pte = vtopte(va); 607 *pte = *head; /* virtual! PG_V is 0 though */ 608 *head = va; 609} 610 611static void 612pmap_ptelist_init(vm_offset_t *head, void *base, int npages) 613{ 614 int i; 615 vm_offset_t va; 616 617 *head = 0; 618 for (i = npages - 1; i >= 0; i--) { 619 va = (vm_offset_t)base + i * PAGE_SIZE; 620 pmap_ptelist_free(head, va); 621 } 622} 623 624 625/* 626 * Initialize the pmap module. 627 * Called by vm_init, to initialize any structures that the pmap 628 * system needs to map virtual memory. 629 */ 630void 631pmap_init(void) 632{ 633 vm_page_t mpte; 634 vm_size_t s; 635 int i, pv_npg; 636 637 /* 638 * Initialize the vm page array entries for the kernel pmap's 639 * page table pages. 640 */ 641 for (i = 0; i < nkpt; i++) { 642 mpte = PHYS_TO_VM_PAGE(PTD[i + KPTDI] & PG_FRAME); 643 KASSERT(mpte >= vm_page_array && 644 mpte < &vm_page_array[vm_page_array_size], 645 ("pmap_init: page table page is out of range")); 646 mpte->pindex = i + KPTDI; 647 mpte->phys_addr = PTD[i + KPTDI] & PG_FRAME; 648 } 649 650 /* 651 * Initialize the address space (zone) for the pv entries. Set a 652 * high water mark so that the system can recover from excessive 653 * numbers of pv entries. 654 */ 655 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc); 656 pv_entry_max = shpgperproc * maxproc + cnt.v_page_count; 657 TUNABLE_INT_FETCH("vm.pmap.pv_entries", &pv_entry_max); 658 pv_entry_max = roundup(pv_entry_max, _NPCPV); 659 pv_entry_high_water = 9 * (pv_entry_max / 10); 660 661 /* 662 * Are large page mappings enabled? 663 */ 664 TUNABLE_INT_FETCH("vm.pmap.pg_ps_enabled", &pg_ps_enabled); 665 666 /* 667 * Calculate the size of the pv head table for superpages. 668 */ 669 for (i = 0; phys_avail[i + 1]; i += 2); 670 pv_npg = round_4mpage(phys_avail[(i - 2) + 1]) / NBPDR; 671 672 /* 673 * Allocate memory for the pv head table for superpages. 674 */ 675 s = (vm_size_t)(pv_npg * sizeof(struct md_page)); 676 s = round_page(s); 677 pv_table = (struct md_page *)kmem_alloc(kernel_map, s); 678 for (i = 0; i < pv_npg; i++) 679 TAILQ_INIT(&pv_table[i].pv_list); 680 681 pv_maxchunks = MAX(pv_entry_max / _NPCPV, maxproc); 682 pv_chunkbase = (struct pv_chunk *)kmem_alloc_nofault(kernel_map, 683 PAGE_SIZE * pv_maxchunks); 684 if (pv_chunkbase == NULL) 685 panic("pmap_init: not enough kvm for pv chunks"); 686 pmap_ptelist_init(&pv_vafree, pv_chunkbase, pv_maxchunks); 687#ifdef PAE 688 pdptzone = uma_zcreate("PDPT", NPGPTD * sizeof(pdpt_entry_t), NULL, 689 NULL, NULL, NULL, (NPGPTD * sizeof(pdpt_entry_t)) - 1, 690 UMA_ZONE_VM | UMA_ZONE_NOFREE); 691 uma_zone_set_allocf(pdptzone, pmap_pdpt_allocf); 692#endif 693} 694 695 696SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_max, CTLFLAG_RD, &pv_entry_max, 0, 697 "Max number of PV entries"); 698SYSCTL_INT(_vm_pmap, OID_AUTO, shpgperproc, CTLFLAG_RD, &shpgperproc, 0, 699 "Page share factor per proc"); 700 701SYSCTL_NODE(_vm_pmap, OID_AUTO, pde, CTLFLAG_RD, 0, 702 "2/4MB page mapping counters"); 703 704static u_long pmap_pde_demotions; 705SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, demotions, CTLFLAG_RD, 706 &pmap_pde_demotions, 0, "2/4MB page demotions"); 707 708static u_long pmap_pde_mappings; 709SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, mappings, CTLFLAG_RD, 710 &pmap_pde_mappings, 0, "2/4MB page mappings"); 711 712static u_long pmap_pde_p_failures; 713SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, p_failures, CTLFLAG_RD, 714 &pmap_pde_p_failures, 0, "2/4MB page promotion failures"); 715 716static u_long pmap_pde_promotions; 717SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, promotions, CTLFLAG_RD, 718 &pmap_pde_promotions, 0, "2/4MB page promotions"); 719 720/*************************************************** 721 * Low level helper routines..... 722 ***************************************************/ 723 724/* 725 * Determine the appropriate bits to set in a PTE or PDE for a specified 726 * caching mode. 727 */ 728static int 729pmap_cache_bits(int mode, boolean_t is_pde) 730{ 731 int pat_flag, pat_index, cache_bits; 732 733 /* The PAT bit is different for PTE's and PDE's. */ 734 pat_flag = is_pde ? PG_PDE_PAT : PG_PTE_PAT; 735 736 /* If we don't support PAT, map extended modes to older ones. */ 737 if (!(cpu_feature & CPUID_PAT)) { 738 switch (mode) { 739 case PAT_UNCACHEABLE: 740 case PAT_WRITE_THROUGH: 741 case PAT_WRITE_BACK: 742 break; 743 case PAT_UNCACHED: 744 case PAT_WRITE_COMBINING: 745 case PAT_WRITE_PROTECTED: 746 mode = PAT_UNCACHEABLE; 747 break; 748 } 749 } 750 751 /* Map the caching mode to a PAT index. */ 752 switch (mode) { 753#ifdef PAT_WORKS 754 case PAT_UNCACHEABLE: 755 pat_index = 3; 756 break; 757 case PAT_WRITE_THROUGH: 758 pat_index = 1; 759 break; 760 case PAT_WRITE_BACK: 761 pat_index = 0; 762 break; 763 case PAT_UNCACHED: 764 pat_index = 2; 765 break; 766 case PAT_WRITE_COMBINING: 767 pat_index = 5; 768 break; 769 case PAT_WRITE_PROTECTED: 770 pat_index = 4; 771 break; 772#else 773 case PAT_UNCACHED: 774 case PAT_UNCACHEABLE: 775 case PAT_WRITE_PROTECTED: 776 pat_index = 3; 777 break; 778 case PAT_WRITE_THROUGH: 779 pat_index = 1; 780 break; 781 case PAT_WRITE_BACK: 782 pat_index = 0; 783 break; 784 case PAT_WRITE_COMBINING: 785 pat_index = 2; 786 break; 787#endif 788 default: 789 panic("Unknown caching mode %d\n", mode); 790 } 791 792 /* Map the 3-bit index value into the PAT, PCD, and PWT bits. */ 793 cache_bits = 0; 794 if (pat_index & 0x4) 795 cache_bits |= pat_flag; 796 if (pat_index & 0x2) 797 cache_bits |= PG_NC_PCD; 798 if (pat_index & 0x1) 799 cache_bits |= PG_NC_PWT; 800 return (cache_bits); 801} 802#ifdef SMP 803/* 804 * For SMP, these functions have to use the IPI mechanism for coherence. 805 * 806 * N.B.: Before calling any of the following TLB invalidation functions, 807 * the calling processor must ensure that all stores updating a non- 808 * kernel page table are globally performed. Otherwise, another 809 * processor could cache an old, pre-update entry without being 810 * invalidated. This can happen one of two ways: (1) The pmap becomes 811 * active on another processor after its pm_active field is checked by 812 * one of the following functions but before a store updating the page 813 * table is globally performed. (2) The pmap becomes active on another 814 * processor before its pm_active field is checked but due to 815 * speculative loads one of the following functions stills reads the 816 * pmap as inactive on the other processor. 817 * 818 * The kernel page table is exempt because its pm_active field is 819 * immutable. The kernel page table is always active on every 820 * processor. 821 */ 822void 823pmap_invalidate_page(pmap_t pmap, vm_offset_t va) 824{ 825 u_int cpumask; 826 u_int other_cpus; 827 828 sched_pin(); 829 if (pmap == kernel_pmap || pmap->pm_active == all_cpus) { 830 invlpg(va); 831 smp_invlpg(va); 832 } else { 833 cpumask = PCPU_GET(cpumask); 834 other_cpus = PCPU_GET(other_cpus); 835 if (pmap->pm_active & cpumask) 836 invlpg(va); 837 if (pmap->pm_active & other_cpus) 838 smp_masked_invlpg(pmap->pm_active & other_cpus, va); 839 } 840 sched_unpin(); 841} 842 843void 844pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 845{ 846 u_int cpumask; 847 u_int other_cpus; 848 vm_offset_t addr; 849 850 sched_pin(); 851 if (pmap == kernel_pmap || pmap->pm_active == all_cpus) { 852 for (addr = sva; addr < eva; addr += PAGE_SIZE) 853 invlpg(addr); 854 smp_invlpg_range(sva, eva); 855 } else { 856 cpumask = PCPU_GET(cpumask); 857 other_cpus = PCPU_GET(other_cpus); 858 if (pmap->pm_active & cpumask) 859 for (addr = sva; addr < eva; addr += PAGE_SIZE) 860 invlpg(addr); 861 if (pmap->pm_active & other_cpus) 862 smp_masked_invlpg_range(pmap->pm_active & other_cpus, 863 sva, eva); 864 } 865 sched_unpin(); 866} 867 868void 869pmap_invalidate_all(pmap_t pmap) 870{ 871 u_int cpumask; 872 u_int other_cpus; 873 874 sched_pin(); 875 if (pmap == kernel_pmap || pmap->pm_active == all_cpus) { 876 invltlb(); 877 smp_invltlb(); 878 } else { 879 cpumask = PCPU_GET(cpumask); 880 other_cpus = PCPU_GET(other_cpus); 881 if (pmap->pm_active & cpumask) 882 invltlb(); 883 if (pmap->pm_active & other_cpus) 884 smp_masked_invltlb(pmap->pm_active & other_cpus); 885 } 886 sched_unpin(); 887} 888 889void 890pmap_invalidate_cache(void) 891{ 892 893 sched_pin(); 894 wbinvd(); 895 smp_cache_flush(); 896 sched_unpin(); 897} 898#else /* !SMP */ 899/* 900 * Normal, non-SMP, 486+ invalidation functions. 901 * We inline these within pmap.c for speed. 902 */ 903PMAP_INLINE void 904pmap_invalidate_page(pmap_t pmap, vm_offset_t va) 905{ 906 907 if (pmap == kernel_pmap || pmap->pm_active) 908 invlpg(va); 909} 910 911PMAP_INLINE void 912pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 913{ 914 vm_offset_t addr; 915 916 if (pmap == kernel_pmap || pmap->pm_active) 917 for (addr = sva; addr < eva; addr += PAGE_SIZE) 918 invlpg(addr); 919} 920 921PMAP_INLINE void 922pmap_invalidate_all(pmap_t pmap) 923{ 924 925 if (pmap == kernel_pmap || pmap->pm_active) 926 invltlb(); 927} 928 929PMAP_INLINE void 930pmap_invalidate_cache(void) 931{ 932 933 wbinvd(); 934} 935#endif /* !SMP */ 936 937/* 938 * Are we current address space or kernel? N.B. We return FALSE when 939 * a pmap's page table is in use because a kernel thread is borrowing 940 * it. The borrowed page table can change spontaneously, making any 941 * dependence on its continued use subject to a race condition. 942 */ 943static __inline int 944pmap_is_current(pmap_t pmap) 945{ 946 947 return (pmap == kernel_pmap || 948 (pmap == vmspace_pmap(curthread->td_proc->p_vmspace) && 949 (pmap->pm_pdir[PTDPTDI] & PG_FRAME) == (PTDpde[0] & PG_FRAME))); 950} 951 952/* 953 * If the given pmap is not the current or kernel pmap, the returned pte must 954 * be released by passing it to pmap_pte_release(). 955 */ 956pt_entry_t * 957pmap_pte(pmap_t pmap, vm_offset_t va) 958{ 959 pd_entry_t newpf; 960 pd_entry_t *pde; 961 962 pde = pmap_pde(pmap, va); 963 if (*pde & PG_PS) 964 return (pde); 965 if (*pde != 0) { 966 /* are we current address space or kernel? */ 967 if (pmap_is_current(pmap)) 968 return (vtopte(va)); 969 mtx_lock(&PMAP2mutex); 970 newpf = *pde & PG_FRAME; 971 if ((*PMAP2 & PG_FRAME) != newpf) { 972 *PMAP2 = newpf | PG_RW | PG_V | PG_A | PG_M; 973 pmap_invalidate_page(kernel_pmap, (vm_offset_t)PADDR2); 974 } 975 return (PADDR2 + (i386_btop(va) & (NPTEPG - 1))); 976 } 977 return (0); 978} 979 980/* 981 * Releases a pte that was obtained from pmap_pte(). Be prepared for the pte 982 * being NULL. 983 */ 984static __inline void 985pmap_pte_release(pt_entry_t *pte) 986{ 987 988 if ((pt_entry_t *)((vm_offset_t)pte & ~PAGE_MASK) == PADDR2) 989 mtx_unlock(&PMAP2mutex); 990} 991 992static __inline void 993invlcaddr(void *caddr) 994{ 995 996 invlpg((u_int)caddr); 997} 998 999/* 1000 * Super fast pmap_pte routine best used when scanning 1001 * the pv lists. This eliminates many coarse-grained 1002 * invltlb calls. Note that many of the pv list 1003 * scans are across different pmaps. It is very wasteful 1004 * to do an entire invltlb for checking a single mapping. 1005 * 1006 * If the given pmap is not the current pmap, vm_page_queue_mtx 1007 * must be held and curthread pinned to a CPU. 1008 */ 1009static pt_entry_t * 1010pmap_pte_quick(pmap_t pmap, vm_offset_t va) 1011{ 1012 pd_entry_t newpf; 1013 pd_entry_t *pde; 1014 1015 pde = pmap_pde(pmap, va); 1016 if (*pde & PG_PS) 1017 return (pde); 1018 if (*pde != 0) { 1019 /* are we current address space or kernel? */ 1020 if (pmap_is_current(pmap)) 1021 return (vtopte(va)); 1022 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1023 KASSERT(curthread->td_pinned > 0, ("curthread not pinned")); 1024 newpf = *pde & PG_FRAME; 1025 if ((*PMAP1 & PG_FRAME) != newpf) { 1026 *PMAP1 = newpf | PG_RW | PG_V | PG_A | PG_M; 1027#ifdef SMP 1028 PMAP1cpu = PCPU_GET(cpuid); 1029#endif 1030 invlcaddr(PADDR1); 1031 PMAP1changed++; 1032 } else 1033#ifdef SMP 1034 if (PMAP1cpu != PCPU_GET(cpuid)) { 1035 PMAP1cpu = PCPU_GET(cpuid); 1036 invlcaddr(PADDR1); 1037 PMAP1changedcpu++; 1038 } else 1039#endif 1040 PMAP1unchanged++; 1041 return (PADDR1 + (i386_btop(va) & (NPTEPG - 1))); 1042 } 1043 return (0); 1044} 1045 1046/* 1047 * Routine: pmap_extract 1048 * Function: 1049 * Extract the physical page address associated 1050 * with the given map/virtual_address pair. 1051 */ 1052vm_paddr_t 1053pmap_extract(pmap_t pmap, vm_offset_t va) 1054{ 1055 vm_paddr_t rtval; 1056 pt_entry_t *pte; 1057 pd_entry_t pde; 1058 1059 rtval = 0; 1060 PMAP_LOCK(pmap); 1061 pde = pmap->pm_pdir[va >> PDRSHIFT]; 1062 if (pde != 0) { 1063 if ((pde & PG_PS) != 0) { 1064 rtval = (pde & PG_PS_FRAME) | (va & PDRMASK); 1065 PMAP_UNLOCK(pmap); 1066 return rtval; 1067 } 1068 pte = pmap_pte(pmap, va); 1069 rtval = (*pte & PG_FRAME) | (va & PAGE_MASK); 1070 pmap_pte_release(pte); 1071 } 1072 PMAP_UNLOCK(pmap); 1073 return (rtval); 1074} 1075 1076/* 1077 * Routine: pmap_extract_and_hold 1078 * Function: 1079 * Atomically extract and hold the physical page 1080 * with the given pmap and virtual address pair 1081 * if that mapping permits the given protection. 1082 */ 1083vm_page_t 1084pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot) 1085{ 1086 pd_entry_t pde; 1087 pt_entry_t pte; 1088 vm_page_t m; 1089 1090 m = NULL; 1091 vm_page_lock_queues(); 1092 PMAP_LOCK(pmap); 1093 pde = *pmap_pde(pmap, va); 1094 if (pde != 0) { 1095 if (pde & PG_PS) { 1096 if ((pde & PG_RW) || (prot & VM_PROT_WRITE) == 0) { 1097 m = PHYS_TO_VM_PAGE((pde & PG_PS_FRAME) | 1098 (va & PDRMASK)); 1099 vm_page_hold(m); 1100 } 1101 } else { 1102 sched_pin(); 1103 pte = *pmap_pte_quick(pmap, va); 1104 if (pte != 0 && 1105 ((pte & PG_RW) || (prot & VM_PROT_WRITE) == 0)) { 1106 m = PHYS_TO_VM_PAGE(pte & PG_FRAME); 1107 vm_page_hold(m); 1108 } 1109 sched_unpin(); 1110 } 1111 } 1112 vm_page_unlock_queues(); 1113 PMAP_UNLOCK(pmap); 1114 return (m); 1115} 1116 1117/*************************************************** 1118 * Low level mapping routines..... 1119 ***************************************************/ 1120 1121/* 1122 * Add a wired page to the kva. 1123 * Note: not SMP coherent. 1124 */ 1125PMAP_INLINE void 1126pmap_kenter(vm_offset_t va, vm_paddr_t pa) 1127{ 1128 pt_entry_t *pte; 1129 1130 pte = vtopte(va); 1131 pte_store(pte, pa | PG_RW | PG_V | pgeflag); 1132} 1133 1134PMAP_INLINE void 1135pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode) 1136{ 1137 pt_entry_t *pte; 1138 1139 pte = vtopte(va); 1140 pte_store(pte, pa | PG_RW | PG_V | pgeflag | pmap_cache_bits(mode, 0)); 1141} 1142 1143/* 1144 * Remove a page from the kernel pagetables. 1145 * Note: not SMP coherent. 1146 */ 1147PMAP_INLINE void 1148pmap_kremove(vm_offset_t va) 1149{ 1150 pt_entry_t *pte; 1151 1152 pte = vtopte(va); 1153 pte_clear(pte); 1154} 1155 1156/* 1157 * Used to map a range of physical addresses into kernel 1158 * virtual address space. 1159 * 1160 * The value passed in '*virt' is a suggested virtual address for 1161 * the mapping. Architectures which can support a direct-mapped 1162 * physical to virtual region can return the appropriate address 1163 * within that region, leaving '*virt' unchanged. Other 1164 * architectures should map the pages starting at '*virt' and 1165 * update '*virt' with the first usable address after the mapped 1166 * region. 1167 */ 1168vm_offset_t 1169pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot) 1170{ 1171 vm_offset_t va, sva; 1172 1173 va = sva = *virt; 1174 while (start < end) { 1175 pmap_kenter(va, start); 1176 va += PAGE_SIZE; 1177 start += PAGE_SIZE; 1178 } 1179 pmap_invalidate_range(kernel_pmap, sva, va); 1180 *virt = va; 1181 return (sva); 1182} 1183 1184 1185/* 1186 * Add a list of wired pages to the kva 1187 * this routine is only used for temporary 1188 * kernel mappings that do not need to have 1189 * page modification or references recorded. 1190 * Note that old mappings are simply written 1191 * over. The page *must* be wired. 1192 * Note: SMP coherent. Uses a ranged shootdown IPI. 1193 */ 1194void 1195pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count) 1196{ 1197 pt_entry_t *endpte, oldpte, *pte; 1198 1199 oldpte = 0; 1200 pte = vtopte(sva); 1201 endpte = pte + count; 1202 while (pte < endpte) { 1203 oldpte |= *pte; 1204 pte_store(pte, VM_PAGE_TO_PHYS(*ma) | pgeflag | PG_RW | PG_V); 1205 pte++; 1206 ma++; 1207 } 1208 if ((oldpte & PG_V) != 0) 1209 pmap_invalidate_range(kernel_pmap, sva, sva + count * 1210 PAGE_SIZE); 1211} 1212 1213/* 1214 * This routine tears out page mappings from the 1215 * kernel -- it is meant only for temporary mappings. 1216 * Note: SMP coherent. Uses a ranged shootdown IPI. 1217 */ 1218void 1219pmap_qremove(vm_offset_t sva, int count) 1220{ 1221 vm_offset_t va; 1222 1223 va = sva; 1224 while (count-- > 0) { 1225 pmap_kremove(va); 1226 va += PAGE_SIZE; 1227 } 1228 pmap_invalidate_range(kernel_pmap, sva, va); 1229} 1230 1231/*************************************************** 1232 * Page table page management routines..... 1233 ***************************************************/ 1234static __inline void 1235pmap_free_zero_pages(vm_page_t free) 1236{ 1237 vm_page_t m; 1238 1239 while (free != NULL) { 1240 m = free; 1241 free = m->right; 1242 /* Preserve the page's PG_ZERO setting. */ 1243 vm_page_free_toq(m); 1244 } 1245} 1246 1247/* 1248 * Schedule the specified unused page table page to be freed. Specifically, 1249 * add the page to the specified list of pages that will be released to the 1250 * physical memory manager after the TLB has been updated. 1251 */ 1252static __inline void 1253pmap_add_delayed_free_list(vm_page_t m, vm_page_t *free, boolean_t set_PG_ZERO) 1254{ 1255 1256 if (set_PG_ZERO) 1257 m->flags |= PG_ZERO; 1258 else 1259 m->flags &= ~PG_ZERO; 1260 m->right = *free; 1261 *free = m; 1262} 1263 1264/* 1265 * Inserts the specified page table page into the specified pmap's collection 1266 * of idle page table pages. Each of a pmap's page table pages is responsible 1267 * for mapping a distinct range of virtual addresses. The pmap's collection is 1268 * ordered by this virtual address range. 1269 */ 1270static void 1271pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte) 1272{ 1273 vm_page_t root; 1274 1275 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1276 root = pmap->pm_root; 1277 if (root == NULL) { 1278 mpte->left = NULL; 1279 mpte->right = NULL; 1280 } else { 1281 root = vm_page_splay(mpte->pindex, root); 1282 if (mpte->pindex < root->pindex) { 1283 mpte->left = root->left; 1284 mpte->right = root; 1285 root->left = NULL; 1286 } else if (mpte->pindex == root->pindex) 1287 panic("pmap_insert_pt_page: pindex already inserted"); 1288 else { 1289 mpte->right = root->right; 1290 mpte->left = root; 1291 root->right = NULL; 1292 } 1293 } 1294 pmap->pm_root = mpte; 1295} 1296 1297/* 1298 * Looks for a page table page mapping the specified virtual address in the 1299 * specified pmap's collection of idle page table pages. Returns NULL if there 1300 * is no page table page corresponding to the specified virtual address. 1301 */ 1302static vm_page_t 1303pmap_lookup_pt_page(pmap_t pmap, vm_offset_t va) 1304{ 1305 vm_page_t mpte; 1306 vm_pindex_t pindex = va >> PDRSHIFT; 1307 1308 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1309 if ((mpte = pmap->pm_root) != NULL && mpte->pindex != pindex) { 1310 mpte = vm_page_splay(pindex, mpte); 1311 if ((pmap->pm_root = mpte)->pindex != pindex) 1312 mpte = NULL; 1313 } 1314 return (mpte); 1315} 1316 1317/* 1318 * Removes the specified page table page from the specified pmap's collection 1319 * of idle page table pages. The specified page table page must be a member of 1320 * the pmap's collection. 1321 */ 1322static void 1323pmap_remove_pt_page(pmap_t pmap, vm_page_t mpte) 1324{ 1325 vm_page_t root; 1326 1327 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1328 if (mpte != pmap->pm_root) 1329 vm_page_splay(mpte->pindex, pmap->pm_root); 1330 if (mpte->left == NULL) 1331 root = mpte->right; 1332 else { 1333 root = vm_page_splay(mpte->pindex, mpte->left); 1334 root->right = mpte->right; 1335 } 1336 pmap->pm_root = root; 1337} 1338 1339/* 1340 * This routine unholds page table pages, and if the hold count 1341 * drops to zero, then it decrements the wire count. 1342 */ 1343static __inline int 1344pmap_unwire_pte_hold(pmap_t pmap, vm_page_t m, vm_page_t *free) 1345{ 1346 1347 --m->wire_count; 1348 if (m->wire_count == 0) 1349 return _pmap_unwire_pte_hold(pmap, m, free); 1350 else 1351 return 0; 1352} 1353 1354static int 1355_pmap_unwire_pte_hold(pmap_t pmap, vm_page_t m, vm_page_t *free) 1356{ 1357 vm_offset_t pteva; 1358 1359 /* 1360 * unmap the page table page 1361 */ 1362 pmap->pm_pdir[m->pindex] = 0; 1363 --pmap->pm_stats.resident_count; 1364 1365 /* 1366 * This is a release store so that the ordinary store unmapping 1367 * the page table page is globally performed before TLB shoot- 1368 * down is begun. 1369 */ 1370 atomic_subtract_rel_int(&cnt.v_wire_count, 1); 1371 1372 /* 1373 * Do an invltlb to make the invalidated mapping 1374 * take effect immediately. 1375 */ 1376 pteva = VM_MAXUSER_ADDRESS + i386_ptob(m->pindex); 1377 pmap_invalidate_page(pmap, pteva); 1378 1379 /* 1380 * Put page on a list so that it is released after 1381 * *ALL* TLB shootdown is done 1382 */ 1383 pmap_add_delayed_free_list(m, free, TRUE); 1384 1385 return 1; 1386} 1387 1388/* 1389 * After removing a page table entry, this routine is used to 1390 * conditionally free the page, and manage the hold/wire counts. 1391 */ 1392static int 1393pmap_unuse_pt(pmap_t pmap, vm_offset_t va, vm_page_t *free) 1394{ 1395 pd_entry_t ptepde; 1396 vm_page_t mpte; 1397 1398 if (va >= VM_MAXUSER_ADDRESS) 1399 return 0; 1400 ptepde = *pmap_pde(pmap, va); 1401 mpte = PHYS_TO_VM_PAGE(ptepde & PG_FRAME); 1402 return pmap_unwire_pte_hold(pmap, mpte, free); 1403} 1404 1405void 1406pmap_pinit0(pmap_t pmap) 1407{ 1408 1409 PMAP_LOCK_INIT(pmap); 1410 pmap->pm_pdir = (pd_entry_t *)(KERNBASE + (vm_offset_t)IdlePTD); 1411#ifdef PAE 1412 pmap->pm_pdpt = (pdpt_entry_t *)(KERNBASE + (vm_offset_t)IdlePDPT); 1413#endif 1414 pmap->pm_root = NULL; 1415 pmap->pm_active = 0; 1416 PCPU_SET(curpmap, pmap); 1417 TAILQ_INIT(&pmap->pm_pvchunk); 1418 bzero(&pmap->pm_stats, sizeof pmap->pm_stats); 1419 mtx_lock_spin(&allpmaps_lock); 1420 LIST_INSERT_HEAD(&allpmaps, pmap, pm_list); 1421 mtx_unlock_spin(&allpmaps_lock); 1422} 1423 1424/* 1425 * Initialize a preallocated and zeroed pmap structure, 1426 * such as one in a vmspace structure. 1427 */ 1428int 1429pmap_pinit(pmap_t pmap) 1430{ 1431 vm_page_t m, ptdpg[NPGPTD]; 1432 vm_paddr_t pa; 1433 static int color; 1434 int i; 1435 1436 PMAP_LOCK_INIT(pmap); 1437 1438 /* 1439 * No need to allocate page table space yet but we do need a valid 1440 * page directory table. 1441 */ 1442 if (pmap->pm_pdir == NULL) { 1443 pmap->pm_pdir = (pd_entry_t *)kmem_alloc_nofault(kernel_map, 1444 NBPTD); 1445 1446 if (pmap->pm_pdir == NULL) { 1447 PMAP_LOCK_DESTROY(pmap); 1448 return (0); 1449 } 1450#ifdef PAE 1451 pmap->pm_pdpt = uma_zalloc(pdptzone, M_WAITOK | M_ZERO); 1452 KASSERT(((vm_offset_t)pmap->pm_pdpt & 1453 ((NPGPTD * sizeof(pdpt_entry_t)) - 1)) == 0, 1454 ("pmap_pinit: pdpt misaligned")); 1455 KASSERT(pmap_kextract((vm_offset_t)pmap->pm_pdpt) < (4ULL<<30), 1456 ("pmap_pinit: pdpt above 4g")); 1457#endif 1458 pmap->pm_root = NULL; 1459 } 1460 KASSERT(pmap->pm_root == NULL, 1461 ("pmap_pinit: pmap has reserved page table page(s)")); 1462 1463 /* 1464 * allocate the page directory page(s) 1465 */ 1466 for (i = 0; i < NPGPTD;) { 1467 m = vm_page_alloc(NULL, color++, 1468 VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | 1469 VM_ALLOC_ZERO); 1470 if (m == NULL) 1471 VM_WAIT; 1472 else { 1473 ptdpg[i++] = m; 1474 } 1475 } 1476 1477 pmap_qenter((vm_offset_t)pmap->pm_pdir, ptdpg, NPGPTD); 1478 1479 for (i = 0; i < NPGPTD; i++) { 1480 if ((ptdpg[i]->flags & PG_ZERO) == 0) 1481 bzero(pmap->pm_pdir + (i * NPDEPG), PAGE_SIZE); 1482 } 1483 1484 mtx_lock_spin(&allpmaps_lock); 1485 LIST_INSERT_HEAD(&allpmaps, pmap, pm_list); 1486 mtx_unlock_spin(&allpmaps_lock); 1487 /* Wire in kernel global address entries. */ 1488 bcopy(PTD + KPTDI, pmap->pm_pdir + KPTDI, nkpt * sizeof(pd_entry_t)); 1489 1490 /* install self-referential address mapping entry(s) */ 1491 for (i = 0; i < NPGPTD; i++) { 1492 pa = VM_PAGE_TO_PHYS(ptdpg[i]); 1493 pmap->pm_pdir[PTDPTDI + i] = pa | PG_V | PG_RW | PG_A | PG_M; 1494#ifdef PAE 1495 pmap->pm_pdpt[i] = pa | PG_V; 1496#endif 1497 } 1498 1499 pmap->pm_active = 0; 1500 TAILQ_INIT(&pmap->pm_pvchunk); 1501 bzero(&pmap->pm_stats, sizeof pmap->pm_stats); 1502 1503 return (1); 1504} 1505 1506/* 1507 * this routine is called if the page table page is not 1508 * mapped correctly. 1509 */ 1510static vm_page_t 1511_pmap_allocpte(pmap_t pmap, unsigned ptepindex, int flags) 1512{ 1513 vm_paddr_t ptepa; 1514 vm_page_t m; 1515 1516 KASSERT((flags & (M_NOWAIT | M_WAITOK)) == M_NOWAIT || 1517 (flags & (M_NOWAIT | M_WAITOK)) == M_WAITOK, 1518 ("_pmap_allocpte: flags is neither M_NOWAIT nor M_WAITOK")); 1519 1520 /* 1521 * Allocate a page table page. 1522 */ 1523 if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ | 1524 VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) { 1525 if (flags & M_WAITOK) { 1526 PMAP_UNLOCK(pmap); 1527 vm_page_unlock_queues(); 1528 VM_WAIT; 1529 vm_page_lock_queues(); 1530 PMAP_LOCK(pmap); 1531 } 1532 1533 /* 1534 * Indicate the need to retry. While waiting, the page table 1535 * page may have been allocated. 1536 */ 1537 return (NULL); 1538 } 1539 if ((m->flags & PG_ZERO) == 0) 1540 pmap_zero_page(m); 1541 1542 /* 1543 * Map the pagetable page into the process address space, if 1544 * it isn't already there. 1545 */ 1546 1547 pmap->pm_stats.resident_count++; 1548 1549 ptepa = VM_PAGE_TO_PHYS(m); 1550 pmap->pm_pdir[ptepindex] = 1551 (pd_entry_t) (ptepa | PG_U | PG_RW | PG_V | PG_A | PG_M); 1552 1553 return m; 1554} 1555 1556static vm_page_t 1557pmap_allocpte(pmap_t pmap, vm_offset_t va, int flags) 1558{ 1559 unsigned ptepindex; 1560 pd_entry_t ptepa; 1561 vm_page_t m; 1562 1563 KASSERT((flags & (M_NOWAIT | M_WAITOK)) == M_NOWAIT || 1564 (flags & (M_NOWAIT | M_WAITOK)) == M_WAITOK, 1565 ("pmap_allocpte: flags is neither M_NOWAIT nor M_WAITOK")); 1566 1567 /* 1568 * Calculate pagetable page index 1569 */ 1570 ptepindex = va >> PDRSHIFT; 1571retry: 1572 /* 1573 * Get the page directory entry 1574 */ 1575 ptepa = pmap->pm_pdir[ptepindex]; 1576 1577 /* 1578 * This supports switching from a 4MB page to a 1579 * normal 4K page. 1580 */ 1581 if (ptepa & PG_PS) { 1582 (void)pmap_demote_pde(pmap, &pmap->pm_pdir[ptepindex], va); 1583 ptepa = pmap->pm_pdir[ptepindex]; 1584 } 1585 1586 /* 1587 * If the page table page is mapped, we just increment the 1588 * hold count, and activate it. 1589 */ 1590 if (ptepa) { 1591 m = PHYS_TO_VM_PAGE(ptepa & PG_FRAME); 1592 m->wire_count++; 1593 } else { 1594 /* 1595 * Here if the pte page isn't mapped, or if it has 1596 * been deallocated. 1597 */ 1598 m = _pmap_allocpte(pmap, ptepindex, flags); 1599 if (m == NULL && (flags & M_WAITOK)) 1600 goto retry; 1601 } 1602 return (m); 1603} 1604 1605 1606/*************************************************** 1607* Pmap allocation/deallocation routines. 1608 ***************************************************/ 1609 1610#ifdef SMP 1611/* 1612 * Deal with a SMP shootdown of other users of the pmap that we are 1613 * trying to dispose of. This can be a bit hairy. 1614 */ 1615static u_int *lazymask; 1616static u_int lazyptd; 1617static volatile u_int lazywait; 1618 1619void pmap_lazyfix_action(void); 1620 1621void 1622pmap_lazyfix_action(void) 1623{ 1624 u_int mymask = PCPU_GET(cpumask); 1625 1626#ifdef COUNT_IPIS 1627 (*ipi_lazypmap_counts[PCPU_GET(cpuid)])++; 1628#endif 1629 if (rcr3() == lazyptd) 1630 load_cr3(PCPU_GET(curpcb)->pcb_cr3); 1631 atomic_clear_int(lazymask, mymask); 1632 atomic_store_rel_int(&lazywait, 1); 1633} 1634 1635static void 1636pmap_lazyfix_self(u_int mymask) 1637{ 1638 1639 if (rcr3() == lazyptd) 1640 load_cr3(PCPU_GET(curpcb)->pcb_cr3); 1641 atomic_clear_int(lazymask, mymask); 1642} 1643 1644 1645static void 1646pmap_lazyfix(pmap_t pmap) 1647{ 1648 u_int mymask; 1649 u_int mask; 1650 u_int spins; 1651 1652 while ((mask = pmap->pm_active) != 0) { 1653 spins = 50000000; 1654 mask = mask & -mask; /* Find least significant set bit */ 1655 mtx_lock_spin(&smp_ipi_mtx); 1656#ifdef PAE 1657 lazyptd = vtophys(pmap->pm_pdpt); 1658#else 1659 lazyptd = vtophys(pmap->pm_pdir); 1660#endif 1661 mymask = PCPU_GET(cpumask); 1662 if (mask == mymask) { 1663 lazymask = &pmap->pm_active; 1664 pmap_lazyfix_self(mymask); 1665 } else { 1666 atomic_store_rel_int((u_int *)&lazymask, 1667 (u_int)&pmap->pm_active); 1668 atomic_store_rel_int(&lazywait, 0); 1669 ipi_selected(mask, IPI_LAZYPMAP); 1670 while (lazywait == 0) { 1671 ia32_pause(); 1672 if (--spins == 0) 1673 break; 1674 } 1675 } 1676 mtx_unlock_spin(&smp_ipi_mtx); 1677 if (spins == 0) 1678 printf("pmap_lazyfix: spun for 50000000\n"); 1679 } 1680} 1681 1682#else /* SMP */ 1683 1684/* 1685 * Cleaning up on uniprocessor is easy. For various reasons, we're 1686 * unlikely to have to even execute this code, including the fact 1687 * that the cleanup is deferred until the parent does a wait(2), which 1688 * means that another userland process has run. 1689 */ 1690static void 1691pmap_lazyfix(pmap_t pmap) 1692{ 1693 u_int cr3; 1694 1695 cr3 = vtophys(pmap->pm_pdir); 1696 if (cr3 == rcr3()) { 1697 load_cr3(PCPU_GET(curpcb)->pcb_cr3); 1698 pmap->pm_active &= ~(PCPU_GET(cpumask)); 1699 } 1700} 1701#endif /* SMP */ 1702 1703/* 1704 * Release any resources held by the given physical map. 1705 * Called when a pmap initialized by pmap_pinit is being released. 1706 * Should only be called if the map contains no valid mappings. 1707 */ 1708void 1709pmap_release(pmap_t pmap) 1710{ 1711 vm_page_t m, ptdpg[NPGPTD]; 1712 int i; 1713 1714 KASSERT(pmap->pm_stats.resident_count == 0, 1715 ("pmap_release: pmap resident count %ld != 0", 1716 pmap->pm_stats.resident_count)); 1717 KASSERT(pmap->pm_root == NULL, 1718 ("pmap_release: pmap has reserved page table page(s)")); 1719 1720 pmap_lazyfix(pmap); 1721 mtx_lock_spin(&allpmaps_lock); 1722 LIST_REMOVE(pmap, pm_list); 1723 mtx_unlock_spin(&allpmaps_lock); 1724 1725 for (i = 0; i < NPGPTD; i++) 1726 ptdpg[i] = PHYS_TO_VM_PAGE(pmap->pm_pdir[PTDPTDI + i] & 1727 PG_FRAME); 1728 1729 bzero(pmap->pm_pdir + PTDPTDI, (nkpt + NPGPTD) * 1730 sizeof(*pmap->pm_pdir)); 1731 1732 pmap_qremove((vm_offset_t)pmap->pm_pdir, NPGPTD); 1733 1734 for (i = 0; i < NPGPTD; i++) { 1735 m = ptdpg[i]; 1736#ifdef PAE 1737 KASSERT(VM_PAGE_TO_PHYS(m) == (pmap->pm_pdpt[i] & PG_FRAME), 1738 ("pmap_release: got wrong ptd page")); 1739#endif 1740 m->wire_count--; 1741 atomic_subtract_int(&cnt.v_wire_count, 1); 1742 vm_page_free_zero(m); 1743 } 1744 PMAP_LOCK_DESTROY(pmap); 1745} 1746 1747static int 1748kvm_size(SYSCTL_HANDLER_ARGS) 1749{ 1750 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - KERNBASE; 1751 1752 return sysctl_handle_long(oidp, &ksize, 0, req); 1753} 1754SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG|CTLFLAG_RD, 1755 0, 0, kvm_size, "IU", "Size of KVM"); 1756 1757static int 1758kvm_free(SYSCTL_HANDLER_ARGS) 1759{ 1760 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end; 1761 1762 return sysctl_handle_long(oidp, &kfree, 0, req); 1763} 1764SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG|CTLFLAG_RD, 1765 0, 0, kvm_free, "IU", "Amount of KVM free"); 1766 1767/* 1768 * grow the number of kernel page table entries, if needed 1769 */ 1770void 1771pmap_growkernel(vm_offset_t addr) 1772{ 1773 struct pmap *pmap; 1774 vm_paddr_t ptppaddr; 1775 vm_page_t nkpg; 1776 pd_entry_t newpdir; 1777 pt_entry_t *pde; 1778 1779 mtx_assert(&kernel_map->system_mtx, MA_OWNED); 1780 if (kernel_vm_end == 0) { 1781 kernel_vm_end = KERNBASE; 1782 nkpt = 0; 1783 while (pdir_pde(PTD, kernel_vm_end)) { 1784 kernel_vm_end = (kernel_vm_end + PAGE_SIZE * NPTEPG) & ~(PAGE_SIZE * NPTEPG - 1); 1785 nkpt++; 1786 if (kernel_vm_end - 1 >= kernel_map->max_offset) { 1787 kernel_vm_end = kernel_map->max_offset; 1788 break; 1789 } 1790 } 1791 } 1792 addr = roundup2(addr, PAGE_SIZE * NPTEPG); 1793 if (addr - 1 >= kernel_map->max_offset) 1794 addr = kernel_map->max_offset; 1795 while (kernel_vm_end < addr) { 1796 if (pdir_pde(PTD, kernel_vm_end)) { 1797 kernel_vm_end = (kernel_vm_end + PAGE_SIZE * NPTEPG) & ~(PAGE_SIZE * NPTEPG - 1); 1798 if (kernel_vm_end - 1 >= kernel_map->max_offset) { 1799 kernel_vm_end = kernel_map->max_offset; 1800 break; 1801 } 1802 continue; 1803 } 1804 1805 nkpg = vm_page_alloc(NULL, kernel_vm_end >> PDRSHIFT, 1806 VM_ALLOC_NOOBJ | VM_ALLOC_SYSTEM | VM_ALLOC_WIRED); 1807 if (nkpg == NULL) 1808 panic("pmap_growkernel: no memory to grow kernel"); 1809 1810 nkpt++; 1811 1812 pmap_zero_page(nkpg); 1813 ptppaddr = VM_PAGE_TO_PHYS(nkpg); 1814 newpdir = (pd_entry_t) (ptppaddr | PG_V | PG_RW | PG_A | PG_M); 1815 pdir_pde(PTD, kernel_vm_end) = newpdir; 1816 1817 mtx_lock_spin(&allpmaps_lock); 1818 LIST_FOREACH(pmap, &allpmaps, pm_list) { 1819 pde = pmap_pde(pmap, kernel_vm_end); 1820 pde_store(pde, newpdir); 1821 } 1822 mtx_unlock_spin(&allpmaps_lock); 1823 kernel_vm_end = (kernel_vm_end + PAGE_SIZE * NPTEPG) & ~(PAGE_SIZE * NPTEPG - 1); 1824 if (kernel_vm_end - 1 >= kernel_map->max_offset) { 1825 kernel_vm_end = kernel_map->max_offset; 1826 break; 1827 } 1828 } 1829} 1830 1831 1832/*************************************************** 1833 * page management routines. 1834 ***************************************************/ 1835 1836CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE); 1837CTASSERT(_NPCM == 11); 1838 1839static __inline struct pv_chunk * 1840pv_to_chunk(pv_entry_t pv) 1841{ 1842 1843 return (struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK); 1844} 1845 1846#define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap) 1847 1848#define PC_FREE0_9 0xfffffffful /* Free values for index 0 through 9 */ 1849#define PC_FREE10 0x0000fffful /* Free values for index 10 */ 1850 1851static uint32_t pc_freemask[11] = { 1852 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9, 1853 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9, 1854 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9, 1855 PC_FREE0_9, PC_FREE10 1856}; 1857 1858SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0, 1859 "Current number of pv entries"); 1860 1861#ifdef PV_STATS 1862static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail; 1863 1864SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0, 1865 "Current number of pv entry chunks"); 1866SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0, 1867 "Current number of pv entry chunks allocated"); 1868SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0, 1869 "Current number of pv entry chunks frees"); 1870SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0, 1871 "Number of times tried to get a chunk page but failed."); 1872 1873static long pv_entry_frees, pv_entry_allocs; 1874static int pv_entry_spare; 1875 1876SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0, 1877 "Current number of pv entry frees"); 1878SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0, 1879 "Current number of pv entry allocs"); 1880SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0, 1881 "Current number of spare pv entries"); 1882 1883static int pmap_collect_inactive, pmap_collect_active; 1884 1885SYSCTL_INT(_vm_pmap, OID_AUTO, pmap_collect_inactive, CTLFLAG_RD, &pmap_collect_inactive, 0, 1886 "Current number times pmap_collect called on inactive queue"); 1887SYSCTL_INT(_vm_pmap, OID_AUTO, pmap_collect_active, CTLFLAG_RD, &pmap_collect_active, 0, 1888 "Current number times pmap_collect called on active queue"); 1889#endif 1890 1891/* 1892 * We are in a serious low memory condition. Resort to 1893 * drastic measures to free some pages so we can allocate 1894 * another pv entry chunk. This is normally called to 1895 * unmap inactive pages, and if necessary, active pages. 1896 */ 1897static void 1898pmap_collect(pmap_t locked_pmap, struct vpgqueues *vpq) 1899{ 1900 struct md_page *pvh; 1901 pd_entry_t *pde; 1902 pmap_t pmap; 1903 pt_entry_t *pte, tpte; 1904 pv_entry_t next_pv, pv; 1905 vm_offset_t va; 1906 vm_page_t m, free; 1907 1908 sched_pin(); 1909 TAILQ_FOREACH(m, &vpq->pl, pageq) { 1910 if (m->hold_count || m->busy) 1911 continue; 1912 TAILQ_FOREACH_SAFE(pv, &m->md.pv_list, pv_list, next_pv) { 1913 va = pv->pv_va; 1914 pmap = PV_PMAP(pv); 1915 /* Avoid deadlock and lock recursion. */ 1916 if (pmap > locked_pmap) 1917 PMAP_LOCK(pmap); 1918 else if (pmap != locked_pmap && !PMAP_TRYLOCK(pmap)) 1919 continue; 1920 pmap->pm_stats.resident_count--; 1921 pde = pmap_pde(pmap, va); 1922 KASSERT((*pde & PG_PS) == 0, ("pmap_collect: found" 1923 " a 4mpage in page %p's pv list", m)); 1924 pte = pmap_pte_quick(pmap, va); 1925 tpte = pte_load_clear(pte); 1926 KASSERT((tpte & PG_W) == 0, 1927 ("pmap_collect: wired pte %#jx", (uintmax_t)tpte)); 1928 if (tpte & PG_A) 1929 vm_page_flag_set(m, PG_REFERENCED); 1930 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) 1931 vm_page_dirty(m); 1932 free = NULL; 1933 pmap_unuse_pt(pmap, va, &free); 1934 pmap_invalidate_page(pmap, va); 1935 pmap_free_zero_pages(free); 1936 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list); 1937 if (TAILQ_EMPTY(&m->md.pv_list)) { 1938 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 1939 if (TAILQ_EMPTY(&pvh->pv_list)) 1940 vm_page_flag_clear(m, PG_WRITEABLE); 1941 } 1942 free_pv_entry(pmap, pv); 1943 if (pmap != locked_pmap) 1944 PMAP_UNLOCK(pmap); 1945 } 1946 } 1947 sched_unpin(); 1948} 1949 1950 1951/* 1952 * free the pv_entry back to the free list 1953 */ 1954static void 1955free_pv_entry(pmap_t pmap, pv_entry_t pv) 1956{ 1957 vm_page_t m; 1958 struct pv_chunk *pc; 1959 int idx, field, bit; 1960 1961 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1962 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1963 PV_STAT(pv_entry_frees++); 1964 PV_STAT(pv_entry_spare++); 1965 pv_entry_count--; 1966 pc = pv_to_chunk(pv); 1967 idx = pv - &pc->pc_pventry[0]; 1968 field = idx / 32; 1969 bit = idx % 32; 1970 pc->pc_map[field] |= 1ul << bit; 1971 /* move to head of list */ 1972 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 1973 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list); 1974 for (idx = 0; idx < _NPCM; idx++) 1975 if (pc->pc_map[idx] != pc_freemask[idx]) 1976 return; 1977 PV_STAT(pv_entry_spare -= _NPCPV); 1978 PV_STAT(pc_chunk_count--); 1979 PV_STAT(pc_chunk_frees++); 1980 /* entire chunk is free, return it */ 1981 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 1982 m = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc)); 1983 pmap_qremove((vm_offset_t)pc, 1); 1984 vm_page_unwire(m, 0); 1985 vm_page_free(m); 1986 pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc); 1987} 1988 1989/* 1990 * get a new pv_entry, allocating a block from the system 1991 * when needed. 1992 */ 1993static pv_entry_t 1994get_pv_entry(pmap_t pmap, int try) 1995{ 1996 static const struct timeval printinterval = { 60, 0 }; 1997 static struct timeval lastprint; 1998 static vm_pindex_t colour; 1999 struct vpgqueues *pq; 2000 int bit, field; 2001 pv_entry_t pv; 2002 struct pv_chunk *pc; 2003 vm_page_t m; 2004 2005 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2006 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2007 PV_STAT(pv_entry_allocs++); 2008 pv_entry_count++; 2009 if (pv_entry_count > pv_entry_high_water) 2010 if (ratecheck(&lastprint, &printinterval)) 2011 printf("Approaching the limit on PV entries, consider " 2012 "increasing either the vm.pmap.shpgperproc or the " 2013 "vm.pmap.pv_entry_max tunable.\n"); 2014 pq = NULL; 2015retry: 2016 pc = TAILQ_FIRST(&pmap->pm_pvchunk); 2017 if (pc != NULL) { 2018 for (field = 0; field < _NPCM; field++) { 2019 if (pc->pc_map[field]) { 2020 bit = bsfl(pc->pc_map[field]); 2021 break; 2022 } 2023 } 2024 if (field < _NPCM) { 2025 pv = &pc->pc_pventry[field * 32 + bit]; 2026 pc->pc_map[field] &= ~(1ul << bit); 2027 /* If this was the last item, move it to tail */ 2028 for (field = 0; field < _NPCM; field++) 2029 if (pc->pc_map[field] != 0) { 2030 PV_STAT(pv_entry_spare--); 2031 return (pv); /* not full, return */ 2032 } 2033 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 2034 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list); 2035 PV_STAT(pv_entry_spare--); 2036 return (pv); 2037 } 2038 } 2039 /* 2040 * Access to the ptelist "pv_vafree" is synchronized by the page 2041 * queues lock. If "pv_vafree" is currently non-empty, it will 2042 * remain non-empty until pmap_ptelist_alloc() completes. 2043 */ 2044 if (pv_vafree == 0 || (m = vm_page_alloc(NULL, colour, (pq == 2045 &vm_page_queues[PQ_ACTIVE] ? VM_ALLOC_SYSTEM : VM_ALLOC_NORMAL) | 2046 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) { 2047 if (try) { 2048 pv_entry_count--; 2049 PV_STAT(pc_chunk_tryfail++); 2050 return (NULL); 2051 } 2052 /* 2053 * Reclaim pv entries: At first, destroy mappings to 2054 * inactive pages. After that, if a pv chunk entry 2055 * is still needed, destroy mappings to active pages. 2056 */ 2057 if (pq == NULL) { 2058 PV_STAT(pmap_collect_inactive++); 2059 pq = &vm_page_queues[PQ_INACTIVE]; 2060 } else if (pq == &vm_page_queues[PQ_INACTIVE]) { 2061 PV_STAT(pmap_collect_active++); 2062 pq = &vm_page_queues[PQ_ACTIVE]; 2063 } else 2064 panic("get_pv_entry: increase vm.pmap.shpgperproc"); 2065 pmap_collect(pmap, pq); 2066 goto retry; 2067 } 2068 PV_STAT(pc_chunk_count++); 2069 PV_STAT(pc_chunk_allocs++); 2070 colour++; 2071 pc = (struct pv_chunk *)pmap_ptelist_alloc(&pv_vafree); 2072 pmap_qenter((vm_offset_t)pc, &m, 1); 2073 pc->pc_pmap = pmap; 2074 pc->pc_map[0] = pc_freemask[0] & ~1ul; /* preallocated bit 0 */ 2075 for (field = 1; field < _NPCM; field++) 2076 pc->pc_map[field] = pc_freemask[field]; 2077 pv = &pc->pc_pventry[0]; 2078 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list); 2079 PV_STAT(pv_entry_spare += _NPCPV - 1); 2080 return (pv); 2081} 2082 2083static __inline pv_entry_t 2084pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va) 2085{ 2086 pv_entry_t pv; 2087 2088 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2089 TAILQ_FOREACH(pv, &pvh->pv_list, pv_list) { 2090 if (pmap == PV_PMAP(pv) && va == pv->pv_va) { 2091 TAILQ_REMOVE(&pvh->pv_list, pv, pv_list); 2092 break; 2093 } 2094 } 2095 return (pv); 2096} 2097 2098static void 2099pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa) 2100{ 2101 struct md_page *pvh; 2102 pv_entry_t pv; 2103 vm_offset_t va_last; 2104 vm_page_t m; 2105 2106 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2107 KASSERT((pa & PDRMASK) == 0, 2108 ("pmap_pv_demote_pde: pa is not 4mpage aligned")); 2109 2110 /* 2111 * Transfer the 4mpage's pv entry for this mapping to the first 2112 * page's pv list. 2113 */ 2114 pvh = pa_to_pvh(pa); 2115 va = trunc_4mpage(va); 2116 pv = pmap_pvh_remove(pvh, pmap, va); 2117 KASSERT(pv != NULL, ("pmap_pv_demote_pde: pv not found")); 2118 m = PHYS_TO_VM_PAGE(pa); 2119 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list); 2120 /* Instantiate the remaining NPTEPG - 1 pv entries. */ 2121 va_last = va + NBPDR - PAGE_SIZE; 2122 do { 2123 m++; 2124 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 2125 ("pmap_pv_demote_pde: page %p is not managed", m)); 2126 va += PAGE_SIZE; 2127 pmap_insert_entry(pmap, va, m); 2128 } while (va < va_last); 2129} 2130 2131static void 2132pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa) 2133{ 2134 struct md_page *pvh; 2135 pv_entry_t pv; 2136 vm_offset_t va_last; 2137 vm_page_t m; 2138 2139 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2140 KASSERT((pa & PDRMASK) == 0, 2141 ("pmap_pv_promote_pde: pa is not 4mpage aligned")); 2142 2143 /* 2144 * Transfer the first page's pv entry for this mapping to the 2145 * 4mpage's pv list. Aside from avoiding the cost of a call 2146 * to get_pv_entry(), a transfer avoids the possibility that 2147 * get_pv_entry() calls pmap_collect() and that pmap_collect() 2148 * removes one of the mappings that is being promoted. 2149 */ 2150 m = PHYS_TO_VM_PAGE(pa); 2151 va = trunc_4mpage(va); 2152 pv = pmap_pvh_remove(&m->md, pmap, va); 2153 KASSERT(pv != NULL, ("pmap_pv_promote_pde: pv not found")); 2154 pvh = pa_to_pvh(pa); 2155 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_list); 2156 /* Free the remaining NPTEPG - 1 pv entries. */ 2157 va_last = va + NBPDR - PAGE_SIZE; 2158 do { 2159 m++; 2160 va += PAGE_SIZE; 2161 pmap_pvh_free(&m->md, pmap, va); 2162 } while (va < va_last); 2163} 2164 2165static void 2166pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va) 2167{ 2168 pv_entry_t pv; 2169 2170 pv = pmap_pvh_remove(pvh, pmap, va); 2171 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found")); 2172 free_pv_entry(pmap, pv); 2173} 2174 2175static void 2176pmap_remove_entry(pmap_t pmap, vm_page_t m, vm_offset_t va) 2177{ 2178 struct md_page *pvh; 2179 2180 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2181 pmap_pvh_free(&m->md, pmap, va); 2182 if (TAILQ_EMPTY(&m->md.pv_list)) { 2183 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 2184 if (TAILQ_EMPTY(&pvh->pv_list)) 2185 vm_page_flag_clear(m, PG_WRITEABLE); 2186 } 2187} 2188 2189/* 2190 * Create a pv entry for page at pa for 2191 * (pmap, va). 2192 */ 2193static void 2194pmap_insert_entry(pmap_t pmap, vm_offset_t va, vm_page_t m) 2195{ 2196 pv_entry_t pv; 2197 2198 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2199 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2200 pv = get_pv_entry(pmap, FALSE); 2201 pv->pv_va = va; 2202 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list); 2203} 2204 2205/* 2206 * Conditionally create a pv entry. 2207 */ 2208static boolean_t 2209pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m) 2210{ 2211 pv_entry_t pv; 2212 2213 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2214 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2215 if (pv_entry_count < pv_entry_high_water && 2216 (pv = get_pv_entry(pmap, TRUE)) != NULL) { 2217 pv->pv_va = va; 2218 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list); 2219 return (TRUE); 2220 } else 2221 return (FALSE); 2222} 2223 2224/* 2225 * Create the pv entries for each of the pages within a superpage. 2226 */ 2227static boolean_t 2228pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, vm_page_t m) 2229{ 2230 struct md_page *pvh; 2231 pv_entry_t pv; 2232 2233 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2234 if (pv_entry_count < pv_entry_high_water && 2235 (pv = get_pv_entry(pmap, TRUE)) != NULL) { 2236 pv->pv_va = va; 2237 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 2238 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_list); 2239 return (TRUE); 2240 } else 2241 return (FALSE); 2242} 2243 2244/* 2245 * Tries to demote a 2- or 4MB page mapping. 2246 */ 2247static boolean_t 2248pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va) 2249{ 2250 pd_entry_t newpde, oldpde; 2251 pmap_t allpmaps_entry; 2252 pt_entry_t *firstpte, newpte, *pte; 2253 vm_paddr_t mptepa; 2254 vm_page_t free, mpte; 2255 2256 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2257 mpte = pmap_lookup_pt_page(pmap, va); 2258 if (mpte != NULL) 2259 pmap_remove_pt_page(pmap, mpte); 2260 else { 2261 KASSERT((*pde & PG_W) == 0, 2262 ("pmap_demote_pde: page table page for a wired mapping" 2263 " is missing")); 2264 free = NULL; 2265 pmap_remove_pde(pmap, pde, trunc_4mpage(va), &free); 2266 pmap_invalidate_page(pmap, trunc_4mpage(va)); 2267 pmap_free_zero_pages(free); 2268 CTR2(KTR_PMAP, "pmap_demote_pde: failure for va %#x" 2269 " in pmap %p", va, pmap); 2270 return (FALSE); 2271 } 2272 mptepa = VM_PAGE_TO_PHYS(mpte); 2273 2274 /* 2275 * Temporarily map the page table page (mpte) into the kernel's 2276 * address space at either PADDR1 or PADDR2. 2277 */ 2278 if (curthread->td_pinned > 0 && mtx_owned(&vm_page_queue_mtx)) { 2279 if ((*PMAP1 & PG_FRAME) != mptepa) { 2280 *PMAP1 = mptepa | PG_RW | PG_V | PG_A | PG_M; 2281#ifdef SMP 2282 PMAP1cpu = PCPU_GET(cpuid); 2283#endif 2284 invlcaddr(PADDR1); 2285 PMAP1changed++; 2286 } else 2287#ifdef SMP 2288 if (PMAP1cpu != PCPU_GET(cpuid)) { 2289 PMAP1cpu = PCPU_GET(cpuid); 2290 invlcaddr(PADDR1); 2291 PMAP1changedcpu++; 2292 } else 2293#endif 2294 PMAP1unchanged++; 2295 firstpte = PADDR1; 2296 } else { 2297 mtx_lock(&PMAP2mutex); 2298 if ((*PMAP2 & PG_FRAME) != mptepa) { 2299 *PMAP2 = mptepa | PG_RW | PG_V | PG_A | PG_M; 2300 pmap_invalidate_page(kernel_pmap, (vm_offset_t)PADDR2); 2301 } 2302 firstpte = PADDR2; 2303 } 2304 oldpde = *pde; 2305 newpde = mptepa | PG_M | PG_A | (oldpde & PG_U) | PG_RW | PG_V; 2306 KASSERT((oldpde & (PG_A | PG_V)) == (PG_A | PG_V), 2307 ("pmap_demote_pde: oldpde is missing PG_A and/or PG_V")); 2308 KASSERT((oldpde & (PG_M | PG_RW)) != PG_RW, 2309 ("pmap_demote_pde: oldpde is missing PG_M")); 2310 KASSERT((oldpde & PG_PS) != 0, 2311 ("pmap_demote_pde: oldpde is missing PG_PS")); 2312 newpte = oldpde & ~PG_PS; 2313 if ((newpte & PG_PDE_PAT) != 0) 2314 newpte ^= PG_PDE_PAT | PG_PTE_PAT; 2315 2316 /* 2317 * If the mapping has changed attributes, update the page table 2318 * entries. 2319 */ 2320 KASSERT((*firstpte & PG_FRAME) == (newpte & PG_FRAME), 2321 ("pmap_demote_pde: firstpte and newpte map different physical" 2322 " addresses")); 2323 if ((*firstpte & PG_PTE_PROMOTE) != (newpte & PG_PTE_PROMOTE)) 2324 for (pte = firstpte; pte < firstpte + NPTEPG; pte++) { 2325 *pte = newpte; 2326 newpte += PAGE_SIZE; 2327 } 2328 2329 /* 2330 * Demote the mapping. This pmap is locked. The old PDE has 2331 * PG_A set. If the old PDE has PG_RW set, it also has PG_M 2332 * set. Thus, there is no danger of a race with another 2333 * processor changing the setting of PG_A and/or PG_M between 2334 * the read above and the store below. 2335 */ 2336 if (pmap == kernel_pmap) { 2337 /* 2338 * A harmless race exists between this loop and the bcopy() 2339 * in pmap_pinit() that initializes the kernel segment of 2340 * the new page table. Specifically, that bcopy() may copy 2341 * the new PDE from the PTD, which is first in allpmaps, to 2342 * the new page table before this loop updates that new 2343 * page table. 2344 */ 2345 mtx_lock_spin(&allpmaps_lock); 2346 LIST_FOREACH(allpmaps_entry, &allpmaps, pm_list) { 2347 pde = pmap_pde(allpmaps_entry, va); 2348 KASSERT(*pde == newpde || (*pde & PG_PTE_PROMOTE) == 2349 (oldpde & PG_PTE_PROMOTE), 2350 ("pmap_demote_pde: pde was %#jx, expected %#jx", 2351 (uintmax_t)*pde, (uintmax_t)oldpde)); 2352 pde_store(pde, newpde); 2353 } 2354 mtx_unlock_spin(&allpmaps_lock); 2355 } else 2356 pde_store(pde, newpde); 2357 if (firstpte == PADDR2) 2358 mtx_unlock(&PMAP2mutex); 2359 2360 /* 2361 * Invalidate the recursive mapping of the page table page. 2362 */ 2363 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va)); 2364 2365 /* 2366 * Demote the pv entry. This depends on the earlier demotion 2367 * of the mapping. Specifically, the (re)creation of a per- 2368 * page pv entry might trigger the execution of pmap_collect(), 2369 * which might reclaim a newly (re)created per-page pv entry 2370 * and destroy the associated mapping. In order to destroy 2371 * the mapping, the PDE must have already changed from mapping 2372 * the 2mpage to referencing the page table page. 2373 */ 2374 if ((oldpde & PG_MANAGED) != 0) 2375 pmap_pv_demote_pde(pmap, va, oldpde & PG_FRAME); 2376 2377 pmap_pde_demotions++; 2378 CTR2(KTR_PMAP, "pmap_demote_pde: success for va %#x" 2379 " in pmap %p", va, pmap); 2380 return (TRUE); 2381} 2382 2383/* 2384 * pmap_remove_pde: do the things to unmap a superpage in a process 2385 */ 2386static void 2387pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva, 2388 vm_page_t *free) 2389{ 2390 struct md_page *pvh; 2391 pd_entry_t oldpde; 2392 vm_offset_t eva, va; 2393 vm_page_t m, mpte; 2394 2395 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2396 KASSERT((sva & PDRMASK) == 0, 2397 ("pmap_remove_pde: sva is not 4mpage aligned")); 2398 oldpde = pte_load_clear(pdq); 2399 if (oldpde & PG_W) 2400 pmap->pm_stats.wired_count -= NBPDR / PAGE_SIZE; 2401 2402 /* 2403 * Machines that don't support invlpg, also don't support 2404 * PG_G. 2405 */ 2406 if (oldpde & PG_G) 2407 pmap_invalidate_page(kernel_pmap, sva); 2408 pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE; 2409 if (oldpde & PG_MANAGED) { 2410 pvh = pa_to_pvh(oldpde & PG_FRAME); 2411 pmap_pvh_free(pvh, pmap, sva); 2412 eva = sva + NBPDR; 2413 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_FRAME); 2414 va < eva; va += PAGE_SIZE, m++) { 2415 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW)) 2416 vm_page_dirty(m); 2417 if (oldpde & PG_A) 2418 vm_page_flag_set(m, PG_REFERENCED); 2419 if (TAILQ_EMPTY(&m->md.pv_list) && 2420 TAILQ_EMPTY(&pvh->pv_list)) 2421 vm_page_flag_clear(m, PG_WRITEABLE); 2422 } 2423 } 2424 if (pmap == kernel_pmap) { 2425 if (!pmap_demote_pde(pmap, pdq, sva)) 2426 panic("pmap_remove_pde: failed demotion"); 2427 } else { 2428 mpte = pmap_lookup_pt_page(pmap, sva); 2429 if (mpte != NULL) { 2430 pmap_remove_pt_page(pmap, mpte); 2431 KASSERT(mpte->wire_count == NPTEPG, 2432 ("pmap_remove_pde: pte page wire count error")); 2433 mpte->wire_count = 0; 2434 pmap_add_delayed_free_list(mpte, free, FALSE); 2435 atomic_subtract_int(&cnt.v_wire_count, 1); 2436 } 2437 } 2438} 2439 2440/* 2441 * pmap_remove_pte: do the things to unmap a page in a process 2442 */ 2443static int 2444pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t va, vm_page_t *free) 2445{ 2446 pt_entry_t oldpte; 2447 vm_page_t m; 2448 2449 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2450 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2451 oldpte = pte_load_clear(ptq); 2452 if (oldpte & PG_W) 2453 pmap->pm_stats.wired_count -= 1; 2454 /* 2455 * Machines that don't support invlpg, also don't support 2456 * PG_G. 2457 */ 2458 if (oldpte & PG_G) 2459 pmap_invalidate_page(kernel_pmap, va); 2460 pmap->pm_stats.resident_count -= 1; 2461 if (oldpte & PG_MANAGED) { 2462 m = PHYS_TO_VM_PAGE(oldpte & PG_FRAME); 2463 if ((oldpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) 2464 vm_page_dirty(m); 2465 if (oldpte & PG_A) 2466 vm_page_flag_set(m, PG_REFERENCED); 2467 pmap_remove_entry(pmap, m, va); 2468 } 2469 return (pmap_unuse_pt(pmap, va, free)); 2470} 2471 2472/* 2473 * Remove a single page from a process address space 2474 */ 2475static void 2476pmap_remove_page(pmap_t pmap, vm_offset_t va, vm_page_t *free) 2477{ 2478 pt_entry_t *pte; 2479 2480 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2481 KASSERT(curthread->td_pinned > 0, ("curthread not pinned")); 2482 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2483 if ((pte = pmap_pte_quick(pmap, va)) == NULL || *pte == 0) 2484 return; 2485 pmap_remove_pte(pmap, pte, va, free); 2486 pmap_invalidate_page(pmap, va); 2487} 2488 2489/* 2490 * Remove the given range of addresses from the specified map. 2491 * 2492 * It is assumed that the start and end are properly 2493 * rounded to the page size. 2494 */ 2495void 2496pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 2497{ 2498 vm_offset_t pdnxt; 2499 pd_entry_t ptpaddr; 2500 pt_entry_t *pte; 2501 vm_page_t free = NULL; 2502 int anyvalid; 2503 2504 /* 2505 * Perform an unsynchronized read. This is, however, safe. 2506 */ 2507 if (pmap->pm_stats.resident_count == 0) 2508 return; 2509 2510 anyvalid = 0; 2511 2512 vm_page_lock_queues(); 2513 sched_pin(); 2514 PMAP_LOCK(pmap); 2515 2516 /* 2517 * special handling of removing one page. a very 2518 * common operation and easy to short circuit some 2519 * code. 2520 */ 2521 if ((sva + PAGE_SIZE == eva) && 2522 ((pmap->pm_pdir[(sva >> PDRSHIFT)] & PG_PS) == 0)) { 2523 pmap_remove_page(pmap, sva, &free); 2524 goto out; 2525 } 2526 2527 for (; sva < eva; sva = pdnxt) { 2528 unsigned pdirindex; 2529 2530 /* 2531 * Calculate index for next page table. 2532 */ 2533 pdnxt = (sva + NBPDR) & ~PDRMASK; 2534 if (pdnxt < sva) 2535 pdnxt = eva; 2536 if (pmap->pm_stats.resident_count == 0) 2537 break; 2538 2539 pdirindex = sva >> PDRSHIFT; 2540 ptpaddr = pmap->pm_pdir[pdirindex]; 2541 2542 /* 2543 * Weed out invalid mappings. Note: we assume that the page 2544 * directory table is always allocated, and in kernel virtual. 2545 */ 2546 if (ptpaddr == 0) 2547 continue; 2548 2549 /* 2550 * Check for large page. 2551 */ 2552 if ((ptpaddr & PG_PS) != 0) { 2553 /* 2554 * Are we removing the entire large page? If not, 2555 * demote the mapping and fall through. 2556 */ 2557 if (sva + NBPDR == pdnxt && eva >= pdnxt) { 2558 /* 2559 * The TLB entry for a PG_G mapping is 2560 * invalidated by pmap_remove_pde(). 2561 */ 2562 if ((ptpaddr & PG_G) == 0) 2563 anyvalid = 1; 2564 pmap_remove_pde(pmap, 2565 &pmap->pm_pdir[pdirindex], sva, &free); 2566 continue; 2567 } else if (!pmap_demote_pde(pmap, 2568 &pmap->pm_pdir[pdirindex], sva)) { 2569 /* The large page mapping was destroyed. */ 2570 continue; 2571 } 2572 } 2573 2574 /* 2575 * Limit our scan to either the end of the va represented 2576 * by the current page table page, or to the end of the 2577 * range being removed. 2578 */ 2579 if (pdnxt > eva) 2580 pdnxt = eva; 2581 2582 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++, 2583 sva += PAGE_SIZE) { 2584 if (*pte == 0) 2585 continue; 2586 2587 /* 2588 * The TLB entry for a PG_G mapping is invalidated 2589 * by pmap_remove_pte(). 2590 */ 2591 if ((*pte & PG_G) == 0) 2592 anyvalid = 1; 2593 if (pmap_remove_pte(pmap, pte, sva, &free)) 2594 break; 2595 } 2596 } 2597out: 2598 sched_unpin(); 2599 if (anyvalid) 2600 pmap_invalidate_all(pmap); 2601 vm_page_unlock_queues(); 2602 PMAP_UNLOCK(pmap); 2603 pmap_free_zero_pages(free); 2604} 2605 2606/* 2607 * Routine: pmap_remove_all 2608 * Function: 2609 * Removes this physical page from 2610 * all physical maps in which it resides. 2611 * Reflects back modify bits to the pager. 2612 * 2613 * Notes: 2614 * Original versions of this routine were very 2615 * inefficient because they iteratively called 2616 * pmap_remove (slow...) 2617 */ 2618 2619void 2620pmap_remove_all(vm_page_t m) 2621{ 2622 struct md_page *pvh; 2623 pv_entry_t pv; 2624 pmap_t pmap; 2625 pt_entry_t *pte, tpte; 2626 pd_entry_t *pde; 2627 vm_offset_t va; 2628 vm_page_t free; 2629 2630#if 0 2631 KASSERT((m->flags & PG_FICTITIOUS) == 0, 2632 ("pmap_remove_all: page %p is fictitious", m)); 2633#endif 2634 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2635 sched_pin(); 2636 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 2637 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) { 2638 va = pv->pv_va; 2639 pmap = PV_PMAP(pv); 2640 PMAP_LOCK(pmap); 2641 pde = pmap_pde(pmap, va); 2642 (void)pmap_demote_pde(pmap, pde, va); 2643 PMAP_UNLOCK(pmap); 2644 } 2645 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) { 2646 pmap = PV_PMAP(pv); 2647 PMAP_LOCK(pmap); 2648 pmap->pm_stats.resident_count--; 2649 pde = pmap_pde(pmap, pv->pv_va); 2650 KASSERT((*pde & PG_PS) == 0, ("pmap_remove_all: found" 2651 " a 4mpage in page %p's pv list", m)); 2652 pte = pmap_pte_quick(pmap, pv->pv_va); 2653 tpte = pte_load_clear(pte); 2654 if (tpte & PG_W) 2655 pmap->pm_stats.wired_count--; 2656 if (tpte & PG_A) 2657 vm_page_flag_set(m, PG_REFERENCED); 2658 2659 /* 2660 * Update the vm_page_t clean and reference bits. 2661 */ 2662 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) 2663 vm_page_dirty(m); 2664 free = NULL; 2665 pmap_unuse_pt(pmap, pv->pv_va, &free); 2666 pmap_invalidate_page(pmap, pv->pv_va); 2667 pmap_free_zero_pages(free); 2668 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list); 2669 free_pv_entry(pmap, pv); 2670 PMAP_UNLOCK(pmap); 2671 } 2672 vm_page_flag_clear(m, PG_WRITEABLE); 2673 sched_unpin(); 2674} 2675 2676/* 2677 * pmap_protect_pde: do the things to protect a 4mpage in a process 2678 */ 2679static boolean_t 2680pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva, vm_prot_t prot) 2681{ 2682 pd_entry_t newpde, oldpde; 2683 vm_offset_t eva, va; 2684 vm_page_t m; 2685 boolean_t anychanged; 2686 2687 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2688 KASSERT((sva & PDRMASK) == 0, 2689 ("pmap_protect_pde: sva is not 4mpage aligned")); 2690 anychanged = FALSE; 2691retry: 2692 oldpde = newpde = *pde; 2693 if (oldpde & PG_MANAGED) { 2694 eva = sva + NBPDR; 2695 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_FRAME); 2696 va < eva; va += PAGE_SIZE, m++) { 2697 /* 2698 * In contrast to the analogous operation on a 4KB page 2699 * mapping, the mapping's PG_A flag is not cleared and 2700 * the page's PG_REFERENCED flag is not set. The 2701 * reason is that pmap_demote_pde() expects that a 2/4MB 2702 * page mapping with a stored page table page has PG_A 2703 * set. 2704 */ 2705 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW)) 2706 vm_page_dirty(m); 2707 } 2708 } 2709 if ((prot & VM_PROT_WRITE) == 0) 2710 newpde &= ~(PG_RW | PG_M); 2711#ifdef PAE 2712 if ((prot & VM_PROT_EXECUTE) == 0) 2713 newpde |= pg_nx; 2714#endif 2715 if (newpde != oldpde) { 2716 if (!pde_cmpset(pde, oldpde, newpde)) 2717 goto retry; 2718 if (oldpde & PG_G) 2719 pmap_invalidate_page(pmap, sva); 2720 else 2721 anychanged = TRUE; 2722 } 2723 return (anychanged); 2724} 2725 2726/* 2727 * Set the physical protection on the 2728 * specified range of this map as requested. 2729 */ 2730void 2731pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot) 2732{ 2733 vm_offset_t pdnxt; 2734 pd_entry_t ptpaddr; 2735 pt_entry_t *pte; 2736 int anychanged; 2737 2738 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 2739 pmap_remove(pmap, sva, eva); 2740 return; 2741 } 2742 2743#ifdef PAE 2744 if ((prot & (VM_PROT_WRITE|VM_PROT_EXECUTE)) == 2745 (VM_PROT_WRITE|VM_PROT_EXECUTE)) 2746 return; 2747#else 2748 if (prot & VM_PROT_WRITE) 2749 return; 2750#endif 2751 2752 anychanged = 0; 2753 2754 vm_page_lock_queues(); 2755 sched_pin(); 2756 PMAP_LOCK(pmap); 2757 for (; sva < eva; sva = pdnxt) { 2758 pt_entry_t obits, pbits; 2759 unsigned pdirindex; 2760 2761 pdnxt = (sva + NBPDR) & ~PDRMASK; 2762 if (pdnxt < sva) 2763 pdnxt = eva; 2764 2765 pdirindex = sva >> PDRSHIFT; 2766 ptpaddr = pmap->pm_pdir[pdirindex]; 2767 2768 /* 2769 * Weed out invalid mappings. Note: we assume that the page 2770 * directory table is always allocated, and in kernel virtual. 2771 */ 2772 if (ptpaddr == 0) 2773 continue; 2774 2775 /* 2776 * Check for large page. 2777 */ 2778 if ((ptpaddr & PG_PS) != 0) { 2779 /* 2780 * Are we protecting the entire large page? If not, 2781 * demote the mapping and fall through. 2782 */ 2783 if (sva + NBPDR == pdnxt && eva >= pdnxt) { 2784 /* 2785 * The TLB entry for a PG_G mapping is 2786 * invalidated by pmap_protect_pde(). 2787 */ 2788 if (pmap_protect_pde(pmap, 2789 &pmap->pm_pdir[pdirindex], sva, prot)) 2790 anychanged = 1; 2791 continue; 2792 } else if (!pmap_demote_pde(pmap, 2793 &pmap->pm_pdir[pdirindex], sva)) { 2794 /* The large page mapping was destroyed. */ 2795 continue; 2796 } 2797 } 2798 2799 if (pdnxt > eva) 2800 pdnxt = eva; 2801 2802 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++, 2803 sva += PAGE_SIZE) { 2804 vm_page_t m; 2805 2806retry: 2807 /* 2808 * Regardless of whether a pte is 32 or 64 bits in 2809 * size, PG_RW, PG_A, and PG_M are among the least 2810 * significant 32 bits. 2811 */ 2812 obits = pbits = *pte; 2813 if ((pbits & PG_V) == 0) 2814 continue; 2815 if (pbits & PG_MANAGED) { 2816 m = NULL; 2817 if (pbits & PG_A) { 2818 m = PHYS_TO_VM_PAGE(pbits & PG_FRAME); 2819 vm_page_flag_set(m, PG_REFERENCED); 2820 pbits &= ~PG_A; 2821 } 2822 if ((pbits & (PG_M | PG_RW)) == (PG_M | PG_RW)) { 2823 if (m == NULL) 2824 m = PHYS_TO_VM_PAGE(pbits & PG_FRAME); 2825 vm_page_dirty(m); 2826 } 2827 } 2828 2829 if ((prot & VM_PROT_WRITE) == 0) 2830 pbits &= ~(PG_RW | PG_M); 2831#ifdef PAE 2832 if ((prot & VM_PROT_EXECUTE) == 0) 2833 pbits |= pg_nx; 2834#endif 2835 2836 if (pbits != obits) { 2837#ifdef PAE 2838 if (!atomic_cmpset_64(pte, obits, pbits)) 2839 goto retry; 2840#else 2841 if (!atomic_cmpset_int((u_int *)pte, obits, 2842 pbits)) 2843 goto retry; 2844#endif 2845 if (obits & PG_G) 2846 pmap_invalidate_page(pmap, sva); 2847 else 2848 anychanged = 1; 2849 } 2850 } 2851 } 2852 sched_unpin(); 2853 if (anychanged) 2854 pmap_invalidate_all(pmap); 2855 vm_page_unlock_queues(); 2856 PMAP_UNLOCK(pmap); 2857} 2858 2859/* 2860 * Tries to promote the 512 or 1024, contiguous 4KB page mappings that are 2861 * within a single page table page to a single 2- or 4MB page mapping. For 2862 * promotion to occur, two conditions must be met: (1) the 4KB page mappings 2863 * must map aligned, contiguous physical memory and (2) the 4KB page mappings 2864 * must have identical characteristics. 2865 * 2866 * Managed (PG_MANAGED) mappings within the kernel address space are not 2867 * promoted. The reason is that kernel PDEs are replicated in each pmap but 2868 * pmap_clear_ptes() and pmap_ts_referenced() only read the PDE from the kernel 2869 * pmap. 2870 */ 2871static void 2872pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va) 2873{ 2874 pd_entry_t newpde; 2875 pmap_t allpmaps_entry; 2876 pt_entry_t *firstpte, oldpte, *pte; 2877 vm_offset_t oldpteva; 2878 vm_paddr_t pa; 2879 vm_page_t mpte; 2880 2881 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2882 firstpte = vtopte(trunc_4mpage(va)); 2883 KASSERT((*firstpte & PG_V) != 0, 2884 ("pmap_promote_pde: firstpte is missing PG_V")); 2885 if ((*firstpte & PG_A) == 0) { 2886 pmap_pde_p_failures++; 2887 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x" 2888 " in pmap %p", va, pmap); 2889 return; 2890 } 2891 if ((*firstpte & PG_MANAGED) != 0 && pmap == kernel_pmap) { 2892 pmap_pde_p_failures++; 2893 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x" 2894 " in pmap %p", va, pmap); 2895 return; 2896 } 2897 pa = *firstpte & PG_PS_FRAME; 2898 newpde = *firstpte; 2899 if ((newpde & (PG_M | PG_RW)) == PG_RW) 2900 newpde &= ~PG_RW; 2901 2902 /* 2903 * Check all the ptes before promotion 2904 */ 2905 for (pte = firstpte; pte < firstpte + NPTEPG; pte++) { 2906retry: 2907 oldpte = *pte; 2908 if ((oldpte & PG_FRAME) != pa) { 2909 pmap_pde_p_failures++; 2910 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x" 2911 " in pmap %p", va, pmap); 2912 return; 2913 } 2914 if ((oldpte & (PG_M | PG_RW)) == PG_RW) { 2915 /* 2916 * When PG_M is already clear, PG_RW can be cleared 2917 * without a TLB invalidation. 2918 */ 2919 if (!atomic_cmpset_int((u_int *)pte, oldpte, 2920 oldpte & ~PG_RW)) 2921 goto retry; 2922 oldpte &= ~PG_RW; 2923 oldpteva = (oldpte & PG_FRAME & PDRMASK) | 2924 (va & ~PDRMASK); 2925 CTR2(KTR_PMAP, "pmap_promote_pde: protect for va %#x" 2926 " in pmap %p", oldpteva, pmap); 2927 } 2928 if ((oldpte & PG_PTE_PROMOTE) != (newpde & PG_PTE_PROMOTE)) { 2929 pmap_pde_p_failures++; 2930 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x" 2931 " in pmap %p", va, pmap); 2932 return; 2933 } 2934 pa += PAGE_SIZE; 2935 } 2936 2937 /* 2938 * Save the page table page in its current state until the PDE 2939 * mapping the superpage is demoted by pmap_demote_pde() or 2940 * destroyed by pmap_remove_pde(). 2941 */ 2942 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME); 2943 KASSERT(mpte >= vm_page_array && 2944 mpte < &vm_page_array[vm_page_array_size], 2945 ("pmap_promote_pde: page table page is out of range")); 2946 KASSERT(mpte->pindex == va >> PDRSHIFT, 2947 ("pmap_promote_pde: page table page's pindex is wrong")); 2948 pmap_insert_pt_page(pmap, mpte); 2949 2950 /* 2951 * Promote the pv entries. 2952 */ 2953 if ((newpde & PG_MANAGED) != 0) 2954 pmap_pv_promote_pde(pmap, va, newpde & PG_FRAME); 2955 2956 /* 2957 * Propagate the PAT index to its proper position. 2958 */ 2959 if ((newpde & PG_PTE_PAT) != 0) 2960 newpde ^= PG_PDE_PAT | PG_PTE_PAT; 2961 2962 /* 2963 * Map the superpage. 2964 */ 2965 if (pmap == kernel_pmap) { 2966 mtx_lock_spin(&allpmaps_lock); 2967 LIST_FOREACH(allpmaps_entry, &allpmaps, pm_list) { 2968 pde = pmap_pde(allpmaps_entry, va); 2969 pde_store(pde, PG_PS | newpde); 2970 } 2971 mtx_unlock_spin(&allpmaps_lock); 2972 } else 2973 pde_store(pde, PG_PS | newpde); 2974 2975 pmap_pde_promotions++; 2976 CTR2(KTR_PMAP, "pmap_promote_pde: success for va %#x" 2977 " in pmap %p", va, pmap); 2978} 2979 2980/* 2981 * Insert the given physical page (p) at 2982 * the specified virtual address (v) in the 2983 * target physical map with the protection requested. 2984 * 2985 * If specified, the page will be wired down, meaning 2986 * that the related pte can not be reclaimed. 2987 * 2988 * NB: This is the only routine which MAY NOT lazy-evaluate 2989 * or lose information. That is, this routine must actually 2990 * insert this page into the given map NOW. 2991 */ 2992void 2993pmap_enter(pmap_t pmap, vm_offset_t va, vm_prot_t access, vm_page_t m, 2994 vm_prot_t prot, boolean_t wired) 2995{ 2996 vm_paddr_t pa; 2997 pd_entry_t *pde; 2998 pt_entry_t *pte; 2999 vm_paddr_t opa; 3000 pt_entry_t origpte, newpte; 3001 vm_page_t mpte, om; 3002 boolean_t invlva; 3003 3004 va = trunc_page(va); 3005 KASSERT(va <= VM_MAX_KERNEL_ADDRESS, ("pmap_enter: toobig")); 3006 KASSERT(va < UPT_MIN_ADDRESS || va >= UPT_MAX_ADDRESS, 3007 ("pmap_enter: invalid to pmap_enter page table pages (va: 0x%x)", va)); 3008 3009 mpte = NULL; 3010 3011 vm_page_lock_queues(); 3012 PMAP_LOCK(pmap); 3013 sched_pin(); 3014 3015 /* 3016 * In the case that a page table page is not 3017 * resident, we are creating it here. 3018 */ 3019 if (va < VM_MAXUSER_ADDRESS) { 3020 mpte = pmap_allocpte(pmap, va, M_WAITOK); 3021 } 3022 3023 pde = pmap_pde(pmap, va); 3024 if ((*pde & PG_PS) != 0) 3025 panic("pmap_enter: attempted pmap_enter on 4MB page"); 3026 pte = pmap_pte_quick(pmap, va); 3027 3028 /* 3029 * Page Directory table entry not valid, we need a new PT page 3030 */ 3031 if (pte == NULL) { 3032 panic("pmap_enter: invalid page directory pdir=%#jx, va=%#x", 3033 (uintmax_t)pmap->pm_pdir[PTDPTDI], va); 3034 } 3035 3036 pa = VM_PAGE_TO_PHYS(m); 3037 om = NULL; 3038 origpte = *pte; 3039 opa = origpte & PG_FRAME; 3040 3041 /* 3042 * Mapping has not changed, must be protection or wiring change. 3043 */ 3044 if (origpte && (opa == pa)) { 3045 /* 3046 * Wiring change, just update stats. We don't worry about 3047 * wiring PT pages as they remain resident as long as there 3048 * are valid mappings in them. Hence, if a user page is wired, 3049 * the PT page will be also. 3050 */ 3051 if (wired && ((origpte & PG_W) == 0)) 3052 pmap->pm_stats.wired_count++; 3053 else if (!wired && (origpte & PG_W)) 3054 pmap->pm_stats.wired_count--; 3055 3056 /* 3057 * Remove extra pte reference 3058 */ 3059 if (mpte) 3060 mpte->wire_count--; 3061 3062 /* 3063 * We might be turning off write access to the page, 3064 * so we go ahead and sense modify status. 3065 */ 3066 if (origpte & PG_MANAGED) { 3067 om = m; 3068 pa |= PG_MANAGED; 3069 } 3070 goto validate; 3071 } 3072 /* 3073 * Mapping has changed, invalidate old range and fall through to 3074 * handle validating new mapping. 3075 */ 3076 if (opa) { 3077 if (origpte & PG_W) 3078 pmap->pm_stats.wired_count--; 3079 if (origpte & PG_MANAGED) { 3080 om = PHYS_TO_VM_PAGE(opa); 3081 pmap_remove_entry(pmap, om, va); 3082 } 3083 if (mpte != NULL) { 3084 mpte->wire_count--; 3085 KASSERT(mpte->wire_count > 0, 3086 ("pmap_enter: missing reference to page table page," 3087 " va: 0x%x", va)); 3088 } 3089 } else 3090 pmap->pm_stats.resident_count++; 3091 3092 /* 3093 * Enter on the PV list if part of our managed memory. 3094 */ 3095 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0) { 3096 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva, 3097 ("pmap_enter: managed mapping within the clean submap")); 3098 pmap_insert_entry(pmap, va, m); 3099 pa |= PG_MANAGED; 3100 } 3101 3102 /* 3103 * Increment counters 3104 */ 3105 if (wired) 3106 pmap->pm_stats.wired_count++; 3107 3108validate: 3109 /* 3110 * Now validate mapping with desired protection/wiring. 3111 */ 3112 newpte = (pt_entry_t)(pa | PG_V); 3113 if ((prot & VM_PROT_WRITE) != 0) { 3114 newpte |= PG_RW; 3115 vm_page_flag_set(m, PG_WRITEABLE); 3116 } 3117#ifdef PAE 3118 if ((prot & VM_PROT_EXECUTE) == 0) 3119 newpte |= pg_nx; 3120#endif 3121 if (wired) 3122 newpte |= PG_W; 3123 if (va < VM_MAXUSER_ADDRESS) 3124 newpte |= PG_U; 3125 if (pmap == kernel_pmap) 3126 newpte |= pgeflag; 3127 3128 /* 3129 * if the mapping or permission bits are different, we need 3130 * to update the pte. 3131 */ 3132 if ((origpte & ~(PG_M|PG_A)) != newpte) { 3133 newpte |= PG_A; 3134 if ((access & VM_PROT_WRITE) != 0) 3135 newpte |= PG_M; 3136 if (origpte & PG_V) { 3137 invlva = FALSE; 3138 origpte = pte_load_store(pte, newpte); 3139 if (origpte & PG_A) { 3140 if (origpte & PG_MANAGED) 3141 vm_page_flag_set(om, PG_REFERENCED); 3142 if (opa != VM_PAGE_TO_PHYS(m)) 3143 invlva = TRUE; 3144#ifdef PAE 3145 if ((origpte & PG_NX) == 0 && 3146 (newpte & PG_NX) != 0) 3147 invlva = TRUE; 3148#endif 3149 } 3150 if ((origpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) { 3151 if ((origpte & PG_MANAGED) != 0) 3152 vm_page_dirty(om); 3153 if ((prot & VM_PROT_WRITE) == 0) 3154 invlva = TRUE; 3155 } 3156 if (invlva) 3157 pmap_invalidate_page(pmap, va); 3158 } else 3159 pte_store(pte, newpte); 3160 } 3161 3162 /* 3163 * If both the page table page and the reservation are fully 3164 * populated, then attempt promotion. 3165 */ 3166 if ((mpte == NULL || mpte->wire_count == NPTEPG) && 3167 pg_ps_enabled && vm_reserv_level_iffullpop(m) == 0) 3168 pmap_promote_pde(pmap, pde, va); 3169 3170 sched_unpin(); 3171 vm_page_unlock_queues(); 3172 PMAP_UNLOCK(pmap); 3173} 3174 3175/* 3176 * Tries to create a 2- or 4MB page mapping. Returns TRUE if successful and 3177 * FALSE otherwise. Fails if (1) a page table page cannot be allocated without 3178 * blocking, (2) a mapping already exists at the specified virtual address, or 3179 * (3) a pv entry cannot be allocated without reclaiming another pv entry. 3180 */ 3181static boolean_t 3182pmap_enter_pde(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot) 3183{ 3184 pd_entry_t *pde, newpde; 3185 3186 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 3187 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 3188 pde = pmap_pde(pmap, va); 3189 if (*pde != 0) { 3190 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx" 3191 " in pmap %p", va, pmap); 3192 return (FALSE); 3193 } 3194 newpde = VM_PAGE_TO_PHYS(m) | PG_PS | PG_V; 3195 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0) { 3196 newpde |= PG_MANAGED; 3197 3198 /* 3199 * Abort this mapping if its PV entry could not be created. 3200 */ 3201 if (!pmap_pv_insert_pde(pmap, va, m)) { 3202 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx" 3203 " in pmap %p", va, pmap); 3204 return (FALSE); 3205 } 3206 } 3207#ifdef PAE 3208 if ((prot & VM_PROT_EXECUTE) == 0) 3209 newpde |= pg_nx; 3210#endif 3211 if (va < VM_MAXUSER_ADDRESS) 3212 newpde |= PG_U; 3213 3214 /* 3215 * Increment counters. 3216 */ 3217 pmap->pm_stats.resident_count += NBPDR / PAGE_SIZE; 3218 3219 /* 3220 * Map the superpage. 3221 */ 3222 pde_store(pde, newpde); 3223 3224 pmap_pde_mappings++; 3225 CTR2(KTR_PMAP, "pmap_enter_pde: success for va %#lx" 3226 " in pmap %p", va, pmap); 3227 return (TRUE); 3228} 3229 3230/* 3231 * Maps a sequence of resident pages belonging to the same object. 3232 * The sequence begins with the given page m_start. This page is 3233 * mapped at the given virtual address start. Each subsequent page is 3234 * mapped at a virtual address that is offset from start by the same 3235 * amount as the page is offset from m_start within the object. The 3236 * last page in the sequence is the page with the largest offset from 3237 * m_start that can be mapped at a virtual address less than the given 3238 * virtual address end. Not every virtual page between start and end 3239 * is mapped; only those for which a resident page exists with the 3240 * corresponding offset from m_start are mapped. 3241 */ 3242void 3243pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end, 3244 vm_page_t m_start, vm_prot_t prot) 3245{ 3246 vm_offset_t va; 3247 vm_page_t m, mpte; 3248 vm_pindex_t diff, psize; 3249 3250 VM_OBJECT_LOCK_ASSERT(m_start->object, MA_OWNED); 3251 psize = atop(end - start); 3252 mpte = NULL; 3253 m = m_start; 3254 PMAP_LOCK(pmap); 3255 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 3256 va = start + ptoa(diff); 3257 if ((va & PDRMASK) == 0 && va + NBPDR <= end && 3258 (VM_PAGE_TO_PHYS(m) & PDRMASK) == 0 && 3259 pg_ps_enabled && vm_reserv_level_iffullpop(m) == 0 && 3260 pmap_enter_pde(pmap, va, m, prot)) 3261 m = &m[NBPDR / PAGE_SIZE - 1]; 3262 else 3263 mpte = pmap_enter_quick_locked(pmap, va, m, prot, 3264 mpte); 3265 m = TAILQ_NEXT(m, listq); 3266 } 3267 PMAP_UNLOCK(pmap); 3268} 3269 3270/* 3271 * this code makes some *MAJOR* assumptions: 3272 * 1. Current pmap & pmap exists. 3273 * 2. Not wired. 3274 * 3. Read access. 3275 * 4. No page table pages. 3276 * but is *MUCH* faster than pmap_enter... 3277 */ 3278 3279void 3280pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot) 3281{ 3282 3283 PMAP_LOCK(pmap); 3284 (void) pmap_enter_quick_locked(pmap, va, m, prot, NULL); 3285 PMAP_UNLOCK(pmap); 3286} 3287 3288static vm_page_t 3289pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m, 3290 vm_prot_t prot, vm_page_t mpte) 3291{ 3292 pt_entry_t *pte; 3293 vm_paddr_t pa; 3294 vm_page_t free; 3295 3296 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva || 3297 (m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0, 3298 ("pmap_enter_quick_locked: managed mapping within the clean submap")); 3299 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 3300 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 3301 3302 /* 3303 * In the case that a page table page is not 3304 * resident, we are creating it here. 3305 */ 3306 if (va < VM_MAXUSER_ADDRESS) { 3307 unsigned ptepindex; 3308 pd_entry_t ptepa; 3309 3310 /* 3311 * Calculate pagetable page index 3312 */ 3313 ptepindex = va >> PDRSHIFT; 3314 if (mpte && (mpte->pindex == ptepindex)) { 3315 mpte->wire_count++; 3316 } else { 3317 /* 3318 * Get the page directory entry 3319 */ 3320 ptepa = pmap->pm_pdir[ptepindex]; 3321 3322 /* 3323 * If the page table page is mapped, we just increment 3324 * the hold count, and activate it. 3325 */ 3326 if (ptepa) { 3327 if (ptepa & PG_PS) 3328 return (NULL); 3329 mpte = PHYS_TO_VM_PAGE(ptepa & PG_FRAME); 3330 mpte->wire_count++; 3331 } else { 3332 mpte = _pmap_allocpte(pmap, ptepindex, 3333 M_NOWAIT); 3334 if (mpte == NULL) 3335 return (mpte); 3336 } 3337 } 3338 } else { 3339 mpte = NULL; 3340 } 3341 3342 /* 3343 * This call to vtopte makes the assumption that we are 3344 * entering the page into the current pmap. In order to support 3345 * quick entry into any pmap, one would likely use pmap_pte_quick. 3346 * But that isn't as quick as vtopte. 3347 */ 3348 pte = vtopte(va); 3349 if (*pte) { 3350 if (mpte != NULL) { 3351 mpte->wire_count--; 3352 mpte = NULL; 3353 } 3354 return (mpte); 3355 } 3356 3357 /* 3358 * Enter on the PV list if part of our managed memory. 3359 */ 3360 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0 && 3361 !pmap_try_insert_pv_entry(pmap, va, m)) { 3362 if (mpte != NULL) { 3363 free = NULL; 3364 if (pmap_unwire_pte_hold(pmap, mpte, &free)) { 3365 pmap_invalidate_page(pmap, va); 3366 pmap_free_zero_pages(free); 3367 } 3368 3369 mpte = NULL; 3370 } 3371 return (mpte); 3372 } 3373 3374 /* 3375 * Increment counters 3376 */ 3377 pmap->pm_stats.resident_count++; 3378 3379 pa = VM_PAGE_TO_PHYS(m); 3380#ifdef PAE 3381 if ((prot & VM_PROT_EXECUTE) == 0) 3382 pa |= pg_nx; 3383#endif 3384 3385 /* 3386 * Now validate mapping with RO protection 3387 */ 3388 if (m->flags & (PG_FICTITIOUS|PG_UNMANAGED)) 3389 pte_store(pte, pa | PG_V | PG_U); 3390 else 3391 pte_store(pte, pa | PG_V | PG_U | PG_MANAGED); 3392 return mpte; 3393} 3394 3395/* 3396 * Make a temporary mapping for a physical address. This is only intended 3397 * to be used for panic dumps. 3398 */ 3399void * 3400pmap_kenter_temporary(vm_paddr_t pa, int i) 3401{ 3402 vm_offset_t va; 3403 3404 va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE); 3405 pmap_kenter(va, pa); 3406 invlpg(va); 3407 return ((void *)crashdumpmap); 3408} 3409 3410/* 3411 * This code maps large physical mmap regions into the 3412 * processor address space. Note that some shortcuts 3413 * are taken, but the code works. 3414 */ 3415void 3416pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, 3417 vm_object_t object, vm_pindex_t pindex, 3418 vm_size_t size) 3419{ 3420 vm_page_t p; 3421 3422 VM_OBJECT_LOCK_ASSERT(object, MA_OWNED); 3423 KASSERT(object->type == OBJT_DEVICE, 3424 ("pmap_object_init_pt: non-device object")); 3425 if (pseflag && 3426 ((addr & (NBPDR - 1)) == 0) && ((size & (NBPDR - 1)) == 0)) { 3427 int i; 3428 vm_page_t m[1]; 3429 unsigned int ptepindex; 3430 int npdes; 3431 pd_entry_t ptepa; 3432 3433 PMAP_LOCK(pmap); 3434 if (pmap->pm_pdir[ptepindex = (addr >> PDRSHIFT)]) 3435 goto out; 3436 PMAP_UNLOCK(pmap); 3437retry: 3438 p = vm_page_lookup(object, pindex); 3439 if (p != NULL) { 3440 if (vm_page_sleep_if_busy(p, FALSE, "init4p")) 3441 goto retry; 3442 } else { 3443 p = vm_page_alloc(object, pindex, VM_ALLOC_NORMAL); 3444 if (p == NULL) 3445 return; 3446 m[0] = p; 3447 3448 if (vm_pager_get_pages(object, m, 1, 0) != VM_PAGER_OK) { 3449 vm_page_lock_queues(); 3450 vm_page_free(p); 3451 vm_page_unlock_queues(); 3452 return; 3453 } 3454 3455 p = vm_page_lookup(object, pindex); 3456 vm_page_lock_queues(); 3457 vm_page_wakeup(p); 3458 vm_page_unlock_queues(); 3459 } 3460 3461 ptepa = VM_PAGE_TO_PHYS(p); 3462 if (ptepa & (NBPDR - 1)) 3463 return; 3464 3465 p->valid = VM_PAGE_BITS_ALL; 3466 3467 PMAP_LOCK(pmap); 3468 pmap->pm_stats.resident_count += size >> PAGE_SHIFT; 3469 npdes = size >> PDRSHIFT; 3470 for(i = 0; i < npdes; i++) { 3471 pde_store(&pmap->pm_pdir[ptepindex], 3472 ptepa | PG_U | PG_RW | PG_V | PG_PS); 3473 ptepa += NBPDR; 3474 ptepindex += 1; 3475 } 3476 pmap_invalidate_all(pmap); 3477out: 3478 PMAP_UNLOCK(pmap); 3479 } 3480} 3481 3482/* 3483 * Routine: pmap_change_wiring 3484 * Function: Change the wiring attribute for a map/virtual-address 3485 * pair. 3486 * In/out conditions: 3487 * The mapping must already exist in the pmap. 3488 */ 3489void 3490pmap_change_wiring(pmap_t pmap, vm_offset_t va, boolean_t wired) 3491{ 3492 pd_entry_t *pde; 3493 pt_entry_t *pte; 3494 boolean_t are_queues_locked; 3495 3496 are_queues_locked = FALSE; 3497retry: 3498 PMAP_LOCK(pmap); 3499 pde = pmap_pde(pmap, va); 3500 if ((*pde & PG_PS) != 0) { 3501 if (!wired != ((*pde & PG_W) == 0)) { 3502 if (!are_queues_locked) { 3503 are_queues_locked = TRUE; 3504 if (!mtx_trylock(&vm_page_queue_mtx)) { 3505 PMAP_UNLOCK(pmap); 3506 vm_page_lock_queues(); 3507 goto retry; 3508 } 3509 } 3510 if (!pmap_demote_pde(pmap, pde, va)) 3511 panic("pmap_change_wiring: demotion failed"); 3512 } else 3513 goto out; 3514 } 3515 pte = pmap_pte(pmap, va); 3516 3517 if (wired && !pmap_pte_w(pte)) 3518 pmap->pm_stats.wired_count++; 3519 else if (!wired && pmap_pte_w(pte)) 3520 pmap->pm_stats.wired_count--; 3521 3522 /* 3523 * Wiring is not a hardware characteristic so there is no need to 3524 * invalidate TLB. 3525 */ 3526 pmap_pte_set_w(pte, wired); 3527 pmap_pte_release(pte); 3528out: 3529 if (are_queues_locked) 3530 vm_page_unlock_queues(); 3531 PMAP_UNLOCK(pmap); 3532} 3533 3534 3535 3536/* 3537 * Copy the range specified by src_addr/len 3538 * from the source map to the range dst_addr/len 3539 * in the destination map. 3540 * 3541 * This routine is only advisory and need not do anything. 3542 */ 3543 3544void 3545pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len, 3546 vm_offset_t src_addr) 3547{ 3548 vm_page_t free; 3549 vm_offset_t addr; 3550 vm_offset_t end_addr = src_addr + len; 3551 vm_offset_t pdnxt; 3552 3553 if (dst_addr != src_addr) 3554 return; 3555 3556 if (!pmap_is_current(src_pmap)) 3557 return; 3558 3559 vm_page_lock_queues(); 3560 if (dst_pmap < src_pmap) { 3561 PMAP_LOCK(dst_pmap); 3562 PMAP_LOCK(src_pmap); 3563 } else { 3564 PMAP_LOCK(src_pmap); 3565 PMAP_LOCK(dst_pmap); 3566 } 3567 sched_pin(); 3568 for (addr = src_addr; addr < end_addr; addr = pdnxt) { 3569 pt_entry_t *src_pte, *dst_pte; 3570 vm_page_t dstmpte, srcmpte; 3571 pd_entry_t srcptepaddr; 3572 unsigned ptepindex; 3573 3574 KASSERT(addr < UPT_MIN_ADDRESS, 3575 ("pmap_copy: invalid to pmap_copy page tables")); 3576 3577 pdnxt = (addr + NBPDR) & ~PDRMASK; 3578 if (pdnxt < addr) 3579 pdnxt = end_addr; 3580 ptepindex = addr >> PDRSHIFT; 3581 3582 srcptepaddr = src_pmap->pm_pdir[ptepindex]; 3583 if (srcptepaddr == 0) 3584 continue; 3585 3586 if (srcptepaddr & PG_PS) { 3587 if (dst_pmap->pm_pdir[ptepindex] == 0 && 3588 ((srcptepaddr & PG_MANAGED) == 0 || 3589 pmap_pv_insert_pde(dst_pmap, addr, 3590 PHYS_TO_VM_PAGE(srcptepaddr & PG_FRAME)))) { 3591 dst_pmap->pm_pdir[ptepindex] = srcptepaddr & 3592 ~PG_W; 3593 dst_pmap->pm_stats.resident_count += 3594 NBPDR / PAGE_SIZE; 3595 } 3596 continue; 3597 } 3598 3599 srcmpte = PHYS_TO_VM_PAGE(srcptepaddr & PG_FRAME); 3600 KASSERT(srcmpte->wire_count > 0, 3601 ("pmap_copy: source page table page is unused")); 3602 3603 if (pdnxt > end_addr) 3604 pdnxt = end_addr; 3605 3606 src_pte = vtopte(addr); 3607 while (addr < pdnxt) { 3608 pt_entry_t ptetemp; 3609 ptetemp = *src_pte; 3610 /* 3611 * we only virtual copy managed pages 3612 */ 3613 if ((ptetemp & PG_MANAGED) != 0) { 3614 dstmpte = pmap_allocpte(dst_pmap, addr, 3615 M_NOWAIT); 3616 if (dstmpte == NULL) 3617 break; 3618 dst_pte = pmap_pte_quick(dst_pmap, addr); 3619 if (*dst_pte == 0 && 3620 pmap_try_insert_pv_entry(dst_pmap, addr, 3621 PHYS_TO_VM_PAGE(ptetemp & PG_FRAME))) { 3622 /* 3623 * Clear the wired, modified, and 3624 * accessed (referenced) bits 3625 * during the copy. 3626 */ 3627 *dst_pte = ptetemp & ~(PG_W | PG_M | 3628 PG_A); 3629 dst_pmap->pm_stats.resident_count++; 3630 } else { 3631 free = NULL; 3632 if (pmap_unwire_pte_hold( dst_pmap, 3633 dstmpte, &free)) { 3634 pmap_invalidate_page(dst_pmap, 3635 addr); 3636 pmap_free_zero_pages(free); 3637 } 3638 } 3639 if (dstmpte->wire_count >= srcmpte->wire_count) 3640 break; 3641 } 3642 addr += PAGE_SIZE; 3643 src_pte++; 3644 } 3645 } 3646 sched_unpin(); 3647 vm_page_unlock_queues(); 3648 PMAP_UNLOCK(src_pmap); 3649 PMAP_UNLOCK(dst_pmap); 3650} 3651 3652static __inline void 3653pagezero(void *page) 3654{ 3655#if defined(I686_CPU) 3656 if (cpu_class == CPUCLASS_686) { 3657#if defined(CPU_ENABLE_SSE) 3658 if (cpu_feature & CPUID_SSE2) 3659 sse2_pagezero(page); 3660 else 3661#endif 3662 i686_pagezero(page); 3663 } else 3664#endif 3665 bzero(page, PAGE_SIZE); 3666} 3667 3668/* 3669 * pmap_zero_page zeros the specified hardware page by mapping 3670 * the page into KVM and using bzero to clear its contents. 3671 */ 3672void 3673pmap_zero_page(vm_page_t m) 3674{ 3675 struct sysmaps *sysmaps; 3676 3677 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)]; 3678 mtx_lock(&sysmaps->lock); 3679 if (*sysmaps->CMAP2) 3680 panic("pmap_zero_page: CMAP2 busy"); 3681 sched_pin(); 3682 *sysmaps->CMAP2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M; 3683 invlcaddr(sysmaps->CADDR2); 3684 pagezero(sysmaps->CADDR2); 3685 *sysmaps->CMAP2 = 0; 3686 sched_unpin(); 3687 mtx_unlock(&sysmaps->lock); 3688} 3689 3690/* 3691 * pmap_zero_page_area zeros the specified hardware page by mapping 3692 * the page into KVM and using bzero to clear its contents. 3693 * 3694 * off and size may not cover an area beyond a single hardware page. 3695 */ 3696void 3697pmap_zero_page_area(vm_page_t m, int off, int size) 3698{ 3699 struct sysmaps *sysmaps; 3700 3701 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)]; 3702 mtx_lock(&sysmaps->lock); 3703 if (*sysmaps->CMAP2) 3704 panic("pmap_zero_page: CMAP2 busy"); 3705 sched_pin(); 3706 *sysmaps->CMAP2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M; 3707 invlcaddr(sysmaps->CADDR2); 3708 if (off == 0 && size == PAGE_SIZE) 3709 pagezero(sysmaps->CADDR2); 3710 else 3711 bzero((char *)sysmaps->CADDR2 + off, size); 3712 *sysmaps->CMAP2 = 0; 3713 sched_unpin(); 3714 mtx_unlock(&sysmaps->lock); 3715} 3716 3717/* 3718 * pmap_zero_page_idle zeros the specified hardware page by mapping 3719 * the page into KVM and using bzero to clear its contents. This 3720 * is intended to be called from the vm_pagezero process only and 3721 * outside of Giant. 3722 */ 3723void 3724pmap_zero_page_idle(vm_page_t m) 3725{ 3726 3727 if (*CMAP3) 3728 panic("pmap_zero_page: CMAP3 busy"); 3729 sched_pin(); 3730 *CMAP3 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M; 3731 invlcaddr(CADDR3); 3732 pagezero(CADDR3); 3733 *CMAP3 = 0; 3734 sched_unpin(); 3735} 3736 3737/* 3738 * pmap_copy_page copies the specified (machine independent) 3739 * page by mapping the page into virtual memory and using 3740 * bcopy to copy the page, one machine dependent page at a 3741 * time. 3742 */ 3743void 3744pmap_copy_page(vm_page_t src, vm_page_t dst) 3745{ 3746 struct sysmaps *sysmaps; 3747 3748 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)]; 3749 mtx_lock(&sysmaps->lock); 3750 if (*sysmaps->CMAP1) 3751 panic("pmap_copy_page: CMAP1 busy"); 3752 if (*sysmaps->CMAP2) 3753 panic("pmap_copy_page: CMAP2 busy"); 3754 sched_pin(); 3755 invlpg((u_int)sysmaps->CADDR1); 3756 invlpg((u_int)sysmaps->CADDR2); 3757 *sysmaps->CMAP1 = PG_V | VM_PAGE_TO_PHYS(src) | PG_A; 3758 *sysmaps->CMAP2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(dst) | PG_A | PG_M; 3759 bcopy(sysmaps->CADDR1, sysmaps->CADDR2, PAGE_SIZE); 3760 *sysmaps->CMAP1 = 0; 3761 *sysmaps->CMAP2 = 0; 3762 sched_unpin(); 3763 mtx_unlock(&sysmaps->lock); 3764} 3765 3766/* 3767 * Returns true if the pmap's pv is one of the first 3768 * 16 pvs linked to from this page. This count may 3769 * be changed upwards or downwards in the future; it 3770 * is only necessary that true be returned for a small 3771 * subset of pmaps for proper page aging. 3772 */ 3773boolean_t 3774pmap_page_exists_quick(pmap_t pmap, vm_page_t m) 3775{ 3776 struct md_page *pvh; 3777 pv_entry_t pv; 3778 int loops = 0; 3779 3780 if (m->flags & PG_FICTITIOUS) 3781 return FALSE; 3782 3783 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 3784 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 3785 if (PV_PMAP(pv) == pmap) { 3786 return TRUE; 3787 } 3788 loops++; 3789 if (loops >= 16) 3790 break; 3791 } 3792 if (loops < 16) { 3793 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 3794 TAILQ_FOREACH(pv, &pvh->pv_list, pv_list) { 3795 if (PV_PMAP(pv) == pmap) 3796 return (TRUE); 3797 loops++; 3798 if (loops >= 16) 3799 break; 3800 } 3801 } 3802 return (FALSE); 3803} 3804 3805/* 3806 * pmap_page_wired_mappings: 3807 * 3808 * Return the number of managed mappings to the given physical page 3809 * that are wired. 3810 */ 3811int 3812pmap_page_wired_mappings(vm_page_t m) 3813{ 3814 pv_entry_t pv; 3815 pt_entry_t *pte; 3816 pmap_t pmap; 3817 int count; 3818 3819 count = 0; 3820 if ((m->flags & PG_FICTITIOUS) != 0) 3821 return (count); 3822 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 3823 sched_pin(); 3824 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 3825 pmap = PV_PMAP(pv); 3826 PMAP_LOCK(pmap); 3827 pte = pmap_pte_quick(pmap, pv->pv_va); 3828 if ((*pte & PG_W) != 0) 3829 count++; 3830 PMAP_UNLOCK(pmap); 3831 } 3832 sched_unpin(); 3833 return (count); 3834} 3835 3836/* 3837 * Returns TRUE if the given page is mapped individually or as part of 3838 * a 4mpage. Otherwise, returns FALSE. 3839 */ 3840boolean_t 3841pmap_page_is_mapped(vm_page_t m) 3842{ 3843 struct md_page *pvh; 3844 3845 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0) 3846 return (FALSE); 3847 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 3848 if (TAILQ_EMPTY(&m->md.pv_list)) { 3849 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 3850 return (!TAILQ_EMPTY(&pvh->pv_list)); 3851 } else 3852 return (TRUE); 3853} 3854 3855/* 3856 * Remove all pages from specified address space 3857 * this aids process exit speeds. Also, this code 3858 * is special cased for current process only, but 3859 * can have the more generic (and slightly slower) 3860 * mode enabled. This is much faster than pmap_remove 3861 * in the case of running down an entire address space. 3862 */ 3863void 3864pmap_remove_pages(pmap_t pmap) 3865{ 3866 pt_entry_t *pte, tpte; 3867 vm_page_t free = NULL; 3868 vm_page_t m, mpte, mt; 3869 pv_entry_t pv; 3870 struct md_page *pvh; 3871 struct pv_chunk *pc, *npc; 3872 int field, idx; 3873 int32_t bit; 3874 uint32_t inuse, bitmask; 3875 int allfree; 3876 3877 if (pmap != vmspace_pmap(curthread->td_proc->p_vmspace)) { 3878 printf("warning: pmap_remove_pages called with non-current pmap\n"); 3879 return; 3880 } 3881 vm_page_lock_queues(); 3882 PMAP_LOCK(pmap); 3883 sched_pin(); 3884 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) { 3885 allfree = 1; 3886 for (field = 0; field < _NPCM; field++) { 3887 inuse = (~(pc->pc_map[field])) & pc_freemask[field]; 3888 while (inuse != 0) { 3889 bit = bsfl(inuse); 3890 bitmask = 1UL << bit; 3891 idx = field * 32 + bit; 3892 pv = &pc->pc_pventry[idx]; 3893 inuse &= ~bitmask; 3894 3895 pte = pmap_pde(pmap, pv->pv_va); 3896 tpte = *pte; 3897 if ((tpte & PG_PS) == 0) { 3898 pte = vtopte(pv->pv_va); 3899 tpte = *pte & ~PG_PTE_PAT; 3900 } 3901 3902 if (tpte == 0) { 3903 printf( 3904 "TPTE at %p IS ZERO @ VA %08x\n", 3905 pte, pv->pv_va); 3906 panic("bad pte"); 3907 } 3908 3909/* 3910 * We cannot remove wired pages from a process' mapping at this time 3911 */ 3912 if (tpte & PG_W) { 3913 allfree = 0; 3914 continue; 3915 } 3916 3917 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME); 3918 KASSERT(m->phys_addr == (tpte & PG_FRAME), 3919 ("vm_page_t %p phys_addr mismatch %016jx %016jx", 3920 m, (uintmax_t)m->phys_addr, 3921 (uintmax_t)tpte)); 3922 3923 KASSERT(m < &vm_page_array[vm_page_array_size], 3924 ("pmap_remove_pages: bad tpte %#jx", 3925 (uintmax_t)tpte)); 3926 3927 pte_clear(pte); 3928 3929 /* 3930 * Update the vm_page_t clean/reference bits. 3931 */ 3932 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) { 3933 if ((tpte & PG_PS) != 0) { 3934 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++) 3935 vm_page_dirty(mt); 3936 } else 3937 vm_page_dirty(m); 3938 } 3939 3940 /* Mark free */ 3941 PV_STAT(pv_entry_frees++); 3942 PV_STAT(pv_entry_spare++); 3943 pv_entry_count--; 3944 pc->pc_map[field] |= bitmask; 3945 if ((tpte & PG_PS) != 0) { 3946 pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE; 3947 pvh = pa_to_pvh(tpte & PG_FRAME); 3948 TAILQ_REMOVE(&pvh->pv_list, pv, pv_list); 3949 if (TAILQ_EMPTY(&pvh->pv_list)) { 3950 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++) 3951 if (TAILQ_EMPTY(&mt->md.pv_list)) 3952 vm_page_flag_clear(mt, PG_WRITEABLE); 3953 } 3954 mpte = pmap_lookup_pt_page(pmap, pv->pv_va); 3955 if (mpte != NULL) { 3956 pmap_remove_pt_page(pmap, mpte); 3957 KASSERT(mpte->wire_count == NPTEPG, 3958 ("pmap_remove_pages: pte page wire count error")); 3959 mpte->wire_count = 0; 3960 pmap_add_delayed_free_list(mpte, &free, FALSE); 3961 atomic_subtract_int(&cnt.v_wire_count, 1); 3962 } 3963 } else { 3964 pmap->pm_stats.resident_count--; 3965 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list); 3966 if (TAILQ_EMPTY(&m->md.pv_list)) { 3967 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 3968 if (TAILQ_EMPTY(&pvh->pv_list)) 3969 vm_page_flag_clear(m, PG_WRITEABLE); 3970 } 3971 pmap_unuse_pt(pmap, pv->pv_va, &free); 3972 } 3973 } 3974 } 3975 if (allfree) { 3976 PV_STAT(pv_entry_spare -= _NPCPV); 3977 PV_STAT(pc_chunk_count--); 3978 PV_STAT(pc_chunk_frees++); 3979 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 3980 m = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc)); 3981 pmap_qremove((vm_offset_t)pc, 1); 3982 vm_page_unwire(m, 0); 3983 vm_page_free(m); 3984 pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc); 3985 } 3986 } 3987 sched_unpin(); 3988 pmap_invalidate_all(pmap); 3989 vm_page_unlock_queues(); 3990 PMAP_UNLOCK(pmap); 3991 pmap_free_zero_pages(free); 3992} 3993 3994/* 3995 * pmap_is_modified: 3996 * 3997 * Return whether or not the specified physical page was modified 3998 * in any physical maps. 3999 */ 4000boolean_t 4001pmap_is_modified(vm_page_t m) 4002{ 4003 4004 if (m->flags & PG_FICTITIOUS) 4005 return (FALSE); 4006 if (pmap_is_modified_pvh(&m->md)) 4007 return (TRUE); 4008 return (pmap_is_modified_pvh(pa_to_pvh(VM_PAGE_TO_PHYS(m)))); 4009} 4010 4011/* 4012 * Returns TRUE if any of the given mappings were used to modify 4013 * physical memory. Otherwise, returns FALSE. Both page and 2mpage 4014 * mappings are supported. 4015 */ 4016static boolean_t 4017pmap_is_modified_pvh(struct md_page *pvh) 4018{ 4019 pv_entry_t pv; 4020 pt_entry_t *pte; 4021 pmap_t pmap; 4022 boolean_t rv; 4023 4024 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 4025 rv = FALSE; 4026 sched_pin(); 4027 TAILQ_FOREACH(pv, &pvh->pv_list, pv_list) { 4028 pmap = PV_PMAP(pv); 4029 PMAP_LOCK(pmap); 4030 pte = pmap_pte_quick(pmap, pv->pv_va); 4031 rv = (*pte & (PG_M | PG_RW)) == (PG_M | PG_RW); 4032 PMAP_UNLOCK(pmap); 4033 if (rv) 4034 break; 4035 } 4036 sched_unpin(); 4037 return (rv); 4038} 4039 4040/* 4041 * pmap_is_prefaultable: 4042 * 4043 * Return whether or not the specified virtual address is elgible 4044 * for prefault. 4045 */ 4046boolean_t 4047pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr) 4048{ 4049 pd_entry_t *pde; 4050 pt_entry_t *pte; 4051 boolean_t rv; 4052 4053 rv = FALSE; 4054 PMAP_LOCK(pmap); 4055 pde = pmap_pde(pmap, addr); 4056 if (*pde != 0 && (*pde & PG_PS) == 0) { 4057 pte = vtopte(addr); 4058 rv = *pte == 0; 4059 } 4060 PMAP_UNLOCK(pmap); 4061 return (rv); 4062} 4063 4064/* 4065 * Clear the write and modified bits in each of the given page's mappings. 4066 */ 4067void 4068pmap_remove_write(vm_page_t m) 4069{ 4070 struct md_page *pvh; 4071 pv_entry_t next_pv, pv; 4072 pmap_t pmap; 4073 pd_entry_t *pde; 4074 pt_entry_t oldpte, *pte; 4075 vm_offset_t va; 4076 4077 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 4078 if ((m->flags & PG_FICTITIOUS) != 0 || 4079 (m->flags & PG_WRITEABLE) == 0) 4080 return; 4081 sched_pin(); 4082 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 4083 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_list, next_pv) { 4084 va = pv->pv_va; 4085 pmap = PV_PMAP(pv); 4086 PMAP_LOCK(pmap); 4087 pde = pmap_pde(pmap, va); 4088 if ((*pde & PG_RW) != 0) 4089 (void)pmap_demote_pde(pmap, pde, va); 4090 PMAP_UNLOCK(pmap); 4091 } 4092 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 4093 pmap = PV_PMAP(pv); 4094 PMAP_LOCK(pmap); 4095 pde = pmap_pde(pmap, pv->pv_va); 4096 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_write: found" 4097 " a 4mpage in page %p's pv list", m)); 4098 pte = pmap_pte_quick(pmap, pv->pv_va); 4099retry: 4100 oldpte = *pte; 4101 if ((oldpte & PG_RW) != 0) { 4102 /* 4103 * Regardless of whether a pte is 32 or 64 bits 4104 * in size, PG_RW and PG_M are among the least 4105 * significant 32 bits. 4106 */ 4107 if (!atomic_cmpset_int((u_int *)pte, oldpte, 4108 oldpte & ~(PG_RW | PG_M))) 4109 goto retry; 4110 if ((oldpte & PG_M) != 0) 4111 vm_page_dirty(m); 4112 pmap_invalidate_page(pmap, pv->pv_va); 4113 } 4114 PMAP_UNLOCK(pmap); 4115 } 4116 vm_page_flag_clear(m, PG_WRITEABLE); 4117 sched_unpin(); 4118} 4119 4120/* 4121 * pmap_ts_referenced: 4122 * 4123 * Return a count of reference bits for a page, clearing those bits. 4124 * It is not necessary for every reference bit to be cleared, but it 4125 * is necessary that 0 only be returned when there are truly no 4126 * reference bits set. 4127 * 4128 * XXX: The exact number of bits to check and clear is a matter that 4129 * should be tested and standardized at some point in the future for 4130 * optimal aging of shared pages. 4131 */ 4132int 4133pmap_ts_referenced(vm_page_t m) 4134{ 4135 struct md_page *pvh; 4136 pv_entry_t pv, pvf, pvn; 4137 pmap_t pmap; 4138 pd_entry_t oldpde, *pde; 4139 pt_entry_t *pte; 4140 vm_offset_t va; 4141 int rtval = 0; 4142 4143 if (m->flags & PG_FICTITIOUS) 4144 return (rtval); 4145 sched_pin(); 4146 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 4147 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 4148 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_list, pvn) { 4149 va = pv->pv_va; 4150 pmap = PV_PMAP(pv); 4151 PMAP_LOCK(pmap); 4152 pde = pmap_pde(pmap, va); 4153 oldpde = *pde; 4154 if ((oldpde & PG_A) != 0) { 4155 if (pmap_demote_pde(pmap, pde, va)) { 4156 if ((oldpde & PG_W) == 0) { 4157 /* 4158 * Remove the mapping to a single page 4159 * so that a subsequent access may 4160 * repromote. Since the underlying 4161 * page table page is fully populated, 4162 * this removal never frees a page 4163 * table page. 4164 */ 4165 va += VM_PAGE_TO_PHYS(m) - (oldpde & 4166 PG_FRAME); 4167 pmap_remove_page(pmap, va, NULL); 4168 rtval++; 4169 if (rtval > 4) { 4170 PMAP_UNLOCK(pmap); 4171 return (rtval); 4172 } 4173 } 4174 } 4175 } 4176 PMAP_UNLOCK(pmap); 4177 } 4178 if ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) { 4179 pvf = pv; 4180 do { 4181 pvn = TAILQ_NEXT(pv, pv_list); 4182 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list); 4183 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list); 4184 pmap = PV_PMAP(pv); 4185 PMAP_LOCK(pmap); 4186 pde = pmap_pde(pmap, pv->pv_va); 4187 KASSERT((*pde & PG_PS) == 0, ("pmap_ts_referenced:" 4188 " found a 4mpage in page %p's pv list", m)); 4189 pte = pmap_pte_quick(pmap, pv->pv_va); 4190 if ((*pte & PG_A) != 0) { 4191 atomic_clear_int((u_int *)pte, PG_A); 4192 pmap_invalidate_page(pmap, pv->pv_va); 4193 rtval++; 4194 if (rtval > 4) 4195 pvn = NULL; 4196 } 4197 PMAP_UNLOCK(pmap); 4198 } while ((pv = pvn) != NULL && pv != pvf); 4199 } 4200 sched_unpin(); 4201 return (rtval); 4202} 4203 4204/* 4205 * Clear the modify bits on the specified physical page. 4206 */ 4207void 4208pmap_clear_modify(vm_page_t m) 4209{ 4210 struct md_page *pvh; 4211 pv_entry_t next_pv, pv; 4212 pmap_t pmap; 4213 pd_entry_t oldpde, *pde; 4214 pt_entry_t oldpte, *pte; 4215 vm_offset_t va; 4216 4217 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 4218 if ((m->flags & PG_FICTITIOUS) != 0) 4219 return; 4220 sched_pin(); 4221 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 4222 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_list, next_pv) { 4223 va = pv->pv_va; 4224 pmap = PV_PMAP(pv); 4225 PMAP_LOCK(pmap); 4226 pde = pmap_pde(pmap, va); 4227 oldpde = *pde; 4228 if ((oldpde & PG_RW) != 0) { 4229 if (pmap_demote_pde(pmap, pde, va)) { 4230 if ((oldpde & PG_W) == 0) { 4231 /* 4232 * Write protect the mapping to a 4233 * single page so that a subsequent 4234 * write access may repromote. 4235 */ 4236 va += VM_PAGE_TO_PHYS(m) - (oldpde & 4237 PG_FRAME); 4238 pte = pmap_pte_quick(pmap, va); 4239 oldpte = *pte; 4240 if ((oldpte & PG_V) != 0) { 4241 /* 4242 * Regardless of whether a pte is 32 or 64 bits 4243 * in size, PG_RW and PG_M are among the least 4244 * significant 32 bits. 4245 */ 4246 while (!atomic_cmpset_int((u_int *)pte, 4247 oldpte, 4248 oldpte & ~(PG_M | PG_RW))) 4249 oldpte = *pte; 4250 vm_page_dirty(m); 4251 pmap_invalidate_page(pmap, va); 4252 } 4253 } 4254 } 4255 } 4256 PMAP_UNLOCK(pmap); 4257 } 4258 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 4259 pmap = PV_PMAP(pv); 4260 PMAP_LOCK(pmap); 4261 pde = pmap_pde(pmap, pv->pv_va); 4262 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_modify: found" 4263 " a 4mpage in page %p's pv list", m)); 4264 pte = pmap_pte_quick(pmap, pv->pv_va); 4265 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) { 4266 /* 4267 * Regardless of whether a pte is 32 or 64 bits 4268 * in size, PG_M is among the least significant 4269 * 32 bits. 4270 */ 4271 atomic_clear_int((u_int *)pte, PG_M); 4272 pmap_invalidate_page(pmap, pv->pv_va); 4273 } 4274 PMAP_UNLOCK(pmap); 4275 } 4276 sched_unpin(); 4277} 4278 4279/* 4280 * pmap_clear_reference: 4281 * 4282 * Clear the reference bit on the specified physical page. 4283 */ 4284void 4285pmap_clear_reference(vm_page_t m) 4286{ 4287 struct md_page *pvh; 4288 pv_entry_t next_pv, pv; 4289 pmap_t pmap; 4290 pd_entry_t oldpde, *pde; 4291 pt_entry_t *pte; 4292 vm_offset_t va; 4293 4294 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 4295 if ((m->flags & PG_FICTITIOUS) != 0) 4296 return; 4297 sched_pin(); 4298 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 4299 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_list, next_pv) { 4300 va = pv->pv_va; 4301 pmap = PV_PMAP(pv); 4302 PMAP_LOCK(pmap); 4303 pde = pmap_pde(pmap, va); 4304 oldpde = *pde; 4305 if ((oldpde & PG_A) != 0) { 4306 if (pmap_demote_pde(pmap, pde, va)) { 4307 /* 4308 * Remove the mapping to a single page so 4309 * that a subsequent access may repromote. 4310 * Since the underlying page table page is 4311 * fully populated, this removal never frees 4312 * a page table page. 4313 */ 4314 va += VM_PAGE_TO_PHYS(m) - (oldpde & PG_FRAME); 4315 pmap_remove_page(pmap, va, NULL); 4316 } 4317 } 4318 PMAP_UNLOCK(pmap); 4319 } 4320 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 4321 pmap = PV_PMAP(pv); 4322 PMAP_LOCK(pmap); 4323 pde = pmap_pde(pmap, pv->pv_va); 4324 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_reference: found" 4325 " a 4mpage in page %p's pv list", m)); 4326 pte = pmap_pte_quick(pmap, pv->pv_va); 4327 if ((*pte & PG_A) != 0) { 4328 /* 4329 * Regardless of whether a pte is 32 or 64 bits 4330 * in size, PG_A is among the least significant 4331 * 32 bits. 4332 */ 4333 atomic_clear_int((u_int *)pte, PG_A); 4334 pmap_invalidate_page(pmap, pv->pv_va); 4335 } 4336 PMAP_UNLOCK(pmap); 4337 } 4338 sched_unpin(); 4339} 4340 4341/* 4342 * Miscellaneous support routines follow 4343 */ 4344 4345/* 4346 * Map a set of physical memory pages into the kernel virtual 4347 * address space. Return a pointer to where it is mapped. This 4348 * routine is intended to be used for mapping device memory, 4349 * NOT real memory. 4350 */ 4351void * 4352pmap_mapdev_attr(vm_paddr_t pa, vm_size_t size, int mode) 4353{ 4354 vm_offset_t va, tmpva, offset; 4355 4356 offset = pa & PAGE_MASK; 4357 size = roundup(offset + size, PAGE_SIZE); 4358 pa = pa & PG_FRAME; 4359 4360 if (pa < KERNLOAD && pa + size <= KERNLOAD) 4361 va = KERNBASE + pa; 4362 else 4363 va = kmem_alloc_nofault(kernel_map, size); 4364 if (!va) 4365 panic("pmap_mapdev: Couldn't alloc kernel virtual memory"); 4366 4367 for (tmpva = va; size > 0; ) { 4368 pmap_kenter_attr(tmpva, pa, mode); 4369 size -= PAGE_SIZE; 4370 tmpva += PAGE_SIZE; 4371 pa += PAGE_SIZE; 4372 } 4373 pmap_invalidate_range(kernel_pmap, va, tmpva); 4374 pmap_invalidate_cache(); 4375 return ((void *)(va + offset)); 4376} 4377 4378void * 4379pmap_mapdev(vm_paddr_t pa, vm_size_t size) 4380{ 4381 4382 return (pmap_mapdev_attr(pa, size, PAT_UNCACHEABLE)); 4383} 4384 4385void * 4386pmap_mapbios(vm_paddr_t pa, vm_size_t size) 4387{ 4388 4389 return (pmap_mapdev_attr(pa, size, PAT_WRITE_BACK)); 4390} 4391 4392void 4393pmap_unmapdev(vm_offset_t va, vm_size_t size) 4394{ 4395 vm_offset_t base, offset, tmpva; 4396 4397 if (va >= KERNBASE && va + size <= KERNBASE + KERNLOAD) 4398 return; 4399 base = trunc_page(va); 4400 offset = va & PAGE_MASK; 4401 size = roundup(offset + size, PAGE_SIZE); 4402 for (tmpva = base; tmpva < (base + size); tmpva += PAGE_SIZE) 4403 pmap_kremove(tmpva); 4404 pmap_invalidate_range(kernel_pmap, va, tmpva); 4405 kmem_free(kernel_map, base, size); 4406} 4407 4408int 4409pmap_change_attr(va, size, mode) 4410 vm_offset_t va; 4411 vm_size_t size; 4412 int mode; 4413{ 4414 vm_offset_t base, offset, tmpva; 4415 pt_entry_t *pte; 4416 u_int opte, npte; 4417 pd_entry_t *pde; 4418 4419 base = trunc_page(va); 4420 offset = va & PAGE_MASK; 4421 size = roundup(offset + size, PAGE_SIZE); 4422 4423 /* Only supported on kernel virtual addresses. */ 4424 if (base <= VM_MAXUSER_ADDRESS) 4425 return (EINVAL); 4426 4427 /* 4MB pages and pages that aren't mapped aren't supported. */ 4428 for (tmpva = base; tmpva < (base + size); tmpva += PAGE_SIZE) { 4429 pde = pmap_pde(kernel_pmap, tmpva); 4430 if (*pde & PG_PS) 4431 return (EINVAL); 4432 if (*pde == 0) 4433 return (EINVAL); 4434 pte = vtopte(va); 4435 if (*pte == 0) 4436 return (EINVAL); 4437 } 4438 4439 /* 4440 * Ok, all the pages exist and are 4k, so run through them updating 4441 * their cache mode. 4442 */ 4443 for (tmpva = base; size > 0; ) { 4444 pte = vtopte(tmpva); 4445 4446 /* 4447 * The cache mode bits are all in the low 32-bits of the 4448 * PTE, so we can just spin on updating the low 32-bits. 4449 */ 4450 do { 4451 opte = *(u_int *)pte; 4452 npte = opte & ~(PG_PTE_PAT | PG_NC_PCD | PG_NC_PWT); 4453 npte |= pmap_cache_bits(mode, 0); 4454 } while (npte != opte && 4455 !atomic_cmpset_int((u_int *)pte, opte, npte)); 4456 tmpva += PAGE_SIZE; 4457 size -= PAGE_SIZE; 4458 } 4459 4460 /* 4461 * Flush CPU caches to make sure any data isn't cached that shouldn't 4462 * be, etc. 4463 */ 4464 pmap_invalidate_range(kernel_pmap, base, tmpva); 4465 pmap_invalidate_cache(); 4466 return (0); 4467} 4468 4469/* 4470 * perform the pmap work for mincore 4471 */ 4472int 4473pmap_mincore(pmap_t pmap, vm_offset_t addr) 4474{ 4475 pd_entry_t *pdep; 4476 pt_entry_t *ptep, pte; 4477 vm_paddr_t pa; 4478 vm_page_t m; 4479 int val = 0; 4480 4481 PMAP_LOCK(pmap); 4482 pdep = pmap_pde(pmap, addr); 4483 if (*pdep != 0) { 4484 if (*pdep & PG_PS) { 4485 pte = *pdep; 4486 val = MINCORE_SUPER; 4487 /* Compute the physical address of the 4KB page. */ 4488 pa = ((*pdep & PG_PS_FRAME) | (addr & PDRMASK)) & 4489 PG_FRAME; 4490 } else { 4491 ptep = pmap_pte(pmap, addr); 4492 pte = *ptep; 4493 pmap_pte_release(ptep); 4494 pa = pte & PG_FRAME; 4495 } 4496 } else { 4497 pte = 0; 4498 pa = 0; 4499 } 4500 PMAP_UNLOCK(pmap); 4501 4502 if (pte != 0) { 4503 val |= MINCORE_INCORE; 4504 if ((pte & PG_MANAGED) == 0) 4505 return val; 4506 4507 m = PHYS_TO_VM_PAGE(pa); 4508 4509 /* 4510 * Modified by us 4511 */ 4512 if ((pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) 4513 val |= MINCORE_MODIFIED|MINCORE_MODIFIED_OTHER; 4514 else { 4515 /* 4516 * Modified by someone else 4517 */ 4518 vm_page_lock_queues(); 4519 if (m->dirty || pmap_is_modified(m)) 4520 val |= MINCORE_MODIFIED_OTHER; 4521 vm_page_unlock_queues(); 4522 } 4523 /* 4524 * Referenced by us 4525 */ 4526 if (pte & PG_A) 4527 val |= MINCORE_REFERENCED|MINCORE_REFERENCED_OTHER; 4528 else { 4529 /* 4530 * Referenced by someone else 4531 */ 4532 vm_page_lock_queues(); 4533 if ((m->flags & PG_REFERENCED) || 4534 pmap_ts_referenced(m)) { 4535 val |= MINCORE_REFERENCED_OTHER; 4536 vm_page_flag_set(m, PG_REFERENCED); 4537 } 4538 vm_page_unlock_queues(); 4539 } 4540 } 4541 return val; 4542} 4543 4544void 4545pmap_activate(struct thread *td) 4546{ 4547 pmap_t pmap, oldpmap; 4548 u_int32_t cr3; 4549 4550 critical_enter(); 4551 pmap = vmspace_pmap(td->td_proc->p_vmspace); 4552 oldpmap = PCPU_GET(curpmap); 4553#if defined(SMP) 4554 atomic_clear_int(&oldpmap->pm_active, PCPU_GET(cpumask)); 4555 atomic_set_int(&pmap->pm_active, PCPU_GET(cpumask)); 4556#else 4557 oldpmap->pm_active &= ~1; 4558 pmap->pm_active |= 1; 4559#endif 4560#ifdef PAE 4561 cr3 = vtophys(pmap->pm_pdpt); 4562#else 4563 cr3 = vtophys(pmap->pm_pdir); 4564#endif 4565 /* 4566 * pmap_activate is for the current thread on the current cpu 4567 */ 4568 td->td_pcb->pcb_cr3 = cr3; 4569 load_cr3(cr3); 4570 PCPU_SET(curpmap, pmap); 4571 critical_exit(); 4572} 4573 4574vm_offset_t 4575pmap_addr_hint(vm_object_t obj, vm_offset_t addr, vm_size_t size) 4576{ 4577 4578 if ((obj == NULL) || (size < NBPDR) || (obj->type != OBJT_DEVICE)) { 4579 return addr; 4580 } 4581 4582 addr = (addr + PDRMASK) & ~PDRMASK; 4583 return addr; 4584} 4585 4586 4587#if defined(PMAP_DEBUG) 4588pmap_pid_dump(int pid) 4589{ 4590 pmap_t pmap; 4591 struct proc *p; 4592 int npte = 0; 4593 int index; 4594 4595 sx_slock(&allproc_lock); 4596 FOREACH_PROC_IN_SYSTEM(p) { 4597 if (p->p_pid != pid) 4598 continue; 4599 4600 if (p->p_vmspace) { 4601 int i,j; 4602 index = 0; 4603 pmap = vmspace_pmap(p->p_vmspace); 4604 for (i = 0; i < NPDEPTD; i++) { 4605 pd_entry_t *pde; 4606 pt_entry_t *pte; 4607 vm_offset_t base = i << PDRSHIFT; 4608 4609 pde = &pmap->pm_pdir[i]; 4610 if (pde && pmap_pde_v(pde)) { 4611 for (j = 0; j < NPTEPG; j++) { 4612 vm_offset_t va = base + (j << PAGE_SHIFT); 4613 if (va >= (vm_offset_t) VM_MIN_KERNEL_ADDRESS) { 4614 if (index) { 4615 index = 0; 4616 printf("\n"); 4617 } 4618 sx_sunlock(&allproc_lock); 4619 return npte; 4620 } 4621 pte = pmap_pte(pmap, va); 4622 if (pte && pmap_pte_v(pte)) { 4623 pt_entry_t pa; 4624 vm_page_t m; 4625 pa = *pte; 4626 m = PHYS_TO_VM_PAGE(pa & PG_FRAME); 4627 printf("va: 0x%x, pt: 0x%x, h: %d, w: %d, f: 0x%x", 4628 va, pa, m->hold_count, m->wire_count, m->flags); 4629 npte++; 4630 index++; 4631 if (index >= 2) { 4632 index = 0; 4633 printf("\n"); 4634 } else { 4635 printf(" "); 4636 } 4637 } 4638 } 4639 } 4640 } 4641 } 4642 } 4643 sx_sunlock(&allproc_lock); 4644 return npte; 4645} 4646#endif 4647 4648#if defined(DEBUG) 4649 4650static void pads(pmap_t pm); 4651void pmap_pvdump(vm_offset_t pa); 4652 4653/* print address space of pmap*/ 4654static void 4655pads(pmap_t pm) 4656{ 4657 int i, j; 4658 vm_paddr_t va; 4659 pt_entry_t *ptep; 4660 4661 if (pm == kernel_pmap) 4662 return; 4663 for (i = 0; i < NPDEPTD; i++) 4664 if (pm->pm_pdir[i]) 4665 for (j = 0; j < NPTEPG; j++) { 4666 va = (i << PDRSHIFT) + (j << PAGE_SHIFT); 4667 if (pm == kernel_pmap && va < KERNBASE) 4668 continue; 4669 if (pm != kernel_pmap && va > UPT_MAX_ADDRESS) 4670 continue; 4671 ptep = pmap_pte(pm, va); 4672 if (pmap_pte_v(ptep)) 4673 printf("%x:%x ", va, *ptep); 4674 }; 4675 4676} 4677 4678void 4679pmap_pvdump(vm_paddr_t pa) 4680{ 4681 pv_entry_t pv; 4682 pmap_t pmap; 4683 vm_page_t m; 4684 4685 printf("pa %x", pa); 4686 m = PHYS_TO_VM_PAGE(pa); 4687 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 4688 pmap = PV_PMAP(pv); 4689 printf(" -> pmap %p, va %x", (void *)pmap, pv->pv_va); 4690 pads(pmap); 4691 } 4692 printf(" "); 4693} 4694#endif 4695