if_xl.c revision 93818
1/* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: head/sys/pci/if_xl.c 93818 2002-04-04 21:03:38Z jhb $ 33 */ 34 35/* 36 * 3Com 3c90x Etherlink XL PCI NIC driver 37 * 38 * Supports the 3Com "boomerang", "cyclone" and "hurricane" PCI 39 * bus-master chips (3c90x cards and embedded controllers) including 40 * the following: 41 * 42 * 3Com 3c900-TPO 10Mbps/RJ-45 43 * 3Com 3c900-COMBO 10Mbps/RJ-45,AUI,BNC 44 * 3Com 3c905-TX 10/100Mbps/RJ-45 45 * 3Com 3c905-T4 10/100Mbps/RJ-45 46 * 3Com 3c900B-TPO 10Mbps/RJ-45 47 * 3Com 3c900B-COMBO 10Mbps/RJ-45,AUI,BNC 48 * 3Com 3c900B-TPC 10Mbps/RJ-45,BNC 49 * 3Com 3c900B-FL 10Mbps/Fiber-optic 50 * 3Com 3c905B-COMBO 10/100Mbps/RJ-45,AUI,BNC 51 * 3Com 3c905B-TX 10/100Mbps/RJ-45 52 * 3Com 3c905B-FL/FX 10/100Mbps/Fiber-optic 53 * 3Com 3c905C-TX 10/100Mbps/RJ-45 (Tornado ASIC) 54 * 3Com 3c980-TX 10/100Mbps server adapter (Hurricane ASIC) 55 * 3Com 3c980C-TX 10/100Mbps server adapter (Tornado ASIC) 56 * 3Com 3cSOHO100-TX 10/100Mbps/RJ-45 (Hurricane ASIC) 57 * 3Com 3c450-TX 10/100Mbps/RJ-45 (Tornado ASIC) 58 * 3Com 3c556 10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC) 59 * 3Com 3c556B 10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC) 60 * 3Com 3c575TX 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 61 * 3Com 3c575B 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 62 * 3Com 3c575C 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 63 * 3Com 3cxfem656 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 64 * 3Com 3cxfem656b 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 65 * 3Com 3cxfem656c 10/100Mbps/RJ-45 (Cardbus, Tornado ASIC) 66 * Dell Optiplex GX1 on-board 3c918 10/100Mbps/RJ-45 67 * Dell on-board 3c920 10/100Mbps/RJ-45 68 * Dell Precision on-board 3c905B 10/100Mbps/RJ-45 69 * Dell Latitude laptop docking station embedded 3c905-TX 70 * 71 * Written by Bill Paul <wpaul@ctr.columbia.edu> 72 * Electrical Engineering Department 73 * Columbia University, New York City 74 */ 75 76/* 77 * The 3c90x series chips use a bus-master DMA interface for transfering 78 * packets to and from the controller chip. Some of the "vortex" cards 79 * (3c59x) also supported a bus master mode, however for those chips 80 * you could only DMA packets to/from a contiguous memory buffer. For 81 * transmission this would mean copying the contents of the queued mbuf 82 * chain into a an mbuf cluster and then DMAing the cluster. This extra 83 * copy would sort of defeat the purpose of the bus master support for 84 * any packet that doesn't fit into a single mbuf. 85 * 86 * By contrast, the 3c90x cards support a fragment-based bus master 87 * mode where mbuf chains can be encapsulated using TX descriptors. 88 * This is similar to other PCI chips such as the Texas Instruments 89 * ThunderLAN and the Intel 82557/82558. 90 * 91 * The "vortex" driver (if_vx.c) happens to work for the "boomerang" 92 * bus master chips because they maintain the old PIO interface for 93 * backwards compatibility, but starting with the 3c905B and the 94 * "cyclone" chips, the compatibility interface has been dropped. 95 * Since using bus master DMA is a big win, we use this driver to 96 * support the PCI "boomerang" chips even though they work with the 97 * "vortex" driver in order to obtain better performance. 98 * 99 * This driver is in the /sys/pci directory because it only supports 100 * PCI-based NICs. 101 */ 102 103#include <sys/param.h> 104#include <sys/systm.h> 105#include <sys/sockio.h> 106#include <sys/mbuf.h> 107#include <sys/malloc.h> 108#include <sys/kernel.h> 109#include <sys/socket.h> 110 111#include <net/if.h> 112#include <net/if_arp.h> 113#include <net/ethernet.h> 114#include <net/if_dl.h> 115#include <net/if_media.h> 116 117#include <net/bpf.h> 118 119#include <vm/vm.h> /* for vtophys */ 120#include <vm/pmap.h> /* for vtophys */ 121#include <machine/bus_memio.h> 122#include <machine/bus_pio.h> 123#include <machine/bus.h> 124#include <machine/resource.h> 125#include <sys/bus.h> 126#include <sys/rman.h> 127 128#include <dev/mii/mii.h> 129#include <dev/mii/miivar.h> 130 131#include <pci/pcireg.h> 132#include <pci/pcivar.h> 133 134MODULE_DEPEND(xl, miibus, 1, 1, 1); 135 136/* "controller miibus0" required. See GENERIC if you get errors here. */ 137#include "miibus_if.h" 138 139/* 140 * The following #define causes the code to use PIO to access the 141 * chip's registers instead of memory mapped mode. The reason PIO mode 142 * is on by default is that the Etherlink XL manual seems to indicate 143 * that only the newer revision chips (3c905B) support both PIO and 144 * memory mapped access. Since we want to be compatible with the older 145 * bus master chips, we use PIO here. If you comment this out, the 146 * driver will use memory mapped I/O, which may be faster but which 147 * might not work on some devices. 148 */ 149#define XL_USEIOSPACE 150 151#include <pci/if_xlreg.h> 152 153#if !defined(lint) 154static const char rcsid[] = 155 "$FreeBSD: head/sys/pci/if_xl.c 93818 2002-04-04 21:03:38Z jhb $"; 156#endif 157 158#define XL905B_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 159 160/* 161 * Various supported device vendors/types and their names. 162 */ 163static struct xl_type xl_devs[] = { 164 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT, 165 "3Com 3c900-TPO Etherlink XL" }, 166 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT_COMBO, 167 "3Com 3c900-COMBO Etherlink XL" }, 168 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10_100BT, 169 "3Com 3c905-TX Fast Etherlink XL" }, 170 { TC_VENDORID, TC_DEVICEID_BOOMERANG_100BT4, 171 "3Com 3c905-T4 Fast Etherlink XL" }, 172 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT, 173 "3Com 3c900B-TPO Etherlink XL" }, 174 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_COMBO, 175 "3Com 3c900B-COMBO Etherlink XL" }, 176 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_TPC, 177 "3Com 3c900B-TPC Etherlink XL" }, 178 { TC_VENDORID, TC_DEVICEID_CYCLONE_10FL, 179 "3Com 3c900B-FL Etherlink XL" }, 180 { TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT, 181 "3Com 3c905B-TX Fast Etherlink XL" }, 182 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100BT4, 183 "3Com 3c905B-T4 Fast Etherlink XL" }, 184 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100FX, 185 "3Com 3c905B-FX/SC Fast Etherlink XL" }, 186 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100_COMBO, 187 "3Com 3c905B-COMBO Fast Etherlink XL" }, 188 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT, 189 "3Com 3c905C-TX Fast Etherlink XL" }, 190 { TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT_SERV, 191 "3Com 3c980 Fast Etherlink XL" }, 192 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_SERV, 193 "3Com 3c980C Fast Etherlink XL" }, 194 { TC_VENDORID, TC_DEVICEID_HURRICANE_SOHO100TX, 195 "3Com 3cSOHO100-TX OfficeConnect" }, 196 { TC_VENDORID, TC_DEVICEID_TORNADO_HOMECONNECT, 197 "3Com 3c450-TX HomeConnect" }, 198 { TC_VENDORID, TC_DEVICEID_HURRICANE_556, 199 "3Com 3c556 Fast Etherlink XL" }, 200 { TC_VENDORID, TC_DEVICEID_HURRICANE_556B, 201 "3Com 3c556B Fast Etherlink XL" }, 202 { TC_VENDORID, TC_DEVICEID_HURRICANE_575A, 203 "3Com 3c575TX Fast Etherlink XL" }, 204 { TC_VENDORID, TC_DEVICEID_HURRICANE_575B, 205 "3Com 3c575B Fast Etherlink XL" }, 206 { TC_VENDORID, TC_DEVICEID_HURRICANE_575C, 207 "3Com 3c575C Fast Etherlink XL" }, 208 { TC_VENDORID, TC_DEVICEID_HURRICANE_656, 209 "3Com 3c656 Fast Etherlink XL" }, 210 { TC_VENDORID, TC_DEVICEID_HURRICANE_656B, 211 "3Com 3c656B Fast Etherlink XL" }, 212 { TC_VENDORID, TC_DEVICEID_TORNADO_656C, 213 "3Com 3c656C Fast Etherlink XL" }, 214 { 0, 0, NULL } 215}; 216 217static int xl_probe (device_t); 218static int xl_attach (device_t); 219static int xl_detach (device_t); 220 221static int xl_newbuf (struct xl_softc *, struct xl_chain_onefrag *); 222static void xl_stats_update (void *); 223static int xl_encap (struct xl_softc *, struct xl_chain *, 224 struct mbuf *); 225static int xl_encap_90xB (struct xl_softc *, struct xl_chain *, 226 struct mbuf *); 227 228static void xl_rxeof (struct xl_softc *); 229static int xl_rx_resync (struct xl_softc *); 230static void xl_txeof (struct xl_softc *); 231static void xl_txeof_90xB (struct xl_softc *); 232static void xl_txeoc (struct xl_softc *); 233static void xl_intr (void *); 234static void xl_start (struct ifnet *); 235static void xl_start_90xB (struct ifnet *); 236static int xl_ioctl (struct ifnet *, u_long, caddr_t); 237static void xl_init (void *); 238static void xl_stop (struct xl_softc *); 239static void xl_watchdog (struct ifnet *); 240static void xl_shutdown (device_t); 241static int xl_suspend (device_t); 242static int xl_resume (device_t); 243 244static int xl_ifmedia_upd (struct ifnet *); 245static void xl_ifmedia_sts (struct ifnet *, struct ifmediareq *); 246 247static int xl_eeprom_wait (struct xl_softc *); 248static int xl_read_eeprom (struct xl_softc *, caddr_t, int, int, int); 249static void xl_mii_sync (struct xl_softc *); 250static void xl_mii_send (struct xl_softc *, u_int32_t, int); 251static int xl_mii_readreg (struct xl_softc *, struct xl_mii_frame *); 252static int xl_mii_writereg (struct xl_softc *, struct xl_mii_frame *); 253 254static void xl_setcfg (struct xl_softc *); 255static void xl_setmode (struct xl_softc *, int); 256static u_int8_t xl_calchash (caddr_t); 257static void xl_setmulti (struct xl_softc *); 258static void xl_setmulti_hash (struct xl_softc *); 259static void xl_reset (struct xl_softc *); 260static int xl_list_rx_init (struct xl_softc *); 261static int xl_list_tx_init (struct xl_softc *); 262static int xl_list_tx_init_90xB (struct xl_softc *); 263static void xl_wait (struct xl_softc *); 264static void xl_mediacheck (struct xl_softc *); 265static void xl_choose_xcvr (struct xl_softc *, int); 266#ifdef notdef 267static void xl_testpacket (struct xl_softc *); 268#endif 269 270static int xl_miibus_readreg (device_t, int, int); 271static int xl_miibus_writereg (device_t, int, int, int); 272static void xl_miibus_statchg (device_t); 273static void xl_miibus_mediainit (device_t); 274 275#ifdef XL_USEIOSPACE 276#define XL_RES SYS_RES_IOPORT 277#define XL_RID XL_PCI_LOIO 278#else 279#define XL_RES SYS_RES_MEMORY 280#define XL_RID XL_PCI_LOMEM 281#endif 282 283static device_method_t xl_methods[] = { 284 /* Device interface */ 285 DEVMETHOD(device_probe, xl_probe), 286 DEVMETHOD(device_attach, xl_attach), 287 DEVMETHOD(device_detach, xl_detach), 288 DEVMETHOD(device_shutdown, xl_shutdown), 289 DEVMETHOD(device_suspend, xl_suspend), 290 DEVMETHOD(device_resume, xl_resume), 291 292 /* bus interface */ 293 DEVMETHOD(bus_print_child, bus_generic_print_child), 294 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 295 296 /* MII interface */ 297 DEVMETHOD(miibus_readreg, xl_miibus_readreg), 298 DEVMETHOD(miibus_writereg, xl_miibus_writereg), 299 DEVMETHOD(miibus_statchg, xl_miibus_statchg), 300 DEVMETHOD(miibus_mediainit, xl_miibus_mediainit), 301 302 { 0, 0 } 303}; 304 305static driver_t xl_driver = { 306 "xl", 307 xl_methods, 308 sizeof(struct xl_softc) 309}; 310 311static devclass_t xl_devclass; 312 313DRIVER_MODULE(if_xl, cardbus, xl_driver, xl_devclass, 0, 0); 314DRIVER_MODULE(if_xl, pci, xl_driver, xl_devclass, 0, 0); 315DRIVER_MODULE(miibus, xl, miibus_driver, miibus_devclass, 0, 0); 316 317/* 318 * Murphy's law says that it's possible the chip can wedge and 319 * the 'command in progress' bit may never clear. Hence, we wait 320 * only a finite amount of time to avoid getting caught in an 321 * infinite loop. Normally this delay routine would be a macro, 322 * but it isn't called during normal operation so we can afford 323 * to make it a function. 324 */ 325static void xl_wait(sc) 326 struct xl_softc *sc; 327{ 328 register int i; 329 330 for (i = 0; i < XL_TIMEOUT; i++) { 331 if (!(CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY)) 332 break; 333 } 334 335 if (i == XL_TIMEOUT) 336 printf("xl%d: command never completed!\n", sc->xl_unit); 337 338 return; 339} 340 341/* 342 * MII access routines are provided for adapters with external 343 * PHYs (3c905-TX, 3c905-T4, 3c905B-T4) and those with built-in 344 * autoneg logic that's faked up to look like a PHY (3c905B-TX). 345 * Note: if you don't perform the MDIO operations just right, 346 * it's possible to end up with code that works correctly with 347 * some chips/CPUs/processor speeds/bus speeds/etc but not 348 * with others. 349 */ 350#define MII_SET(x) \ 351 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, \ 352 CSR_READ_2(sc, XL_W4_PHY_MGMT) | x) 353 354#define MII_CLR(x) \ 355 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, \ 356 CSR_READ_2(sc, XL_W4_PHY_MGMT) & ~x) 357 358/* 359 * Sync the PHYs by setting data bit and strobing the clock 32 times. 360 */ 361static void xl_mii_sync(sc) 362 struct xl_softc *sc; 363{ 364 register int i; 365 366 XL_SEL_WIN(4); 367 MII_SET(XL_MII_DIR|XL_MII_DATA); 368 369 for (i = 0; i < 32; i++) { 370 MII_SET(XL_MII_CLK); 371 DELAY(1); 372 MII_CLR(XL_MII_CLK); 373 DELAY(1); 374 } 375 376 return; 377} 378 379/* 380 * Clock a series of bits through the MII. 381 */ 382static void xl_mii_send(sc, bits, cnt) 383 struct xl_softc *sc; 384 u_int32_t bits; 385 int cnt; 386{ 387 int i; 388 389 XL_SEL_WIN(4); 390 MII_CLR(XL_MII_CLK); 391 392 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 393 if (bits & i) { 394 MII_SET(XL_MII_DATA); 395 } else { 396 MII_CLR(XL_MII_DATA); 397 } 398 DELAY(1); 399 MII_CLR(XL_MII_CLK); 400 DELAY(1); 401 MII_SET(XL_MII_CLK); 402 } 403} 404 405/* 406 * Read an PHY register through the MII. 407 */ 408static int xl_mii_readreg(sc, frame) 409 struct xl_softc *sc; 410 struct xl_mii_frame *frame; 411 412{ 413 int i, ack; 414 415 XL_LOCK(sc); 416 417 /* 418 * Set up frame for RX. 419 */ 420 frame->mii_stdelim = XL_MII_STARTDELIM; 421 frame->mii_opcode = XL_MII_READOP; 422 frame->mii_turnaround = 0; 423 frame->mii_data = 0; 424 425 /* 426 * Select register window 4. 427 */ 428 429 XL_SEL_WIN(4); 430 431 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, 0); 432 /* 433 * Turn on data xmit. 434 */ 435 MII_SET(XL_MII_DIR); 436 437 xl_mii_sync(sc); 438 439 /* 440 * Send command/address info. 441 */ 442 xl_mii_send(sc, frame->mii_stdelim, 2); 443 xl_mii_send(sc, frame->mii_opcode, 2); 444 xl_mii_send(sc, frame->mii_phyaddr, 5); 445 xl_mii_send(sc, frame->mii_regaddr, 5); 446 447 /* Idle bit */ 448 MII_CLR((XL_MII_CLK|XL_MII_DATA)); 449 DELAY(1); 450 MII_SET(XL_MII_CLK); 451 DELAY(1); 452 453 /* Turn off xmit. */ 454 MII_CLR(XL_MII_DIR); 455 456 /* Check for ack */ 457 MII_CLR(XL_MII_CLK); 458 DELAY(1); 459 MII_SET(XL_MII_CLK); 460 DELAY(1); 461 ack = CSR_READ_2(sc, XL_W4_PHY_MGMT) & XL_MII_DATA; 462 463 /* 464 * Now try reading data bits. If the ack failed, we still 465 * need to clock through 16 cycles to keep the PHY(s) in sync. 466 */ 467 if (ack) { 468 for(i = 0; i < 16; i++) { 469 MII_CLR(XL_MII_CLK); 470 DELAY(1); 471 MII_SET(XL_MII_CLK); 472 DELAY(1); 473 } 474 goto fail; 475 } 476 477 for (i = 0x8000; i; i >>= 1) { 478 MII_CLR(XL_MII_CLK); 479 DELAY(1); 480 if (!ack) { 481 if (CSR_READ_2(sc, XL_W4_PHY_MGMT) & XL_MII_DATA) 482 frame->mii_data |= i; 483 DELAY(1); 484 } 485 MII_SET(XL_MII_CLK); 486 DELAY(1); 487 } 488 489fail: 490 491 MII_CLR(XL_MII_CLK); 492 DELAY(1); 493 MII_SET(XL_MII_CLK); 494 DELAY(1); 495 496 XL_UNLOCK(sc); 497 498 if (ack) 499 return(1); 500 return(0); 501} 502 503/* 504 * Write to a PHY register through the MII. 505 */ 506static int xl_mii_writereg(sc, frame) 507 struct xl_softc *sc; 508 struct xl_mii_frame *frame; 509 510{ 511 XL_LOCK(sc); 512 513 /* 514 * Set up frame for TX. 515 */ 516 517 frame->mii_stdelim = XL_MII_STARTDELIM; 518 frame->mii_opcode = XL_MII_WRITEOP; 519 frame->mii_turnaround = XL_MII_TURNAROUND; 520 521 /* 522 * Select the window 4. 523 */ 524 XL_SEL_WIN(4); 525 526 /* 527 * Turn on data output. 528 */ 529 MII_SET(XL_MII_DIR); 530 531 xl_mii_sync(sc); 532 533 xl_mii_send(sc, frame->mii_stdelim, 2); 534 xl_mii_send(sc, frame->mii_opcode, 2); 535 xl_mii_send(sc, frame->mii_phyaddr, 5); 536 xl_mii_send(sc, frame->mii_regaddr, 5); 537 xl_mii_send(sc, frame->mii_turnaround, 2); 538 xl_mii_send(sc, frame->mii_data, 16); 539 540 /* Idle bit. */ 541 MII_SET(XL_MII_CLK); 542 DELAY(1); 543 MII_CLR(XL_MII_CLK); 544 DELAY(1); 545 546 /* 547 * Turn off xmit. 548 */ 549 MII_CLR(XL_MII_DIR); 550 551 XL_UNLOCK(sc); 552 553 return(0); 554} 555 556static int xl_miibus_readreg(dev, phy, reg) 557 device_t dev; 558 int phy, reg; 559{ 560 struct xl_softc *sc; 561 struct xl_mii_frame frame; 562 563 sc = device_get_softc(dev); 564 565 /* 566 * Pretend that PHYs are only available at MII address 24. 567 * This is to guard against problems with certain 3Com ASIC 568 * revisions that incorrectly map the internal transceiver 569 * control registers at all MII addresses. This can cause 570 * the miibus code to attach the same PHY several times over. 571 */ 572 if ((!(sc->xl_flags & XL_FLAG_PHYOK)) && phy != 24) 573 return(0); 574 575 bzero((char *)&frame, sizeof(frame)); 576 577 frame.mii_phyaddr = phy; 578 frame.mii_regaddr = reg; 579 xl_mii_readreg(sc, &frame); 580 581 return(frame.mii_data); 582} 583 584static int xl_miibus_writereg(dev, phy, reg, data) 585 device_t dev; 586 int phy, reg, data; 587{ 588 struct xl_softc *sc; 589 struct xl_mii_frame frame; 590 591 sc = device_get_softc(dev); 592 593 if ((!(sc->xl_flags & XL_FLAG_PHYOK)) && phy != 24) 594 return(0); 595 596 bzero((char *)&frame, sizeof(frame)); 597 598 frame.mii_phyaddr = phy; 599 frame.mii_regaddr = reg; 600 frame.mii_data = data; 601 602 xl_mii_writereg(sc, &frame); 603 604 return(0); 605} 606 607static void xl_miibus_statchg(dev) 608 device_t dev; 609{ 610 struct xl_softc *sc; 611 struct mii_data *mii; 612 613 614 sc = device_get_softc(dev); 615 mii = device_get_softc(sc->xl_miibus); 616 617 XL_LOCK(sc); 618 619 xl_setcfg(sc); 620 621 /* Set ASIC's duplex mode to match the PHY. */ 622 XL_SEL_WIN(3); 623 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 624 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX); 625 else 626 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, 627 (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX)); 628 629 XL_UNLOCK(sc); 630 631 return; 632} 633 634/* 635 * Special support for the 3c905B-COMBO. This card has 10/100 support 636 * plus BNC and AUI ports. This means we will have both an miibus attached 637 * plus some non-MII media settings. In order to allow this, we have to 638 * add the extra media to the miibus's ifmedia struct, but we can't do 639 * that during xl_attach() because the miibus hasn't been attached yet. 640 * So instead, we wait until the miibus probe/attach is done, at which 641 * point we will get a callback telling is that it's safe to add our 642 * extra media. 643 */ 644static void xl_miibus_mediainit(dev) 645 device_t dev; 646{ 647 struct xl_softc *sc; 648 struct mii_data *mii; 649 struct ifmedia *ifm; 650 651 sc = device_get_softc(dev); 652 mii = device_get_softc(sc->xl_miibus); 653 ifm = &mii->mii_media; 654 655 XL_LOCK(sc); 656 657 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) { 658 /* 659 * Check for a 10baseFL board in disguise. 660 */ 661 if (sc->xl_type == XL_TYPE_905B && 662 sc->xl_media == XL_MEDIAOPT_10FL) { 663 if (bootverbose) 664 printf("xl%d: found 10baseFL\n", sc->xl_unit); 665 ifmedia_add(ifm, IFM_ETHER|IFM_10_FL, 0, NULL); 666 ifmedia_add(ifm, IFM_ETHER|IFM_10_FL|IFM_HDX, 0, NULL); 667 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX) 668 ifmedia_add(ifm, 669 IFM_ETHER|IFM_10_FL|IFM_FDX, 0, NULL); 670 } else { 671 if (bootverbose) 672 printf("xl%d: found AUI\n", sc->xl_unit); 673 ifmedia_add(ifm, IFM_ETHER|IFM_10_5, 0, NULL); 674 } 675 } 676 677 if (sc->xl_media & XL_MEDIAOPT_BNC) { 678 if (bootverbose) 679 printf("xl%d: found BNC\n", sc->xl_unit); 680 ifmedia_add(ifm, IFM_ETHER|IFM_10_2, 0, NULL); 681 } 682 683 XL_UNLOCK(sc); 684 685 return; 686} 687 688/* 689 * The EEPROM is slow: give it time to come ready after issuing 690 * it a command. 691 */ 692static int xl_eeprom_wait(sc) 693 struct xl_softc *sc; 694{ 695 int i; 696 697 for (i = 0; i < 100; i++) { 698 if (CSR_READ_2(sc, XL_W0_EE_CMD) & XL_EE_BUSY) 699 DELAY(162); 700 else 701 break; 702 } 703 704 if (i == 100) { 705 printf("xl%d: eeprom failed to come ready\n", sc->xl_unit); 706 return(1); 707 } 708 709 return(0); 710} 711 712/* 713 * Read a sequence of words from the EEPROM. Note that ethernet address 714 * data is stored in the EEPROM in network byte order. 715 */ 716static int xl_read_eeprom(sc, dest, off, cnt, swap) 717 struct xl_softc *sc; 718 caddr_t dest; 719 int off; 720 int cnt; 721 int swap; 722{ 723 int err = 0, i; 724 u_int16_t word = 0, *ptr; 725#define EEPROM_5BIT_OFFSET(A) ((((A) << 2) & 0x7F00) | ((A) & 0x003F)) 726#define EEPROM_8BIT_OFFSET(A) ((A) & 0x003F) 727 /* WARNING! DANGER! 728 * It's easy to accidentally overwrite the rom content! 729 * Note: the 3c575 uses 8bit EEPROM offsets. 730 */ 731 XL_SEL_WIN(0); 732 733 if (xl_eeprom_wait(sc)) 734 return(1); 735 736 if (sc->xl_flags & XL_FLAG_EEPROM_OFFSET_30) 737 off += 0x30; 738 739 for (i = 0; i < cnt; i++) { 740 if (sc->xl_flags & XL_FLAG_8BITROM) 741 CSR_WRITE_2(sc, XL_W0_EE_CMD, 742 XL_EE_8BIT_READ | EEPROM_8BIT_OFFSET(off + i)); 743 else 744 CSR_WRITE_2(sc, XL_W0_EE_CMD, 745 XL_EE_READ | EEPROM_5BIT_OFFSET(off + i)); 746 err = xl_eeprom_wait(sc); 747 if (err) 748 break; 749 word = CSR_READ_2(sc, XL_W0_EE_DATA); 750 ptr = (u_int16_t *)(dest + (i * 2)); 751 if (swap) 752 *ptr = ntohs(word); 753 else 754 *ptr = word; 755 } 756 757 return(err ? 1 : 0); 758} 759 760/* 761 * This routine is taken from the 3Com Etherlink XL manual, 762 * page 10-7. It calculates a CRC of the supplied multicast 763 * group address and returns the lower 8 bits, which are used 764 * as the multicast filter position. 765 * Note: the 3c905B currently only supports a 64-bit hash table, 766 * which means we really only need 6 bits, but the manual indicates 767 * that future chip revisions will have a 256-bit hash table, 768 * hence the routine is set up to calculate 8 bits of position 769 * info in case we need it some day. 770 * Note II, The Sequel: _CURRENT_ versions of the 3c905B have a 771 * 256 bit hash table. This means we have to use all 8 bits regardless. 772 * On older cards, the upper 2 bits will be ignored. Grrrr.... 773 */ 774static u_int8_t xl_calchash(addr) 775 caddr_t addr; 776{ 777 u_int32_t crc, carry; 778 int i, j; 779 u_int8_t c; 780 781 /* Compute CRC for the address value. */ 782 crc = 0xFFFFFFFF; /* initial value */ 783 784 for (i = 0; i < 6; i++) { 785 c = *(addr + i); 786 for (j = 0; j < 8; j++) { 787 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 788 crc <<= 1; 789 c >>= 1; 790 if (carry) 791 crc = (crc ^ 0x04c11db6) | carry; 792 } 793 } 794 795 /* return the filter bit position */ 796 return(crc & 0x000000FF); 797} 798 799/* 800 * NICs older than the 3c905B have only one multicast option, which 801 * is to enable reception of all multicast frames. 802 */ 803static void xl_setmulti(sc) 804 struct xl_softc *sc; 805{ 806 struct ifnet *ifp; 807 struct ifmultiaddr *ifma; 808 u_int8_t rxfilt; 809 int mcnt = 0; 810 811 ifp = &sc->arpcom.ac_if; 812 813 XL_SEL_WIN(5); 814 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); 815 816 if (ifp->if_flags & IFF_ALLMULTI) { 817 rxfilt |= XL_RXFILTER_ALLMULTI; 818 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 819 return; 820 } 821 822 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) 823 mcnt++; 824 825 if (mcnt) 826 rxfilt |= XL_RXFILTER_ALLMULTI; 827 else 828 rxfilt &= ~XL_RXFILTER_ALLMULTI; 829 830 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 831 832 return; 833} 834 835/* 836 * 3c905B adapters have a hash filter that we can program. 837 */ 838static void xl_setmulti_hash(sc) 839 struct xl_softc *sc; 840{ 841 struct ifnet *ifp; 842 int h = 0, i; 843 struct ifmultiaddr *ifma; 844 u_int8_t rxfilt; 845 int mcnt = 0; 846 847 ifp = &sc->arpcom.ac_if; 848 849 XL_SEL_WIN(5); 850 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); 851 852 if (ifp->if_flags & IFF_ALLMULTI) { 853 rxfilt |= XL_RXFILTER_ALLMULTI; 854 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 855 return; 856 } else 857 rxfilt &= ~XL_RXFILTER_ALLMULTI; 858 859 860 /* first, zot all the existing hash bits */ 861 for (i = 0; i < XL_HASHFILT_SIZE; i++) 862 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_HASH|i); 863 864 /* now program new ones */ 865 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 866 if (ifma->ifma_addr->sa_family != AF_LINK) 867 continue; 868 h = xl_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 869 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_HASH|XL_HASH_SET|h); 870 mcnt++; 871 } 872 873 if (mcnt) 874 rxfilt |= XL_RXFILTER_MULTIHASH; 875 else 876 rxfilt &= ~XL_RXFILTER_MULTIHASH; 877 878 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 879 880 return; 881} 882 883#ifdef notdef 884static void xl_testpacket(sc) 885 struct xl_softc *sc; 886{ 887 struct mbuf *m; 888 struct ifnet *ifp; 889 890 ifp = &sc->arpcom.ac_if; 891 892 MGETHDR(m, M_DONTWAIT, MT_DATA); 893 894 if (m == NULL) 895 return; 896 897 bcopy(&sc->arpcom.ac_enaddr, 898 mtod(m, struct ether_header *)->ether_dhost, ETHER_ADDR_LEN); 899 bcopy(&sc->arpcom.ac_enaddr, 900 mtod(m, struct ether_header *)->ether_shost, ETHER_ADDR_LEN); 901 mtod(m, struct ether_header *)->ether_type = htons(3); 902 mtod(m, unsigned char *)[14] = 0; 903 mtod(m, unsigned char *)[15] = 0; 904 mtod(m, unsigned char *)[16] = 0xE3; 905 m->m_len = m->m_pkthdr.len = sizeof(struct ether_header) + 3; 906 IF_ENQUEUE(&ifp->if_snd, m); 907 xl_start(ifp); 908 909 return; 910} 911#endif 912 913static void xl_setcfg(sc) 914 struct xl_softc *sc; 915{ 916 u_int32_t icfg; 917 918 XL_SEL_WIN(3); 919 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG); 920 icfg &= ~XL_ICFG_CONNECTOR_MASK; 921 if (sc->xl_media & XL_MEDIAOPT_MII || 922 sc->xl_media & XL_MEDIAOPT_BT4) 923 icfg |= (XL_XCVR_MII << XL_ICFG_CONNECTOR_BITS); 924 if (sc->xl_media & XL_MEDIAOPT_BTX) 925 icfg |= (XL_XCVR_AUTO << XL_ICFG_CONNECTOR_BITS); 926 927 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg); 928 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 929 930 return; 931} 932 933static void xl_setmode(sc, media) 934 struct xl_softc *sc; 935 int media; 936{ 937 u_int32_t icfg; 938 u_int16_t mediastat; 939 940 printf("xl%d: selecting ", sc->xl_unit); 941 942 XL_SEL_WIN(4); 943 mediastat = CSR_READ_2(sc, XL_W4_MEDIA_STATUS); 944 XL_SEL_WIN(3); 945 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG); 946 947 if (sc->xl_media & XL_MEDIAOPT_BT) { 948 if (IFM_SUBTYPE(media) == IFM_10_T) { 949 printf("10baseT transceiver, "); 950 sc->xl_xcvr = XL_XCVR_10BT; 951 icfg &= ~XL_ICFG_CONNECTOR_MASK; 952 icfg |= (XL_XCVR_10BT << XL_ICFG_CONNECTOR_BITS); 953 mediastat |= XL_MEDIASTAT_LINKBEAT| 954 XL_MEDIASTAT_JABGUARD; 955 mediastat &= ~XL_MEDIASTAT_SQEENB; 956 } 957 } 958 959 if (sc->xl_media & XL_MEDIAOPT_BFX) { 960 if (IFM_SUBTYPE(media) == IFM_100_FX) { 961 printf("100baseFX port, "); 962 sc->xl_xcvr = XL_XCVR_100BFX; 963 icfg &= ~XL_ICFG_CONNECTOR_MASK; 964 icfg |= (XL_XCVR_100BFX << XL_ICFG_CONNECTOR_BITS); 965 mediastat |= XL_MEDIASTAT_LINKBEAT; 966 mediastat &= ~XL_MEDIASTAT_SQEENB; 967 } 968 } 969 970 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) { 971 if (IFM_SUBTYPE(media) == IFM_10_5) { 972 printf("AUI port, "); 973 sc->xl_xcvr = XL_XCVR_AUI; 974 icfg &= ~XL_ICFG_CONNECTOR_MASK; 975 icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS); 976 mediastat &= ~(XL_MEDIASTAT_LINKBEAT| 977 XL_MEDIASTAT_JABGUARD); 978 mediastat |= ~XL_MEDIASTAT_SQEENB; 979 } 980 if (IFM_SUBTYPE(media) == IFM_10_FL) { 981 printf("10baseFL transceiver, "); 982 sc->xl_xcvr = XL_XCVR_AUI; 983 icfg &= ~XL_ICFG_CONNECTOR_MASK; 984 icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS); 985 mediastat &= ~(XL_MEDIASTAT_LINKBEAT| 986 XL_MEDIASTAT_JABGUARD); 987 mediastat |= ~XL_MEDIASTAT_SQEENB; 988 } 989 } 990 991 if (sc->xl_media & XL_MEDIAOPT_BNC) { 992 if (IFM_SUBTYPE(media) == IFM_10_2) { 993 printf("BNC port, "); 994 sc->xl_xcvr = XL_XCVR_COAX; 995 icfg &= ~XL_ICFG_CONNECTOR_MASK; 996 icfg |= (XL_XCVR_COAX << XL_ICFG_CONNECTOR_BITS); 997 mediastat &= ~(XL_MEDIASTAT_LINKBEAT| 998 XL_MEDIASTAT_JABGUARD| 999 XL_MEDIASTAT_SQEENB); 1000 } 1001 } 1002 1003 if ((media & IFM_GMASK) == IFM_FDX || 1004 IFM_SUBTYPE(media) == IFM_100_FX) { 1005 printf("full duplex\n"); 1006 XL_SEL_WIN(3); 1007 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX); 1008 } else { 1009 printf("half duplex\n"); 1010 XL_SEL_WIN(3); 1011 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, 1012 (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX)); 1013 } 1014 1015 if (IFM_SUBTYPE(media) == IFM_10_2) 1016 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START); 1017 else 1018 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 1019 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg); 1020 XL_SEL_WIN(4); 1021 CSR_WRITE_2(sc, XL_W4_MEDIA_STATUS, mediastat); 1022 DELAY(800); 1023 XL_SEL_WIN(7); 1024 1025 return; 1026} 1027 1028static void xl_reset(sc) 1029 struct xl_softc *sc; 1030{ 1031 register int i; 1032 1033 XL_SEL_WIN(0); 1034 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RESET | 1035 ((sc->xl_flags & XL_FLAG_WEIRDRESET) ? 1036 XL_RESETOPT_DISADVFD:0)); 1037 1038 for (i = 0; i < XL_TIMEOUT; i++) { 1039 DELAY(10); 1040 if (!(CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY)) 1041 break; 1042 } 1043 1044 if (i == XL_TIMEOUT) 1045 printf("xl%d: reset didn't complete\n", sc->xl_unit); 1046 1047 /* Reset TX and RX. */ 1048 /* Note: the RX reset takes an absurd amount of time 1049 * on newer versions of the Tornado chips such as those 1050 * on the 3c905CX and newer 3c908C cards. We wait an 1051 * extra amount of time so that xl_wait() doesn't complain 1052 * and annoy the users. 1053 */ 1054 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 1055 DELAY(100000); 1056 xl_wait(sc); 1057 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 1058 xl_wait(sc); 1059 1060 if (sc->xl_flags & XL_FLAG_INVERT_LED_PWR || 1061 sc->xl_flags & XL_FLAG_INVERT_MII_PWR) { 1062 XL_SEL_WIN(2); 1063 CSR_WRITE_2(sc, XL_W2_RESET_OPTIONS, CSR_READ_2(sc, 1064 XL_W2_RESET_OPTIONS) 1065 | ((sc->xl_flags & XL_FLAG_INVERT_LED_PWR)?XL_RESETOPT_INVERT_LED:0) 1066 | ((sc->xl_flags & XL_FLAG_INVERT_MII_PWR)?XL_RESETOPT_INVERT_MII:0) 1067 ); 1068 } 1069 1070 /* Wait a little while for the chip to get its brains in order. */ 1071 DELAY(100000); 1072 return; 1073} 1074 1075/* 1076 * Probe for a 3Com Etherlink XL chip. Check the PCI vendor and device 1077 * IDs against our list and return a device name if we find a match. 1078 */ 1079static int xl_probe(dev) 1080 device_t dev; 1081{ 1082 struct xl_type *t; 1083 1084 t = xl_devs; 1085 1086 while(t->xl_name != NULL) { 1087 if ((pci_get_vendor(dev) == t->xl_vid) && 1088 (pci_get_device(dev) == t->xl_did)) { 1089 device_set_desc(dev, t->xl_name); 1090 return(0); 1091 } 1092 t++; 1093 } 1094 1095 return(ENXIO); 1096} 1097 1098/* 1099 * This routine is a kludge to work around possible hardware faults 1100 * or manufacturing defects that can cause the media options register 1101 * (or reset options register, as it's called for the first generation 1102 * 3c90x adapters) to return an incorrect result. I have encountered 1103 * one Dell Latitude laptop docking station with an integrated 3c905-TX 1104 * which doesn't have any of the 'mediaopt' bits set. This screws up 1105 * the attach routine pretty badly because it doesn't know what media 1106 * to look for. If we find ourselves in this predicament, this routine 1107 * will try to guess the media options values and warn the user of a 1108 * possible manufacturing defect with his adapter/system/whatever. 1109 */ 1110static void xl_mediacheck(sc) 1111 struct xl_softc *sc; 1112{ 1113 1114 /* 1115 * If some of the media options bits are set, assume they are 1116 * correct. If not, try to figure it out down below. 1117 * XXX I should check for 10baseFL, but I don't have an adapter 1118 * to test with. 1119 */ 1120 if (sc->xl_media & (XL_MEDIAOPT_MASK & ~XL_MEDIAOPT_VCO)) { 1121 /* 1122 * Check the XCVR value. If it's not in the normal range 1123 * of values, we need to fake it up here. 1124 */ 1125 if (sc->xl_xcvr <= XL_XCVR_AUTO) 1126 return; 1127 else { 1128 printf("xl%d: bogus xcvr value " 1129 "in EEPROM (%x)\n", sc->xl_unit, sc->xl_xcvr); 1130 printf("xl%d: choosing new default based " 1131 "on card type\n", sc->xl_unit); 1132 } 1133 } else { 1134 if (sc->xl_type == XL_TYPE_905B && 1135 sc->xl_media & XL_MEDIAOPT_10FL) 1136 return; 1137 printf("xl%d: WARNING: no media options bits set in " 1138 "the media options register!!\n", sc->xl_unit); 1139 printf("xl%d: this could be a manufacturing defect in " 1140 "your adapter or system\n", sc->xl_unit); 1141 printf("xl%d: attempting to guess media type; you " 1142 "should probably consult your vendor\n", sc->xl_unit); 1143 } 1144 1145 xl_choose_xcvr(sc, 1); 1146 1147 return; 1148} 1149 1150static void xl_choose_xcvr(sc, verbose) 1151 struct xl_softc *sc; 1152 int verbose; 1153{ 1154 u_int16_t devid; 1155 1156 /* 1157 * Read the device ID from the EEPROM. 1158 * This is what's loaded into the PCI device ID register, so it has 1159 * to be correct otherwise we wouldn't have gotten this far. 1160 */ 1161 xl_read_eeprom(sc, (caddr_t)&devid, XL_EE_PRODID, 1, 0); 1162 1163 switch(devid) { 1164 case TC_DEVICEID_BOOMERANG_10BT: /* 3c900-TPO */ 1165 case TC_DEVICEID_KRAKATOA_10BT: /* 3c900B-TPO */ 1166 sc->xl_media = XL_MEDIAOPT_BT; 1167 sc->xl_xcvr = XL_XCVR_10BT; 1168 if (verbose) 1169 printf("xl%d: guessing 10BaseT " 1170 "transceiver\n", sc->xl_unit); 1171 break; 1172 case TC_DEVICEID_BOOMERANG_10BT_COMBO: /* 3c900-COMBO */ 1173 case TC_DEVICEID_KRAKATOA_10BT_COMBO: /* 3c900B-COMBO */ 1174 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI; 1175 sc->xl_xcvr = XL_XCVR_10BT; 1176 if (verbose) 1177 printf("xl%d: guessing COMBO " 1178 "(AUI/BNC/TP)\n", sc->xl_unit); 1179 break; 1180 case TC_DEVICEID_KRAKATOA_10BT_TPC: /* 3c900B-TPC */ 1181 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC; 1182 sc->xl_xcvr = XL_XCVR_10BT; 1183 if (verbose) 1184 printf("xl%d: guessing TPC (BNC/TP)\n", sc->xl_unit); 1185 break; 1186 case TC_DEVICEID_CYCLONE_10FL: /* 3c900B-FL */ 1187 sc->xl_media = XL_MEDIAOPT_10FL; 1188 sc->xl_xcvr = XL_XCVR_AUI; 1189 if (verbose) 1190 printf("xl%d: guessing 10baseFL\n", sc->xl_unit); 1191 break; 1192 case TC_DEVICEID_BOOMERANG_10_100BT: /* 3c905-TX */ 1193 case TC_DEVICEID_HURRICANE_556: /* 3c556 */ 1194 case TC_DEVICEID_HURRICANE_556B: /* 3c556B */ 1195 case TC_DEVICEID_HURRICANE_575A: /* 3c575TX */ 1196 case TC_DEVICEID_HURRICANE_575B: /* 3c575B */ 1197 case TC_DEVICEID_HURRICANE_575C: /* 3c575C */ 1198 case TC_DEVICEID_HURRICANE_656: /* 3c656 */ 1199 case TC_DEVICEID_HURRICANE_656B: /* 3c656B */ 1200 case TC_DEVICEID_TORNADO_656C: /* 3c656C */ 1201 sc->xl_media = XL_MEDIAOPT_MII; 1202 sc->xl_xcvr = XL_XCVR_MII; 1203 if (verbose) 1204 printf("xl%d: guessing MII\n", sc->xl_unit); 1205 break; 1206 case TC_DEVICEID_BOOMERANG_100BT4: /* 3c905-T4 */ 1207 case TC_DEVICEID_CYCLONE_10_100BT4: /* 3c905B-T4 */ 1208 sc->xl_media = XL_MEDIAOPT_BT4; 1209 sc->xl_xcvr = XL_XCVR_MII; 1210 if (verbose) 1211 printf("xl%d: guessing 100BaseT4/MII\n", sc->xl_unit); 1212 break; 1213 case TC_DEVICEID_HURRICANE_10_100BT: /* 3c905B-TX */ 1214 case TC_DEVICEID_HURRICANE_10_100BT_SERV:/*3c980-TX */ 1215 case TC_DEVICEID_TORNADO_10_100BT_SERV: /* 3c980C-TX */ 1216 case TC_DEVICEID_HURRICANE_SOHO100TX: /* 3cSOHO100-TX */ 1217 case TC_DEVICEID_TORNADO_10_100BT: /* 3c905C-TX */ 1218 case TC_DEVICEID_TORNADO_HOMECONNECT: /* 3c450-TX */ 1219 sc->xl_media = XL_MEDIAOPT_BTX; 1220 sc->xl_xcvr = XL_XCVR_AUTO; 1221 if (verbose) 1222 printf("xl%d: guessing 10/100 internal\n", sc->xl_unit); 1223 break; 1224 case TC_DEVICEID_CYCLONE_10_100_COMBO: /* 3c905B-COMBO */ 1225 sc->xl_media = XL_MEDIAOPT_BTX|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI; 1226 sc->xl_xcvr = XL_XCVR_AUTO; 1227 if (verbose) 1228 printf("xl%d: guessing 10/100 " 1229 "plus BNC/AUI\n", sc->xl_unit); 1230 break; 1231 default: 1232 printf("xl%d: unknown device ID: %x -- " 1233 "defaulting to 10baseT\n", sc->xl_unit, devid); 1234 sc->xl_media = XL_MEDIAOPT_BT; 1235 break; 1236 } 1237 1238 return; 1239} 1240 1241/* 1242 * Attach the interface. Allocate softc structures, do ifmedia 1243 * setup and ethernet/BPF attach. 1244 */ 1245static int xl_attach(dev) 1246 device_t dev; 1247{ 1248 u_char eaddr[ETHER_ADDR_LEN]; 1249 u_int32_t command; 1250 struct xl_softc *sc; 1251 struct ifnet *ifp; 1252 int media = IFM_ETHER|IFM_100_TX|IFM_FDX; 1253 int unit, error = 0, rid; 1254 1255 sc = device_get_softc(dev); 1256 unit = device_get_unit(dev); 1257 1258 mtx_init(&sc->xl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1259 MTX_DEF | MTX_RECURSE); 1260 XL_LOCK(sc); 1261 1262 sc->xl_flags = 0; 1263 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_556 || 1264 pci_get_device(dev) == TC_DEVICEID_HURRICANE_556B) 1265 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK | 1266 XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_WEIRDRESET | 1267 XL_FLAG_INVERT_LED_PWR | XL_FLAG_INVERT_MII_PWR; 1268 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_556) 1269 sc->xl_flags |= XL_FLAG_8BITROM; 1270 1271 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_575A || 1272 pci_get_device(dev) == TC_DEVICEID_HURRICANE_575B || 1273 pci_get_device(dev) == TC_DEVICEID_HURRICANE_575C || 1274 pci_get_device(dev) == TC_DEVICEID_HURRICANE_656B || 1275 pci_get_device(dev) == TC_DEVICEID_TORNADO_656C) 1276 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK | 1277 XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_8BITROM; 1278 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_656) 1279 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK; 1280 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_575B) 1281 sc->xl_flags |= XL_FLAG_INVERT_LED_PWR; 1282 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_575C) 1283 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR; 1284 if (pci_get_device(dev) == TC_DEVICEID_TORNADO_656C) 1285 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR; 1286 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_656 || 1287 pci_get_device(dev) == TC_DEVICEID_HURRICANE_656B) 1288 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR | 1289 XL_FLAG_INVERT_LED_PWR; 1290 1291 /* 1292 * If this is a 3c905B, we have to check one extra thing. 1293 * The 905B supports power management and may be placed in 1294 * a low-power mode (D3 mode), typically by certain operating 1295 * systems which shall not be named. The PCI BIOS is supposed 1296 * to reset the NIC and bring it out of low-power mode, but 1297 * some do not. Consequently, we have to see if this chip 1298 * supports power management, and if so, make sure it's not 1299 * in low-power mode. If power management is available, the 1300 * capid byte will be 0x01. 1301 * 1302 * I _think_ that what actually happens is that the chip 1303 * loses its PCI configuration during the transition from 1304 * D3 back to D0; this means that it should be possible for 1305 * us to save the PCI iobase, membase and IRQ, put the chip 1306 * back in the D0 state, then restore the PCI config ourselves. 1307 */ 1308 1309 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 1310 u_int32_t iobase, membase, irq; 1311 1312 /* Save important PCI config data. */ 1313 iobase = pci_read_config(dev, XL_PCI_LOIO, 4); 1314 membase = pci_read_config(dev, XL_PCI_LOMEM, 4); 1315 irq = pci_read_config(dev, XL_PCI_INTLINE, 4); 1316 1317 /* Reset the power state. */ 1318 printf("xl%d: chip is in D%d power mode " 1319 "-- setting to D0\n", unit, 1320 pci_get_powerstate(dev)); 1321 1322 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1323 1324 /* Restore PCI config data. */ 1325 pci_write_config(dev, XL_PCI_LOIO, iobase, 4); 1326 pci_write_config(dev, XL_PCI_LOMEM, membase, 4); 1327 pci_write_config(dev, XL_PCI_INTLINE, irq, 4); 1328 } 1329 1330 /* 1331 * Map control/status registers. 1332 */ 1333 pci_enable_busmaster(dev); 1334 pci_enable_io(dev, SYS_RES_IOPORT); 1335 pci_enable_io(dev, SYS_RES_MEMORY); 1336 command = pci_read_config(dev, PCIR_COMMAND, 4); 1337 1338#ifdef XL_USEIOSPACE 1339 if (!(command & PCIM_CMD_PORTEN)) { 1340 printf("xl%d: failed to enable I/O ports!\n", unit); 1341 error = ENXIO; 1342 goto fail; 1343 } 1344#else 1345 if (!(command & PCIM_CMD_MEMEN)) { 1346 printf("xl%d: failed to enable memory mapping!\n", unit); 1347 error = ENXIO; 1348 goto fail; 1349 } 1350#endif 1351 1352 rid = XL_RID; 1353 sc->xl_res = bus_alloc_resource(dev, XL_RES, &rid, 1354 0, ~0, 1, RF_ACTIVE); 1355 1356 if (sc->xl_res == NULL) { 1357 printf ("xl%d: couldn't map ports/memory\n", unit); 1358 error = ENXIO; 1359 goto fail; 1360 } 1361 1362 sc->xl_btag = rman_get_bustag(sc->xl_res); 1363 sc->xl_bhandle = rman_get_bushandle(sc->xl_res); 1364 1365 if (sc->xl_flags & XL_FLAG_FUNCREG) { 1366 rid = XL_PCI_FUNCMEM; 1367 sc->xl_fres = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 1368 0, ~0, 1, RF_ACTIVE); 1369 1370 if (sc->xl_fres == NULL) { 1371 printf ("xl%d: couldn't map ports/memory\n", unit); 1372 bus_release_resource(dev, XL_RES, XL_RID, sc->xl_res); 1373 error = ENXIO; 1374 goto fail; 1375 } 1376 1377 sc->xl_ftag = rman_get_bustag(sc->xl_fres); 1378 sc->xl_fhandle = rman_get_bushandle(sc->xl_fres); 1379 } 1380 1381 rid = 0; 1382 sc->xl_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 1383 RF_SHAREABLE | RF_ACTIVE); 1384 1385 if (sc->xl_irq == NULL) { 1386 printf("xl%d: couldn't map interrupt\n", unit); 1387 if (sc->xl_fres != NULL) 1388 bus_release_resource(dev, SYS_RES_MEMORY, 1389 XL_PCI_FUNCMEM, sc->xl_fres); 1390 bus_release_resource(dev, XL_RES, XL_RID, sc->xl_res); 1391 error = ENXIO; 1392 goto fail; 1393 } 1394 1395 error = bus_setup_intr(dev, sc->xl_irq, INTR_TYPE_NET, 1396 xl_intr, sc, &sc->xl_intrhand); 1397 1398 if (error) { 1399 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->xl_irq); 1400 if (sc->xl_fres != NULL) 1401 bus_release_resource(dev, SYS_RES_MEMORY, 1402 XL_PCI_FUNCMEM, sc->xl_fres); 1403 bus_release_resource(dev, XL_RES, XL_RID, sc->xl_res); 1404 printf("xl%d: couldn't set up irq\n", unit); 1405 goto fail; 1406 } 1407 1408 /* Reset the adapter. */ 1409 xl_reset(sc); 1410 1411 /* 1412 * Get station address from the EEPROM. 1413 */ 1414 if (xl_read_eeprom(sc, (caddr_t)&eaddr, XL_EE_OEM_ADR0, 3, 1)) { 1415 printf("xl%d: failed to read station address\n", sc->xl_unit); 1416 bus_teardown_intr(dev, sc->xl_irq, sc->xl_intrhand); 1417 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->xl_irq); 1418 if (sc->xl_fres != NULL) 1419 bus_release_resource(dev, SYS_RES_MEMORY, 1420 XL_PCI_FUNCMEM, sc->xl_fres); 1421 bus_release_resource(dev, XL_RES, XL_RID, sc->xl_res); 1422 error = ENXIO; 1423 goto fail; 1424 } 1425 1426 /* 1427 * A 3Com chip was detected. Inform the world. 1428 */ 1429 printf("xl%d: Ethernet address: %6D\n", unit, eaddr, ":"); 1430 1431 sc->xl_unit = unit; 1432 callout_handle_init(&sc->xl_stat_ch); 1433 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 1434 1435 sc->xl_ldata = contigmalloc(sizeof(struct xl_list_data), M_DEVBUF, 1436 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1437 1438 if (sc->xl_ldata == NULL) { 1439 printf("xl%d: no memory for list buffers!\n", unit); 1440 bus_teardown_intr(dev, sc->xl_irq, sc->xl_intrhand); 1441 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->xl_irq); 1442 if (sc->xl_fres != NULL) 1443 bus_release_resource(dev, SYS_RES_MEMORY, 1444 XL_PCI_FUNCMEM, sc->xl_fres); 1445 bus_release_resource(dev, XL_RES, XL_RID, sc->xl_res); 1446 error = ENXIO; 1447 goto fail; 1448 } 1449 1450 bzero(sc->xl_ldata, sizeof(struct xl_list_data)); 1451 1452 /* 1453 * Figure out the card type. 3c905B adapters have the 1454 * 'supportsNoTxLength' bit set in the capabilities 1455 * word in the EEPROM. 1456 */ 1457 xl_read_eeprom(sc, (caddr_t)&sc->xl_caps, XL_EE_CAPS, 1, 0); 1458 if (sc->xl_caps & XL_CAPS_NO_TXLENGTH) 1459 sc->xl_type = XL_TYPE_905B; 1460 else 1461 sc->xl_type = XL_TYPE_90X; 1462 1463 ifp = &sc->arpcom.ac_if; 1464 ifp->if_softc = sc; 1465 ifp->if_unit = unit; 1466 ifp->if_name = "xl"; 1467 ifp->if_mtu = ETHERMTU; 1468 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1469 ifp->if_ioctl = xl_ioctl; 1470 ifp->if_output = ether_output; 1471 if (sc->xl_type == XL_TYPE_905B) { 1472 ifp->if_start = xl_start_90xB; 1473 ifp->if_hwassist = XL905B_CSUM_FEATURES; 1474 ifp->if_capabilities = IFCAP_HWCSUM; 1475 } else 1476 ifp->if_start = xl_start; 1477 ifp->if_watchdog = xl_watchdog; 1478 ifp->if_init = xl_init; 1479 ifp->if_baudrate = 10000000; 1480 ifp->if_snd.ifq_maxlen = XL_TX_LIST_CNT - 1; 1481 ifp->if_capenable = ifp->if_capabilities; 1482 1483 /* 1484 * Now we have to see what sort of media we have. 1485 * This includes probing for an MII interace and a 1486 * possible PHY. 1487 */ 1488 XL_SEL_WIN(3); 1489 sc->xl_media = CSR_READ_2(sc, XL_W3_MEDIA_OPT); 1490 if (bootverbose) 1491 printf("xl%d: media options word: %x\n", sc->xl_unit, 1492 sc->xl_media); 1493 1494 xl_read_eeprom(sc, (char *)&sc->xl_xcvr, XL_EE_ICFG_0, 2, 0); 1495 sc->xl_xcvr &= XL_ICFG_CONNECTOR_MASK; 1496 sc->xl_xcvr >>= XL_ICFG_CONNECTOR_BITS; 1497 1498 xl_mediacheck(sc); 1499 1500 if (sc->xl_media & XL_MEDIAOPT_MII || sc->xl_media & XL_MEDIAOPT_BTX 1501 || sc->xl_media & XL_MEDIAOPT_BT4) { 1502 if (bootverbose) 1503 printf("xl%d: found MII/AUTO\n", sc->xl_unit); 1504 xl_setcfg(sc); 1505 if (mii_phy_probe(dev, &sc->xl_miibus, 1506 xl_ifmedia_upd, xl_ifmedia_sts)) { 1507 printf("xl%d: no PHY found!\n", sc->xl_unit); 1508 bus_teardown_intr(dev, sc->xl_irq, sc->xl_intrhand); 1509 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->xl_irq); 1510 bus_release_resource(dev, XL_RES, XL_RID, sc->xl_res); 1511 contigfree(sc->xl_ldata, 1512 sizeof(struct xl_list_data), M_DEVBUF); 1513 error = ENXIO; 1514 goto fail; 1515 } 1516 1517 goto done; 1518 } 1519 1520 /* 1521 * Sanity check. If the user has selected "auto" and this isn't 1522 * a 10/100 card of some kind, we need to force the transceiver 1523 * type to something sane. 1524 */ 1525 if (sc->xl_xcvr == XL_XCVR_AUTO) 1526 xl_choose_xcvr(sc, bootverbose); 1527 1528 /* 1529 * Do ifmedia setup. 1530 */ 1531 1532 ifmedia_init(&sc->ifmedia, 0, xl_ifmedia_upd, xl_ifmedia_sts); 1533 1534 if (sc->xl_media & XL_MEDIAOPT_BT) { 1535 if (bootverbose) 1536 printf("xl%d: found 10baseT\n", sc->xl_unit); 1537 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 1538 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL); 1539 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX) 1540 ifmedia_add(&sc->ifmedia, 1541 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 1542 } 1543 1544 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) { 1545 /* 1546 * Check for a 10baseFL board in disguise. 1547 */ 1548 if (sc->xl_type == XL_TYPE_905B && 1549 sc->xl_media == XL_MEDIAOPT_10FL) { 1550 if (bootverbose) 1551 printf("xl%d: found 10baseFL\n", sc->xl_unit); 1552 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL, 0, NULL); 1553 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL|IFM_HDX, 1554 0, NULL); 1555 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX) 1556 ifmedia_add(&sc->ifmedia, 1557 IFM_ETHER|IFM_10_FL|IFM_FDX, 0, NULL); 1558 } else { 1559 if (bootverbose) 1560 printf("xl%d: found AUI\n", sc->xl_unit); 1561 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_5, 0, NULL); 1562 } 1563 } 1564 1565 if (sc->xl_media & XL_MEDIAOPT_BNC) { 1566 if (bootverbose) 1567 printf("xl%d: found BNC\n", sc->xl_unit); 1568 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_2, 0, NULL); 1569 } 1570 1571 if (sc->xl_media & XL_MEDIAOPT_BFX) { 1572 if (bootverbose) 1573 printf("xl%d: found 100baseFX\n", sc->xl_unit); 1574 ifp->if_baudrate = 100000000; 1575 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_FX, 0, NULL); 1576 } 1577 1578 /* Choose a default media. */ 1579 switch(sc->xl_xcvr) { 1580 case XL_XCVR_10BT: 1581 media = IFM_ETHER|IFM_10_T; 1582 xl_setmode(sc, media); 1583 break; 1584 case XL_XCVR_AUI: 1585 if (sc->xl_type == XL_TYPE_905B && 1586 sc->xl_media == XL_MEDIAOPT_10FL) { 1587 media = IFM_ETHER|IFM_10_FL; 1588 xl_setmode(sc, media); 1589 } else { 1590 media = IFM_ETHER|IFM_10_5; 1591 xl_setmode(sc, media); 1592 } 1593 break; 1594 case XL_XCVR_COAX: 1595 media = IFM_ETHER|IFM_10_2; 1596 xl_setmode(sc, media); 1597 break; 1598 case XL_XCVR_AUTO: 1599 case XL_XCVR_100BTX: 1600 case XL_XCVR_MII: 1601 /* Chosen by miibus */ 1602 break; 1603 case XL_XCVR_100BFX: 1604 media = IFM_ETHER|IFM_100_FX; 1605 break; 1606 default: 1607 printf("xl%d: unknown XCVR type: %d\n", sc->xl_unit, 1608 sc->xl_xcvr); 1609 /* 1610 * This will probably be wrong, but it prevents 1611 * the ifmedia code from panicking. 1612 */ 1613 media = IFM_ETHER|IFM_10_T; 1614 break; 1615 } 1616 1617 if (sc->xl_miibus == NULL) 1618 ifmedia_set(&sc->ifmedia, media); 1619 1620done: 1621 1622 /* 1623 * Call MI attach routine. 1624 */ 1625 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 1626 XL_UNLOCK(sc); 1627 return(0); 1628 1629fail: 1630 XL_UNLOCK(sc); 1631 mtx_destroy(&sc->xl_mtx); 1632 1633 return(error); 1634} 1635 1636static int xl_detach(dev) 1637 device_t dev; 1638{ 1639 struct xl_softc *sc; 1640 struct ifnet *ifp; 1641 1642 sc = device_get_softc(dev); 1643 XL_LOCK(sc); 1644 ifp = &sc->arpcom.ac_if; 1645 1646 xl_reset(sc); 1647 xl_stop(sc); 1648 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 1649 1650 /* Delete any miibus and phy devices attached to this interface */ 1651 if (sc->xl_miibus != NULL) { 1652 bus_generic_detach(dev); 1653 device_delete_child(dev, sc->xl_miibus); 1654 } 1655 1656 bus_teardown_intr(dev, sc->xl_irq, sc->xl_intrhand); 1657 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->xl_irq); 1658 if (sc->xl_fres != NULL) 1659 bus_release_resource(dev, SYS_RES_MEMORY, 1660 XL_PCI_FUNCMEM, sc->xl_fres); 1661 bus_release_resource(dev, XL_RES, XL_RID, sc->xl_res); 1662 1663 ifmedia_removeall(&sc->ifmedia); 1664 contigfree(sc->xl_ldata, sizeof(struct xl_list_data), M_DEVBUF); 1665 1666 XL_UNLOCK(sc); 1667 mtx_destroy(&sc->xl_mtx); 1668 1669 return(0); 1670} 1671 1672/* 1673 * Initialize the transmit descriptors. 1674 */ 1675static int xl_list_tx_init(sc) 1676 struct xl_softc *sc; 1677{ 1678 struct xl_chain_data *cd; 1679 struct xl_list_data *ld; 1680 int i; 1681 1682 cd = &sc->xl_cdata; 1683 ld = sc->xl_ldata; 1684 for (i = 0; i < XL_TX_LIST_CNT; i++) { 1685 cd->xl_tx_chain[i].xl_ptr = &ld->xl_tx_list[i]; 1686 if (i == (XL_TX_LIST_CNT - 1)) 1687 cd->xl_tx_chain[i].xl_next = NULL; 1688 else 1689 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1]; 1690 } 1691 1692 cd->xl_tx_free = &cd->xl_tx_chain[0]; 1693 cd->xl_tx_tail = cd->xl_tx_head = NULL; 1694 1695 return(0); 1696} 1697 1698/* 1699 * Initialize the transmit descriptors. 1700 */ 1701static int xl_list_tx_init_90xB(sc) 1702 struct xl_softc *sc; 1703{ 1704 struct xl_chain_data *cd; 1705 struct xl_list_data *ld; 1706 int i; 1707 1708 cd = &sc->xl_cdata; 1709 ld = sc->xl_ldata; 1710 for (i = 0; i < XL_TX_LIST_CNT; i++) { 1711 cd->xl_tx_chain[i].xl_ptr = &ld->xl_tx_list[i]; 1712 cd->xl_tx_chain[i].xl_phys = vtophys(&ld->xl_tx_list[i]); 1713 if (i == (XL_TX_LIST_CNT - 1)) 1714 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[0]; 1715 else 1716 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1]; 1717 if (i == 0) 1718 cd->xl_tx_chain[i].xl_prev = 1719 &cd->xl_tx_chain[XL_TX_LIST_CNT - 1]; 1720 else 1721 cd->xl_tx_chain[i].xl_prev = 1722 &cd->xl_tx_chain[i - 1]; 1723 } 1724 1725 bzero((char *)ld->xl_tx_list, 1726 sizeof(struct xl_list) * XL_TX_LIST_CNT); 1727 ld->xl_tx_list[0].xl_status = XL_TXSTAT_EMPTY; 1728 1729 cd->xl_tx_prod = 1; 1730 cd->xl_tx_cons = 1; 1731 cd->xl_tx_cnt = 0; 1732 1733 return(0); 1734} 1735 1736/* 1737 * Initialize the RX descriptors and allocate mbufs for them. Note that 1738 * we arrange the descriptors in a closed ring, so that the last descriptor 1739 * points back to the first. 1740 */ 1741static int xl_list_rx_init(sc) 1742 struct xl_softc *sc; 1743{ 1744 struct xl_chain_data *cd; 1745 struct xl_list_data *ld; 1746 int i; 1747 1748 cd = &sc->xl_cdata; 1749 ld = sc->xl_ldata; 1750 1751 for (i = 0; i < XL_RX_LIST_CNT; i++) { 1752 cd->xl_rx_chain[i].xl_ptr = 1753 (struct xl_list_onefrag *)&ld->xl_rx_list[i]; 1754 if (xl_newbuf(sc, &cd->xl_rx_chain[i]) == ENOBUFS) 1755 return(ENOBUFS); 1756 if (i == (XL_RX_LIST_CNT - 1)) { 1757 cd->xl_rx_chain[i].xl_next = &cd->xl_rx_chain[0]; 1758 ld->xl_rx_list[i].xl_next = 1759 vtophys(&ld->xl_rx_list[0]); 1760 } else { 1761 cd->xl_rx_chain[i].xl_next = &cd->xl_rx_chain[i + 1]; 1762 ld->xl_rx_list[i].xl_next = 1763 vtophys(&ld->xl_rx_list[i + 1]); 1764 } 1765 } 1766 1767 cd->xl_rx_head = &cd->xl_rx_chain[0]; 1768 1769 return(0); 1770} 1771 1772/* 1773 * Initialize an RX descriptor and attach an MBUF cluster. 1774 */ 1775static int xl_newbuf(sc, c) 1776 struct xl_softc *sc; 1777 struct xl_chain_onefrag *c; 1778{ 1779 struct mbuf *m_new = NULL; 1780 1781 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1782 if (m_new == NULL) 1783 return(ENOBUFS); 1784 1785 MCLGET(m_new, M_DONTWAIT); 1786 if (!(m_new->m_flags & M_EXT)) { 1787 m_freem(m_new); 1788 return(ENOBUFS); 1789 } 1790 1791 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1792 1793 /* Force longword alignment for packet payload. */ 1794 m_adj(m_new, ETHER_ALIGN); 1795 1796 c->xl_mbuf = m_new; 1797 c->xl_ptr->xl_frag.xl_addr = vtophys(mtod(m_new, caddr_t)); 1798 c->xl_ptr->xl_frag.xl_len = MCLBYTES | XL_LAST_FRAG; 1799 c->xl_ptr->xl_status = 0; 1800 1801 return(0); 1802} 1803 1804static int xl_rx_resync(sc) 1805 struct xl_softc *sc; 1806{ 1807 struct xl_chain_onefrag *pos; 1808 int i; 1809 1810 pos = sc->xl_cdata.xl_rx_head; 1811 1812 for (i = 0; i < XL_RX_LIST_CNT; i++) { 1813 if (pos->xl_ptr->xl_status) 1814 break; 1815 pos = pos->xl_next; 1816 } 1817 1818 if (i == XL_RX_LIST_CNT) 1819 return(0); 1820 1821 sc->xl_cdata.xl_rx_head = pos; 1822 1823 return(EAGAIN); 1824} 1825 1826/* 1827 * A frame has been uploaded: pass the resulting mbuf chain up to 1828 * the higher level protocols. 1829 */ 1830static void xl_rxeof(sc) 1831 struct xl_softc *sc; 1832{ 1833 struct ether_header *eh; 1834 struct mbuf *m; 1835 struct ifnet *ifp; 1836 struct xl_chain_onefrag *cur_rx; 1837 int total_len = 0; 1838 u_int32_t rxstat; 1839 1840 ifp = &sc->arpcom.ac_if; 1841 1842again: 1843 1844 while((rxstat = sc->xl_cdata.xl_rx_head->xl_ptr->xl_status)) { 1845 cur_rx = sc->xl_cdata.xl_rx_head; 1846 sc->xl_cdata.xl_rx_head = cur_rx->xl_next; 1847 1848 /* 1849 * If an error occurs, update stats, clear the 1850 * status word and leave the mbuf cluster in place: 1851 * it should simply get re-used next time this descriptor 1852 * comes up in the ring. 1853 */ 1854 if (rxstat & XL_RXSTAT_UP_ERROR) { 1855 ifp->if_ierrors++; 1856 cur_rx->xl_ptr->xl_status = 0; 1857 continue; 1858 } 1859 1860 /* 1861 * If there error bit was not set, the upload complete 1862 * bit should be set which means we have a valid packet. 1863 * If not, something truly strange has happened. 1864 */ 1865 if (!(rxstat & XL_RXSTAT_UP_CMPLT)) { 1866 printf("xl%d: bad receive status -- " 1867 "packet dropped", sc->xl_unit); 1868 ifp->if_ierrors++; 1869 cur_rx->xl_ptr->xl_status = 0; 1870 continue; 1871 } 1872 1873 /* No errors; receive the packet. */ 1874 m = cur_rx->xl_mbuf; 1875 total_len = cur_rx->xl_ptr->xl_status & XL_RXSTAT_LENMASK; 1876 1877 /* 1878 * Try to conjure up a new mbuf cluster. If that 1879 * fails, it means we have an out of memory condition and 1880 * should leave the buffer in place and continue. This will 1881 * result in a lost packet, but there's little else we 1882 * can do in this situation. 1883 */ 1884 if (xl_newbuf(sc, cur_rx) == ENOBUFS) { 1885 ifp->if_ierrors++; 1886 cur_rx->xl_ptr->xl_status = 0; 1887 continue; 1888 } 1889 1890 ifp->if_ipackets++; 1891 eh = mtod(m, struct ether_header *); 1892 m->m_pkthdr.rcvif = ifp; 1893 m->m_pkthdr.len = m->m_len = total_len; 1894 1895 /* Remove header from mbuf and pass it on. */ 1896 m_adj(m, sizeof(struct ether_header)); 1897 1898 if (sc->xl_type == XL_TYPE_905B) { 1899 /* Do IP checksum checking. */ 1900 if (rxstat & XL_RXSTAT_IPCKOK) 1901 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1902 if (!(rxstat & XL_RXSTAT_IPCKERR)) 1903 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1904 if ((rxstat & XL_RXSTAT_TCPCOK && 1905 !(rxstat & XL_RXSTAT_TCPCKERR)) || 1906 (rxstat & XL_RXSTAT_UDPCKOK && 1907 !(rxstat & XL_RXSTAT_UDPCKERR))) { 1908 m->m_pkthdr.csum_flags |= 1909 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1910 m->m_pkthdr.csum_data = 0xffff; 1911 } 1912 } 1913 ether_input(ifp, eh, m); 1914 } 1915 1916 /* 1917 * Handle the 'end of channel' condition. When the upload 1918 * engine hits the end of the RX ring, it will stall. This 1919 * is our cue to flush the RX ring, reload the uplist pointer 1920 * register and unstall the engine. 1921 * XXX This is actually a little goofy. With the ThunderLAN 1922 * chip, you get an interrupt when the receiver hits the end 1923 * of the receive ring, which tells you exactly when you 1924 * you need to reload the ring pointer. Here we have to 1925 * fake it. I'm mad at myself for not being clever enough 1926 * to avoid the use of a goto here. 1927 */ 1928 if (CSR_READ_4(sc, XL_UPLIST_PTR) == 0 || 1929 CSR_READ_4(sc, XL_UPLIST_STATUS) & XL_PKTSTAT_UP_STALLED) { 1930 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL); 1931 xl_wait(sc); 1932 CSR_WRITE_4(sc, XL_UPLIST_PTR, 1933 vtophys(&sc->xl_ldata->xl_rx_list[0])); 1934 sc->xl_cdata.xl_rx_head = &sc->xl_cdata.xl_rx_chain[0]; 1935 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL); 1936 goto again; 1937 } 1938 1939 return; 1940} 1941 1942/* 1943 * A frame was downloaded to the chip. It's safe for us to clean up 1944 * the list buffers. 1945 */ 1946static void xl_txeof(sc) 1947 struct xl_softc *sc; 1948{ 1949 struct xl_chain *cur_tx; 1950 struct ifnet *ifp; 1951 1952 ifp = &sc->arpcom.ac_if; 1953 1954 /* Clear the timeout timer. */ 1955 ifp->if_timer = 0; 1956 1957 /* 1958 * Go through our tx list and free mbufs for those 1959 * frames that have been uploaded. Note: the 3c905B 1960 * sets a special bit in the status word to let us 1961 * know that a frame has been downloaded, but the 1962 * original 3c900/3c905 adapters don't do that. 1963 * Consequently, we have to use a different test if 1964 * xl_type != XL_TYPE_905B. 1965 */ 1966 while(sc->xl_cdata.xl_tx_head != NULL) { 1967 cur_tx = sc->xl_cdata.xl_tx_head; 1968 1969 if (CSR_READ_4(sc, XL_DOWNLIST_PTR)) 1970 break; 1971 1972 sc->xl_cdata.xl_tx_head = cur_tx->xl_next; 1973 m_freem(cur_tx->xl_mbuf); 1974 cur_tx->xl_mbuf = NULL; 1975 ifp->if_opackets++; 1976 1977 cur_tx->xl_next = sc->xl_cdata.xl_tx_free; 1978 sc->xl_cdata.xl_tx_free = cur_tx; 1979 } 1980 1981 if (sc->xl_cdata.xl_tx_head == NULL) { 1982 ifp->if_flags &= ~IFF_OACTIVE; 1983 sc->xl_cdata.xl_tx_tail = NULL; 1984 } else { 1985 if (CSR_READ_4(sc, XL_DMACTL) & XL_DMACTL_DOWN_STALLED || 1986 !CSR_READ_4(sc, XL_DOWNLIST_PTR)) { 1987 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 1988 vtophys(sc->xl_cdata.xl_tx_head->xl_ptr)); 1989 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 1990 } 1991 } 1992 1993 return; 1994} 1995 1996static void xl_txeof_90xB(sc) 1997 struct xl_softc *sc; 1998{ 1999 struct xl_chain *cur_tx = NULL; 2000 struct ifnet *ifp; 2001 int idx; 2002 2003 ifp = &sc->arpcom.ac_if; 2004 2005 idx = sc->xl_cdata.xl_tx_cons; 2006 while(idx != sc->xl_cdata.xl_tx_prod) { 2007 2008 cur_tx = &sc->xl_cdata.xl_tx_chain[idx]; 2009 2010 if (!(cur_tx->xl_ptr->xl_status & XL_TXSTAT_DL_COMPLETE)) 2011 break; 2012 2013 if (cur_tx->xl_mbuf != NULL) { 2014 m_freem(cur_tx->xl_mbuf); 2015 cur_tx->xl_mbuf = NULL; 2016 } 2017 2018 ifp->if_opackets++; 2019 2020 sc->xl_cdata.xl_tx_cnt--; 2021 XL_INC(idx, XL_TX_LIST_CNT); 2022 ifp->if_timer = 0; 2023 } 2024 2025 sc->xl_cdata.xl_tx_cons = idx; 2026 2027 if (cur_tx != NULL) 2028 ifp->if_flags &= ~IFF_OACTIVE; 2029 2030 return; 2031} 2032 2033/* 2034 * TX 'end of channel' interrupt handler. Actually, we should 2035 * only get a 'TX complete' interrupt if there's a transmit error, 2036 * so this is really TX error handler. 2037 */ 2038static void xl_txeoc(sc) 2039 struct xl_softc *sc; 2040{ 2041 u_int8_t txstat; 2042 2043 while((txstat = CSR_READ_1(sc, XL_TX_STATUS))) { 2044 if (txstat & XL_TXSTATUS_UNDERRUN || 2045 txstat & XL_TXSTATUS_JABBER || 2046 txstat & XL_TXSTATUS_RECLAIM) { 2047 printf("xl%d: transmission error: %x\n", 2048 sc->xl_unit, txstat); 2049 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 2050 xl_wait(sc); 2051 if (sc->xl_type == XL_TYPE_905B) { 2052 if (sc->xl_cdata.xl_tx_cnt) { 2053 int i; 2054 struct xl_chain *c; 2055 i = sc->xl_cdata.xl_tx_cons; 2056 c = &sc->xl_cdata.xl_tx_chain[i]; 2057 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2058 c->xl_phys); 2059 CSR_WRITE_1(sc, XL_DOWN_POLL, 64); 2060 } 2061 } else { 2062 if (sc->xl_cdata.xl_tx_head != NULL) 2063 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2064 vtophys(sc->xl_cdata.xl_tx_head->xl_ptr)); 2065 } 2066 /* 2067 * Remember to set this for the 2068 * first generation 3c90X chips. 2069 */ 2070 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8); 2071 if (txstat & XL_TXSTATUS_UNDERRUN && 2072 sc->xl_tx_thresh < XL_PACKET_SIZE) { 2073 sc->xl_tx_thresh += XL_MIN_FRAMELEN; 2074 printf("xl%d: tx underrun, increasing tx start" 2075 " threshold to %d bytes\n", sc->xl_unit, 2076 sc->xl_tx_thresh); 2077 } 2078 CSR_WRITE_2(sc, XL_COMMAND, 2079 XL_CMD_TX_SET_START|sc->xl_tx_thresh); 2080 if (sc->xl_type == XL_TYPE_905B) { 2081 CSR_WRITE_2(sc, XL_COMMAND, 2082 XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4)); 2083 } 2084 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE); 2085 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2086 } else { 2087 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE); 2088 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2089 } 2090 /* 2091 * Write an arbitrary byte to the TX_STATUS register 2092 * to clear this interrupt/error and advance to the next. 2093 */ 2094 CSR_WRITE_1(sc, XL_TX_STATUS, 0x01); 2095 } 2096 2097 return; 2098} 2099 2100static void xl_intr(arg) 2101 void *arg; 2102{ 2103 struct xl_softc *sc; 2104 struct ifnet *ifp; 2105 u_int16_t status; 2106 2107 sc = arg; 2108 XL_LOCK(sc); 2109 ifp = &sc->arpcom.ac_if; 2110 2111 while((status = CSR_READ_2(sc, XL_STATUS)) & XL_INTRS && status != 0xFFFF) { 2112 2113 CSR_WRITE_2(sc, XL_COMMAND, 2114 XL_CMD_INTR_ACK|(status & XL_INTRS)); 2115 2116 if (status & XL_STAT_UP_COMPLETE) { 2117 int curpkts; 2118 2119 curpkts = ifp->if_ipackets; 2120 xl_rxeof(sc); 2121 if (curpkts == ifp->if_ipackets) { 2122 while (xl_rx_resync(sc)) 2123 xl_rxeof(sc); 2124 } 2125 } 2126 2127 if (status & XL_STAT_DOWN_COMPLETE) { 2128 if (sc->xl_type == XL_TYPE_905B) 2129 xl_txeof_90xB(sc); 2130 else 2131 xl_txeof(sc); 2132 } 2133 2134 if (status & XL_STAT_TX_COMPLETE) { 2135 ifp->if_oerrors++; 2136 xl_txeoc(sc); 2137 } 2138 2139 if (status & XL_STAT_ADFAIL) { 2140 xl_reset(sc); 2141 xl_init(sc); 2142 } 2143 2144 if (status & XL_STAT_STATSOFLOW) { 2145 sc->xl_stats_no_timeout = 1; 2146 xl_stats_update(sc); 2147 sc->xl_stats_no_timeout = 0; 2148 } 2149 } 2150 2151 if (ifp->if_snd.ifq_head != NULL) 2152 (*ifp->if_start)(ifp); 2153 2154 XL_UNLOCK(sc); 2155 2156 return; 2157} 2158 2159static void xl_stats_update(xsc) 2160 void *xsc; 2161{ 2162 struct xl_softc *sc; 2163 struct ifnet *ifp; 2164 struct xl_stats xl_stats; 2165 u_int8_t *p; 2166 int i; 2167 struct mii_data *mii = NULL; 2168 2169 bzero((char *)&xl_stats, sizeof(struct xl_stats)); 2170 2171 sc = xsc; 2172 ifp = &sc->arpcom.ac_if; 2173 if (sc->xl_miibus != NULL) 2174 mii = device_get_softc(sc->xl_miibus); 2175 2176 p = (u_int8_t *)&xl_stats; 2177 2178 /* Read all the stats registers. */ 2179 XL_SEL_WIN(6); 2180 2181 for (i = 0; i < 16; i++) 2182 *p++ = CSR_READ_1(sc, XL_W6_CARRIER_LOST + i); 2183 2184 ifp->if_ierrors += xl_stats.xl_rx_overrun; 2185 2186 ifp->if_collisions += xl_stats.xl_tx_multi_collision + 2187 xl_stats.xl_tx_single_collision + 2188 xl_stats.xl_tx_late_collision; 2189 2190 /* 2191 * Boomerang and cyclone chips have an extra stats counter 2192 * in window 4 (BadSSD). We have to read this too in order 2193 * to clear out all the stats registers and avoid a statsoflow 2194 * interrupt. 2195 */ 2196 XL_SEL_WIN(4); 2197 CSR_READ_1(sc, XL_W4_BADSSD); 2198 2199 if ((mii != NULL) && (!sc->xl_stats_no_timeout)) 2200 mii_tick(mii); 2201 2202 XL_SEL_WIN(7); 2203 2204 if (!sc->xl_stats_no_timeout) 2205 sc->xl_stat_ch = timeout(xl_stats_update, sc, hz); 2206 2207 return; 2208} 2209 2210/* 2211 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 2212 * pointers to the fragment pointers. 2213 */ 2214static int xl_encap(sc, c, m_head) 2215 struct xl_softc *sc; 2216 struct xl_chain *c; 2217 struct mbuf *m_head; 2218{ 2219 int frag = 0; 2220 struct xl_frag *f = NULL; 2221 int total_len; 2222 struct mbuf *m; 2223 2224 /* 2225 * Start packing the mbufs in this chain into 2226 * the fragment pointers. Stop when we run out 2227 * of fragments or hit the end of the mbuf chain. 2228 */ 2229 m = m_head; 2230 total_len = 0; 2231 2232 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 2233 if (m->m_len != 0) { 2234 if (frag == XL_MAXFRAGS) 2235 break; 2236 total_len+= m->m_len; 2237 c->xl_ptr->xl_frag[frag].xl_addr = 2238 vtophys(mtod(m, vm_offset_t)); 2239 c->xl_ptr->xl_frag[frag].xl_len = m->m_len; 2240 frag++; 2241 } 2242 } 2243 2244 /* 2245 * Handle special case: we used up all 63 fragments, 2246 * but we have more mbufs left in the chain. Copy the 2247 * data into an mbuf cluster. Note that we don't 2248 * bother clearing the values in the other fragment 2249 * pointers/counters; it wouldn't gain us anything, 2250 * and would waste cycles. 2251 */ 2252 if (m != NULL) { 2253 struct mbuf *m_new = NULL; 2254 2255 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 2256 if (m_new == NULL) { 2257 printf("xl%d: no memory for tx list", sc->xl_unit); 2258 return(1); 2259 } 2260 if (m_head->m_pkthdr.len > MHLEN) { 2261 MCLGET(m_new, M_DONTWAIT); 2262 if (!(m_new->m_flags & M_EXT)) { 2263 m_freem(m_new); 2264 printf("xl%d: no memory for tx list", 2265 sc->xl_unit); 2266 return(1); 2267 } 2268 } 2269 m_copydata(m_head, 0, m_head->m_pkthdr.len, 2270 mtod(m_new, caddr_t)); 2271 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 2272 m_freem(m_head); 2273 m_head = m_new; 2274 f = &c->xl_ptr->xl_frag[0]; 2275 f->xl_addr = vtophys(mtod(m_new, caddr_t)); 2276 f->xl_len = total_len = m_new->m_len; 2277 frag = 1; 2278 } 2279 2280 c->xl_mbuf = m_head; 2281 c->xl_ptr->xl_frag[frag - 1].xl_len |= XL_LAST_FRAG; 2282 c->xl_ptr->xl_status = total_len; 2283 c->xl_ptr->xl_next = 0; 2284 2285 return(0); 2286} 2287 2288/* 2289 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2290 * to the mbuf data regions directly in the transmit lists. We also save a 2291 * copy of the pointers since the transmit list fragment pointers are 2292 * physical addresses. 2293 */ 2294static void xl_start(ifp) 2295 struct ifnet *ifp; 2296{ 2297 struct xl_softc *sc; 2298 struct mbuf *m_head = NULL; 2299 struct xl_chain *prev = NULL, *cur_tx = NULL, *start_tx; 2300 2301 sc = ifp->if_softc; 2302 XL_LOCK(sc); 2303 /* 2304 * Check for an available queue slot. If there are none, 2305 * punt. 2306 */ 2307 if (sc->xl_cdata.xl_tx_free == NULL) { 2308 xl_txeoc(sc); 2309 xl_txeof(sc); 2310 if (sc->xl_cdata.xl_tx_free == NULL) { 2311 ifp->if_flags |= IFF_OACTIVE; 2312 XL_UNLOCK(sc); 2313 return; 2314 } 2315 } 2316 2317 start_tx = sc->xl_cdata.xl_tx_free; 2318 2319 while(sc->xl_cdata.xl_tx_free != NULL) { 2320 IF_DEQUEUE(&ifp->if_snd, m_head); 2321 if (m_head == NULL) 2322 break; 2323 2324 /* Pick a descriptor off the free list. */ 2325 cur_tx = sc->xl_cdata.xl_tx_free; 2326 sc->xl_cdata.xl_tx_free = cur_tx->xl_next; 2327 2328 cur_tx->xl_next = NULL; 2329 2330 /* Pack the data into the descriptor. */ 2331 xl_encap(sc, cur_tx, m_head); 2332 2333 /* Chain it together. */ 2334 if (prev != NULL) { 2335 prev->xl_next = cur_tx; 2336 prev->xl_ptr->xl_next = vtophys(cur_tx->xl_ptr); 2337 } 2338 prev = cur_tx; 2339 2340 /* 2341 * If there's a BPF listener, bounce a copy of this frame 2342 * to him. 2343 */ 2344 if (ifp->if_bpf) 2345 bpf_mtap(ifp, cur_tx->xl_mbuf); 2346 } 2347 2348 /* 2349 * If there are no packets queued, bail. 2350 */ 2351 if (cur_tx == NULL) { 2352 XL_UNLOCK(sc); 2353 return; 2354 } 2355 2356 /* 2357 * Place the request for the upload interrupt 2358 * in the last descriptor in the chain. This way, if 2359 * we're chaining several packets at once, we'll only 2360 * get an interupt once for the whole chain rather than 2361 * once for each packet. 2362 */ 2363 cur_tx->xl_ptr->xl_status |= XL_TXSTAT_DL_INTR; 2364 2365 /* 2366 * Queue the packets. If the TX channel is clear, update 2367 * the downlist pointer register. 2368 */ 2369 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL); 2370 xl_wait(sc); 2371 2372 if (sc->xl_cdata.xl_tx_head != NULL) { 2373 sc->xl_cdata.xl_tx_tail->xl_next = start_tx; 2374 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_next = 2375 vtophys(start_tx->xl_ptr); 2376 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_status &= 2377 ~XL_TXSTAT_DL_INTR; 2378 sc->xl_cdata.xl_tx_tail = cur_tx; 2379 } else { 2380 sc->xl_cdata.xl_tx_head = start_tx; 2381 sc->xl_cdata.xl_tx_tail = cur_tx; 2382 } 2383 if (!CSR_READ_4(sc, XL_DOWNLIST_PTR)) 2384 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, vtophys(start_tx->xl_ptr)); 2385 2386 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2387 2388 XL_SEL_WIN(7); 2389 2390 /* 2391 * Set a timeout in case the chip goes out to lunch. 2392 */ 2393 ifp->if_timer = 5; 2394 2395 /* 2396 * XXX Under certain conditions, usually on slower machines 2397 * where interrupts may be dropped, it's possible for the 2398 * adapter to chew up all the buffers in the receive ring 2399 * and stall, without us being able to do anything about it. 2400 * To guard against this, we need to make a pass over the 2401 * RX queue to make sure there aren't any packets pending. 2402 * Doing it here means we can flush the receive ring at the 2403 * same time the chip is DMAing the transmit descriptors we 2404 * just gave it. 2405 * 2406 * 3Com goes to some lengths to emphasize the Parallel Tasking (tm) 2407 * nature of their chips in all their marketing literature; 2408 * we may as well take advantage of it. :) 2409 */ 2410 xl_rxeof(sc); 2411 2412 XL_UNLOCK(sc); 2413 2414 return; 2415} 2416 2417static int xl_encap_90xB(sc, c, m_head) 2418 struct xl_softc *sc; 2419 struct xl_chain *c; 2420 struct mbuf *m_head; 2421{ 2422 int frag = 0; 2423 struct xl_frag *f = NULL; 2424 struct mbuf *m; 2425 struct xl_list *d; 2426 2427 /* 2428 * Start packing the mbufs in this chain into 2429 * the fragment pointers. Stop when we run out 2430 * of fragments or hit the end of the mbuf chain. 2431 */ 2432 d = c->xl_ptr; 2433 d->xl_status = 0; 2434 d->xl_next = 0; 2435 2436 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 2437 if (m->m_len != 0) { 2438 if (frag == XL_MAXFRAGS) 2439 break; 2440 f = &d->xl_frag[frag]; 2441 f->xl_addr = vtophys(mtod(m, vm_offset_t)); 2442 f->xl_len = m->m_len; 2443 frag++; 2444 } 2445 } 2446 2447 c->xl_mbuf = m_head; 2448 c->xl_ptr->xl_frag[frag - 1].xl_len |= XL_LAST_FRAG; 2449 c->xl_ptr->xl_status = XL_TXSTAT_RND_DEFEAT; 2450 2451 if (m_head->m_pkthdr.csum_flags) { 2452 if (m_head->m_pkthdr.csum_flags & CSUM_IP) 2453 c->xl_ptr->xl_status |= XL_TXSTAT_IPCKSUM; 2454 if (m_head->m_pkthdr.csum_flags & CSUM_TCP) 2455 c->xl_ptr->xl_status |= XL_TXSTAT_TCPCKSUM; 2456 if (m_head->m_pkthdr.csum_flags & CSUM_UDP) 2457 c->xl_ptr->xl_status |= XL_TXSTAT_UDPCKSUM; 2458 } 2459 return(0); 2460} 2461 2462static void xl_start_90xB(ifp) 2463 struct ifnet *ifp; 2464{ 2465 struct xl_softc *sc; 2466 struct mbuf *m_head = NULL; 2467 struct xl_chain *prev = NULL, *cur_tx = NULL, *start_tx; 2468 int idx; 2469 2470 sc = ifp->if_softc; 2471 XL_LOCK(sc); 2472 2473 if (ifp->if_flags & IFF_OACTIVE) { 2474 XL_UNLOCK(sc); 2475 return; 2476 } 2477 2478 idx = sc->xl_cdata.xl_tx_prod; 2479 start_tx = &sc->xl_cdata.xl_tx_chain[idx]; 2480 2481 while (sc->xl_cdata.xl_tx_chain[idx].xl_mbuf == NULL) { 2482 2483 if ((XL_TX_LIST_CNT - sc->xl_cdata.xl_tx_cnt) < 3) { 2484 ifp->if_flags |= IFF_OACTIVE; 2485 break; 2486 } 2487 2488 IF_DEQUEUE(&ifp->if_snd, m_head); 2489 if (m_head == NULL) 2490 break; 2491 2492 cur_tx = &sc->xl_cdata.xl_tx_chain[idx]; 2493 2494 /* Pack the data into the descriptor. */ 2495 xl_encap_90xB(sc, cur_tx, m_head); 2496 2497 /* Chain it together. */ 2498 if (prev != NULL) 2499 prev->xl_ptr->xl_next = cur_tx->xl_phys; 2500 prev = cur_tx; 2501 2502 /* 2503 * If there's a BPF listener, bounce a copy of this frame 2504 * to him. 2505 */ 2506 if (ifp->if_bpf) 2507 bpf_mtap(ifp, cur_tx->xl_mbuf); 2508 2509 XL_INC(idx, XL_TX_LIST_CNT); 2510 sc->xl_cdata.xl_tx_cnt++; 2511 } 2512 2513 /* 2514 * If there are no packets queued, bail. 2515 */ 2516 if (cur_tx == NULL) { 2517 XL_UNLOCK(sc); 2518 return; 2519 } 2520 2521 /* 2522 * Place the request for the upload interrupt 2523 * in the last descriptor in the chain. This way, if 2524 * we're chaining several packets at once, we'll only 2525 * get an interupt once for the whole chain rather than 2526 * once for each packet. 2527 */ 2528 cur_tx->xl_ptr->xl_status |= XL_TXSTAT_DL_INTR; 2529 2530 /* Start transmission */ 2531 sc->xl_cdata.xl_tx_prod = idx; 2532 start_tx->xl_prev->xl_ptr->xl_next = start_tx->xl_phys; 2533 2534 /* 2535 * Set a timeout in case the chip goes out to lunch. 2536 */ 2537 ifp->if_timer = 5; 2538 2539 XL_UNLOCK(sc); 2540 2541 return; 2542} 2543 2544static void xl_init(xsc) 2545 void *xsc; 2546{ 2547 struct xl_softc *sc = xsc; 2548 struct ifnet *ifp = &sc->arpcom.ac_if; 2549 int i; 2550 u_int16_t rxfilt = 0; 2551 struct mii_data *mii = NULL; 2552 2553 XL_LOCK(sc); 2554 2555 /* 2556 * Cancel pending I/O and free all RX/TX buffers. 2557 */ 2558 xl_stop(sc); 2559 2560 if (sc->xl_miibus == NULL) { 2561 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 2562 xl_wait(sc); 2563 } 2564 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 2565 xl_wait(sc); 2566 DELAY(10000); 2567 2568 if (sc->xl_miibus != NULL) 2569 mii = device_get_softc(sc->xl_miibus); 2570 2571 /* Init our MAC address */ 2572 XL_SEL_WIN(2); 2573 for (i = 0; i < ETHER_ADDR_LEN; i++) { 2574 CSR_WRITE_1(sc, XL_W2_STATION_ADDR_LO + i, 2575 sc->arpcom.ac_enaddr[i]); 2576 } 2577 2578 /* Clear the station mask. */ 2579 for (i = 0; i < 3; i++) 2580 CSR_WRITE_2(sc, XL_W2_STATION_MASK_LO + (i * 2), 0); 2581#ifdef notdef 2582 /* Reset TX and RX. */ 2583 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 2584 xl_wait(sc); 2585 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 2586 xl_wait(sc); 2587#endif 2588 /* Init circular RX list. */ 2589 if (xl_list_rx_init(sc) == ENOBUFS) { 2590 printf("xl%d: initialization failed: no " 2591 "memory for rx buffers\n", sc->xl_unit); 2592 xl_stop(sc); 2593 XL_UNLOCK(sc); 2594 return; 2595 } 2596 2597 /* Init TX descriptors. */ 2598 if (sc->xl_type == XL_TYPE_905B) 2599 xl_list_tx_init_90xB(sc); 2600 else 2601 xl_list_tx_init(sc); 2602 2603 /* 2604 * Set the TX freethresh value. 2605 * Note that this has no effect on 3c905B "cyclone" 2606 * cards but is required for 3c900/3c905 "boomerang" 2607 * cards in order to enable the download engine. 2608 */ 2609 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8); 2610 2611 /* Set the TX start threshold for best performance. */ 2612 sc->xl_tx_thresh = XL_MIN_FRAMELEN; 2613 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_SET_START|sc->xl_tx_thresh); 2614 2615 /* 2616 * If this is a 3c905B, also set the tx reclaim threshold. 2617 * This helps cut down on the number of tx reclaim errors 2618 * that could happen on a busy network. The chip multiplies 2619 * the register value by 16 to obtain the actual threshold 2620 * in bytes, so we divide by 16 when setting the value here. 2621 * The existing threshold value can be examined by reading 2622 * the register at offset 9 in window 5. 2623 */ 2624 if (sc->xl_type == XL_TYPE_905B) { 2625 CSR_WRITE_2(sc, XL_COMMAND, 2626 XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4)); 2627 } 2628 2629 /* Set RX filter bits. */ 2630 XL_SEL_WIN(5); 2631 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); 2632 2633 /* Set the individual bit to receive frames for this host only. */ 2634 rxfilt |= XL_RXFILTER_INDIVIDUAL; 2635 2636 /* If we want promiscuous mode, set the allframes bit. */ 2637 if (ifp->if_flags & IFF_PROMISC) { 2638 rxfilt |= XL_RXFILTER_ALLFRAMES; 2639 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 2640 } else { 2641 rxfilt &= ~XL_RXFILTER_ALLFRAMES; 2642 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 2643 } 2644 2645 /* 2646 * Set capture broadcast bit to capture broadcast frames. 2647 */ 2648 if (ifp->if_flags & IFF_BROADCAST) { 2649 rxfilt |= XL_RXFILTER_BROADCAST; 2650 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 2651 } else { 2652 rxfilt &= ~XL_RXFILTER_BROADCAST; 2653 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 2654 } 2655 2656 /* 2657 * Program the multicast filter, if necessary. 2658 */ 2659 if (sc->xl_type == XL_TYPE_905B) 2660 xl_setmulti_hash(sc); 2661 else 2662 xl_setmulti(sc); 2663 2664 /* 2665 * Load the address of the RX list. We have to 2666 * stall the upload engine before we can manipulate 2667 * the uplist pointer register, then unstall it when 2668 * we're finished. We also have to wait for the 2669 * stall command to complete before proceeding. 2670 * Note that we have to do this after any RX resets 2671 * have completed since the uplist register is cleared 2672 * by a reset. 2673 */ 2674 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL); 2675 xl_wait(sc); 2676 CSR_WRITE_4(sc, XL_UPLIST_PTR, vtophys(&sc->xl_ldata->xl_rx_list[0])); 2677 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL); 2678 xl_wait(sc); 2679 2680 2681 if (sc->xl_type == XL_TYPE_905B) { 2682 /* Set polling interval */ 2683 CSR_WRITE_1(sc, XL_DOWN_POLL, 64); 2684 /* Load the address of the TX list */ 2685 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL); 2686 xl_wait(sc); 2687 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2688 vtophys(&sc->xl_ldata->xl_tx_list[0])); 2689 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2690 xl_wait(sc); 2691 } 2692 2693 /* 2694 * If the coax transceiver is on, make sure to enable 2695 * the DC-DC converter. 2696 */ 2697 XL_SEL_WIN(3); 2698 if (sc->xl_xcvr == XL_XCVR_COAX) 2699 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START); 2700 else 2701 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 2702 2703 /* increase packet size to allow reception of 802.1q or ISL packets */ 2704 if (sc->xl_type == XL_TYPE_905B) 2705 CSR_WRITE_2(sc, XL_W3_MAXPKTSIZE, XL_PACKET_SIZE); 2706 /* Clear out the stats counters. */ 2707 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE); 2708 sc->xl_stats_no_timeout = 1; 2709 xl_stats_update(sc); 2710 sc->xl_stats_no_timeout = 0; 2711 XL_SEL_WIN(4); 2712 CSR_WRITE_2(sc, XL_W4_NET_DIAG, XL_NETDIAG_UPPER_BYTES_ENABLE); 2713 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_ENABLE); 2714 2715 /* 2716 * Enable interrupts. 2717 */ 2718 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|0xFF); 2719 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|XL_INTRS); 2720 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|XL_INTRS); 2721 if (sc->xl_flags & XL_FLAG_FUNCREG) 2722 bus_space_write_4(sc->xl_ftag, sc->xl_fhandle, 4, 0x8000); 2723 2724 /* Set the RX early threshold */ 2725 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_THRESH|(XL_PACKET_SIZE >>2)); 2726 CSR_WRITE_2(sc, XL_DMACTL, XL_DMACTL_UP_RX_EARLY); 2727 2728 /* Enable receiver and transmitter. */ 2729 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE); 2730 xl_wait(sc); 2731 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_ENABLE); 2732 xl_wait(sc); 2733 2734 if (mii != NULL) 2735 mii_mediachg(mii); 2736 2737 /* Select window 7 for normal operations. */ 2738 XL_SEL_WIN(7); 2739 2740 ifp->if_flags |= IFF_RUNNING; 2741 ifp->if_flags &= ~IFF_OACTIVE; 2742 2743 sc->xl_stat_ch = timeout(xl_stats_update, sc, hz); 2744 2745 XL_UNLOCK(sc); 2746 2747 return; 2748} 2749 2750/* 2751 * Set media options. 2752 */ 2753static int xl_ifmedia_upd(ifp) 2754 struct ifnet *ifp; 2755{ 2756 struct xl_softc *sc; 2757 struct ifmedia *ifm = NULL; 2758 struct mii_data *mii = NULL; 2759 2760 sc = ifp->if_softc; 2761 if (sc->xl_miibus != NULL) 2762 mii = device_get_softc(sc->xl_miibus); 2763 if (mii == NULL) 2764 ifm = &sc->ifmedia; 2765 else 2766 ifm = &mii->mii_media; 2767 2768 switch(IFM_SUBTYPE(ifm->ifm_media)) { 2769 case IFM_100_FX: 2770 case IFM_10_FL: 2771 case IFM_10_2: 2772 case IFM_10_5: 2773 xl_setmode(sc, ifm->ifm_media); 2774 return(0); 2775 break; 2776 default: 2777 break; 2778 } 2779 2780 if (sc->xl_media & XL_MEDIAOPT_MII || sc->xl_media & XL_MEDIAOPT_BTX 2781 || sc->xl_media & XL_MEDIAOPT_BT4) { 2782 xl_init(sc); 2783 } else { 2784 xl_setmode(sc, ifm->ifm_media); 2785 } 2786 2787 return(0); 2788} 2789 2790/* 2791 * Report current media status. 2792 */ 2793static void xl_ifmedia_sts(ifp, ifmr) 2794 struct ifnet *ifp; 2795 struct ifmediareq *ifmr; 2796{ 2797 struct xl_softc *sc; 2798 u_int32_t icfg; 2799 struct mii_data *mii = NULL; 2800 2801 sc = ifp->if_softc; 2802 if (sc->xl_miibus != NULL) 2803 mii = device_get_softc(sc->xl_miibus); 2804 2805 XL_SEL_WIN(3); 2806 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG) & XL_ICFG_CONNECTOR_MASK; 2807 icfg >>= XL_ICFG_CONNECTOR_BITS; 2808 2809 ifmr->ifm_active = IFM_ETHER; 2810 2811 switch(icfg) { 2812 case XL_XCVR_10BT: 2813 ifmr->ifm_active = IFM_ETHER|IFM_10_T; 2814 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX) 2815 ifmr->ifm_active |= IFM_FDX; 2816 else 2817 ifmr->ifm_active |= IFM_HDX; 2818 break; 2819 case XL_XCVR_AUI: 2820 if (sc->xl_type == XL_TYPE_905B && 2821 sc->xl_media == XL_MEDIAOPT_10FL) { 2822 ifmr->ifm_active = IFM_ETHER|IFM_10_FL; 2823 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX) 2824 ifmr->ifm_active |= IFM_FDX; 2825 else 2826 ifmr->ifm_active |= IFM_HDX; 2827 } else 2828 ifmr->ifm_active = IFM_ETHER|IFM_10_5; 2829 break; 2830 case XL_XCVR_COAX: 2831 ifmr->ifm_active = IFM_ETHER|IFM_10_2; 2832 break; 2833 /* 2834 * XXX MII and BTX/AUTO should be separate cases. 2835 */ 2836 2837 case XL_XCVR_100BTX: 2838 case XL_XCVR_AUTO: 2839 case XL_XCVR_MII: 2840 if (mii != NULL) { 2841 mii_pollstat(mii); 2842 ifmr->ifm_active = mii->mii_media_active; 2843 ifmr->ifm_status = mii->mii_media_status; 2844 } 2845 break; 2846 case XL_XCVR_100BFX: 2847 ifmr->ifm_active = IFM_ETHER|IFM_100_FX; 2848 break; 2849 default: 2850 printf("xl%d: unknown XCVR type: %d\n", sc->xl_unit, icfg); 2851 break; 2852 } 2853 2854 return; 2855} 2856 2857static int xl_ioctl(ifp, command, data) 2858 struct ifnet *ifp; 2859 u_long command; 2860 caddr_t data; 2861{ 2862 struct xl_softc *sc = ifp->if_softc; 2863 struct ifreq *ifr = (struct ifreq *) data; 2864 int error = 0; 2865 struct mii_data *mii = NULL; 2866 u_int8_t rxfilt; 2867 2868 XL_LOCK(sc); 2869 2870 switch(command) { 2871 case SIOCSIFADDR: 2872 case SIOCGIFADDR: 2873 case SIOCSIFMTU: 2874 error = ether_ioctl(ifp, command, data); 2875 break; 2876 case SIOCSIFFLAGS: 2877 XL_SEL_WIN(5); 2878 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); 2879 if (ifp->if_flags & IFF_UP) { 2880 if (ifp->if_flags & IFF_RUNNING && 2881 ifp->if_flags & IFF_PROMISC && 2882 !(sc->xl_if_flags & IFF_PROMISC)) { 2883 rxfilt |= XL_RXFILTER_ALLFRAMES; 2884 CSR_WRITE_2(sc, XL_COMMAND, 2885 XL_CMD_RX_SET_FILT|rxfilt); 2886 XL_SEL_WIN(7); 2887 } else if (ifp->if_flags & IFF_RUNNING && 2888 !(ifp->if_flags & IFF_PROMISC) && 2889 sc->xl_if_flags & IFF_PROMISC) { 2890 rxfilt &= ~XL_RXFILTER_ALLFRAMES; 2891 CSR_WRITE_2(sc, XL_COMMAND, 2892 XL_CMD_RX_SET_FILT|rxfilt); 2893 XL_SEL_WIN(7); 2894 } else 2895 xl_init(sc); 2896 } else { 2897 if (ifp->if_flags & IFF_RUNNING) 2898 xl_stop(sc); 2899 } 2900 sc->xl_if_flags = ifp->if_flags; 2901 error = 0; 2902 break; 2903 case SIOCADDMULTI: 2904 case SIOCDELMULTI: 2905 if (sc->xl_type == XL_TYPE_905B) 2906 xl_setmulti_hash(sc); 2907 else 2908 xl_setmulti(sc); 2909 error = 0; 2910 break; 2911 case SIOCGIFMEDIA: 2912 case SIOCSIFMEDIA: 2913 if (sc->xl_miibus != NULL) 2914 mii = device_get_softc(sc->xl_miibus); 2915 if (mii == NULL) 2916 error = ifmedia_ioctl(ifp, ifr, 2917 &sc->ifmedia, command); 2918 else 2919 error = ifmedia_ioctl(ifp, ifr, 2920 &mii->mii_media, command); 2921 break; 2922 default: 2923 error = EINVAL; 2924 break; 2925 } 2926 2927 XL_UNLOCK(sc); 2928 2929 return(error); 2930} 2931 2932static void xl_watchdog(ifp) 2933 struct ifnet *ifp; 2934{ 2935 struct xl_softc *sc; 2936 u_int16_t status = 0; 2937 2938 sc = ifp->if_softc; 2939 2940 XL_LOCK(sc); 2941 2942 ifp->if_oerrors++; 2943 XL_SEL_WIN(4); 2944 status = CSR_READ_2(sc, XL_W4_MEDIA_STATUS); 2945 printf("xl%d: watchdog timeout\n", sc->xl_unit); 2946 2947 if (status & XL_MEDIASTAT_CARRIER) 2948 printf("xl%d: no carrier - transceiver cable problem?\n", 2949 sc->xl_unit); 2950 xl_txeoc(sc); 2951 xl_txeof(sc); 2952 xl_rxeof(sc); 2953 xl_reset(sc); 2954 xl_init(sc); 2955 2956 if (ifp->if_snd.ifq_head != NULL) 2957 (*ifp->if_start)(ifp); 2958 2959 XL_UNLOCK(sc); 2960 2961 return; 2962} 2963 2964/* 2965 * Stop the adapter and free any mbufs allocated to the 2966 * RX and TX lists. 2967 */ 2968static void xl_stop(sc) 2969 struct xl_softc *sc; 2970{ 2971 register int i; 2972 struct ifnet *ifp; 2973 2974 XL_LOCK(sc); 2975 2976 ifp = &sc->arpcom.ac_if; 2977 ifp->if_timer = 0; 2978 2979 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISABLE); 2980 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE); 2981 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB); 2982 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISCARD); 2983 xl_wait(sc); 2984 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_DISABLE); 2985 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 2986 DELAY(800); 2987 2988#ifdef foo 2989 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 2990 xl_wait(sc); 2991 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 2992 xl_wait(sc); 2993#endif 2994 2995 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|XL_STAT_INTLATCH); 2996 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|0); 2997 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0); 2998 if (sc->xl_flags & XL_FLAG_FUNCREG) bus_space_write_4 (sc->xl_ftag, sc->xl_fhandle, 4, 0x8000); 2999 3000 /* Stop the stats updater. */ 3001 untimeout(xl_stats_update, sc, sc->xl_stat_ch); 3002 3003 /* 3004 * Free data in the RX lists. 3005 */ 3006 for (i = 0; i < XL_RX_LIST_CNT; i++) { 3007 if (sc->xl_cdata.xl_rx_chain[i].xl_mbuf != NULL) { 3008 m_freem(sc->xl_cdata.xl_rx_chain[i].xl_mbuf); 3009 sc->xl_cdata.xl_rx_chain[i].xl_mbuf = NULL; 3010 } 3011 } 3012 bzero((char *)&sc->xl_ldata->xl_rx_list, 3013 sizeof(sc->xl_ldata->xl_rx_list)); 3014 /* 3015 * Free the TX list buffers. 3016 */ 3017 for (i = 0; i < XL_TX_LIST_CNT; i++) { 3018 if (sc->xl_cdata.xl_tx_chain[i].xl_mbuf != NULL) { 3019 m_freem(sc->xl_cdata.xl_tx_chain[i].xl_mbuf); 3020 sc->xl_cdata.xl_tx_chain[i].xl_mbuf = NULL; 3021 } 3022 } 3023 bzero((char *)&sc->xl_ldata->xl_tx_list, 3024 sizeof(sc->xl_ldata->xl_tx_list)); 3025 3026 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3027 3028 XL_UNLOCK(sc); 3029 3030 return; 3031} 3032 3033/* 3034 * Stop all chip I/O so that the kernel's probe routines don't 3035 * get confused by errant DMAs when rebooting. 3036 */ 3037static void xl_shutdown(dev) 3038 device_t dev; 3039{ 3040 struct xl_softc *sc; 3041 3042 sc = device_get_softc(dev); 3043 3044 XL_LOCK(sc); 3045 xl_reset(sc); 3046 xl_stop(sc); 3047 XL_UNLOCK(sc); 3048 3049 return; 3050} 3051 3052static int xl_suspend(dev) 3053 device_t dev; 3054{ 3055 struct xl_softc *sc; 3056 3057 sc = device_get_softc(dev); 3058 3059 XL_LOCK(sc); 3060 xl_stop(sc); 3061 XL_UNLOCK(sc); 3062 3063 return(0); 3064} 3065 3066static int xl_resume(dev) 3067 device_t dev; 3068{ 3069 struct xl_softc *sc; 3070 struct ifnet *ifp; 3071 3072 sc = device_get_softc(dev); 3073 XL_LOCK(sc); 3074 ifp = &sc->arpcom.ac_if; 3075 3076 xl_reset(sc); 3077 if (ifp->if_flags & IFF_UP) 3078 xl_init(sc); 3079 3080 XL_UNLOCK(sc); 3081 return(0); 3082} 3083