if_xl.c revision 83849
1/* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: head/sys/pci/if_xl.c 83849 2001-09-23 05:13:12Z alc $ 33 */ 34 35/* 36 * 3Com 3c90x Etherlink XL PCI NIC driver 37 * 38 * Supports the 3Com "boomerang", "cyclone" and "hurricane" PCI 39 * bus-master chips (3c90x cards and embedded controllers) including 40 * the following: 41 * 42 * 3Com 3c900-TPO 10Mbps/RJ-45 43 * 3Com 3c900-COMBO 10Mbps/RJ-45,AUI,BNC 44 * 3Com 3c905-TX 10/100Mbps/RJ-45 45 * 3Com 3c905-T4 10/100Mbps/RJ-45 46 * 3Com 3c900B-TPO 10Mbps/RJ-45 47 * 3Com 3c900B-COMBO 10Mbps/RJ-45,AUI,BNC 48 * 3Com 3c900B-TPC 10Mbps/RJ-45,BNC 49 * 3Com 3c900B-FL 10Mbps/Fiber-optic 50 * 3Com 3c905B-COMBO 10/100Mbps/RJ-45,AUI,BNC 51 * 3Com 3c905B-TX 10/100Mbps/RJ-45 52 * 3Com 3c905B-FL/FX 10/100Mbps/Fiber-optic 53 * 3Com 3c905C-TX 10/100Mbps/RJ-45 (Tornado ASIC) 54 * 3Com 3c980-TX 10/100Mbps server adapter (Hurricane ASIC) 55 * 3Com 3c980C-TX 10/100Mbps server adapter (Tornado ASIC) 56 * 3Com 3cSOHO100-TX 10/100Mbps/RJ-45 (Hurricane ASIC) 57 * 3Com 3c450-TX 10/100Mbps/RJ-45 (Tornado ASIC) 58 * 3Com 3c556 10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC) 59 * 3Com 3c556B 10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC) 60 * 3Com 3c575TX 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 61 * 3Com 3c575B 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 62 * 3Com 3c575C 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 63 * 3Com 3cxfem656 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 64 * 3Com 3cxfem656b 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 65 * 3Com 3cxfem656c 10/100Mbps/RJ-45 (Cardbus, Tornado ASIC) 66 * Dell Optiplex GX1 on-board 3c918 10/100Mbps/RJ-45 67 * Dell on-board 3c920 10/100Mbps/RJ-45 68 * Dell Precision on-board 3c905B 10/100Mbps/RJ-45 69 * Dell Latitude laptop docking station embedded 3c905-TX 70 * 71 * Written by Bill Paul <wpaul@ctr.columbia.edu> 72 * Electrical Engineering Department 73 * Columbia University, New York City 74 */ 75 76/* 77 * The 3c90x series chips use a bus-master DMA interface for transfering 78 * packets to and from the controller chip. Some of the "vortex" cards 79 * (3c59x) also supported a bus master mode, however for those chips 80 * you could only DMA packets to/from a contiguous memory buffer. For 81 * transmission this would mean copying the contents of the queued mbuf 82 * chain into a an mbuf cluster and then DMAing the cluster. This extra 83 * copy would sort of defeat the purpose of the bus master support for 84 * any packet that doesn't fit into a single mbuf. 85 * 86 * By contrast, the 3c90x cards support a fragment-based bus master 87 * mode where mbuf chains can be encapsulated using TX descriptors. 88 * This is similar to other PCI chips such as the Texas Instruments 89 * ThunderLAN and the Intel 82557/82558. 90 * 91 * The "vortex" driver (if_vx.c) happens to work for the "boomerang" 92 * bus master chips because they maintain the old PIO interface for 93 * backwards compatibility, but starting with the 3c905B and the 94 * "cyclone" chips, the compatibility interface has been dropped. 95 * Since using bus master DMA is a big win, we use this driver to 96 * support the PCI "boomerang" chips even though they work with the 97 * "vortex" driver in order to obtain better performance. 98 * 99 * This driver is in the /sys/pci directory because it only supports 100 * PCI-based NICs. 101 */ 102 103#include <sys/param.h> 104#include <sys/systm.h> 105#include <sys/sockio.h> 106#include <sys/mbuf.h> 107#include <sys/malloc.h> 108#include <sys/kernel.h> 109#include <sys/socket.h> 110 111#include <net/if.h> 112#include <net/if_arp.h> 113#include <net/ethernet.h> 114#include <net/if_dl.h> 115#include <net/if_media.h> 116 117#include <net/bpf.h> 118 119#include <vm/vm.h> /* for vtophys */ 120#include <vm/pmap.h> /* for vtophys */ 121#include <machine/bus_memio.h> 122#include <machine/bus_pio.h> 123#include <machine/bus.h> 124#include <machine/resource.h> 125#include <sys/bus.h> 126#include <sys/rman.h> 127 128#include <dev/mii/mii.h> 129#include <dev/mii/miivar.h> 130 131#include <pci/pcireg.h> 132#include <pci/pcivar.h> 133 134MODULE_DEPEND(xl, miibus, 1, 1, 1); 135 136/* "controller miibus0" required. See GENERIC if you get errors here. */ 137#include "miibus_if.h" 138 139/* 140 * The following #define causes the code to use PIO to access the 141 * chip's registers instead of memory mapped mode. The reason PIO mode 142 * is on by default is that the Etherlink XL manual seems to indicate 143 * that only the newer revision chips (3c905B) support both PIO and 144 * memory mapped access. Since we want to be compatible with the older 145 * bus master chips, we use PIO here. If you comment this out, the 146 * driver will use memory mapped I/O, which may be faster but which 147 * might not work on some devices. 148 */ 149#define XL_USEIOSPACE 150 151#include <pci/if_xlreg.h> 152 153#if !defined(lint) 154static const char rcsid[] = 155 "$FreeBSD: head/sys/pci/if_xl.c 83849 2001-09-23 05:13:12Z alc $"; 156#endif 157 158/* 159 * Various supported device vendors/types and their names. 160 */ 161static struct xl_type xl_devs[] = { 162 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT, 163 "3Com 3c900-TPO Etherlink XL" }, 164 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT_COMBO, 165 "3Com 3c900-COMBO Etherlink XL" }, 166 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10_100BT, 167 "3Com 3c905-TX Fast Etherlink XL" }, 168 { TC_VENDORID, TC_DEVICEID_BOOMERANG_100BT4, 169 "3Com 3c905-T4 Fast Etherlink XL" }, 170 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT, 171 "3Com 3c900B-TPO Etherlink XL" }, 172 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_COMBO, 173 "3Com 3c900B-COMBO Etherlink XL" }, 174 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_TPC, 175 "3Com 3c900B-TPC Etherlink XL" }, 176 { TC_VENDORID, TC_DEVICEID_CYCLONE_10FL, 177 "3Com 3c900B-FL Etherlink XL" }, 178 { TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT, 179 "3Com 3c905B-TX Fast Etherlink XL" }, 180 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100BT4, 181 "3Com 3c905B-T4 Fast Etherlink XL" }, 182 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100FX, 183 "3Com 3c905B-FX/SC Fast Etherlink XL" }, 184 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100_COMBO, 185 "3Com 3c905B-COMBO Fast Etherlink XL" }, 186 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT, 187 "3Com 3c905C-TX Fast Etherlink XL" }, 188 { TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT_SERV, 189 "3Com 3c980 Fast Etherlink XL" }, 190 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_SERV, 191 "3Com 3c980C Fast Etherlink XL" }, 192 { TC_VENDORID, TC_DEVICEID_HURRICANE_SOHO100TX, 193 "3Com 3cSOHO100-TX OfficeConnect" }, 194 { TC_VENDORID, TC_DEVICEID_TORNADO_HOMECONNECT, 195 "3Com 3c450-TX HomeConnect" }, 196 { TC_VENDORID, TC_DEVICEID_HURRICANE_556, 197 "3Com 3c556 Fast Etherlink XL" }, 198 { TC_VENDORID, TC_DEVICEID_HURRICANE_556B, 199 "3Com 3c556B Fast Etherlink XL" }, 200 { TC_VENDORID, TC_DEVICEID_HURRICANE_575A, 201 "3Com 3c575TX Fast Etherlink XL" }, 202 { TC_VENDORID, TC_DEVICEID_HURRICANE_575B, 203 "3Com 3c575B Fast Etherlink XL" }, 204 { TC_VENDORID, TC_DEVICEID_HURRICANE_575C, 205 "3Com 3c575C Fast Etherlink XL" }, 206 { TC_VENDORID, TC_DEVICEID_HURRICANE_656, 207 "3Com 3c656 Fast Etherlink XL" }, 208 { TC_VENDORID, TC_DEVICEID_HURRICANE_656B, 209 "3Com 3c656B Fast Etherlink XL" }, 210 { TC_VENDORID, TC_DEVICEID_TORNADO_656C, 211 "3Com 3c656C Fast Etherlink XL" }, 212 { 0, 0, NULL } 213}; 214 215static int xl_probe __P((device_t)); 216static int xl_attach __P((device_t)); 217static int xl_detach __P((device_t)); 218 219static int xl_newbuf __P((struct xl_softc *, 220 struct xl_chain_onefrag *)); 221static void xl_stats_update __P((void *)); 222static int xl_encap __P((struct xl_softc *, struct xl_chain *, 223 struct mbuf * )); 224static int xl_encap_90xB __P((struct xl_softc *, struct xl_chain *, 225 struct mbuf * )); 226 227static void xl_rxeof __P((struct xl_softc *)); 228static int xl_rx_resync __P((struct xl_softc *)); 229static void xl_txeof __P((struct xl_softc *)); 230static void xl_txeof_90xB __P((struct xl_softc *)); 231static void xl_txeoc __P((struct xl_softc *)); 232static void xl_intr __P((void *)); 233static void xl_start __P((struct ifnet *)); 234static void xl_start_90xB __P((struct ifnet *)); 235static int xl_ioctl __P((struct ifnet *, u_long, caddr_t)); 236static void xl_init __P((void *)); 237static void xl_stop __P((struct xl_softc *)); 238static void xl_watchdog __P((struct ifnet *)); 239static void xl_shutdown __P((device_t)); 240static int xl_ifmedia_upd __P((struct ifnet *)); 241static void xl_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 242 243static int xl_eeprom_wait __P((struct xl_softc *)); 244static int xl_read_eeprom __P((struct xl_softc *, caddr_t, int, 245 int, int)); 246static void xl_mii_sync __P((struct xl_softc *)); 247static void xl_mii_send __P((struct xl_softc *, u_int32_t, int)); 248static int xl_mii_readreg __P((struct xl_softc *, struct xl_mii_frame *)); 249static int xl_mii_writereg __P((struct xl_softc *, struct xl_mii_frame *)); 250 251static void xl_setcfg __P((struct xl_softc *)); 252static void xl_setmode __P((struct xl_softc *, int)); 253static u_int8_t xl_calchash __P((caddr_t)); 254static void xl_setmulti __P((struct xl_softc *)); 255static void xl_setmulti_hash __P((struct xl_softc *)); 256static void xl_reset __P((struct xl_softc *)); 257static int xl_list_rx_init __P((struct xl_softc *)); 258static int xl_list_tx_init __P((struct xl_softc *)); 259static int xl_list_tx_init_90xB __P((struct xl_softc *)); 260static void xl_wait __P((struct xl_softc *)); 261static void xl_mediacheck __P((struct xl_softc *)); 262static void xl_choose_xcvr __P((struct xl_softc *, int)); 263#ifdef notdef 264static void xl_testpacket __P((struct xl_softc *)); 265#endif 266 267static int xl_miibus_readreg __P((device_t, int, int)); 268static int xl_miibus_writereg __P((device_t, int, int, int)); 269static void xl_miibus_statchg __P((device_t)); 270static void xl_miibus_mediainit __P((device_t)); 271 272#ifdef XL_USEIOSPACE 273#define XL_RES SYS_RES_IOPORT 274#define XL_RID XL_PCI_LOIO 275#else 276#define XL_RES SYS_RES_MEMORY 277#define XL_RID XL_PCI_LOMEM 278#endif 279 280static device_method_t xl_methods[] = { 281 /* Device interface */ 282 DEVMETHOD(device_probe, xl_probe), 283 DEVMETHOD(device_attach, xl_attach), 284 DEVMETHOD(device_detach, xl_detach), 285 DEVMETHOD(device_shutdown, xl_shutdown), 286 287 /* bus interface */ 288 DEVMETHOD(bus_print_child, bus_generic_print_child), 289 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 290 291 /* MII interface */ 292 DEVMETHOD(miibus_readreg, xl_miibus_readreg), 293 DEVMETHOD(miibus_writereg, xl_miibus_writereg), 294 DEVMETHOD(miibus_statchg, xl_miibus_statchg), 295 DEVMETHOD(miibus_mediainit, xl_miibus_mediainit), 296 297 { 0, 0 } 298}; 299 300static driver_t xl_driver = { 301 "xl", 302 xl_methods, 303 sizeof(struct xl_softc) 304}; 305 306static devclass_t xl_devclass; 307 308DRIVER_MODULE(if_xl, cardbus, xl_driver, xl_devclass, 0, 0); 309DRIVER_MODULE(if_xl, pci, xl_driver, xl_devclass, 0, 0); 310DRIVER_MODULE(miibus, xl, miibus_driver, miibus_devclass, 0, 0); 311 312/* 313 * Murphy's law says that it's possible the chip can wedge and 314 * the 'command in progress' bit may never clear. Hence, we wait 315 * only a finite amount of time to avoid getting caught in an 316 * infinite loop. Normally this delay routine would be a macro, 317 * but it isn't called during normal operation so we can afford 318 * to make it a function. 319 */ 320static void xl_wait(sc) 321 struct xl_softc *sc; 322{ 323 register int i; 324 325 for (i = 0; i < XL_TIMEOUT; i++) { 326 if (!(CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY)) 327 break; 328 } 329 330 if (i == XL_TIMEOUT) 331 printf("xl%d: command never completed!\n", sc->xl_unit); 332 333 return; 334} 335 336/* 337 * MII access routines are provided for adapters with external 338 * PHYs (3c905-TX, 3c905-T4, 3c905B-T4) and those with built-in 339 * autoneg logic that's faked up to look like a PHY (3c905B-TX). 340 * Note: if you don't perform the MDIO operations just right, 341 * it's possible to end up with code that works correctly with 342 * some chips/CPUs/processor speeds/bus speeds/etc but not 343 * with others. 344 */ 345#define MII_SET(x) \ 346 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, \ 347 CSR_READ_2(sc, XL_W4_PHY_MGMT) | x) 348 349#define MII_CLR(x) \ 350 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, \ 351 CSR_READ_2(sc, XL_W4_PHY_MGMT) & ~x) 352 353/* 354 * Sync the PHYs by setting data bit and strobing the clock 32 times. 355 */ 356static void xl_mii_sync(sc) 357 struct xl_softc *sc; 358{ 359 register int i; 360 361 XL_SEL_WIN(4); 362 MII_SET(XL_MII_DIR|XL_MII_DATA); 363 364 for (i = 0; i < 32; i++) { 365 MII_SET(XL_MII_CLK); 366 DELAY(1); 367 MII_CLR(XL_MII_CLK); 368 DELAY(1); 369 } 370 371 return; 372} 373 374/* 375 * Clock a series of bits through the MII. 376 */ 377static void xl_mii_send(sc, bits, cnt) 378 struct xl_softc *sc; 379 u_int32_t bits; 380 int cnt; 381{ 382 int i; 383 384 XL_SEL_WIN(4); 385 MII_CLR(XL_MII_CLK); 386 387 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 388 if (bits & i) { 389 MII_SET(XL_MII_DATA); 390 } else { 391 MII_CLR(XL_MII_DATA); 392 } 393 DELAY(1); 394 MII_CLR(XL_MII_CLK); 395 DELAY(1); 396 MII_SET(XL_MII_CLK); 397 } 398} 399 400/* 401 * Read an PHY register through the MII. 402 */ 403static int xl_mii_readreg(sc, frame) 404 struct xl_softc *sc; 405 struct xl_mii_frame *frame; 406 407{ 408 int i, ack; 409 410 XL_LOCK(sc); 411 412 /* 413 * Set up frame for RX. 414 */ 415 frame->mii_stdelim = XL_MII_STARTDELIM; 416 frame->mii_opcode = XL_MII_READOP; 417 frame->mii_turnaround = 0; 418 frame->mii_data = 0; 419 420 /* 421 * Select register window 4. 422 */ 423 424 XL_SEL_WIN(4); 425 426 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, 0); 427 /* 428 * Turn on data xmit. 429 */ 430 MII_SET(XL_MII_DIR); 431 432 xl_mii_sync(sc); 433 434 /* 435 * Send command/address info. 436 */ 437 xl_mii_send(sc, frame->mii_stdelim, 2); 438 xl_mii_send(sc, frame->mii_opcode, 2); 439 xl_mii_send(sc, frame->mii_phyaddr, 5); 440 xl_mii_send(sc, frame->mii_regaddr, 5); 441 442 /* Idle bit */ 443 MII_CLR((XL_MII_CLK|XL_MII_DATA)); 444 DELAY(1); 445 MII_SET(XL_MII_CLK); 446 DELAY(1); 447 448 /* Turn off xmit. */ 449 MII_CLR(XL_MII_DIR); 450 451 /* Check for ack */ 452 MII_CLR(XL_MII_CLK); 453 DELAY(1); 454 MII_SET(XL_MII_CLK); 455 DELAY(1); 456 ack = CSR_READ_2(sc, XL_W4_PHY_MGMT) & XL_MII_DATA; 457 458 /* 459 * Now try reading data bits. If the ack failed, we still 460 * need to clock through 16 cycles to keep the PHY(s) in sync. 461 */ 462 if (ack) { 463 for(i = 0; i < 16; i++) { 464 MII_CLR(XL_MII_CLK); 465 DELAY(1); 466 MII_SET(XL_MII_CLK); 467 DELAY(1); 468 } 469 goto fail; 470 } 471 472 for (i = 0x8000; i; i >>= 1) { 473 MII_CLR(XL_MII_CLK); 474 DELAY(1); 475 if (!ack) { 476 if (CSR_READ_2(sc, XL_W4_PHY_MGMT) & XL_MII_DATA) 477 frame->mii_data |= i; 478 DELAY(1); 479 } 480 MII_SET(XL_MII_CLK); 481 DELAY(1); 482 } 483 484fail: 485 486 MII_CLR(XL_MII_CLK); 487 DELAY(1); 488 MII_SET(XL_MII_CLK); 489 DELAY(1); 490 491 XL_UNLOCK(sc); 492 493 if (ack) 494 return(1); 495 return(0); 496} 497 498/* 499 * Write to a PHY register through the MII. 500 */ 501static int xl_mii_writereg(sc, frame) 502 struct xl_softc *sc; 503 struct xl_mii_frame *frame; 504 505{ 506 XL_LOCK(sc); 507 508 /* 509 * Set up frame for TX. 510 */ 511 512 frame->mii_stdelim = XL_MII_STARTDELIM; 513 frame->mii_opcode = XL_MII_WRITEOP; 514 frame->mii_turnaround = XL_MII_TURNAROUND; 515 516 /* 517 * Select the window 4. 518 */ 519 XL_SEL_WIN(4); 520 521 /* 522 * Turn on data output. 523 */ 524 MII_SET(XL_MII_DIR); 525 526 xl_mii_sync(sc); 527 528 xl_mii_send(sc, frame->mii_stdelim, 2); 529 xl_mii_send(sc, frame->mii_opcode, 2); 530 xl_mii_send(sc, frame->mii_phyaddr, 5); 531 xl_mii_send(sc, frame->mii_regaddr, 5); 532 xl_mii_send(sc, frame->mii_turnaround, 2); 533 xl_mii_send(sc, frame->mii_data, 16); 534 535 /* Idle bit. */ 536 MII_SET(XL_MII_CLK); 537 DELAY(1); 538 MII_CLR(XL_MII_CLK); 539 DELAY(1); 540 541 /* 542 * Turn off xmit. 543 */ 544 MII_CLR(XL_MII_DIR); 545 546 XL_UNLOCK(sc); 547 548 return(0); 549} 550 551static int xl_miibus_readreg(dev, phy, reg) 552 device_t dev; 553 int phy, reg; 554{ 555 struct xl_softc *sc; 556 struct xl_mii_frame frame; 557 558 sc = device_get_softc(dev); 559 560 /* 561 * Pretend that PHYs are only available at MII address 24. 562 * This is to guard against problems with certain 3Com ASIC 563 * revisions that incorrectly map the internal transceiver 564 * control registers at all MII addresses. This can cause 565 * the miibus code to attach the same PHY several times over. 566 */ 567 if ((!(sc->xl_flags & XL_FLAG_PHYOK)) && phy != 24) 568 return(0); 569 570 bzero((char *)&frame, sizeof(frame)); 571 572 frame.mii_phyaddr = phy; 573 frame.mii_regaddr = reg; 574 xl_mii_readreg(sc, &frame); 575 576 return(frame.mii_data); 577} 578 579static int xl_miibus_writereg(dev, phy, reg, data) 580 device_t dev; 581 int phy, reg, data; 582{ 583 struct xl_softc *sc; 584 struct xl_mii_frame frame; 585 586 sc = device_get_softc(dev); 587 588 if ((!(sc->xl_flags & XL_FLAG_PHYOK)) && phy != 24) 589 return(0); 590 591 bzero((char *)&frame, sizeof(frame)); 592 593 frame.mii_phyaddr = phy; 594 frame.mii_regaddr = reg; 595 frame.mii_data = data; 596 597 xl_mii_writereg(sc, &frame); 598 599 return(0); 600} 601 602static void xl_miibus_statchg(dev) 603 device_t dev; 604{ 605 struct xl_softc *sc; 606 struct mii_data *mii; 607 608 609 sc = device_get_softc(dev); 610 mii = device_get_softc(sc->xl_miibus); 611 612 XL_LOCK(sc); 613 614 xl_setcfg(sc); 615 616 /* Set ASIC's duplex mode to match the PHY. */ 617 XL_SEL_WIN(3); 618 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 619 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX); 620 else 621 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, 622 (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX)); 623 624 XL_UNLOCK(sc); 625 626 return; 627} 628 629/* 630 * Special support for the 3c905B-COMBO. This card has 10/100 support 631 * plus BNC and AUI ports. This means we will have both an miibus attached 632 * plus some non-MII media settings. In order to allow this, we have to 633 * add the extra media to the miibus's ifmedia struct, but we can't do 634 * that during xl_attach() because the miibus hasn't been attached yet. 635 * So instead, we wait until the miibus probe/attach is done, at which 636 * point we will get a callback telling is that it's safe to add our 637 * extra media. 638 */ 639static void xl_miibus_mediainit(dev) 640 device_t dev; 641{ 642 struct xl_softc *sc; 643 struct mii_data *mii; 644 struct ifmedia *ifm; 645 646 sc = device_get_softc(dev); 647 mii = device_get_softc(sc->xl_miibus); 648 ifm = &mii->mii_media; 649 650 XL_LOCK(sc); 651 652 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) { 653 /* 654 * Check for a 10baseFL board in disguise. 655 */ 656 if (sc->xl_type == XL_TYPE_905B && 657 sc->xl_media == XL_MEDIAOPT_10FL) { 658 if (bootverbose) 659 printf("xl%d: found 10baseFL\n", sc->xl_unit); 660 ifmedia_add(ifm, IFM_ETHER|IFM_10_FL, 0, NULL); 661 ifmedia_add(ifm, IFM_ETHER|IFM_10_FL|IFM_HDX, 0, NULL); 662 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX) 663 ifmedia_add(ifm, 664 IFM_ETHER|IFM_10_FL|IFM_FDX, 0, NULL); 665 } else { 666 if (bootverbose) 667 printf("xl%d: found AUI\n", sc->xl_unit); 668 ifmedia_add(ifm, IFM_ETHER|IFM_10_5, 0, NULL); 669 } 670 } 671 672 if (sc->xl_media & XL_MEDIAOPT_BNC) { 673 if (bootverbose) 674 printf("xl%d: found BNC\n", sc->xl_unit); 675 ifmedia_add(ifm, IFM_ETHER|IFM_10_2, 0, NULL); 676 } 677 678 XL_UNLOCK(sc); 679 680 return; 681} 682 683/* 684 * The EEPROM is slow: give it time to come ready after issuing 685 * it a command. 686 */ 687static int xl_eeprom_wait(sc) 688 struct xl_softc *sc; 689{ 690 int i; 691 692 for (i = 0; i < 100; i++) { 693 if (CSR_READ_2(sc, XL_W0_EE_CMD) & XL_EE_BUSY) 694 DELAY(162); 695 else 696 break; 697 } 698 699 if (i == 100) { 700 printf("xl%d: eeprom failed to come ready\n", sc->xl_unit); 701 return(1); 702 } 703 704 return(0); 705} 706 707/* 708 * Read a sequence of words from the EEPROM. Note that ethernet address 709 * data is stored in the EEPROM in network byte order. 710 */ 711static int xl_read_eeprom(sc, dest, off, cnt, swap) 712 struct xl_softc *sc; 713 caddr_t dest; 714 int off; 715 int cnt; 716 int swap; 717{ 718 int err = 0, i; 719 u_int16_t word = 0, *ptr; 720#define EEPROM_5BIT_OFFSET(A) ((((A) << 2) & 0x7F00) | ((A) & 0x003F)) 721#define EEPROM_8BIT_OFFSET(A) ((A) & 0x003F) 722 /* WARNING! DANGER! 723 * It's easy to accidentally overwrite the rom content! 724 * Note: the 3c575 uses 8bit EEPROM offsets. 725 */ 726 XL_SEL_WIN(0); 727 728 if (xl_eeprom_wait(sc)) 729 return(1); 730 731 if (sc->xl_flags & XL_FLAG_EEPROM_OFFSET_30) 732 off += 0x30; 733 734 for (i = 0; i < cnt; i++) { 735 if (sc->xl_flags & XL_FLAG_8BITROM) 736 CSR_WRITE_2(sc, XL_W0_EE_CMD, 737 XL_EE_8BIT_READ | EEPROM_8BIT_OFFSET(off + i)); 738 else 739 CSR_WRITE_2(sc, XL_W0_EE_CMD, 740 XL_EE_READ | EEPROM_5BIT_OFFSET(off + i)); 741 err = xl_eeprom_wait(sc); 742 if (err) 743 break; 744 word = CSR_READ_2(sc, XL_W0_EE_DATA); 745 ptr = (u_int16_t *)(dest + (i * 2)); 746 if (swap) 747 *ptr = ntohs(word); 748 else 749 *ptr = word; 750 } 751 752 return(err ? 1 : 0); 753} 754 755/* 756 * This routine is taken from the 3Com Etherlink XL manual, 757 * page 10-7. It calculates a CRC of the supplied multicast 758 * group address and returns the lower 8 bits, which are used 759 * as the multicast filter position. 760 * Note: the 3c905B currently only supports a 64-bit hash table, 761 * which means we really only need 6 bits, but the manual indicates 762 * that future chip revisions will have a 256-bit hash table, 763 * hence the routine is set up to calculate 8 bits of position 764 * info in case we need it some day. 765 * Note II, The Sequel: _CURRENT_ versions of the 3c905B have a 766 * 256 bit hash table. This means we have to use all 8 bits regardless. 767 * On older cards, the upper 2 bits will be ignored. Grrrr.... 768 */ 769static u_int8_t xl_calchash(addr) 770 caddr_t addr; 771{ 772 u_int32_t crc, carry; 773 int i, j; 774 u_int8_t c; 775 776 /* Compute CRC for the address value. */ 777 crc = 0xFFFFFFFF; /* initial value */ 778 779 for (i = 0; i < 6; i++) { 780 c = *(addr + i); 781 for (j = 0; j < 8; j++) { 782 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 783 crc <<= 1; 784 c >>= 1; 785 if (carry) 786 crc = (crc ^ 0x04c11db6) | carry; 787 } 788 } 789 790 /* return the filter bit position */ 791 return(crc & 0x000000FF); 792} 793 794/* 795 * NICs older than the 3c905B have only one multicast option, which 796 * is to enable reception of all multicast frames. 797 */ 798static void xl_setmulti(sc) 799 struct xl_softc *sc; 800{ 801 struct ifnet *ifp; 802 struct ifmultiaddr *ifma; 803 u_int8_t rxfilt; 804 int mcnt = 0; 805 806 ifp = &sc->arpcom.ac_if; 807 808 XL_SEL_WIN(5); 809 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); 810 811 if (ifp->if_flags & IFF_ALLMULTI) { 812 rxfilt |= XL_RXFILTER_ALLMULTI; 813 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 814 return; 815 } 816 817 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) 818 mcnt++; 819 820 if (mcnt) 821 rxfilt |= XL_RXFILTER_ALLMULTI; 822 else 823 rxfilt &= ~XL_RXFILTER_ALLMULTI; 824 825 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 826 827 return; 828} 829 830/* 831 * 3c905B adapters have a hash filter that we can program. 832 */ 833static void xl_setmulti_hash(sc) 834 struct xl_softc *sc; 835{ 836 struct ifnet *ifp; 837 int h = 0, i; 838 struct ifmultiaddr *ifma; 839 u_int8_t rxfilt; 840 int mcnt = 0; 841 842 ifp = &sc->arpcom.ac_if; 843 844 XL_SEL_WIN(5); 845 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); 846 847 if (ifp->if_flags & IFF_ALLMULTI) { 848 rxfilt |= XL_RXFILTER_ALLMULTI; 849 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 850 return; 851 } else 852 rxfilt &= ~XL_RXFILTER_ALLMULTI; 853 854 855 /* first, zot all the existing hash bits */ 856 for (i = 0; i < XL_HASHFILT_SIZE; i++) 857 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_HASH|i); 858 859 /* now program new ones */ 860 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 861 if (ifma->ifma_addr->sa_family != AF_LINK) 862 continue; 863 h = xl_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 864 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_HASH|XL_HASH_SET|h); 865 mcnt++; 866 } 867 868 if (mcnt) 869 rxfilt |= XL_RXFILTER_MULTIHASH; 870 else 871 rxfilt &= ~XL_RXFILTER_MULTIHASH; 872 873 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 874 875 return; 876} 877 878#ifdef notdef 879static void xl_testpacket(sc) 880 struct xl_softc *sc; 881{ 882 struct mbuf *m; 883 struct ifnet *ifp; 884 885 ifp = &sc->arpcom.ac_if; 886 887 MGETHDR(m, M_DONTWAIT, MT_DATA); 888 889 if (m == NULL) 890 return; 891 892 bcopy(&sc->arpcom.ac_enaddr, 893 mtod(m, struct ether_header *)->ether_dhost, ETHER_ADDR_LEN); 894 bcopy(&sc->arpcom.ac_enaddr, 895 mtod(m, struct ether_header *)->ether_shost, ETHER_ADDR_LEN); 896 mtod(m, struct ether_header *)->ether_type = htons(3); 897 mtod(m, unsigned char *)[14] = 0; 898 mtod(m, unsigned char *)[15] = 0; 899 mtod(m, unsigned char *)[16] = 0xE3; 900 m->m_len = m->m_pkthdr.len = sizeof(struct ether_header) + 3; 901 IF_ENQUEUE(&ifp->if_snd, m); 902 xl_start(ifp); 903 904 return; 905} 906#endif 907 908static void xl_setcfg(sc) 909 struct xl_softc *sc; 910{ 911 u_int32_t icfg; 912 913 XL_SEL_WIN(3); 914 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG); 915 icfg &= ~XL_ICFG_CONNECTOR_MASK; 916 if (sc->xl_media & XL_MEDIAOPT_MII || 917 sc->xl_media & XL_MEDIAOPT_BT4) 918 icfg |= (XL_XCVR_MII << XL_ICFG_CONNECTOR_BITS); 919 if (sc->xl_media & XL_MEDIAOPT_BTX) 920 icfg |= (XL_XCVR_AUTO << XL_ICFG_CONNECTOR_BITS); 921 922 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg); 923 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 924 925 return; 926} 927 928static void xl_setmode(sc, media) 929 struct xl_softc *sc; 930 int media; 931{ 932 u_int32_t icfg; 933 u_int16_t mediastat; 934 935 printf("xl%d: selecting ", sc->xl_unit); 936 937 XL_SEL_WIN(4); 938 mediastat = CSR_READ_2(sc, XL_W4_MEDIA_STATUS); 939 XL_SEL_WIN(3); 940 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG); 941 942 if (sc->xl_media & XL_MEDIAOPT_BT) { 943 if (IFM_SUBTYPE(media) == IFM_10_T) { 944 printf("10baseT transceiver, "); 945 sc->xl_xcvr = XL_XCVR_10BT; 946 icfg &= ~XL_ICFG_CONNECTOR_MASK; 947 icfg |= (XL_XCVR_10BT << XL_ICFG_CONNECTOR_BITS); 948 mediastat |= XL_MEDIASTAT_LINKBEAT| 949 XL_MEDIASTAT_JABGUARD; 950 mediastat &= ~XL_MEDIASTAT_SQEENB; 951 } 952 } 953 954 if (sc->xl_media & XL_MEDIAOPT_BFX) { 955 if (IFM_SUBTYPE(media) == IFM_100_FX) { 956 printf("100baseFX port, "); 957 sc->xl_xcvr = XL_XCVR_100BFX; 958 icfg &= ~XL_ICFG_CONNECTOR_MASK; 959 icfg |= (XL_XCVR_100BFX << XL_ICFG_CONNECTOR_BITS); 960 mediastat |= XL_MEDIASTAT_LINKBEAT; 961 mediastat &= ~XL_MEDIASTAT_SQEENB; 962 } 963 } 964 965 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) { 966 if (IFM_SUBTYPE(media) == IFM_10_5) { 967 printf("AUI port, "); 968 sc->xl_xcvr = XL_XCVR_AUI; 969 icfg &= ~XL_ICFG_CONNECTOR_MASK; 970 icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS); 971 mediastat &= ~(XL_MEDIASTAT_LINKBEAT| 972 XL_MEDIASTAT_JABGUARD); 973 mediastat |= ~XL_MEDIASTAT_SQEENB; 974 } 975 if (IFM_SUBTYPE(media) == IFM_10_FL) { 976 printf("10baseFL transceiver, "); 977 sc->xl_xcvr = XL_XCVR_AUI; 978 icfg &= ~XL_ICFG_CONNECTOR_MASK; 979 icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS); 980 mediastat &= ~(XL_MEDIASTAT_LINKBEAT| 981 XL_MEDIASTAT_JABGUARD); 982 mediastat |= ~XL_MEDIASTAT_SQEENB; 983 } 984 } 985 986 if (sc->xl_media & XL_MEDIAOPT_BNC) { 987 if (IFM_SUBTYPE(media) == IFM_10_2) { 988 printf("BNC port, "); 989 sc->xl_xcvr = XL_XCVR_COAX; 990 icfg &= ~XL_ICFG_CONNECTOR_MASK; 991 icfg |= (XL_XCVR_COAX << XL_ICFG_CONNECTOR_BITS); 992 mediastat &= ~(XL_MEDIASTAT_LINKBEAT| 993 XL_MEDIASTAT_JABGUARD| 994 XL_MEDIASTAT_SQEENB); 995 } 996 } 997 998 if ((media & IFM_GMASK) == IFM_FDX || 999 IFM_SUBTYPE(media) == IFM_100_FX) { 1000 printf("full duplex\n"); 1001 XL_SEL_WIN(3); 1002 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX); 1003 } else { 1004 printf("half duplex\n"); 1005 XL_SEL_WIN(3); 1006 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, 1007 (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX)); 1008 } 1009 1010 if (IFM_SUBTYPE(media) == IFM_10_2) 1011 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START); 1012 else 1013 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 1014 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg); 1015 XL_SEL_WIN(4); 1016 CSR_WRITE_2(sc, XL_W4_MEDIA_STATUS, mediastat); 1017 DELAY(800); 1018 XL_SEL_WIN(7); 1019 1020 return; 1021} 1022 1023static void xl_reset(sc) 1024 struct xl_softc *sc; 1025{ 1026 register int i; 1027 1028 XL_SEL_WIN(0); 1029 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RESET | 1030 ((sc->xl_flags & XL_FLAG_WEIRDRESET) ? 1031 XL_RESETOPT_DISADVFD:0)); 1032 1033 for (i = 0; i < XL_TIMEOUT; i++) { 1034 DELAY(10); 1035 if (!(CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY)) 1036 break; 1037 } 1038 1039 if (i == XL_TIMEOUT) 1040 printf("xl%d: reset didn't complete\n", sc->xl_unit); 1041 1042 /* Reset TX and RX. */ 1043 /* Note: the RX reset takes an absurd amount of time 1044 * on newer versions of the Tornado chips such as those 1045 * on the 3c905CX and newer 3c908C cards. We wait an 1046 * extra amount of time so that xl_wait() doesn't complain 1047 * and annoy the users. 1048 */ 1049 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 1050 DELAY(100000); 1051 xl_wait(sc); 1052 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 1053 xl_wait(sc); 1054 1055 if (sc->xl_flags & XL_FLAG_INVERT_LED_PWR || 1056 sc->xl_flags & XL_FLAG_INVERT_MII_PWR) { 1057 XL_SEL_WIN(2); 1058 CSR_WRITE_2(sc, XL_W2_RESET_OPTIONS, CSR_READ_2(sc, 1059 XL_W2_RESET_OPTIONS) 1060 | ((sc->xl_flags & XL_FLAG_INVERT_LED_PWR)?XL_RESETOPT_INVERT_LED:0) 1061 | ((sc->xl_flags & XL_FLAG_INVERT_MII_PWR)?XL_RESETOPT_INVERT_MII:0) 1062 ); 1063 } 1064 1065 /* Wait a little while for the chip to get its brains in order. */ 1066 DELAY(100000); 1067 return; 1068} 1069 1070/* 1071 * Probe for a 3Com Etherlink XL chip. Check the PCI vendor and device 1072 * IDs against our list and return a device name if we find a match. 1073 */ 1074static int xl_probe(dev) 1075 device_t dev; 1076{ 1077 struct xl_type *t; 1078 1079 t = xl_devs; 1080 1081 while(t->xl_name != NULL) { 1082 if ((pci_get_vendor(dev) == t->xl_vid) && 1083 (pci_get_device(dev) == t->xl_did)) { 1084 device_set_desc(dev, t->xl_name); 1085 return(0); 1086 } 1087 t++; 1088 } 1089 1090 return(ENXIO); 1091} 1092 1093/* 1094 * This routine is a kludge to work around possible hardware faults 1095 * or manufacturing defects that can cause the media options register 1096 * (or reset options register, as it's called for the first generation 1097 * 3c90x adapters) to return an incorrect result. I have encountered 1098 * one Dell Latitude laptop docking station with an integrated 3c905-TX 1099 * which doesn't have any of the 'mediaopt' bits set. This screws up 1100 * the attach routine pretty badly because it doesn't know what media 1101 * to look for. If we find ourselves in this predicament, this routine 1102 * will try to guess the media options values and warn the user of a 1103 * possible manufacturing defect with his adapter/system/whatever. 1104 */ 1105static void xl_mediacheck(sc) 1106 struct xl_softc *sc; 1107{ 1108 1109 /* 1110 * If some of the media options bits are set, assume they are 1111 * correct. If not, try to figure it out down below. 1112 * XXX I should check for 10baseFL, but I don't have an adapter 1113 * to test with. 1114 */ 1115 if (sc->xl_media & (XL_MEDIAOPT_MASK & ~XL_MEDIAOPT_VCO)) { 1116 /* 1117 * Check the XCVR value. If it's not in the normal range 1118 * of values, we need to fake it up here. 1119 */ 1120 if (sc->xl_xcvr <= XL_XCVR_AUTO) 1121 return; 1122 else { 1123 printf("xl%d: bogus xcvr value " 1124 "in EEPROM (%x)\n", sc->xl_unit, sc->xl_xcvr); 1125 printf("xl%d: choosing new default based " 1126 "on card type\n", sc->xl_unit); 1127 } 1128 } else { 1129 if (sc->xl_type == XL_TYPE_905B && 1130 sc->xl_media & XL_MEDIAOPT_10FL) 1131 return; 1132 printf("xl%d: WARNING: no media options bits set in " 1133 "the media options register!!\n", sc->xl_unit); 1134 printf("xl%d: this could be a manufacturing defect in " 1135 "your adapter or system\n", sc->xl_unit); 1136 printf("xl%d: attempting to guess media type; you " 1137 "should probably consult your vendor\n", sc->xl_unit); 1138 } 1139 1140 xl_choose_xcvr(sc, 1); 1141 1142 return; 1143} 1144 1145static void xl_choose_xcvr(sc, verbose) 1146 struct xl_softc *sc; 1147 int verbose; 1148{ 1149 u_int16_t devid; 1150 1151 /* 1152 * Read the device ID from the EEPROM. 1153 * This is what's loaded into the PCI device ID register, so it has 1154 * to be correct otherwise we wouldn't have gotten this far. 1155 */ 1156 xl_read_eeprom(sc, (caddr_t)&devid, XL_EE_PRODID, 1, 0); 1157 1158 switch(devid) { 1159 case TC_DEVICEID_BOOMERANG_10BT: /* 3c900-TPO */ 1160 case TC_DEVICEID_KRAKATOA_10BT: /* 3c900B-TPO */ 1161 sc->xl_media = XL_MEDIAOPT_BT; 1162 sc->xl_xcvr = XL_XCVR_10BT; 1163 if (verbose) 1164 printf("xl%d: guessing 10BaseT " 1165 "transceiver\n", sc->xl_unit); 1166 break; 1167 case TC_DEVICEID_BOOMERANG_10BT_COMBO: /* 3c900-COMBO */ 1168 case TC_DEVICEID_KRAKATOA_10BT_COMBO: /* 3c900B-COMBO */ 1169 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI; 1170 sc->xl_xcvr = XL_XCVR_10BT; 1171 if (verbose) 1172 printf("xl%d: guessing COMBO " 1173 "(AUI/BNC/TP)\n", sc->xl_unit); 1174 break; 1175 case TC_DEVICEID_KRAKATOA_10BT_TPC: /* 3c900B-TPC */ 1176 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC; 1177 sc->xl_xcvr = XL_XCVR_10BT; 1178 if (verbose) 1179 printf("xl%d: guessing TPC (BNC/TP)\n", sc->xl_unit); 1180 break; 1181 case TC_DEVICEID_CYCLONE_10FL: /* 3c900B-FL */ 1182 sc->xl_media = XL_MEDIAOPT_10FL; 1183 sc->xl_xcvr = XL_XCVR_AUI; 1184 if (verbose) 1185 printf("xl%d: guessing 10baseFL\n", sc->xl_unit); 1186 break; 1187 case TC_DEVICEID_BOOMERANG_10_100BT: /* 3c905-TX */ 1188 case TC_DEVICEID_HURRICANE_556: /* 3c556 */ 1189 case TC_DEVICEID_HURRICANE_556B: /* 3c556B */ 1190 case TC_DEVICEID_HURRICANE_575A: /* 3c575TX */ 1191 case TC_DEVICEID_HURRICANE_575B: /* 3c575B */ 1192 case TC_DEVICEID_HURRICANE_575C: /* 3c575C */ 1193 case TC_DEVICEID_HURRICANE_656: /* 3c656 */ 1194 case TC_DEVICEID_HURRICANE_656B: /* 3c656B */ 1195 case TC_DEVICEID_TORNADO_656C: /* 3c656C */ 1196 sc->xl_media = XL_MEDIAOPT_MII; 1197 sc->xl_xcvr = XL_XCVR_MII; 1198 if (verbose) 1199 printf("xl%d: guessing MII\n", sc->xl_unit); 1200 break; 1201 case TC_DEVICEID_BOOMERANG_100BT4: /* 3c905-T4 */ 1202 case TC_DEVICEID_CYCLONE_10_100BT4: /* 3c905B-T4 */ 1203 sc->xl_media = XL_MEDIAOPT_BT4; 1204 sc->xl_xcvr = XL_XCVR_MII; 1205 if (verbose) 1206 printf("xl%d: guessing 100BaseT4/MII\n", sc->xl_unit); 1207 break; 1208 case TC_DEVICEID_HURRICANE_10_100BT: /* 3c905B-TX */ 1209 case TC_DEVICEID_HURRICANE_10_100BT_SERV:/*3c980-TX */ 1210 case TC_DEVICEID_TORNADO_10_100BT_SERV: /* 3c980C-TX */ 1211 case TC_DEVICEID_HURRICANE_SOHO100TX: /* 3cSOHO100-TX */ 1212 case TC_DEVICEID_TORNADO_10_100BT: /* 3c905C-TX */ 1213 case TC_DEVICEID_TORNADO_HOMECONNECT: /* 3c450-TX */ 1214 sc->xl_media = XL_MEDIAOPT_BTX; 1215 sc->xl_xcvr = XL_XCVR_AUTO; 1216 if (verbose) 1217 printf("xl%d: guessing 10/100 internal\n", sc->xl_unit); 1218 break; 1219 case TC_DEVICEID_CYCLONE_10_100_COMBO: /* 3c905B-COMBO */ 1220 sc->xl_media = XL_MEDIAOPT_BTX|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI; 1221 sc->xl_xcvr = XL_XCVR_AUTO; 1222 if (verbose) 1223 printf("xl%d: guessing 10/100 " 1224 "plus BNC/AUI\n", sc->xl_unit); 1225 break; 1226 default: 1227 printf("xl%d: unknown device ID: %x -- " 1228 "defaulting to 10baseT\n", sc->xl_unit, devid); 1229 sc->xl_media = XL_MEDIAOPT_BT; 1230 break; 1231 } 1232 1233 return; 1234} 1235 1236/* 1237 * Attach the interface. Allocate softc structures, do ifmedia 1238 * setup and ethernet/BPF attach. 1239 */ 1240static int xl_attach(dev) 1241 device_t dev; 1242{ 1243 u_char eaddr[ETHER_ADDR_LEN]; 1244 u_int32_t command; 1245 struct xl_softc *sc; 1246 struct ifnet *ifp; 1247 int media = IFM_ETHER|IFM_100_TX|IFM_FDX; 1248 int unit, error = 0, rid; 1249 1250 sc = device_get_softc(dev); 1251 unit = device_get_unit(dev); 1252 1253 mtx_init(&sc->xl_mtx, device_get_nameunit(dev), MTX_DEF | MTX_RECURSE); 1254 XL_LOCK(sc); 1255 1256 sc->xl_flags = 0; 1257 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_556 || 1258 pci_get_device(dev) == TC_DEVICEID_HURRICANE_556B) 1259 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK | 1260 XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_WEIRDRESET | 1261 XL_FLAG_INVERT_LED_PWR | XL_FLAG_INVERT_MII_PWR; 1262 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_556) 1263 sc->xl_flags |= XL_FLAG_8BITROM; 1264 1265 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_575A || 1266 pci_get_device(dev) == TC_DEVICEID_HURRICANE_575B || 1267 pci_get_device(dev) == TC_DEVICEID_HURRICANE_575C || 1268 pci_get_device(dev) == TC_DEVICEID_HURRICANE_656B || 1269 pci_get_device(dev) == TC_DEVICEID_TORNADO_656C) 1270 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK | 1271 XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_8BITROM; 1272 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_656) 1273 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK; 1274 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_575B) 1275 sc->xl_flags |= XL_FLAG_INVERT_LED_PWR; 1276 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_575C) 1277 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR; 1278 if (pci_get_device(dev) == TC_DEVICEID_TORNADO_656C) 1279 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR; 1280 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_656 || 1281 pci_get_device(dev) == TC_DEVICEID_HURRICANE_656B) 1282 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR | 1283 XL_FLAG_INVERT_LED_PWR; 1284 1285 /* 1286 * If this is a 3c905B, we have to check one extra thing. 1287 * The 905B supports power management and may be placed in 1288 * a low-power mode (D3 mode), typically by certain operating 1289 * systems which shall not be named. The PCI BIOS is supposed 1290 * to reset the NIC and bring it out of low-power mode, but 1291 * some do not. Consequently, we have to see if this chip 1292 * supports power management, and if so, make sure it's not 1293 * in low-power mode. If power management is available, the 1294 * capid byte will be 0x01. 1295 * 1296 * I _think_ that what actually happens is that the chip 1297 * loses its PCI configuration during the transition from 1298 * D3 back to D0; this means that it should be possible for 1299 * us to save the PCI iobase, membase and IRQ, put the chip 1300 * back in the D0 state, then restore the PCI config ourselves. 1301 */ 1302 1303 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 1304 u_int32_t iobase, membase, irq; 1305 1306 /* Save important PCI config data. */ 1307 iobase = pci_read_config(dev, XL_PCI_LOIO, 4); 1308 membase = pci_read_config(dev, XL_PCI_LOMEM, 4); 1309 irq = pci_read_config(dev, XL_PCI_INTLINE, 4); 1310 1311 /* Reset the power state. */ 1312 printf("xl%d: chip is in D%d power mode " 1313 "-- setting to D0\n", unit, 1314 pci_get_powerstate(dev)); 1315 1316 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1317 1318 /* Restore PCI config data. */ 1319 pci_write_config(dev, XL_PCI_LOIO, iobase, 4); 1320 pci_write_config(dev, XL_PCI_LOMEM, membase, 4); 1321 pci_write_config(dev, XL_PCI_INTLINE, irq, 4); 1322 } 1323 1324 /* 1325 * Map control/status registers. 1326 */ 1327 pci_enable_busmaster(dev); 1328 pci_enable_io(dev, SYS_RES_IOPORT); 1329 pci_enable_io(dev, SYS_RES_MEMORY); 1330 command = pci_read_config(dev, PCIR_COMMAND, 4); 1331 1332#ifdef XL_USEIOSPACE 1333 if (!(command & PCIM_CMD_PORTEN)) { 1334 printf("xl%d: failed to enable I/O ports!\n", unit); 1335 error = ENXIO; 1336 goto fail; 1337 } 1338#else 1339 if (!(command & PCIM_CMD_MEMEN)) { 1340 printf("xl%d: failed to enable memory mapping!\n", unit); 1341 error = ENXIO; 1342 goto fail; 1343 } 1344#endif 1345 1346 rid = XL_RID; 1347 sc->xl_res = bus_alloc_resource(dev, XL_RES, &rid, 1348 0, ~0, 1, RF_ACTIVE); 1349 1350 if (sc->xl_res == NULL) { 1351 printf ("xl%d: couldn't map ports/memory\n", unit); 1352 error = ENXIO; 1353 goto fail; 1354 } 1355 1356 sc->xl_btag = rman_get_bustag(sc->xl_res); 1357 sc->xl_bhandle = rman_get_bushandle(sc->xl_res); 1358 1359 if (sc->xl_flags & XL_FLAG_FUNCREG) { 1360 rid = XL_PCI_FUNCMEM; 1361 sc->xl_fres = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 1362 0, ~0, 1, RF_ACTIVE); 1363 1364 if (sc->xl_fres == NULL) { 1365 printf ("xl%d: couldn't map ports/memory\n", unit); 1366 bus_release_resource(dev, XL_RES, XL_RID, sc->xl_res); 1367 error = ENXIO; 1368 goto fail; 1369 } 1370 1371 sc->xl_ftag = rman_get_bustag(sc->xl_fres); 1372 sc->xl_fhandle = rman_get_bushandle(sc->xl_fres); 1373 } 1374 1375 rid = 0; 1376 sc->xl_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 1377 RF_SHAREABLE | RF_ACTIVE); 1378 1379 if (sc->xl_irq == NULL) { 1380 printf("xl%d: couldn't map interrupt\n", unit); 1381 if (sc->xl_fres != NULL) 1382 bus_release_resource(dev, SYS_RES_MEMORY, 1383 XL_PCI_FUNCMEM, sc->xl_fres); 1384 bus_release_resource(dev, XL_RES, XL_RID, sc->xl_res); 1385 error = ENXIO; 1386 goto fail; 1387 } 1388 1389 error = bus_setup_intr(dev, sc->xl_irq, INTR_TYPE_NET, 1390 xl_intr, sc, &sc->xl_intrhand); 1391 1392 if (error) { 1393 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->xl_irq); 1394 if (sc->xl_fres != NULL) 1395 bus_release_resource(dev, SYS_RES_MEMORY, 1396 XL_PCI_FUNCMEM, sc->xl_fres); 1397 bus_release_resource(dev, XL_RES, XL_RID, sc->xl_res); 1398 printf("xl%d: couldn't set up irq\n", unit); 1399 goto fail; 1400 } 1401 1402 /* Reset the adapter. */ 1403 xl_reset(sc); 1404 1405 /* 1406 * Get station address from the EEPROM. 1407 */ 1408 if (xl_read_eeprom(sc, (caddr_t)&eaddr, XL_EE_OEM_ADR0, 3, 1)) { 1409 printf("xl%d: failed to read station address\n", sc->xl_unit); 1410 bus_teardown_intr(dev, sc->xl_irq, sc->xl_intrhand); 1411 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->xl_irq); 1412 if (sc->xl_fres != NULL) 1413 bus_release_resource(dev, SYS_RES_MEMORY, 1414 XL_PCI_FUNCMEM, sc->xl_fres); 1415 bus_release_resource(dev, XL_RES, XL_RID, sc->xl_res); 1416 error = ENXIO; 1417 goto fail; 1418 } 1419 1420 /* 1421 * A 3Com chip was detected. Inform the world. 1422 */ 1423 printf("xl%d: Ethernet address: %6D\n", unit, eaddr, ":"); 1424 1425 sc->xl_unit = unit; 1426 callout_handle_init(&sc->xl_stat_ch); 1427 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 1428 1429 sc->xl_ldata = contigmalloc(sizeof(struct xl_list_data), M_DEVBUF, 1430 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1431 1432 if (sc->xl_ldata == NULL) { 1433 printf("xl%d: no memory for list buffers!\n", unit); 1434 bus_teardown_intr(dev, sc->xl_irq, sc->xl_intrhand); 1435 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->xl_irq); 1436 if (sc->xl_fres != NULL) 1437 bus_release_resource(dev, SYS_RES_MEMORY, 1438 XL_PCI_FUNCMEM, sc->xl_fres); 1439 bus_release_resource(dev, XL_RES, XL_RID, sc->xl_res); 1440 error = ENXIO; 1441 goto fail; 1442 } 1443 1444 bzero(sc->xl_ldata, sizeof(struct xl_list_data)); 1445 1446 /* 1447 * Figure out the card type. 3c905B adapters have the 1448 * 'supportsNoTxLength' bit set in the capabilities 1449 * word in the EEPROM. 1450 */ 1451 xl_read_eeprom(sc, (caddr_t)&sc->xl_caps, XL_EE_CAPS, 1, 0); 1452 if (sc->xl_caps & XL_CAPS_NO_TXLENGTH) 1453 sc->xl_type = XL_TYPE_905B; 1454 else 1455 sc->xl_type = XL_TYPE_90X; 1456 1457 ifp = &sc->arpcom.ac_if; 1458 ifp->if_softc = sc; 1459 ifp->if_unit = unit; 1460 ifp->if_name = "xl"; 1461 ifp->if_mtu = ETHERMTU; 1462 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1463 ifp->if_ioctl = xl_ioctl; 1464 ifp->if_output = ether_output; 1465 if (sc->xl_type == XL_TYPE_905B) { 1466 ifp->if_start = xl_start_90xB; 1467 ifp->if_capabilities = IFCAP_RXCSUM; 1468 } else 1469 ifp->if_start = xl_start; 1470 ifp->if_watchdog = xl_watchdog; 1471 ifp->if_init = xl_init; 1472 ifp->if_baudrate = 10000000; 1473 ifp->if_snd.ifq_maxlen = XL_TX_LIST_CNT - 1; 1474 ifp->if_capenable = ifp->if_capabilities; 1475 1476 /* 1477 * Now we have to see what sort of media we have. 1478 * This includes probing for an MII interace and a 1479 * possible PHY. 1480 */ 1481 XL_SEL_WIN(3); 1482 sc->xl_media = CSR_READ_2(sc, XL_W3_MEDIA_OPT); 1483 if (bootverbose) 1484 printf("xl%d: media options word: %x\n", sc->xl_unit, 1485 sc->xl_media); 1486 1487 xl_read_eeprom(sc, (char *)&sc->xl_xcvr, XL_EE_ICFG_0, 2, 0); 1488 sc->xl_xcvr &= XL_ICFG_CONNECTOR_MASK; 1489 sc->xl_xcvr >>= XL_ICFG_CONNECTOR_BITS; 1490 1491 xl_mediacheck(sc); 1492 1493 if (sc->xl_media & XL_MEDIAOPT_MII || sc->xl_media & XL_MEDIAOPT_BTX 1494 || sc->xl_media & XL_MEDIAOPT_BT4) { 1495 if (bootverbose) 1496 printf("xl%d: found MII/AUTO\n", sc->xl_unit); 1497 xl_setcfg(sc); 1498 if (mii_phy_probe(dev, &sc->xl_miibus, 1499 xl_ifmedia_upd, xl_ifmedia_sts)) { 1500 printf("xl%d: no PHY found!\n", sc->xl_unit); 1501 bus_teardown_intr(dev, sc->xl_irq, sc->xl_intrhand); 1502 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->xl_irq); 1503 bus_release_resource(dev, XL_RES, XL_RID, sc->xl_res); 1504 contigfree(sc->xl_ldata, 1505 sizeof(struct xl_list_data), M_DEVBUF); 1506 error = ENXIO; 1507 goto fail; 1508 } 1509 1510 goto done; 1511 } 1512 1513 /* 1514 * Sanity check. If the user has selected "auto" and this isn't 1515 * a 10/100 card of some kind, we need to force the transceiver 1516 * type to something sane. 1517 */ 1518 if (sc->xl_xcvr == XL_XCVR_AUTO) 1519 xl_choose_xcvr(sc, bootverbose); 1520 1521 /* 1522 * Do ifmedia setup. 1523 */ 1524 1525 ifmedia_init(&sc->ifmedia, 0, xl_ifmedia_upd, xl_ifmedia_sts); 1526 1527 if (sc->xl_media & XL_MEDIAOPT_BT) { 1528 if (bootverbose) 1529 printf("xl%d: found 10baseT\n", sc->xl_unit); 1530 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 1531 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL); 1532 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX) 1533 ifmedia_add(&sc->ifmedia, 1534 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 1535 } 1536 1537 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) { 1538 /* 1539 * Check for a 10baseFL board in disguise. 1540 */ 1541 if (sc->xl_type == XL_TYPE_905B && 1542 sc->xl_media == XL_MEDIAOPT_10FL) { 1543 if (bootverbose) 1544 printf("xl%d: found 10baseFL\n", sc->xl_unit); 1545 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL, 0, NULL); 1546 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL|IFM_HDX, 1547 0, NULL); 1548 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX) 1549 ifmedia_add(&sc->ifmedia, 1550 IFM_ETHER|IFM_10_FL|IFM_FDX, 0, NULL); 1551 } else { 1552 if (bootverbose) 1553 printf("xl%d: found AUI\n", sc->xl_unit); 1554 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_5, 0, NULL); 1555 } 1556 } 1557 1558 if (sc->xl_media & XL_MEDIAOPT_BNC) { 1559 if (bootverbose) 1560 printf("xl%d: found BNC\n", sc->xl_unit); 1561 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_2, 0, NULL); 1562 } 1563 1564 if (sc->xl_media & XL_MEDIAOPT_BFX) { 1565 if (bootverbose) 1566 printf("xl%d: found 100baseFX\n", sc->xl_unit); 1567 ifp->if_baudrate = 100000000; 1568 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_FX, 0, NULL); 1569 } 1570 1571 /* Choose a default media. */ 1572 switch(sc->xl_xcvr) { 1573 case XL_XCVR_10BT: 1574 media = IFM_ETHER|IFM_10_T; 1575 xl_setmode(sc, media); 1576 break; 1577 case XL_XCVR_AUI: 1578 if (sc->xl_type == XL_TYPE_905B && 1579 sc->xl_media == XL_MEDIAOPT_10FL) { 1580 media = IFM_ETHER|IFM_10_FL; 1581 xl_setmode(sc, media); 1582 } else { 1583 media = IFM_ETHER|IFM_10_5; 1584 xl_setmode(sc, media); 1585 } 1586 break; 1587 case XL_XCVR_COAX: 1588 media = IFM_ETHER|IFM_10_2; 1589 xl_setmode(sc, media); 1590 break; 1591 case XL_XCVR_AUTO: 1592 case XL_XCVR_100BTX: 1593 case XL_XCVR_MII: 1594 /* Chosen by miibus */ 1595 break; 1596 case XL_XCVR_100BFX: 1597 media = IFM_ETHER|IFM_100_FX; 1598 break; 1599 default: 1600 printf("xl%d: unknown XCVR type: %d\n", sc->xl_unit, 1601 sc->xl_xcvr); 1602 /* 1603 * This will probably be wrong, but it prevents 1604 * the ifmedia code from panicking. 1605 */ 1606 media = IFM_ETHER|IFM_10_T; 1607 break; 1608 } 1609 1610 if (sc->xl_miibus == NULL) 1611 ifmedia_set(&sc->ifmedia, media); 1612 1613done: 1614 1615 /* 1616 * Call MI attach routine. 1617 */ 1618 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 1619 XL_UNLOCK(sc); 1620 return(0); 1621 1622fail: 1623 XL_UNLOCK(sc); 1624 mtx_destroy(&sc->xl_mtx); 1625 1626 return(error); 1627} 1628 1629static int xl_detach(dev) 1630 device_t dev; 1631{ 1632 struct xl_softc *sc; 1633 struct ifnet *ifp; 1634 1635 sc = device_get_softc(dev); 1636 XL_LOCK(sc); 1637 ifp = &sc->arpcom.ac_if; 1638 1639 xl_reset(sc); 1640 xl_stop(sc); 1641 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 1642 1643 /* Delete any miibus and phy devices attached to this interface */ 1644 if (sc->xl_miibus != NULL) { 1645 bus_generic_detach(dev); 1646 device_delete_child(dev, sc->xl_miibus); 1647 } 1648 1649 bus_teardown_intr(dev, sc->xl_irq, sc->xl_intrhand); 1650 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->xl_irq); 1651 if (sc->xl_fres != NULL) 1652 bus_release_resource(dev, SYS_RES_MEMORY, 1653 XL_PCI_FUNCMEM, sc->xl_fres); 1654 bus_release_resource(dev, XL_RES, XL_RID, sc->xl_res); 1655 1656 ifmedia_removeall(&sc->ifmedia); 1657 contigfree(sc->xl_ldata, sizeof(struct xl_list_data), M_DEVBUF); 1658 1659 XL_UNLOCK(sc); 1660 mtx_destroy(&sc->xl_mtx); 1661 1662 return(0); 1663} 1664 1665/* 1666 * Initialize the transmit descriptors. 1667 */ 1668static int xl_list_tx_init(sc) 1669 struct xl_softc *sc; 1670{ 1671 struct xl_chain_data *cd; 1672 struct xl_list_data *ld; 1673 int i; 1674 1675 cd = &sc->xl_cdata; 1676 ld = sc->xl_ldata; 1677 for (i = 0; i < XL_TX_LIST_CNT; i++) { 1678 cd->xl_tx_chain[i].xl_ptr = &ld->xl_tx_list[i]; 1679 if (i == (XL_TX_LIST_CNT - 1)) 1680 cd->xl_tx_chain[i].xl_next = NULL; 1681 else 1682 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1]; 1683 } 1684 1685 cd->xl_tx_free = &cd->xl_tx_chain[0]; 1686 cd->xl_tx_tail = cd->xl_tx_head = NULL; 1687 1688 return(0); 1689} 1690 1691/* 1692 * Initialize the transmit descriptors. 1693 */ 1694static int xl_list_tx_init_90xB(sc) 1695 struct xl_softc *sc; 1696{ 1697 struct xl_chain_data *cd; 1698 struct xl_list_data *ld; 1699 int i; 1700 1701 cd = &sc->xl_cdata; 1702 ld = sc->xl_ldata; 1703 for (i = 0; i < XL_TX_LIST_CNT; i++) { 1704 cd->xl_tx_chain[i].xl_ptr = &ld->xl_tx_list[i]; 1705 cd->xl_tx_chain[i].xl_phys = vtophys(&ld->xl_tx_list[i]); 1706 if (i == (XL_TX_LIST_CNT - 1)) 1707 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[0]; 1708 else 1709 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1]; 1710 if (i == 0) 1711 cd->xl_tx_chain[i].xl_prev = 1712 &cd->xl_tx_chain[XL_TX_LIST_CNT - 1]; 1713 else 1714 cd->xl_tx_chain[i].xl_prev = 1715 &cd->xl_tx_chain[i - 1]; 1716 } 1717 1718 bzero((char *)ld->xl_tx_list, 1719 sizeof(struct xl_list) * XL_TX_LIST_CNT); 1720 ld->xl_tx_list[0].xl_status = XL_TXSTAT_EMPTY; 1721 1722 cd->xl_tx_prod = 1; 1723 cd->xl_tx_cons = 1; 1724 cd->xl_tx_cnt = 0; 1725 1726 return(0); 1727} 1728 1729/* 1730 * Initialize the RX descriptors and allocate mbufs for them. Note that 1731 * we arrange the descriptors in a closed ring, so that the last descriptor 1732 * points back to the first. 1733 */ 1734static int xl_list_rx_init(sc) 1735 struct xl_softc *sc; 1736{ 1737 struct xl_chain_data *cd; 1738 struct xl_list_data *ld; 1739 int i; 1740 1741 cd = &sc->xl_cdata; 1742 ld = sc->xl_ldata; 1743 1744 for (i = 0; i < XL_RX_LIST_CNT; i++) { 1745 cd->xl_rx_chain[i].xl_ptr = 1746 (struct xl_list_onefrag *)&ld->xl_rx_list[i]; 1747 if (xl_newbuf(sc, &cd->xl_rx_chain[i]) == ENOBUFS) 1748 return(ENOBUFS); 1749 if (i == (XL_RX_LIST_CNT - 1)) { 1750 cd->xl_rx_chain[i].xl_next = &cd->xl_rx_chain[0]; 1751 ld->xl_rx_list[i].xl_next = 1752 vtophys(&ld->xl_rx_list[0]); 1753 } else { 1754 cd->xl_rx_chain[i].xl_next = &cd->xl_rx_chain[i + 1]; 1755 ld->xl_rx_list[i].xl_next = 1756 vtophys(&ld->xl_rx_list[i + 1]); 1757 } 1758 } 1759 1760 cd->xl_rx_head = &cd->xl_rx_chain[0]; 1761 1762 return(0); 1763} 1764 1765/* 1766 * Initialize an RX descriptor and attach an MBUF cluster. 1767 */ 1768static int xl_newbuf(sc, c) 1769 struct xl_softc *sc; 1770 struct xl_chain_onefrag *c; 1771{ 1772 struct mbuf *m_new = NULL; 1773 1774 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1775 if (m_new == NULL) { 1776 printf("xl%d: no memory for rx list -- " 1777 "packet dropped!\n", sc->xl_unit); 1778 return(ENOBUFS); 1779 } 1780 1781 MCLGET(m_new, M_DONTWAIT); 1782 if (!(m_new->m_flags & M_EXT)) { 1783 printf("xl%d: no memory for rx list -- " 1784 "packet dropped!\n", sc->xl_unit); 1785 m_freem(m_new); 1786 return(ENOBUFS); 1787 } 1788 1789 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1790 1791 /* Force longword alignment for packet payload. */ 1792 m_adj(m_new, ETHER_ALIGN); 1793 1794 c->xl_mbuf = m_new; 1795 c->xl_ptr->xl_frag.xl_addr = vtophys(mtod(m_new, caddr_t)); 1796 c->xl_ptr->xl_frag.xl_len = MCLBYTES | XL_LAST_FRAG; 1797 c->xl_ptr->xl_status = 0; 1798 1799 return(0); 1800} 1801 1802static int xl_rx_resync(sc) 1803 struct xl_softc *sc; 1804{ 1805 struct xl_chain_onefrag *pos; 1806 int i; 1807 1808 pos = sc->xl_cdata.xl_rx_head; 1809 1810 for (i = 0; i < XL_RX_LIST_CNT; i++) { 1811 if (pos->xl_ptr->xl_status) 1812 break; 1813 pos = pos->xl_next; 1814 } 1815 1816 if (i == XL_RX_LIST_CNT) 1817 return(0); 1818 1819 sc->xl_cdata.xl_rx_head = pos; 1820 1821 return(EAGAIN); 1822} 1823 1824/* 1825 * A frame has been uploaded: pass the resulting mbuf chain up to 1826 * the higher level protocols. 1827 */ 1828static void xl_rxeof(sc) 1829 struct xl_softc *sc; 1830{ 1831 struct ether_header *eh; 1832 struct mbuf *m; 1833 struct ifnet *ifp; 1834 struct xl_chain_onefrag *cur_rx; 1835 int total_len = 0; 1836 u_int32_t rxstat; 1837 1838 ifp = &sc->arpcom.ac_if; 1839 1840again: 1841 1842 while((rxstat = sc->xl_cdata.xl_rx_head->xl_ptr->xl_status)) { 1843 cur_rx = sc->xl_cdata.xl_rx_head; 1844 sc->xl_cdata.xl_rx_head = cur_rx->xl_next; 1845 1846 /* 1847 * If an error occurs, update stats, clear the 1848 * status word and leave the mbuf cluster in place: 1849 * it should simply get re-used next time this descriptor 1850 * comes up in the ring. 1851 */ 1852 if (rxstat & XL_RXSTAT_UP_ERROR) { 1853 ifp->if_ierrors++; 1854 cur_rx->xl_ptr->xl_status = 0; 1855 continue; 1856 } 1857 1858 /* 1859 * If there error bit was not set, the upload complete 1860 * bit should be set which means we have a valid packet. 1861 * If not, something truly strange has happened. 1862 */ 1863 if (!(rxstat & XL_RXSTAT_UP_CMPLT)) { 1864 printf("xl%d: bad receive status -- " 1865 "packet dropped", sc->xl_unit); 1866 ifp->if_ierrors++; 1867 cur_rx->xl_ptr->xl_status = 0; 1868 continue; 1869 } 1870 1871 /* No errors; receive the packet. */ 1872 m = cur_rx->xl_mbuf; 1873 total_len = cur_rx->xl_ptr->xl_status & XL_RXSTAT_LENMASK; 1874 1875 /* 1876 * Try to conjure up a new mbuf cluster. If that 1877 * fails, it means we have an out of memory condition and 1878 * should leave the buffer in place and continue. This will 1879 * result in a lost packet, but there's little else we 1880 * can do in this situation. 1881 */ 1882 if (xl_newbuf(sc, cur_rx) == ENOBUFS) { 1883 ifp->if_ierrors++; 1884 cur_rx->xl_ptr->xl_status = 0; 1885 continue; 1886 } 1887 1888 ifp->if_ipackets++; 1889 eh = mtod(m, struct ether_header *); 1890 m->m_pkthdr.rcvif = ifp; 1891 m->m_pkthdr.len = m->m_len = total_len; 1892 1893 /* Remove header from mbuf and pass it on. */ 1894 m_adj(m, sizeof(struct ether_header)); 1895 1896 if (sc->xl_type == XL_TYPE_905B) { 1897 /* Do IP checksum checking. */ 1898 if (rxstat & XL_RXSTAT_IPCKOK) 1899 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1900 if (!(rxstat & XL_RXSTAT_IPCKERR)) 1901 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1902 if ((rxstat & XL_RXSTAT_TCPCOK && 1903 !(rxstat & XL_RXSTAT_TCPCKERR)) || 1904 (rxstat & XL_RXSTAT_UDPCKOK && 1905 !(rxstat & XL_RXSTAT_UDPCKERR))) { 1906 m->m_pkthdr.csum_flags |= 1907 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1908 m->m_pkthdr.csum_data = 0xffff; 1909 } 1910 } 1911 ether_input(ifp, eh, m); 1912 } 1913 1914 /* 1915 * Handle the 'end of channel' condition. When the upload 1916 * engine hits the end of the RX ring, it will stall. This 1917 * is our cue to flush the RX ring, reload the uplist pointer 1918 * register and unstall the engine. 1919 * XXX This is actually a little goofy. With the ThunderLAN 1920 * chip, you get an interrupt when the receiver hits the end 1921 * of the receive ring, which tells you exactly when you 1922 * you need to reload the ring pointer. Here we have to 1923 * fake it. I'm mad at myself for not being clever enough 1924 * to avoid the use of a goto here. 1925 */ 1926 if (CSR_READ_4(sc, XL_UPLIST_PTR) == 0 || 1927 CSR_READ_4(sc, XL_UPLIST_STATUS) & XL_PKTSTAT_UP_STALLED) { 1928 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL); 1929 xl_wait(sc); 1930 CSR_WRITE_4(sc, XL_UPLIST_PTR, 1931 vtophys(&sc->xl_ldata->xl_rx_list[0])); 1932 sc->xl_cdata.xl_rx_head = &sc->xl_cdata.xl_rx_chain[0]; 1933 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL); 1934 goto again; 1935 } 1936 1937 return; 1938} 1939 1940/* 1941 * A frame was downloaded to the chip. It's safe for us to clean up 1942 * the list buffers. 1943 */ 1944static void xl_txeof(sc) 1945 struct xl_softc *sc; 1946{ 1947 struct xl_chain *cur_tx; 1948 struct ifnet *ifp; 1949 1950 ifp = &sc->arpcom.ac_if; 1951 1952 /* Clear the timeout timer. */ 1953 ifp->if_timer = 0; 1954 1955 /* 1956 * Go through our tx list and free mbufs for those 1957 * frames that have been uploaded. Note: the 3c905B 1958 * sets a special bit in the status word to let us 1959 * know that a frame has been downloaded, but the 1960 * original 3c900/3c905 adapters don't do that. 1961 * Consequently, we have to use a different test if 1962 * xl_type != XL_TYPE_905B. 1963 */ 1964 while(sc->xl_cdata.xl_tx_head != NULL) { 1965 cur_tx = sc->xl_cdata.xl_tx_head; 1966 1967 if (CSR_READ_4(sc, XL_DOWNLIST_PTR)) 1968 break; 1969 1970 sc->xl_cdata.xl_tx_head = cur_tx->xl_next; 1971 m_freem(cur_tx->xl_mbuf); 1972 cur_tx->xl_mbuf = NULL; 1973 ifp->if_opackets++; 1974 1975 cur_tx->xl_next = sc->xl_cdata.xl_tx_free; 1976 sc->xl_cdata.xl_tx_free = cur_tx; 1977 } 1978 1979 if (sc->xl_cdata.xl_tx_head == NULL) { 1980 ifp->if_flags &= ~IFF_OACTIVE; 1981 sc->xl_cdata.xl_tx_tail = NULL; 1982 } else { 1983 if (CSR_READ_4(sc, XL_DMACTL) & XL_DMACTL_DOWN_STALLED || 1984 !CSR_READ_4(sc, XL_DOWNLIST_PTR)) { 1985 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 1986 vtophys(sc->xl_cdata.xl_tx_head->xl_ptr)); 1987 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 1988 } 1989 } 1990 1991 return; 1992} 1993 1994static void xl_txeof_90xB(sc) 1995 struct xl_softc *sc; 1996{ 1997 struct xl_chain *cur_tx = NULL; 1998 struct ifnet *ifp; 1999 int idx; 2000 2001 ifp = &sc->arpcom.ac_if; 2002 2003 idx = sc->xl_cdata.xl_tx_cons; 2004 while(idx != sc->xl_cdata.xl_tx_prod) { 2005 2006 cur_tx = &sc->xl_cdata.xl_tx_chain[idx]; 2007 2008 if (!(cur_tx->xl_ptr->xl_status & XL_TXSTAT_DL_COMPLETE)) 2009 break; 2010 2011 if (cur_tx->xl_mbuf != NULL) { 2012 m_freem(cur_tx->xl_mbuf); 2013 cur_tx->xl_mbuf = NULL; 2014 } 2015 2016 ifp->if_opackets++; 2017 2018 sc->xl_cdata.xl_tx_cnt--; 2019 XL_INC(idx, XL_TX_LIST_CNT); 2020 ifp->if_timer = 0; 2021 } 2022 2023 sc->xl_cdata.xl_tx_cons = idx; 2024 2025 if (cur_tx != NULL) 2026 ifp->if_flags &= ~IFF_OACTIVE; 2027 2028 return; 2029} 2030 2031/* 2032 * TX 'end of channel' interrupt handler. Actually, we should 2033 * only get a 'TX complete' interrupt if there's a transmit error, 2034 * so this is really TX error handler. 2035 */ 2036static void xl_txeoc(sc) 2037 struct xl_softc *sc; 2038{ 2039 u_int8_t txstat; 2040 2041 while((txstat = CSR_READ_1(sc, XL_TX_STATUS))) { 2042 if (txstat & XL_TXSTATUS_UNDERRUN || 2043 txstat & XL_TXSTATUS_JABBER || 2044 txstat & XL_TXSTATUS_RECLAIM) { 2045 printf("xl%d: transmission error: %x\n", 2046 sc->xl_unit, txstat); 2047 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 2048 xl_wait(sc); 2049 if (sc->xl_type == XL_TYPE_905B) { 2050 if (sc->xl_cdata.xl_tx_cnt) { 2051 int i; 2052 struct xl_chain *c; 2053 i = sc->xl_cdata.xl_tx_cons; 2054 c = &sc->xl_cdata.xl_tx_chain[i]; 2055 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2056 c->xl_phys); 2057 CSR_WRITE_1(sc, XL_DOWN_POLL, 64); 2058 } 2059 } else { 2060 if (sc->xl_cdata.xl_tx_head != NULL) 2061 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2062 vtophys(sc->xl_cdata.xl_tx_head->xl_ptr)); 2063 } 2064 /* 2065 * Remember to set this for the 2066 * first generation 3c90X chips. 2067 */ 2068 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8); 2069 if (txstat & XL_TXSTATUS_UNDERRUN && 2070 sc->xl_tx_thresh < XL_PACKET_SIZE) { 2071 sc->xl_tx_thresh += XL_MIN_FRAMELEN; 2072 printf("xl%d: tx underrun, increasing tx start" 2073 " threshold to %d bytes\n", sc->xl_unit, 2074 sc->xl_tx_thresh); 2075 } 2076 CSR_WRITE_2(sc, XL_COMMAND, 2077 XL_CMD_TX_SET_START|sc->xl_tx_thresh); 2078 if (sc->xl_type == XL_TYPE_905B) { 2079 CSR_WRITE_2(sc, XL_COMMAND, 2080 XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4)); 2081 } 2082 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE); 2083 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2084 } else { 2085 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE); 2086 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2087 } 2088 /* 2089 * Write an arbitrary byte to the TX_STATUS register 2090 * to clear this interrupt/error and advance to the next. 2091 */ 2092 CSR_WRITE_1(sc, XL_TX_STATUS, 0x01); 2093 } 2094 2095 return; 2096} 2097 2098static void xl_intr(arg) 2099 void *arg; 2100{ 2101 struct xl_softc *sc; 2102 struct ifnet *ifp; 2103 u_int16_t status; 2104 2105 sc = arg; 2106 XL_LOCK(sc); 2107 ifp = &sc->arpcom.ac_if; 2108 2109 while((status = CSR_READ_2(sc, XL_STATUS)) & XL_INTRS && status != 0xFFFF) { 2110 2111 CSR_WRITE_2(sc, XL_COMMAND, 2112 XL_CMD_INTR_ACK|(status & XL_INTRS)); 2113 2114 if (status & XL_STAT_UP_COMPLETE) { 2115 int curpkts; 2116 2117 curpkts = ifp->if_ipackets; 2118 xl_rxeof(sc); 2119 if (curpkts == ifp->if_ipackets) { 2120 while (xl_rx_resync(sc)) 2121 xl_rxeof(sc); 2122 } 2123 } 2124 2125 if (status & XL_STAT_DOWN_COMPLETE) { 2126 if (sc->xl_type == XL_TYPE_905B) 2127 xl_txeof_90xB(sc); 2128 else 2129 xl_txeof(sc); 2130 } 2131 2132 if (status & XL_STAT_TX_COMPLETE) { 2133 ifp->if_oerrors++; 2134 xl_txeoc(sc); 2135 } 2136 2137 if (status & XL_STAT_ADFAIL) { 2138 xl_reset(sc); 2139 xl_init(sc); 2140 } 2141 2142 if (status & XL_STAT_STATSOFLOW) { 2143 sc->xl_stats_no_timeout = 1; 2144 xl_stats_update(sc); 2145 sc->xl_stats_no_timeout = 0; 2146 } 2147 } 2148 2149 if (ifp->if_snd.ifq_head != NULL) 2150 (*ifp->if_start)(ifp); 2151 2152 XL_UNLOCK(sc); 2153 2154 return; 2155} 2156 2157static void xl_stats_update(xsc) 2158 void *xsc; 2159{ 2160 struct xl_softc *sc; 2161 struct ifnet *ifp; 2162 struct xl_stats xl_stats; 2163 u_int8_t *p; 2164 int i; 2165 struct mii_data *mii = NULL; 2166 2167 bzero((char *)&xl_stats, sizeof(struct xl_stats)); 2168 2169 sc = xsc; 2170 ifp = &sc->arpcom.ac_if; 2171 if (sc->xl_miibus != NULL) 2172 mii = device_get_softc(sc->xl_miibus); 2173 2174 p = (u_int8_t *)&xl_stats; 2175 2176 /* Read all the stats registers. */ 2177 XL_SEL_WIN(6); 2178 2179 for (i = 0; i < 16; i++) 2180 *p++ = CSR_READ_1(sc, XL_W6_CARRIER_LOST + i); 2181 2182 ifp->if_ierrors += xl_stats.xl_rx_overrun; 2183 2184 ifp->if_collisions += xl_stats.xl_tx_multi_collision + 2185 xl_stats.xl_tx_single_collision + 2186 xl_stats.xl_tx_late_collision; 2187 2188 /* 2189 * Boomerang and cyclone chips have an extra stats counter 2190 * in window 4 (BadSSD). We have to read this too in order 2191 * to clear out all the stats registers and avoid a statsoflow 2192 * interrupt. 2193 */ 2194 XL_SEL_WIN(4); 2195 CSR_READ_1(sc, XL_W4_BADSSD); 2196 2197 if (mii != NULL) 2198 mii_tick(mii); 2199 2200 XL_SEL_WIN(7); 2201 2202 if (!sc->xl_stats_no_timeout) 2203 sc->xl_stat_ch = timeout(xl_stats_update, sc, hz); 2204 2205 return; 2206} 2207 2208/* 2209 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 2210 * pointers to the fragment pointers. 2211 */ 2212static int xl_encap(sc, c, m_head) 2213 struct xl_softc *sc; 2214 struct xl_chain *c; 2215 struct mbuf *m_head; 2216{ 2217 int frag = 0; 2218 struct xl_frag *f = NULL; 2219 int total_len; 2220 struct mbuf *m; 2221 2222 /* 2223 * Start packing the mbufs in this chain into 2224 * the fragment pointers. Stop when we run out 2225 * of fragments or hit the end of the mbuf chain. 2226 */ 2227 m = m_head; 2228 total_len = 0; 2229 2230 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 2231 if (m->m_len != 0) { 2232 if (frag == XL_MAXFRAGS) 2233 break; 2234 total_len+= m->m_len; 2235 c->xl_ptr->xl_frag[frag].xl_addr = 2236 vtophys(mtod(m, vm_offset_t)); 2237 c->xl_ptr->xl_frag[frag].xl_len = m->m_len; 2238 frag++; 2239 } 2240 } 2241 2242 /* 2243 * Handle special case: we used up all 63 fragments, 2244 * but we have more mbufs left in the chain. Copy the 2245 * data into an mbuf cluster. Note that we don't 2246 * bother clearing the values in the other fragment 2247 * pointers/counters; it wouldn't gain us anything, 2248 * and would waste cycles. 2249 */ 2250 if (m != NULL) { 2251 struct mbuf *m_new = NULL; 2252 2253 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 2254 if (m_new == NULL) { 2255 printf("xl%d: no memory for tx list", sc->xl_unit); 2256 return(1); 2257 } 2258 if (m_head->m_pkthdr.len > MHLEN) { 2259 MCLGET(m_new, M_DONTWAIT); 2260 if (!(m_new->m_flags & M_EXT)) { 2261 m_freem(m_new); 2262 printf("xl%d: no memory for tx list", 2263 sc->xl_unit); 2264 return(1); 2265 } 2266 } 2267 m_copydata(m_head, 0, m_head->m_pkthdr.len, 2268 mtod(m_new, caddr_t)); 2269 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 2270 m_freem(m_head); 2271 m_head = m_new; 2272 f = &c->xl_ptr->xl_frag[0]; 2273 f->xl_addr = vtophys(mtod(m_new, caddr_t)); 2274 f->xl_len = total_len = m_new->m_len; 2275 frag = 1; 2276 } 2277 2278 c->xl_mbuf = m_head; 2279 c->xl_ptr->xl_frag[frag - 1].xl_len |= XL_LAST_FRAG; 2280 c->xl_ptr->xl_status = total_len; 2281 c->xl_ptr->xl_next = 0; 2282 2283 return(0); 2284} 2285 2286/* 2287 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2288 * to the mbuf data regions directly in the transmit lists. We also save a 2289 * copy of the pointers since the transmit list fragment pointers are 2290 * physical addresses. 2291 */ 2292static void xl_start(ifp) 2293 struct ifnet *ifp; 2294{ 2295 struct xl_softc *sc; 2296 struct mbuf *m_head = NULL; 2297 struct xl_chain *prev = NULL, *cur_tx = NULL, *start_tx; 2298 2299 sc = ifp->if_softc; 2300 XL_LOCK(sc); 2301 /* 2302 * Check for an available queue slot. If there are none, 2303 * punt. 2304 */ 2305 if (sc->xl_cdata.xl_tx_free == NULL) { 2306 xl_txeoc(sc); 2307 xl_txeof(sc); 2308 if (sc->xl_cdata.xl_tx_free == NULL) { 2309 ifp->if_flags |= IFF_OACTIVE; 2310 XL_UNLOCK(sc); 2311 return; 2312 } 2313 } 2314 2315 start_tx = sc->xl_cdata.xl_tx_free; 2316 2317 while(sc->xl_cdata.xl_tx_free != NULL) { 2318 IF_DEQUEUE(&ifp->if_snd, m_head); 2319 if (m_head == NULL) 2320 break; 2321 2322 /* Pick a descriptor off the free list. */ 2323 cur_tx = sc->xl_cdata.xl_tx_free; 2324 sc->xl_cdata.xl_tx_free = cur_tx->xl_next; 2325 2326 cur_tx->xl_next = NULL; 2327 2328 /* Pack the data into the descriptor. */ 2329 xl_encap(sc, cur_tx, m_head); 2330 2331 /* Chain it together. */ 2332 if (prev != NULL) { 2333 prev->xl_next = cur_tx; 2334 prev->xl_ptr->xl_next = vtophys(cur_tx->xl_ptr); 2335 } 2336 prev = cur_tx; 2337 2338 /* 2339 * If there's a BPF listener, bounce a copy of this frame 2340 * to him. 2341 */ 2342 if (ifp->if_bpf) 2343 bpf_mtap(ifp, cur_tx->xl_mbuf); 2344 } 2345 2346 /* 2347 * If there are no packets queued, bail. 2348 */ 2349 if (cur_tx == NULL) { 2350 XL_UNLOCK(sc); 2351 return; 2352 } 2353 2354 /* 2355 * Place the request for the upload interrupt 2356 * in the last descriptor in the chain. This way, if 2357 * we're chaining several packets at once, we'll only 2358 * get an interupt once for the whole chain rather than 2359 * once for each packet. 2360 */ 2361 cur_tx->xl_ptr->xl_status |= XL_TXSTAT_DL_INTR; 2362 2363 /* 2364 * Queue the packets. If the TX channel is clear, update 2365 * the downlist pointer register. 2366 */ 2367 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL); 2368 xl_wait(sc); 2369 2370 if (sc->xl_cdata.xl_tx_head != NULL) { 2371 sc->xl_cdata.xl_tx_tail->xl_next = start_tx; 2372 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_next = 2373 vtophys(start_tx->xl_ptr); 2374 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_status &= 2375 ~XL_TXSTAT_DL_INTR; 2376 sc->xl_cdata.xl_tx_tail = cur_tx; 2377 } else { 2378 sc->xl_cdata.xl_tx_head = start_tx; 2379 sc->xl_cdata.xl_tx_tail = cur_tx; 2380 } 2381 if (!CSR_READ_4(sc, XL_DOWNLIST_PTR)) 2382 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, vtophys(start_tx->xl_ptr)); 2383 2384 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2385 2386 XL_SEL_WIN(7); 2387 2388 /* 2389 * Set a timeout in case the chip goes out to lunch. 2390 */ 2391 ifp->if_timer = 5; 2392 2393 /* 2394 * XXX Under certain conditions, usually on slower machines 2395 * where interrupts may be dropped, it's possible for the 2396 * adapter to chew up all the buffers in the receive ring 2397 * and stall, without us being able to do anything about it. 2398 * To guard against this, we need to make a pass over the 2399 * RX queue to make sure there aren't any packets pending. 2400 * Doing it here means we can flush the receive ring at the 2401 * same time the chip is DMAing the transmit descriptors we 2402 * just gave it. 2403 * 2404 * 3Com goes to some lengths to emphasize the Parallel Tasking (tm) 2405 * nature of their chips in all their marketing literature; 2406 * we may as well take advantage of it. :) 2407 */ 2408 xl_rxeof(sc); 2409 2410 XL_UNLOCK(sc); 2411 2412 return; 2413} 2414 2415static int xl_encap_90xB(sc, c, m_head) 2416 struct xl_softc *sc; 2417 struct xl_chain *c; 2418 struct mbuf *m_head; 2419{ 2420 int frag = 0; 2421 struct xl_frag *f = NULL; 2422 struct mbuf *m; 2423 struct xl_list *d; 2424 2425 /* 2426 * Start packing the mbufs in this chain into 2427 * the fragment pointers. Stop when we run out 2428 * of fragments or hit the end of the mbuf chain. 2429 */ 2430 d = c->xl_ptr; 2431 d->xl_status = 0; 2432 d->xl_next = 0; 2433 2434 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 2435 if (m->m_len != 0) { 2436 if (frag == XL_MAXFRAGS) 2437 break; 2438 f = &d->xl_frag[frag]; 2439 f->xl_addr = vtophys(mtod(m, vm_offset_t)); 2440 f->xl_len = m->m_len; 2441 frag++; 2442 } 2443 } 2444 2445 c->xl_mbuf = m_head; 2446 c->xl_ptr->xl_frag[frag - 1].xl_len |= XL_LAST_FRAG; 2447 c->xl_ptr->xl_status = XL_TXSTAT_RND_DEFEAT; 2448 2449 return(0); 2450} 2451 2452static void xl_start_90xB(ifp) 2453 struct ifnet *ifp; 2454{ 2455 struct xl_softc *sc; 2456 struct mbuf *m_head = NULL; 2457 struct xl_chain *prev = NULL, *cur_tx = NULL, *start_tx; 2458 int idx; 2459 2460 sc = ifp->if_softc; 2461 XL_LOCK(sc); 2462 2463 if (ifp->if_flags & IFF_OACTIVE) { 2464 XL_UNLOCK(sc); 2465 return; 2466 } 2467 2468 idx = sc->xl_cdata.xl_tx_prod; 2469 start_tx = &sc->xl_cdata.xl_tx_chain[idx]; 2470 2471 while (sc->xl_cdata.xl_tx_chain[idx].xl_mbuf == NULL) { 2472 2473 if ((XL_TX_LIST_CNT - sc->xl_cdata.xl_tx_cnt) < 3) { 2474 ifp->if_flags |= IFF_OACTIVE; 2475 break; 2476 } 2477 2478 IF_DEQUEUE(&ifp->if_snd, m_head); 2479 if (m_head == NULL) 2480 break; 2481 2482 cur_tx = &sc->xl_cdata.xl_tx_chain[idx]; 2483 2484 /* Pack the data into the descriptor. */ 2485 xl_encap_90xB(sc, cur_tx, m_head); 2486 2487 /* Chain it together. */ 2488 if (prev != NULL) 2489 prev->xl_ptr->xl_next = cur_tx->xl_phys; 2490 prev = cur_tx; 2491 2492 /* 2493 * If there's a BPF listener, bounce a copy of this frame 2494 * to him. 2495 */ 2496 if (ifp->if_bpf) 2497 bpf_mtap(ifp, cur_tx->xl_mbuf); 2498 2499 XL_INC(idx, XL_TX_LIST_CNT); 2500 sc->xl_cdata.xl_tx_cnt++; 2501 } 2502 2503 /* 2504 * If there are no packets queued, bail. 2505 */ 2506 if (cur_tx == NULL) { 2507 XL_UNLOCK(sc); 2508 return; 2509 } 2510 2511 /* 2512 * Place the request for the upload interrupt 2513 * in the last descriptor in the chain. This way, if 2514 * we're chaining several packets at once, we'll only 2515 * get an interupt once for the whole chain rather than 2516 * once for each packet. 2517 */ 2518 cur_tx->xl_ptr->xl_status |= XL_TXSTAT_DL_INTR; 2519 2520 /* Start transmission */ 2521 sc->xl_cdata.xl_tx_prod = idx; 2522 start_tx->xl_prev->xl_ptr->xl_next = start_tx->xl_phys; 2523 2524 /* 2525 * Set a timeout in case the chip goes out to lunch. 2526 */ 2527 ifp->if_timer = 5; 2528 2529 XL_UNLOCK(sc); 2530 2531 return; 2532} 2533 2534static void xl_init(xsc) 2535 void *xsc; 2536{ 2537 struct xl_softc *sc = xsc; 2538 struct ifnet *ifp = &sc->arpcom.ac_if; 2539 int i; 2540 u_int16_t rxfilt = 0; 2541 struct mii_data *mii = NULL; 2542 2543 XL_LOCK(sc); 2544 2545 /* 2546 * Cancel pending I/O and free all RX/TX buffers. 2547 */ 2548 xl_stop(sc); 2549 2550 if (sc->xl_miibus == NULL) { 2551 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 2552 xl_wait(sc); 2553 } 2554 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 2555 xl_wait(sc); 2556 DELAY(10000); 2557 2558 if (sc->xl_miibus != NULL) 2559 mii = device_get_softc(sc->xl_miibus); 2560 2561 /* Init our MAC address */ 2562 XL_SEL_WIN(2); 2563 for (i = 0; i < ETHER_ADDR_LEN; i++) { 2564 CSR_WRITE_1(sc, XL_W2_STATION_ADDR_LO + i, 2565 sc->arpcom.ac_enaddr[i]); 2566 } 2567 2568 /* Clear the station mask. */ 2569 for (i = 0; i < 3; i++) 2570 CSR_WRITE_2(sc, XL_W2_STATION_MASK_LO + (i * 2), 0); 2571#ifdef notdef 2572 /* Reset TX and RX. */ 2573 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 2574 xl_wait(sc); 2575 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 2576 xl_wait(sc); 2577#endif 2578 /* Init circular RX list. */ 2579 if (xl_list_rx_init(sc) == ENOBUFS) { 2580 printf("xl%d: initialization failed: no " 2581 "memory for rx buffers\n", sc->xl_unit); 2582 xl_stop(sc); 2583 return; 2584 } 2585 2586 /* Init TX descriptors. */ 2587 if (sc->xl_type == XL_TYPE_905B) 2588 xl_list_tx_init_90xB(sc); 2589 else 2590 xl_list_tx_init(sc); 2591 2592 /* 2593 * Set the TX freethresh value. 2594 * Note that this has no effect on 3c905B "cyclone" 2595 * cards but is required for 3c900/3c905 "boomerang" 2596 * cards in order to enable the download engine. 2597 */ 2598 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8); 2599 2600 /* Set the TX start threshold for best performance. */ 2601 sc->xl_tx_thresh = XL_MIN_FRAMELEN; 2602 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_SET_START|sc->xl_tx_thresh); 2603 2604 /* 2605 * If this is a 3c905B, also set the tx reclaim threshold. 2606 * This helps cut down on the number of tx reclaim errors 2607 * that could happen on a busy network. The chip multiplies 2608 * the register value by 16 to obtain the actual threshold 2609 * in bytes, so we divide by 16 when setting the value here. 2610 * The existing threshold value can be examined by reading 2611 * the register at offset 9 in window 5. 2612 */ 2613 if (sc->xl_type == XL_TYPE_905B) { 2614 CSR_WRITE_2(sc, XL_COMMAND, 2615 XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4)); 2616 } 2617 2618 /* Set RX filter bits. */ 2619 XL_SEL_WIN(5); 2620 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); 2621 2622 /* Set the individual bit to receive frames for this host only. */ 2623 rxfilt |= XL_RXFILTER_INDIVIDUAL; 2624 2625 /* If we want promiscuous mode, set the allframes bit. */ 2626 if (ifp->if_flags & IFF_PROMISC) { 2627 rxfilt |= XL_RXFILTER_ALLFRAMES; 2628 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 2629 } else { 2630 rxfilt &= ~XL_RXFILTER_ALLFRAMES; 2631 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 2632 } 2633 2634 /* 2635 * Set capture broadcast bit to capture broadcast frames. 2636 */ 2637 if (ifp->if_flags & IFF_BROADCAST) { 2638 rxfilt |= XL_RXFILTER_BROADCAST; 2639 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 2640 } else { 2641 rxfilt &= ~XL_RXFILTER_BROADCAST; 2642 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 2643 } 2644 2645 /* 2646 * Program the multicast filter, if necessary. 2647 */ 2648 if (sc->xl_type == XL_TYPE_905B) 2649 xl_setmulti_hash(sc); 2650 else 2651 xl_setmulti(sc); 2652 2653 /* 2654 * Load the address of the RX list. We have to 2655 * stall the upload engine before we can manipulate 2656 * the uplist pointer register, then unstall it when 2657 * we're finished. We also have to wait for the 2658 * stall command to complete before proceeding. 2659 * Note that we have to do this after any RX resets 2660 * have completed since the uplist register is cleared 2661 * by a reset. 2662 */ 2663 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL); 2664 xl_wait(sc); 2665 CSR_WRITE_4(sc, XL_UPLIST_PTR, vtophys(&sc->xl_ldata->xl_rx_list[0])); 2666 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL); 2667 xl_wait(sc); 2668 2669 2670 if (sc->xl_type == XL_TYPE_905B) { 2671 /* Set polling interval */ 2672 CSR_WRITE_1(sc, XL_DOWN_POLL, 64); 2673 /* Load the address of the TX list */ 2674 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL); 2675 xl_wait(sc); 2676 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2677 vtophys(&sc->xl_ldata->xl_tx_list[0])); 2678 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2679 xl_wait(sc); 2680 } 2681 2682 /* 2683 * If the coax transceiver is on, make sure to enable 2684 * the DC-DC converter. 2685 */ 2686 XL_SEL_WIN(3); 2687 if (sc->xl_xcvr == XL_XCVR_COAX) 2688 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START); 2689 else 2690 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 2691 2692 /* increase packet size to allow reception of 802.1q or ISL packets */ 2693 if (sc->xl_type == XL_TYPE_905B) 2694 CSR_WRITE_2(sc, XL_W3_MAXPKTSIZE, XL_PACKET_SIZE); 2695 /* Clear out the stats counters. */ 2696 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE); 2697 sc->xl_stats_no_timeout = 1; 2698 xl_stats_update(sc); 2699 sc->xl_stats_no_timeout = 0; 2700 XL_SEL_WIN(4); 2701 CSR_WRITE_2(sc, XL_W4_NET_DIAG, XL_NETDIAG_UPPER_BYTES_ENABLE); 2702 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_ENABLE); 2703 2704 /* 2705 * Enable interrupts. 2706 */ 2707 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|0xFF); 2708 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|XL_INTRS); 2709 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|XL_INTRS); 2710 if (sc->xl_flags & XL_FLAG_FUNCREG) 2711 bus_space_write_4(sc->xl_ftag, sc->xl_fhandle, 4, 0x8000); 2712 2713 /* Set the RX early threshold */ 2714 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_THRESH|(XL_PACKET_SIZE >>2)); 2715 CSR_WRITE_2(sc, XL_DMACTL, XL_DMACTL_UP_RX_EARLY); 2716 2717 /* Enable receiver and transmitter. */ 2718 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE); 2719 xl_wait(sc); 2720 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_ENABLE); 2721 xl_wait(sc); 2722 2723 if (mii != NULL) 2724 mii_mediachg(mii); 2725 2726 /* Select window 7 for normal operations. */ 2727 XL_SEL_WIN(7); 2728 2729 ifp->if_flags |= IFF_RUNNING; 2730 ifp->if_flags &= ~IFF_OACTIVE; 2731 2732 sc->xl_stat_ch = timeout(xl_stats_update, sc, hz); 2733 2734 XL_UNLOCK(sc); 2735 2736 return; 2737} 2738 2739/* 2740 * Set media options. 2741 */ 2742static int xl_ifmedia_upd(ifp) 2743 struct ifnet *ifp; 2744{ 2745 struct xl_softc *sc; 2746 struct ifmedia *ifm = NULL; 2747 struct mii_data *mii = NULL; 2748 2749 sc = ifp->if_softc; 2750 if (sc->xl_miibus != NULL) 2751 mii = device_get_softc(sc->xl_miibus); 2752 if (mii == NULL) 2753 ifm = &sc->ifmedia; 2754 else 2755 ifm = &mii->mii_media; 2756 2757 switch(IFM_SUBTYPE(ifm->ifm_media)) { 2758 case IFM_100_FX: 2759 case IFM_10_FL: 2760 case IFM_10_2: 2761 case IFM_10_5: 2762 xl_setmode(sc, ifm->ifm_media); 2763 return(0); 2764 break; 2765 default: 2766 break; 2767 } 2768 2769 if (sc->xl_media & XL_MEDIAOPT_MII || sc->xl_media & XL_MEDIAOPT_BTX 2770 || sc->xl_media & XL_MEDIAOPT_BT4) { 2771 xl_init(sc); 2772 } else { 2773 xl_setmode(sc, ifm->ifm_media); 2774 } 2775 2776 return(0); 2777} 2778 2779/* 2780 * Report current media status. 2781 */ 2782static void xl_ifmedia_sts(ifp, ifmr) 2783 struct ifnet *ifp; 2784 struct ifmediareq *ifmr; 2785{ 2786 struct xl_softc *sc; 2787 u_int32_t icfg; 2788 struct mii_data *mii = NULL; 2789 2790 sc = ifp->if_softc; 2791 if (sc->xl_miibus != NULL) 2792 mii = device_get_softc(sc->xl_miibus); 2793 2794 XL_SEL_WIN(3); 2795 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG) & XL_ICFG_CONNECTOR_MASK; 2796 icfg >>= XL_ICFG_CONNECTOR_BITS; 2797 2798 ifmr->ifm_active = IFM_ETHER; 2799 2800 switch(icfg) { 2801 case XL_XCVR_10BT: 2802 ifmr->ifm_active = IFM_ETHER|IFM_10_T; 2803 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX) 2804 ifmr->ifm_active |= IFM_FDX; 2805 else 2806 ifmr->ifm_active |= IFM_HDX; 2807 break; 2808 case XL_XCVR_AUI: 2809 if (sc->xl_type == XL_TYPE_905B && 2810 sc->xl_media == XL_MEDIAOPT_10FL) { 2811 ifmr->ifm_active = IFM_ETHER|IFM_10_FL; 2812 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX) 2813 ifmr->ifm_active |= IFM_FDX; 2814 else 2815 ifmr->ifm_active |= IFM_HDX; 2816 } else 2817 ifmr->ifm_active = IFM_ETHER|IFM_10_5; 2818 break; 2819 case XL_XCVR_COAX: 2820 ifmr->ifm_active = IFM_ETHER|IFM_10_2; 2821 break; 2822 /* 2823 * XXX MII and BTX/AUTO should be separate cases. 2824 */ 2825 2826 case XL_XCVR_100BTX: 2827 case XL_XCVR_AUTO: 2828 case XL_XCVR_MII: 2829 if (mii != NULL) { 2830 mii_pollstat(mii); 2831 ifmr->ifm_active = mii->mii_media_active; 2832 ifmr->ifm_status = mii->mii_media_status; 2833 } 2834 break; 2835 case XL_XCVR_100BFX: 2836 ifmr->ifm_active = IFM_ETHER|IFM_100_FX; 2837 break; 2838 default: 2839 printf("xl%d: unknown XCVR type: %d\n", sc->xl_unit, icfg); 2840 break; 2841 } 2842 2843 return; 2844} 2845 2846static int xl_ioctl(ifp, command, data) 2847 struct ifnet *ifp; 2848 u_long command; 2849 caddr_t data; 2850{ 2851 struct xl_softc *sc = ifp->if_softc; 2852 struct ifreq *ifr = (struct ifreq *) data; 2853 int error = 0; 2854 struct mii_data *mii = NULL; 2855 u_int8_t rxfilt; 2856 2857 XL_LOCK(sc); 2858 2859 switch(command) { 2860 case SIOCSIFADDR: 2861 case SIOCGIFADDR: 2862 case SIOCSIFMTU: 2863 error = ether_ioctl(ifp, command, data); 2864 break; 2865 case SIOCSIFFLAGS: 2866 XL_SEL_WIN(5); 2867 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); 2868 if (ifp->if_flags & IFF_UP) { 2869 if (ifp->if_flags & IFF_RUNNING && 2870 ifp->if_flags & IFF_PROMISC && 2871 !(sc->xl_if_flags & IFF_PROMISC)) { 2872 rxfilt |= XL_RXFILTER_ALLFRAMES; 2873 CSR_WRITE_2(sc, XL_COMMAND, 2874 XL_CMD_RX_SET_FILT|rxfilt); 2875 XL_SEL_WIN(7); 2876 } else if (ifp->if_flags & IFF_RUNNING && 2877 !(ifp->if_flags & IFF_PROMISC) && 2878 sc->xl_if_flags & IFF_PROMISC) { 2879 rxfilt &= ~XL_RXFILTER_ALLFRAMES; 2880 CSR_WRITE_2(sc, XL_COMMAND, 2881 XL_CMD_RX_SET_FILT|rxfilt); 2882 XL_SEL_WIN(7); 2883 } else 2884 xl_init(sc); 2885 } else { 2886 if (ifp->if_flags & IFF_RUNNING) 2887 xl_stop(sc); 2888 } 2889 sc->xl_if_flags = ifp->if_flags; 2890 error = 0; 2891 break; 2892 case SIOCADDMULTI: 2893 case SIOCDELMULTI: 2894 if (sc->xl_type == XL_TYPE_905B) 2895 xl_setmulti_hash(sc); 2896 else 2897 xl_setmulti(sc); 2898 error = 0; 2899 break; 2900 case SIOCGIFMEDIA: 2901 case SIOCSIFMEDIA: 2902 if (sc->xl_miibus != NULL) 2903 mii = device_get_softc(sc->xl_miibus); 2904 if (mii == NULL) 2905 error = ifmedia_ioctl(ifp, ifr, 2906 &sc->ifmedia, command); 2907 else 2908 error = ifmedia_ioctl(ifp, ifr, 2909 &mii->mii_media, command); 2910 break; 2911 default: 2912 error = EINVAL; 2913 break; 2914 } 2915 2916 XL_UNLOCK(sc); 2917 2918 return(error); 2919} 2920 2921static void xl_watchdog(ifp) 2922 struct ifnet *ifp; 2923{ 2924 struct xl_softc *sc; 2925 u_int16_t status = 0; 2926 2927 sc = ifp->if_softc; 2928 2929 XL_LOCK(sc); 2930 2931 ifp->if_oerrors++; 2932 XL_SEL_WIN(4); 2933 status = CSR_READ_2(sc, XL_W4_MEDIA_STATUS); 2934 printf("xl%d: watchdog timeout\n", sc->xl_unit); 2935 2936 if (status & XL_MEDIASTAT_CARRIER) 2937 printf("xl%d: no carrier - transceiver cable problem?\n", 2938 sc->xl_unit); 2939 xl_txeoc(sc); 2940 xl_txeof(sc); 2941 xl_rxeof(sc); 2942 xl_reset(sc); 2943 xl_init(sc); 2944 2945 if (ifp->if_snd.ifq_head != NULL) 2946 (*ifp->if_start)(ifp); 2947 2948 XL_UNLOCK(sc); 2949 2950 return; 2951} 2952 2953/* 2954 * Stop the adapter and free any mbufs allocated to the 2955 * RX and TX lists. 2956 */ 2957static void xl_stop(sc) 2958 struct xl_softc *sc; 2959{ 2960 register int i; 2961 struct ifnet *ifp; 2962 2963 XL_LOCK(sc); 2964 2965 ifp = &sc->arpcom.ac_if; 2966 ifp->if_timer = 0; 2967 2968 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISABLE); 2969 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE); 2970 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB); 2971 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISCARD); 2972 xl_wait(sc); 2973 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_DISABLE); 2974 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 2975 DELAY(800); 2976 2977#ifdef foo 2978 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 2979 xl_wait(sc); 2980 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 2981 xl_wait(sc); 2982#endif 2983 2984 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|XL_STAT_INTLATCH); 2985 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|0); 2986 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0); 2987 if (sc->xl_flags & XL_FLAG_FUNCREG) bus_space_write_4 (sc->xl_ftag, sc->xl_fhandle, 4, 0x8000); 2988 2989 /* Stop the stats updater. */ 2990 untimeout(xl_stats_update, sc, sc->xl_stat_ch); 2991 2992 /* 2993 * Free data in the RX lists. 2994 */ 2995 for (i = 0; i < XL_RX_LIST_CNT; i++) { 2996 if (sc->xl_cdata.xl_rx_chain[i].xl_mbuf != NULL) { 2997 m_freem(sc->xl_cdata.xl_rx_chain[i].xl_mbuf); 2998 sc->xl_cdata.xl_rx_chain[i].xl_mbuf = NULL; 2999 } 3000 } 3001 bzero((char *)&sc->xl_ldata->xl_rx_list, 3002 sizeof(sc->xl_ldata->xl_rx_list)); 3003 /* 3004 * Free the TX list buffers. 3005 */ 3006 for (i = 0; i < XL_TX_LIST_CNT; i++) { 3007 if (sc->xl_cdata.xl_tx_chain[i].xl_mbuf != NULL) { 3008 m_freem(sc->xl_cdata.xl_tx_chain[i].xl_mbuf); 3009 sc->xl_cdata.xl_tx_chain[i].xl_mbuf = NULL; 3010 } 3011 } 3012 bzero((char *)&sc->xl_ldata->xl_tx_list, 3013 sizeof(sc->xl_ldata->xl_tx_list)); 3014 3015 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3016 3017 XL_UNLOCK(sc); 3018 3019 return; 3020} 3021 3022/* 3023 * Stop all chip I/O so that the kernel's probe routines don't 3024 * get confused by errant DMAs when rebooting. 3025 */ 3026static void xl_shutdown(dev) 3027 device_t dev; 3028{ 3029 struct xl_softc *sc; 3030 3031 sc = device_get_softc(dev); 3032 3033 XL_LOCK(sc); 3034 xl_reset(sc); 3035 xl_stop(sc); 3036 XL_UNLOCK(sc); 3037 3038 return; 3039} 3040