if_xl.c revision 221564
1/*- 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/dev/xl/if_xl.c 221564 2011-05-06 23:01:29Z yongari $"); 35 36/* 37 * 3Com 3c90x Etherlink XL PCI NIC driver 38 * 39 * Supports the 3Com "boomerang", "cyclone" and "hurricane" PCI 40 * bus-master chips (3c90x cards and embedded controllers) including 41 * the following: 42 * 43 * 3Com 3c900-TPO 10Mbps/RJ-45 44 * 3Com 3c900-COMBO 10Mbps/RJ-45,AUI,BNC 45 * 3Com 3c905-TX 10/100Mbps/RJ-45 46 * 3Com 3c905-T4 10/100Mbps/RJ-45 47 * 3Com 3c900B-TPO 10Mbps/RJ-45 48 * 3Com 3c900B-COMBO 10Mbps/RJ-45,AUI,BNC 49 * 3Com 3c900B-TPC 10Mbps/RJ-45,BNC 50 * 3Com 3c900B-FL 10Mbps/Fiber-optic 51 * 3Com 3c905B-COMBO 10/100Mbps/RJ-45,AUI,BNC 52 * 3Com 3c905B-TX 10/100Mbps/RJ-45 53 * 3Com 3c905B-FL/FX 10/100Mbps/Fiber-optic 54 * 3Com 3c905C-TX 10/100Mbps/RJ-45 (Tornado ASIC) 55 * 3Com 3c980-TX 10/100Mbps server adapter (Hurricane ASIC) 56 * 3Com 3c980C-TX 10/100Mbps server adapter (Tornado ASIC) 57 * 3Com 3cSOHO100-TX 10/100Mbps/RJ-45 (Hurricane ASIC) 58 * 3Com 3c450-TX 10/100Mbps/RJ-45 (Tornado ASIC) 59 * 3Com 3c555 10/100Mbps/RJ-45 (MiniPCI, Laptop Hurricane) 60 * 3Com 3c556 10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC) 61 * 3Com 3c556B 10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC) 62 * 3Com 3c575TX 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 63 * 3Com 3c575B 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 64 * 3Com 3c575C 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 65 * 3Com 3cxfem656 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 66 * 3Com 3cxfem656b 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 67 * 3Com 3cxfem656c 10/100Mbps/RJ-45 (Cardbus, Tornado ASIC) 68 * Dell Optiplex GX1 on-board 3c918 10/100Mbps/RJ-45 69 * Dell on-board 3c920 10/100Mbps/RJ-45 70 * Dell Precision on-board 3c905B 10/100Mbps/RJ-45 71 * Dell Latitude laptop docking station embedded 3c905-TX 72 * 73 * Written by Bill Paul <wpaul@ctr.columbia.edu> 74 * Electrical Engineering Department 75 * Columbia University, New York City 76 */ 77/* 78 * The 3c90x series chips use a bus-master DMA interface for transfering 79 * packets to and from the controller chip. Some of the "vortex" cards 80 * (3c59x) also supported a bus master mode, however for those chips 81 * you could only DMA packets to/from a contiguous memory buffer. For 82 * transmission this would mean copying the contents of the queued mbuf 83 * chain into an mbuf cluster and then DMAing the cluster. This extra 84 * copy would sort of defeat the purpose of the bus master support for 85 * any packet that doesn't fit into a single mbuf. 86 * 87 * By contrast, the 3c90x cards support a fragment-based bus master 88 * mode where mbuf chains can be encapsulated using TX descriptors. 89 * This is similar to other PCI chips such as the Texas Instruments 90 * ThunderLAN and the Intel 82557/82558. 91 * 92 * The "vortex" driver (if_vx.c) happens to work for the "boomerang" 93 * bus master chips because they maintain the old PIO interface for 94 * backwards compatibility, but starting with the 3c905B and the 95 * "cyclone" chips, the compatibility interface has been dropped. 96 * Since using bus master DMA is a big win, we use this driver to 97 * support the PCI "boomerang" chips even though they work with the 98 * "vortex" driver in order to obtain better performance. 99 */ 100 101#ifdef HAVE_KERNEL_OPTION_HEADERS 102#include "opt_device_polling.h" 103#endif 104 105#include <sys/param.h> 106#include <sys/systm.h> 107#include <sys/sockio.h> 108#include <sys/endian.h> 109#include <sys/mbuf.h> 110#include <sys/kernel.h> 111#include <sys/module.h> 112#include <sys/socket.h> 113#include <sys/taskqueue.h> 114 115#include <net/if.h> 116#include <net/if_arp.h> 117#include <net/ethernet.h> 118#include <net/if_dl.h> 119#include <net/if_media.h> 120#include <net/if_types.h> 121 122#include <net/bpf.h> 123 124#include <machine/bus.h> 125#include <machine/resource.h> 126#include <sys/bus.h> 127#include <sys/rman.h> 128 129#include <dev/mii/mii.h> 130#include <dev/mii/miivar.h> 131 132#include <dev/pci/pcireg.h> 133#include <dev/pci/pcivar.h> 134 135MODULE_DEPEND(xl, pci, 1, 1, 1); 136MODULE_DEPEND(xl, ether, 1, 1, 1); 137MODULE_DEPEND(xl, miibus, 1, 1, 1); 138 139/* "device miibus" required. See GENERIC if you get errors here. */ 140#include "miibus_if.h" 141 142#include <dev/xl/if_xlreg.h> 143 144/* 145 * TX Checksumming is disabled by default for two reasons: 146 * - TX Checksumming will occasionally produce corrupt packets 147 * - TX Checksumming seems to reduce performance 148 * 149 * Only 905B/C cards were reported to have this problem, it is possible 150 * that later chips _may_ be immune. 151 */ 152#define XL905B_TXCSUM_BROKEN 1 153 154#ifdef XL905B_TXCSUM_BROKEN 155#define XL905B_CSUM_FEATURES 0 156#else 157#define XL905B_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 158#endif 159 160/* 161 * Various supported device vendors/types and their names. 162 */ 163static const struct xl_type xl_devs[] = { 164 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT, 165 "3Com 3c900-TPO Etherlink XL" }, 166 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT_COMBO, 167 "3Com 3c900-COMBO Etherlink XL" }, 168 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10_100BT, 169 "3Com 3c905-TX Fast Etherlink XL" }, 170 { TC_VENDORID, TC_DEVICEID_BOOMERANG_100BT4, 171 "3Com 3c905-T4 Fast Etherlink XL" }, 172 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT, 173 "3Com 3c900B-TPO Etherlink XL" }, 174 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_COMBO, 175 "3Com 3c900B-COMBO Etherlink XL" }, 176 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_TPC, 177 "3Com 3c900B-TPC Etherlink XL" }, 178 { TC_VENDORID, TC_DEVICEID_CYCLONE_10FL, 179 "3Com 3c900B-FL Etherlink XL" }, 180 { TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT, 181 "3Com 3c905B-TX Fast Etherlink XL" }, 182 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100BT4, 183 "3Com 3c905B-T4 Fast Etherlink XL" }, 184 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100FX, 185 "3Com 3c905B-FX/SC Fast Etherlink XL" }, 186 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100_COMBO, 187 "3Com 3c905B-COMBO Fast Etherlink XL" }, 188 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT, 189 "3Com 3c905C-TX Fast Etherlink XL" }, 190 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_920B, 191 "3Com 3c920B-EMB Integrated Fast Etherlink XL" }, 192 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_920B_WNM, 193 "3Com 3c920B-EMB-WNM Integrated Fast Etherlink XL" }, 194 { TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT_SERV, 195 "3Com 3c980 Fast Etherlink XL" }, 196 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_SERV, 197 "3Com 3c980C Fast Etherlink XL" }, 198 { TC_VENDORID, TC_DEVICEID_HURRICANE_SOHO100TX, 199 "3Com 3cSOHO100-TX OfficeConnect" }, 200 { TC_VENDORID, TC_DEVICEID_TORNADO_HOMECONNECT, 201 "3Com 3c450-TX HomeConnect" }, 202 { TC_VENDORID, TC_DEVICEID_HURRICANE_555, 203 "3Com 3c555 Fast Etherlink XL" }, 204 { TC_VENDORID, TC_DEVICEID_HURRICANE_556, 205 "3Com 3c556 Fast Etherlink XL" }, 206 { TC_VENDORID, TC_DEVICEID_HURRICANE_556B, 207 "3Com 3c556B Fast Etherlink XL" }, 208 { TC_VENDORID, TC_DEVICEID_HURRICANE_575A, 209 "3Com 3c575TX Fast Etherlink XL" }, 210 { TC_VENDORID, TC_DEVICEID_HURRICANE_575B, 211 "3Com 3c575B Fast Etherlink XL" }, 212 { TC_VENDORID, TC_DEVICEID_HURRICANE_575C, 213 "3Com 3c575C Fast Etherlink XL" }, 214 { TC_VENDORID, TC_DEVICEID_HURRICANE_656, 215 "3Com 3c656 Fast Etherlink XL" }, 216 { TC_VENDORID, TC_DEVICEID_HURRICANE_656B, 217 "3Com 3c656B Fast Etherlink XL" }, 218 { TC_VENDORID, TC_DEVICEID_TORNADO_656C, 219 "3Com 3c656C Fast Etherlink XL" }, 220 { 0, 0, NULL } 221}; 222 223static int xl_probe(device_t); 224static int xl_attach(device_t); 225static int xl_detach(device_t); 226 227static int xl_newbuf(struct xl_softc *, struct xl_chain_onefrag *); 228static void xl_stats_update(void *); 229static void xl_stats_update_locked(struct xl_softc *); 230static int xl_encap(struct xl_softc *, struct xl_chain *, struct mbuf **); 231static int xl_rxeof(struct xl_softc *); 232static void xl_rxeof_task(void *, int); 233static int xl_rx_resync(struct xl_softc *); 234static void xl_txeof(struct xl_softc *); 235static void xl_txeof_90xB(struct xl_softc *); 236static void xl_txeoc(struct xl_softc *); 237static void xl_intr(void *); 238static void xl_start(struct ifnet *); 239static void xl_start_locked(struct ifnet *); 240static void xl_start_90xB_locked(struct ifnet *); 241static int xl_ioctl(struct ifnet *, u_long, caddr_t); 242static void xl_init(void *); 243static void xl_init_locked(struct xl_softc *); 244static void xl_stop(struct xl_softc *); 245static int xl_watchdog(struct xl_softc *); 246static int xl_shutdown(device_t); 247static int xl_suspend(device_t); 248static int xl_resume(device_t); 249static void xl_setwol(struct xl_softc *); 250 251#ifdef DEVICE_POLLING 252static int xl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count); 253static int xl_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count); 254#endif 255 256static int xl_ifmedia_upd(struct ifnet *); 257static void xl_ifmedia_sts(struct ifnet *, struct ifmediareq *); 258 259static int xl_eeprom_wait(struct xl_softc *); 260static int xl_read_eeprom(struct xl_softc *, caddr_t, int, int, int); 261static void xl_mii_sync(struct xl_softc *); 262static void xl_mii_send(struct xl_softc *, u_int32_t, int); 263static int xl_mii_readreg(struct xl_softc *, struct xl_mii_frame *); 264static int xl_mii_writereg(struct xl_softc *, struct xl_mii_frame *); 265 266static void xl_rxfilter(struct xl_softc *); 267static void xl_rxfilter_90x(struct xl_softc *); 268static void xl_rxfilter_90xB(struct xl_softc *); 269static void xl_setcfg(struct xl_softc *); 270static void xl_setmode(struct xl_softc *, int); 271static void xl_reset(struct xl_softc *); 272static int xl_list_rx_init(struct xl_softc *); 273static int xl_list_tx_init(struct xl_softc *); 274static int xl_list_tx_init_90xB(struct xl_softc *); 275static void xl_wait(struct xl_softc *); 276static void xl_mediacheck(struct xl_softc *); 277static void xl_choose_media(struct xl_softc *sc, int *media); 278static void xl_choose_xcvr(struct xl_softc *, int); 279static void xl_dma_map_addr(void *, bus_dma_segment_t *, int, int); 280#ifdef notdef 281static void xl_testpacket(struct xl_softc *); 282#endif 283 284static int xl_miibus_readreg(device_t, int, int); 285static int xl_miibus_writereg(device_t, int, int, int); 286static void xl_miibus_statchg(device_t); 287static void xl_miibus_mediainit(device_t); 288 289static device_method_t xl_methods[] = { 290 /* Device interface */ 291 DEVMETHOD(device_probe, xl_probe), 292 DEVMETHOD(device_attach, xl_attach), 293 DEVMETHOD(device_detach, xl_detach), 294 DEVMETHOD(device_shutdown, xl_shutdown), 295 DEVMETHOD(device_suspend, xl_suspend), 296 DEVMETHOD(device_resume, xl_resume), 297 298 /* bus interface */ 299 DEVMETHOD(bus_print_child, bus_generic_print_child), 300 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 301 302 /* MII interface */ 303 DEVMETHOD(miibus_readreg, xl_miibus_readreg), 304 DEVMETHOD(miibus_writereg, xl_miibus_writereg), 305 DEVMETHOD(miibus_statchg, xl_miibus_statchg), 306 DEVMETHOD(miibus_mediainit, xl_miibus_mediainit), 307 308 { 0, 0 } 309}; 310 311static driver_t xl_driver = { 312 "xl", 313 xl_methods, 314 sizeof(struct xl_softc) 315}; 316 317static devclass_t xl_devclass; 318 319DRIVER_MODULE(xl, pci, xl_driver, xl_devclass, 0, 0); 320DRIVER_MODULE(miibus, xl, miibus_driver, miibus_devclass, 0, 0); 321 322static void 323xl_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 324{ 325 u_int32_t *paddr; 326 327 paddr = arg; 328 *paddr = segs->ds_addr; 329} 330 331/* 332 * Murphy's law says that it's possible the chip can wedge and 333 * the 'command in progress' bit may never clear. Hence, we wait 334 * only a finite amount of time to avoid getting caught in an 335 * infinite loop. Normally this delay routine would be a macro, 336 * but it isn't called during normal operation so we can afford 337 * to make it a function. 338 */ 339static void 340xl_wait(struct xl_softc *sc) 341{ 342 register int i; 343 344 for (i = 0; i < XL_TIMEOUT; i++) { 345 if ((CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY) == 0) 346 break; 347 } 348 349 if (i == XL_TIMEOUT) 350 device_printf(sc->xl_dev, "command never completed!\n"); 351} 352 353/* 354 * MII access routines are provided for adapters with external 355 * PHYs (3c905-TX, 3c905-T4, 3c905B-T4) and those with built-in 356 * autoneg logic that's faked up to look like a PHY (3c905B-TX). 357 * Note: if you don't perform the MDIO operations just right, 358 * it's possible to end up with code that works correctly with 359 * some chips/CPUs/processor speeds/bus speeds/etc but not 360 * with others. 361 */ 362#define MII_SET(x) \ 363 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, \ 364 CSR_READ_2(sc, XL_W4_PHY_MGMT) | (x)) 365 366#define MII_CLR(x) \ 367 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, \ 368 CSR_READ_2(sc, XL_W4_PHY_MGMT) & ~(x)) 369 370/* 371 * Sync the PHYs by setting data bit and strobing the clock 32 times. 372 */ 373static void 374xl_mii_sync(struct xl_softc *sc) 375{ 376 register int i; 377 378 XL_SEL_WIN(4); 379 MII_SET(XL_MII_DIR|XL_MII_DATA); 380 381 for (i = 0; i < 32; i++) { 382 MII_SET(XL_MII_CLK); 383 MII_SET(XL_MII_DATA); 384 MII_SET(XL_MII_DATA); 385 MII_CLR(XL_MII_CLK); 386 MII_SET(XL_MII_DATA); 387 MII_SET(XL_MII_DATA); 388 } 389} 390 391/* 392 * Clock a series of bits through the MII. 393 */ 394static void 395xl_mii_send(struct xl_softc *sc, u_int32_t bits, int cnt) 396{ 397 int i; 398 399 XL_SEL_WIN(4); 400 MII_CLR(XL_MII_CLK); 401 402 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 403 if (bits & i) { 404 MII_SET(XL_MII_DATA); 405 } else { 406 MII_CLR(XL_MII_DATA); 407 } 408 MII_CLR(XL_MII_CLK); 409 MII_SET(XL_MII_CLK); 410 } 411} 412 413/* 414 * Read an PHY register through the MII. 415 */ 416static int 417xl_mii_readreg(struct xl_softc *sc, struct xl_mii_frame *frame) 418{ 419 int i, ack; 420 421 /* Set up frame for RX. */ 422 frame->mii_stdelim = XL_MII_STARTDELIM; 423 frame->mii_opcode = XL_MII_READOP; 424 frame->mii_turnaround = 0; 425 frame->mii_data = 0; 426 427 /* Select register window 4. */ 428 XL_SEL_WIN(4); 429 430 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, 0); 431 /* Turn on data xmit. */ 432 MII_SET(XL_MII_DIR); 433 434 xl_mii_sync(sc); 435 436 /* Send command/address info. */ 437 xl_mii_send(sc, frame->mii_stdelim, 2); 438 xl_mii_send(sc, frame->mii_opcode, 2); 439 xl_mii_send(sc, frame->mii_phyaddr, 5); 440 xl_mii_send(sc, frame->mii_regaddr, 5); 441 442 /* Idle bit */ 443 MII_CLR((XL_MII_CLK|XL_MII_DATA)); 444 MII_SET(XL_MII_CLK); 445 446 /* Turn off xmit. */ 447 MII_CLR(XL_MII_DIR); 448 449 /* Check for ack */ 450 MII_CLR(XL_MII_CLK); 451 ack = CSR_READ_2(sc, XL_W4_PHY_MGMT) & XL_MII_DATA; 452 MII_SET(XL_MII_CLK); 453 454 /* 455 * Now try reading data bits. If the ack failed, we still 456 * need to clock through 16 cycles to keep the PHY(s) in sync. 457 */ 458 if (ack) { 459 for (i = 0; i < 16; i++) { 460 MII_CLR(XL_MII_CLK); 461 MII_SET(XL_MII_CLK); 462 } 463 goto fail; 464 } 465 466 for (i = 0x8000; i; i >>= 1) { 467 MII_CLR(XL_MII_CLK); 468 if (!ack) { 469 if (CSR_READ_2(sc, XL_W4_PHY_MGMT) & XL_MII_DATA) 470 frame->mii_data |= i; 471 } 472 MII_SET(XL_MII_CLK); 473 } 474 475fail: 476 MII_CLR(XL_MII_CLK); 477 MII_SET(XL_MII_CLK); 478 479 return (ack ? 1 : 0); 480} 481 482/* 483 * Write to a PHY register through the MII. 484 */ 485static int 486xl_mii_writereg(struct xl_softc *sc, struct xl_mii_frame *frame) 487{ 488 489 /* Set up frame for TX. */ 490 frame->mii_stdelim = XL_MII_STARTDELIM; 491 frame->mii_opcode = XL_MII_WRITEOP; 492 frame->mii_turnaround = XL_MII_TURNAROUND; 493 494 /* Select the window 4. */ 495 XL_SEL_WIN(4); 496 497 /* Turn on data output. */ 498 MII_SET(XL_MII_DIR); 499 500 xl_mii_sync(sc); 501 502 xl_mii_send(sc, frame->mii_stdelim, 2); 503 xl_mii_send(sc, frame->mii_opcode, 2); 504 xl_mii_send(sc, frame->mii_phyaddr, 5); 505 xl_mii_send(sc, frame->mii_regaddr, 5); 506 xl_mii_send(sc, frame->mii_turnaround, 2); 507 xl_mii_send(sc, frame->mii_data, 16); 508 509 /* Idle bit. */ 510 MII_SET(XL_MII_CLK); 511 MII_CLR(XL_MII_CLK); 512 513 /* Turn off xmit. */ 514 MII_CLR(XL_MII_DIR); 515 516 return (0); 517} 518 519static int 520xl_miibus_readreg(device_t dev, int phy, int reg) 521{ 522 struct xl_softc *sc; 523 struct xl_mii_frame frame; 524 525 sc = device_get_softc(dev); 526 527 bzero((char *)&frame, sizeof(frame)); 528 frame.mii_phyaddr = phy; 529 frame.mii_regaddr = reg; 530 531 xl_mii_readreg(sc, &frame); 532 533 return (frame.mii_data); 534} 535 536static int 537xl_miibus_writereg(device_t dev, int phy, int reg, int data) 538{ 539 struct xl_softc *sc; 540 struct xl_mii_frame frame; 541 542 sc = device_get_softc(dev); 543 544 bzero((char *)&frame, sizeof(frame)); 545 frame.mii_phyaddr = phy; 546 frame.mii_regaddr = reg; 547 frame.mii_data = data; 548 549 xl_mii_writereg(sc, &frame); 550 551 return (0); 552} 553 554static void 555xl_miibus_statchg(device_t dev) 556{ 557 struct xl_softc *sc; 558 struct mii_data *mii; 559 uint8_t macctl; 560 561 sc = device_get_softc(dev); 562 mii = device_get_softc(sc->xl_miibus); 563 564 xl_setcfg(sc); 565 566 /* Set ASIC's duplex mode to match the PHY. */ 567 XL_SEL_WIN(3); 568 macctl = CSR_READ_1(sc, XL_W3_MAC_CTRL); 569 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 570 macctl |= XL_MACCTRL_DUPLEX; 571 if (sc->xl_type == XL_TYPE_905B) { 572 if ((IFM_OPTIONS(mii->mii_media_active) & 573 IFM_ETH_RXPAUSE) != 0) 574 macctl |= XL_MACCTRL_FLOW_CONTROL_ENB; 575 else 576 macctl &= ~XL_MACCTRL_FLOW_CONTROL_ENB; 577 } 578 } else { 579 macctl &= ~XL_MACCTRL_DUPLEX; 580 if (sc->xl_type == XL_TYPE_905B) 581 macctl &= ~XL_MACCTRL_FLOW_CONTROL_ENB; 582 } 583 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, macctl); 584} 585 586/* 587 * Special support for the 3c905B-COMBO. This card has 10/100 support 588 * plus BNC and AUI ports. This means we will have both an miibus attached 589 * plus some non-MII media settings. In order to allow this, we have to 590 * add the extra media to the miibus's ifmedia struct, but we can't do 591 * that during xl_attach() because the miibus hasn't been attached yet. 592 * So instead, we wait until the miibus probe/attach is done, at which 593 * point we will get a callback telling is that it's safe to add our 594 * extra media. 595 */ 596static void 597xl_miibus_mediainit(device_t dev) 598{ 599 struct xl_softc *sc; 600 struct mii_data *mii; 601 struct ifmedia *ifm; 602 603 sc = device_get_softc(dev); 604 mii = device_get_softc(sc->xl_miibus); 605 ifm = &mii->mii_media; 606 607 if (sc->xl_media & (XL_MEDIAOPT_AUI | XL_MEDIAOPT_10FL)) { 608 /* 609 * Check for a 10baseFL board in disguise. 610 */ 611 if (sc->xl_type == XL_TYPE_905B && 612 sc->xl_media == XL_MEDIAOPT_10FL) { 613 if (bootverbose) 614 device_printf(sc->xl_dev, "found 10baseFL\n"); 615 ifmedia_add(ifm, IFM_ETHER | IFM_10_FL, 0, NULL); 616 ifmedia_add(ifm, IFM_ETHER | IFM_10_FL|IFM_HDX, 0, 617 NULL); 618 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX) 619 ifmedia_add(ifm, 620 IFM_ETHER | IFM_10_FL | IFM_FDX, 0, NULL); 621 } else { 622 if (bootverbose) 623 device_printf(sc->xl_dev, "found AUI\n"); 624 ifmedia_add(ifm, IFM_ETHER | IFM_10_5, 0, NULL); 625 } 626 } 627 628 if (sc->xl_media & XL_MEDIAOPT_BNC) { 629 if (bootverbose) 630 device_printf(sc->xl_dev, "found BNC\n"); 631 ifmedia_add(ifm, IFM_ETHER | IFM_10_2, 0, NULL); 632 } 633} 634 635/* 636 * The EEPROM is slow: give it time to come ready after issuing 637 * it a command. 638 */ 639static int 640xl_eeprom_wait(struct xl_softc *sc) 641{ 642 int i; 643 644 for (i = 0; i < 100; i++) { 645 if (CSR_READ_2(sc, XL_W0_EE_CMD) & XL_EE_BUSY) 646 DELAY(162); 647 else 648 break; 649 } 650 651 if (i == 100) { 652 device_printf(sc->xl_dev, "eeprom failed to come ready\n"); 653 return (1); 654 } 655 656 return (0); 657} 658 659/* 660 * Read a sequence of words from the EEPROM. Note that ethernet address 661 * data is stored in the EEPROM in network byte order. 662 */ 663static int 664xl_read_eeprom(struct xl_softc *sc, caddr_t dest, int off, int cnt, int swap) 665{ 666 int err = 0, i; 667 u_int16_t word = 0, *ptr; 668 669#define EEPROM_5BIT_OFFSET(A) ((((A) << 2) & 0x7F00) | ((A) & 0x003F)) 670#define EEPROM_8BIT_OFFSET(A) ((A) & 0x003F) 671 /* 672 * XXX: WARNING! DANGER! 673 * It's easy to accidentally overwrite the rom content! 674 * Note: the 3c575 uses 8bit EEPROM offsets. 675 */ 676 XL_SEL_WIN(0); 677 678 if (xl_eeprom_wait(sc)) 679 return (1); 680 681 if (sc->xl_flags & XL_FLAG_EEPROM_OFFSET_30) 682 off += 0x30; 683 684 for (i = 0; i < cnt; i++) { 685 if (sc->xl_flags & XL_FLAG_8BITROM) 686 CSR_WRITE_2(sc, XL_W0_EE_CMD, 687 XL_EE_8BIT_READ | EEPROM_8BIT_OFFSET(off + i)); 688 else 689 CSR_WRITE_2(sc, XL_W0_EE_CMD, 690 XL_EE_READ | EEPROM_5BIT_OFFSET(off + i)); 691 err = xl_eeprom_wait(sc); 692 if (err) 693 break; 694 word = CSR_READ_2(sc, XL_W0_EE_DATA); 695 ptr = (u_int16_t *)(dest + (i * 2)); 696 if (swap) 697 *ptr = ntohs(word); 698 else 699 *ptr = word; 700 } 701 702 return (err ? 1 : 0); 703} 704 705static void 706xl_rxfilter(struct xl_softc *sc) 707{ 708 709 if (sc->xl_type == XL_TYPE_905B) 710 xl_rxfilter_90xB(sc); 711 else 712 xl_rxfilter_90x(sc); 713} 714 715/* 716 * NICs older than the 3c905B have only one multicast option, which 717 * is to enable reception of all multicast frames. 718 */ 719static void 720xl_rxfilter_90x(struct xl_softc *sc) 721{ 722 struct ifnet *ifp; 723 struct ifmultiaddr *ifma; 724 u_int8_t rxfilt; 725 726 XL_LOCK_ASSERT(sc); 727 728 ifp = sc->xl_ifp; 729 730 XL_SEL_WIN(5); 731 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); 732 rxfilt &= ~(XL_RXFILTER_ALLFRAMES | XL_RXFILTER_ALLMULTI | 733 XL_RXFILTER_BROADCAST | XL_RXFILTER_INDIVIDUAL); 734 735 /* Set the individual bit to receive frames for this host only. */ 736 rxfilt |= XL_RXFILTER_INDIVIDUAL; 737 /* Set capture broadcast bit to capture broadcast frames. */ 738 if (ifp->if_flags & IFF_BROADCAST) 739 rxfilt |= XL_RXFILTER_BROADCAST; 740 741 /* If we want promiscuous mode, set the allframes bit. */ 742 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) { 743 if (ifp->if_flags & IFF_PROMISC) 744 rxfilt |= XL_RXFILTER_ALLFRAMES; 745 if (ifp->if_flags & IFF_ALLMULTI) 746 rxfilt |= XL_RXFILTER_ALLMULTI; 747 } else { 748 if_maddr_rlock(ifp); 749 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 750 if (ifma->ifma_addr->sa_family != AF_LINK) 751 continue; 752 rxfilt |= XL_RXFILTER_ALLMULTI; 753 break; 754 } 755 if_maddr_runlock(ifp); 756 } 757 758 CSR_WRITE_2(sc, XL_COMMAND, rxfilt | XL_CMD_RX_SET_FILT); 759 XL_SEL_WIN(7); 760} 761 762/* 763 * 3c905B adapters have a hash filter that we can program. 764 */ 765static void 766xl_rxfilter_90xB(struct xl_softc *sc) 767{ 768 struct ifnet *ifp; 769 struct ifmultiaddr *ifma; 770 int i, mcnt; 771 u_int16_t h; 772 u_int8_t rxfilt; 773 774 XL_LOCK_ASSERT(sc); 775 776 ifp = sc->xl_ifp; 777 778 XL_SEL_WIN(5); 779 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); 780 rxfilt &= ~(XL_RXFILTER_ALLFRAMES | XL_RXFILTER_ALLMULTI | 781 XL_RXFILTER_BROADCAST | XL_RXFILTER_INDIVIDUAL | 782 XL_RXFILTER_MULTIHASH); 783 784 /* Set the individual bit to receive frames for this host only. */ 785 rxfilt |= XL_RXFILTER_INDIVIDUAL; 786 /* Set capture broadcast bit to capture broadcast frames. */ 787 if (ifp->if_flags & IFF_BROADCAST) 788 rxfilt |= XL_RXFILTER_BROADCAST; 789 790 /* If we want promiscuous mode, set the allframes bit. */ 791 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) { 792 if (ifp->if_flags & IFF_PROMISC) 793 rxfilt |= XL_RXFILTER_ALLFRAMES; 794 if (ifp->if_flags & IFF_ALLMULTI) 795 rxfilt |= XL_RXFILTER_ALLMULTI; 796 } else { 797 /* First, zot all the existing hash bits. */ 798 for (i = 0; i < XL_HASHFILT_SIZE; i++) 799 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_HASH | i); 800 801 /* Now program new ones. */ 802 mcnt = 0; 803 if_maddr_rlock(ifp); 804 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 805 if (ifma->ifma_addr->sa_family != AF_LINK) 806 continue; 807 /* 808 * Note: the 3c905B currently only supports a 64-bit 809 * hash table, which means we really only need 6 bits, 810 * but the manual indicates that future chip revisions 811 * will have a 256-bit hash table, hence the routine 812 * is set up to calculate 8 bits of position info in 813 * case we need it some day. 814 * Note II, The Sequel: _CURRENT_ versions of the 815 * 3c905B have a 256 bit hash table. This means we have 816 * to use all 8 bits regardless. On older cards, the 817 * upper 2 bits will be ignored. Grrrr.... 818 */ 819 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 820 ifma->ifma_addr), ETHER_ADDR_LEN) & 0xFF; 821 CSR_WRITE_2(sc, XL_COMMAND, 822 h | XL_CMD_RX_SET_HASH | XL_HASH_SET); 823 mcnt++; 824 } 825 if_maddr_runlock(ifp); 826 if (mcnt > 0) 827 rxfilt |= XL_RXFILTER_MULTIHASH; 828 } 829 830 CSR_WRITE_2(sc, XL_COMMAND, rxfilt | XL_CMD_RX_SET_FILT); 831 XL_SEL_WIN(7); 832} 833 834static void 835xl_setcfg(struct xl_softc *sc) 836{ 837 u_int32_t icfg; 838 839 /*XL_LOCK_ASSERT(sc);*/ 840 841 XL_SEL_WIN(3); 842 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG); 843 icfg &= ~XL_ICFG_CONNECTOR_MASK; 844 if (sc->xl_media & XL_MEDIAOPT_MII || 845 sc->xl_media & XL_MEDIAOPT_BT4) 846 icfg |= (XL_XCVR_MII << XL_ICFG_CONNECTOR_BITS); 847 if (sc->xl_media & XL_MEDIAOPT_BTX) 848 icfg |= (XL_XCVR_AUTO << XL_ICFG_CONNECTOR_BITS); 849 850 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg); 851 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 852} 853 854static void 855xl_setmode(struct xl_softc *sc, int media) 856{ 857 u_int32_t icfg; 858 u_int16_t mediastat; 859 char *pmsg = "", *dmsg = ""; 860 861 XL_LOCK_ASSERT(sc); 862 863 XL_SEL_WIN(4); 864 mediastat = CSR_READ_2(sc, XL_W4_MEDIA_STATUS); 865 XL_SEL_WIN(3); 866 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG); 867 868 if (sc->xl_media & XL_MEDIAOPT_BT) { 869 if (IFM_SUBTYPE(media) == IFM_10_T) { 870 pmsg = "10baseT transceiver"; 871 sc->xl_xcvr = XL_XCVR_10BT; 872 icfg &= ~XL_ICFG_CONNECTOR_MASK; 873 icfg |= (XL_XCVR_10BT << XL_ICFG_CONNECTOR_BITS); 874 mediastat |= XL_MEDIASTAT_LINKBEAT | 875 XL_MEDIASTAT_JABGUARD; 876 mediastat &= ~XL_MEDIASTAT_SQEENB; 877 } 878 } 879 880 if (sc->xl_media & XL_MEDIAOPT_BFX) { 881 if (IFM_SUBTYPE(media) == IFM_100_FX) { 882 pmsg = "100baseFX port"; 883 sc->xl_xcvr = XL_XCVR_100BFX; 884 icfg &= ~XL_ICFG_CONNECTOR_MASK; 885 icfg |= (XL_XCVR_100BFX << XL_ICFG_CONNECTOR_BITS); 886 mediastat |= XL_MEDIASTAT_LINKBEAT; 887 mediastat &= ~XL_MEDIASTAT_SQEENB; 888 } 889 } 890 891 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) { 892 if (IFM_SUBTYPE(media) == IFM_10_5) { 893 pmsg = "AUI port"; 894 sc->xl_xcvr = XL_XCVR_AUI; 895 icfg &= ~XL_ICFG_CONNECTOR_MASK; 896 icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS); 897 mediastat &= ~(XL_MEDIASTAT_LINKBEAT | 898 XL_MEDIASTAT_JABGUARD); 899 mediastat |= ~XL_MEDIASTAT_SQEENB; 900 } 901 if (IFM_SUBTYPE(media) == IFM_10_FL) { 902 pmsg = "10baseFL transceiver"; 903 sc->xl_xcvr = XL_XCVR_AUI; 904 icfg &= ~XL_ICFG_CONNECTOR_MASK; 905 icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS); 906 mediastat &= ~(XL_MEDIASTAT_LINKBEAT | 907 XL_MEDIASTAT_JABGUARD); 908 mediastat |= ~XL_MEDIASTAT_SQEENB; 909 } 910 } 911 912 if (sc->xl_media & XL_MEDIAOPT_BNC) { 913 if (IFM_SUBTYPE(media) == IFM_10_2) { 914 pmsg = "AUI port"; 915 sc->xl_xcvr = XL_XCVR_COAX; 916 icfg &= ~XL_ICFG_CONNECTOR_MASK; 917 icfg |= (XL_XCVR_COAX << XL_ICFG_CONNECTOR_BITS); 918 mediastat &= ~(XL_MEDIASTAT_LINKBEAT | 919 XL_MEDIASTAT_JABGUARD | XL_MEDIASTAT_SQEENB); 920 } 921 } 922 923 if ((media & IFM_GMASK) == IFM_FDX || 924 IFM_SUBTYPE(media) == IFM_100_FX) { 925 dmsg = "full"; 926 XL_SEL_WIN(3); 927 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX); 928 } else { 929 dmsg = "half"; 930 XL_SEL_WIN(3); 931 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, 932 (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX)); 933 } 934 935 if (IFM_SUBTYPE(media) == IFM_10_2) 936 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START); 937 else 938 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 939 940 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg); 941 XL_SEL_WIN(4); 942 CSR_WRITE_2(sc, XL_W4_MEDIA_STATUS, mediastat); 943 944 DELAY(800); 945 XL_SEL_WIN(7); 946 947 device_printf(sc->xl_dev, "selecting %s, %s duplex\n", pmsg, dmsg); 948} 949 950static void 951xl_reset(struct xl_softc *sc) 952{ 953 register int i; 954 955 XL_LOCK_ASSERT(sc); 956 957 XL_SEL_WIN(0); 958 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RESET | 959 ((sc->xl_flags & XL_FLAG_WEIRDRESET) ? 960 XL_RESETOPT_DISADVFD:0)); 961 962 /* 963 * If we're using memory mapped register mode, pause briefly 964 * after issuing the reset command before trying to access any 965 * other registers. With my 3c575C CardBus card, failing to do 966 * this results in the system locking up while trying to poll 967 * the command busy bit in the status register. 968 */ 969 if (sc->xl_flags & XL_FLAG_USE_MMIO) 970 DELAY(100000); 971 972 for (i = 0; i < XL_TIMEOUT; i++) { 973 DELAY(10); 974 if (!(CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY)) 975 break; 976 } 977 978 if (i == XL_TIMEOUT) 979 device_printf(sc->xl_dev, "reset didn't complete\n"); 980 981 /* Reset TX and RX. */ 982 /* Note: the RX reset takes an absurd amount of time 983 * on newer versions of the Tornado chips such as those 984 * on the 3c905CX and newer 3c908C cards. We wait an 985 * extra amount of time so that xl_wait() doesn't complain 986 * and annoy the users. 987 */ 988 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 989 DELAY(100000); 990 xl_wait(sc); 991 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 992 xl_wait(sc); 993 994 if (sc->xl_flags & XL_FLAG_INVERT_LED_PWR || 995 sc->xl_flags & XL_FLAG_INVERT_MII_PWR) { 996 XL_SEL_WIN(2); 997 CSR_WRITE_2(sc, XL_W2_RESET_OPTIONS, 998 CSR_READ_2(sc, XL_W2_RESET_OPTIONS) | 999 ((sc->xl_flags & XL_FLAG_INVERT_LED_PWR) ? 1000 XL_RESETOPT_INVERT_LED : 0) | 1001 ((sc->xl_flags & XL_FLAG_INVERT_MII_PWR) ? 1002 XL_RESETOPT_INVERT_MII : 0)); 1003 } 1004 1005 /* Wait a little while for the chip to get its brains in order. */ 1006 DELAY(100000); 1007} 1008 1009/* 1010 * Probe for a 3Com Etherlink XL chip. Check the PCI vendor and device 1011 * IDs against our list and return a device name if we find a match. 1012 */ 1013static int 1014xl_probe(device_t dev) 1015{ 1016 const struct xl_type *t; 1017 1018 t = xl_devs; 1019 1020 while (t->xl_name != NULL) { 1021 if ((pci_get_vendor(dev) == t->xl_vid) && 1022 (pci_get_device(dev) == t->xl_did)) { 1023 device_set_desc(dev, t->xl_name); 1024 return (BUS_PROBE_DEFAULT); 1025 } 1026 t++; 1027 } 1028 1029 return (ENXIO); 1030} 1031 1032/* 1033 * This routine is a kludge to work around possible hardware faults 1034 * or manufacturing defects that can cause the media options register 1035 * (or reset options register, as it's called for the first generation 1036 * 3c90x adapters) to return an incorrect result. I have encountered 1037 * one Dell Latitude laptop docking station with an integrated 3c905-TX 1038 * which doesn't have any of the 'mediaopt' bits set. This screws up 1039 * the attach routine pretty badly because it doesn't know what media 1040 * to look for. If we find ourselves in this predicament, this routine 1041 * will try to guess the media options values and warn the user of a 1042 * possible manufacturing defect with his adapter/system/whatever. 1043 */ 1044static void 1045xl_mediacheck(struct xl_softc *sc) 1046{ 1047 1048 /* 1049 * If some of the media options bits are set, assume they are 1050 * correct. If not, try to figure it out down below. 1051 * XXX I should check for 10baseFL, but I don't have an adapter 1052 * to test with. 1053 */ 1054 if (sc->xl_media & (XL_MEDIAOPT_MASK & ~XL_MEDIAOPT_VCO)) { 1055 /* 1056 * Check the XCVR value. If it's not in the normal range 1057 * of values, we need to fake it up here. 1058 */ 1059 if (sc->xl_xcvr <= XL_XCVR_AUTO) 1060 return; 1061 else { 1062 device_printf(sc->xl_dev, 1063 "bogus xcvr value in EEPROM (%x)\n", sc->xl_xcvr); 1064 device_printf(sc->xl_dev, 1065 "choosing new default based on card type\n"); 1066 } 1067 } else { 1068 if (sc->xl_type == XL_TYPE_905B && 1069 sc->xl_media & XL_MEDIAOPT_10FL) 1070 return; 1071 device_printf(sc->xl_dev, 1072"WARNING: no media options bits set in the media options register!!\n"); 1073 device_printf(sc->xl_dev, 1074"this could be a manufacturing defect in your adapter or system\n"); 1075 device_printf(sc->xl_dev, 1076"attempting to guess media type; you should probably consult your vendor\n"); 1077 } 1078 1079 xl_choose_xcvr(sc, 1); 1080} 1081 1082static void 1083xl_choose_xcvr(struct xl_softc *sc, int verbose) 1084{ 1085 u_int16_t devid; 1086 1087 /* 1088 * Read the device ID from the EEPROM. 1089 * This is what's loaded into the PCI device ID register, so it has 1090 * to be correct otherwise we wouldn't have gotten this far. 1091 */ 1092 xl_read_eeprom(sc, (caddr_t)&devid, XL_EE_PRODID, 1, 0); 1093 1094 switch (devid) { 1095 case TC_DEVICEID_BOOMERANG_10BT: /* 3c900-TPO */ 1096 case TC_DEVICEID_KRAKATOA_10BT: /* 3c900B-TPO */ 1097 sc->xl_media = XL_MEDIAOPT_BT; 1098 sc->xl_xcvr = XL_XCVR_10BT; 1099 if (verbose) 1100 device_printf(sc->xl_dev, 1101 "guessing 10BaseT transceiver\n"); 1102 break; 1103 case TC_DEVICEID_BOOMERANG_10BT_COMBO: /* 3c900-COMBO */ 1104 case TC_DEVICEID_KRAKATOA_10BT_COMBO: /* 3c900B-COMBO */ 1105 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI; 1106 sc->xl_xcvr = XL_XCVR_10BT; 1107 if (verbose) 1108 device_printf(sc->xl_dev, 1109 "guessing COMBO (AUI/BNC/TP)\n"); 1110 break; 1111 case TC_DEVICEID_KRAKATOA_10BT_TPC: /* 3c900B-TPC */ 1112 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC; 1113 sc->xl_xcvr = XL_XCVR_10BT; 1114 if (verbose) 1115 device_printf(sc->xl_dev, "guessing TPC (BNC/TP)\n"); 1116 break; 1117 case TC_DEVICEID_CYCLONE_10FL: /* 3c900B-FL */ 1118 sc->xl_media = XL_MEDIAOPT_10FL; 1119 sc->xl_xcvr = XL_XCVR_AUI; 1120 if (verbose) 1121 device_printf(sc->xl_dev, "guessing 10baseFL\n"); 1122 break; 1123 case TC_DEVICEID_BOOMERANG_10_100BT: /* 3c905-TX */ 1124 case TC_DEVICEID_HURRICANE_555: /* 3c555 */ 1125 case TC_DEVICEID_HURRICANE_556: /* 3c556 */ 1126 case TC_DEVICEID_HURRICANE_556B: /* 3c556B */ 1127 case TC_DEVICEID_HURRICANE_575A: /* 3c575TX */ 1128 case TC_DEVICEID_HURRICANE_575B: /* 3c575B */ 1129 case TC_DEVICEID_HURRICANE_575C: /* 3c575C */ 1130 case TC_DEVICEID_HURRICANE_656: /* 3c656 */ 1131 case TC_DEVICEID_HURRICANE_656B: /* 3c656B */ 1132 case TC_DEVICEID_TORNADO_656C: /* 3c656C */ 1133 case TC_DEVICEID_TORNADO_10_100BT_920B: /* 3c920B-EMB */ 1134 case TC_DEVICEID_TORNADO_10_100BT_920B_WNM: /* 3c920B-EMB-WNM */ 1135 sc->xl_media = XL_MEDIAOPT_MII; 1136 sc->xl_xcvr = XL_XCVR_MII; 1137 if (verbose) 1138 device_printf(sc->xl_dev, "guessing MII\n"); 1139 break; 1140 case TC_DEVICEID_BOOMERANG_100BT4: /* 3c905-T4 */ 1141 case TC_DEVICEID_CYCLONE_10_100BT4: /* 3c905B-T4 */ 1142 sc->xl_media = XL_MEDIAOPT_BT4; 1143 sc->xl_xcvr = XL_XCVR_MII; 1144 if (verbose) 1145 device_printf(sc->xl_dev, "guessing 100baseT4/MII\n"); 1146 break; 1147 case TC_DEVICEID_HURRICANE_10_100BT: /* 3c905B-TX */ 1148 case TC_DEVICEID_HURRICANE_10_100BT_SERV:/*3c980-TX */ 1149 case TC_DEVICEID_TORNADO_10_100BT_SERV: /* 3c980C-TX */ 1150 case TC_DEVICEID_HURRICANE_SOHO100TX: /* 3cSOHO100-TX */ 1151 case TC_DEVICEID_TORNADO_10_100BT: /* 3c905C-TX */ 1152 case TC_DEVICEID_TORNADO_HOMECONNECT: /* 3c450-TX */ 1153 sc->xl_media = XL_MEDIAOPT_BTX; 1154 sc->xl_xcvr = XL_XCVR_AUTO; 1155 if (verbose) 1156 device_printf(sc->xl_dev, "guessing 10/100 internal\n"); 1157 break; 1158 case TC_DEVICEID_CYCLONE_10_100_COMBO: /* 3c905B-COMBO */ 1159 sc->xl_media = XL_MEDIAOPT_BTX|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI; 1160 sc->xl_xcvr = XL_XCVR_AUTO; 1161 if (verbose) 1162 device_printf(sc->xl_dev, 1163 "guessing 10/100 plus BNC/AUI\n"); 1164 break; 1165 default: 1166 device_printf(sc->xl_dev, 1167 "unknown device ID: %x -- defaulting to 10baseT\n", devid); 1168 sc->xl_media = XL_MEDIAOPT_BT; 1169 break; 1170 } 1171} 1172 1173/* 1174 * Attach the interface. Allocate softc structures, do ifmedia 1175 * setup and ethernet/BPF attach. 1176 */ 1177static int 1178xl_attach(device_t dev) 1179{ 1180 u_char eaddr[ETHER_ADDR_LEN]; 1181 u_int16_t sinfo2, xcvr[2]; 1182 struct xl_softc *sc; 1183 struct ifnet *ifp; 1184 int media, pmcap; 1185 int error = 0, phy, rid, res, unit; 1186 uint16_t did; 1187 1188 sc = device_get_softc(dev); 1189 sc->xl_dev = dev; 1190 1191 unit = device_get_unit(dev); 1192 1193 mtx_init(&sc->xl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1194 MTX_DEF); 1195 ifmedia_init(&sc->ifmedia, 0, xl_ifmedia_upd, xl_ifmedia_sts); 1196 1197 did = pci_get_device(dev); 1198 1199 sc->xl_flags = 0; 1200 if (did == TC_DEVICEID_HURRICANE_555) 1201 sc->xl_flags |= XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_PHYOK; 1202 if (did == TC_DEVICEID_HURRICANE_556 || 1203 did == TC_DEVICEID_HURRICANE_556B) 1204 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK | 1205 XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_WEIRDRESET | 1206 XL_FLAG_INVERT_LED_PWR | XL_FLAG_INVERT_MII_PWR; 1207 if (did == TC_DEVICEID_HURRICANE_555 || 1208 did == TC_DEVICEID_HURRICANE_556) 1209 sc->xl_flags |= XL_FLAG_8BITROM; 1210 if (did == TC_DEVICEID_HURRICANE_556B) 1211 sc->xl_flags |= XL_FLAG_NO_XCVR_PWR; 1212 1213 if (did == TC_DEVICEID_HURRICANE_575B || 1214 did == TC_DEVICEID_HURRICANE_575C || 1215 did == TC_DEVICEID_HURRICANE_656B || 1216 did == TC_DEVICEID_TORNADO_656C) 1217 sc->xl_flags |= XL_FLAG_FUNCREG; 1218 if (did == TC_DEVICEID_HURRICANE_575A || 1219 did == TC_DEVICEID_HURRICANE_575B || 1220 did == TC_DEVICEID_HURRICANE_575C || 1221 did == TC_DEVICEID_HURRICANE_656B || 1222 did == TC_DEVICEID_TORNADO_656C) 1223 sc->xl_flags |= XL_FLAG_PHYOK | XL_FLAG_EEPROM_OFFSET_30 | 1224 XL_FLAG_8BITROM; 1225 if (did == TC_DEVICEID_HURRICANE_656) 1226 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK; 1227 if (did == TC_DEVICEID_HURRICANE_575B) 1228 sc->xl_flags |= XL_FLAG_INVERT_LED_PWR; 1229 if (did == TC_DEVICEID_HURRICANE_575C) 1230 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR; 1231 if (did == TC_DEVICEID_TORNADO_656C) 1232 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR; 1233 if (did == TC_DEVICEID_HURRICANE_656 || 1234 did == TC_DEVICEID_HURRICANE_656B) 1235 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR | 1236 XL_FLAG_INVERT_LED_PWR; 1237 if (did == TC_DEVICEID_TORNADO_10_100BT_920B || 1238 did == TC_DEVICEID_TORNADO_10_100BT_920B_WNM) 1239 sc->xl_flags |= XL_FLAG_PHYOK; 1240 1241 switch (did) { 1242 case TC_DEVICEID_BOOMERANG_10_100BT: /* 3c905-TX */ 1243 case TC_DEVICEID_HURRICANE_575A: 1244 case TC_DEVICEID_HURRICANE_575B: 1245 case TC_DEVICEID_HURRICANE_575C: 1246 sc->xl_flags |= XL_FLAG_NO_MMIO; 1247 break; 1248 default: 1249 break; 1250 } 1251 1252 /* 1253 * Map control/status registers. 1254 */ 1255 pci_enable_busmaster(dev); 1256 1257 if ((sc->xl_flags & XL_FLAG_NO_MMIO) == 0) { 1258 rid = XL_PCI_LOMEM; 1259 res = SYS_RES_MEMORY; 1260 1261 sc->xl_res = bus_alloc_resource_any(dev, res, &rid, RF_ACTIVE); 1262 } 1263 1264 if (sc->xl_res != NULL) { 1265 sc->xl_flags |= XL_FLAG_USE_MMIO; 1266 if (bootverbose) 1267 device_printf(dev, "using memory mapped I/O\n"); 1268 } else { 1269 rid = XL_PCI_LOIO; 1270 res = SYS_RES_IOPORT; 1271 sc->xl_res = bus_alloc_resource_any(dev, res, &rid, RF_ACTIVE); 1272 if (sc->xl_res == NULL) { 1273 device_printf(dev, "couldn't map ports/memory\n"); 1274 error = ENXIO; 1275 goto fail; 1276 } 1277 if (bootverbose) 1278 device_printf(dev, "using port I/O\n"); 1279 } 1280 1281 sc->xl_btag = rman_get_bustag(sc->xl_res); 1282 sc->xl_bhandle = rman_get_bushandle(sc->xl_res); 1283 1284 if (sc->xl_flags & XL_FLAG_FUNCREG) { 1285 rid = XL_PCI_FUNCMEM; 1286 sc->xl_fres = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 1287 RF_ACTIVE); 1288 1289 if (sc->xl_fres == NULL) { 1290 device_printf(dev, "couldn't map funcreg memory\n"); 1291 error = ENXIO; 1292 goto fail; 1293 } 1294 1295 sc->xl_ftag = rman_get_bustag(sc->xl_fres); 1296 sc->xl_fhandle = rman_get_bushandle(sc->xl_fres); 1297 } 1298 1299 /* Allocate interrupt */ 1300 rid = 0; 1301 sc->xl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1302 RF_SHAREABLE | RF_ACTIVE); 1303 if (sc->xl_irq == NULL) { 1304 device_printf(dev, "couldn't map interrupt\n"); 1305 error = ENXIO; 1306 goto fail; 1307 } 1308 1309 /* Initialize interface name. */ 1310 ifp = sc->xl_ifp = if_alloc(IFT_ETHER); 1311 if (ifp == NULL) { 1312 device_printf(dev, "can not if_alloc()\n"); 1313 error = ENOSPC; 1314 goto fail; 1315 } 1316 ifp->if_softc = sc; 1317 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1318 1319 /* Reset the adapter. */ 1320 XL_LOCK(sc); 1321 xl_reset(sc); 1322 XL_UNLOCK(sc); 1323 1324 /* 1325 * Get station address from the EEPROM. 1326 */ 1327 if (xl_read_eeprom(sc, (caddr_t)&eaddr, XL_EE_OEM_ADR0, 3, 1)) { 1328 device_printf(dev, "failed to read station address\n"); 1329 error = ENXIO; 1330 goto fail; 1331 } 1332 1333 callout_init_mtx(&sc->xl_stat_callout, &sc->xl_mtx, 0); 1334 TASK_INIT(&sc->xl_task, 0, xl_rxeof_task, sc); 1335 1336 /* 1337 * Now allocate a tag for the DMA descriptor lists and a chunk 1338 * of DMA-able memory based on the tag. Also obtain the DMA 1339 * addresses of the RX and TX ring, which we'll need later. 1340 * All of our lists are allocated as a contiguous block 1341 * of memory. 1342 */ 1343 error = bus_dma_tag_create(bus_get_dma_tag(dev), 8, 0, 1344 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 1345 XL_RX_LIST_SZ, 1, XL_RX_LIST_SZ, 0, NULL, NULL, 1346 &sc->xl_ldata.xl_rx_tag); 1347 if (error) { 1348 device_printf(dev, "failed to allocate rx dma tag\n"); 1349 goto fail; 1350 } 1351 1352 error = bus_dmamem_alloc(sc->xl_ldata.xl_rx_tag, 1353 (void **)&sc->xl_ldata.xl_rx_list, BUS_DMA_NOWAIT | 1354 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->xl_ldata.xl_rx_dmamap); 1355 if (error) { 1356 device_printf(dev, "no memory for rx list buffers!\n"); 1357 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag); 1358 sc->xl_ldata.xl_rx_tag = NULL; 1359 goto fail; 1360 } 1361 1362 error = bus_dmamap_load(sc->xl_ldata.xl_rx_tag, 1363 sc->xl_ldata.xl_rx_dmamap, sc->xl_ldata.xl_rx_list, 1364 XL_RX_LIST_SZ, xl_dma_map_addr, 1365 &sc->xl_ldata.xl_rx_dmaaddr, BUS_DMA_NOWAIT); 1366 if (error) { 1367 device_printf(dev, "cannot get dma address of the rx ring!\n"); 1368 bus_dmamem_free(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_list, 1369 sc->xl_ldata.xl_rx_dmamap); 1370 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag); 1371 sc->xl_ldata.xl_rx_tag = NULL; 1372 goto fail; 1373 } 1374 1375 error = bus_dma_tag_create(bus_get_dma_tag(dev), 8, 0, 1376 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 1377 XL_TX_LIST_SZ, 1, XL_TX_LIST_SZ, 0, NULL, NULL, 1378 &sc->xl_ldata.xl_tx_tag); 1379 if (error) { 1380 device_printf(dev, "failed to allocate tx dma tag\n"); 1381 goto fail; 1382 } 1383 1384 error = bus_dmamem_alloc(sc->xl_ldata.xl_tx_tag, 1385 (void **)&sc->xl_ldata.xl_tx_list, BUS_DMA_NOWAIT | 1386 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->xl_ldata.xl_tx_dmamap); 1387 if (error) { 1388 device_printf(dev, "no memory for list buffers!\n"); 1389 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag); 1390 sc->xl_ldata.xl_tx_tag = NULL; 1391 goto fail; 1392 } 1393 1394 error = bus_dmamap_load(sc->xl_ldata.xl_tx_tag, 1395 sc->xl_ldata.xl_tx_dmamap, sc->xl_ldata.xl_tx_list, 1396 XL_TX_LIST_SZ, xl_dma_map_addr, 1397 &sc->xl_ldata.xl_tx_dmaaddr, BUS_DMA_NOWAIT); 1398 if (error) { 1399 device_printf(dev, "cannot get dma address of the tx ring!\n"); 1400 bus_dmamem_free(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_list, 1401 sc->xl_ldata.xl_tx_dmamap); 1402 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag); 1403 sc->xl_ldata.xl_tx_tag = NULL; 1404 goto fail; 1405 } 1406 1407 /* 1408 * Allocate a DMA tag for the mapping of mbufs. 1409 */ 1410 error = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0, 1411 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 1412 MCLBYTES * XL_MAXFRAGS, XL_MAXFRAGS, MCLBYTES, 0, NULL, 1413 NULL, &sc->xl_mtag); 1414 if (error) { 1415 device_printf(dev, "failed to allocate mbuf dma tag\n"); 1416 goto fail; 1417 } 1418 1419 /* We need a spare DMA map for the RX ring. */ 1420 error = bus_dmamap_create(sc->xl_mtag, 0, &sc->xl_tmpmap); 1421 if (error) 1422 goto fail; 1423 1424 /* 1425 * Figure out the card type. 3c905B adapters have the 1426 * 'supportsNoTxLength' bit set in the capabilities 1427 * word in the EEPROM. 1428 * Note: my 3c575C CardBus card lies. It returns a value 1429 * of 0x1578 for its capabilities word, which is somewhat 1430 * nonsensical. Another way to distinguish a 3c90x chip 1431 * from a 3c90xB/C chip is to check for the 'supportsLargePackets' 1432 * bit. This will only be set for 3c90x boomerage chips. 1433 */ 1434 xl_read_eeprom(sc, (caddr_t)&sc->xl_caps, XL_EE_CAPS, 1, 0); 1435 if (sc->xl_caps & XL_CAPS_NO_TXLENGTH || 1436 !(sc->xl_caps & XL_CAPS_LARGE_PKTS)) 1437 sc->xl_type = XL_TYPE_905B; 1438 else 1439 sc->xl_type = XL_TYPE_90X; 1440 1441 /* Check availability of WOL. */ 1442 if ((sc->xl_caps & XL_CAPS_PWRMGMT) != 0 && 1443 pci_find_cap(dev, PCIY_PMG, &pmcap) == 0) { 1444 sc->xl_pmcap = pmcap; 1445 sc->xl_flags |= XL_FLAG_WOL; 1446 sinfo2 = 0; 1447 xl_read_eeprom(sc, (caddr_t)&sinfo2, XL_EE_SOFTINFO2, 1, 0); 1448 if ((sinfo2 & XL_SINFO2_AUX_WOL_CON) == 0 && bootverbose) 1449 device_printf(dev, 1450 "No auxiliary remote wakeup connector!\n"); 1451 } 1452 1453 /* Set the TX start threshold for best performance. */ 1454 sc->xl_tx_thresh = XL_MIN_FRAMELEN; 1455 1456 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1457 ifp->if_ioctl = xl_ioctl; 1458 ifp->if_capabilities = IFCAP_VLAN_MTU; 1459 if (sc->xl_type == XL_TYPE_905B) { 1460 ifp->if_hwassist = XL905B_CSUM_FEATURES; 1461#ifdef XL905B_TXCSUM_BROKEN 1462 ifp->if_capabilities |= IFCAP_RXCSUM; 1463#else 1464 ifp->if_capabilities |= IFCAP_HWCSUM; 1465#endif 1466 } 1467 if ((sc->xl_flags & XL_FLAG_WOL) != 0) 1468 ifp->if_capabilities |= IFCAP_WOL_MAGIC; 1469 ifp->if_capenable = ifp->if_capabilities; 1470#ifdef DEVICE_POLLING 1471 ifp->if_capabilities |= IFCAP_POLLING; 1472#endif 1473 ifp->if_start = xl_start; 1474 ifp->if_init = xl_init; 1475 IFQ_SET_MAXLEN(&ifp->if_snd, XL_TX_LIST_CNT - 1); 1476 ifp->if_snd.ifq_drv_maxlen = XL_TX_LIST_CNT - 1; 1477 IFQ_SET_READY(&ifp->if_snd); 1478 1479 /* 1480 * Now we have to see what sort of media we have. 1481 * This includes probing for an MII interace and a 1482 * possible PHY. 1483 */ 1484 XL_SEL_WIN(3); 1485 sc->xl_media = CSR_READ_2(sc, XL_W3_MEDIA_OPT); 1486 if (bootverbose) 1487 device_printf(dev, "media options word: %x\n", sc->xl_media); 1488 1489 xl_read_eeprom(sc, (char *)&xcvr, XL_EE_ICFG_0, 2, 0); 1490 sc->xl_xcvr = xcvr[0] | xcvr[1] << 16; 1491 sc->xl_xcvr &= XL_ICFG_CONNECTOR_MASK; 1492 sc->xl_xcvr >>= XL_ICFG_CONNECTOR_BITS; 1493 1494 xl_mediacheck(sc); 1495 1496 if (sc->xl_media & XL_MEDIAOPT_MII || 1497 sc->xl_media & XL_MEDIAOPT_BTX || 1498 sc->xl_media & XL_MEDIAOPT_BT4) { 1499 if (bootverbose) 1500 device_printf(dev, "found MII/AUTO\n"); 1501 xl_setcfg(sc); 1502 /* 1503 * Attach PHYs only at MII address 24 if !XL_FLAG_PHYOK. 1504 * This is to guard against problems with certain 3Com ASIC 1505 * revisions that incorrectly map the internal transceiver 1506 * control registers at all MII addresses. 1507 */ 1508 phy = MII_PHY_ANY; 1509 if ((sc->xl_flags & XL_FLAG_PHYOK) == 0) 1510 phy = 24; 1511 error = mii_attach(dev, &sc->xl_miibus, ifp, xl_ifmedia_upd, 1512 xl_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, 1513 sc->xl_type == XL_TYPE_905B ? MIIF_DOPAUSE : 0); 1514 if (error != 0) { 1515 device_printf(dev, "attaching PHYs failed\n"); 1516 goto fail; 1517 } 1518 goto done; 1519 } 1520 1521 /* 1522 * Sanity check. If the user has selected "auto" and this isn't 1523 * a 10/100 card of some kind, we need to force the transceiver 1524 * type to something sane. 1525 */ 1526 if (sc->xl_xcvr == XL_XCVR_AUTO) 1527 xl_choose_xcvr(sc, bootverbose); 1528 1529 /* 1530 * Do ifmedia setup. 1531 */ 1532 if (sc->xl_media & XL_MEDIAOPT_BT) { 1533 if (bootverbose) 1534 device_printf(dev, "found 10baseT\n"); 1535 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 1536 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL); 1537 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX) 1538 ifmedia_add(&sc->ifmedia, 1539 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 1540 } 1541 1542 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) { 1543 /* 1544 * Check for a 10baseFL board in disguise. 1545 */ 1546 if (sc->xl_type == XL_TYPE_905B && 1547 sc->xl_media == XL_MEDIAOPT_10FL) { 1548 if (bootverbose) 1549 device_printf(dev, "found 10baseFL\n"); 1550 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL, 0, NULL); 1551 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL|IFM_HDX, 1552 0, NULL); 1553 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX) 1554 ifmedia_add(&sc->ifmedia, 1555 IFM_ETHER|IFM_10_FL|IFM_FDX, 0, NULL); 1556 } else { 1557 if (bootverbose) 1558 device_printf(dev, "found AUI\n"); 1559 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_5, 0, NULL); 1560 } 1561 } 1562 1563 if (sc->xl_media & XL_MEDIAOPT_BNC) { 1564 if (bootverbose) 1565 device_printf(dev, "found BNC\n"); 1566 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_2, 0, NULL); 1567 } 1568 1569 if (sc->xl_media & XL_MEDIAOPT_BFX) { 1570 if (bootverbose) 1571 device_printf(dev, "found 100baseFX\n"); 1572 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_FX, 0, NULL); 1573 } 1574 1575 media = IFM_ETHER|IFM_100_TX|IFM_FDX; 1576 xl_choose_media(sc, &media); 1577 1578 if (sc->xl_miibus == NULL) 1579 ifmedia_set(&sc->ifmedia, media); 1580 1581done: 1582 if (sc->xl_flags & XL_FLAG_NO_XCVR_PWR) { 1583 XL_SEL_WIN(0); 1584 CSR_WRITE_2(sc, XL_W0_MFG_ID, XL_NO_XCVR_PWR_MAGICBITS); 1585 } 1586 1587 /* 1588 * Call MI attach routine. 1589 */ 1590 ether_ifattach(ifp, eaddr); 1591 1592 error = bus_setup_intr(dev, sc->xl_irq, INTR_TYPE_NET | INTR_MPSAFE, 1593 NULL, xl_intr, sc, &sc->xl_intrhand); 1594 if (error) { 1595 device_printf(dev, "couldn't set up irq\n"); 1596 ether_ifdetach(ifp); 1597 goto fail; 1598 } 1599 1600fail: 1601 if (error) 1602 xl_detach(dev); 1603 1604 return (error); 1605} 1606 1607/* 1608 * Choose a default media. 1609 * XXX This is a leaf function only called by xl_attach() and 1610 * acquires/releases the non-recursible driver mutex to 1611 * satisfy lock assertions. 1612 */ 1613static void 1614xl_choose_media(struct xl_softc *sc, int *media) 1615{ 1616 1617 XL_LOCK(sc); 1618 1619 switch (sc->xl_xcvr) { 1620 case XL_XCVR_10BT: 1621 *media = IFM_ETHER|IFM_10_T; 1622 xl_setmode(sc, *media); 1623 break; 1624 case XL_XCVR_AUI: 1625 if (sc->xl_type == XL_TYPE_905B && 1626 sc->xl_media == XL_MEDIAOPT_10FL) { 1627 *media = IFM_ETHER|IFM_10_FL; 1628 xl_setmode(sc, *media); 1629 } else { 1630 *media = IFM_ETHER|IFM_10_5; 1631 xl_setmode(sc, *media); 1632 } 1633 break; 1634 case XL_XCVR_COAX: 1635 *media = IFM_ETHER|IFM_10_2; 1636 xl_setmode(sc, *media); 1637 break; 1638 case XL_XCVR_AUTO: 1639 case XL_XCVR_100BTX: 1640 case XL_XCVR_MII: 1641 /* Chosen by miibus */ 1642 break; 1643 case XL_XCVR_100BFX: 1644 *media = IFM_ETHER|IFM_100_FX; 1645 break; 1646 default: 1647 device_printf(sc->xl_dev, "unknown XCVR type: %d\n", 1648 sc->xl_xcvr); 1649 /* 1650 * This will probably be wrong, but it prevents 1651 * the ifmedia code from panicking. 1652 */ 1653 *media = IFM_ETHER|IFM_10_T; 1654 break; 1655 } 1656 1657 XL_UNLOCK(sc); 1658} 1659 1660/* 1661 * Shutdown hardware and free up resources. This can be called any 1662 * time after the mutex has been initialized. It is called in both 1663 * the error case in attach and the normal detach case so it needs 1664 * to be careful about only freeing resources that have actually been 1665 * allocated. 1666 */ 1667static int 1668xl_detach(device_t dev) 1669{ 1670 struct xl_softc *sc; 1671 struct ifnet *ifp; 1672 int rid, res; 1673 1674 sc = device_get_softc(dev); 1675 ifp = sc->xl_ifp; 1676 1677 KASSERT(mtx_initialized(&sc->xl_mtx), ("xl mutex not initialized")); 1678 1679#ifdef DEVICE_POLLING 1680 if (ifp && ifp->if_capenable & IFCAP_POLLING) 1681 ether_poll_deregister(ifp); 1682#endif 1683 1684 if (sc->xl_flags & XL_FLAG_USE_MMIO) { 1685 rid = XL_PCI_LOMEM; 1686 res = SYS_RES_MEMORY; 1687 } else { 1688 rid = XL_PCI_LOIO; 1689 res = SYS_RES_IOPORT; 1690 } 1691 1692 /* These should only be active if attach succeeded */ 1693 if (device_is_attached(dev)) { 1694 XL_LOCK(sc); 1695 xl_stop(sc); 1696 XL_UNLOCK(sc); 1697 taskqueue_drain(taskqueue_swi, &sc->xl_task); 1698 callout_drain(&sc->xl_stat_callout); 1699 ether_ifdetach(ifp); 1700 } 1701 if (sc->xl_miibus) 1702 device_delete_child(dev, sc->xl_miibus); 1703 bus_generic_detach(dev); 1704 ifmedia_removeall(&sc->ifmedia); 1705 1706 if (sc->xl_intrhand) 1707 bus_teardown_intr(dev, sc->xl_irq, sc->xl_intrhand); 1708 if (sc->xl_irq) 1709 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->xl_irq); 1710 if (sc->xl_fres != NULL) 1711 bus_release_resource(dev, SYS_RES_MEMORY, 1712 XL_PCI_FUNCMEM, sc->xl_fres); 1713 if (sc->xl_res) 1714 bus_release_resource(dev, res, rid, sc->xl_res); 1715 1716 if (ifp) 1717 if_free(ifp); 1718 1719 if (sc->xl_mtag) { 1720 bus_dmamap_destroy(sc->xl_mtag, sc->xl_tmpmap); 1721 bus_dma_tag_destroy(sc->xl_mtag); 1722 } 1723 if (sc->xl_ldata.xl_rx_tag) { 1724 bus_dmamap_unload(sc->xl_ldata.xl_rx_tag, 1725 sc->xl_ldata.xl_rx_dmamap); 1726 bus_dmamem_free(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_list, 1727 sc->xl_ldata.xl_rx_dmamap); 1728 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag); 1729 } 1730 if (sc->xl_ldata.xl_tx_tag) { 1731 bus_dmamap_unload(sc->xl_ldata.xl_tx_tag, 1732 sc->xl_ldata.xl_tx_dmamap); 1733 bus_dmamem_free(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_list, 1734 sc->xl_ldata.xl_tx_dmamap); 1735 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag); 1736 } 1737 1738 mtx_destroy(&sc->xl_mtx); 1739 1740 return (0); 1741} 1742 1743/* 1744 * Initialize the transmit descriptors. 1745 */ 1746static int 1747xl_list_tx_init(struct xl_softc *sc) 1748{ 1749 struct xl_chain_data *cd; 1750 struct xl_list_data *ld; 1751 int error, i; 1752 1753 XL_LOCK_ASSERT(sc); 1754 1755 cd = &sc->xl_cdata; 1756 ld = &sc->xl_ldata; 1757 for (i = 0; i < XL_TX_LIST_CNT; i++) { 1758 cd->xl_tx_chain[i].xl_ptr = &ld->xl_tx_list[i]; 1759 error = bus_dmamap_create(sc->xl_mtag, 0, 1760 &cd->xl_tx_chain[i].xl_map); 1761 if (error) 1762 return (error); 1763 cd->xl_tx_chain[i].xl_phys = ld->xl_tx_dmaaddr + 1764 i * sizeof(struct xl_list); 1765 if (i == (XL_TX_LIST_CNT - 1)) 1766 cd->xl_tx_chain[i].xl_next = NULL; 1767 else 1768 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1]; 1769 } 1770 1771 cd->xl_tx_free = &cd->xl_tx_chain[0]; 1772 cd->xl_tx_tail = cd->xl_tx_head = NULL; 1773 1774 bus_dmamap_sync(ld->xl_tx_tag, ld->xl_tx_dmamap, BUS_DMASYNC_PREWRITE); 1775 return (0); 1776} 1777 1778/* 1779 * Initialize the transmit descriptors. 1780 */ 1781static int 1782xl_list_tx_init_90xB(struct xl_softc *sc) 1783{ 1784 struct xl_chain_data *cd; 1785 struct xl_list_data *ld; 1786 int error, i; 1787 1788 XL_LOCK_ASSERT(sc); 1789 1790 cd = &sc->xl_cdata; 1791 ld = &sc->xl_ldata; 1792 for (i = 0; i < XL_TX_LIST_CNT; i++) { 1793 cd->xl_tx_chain[i].xl_ptr = &ld->xl_tx_list[i]; 1794 error = bus_dmamap_create(sc->xl_mtag, 0, 1795 &cd->xl_tx_chain[i].xl_map); 1796 if (error) 1797 return (error); 1798 cd->xl_tx_chain[i].xl_phys = ld->xl_tx_dmaaddr + 1799 i * sizeof(struct xl_list); 1800 if (i == (XL_TX_LIST_CNT - 1)) 1801 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[0]; 1802 else 1803 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1]; 1804 if (i == 0) 1805 cd->xl_tx_chain[i].xl_prev = 1806 &cd->xl_tx_chain[XL_TX_LIST_CNT - 1]; 1807 else 1808 cd->xl_tx_chain[i].xl_prev = 1809 &cd->xl_tx_chain[i - 1]; 1810 } 1811 1812 bzero(ld->xl_tx_list, XL_TX_LIST_SZ); 1813 ld->xl_tx_list[0].xl_status = htole32(XL_TXSTAT_EMPTY); 1814 1815 cd->xl_tx_prod = 1; 1816 cd->xl_tx_cons = 1; 1817 cd->xl_tx_cnt = 0; 1818 1819 bus_dmamap_sync(ld->xl_tx_tag, ld->xl_tx_dmamap, BUS_DMASYNC_PREWRITE); 1820 return (0); 1821} 1822 1823/* 1824 * Initialize the RX descriptors and allocate mbufs for them. Note that 1825 * we arrange the descriptors in a closed ring, so that the last descriptor 1826 * points back to the first. 1827 */ 1828static int 1829xl_list_rx_init(struct xl_softc *sc) 1830{ 1831 struct xl_chain_data *cd; 1832 struct xl_list_data *ld; 1833 int error, i, next; 1834 u_int32_t nextptr; 1835 1836 XL_LOCK_ASSERT(sc); 1837 1838 cd = &sc->xl_cdata; 1839 ld = &sc->xl_ldata; 1840 1841 for (i = 0; i < XL_RX_LIST_CNT; i++) { 1842 cd->xl_rx_chain[i].xl_ptr = &ld->xl_rx_list[i]; 1843 error = bus_dmamap_create(sc->xl_mtag, 0, 1844 &cd->xl_rx_chain[i].xl_map); 1845 if (error) 1846 return (error); 1847 error = xl_newbuf(sc, &cd->xl_rx_chain[i]); 1848 if (error) 1849 return (error); 1850 if (i == (XL_RX_LIST_CNT - 1)) 1851 next = 0; 1852 else 1853 next = i + 1; 1854 nextptr = ld->xl_rx_dmaaddr + 1855 next * sizeof(struct xl_list_onefrag); 1856 cd->xl_rx_chain[i].xl_next = &cd->xl_rx_chain[next]; 1857 ld->xl_rx_list[i].xl_next = htole32(nextptr); 1858 } 1859 1860 bus_dmamap_sync(ld->xl_rx_tag, ld->xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 1861 cd->xl_rx_head = &cd->xl_rx_chain[0]; 1862 1863 return (0); 1864} 1865 1866/* 1867 * Initialize an RX descriptor and attach an MBUF cluster. 1868 * If we fail to do so, we need to leave the old mbuf and 1869 * the old DMA map untouched so that it can be reused. 1870 */ 1871static int 1872xl_newbuf(struct xl_softc *sc, struct xl_chain_onefrag *c) 1873{ 1874 struct mbuf *m_new = NULL; 1875 bus_dmamap_t map; 1876 bus_dma_segment_t segs[1]; 1877 int error, nseg; 1878 1879 XL_LOCK_ASSERT(sc); 1880 1881 m_new = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1882 if (m_new == NULL) 1883 return (ENOBUFS); 1884 1885 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1886 1887 /* Force longword alignment for packet payload. */ 1888 m_adj(m_new, ETHER_ALIGN); 1889 1890 error = bus_dmamap_load_mbuf_sg(sc->xl_mtag, sc->xl_tmpmap, m_new, 1891 segs, &nseg, BUS_DMA_NOWAIT); 1892 if (error) { 1893 m_freem(m_new); 1894 device_printf(sc->xl_dev, "can't map mbuf (error %d)\n", 1895 error); 1896 return (error); 1897 } 1898 KASSERT(nseg == 1, 1899 ("%s: too many DMA segments (%d)", __func__, nseg)); 1900 1901 bus_dmamap_unload(sc->xl_mtag, c->xl_map); 1902 map = c->xl_map; 1903 c->xl_map = sc->xl_tmpmap; 1904 sc->xl_tmpmap = map; 1905 c->xl_mbuf = m_new; 1906 c->xl_ptr->xl_frag.xl_len = htole32(m_new->m_len | XL_LAST_FRAG); 1907 c->xl_ptr->xl_frag.xl_addr = htole32(segs->ds_addr); 1908 c->xl_ptr->xl_status = 0; 1909 bus_dmamap_sync(sc->xl_mtag, c->xl_map, BUS_DMASYNC_PREREAD); 1910 return (0); 1911} 1912 1913static int 1914xl_rx_resync(struct xl_softc *sc) 1915{ 1916 struct xl_chain_onefrag *pos; 1917 int i; 1918 1919 XL_LOCK_ASSERT(sc); 1920 1921 pos = sc->xl_cdata.xl_rx_head; 1922 1923 for (i = 0; i < XL_RX_LIST_CNT; i++) { 1924 if (pos->xl_ptr->xl_status) 1925 break; 1926 pos = pos->xl_next; 1927 } 1928 1929 if (i == XL_RX_LIST_CNT) 1930 return (0); 1931 1932 sc->xl_cdata.xl_rx_head = pos; 1933 1934 return (EAGAIN); 1935} 1936 1937/* 1938 * A frame has been uploaded: pass the resulting mbuf chain up to 1939 * the higher level protocols. 1940 */ 1941static int 1942xl_rxeof(struct xl_softc *sc) 1943{ 1944 struct mbuf *m; 1945 struct ifnet *ifp = sc->xl_ifp; 1946 struct xl_chain_onefrag *cur_rx; 1947 int total_len; 1948 int rx_npkts = 0; 1949 u_int32_t rxstat; 1950 1951 XL_LOCK_ASSERT(sc); 1952again: 1953 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_dmamap, 1954 BUS_DMASYNC_POSTREAD); 1955 while ((rxstat = le32toh(sc->xl_cdata.xl_rx_head->xl_ptr->xl_status))) { 1956#ifdef DEVICE_POLLING 1957 if (ifp->if_capenable & IFCAP_POLLING) { 1958 if (sc->rxcycles <= 0) 1959 break; 1960 sc->rxcycles--; 1961 } 1962#endif 1963 cur_rx = sc->xl_cdata.xl_rx_head; 1964 sc->xl_cdata.xl_rx_head = cur_rx->xl_next; 1965 total_len = rxstat & XL_RXSTAT_LENMASK; 1966 rx_npkts++; 1967 1968 /* 1969 * Since we have told the chip to allow large frames, 1970 * we need to trap giant frame errors in software. We allow 1971 * a little more than the normal frame size to account for 1972 * frames with VLAN tags. 1973 */ 1974 if (total_len > XL_MAX_FRAMELEN) 1975 rxstat |= (XL_RXSTAT_UP_ERROR|XL_RXSTAT_OVERSIZE); 1976 1977 /* 1978 * If an error occurs, update stats, clear the 1979 * status word and leave the mbuf cluster in place: 1980 * it should simply get re-used next time this descriptor 1981 * comes up in the ring. 1982 */ 1983 if (rxstat & XL_RXSTAT_UP_ERROR) { 1984 ifp->if_ierrors++; 1985 cur_rx->xl_ptr->xl_status = 0; 1986 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, 1987 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 1988 continue; 1989 } 1990 1991 /* 1992 * If the error bit was not set, the upload complete 1993 * bit should be set which means we have a valid packet. 1994 * If not, something truly strange has happened. 1995 */ 1996 if (!(rxstat & XL_RXSTAT_UP_CMPLT)) { 1997 device_printf(sc->xl_dev, 1998 "bad receive status -- packet dropped\n"); 1999 ifp->if_ierrors++; 2000 cur_rx->xl_ptr->xl_status = 0; 2001 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, 2002 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 2003 continue; 2004 } 2005 2006 /* No errors; receive the packet. */ 2007 bus_dmamap_sync(sc->xl_mtag, cur_rx->xl_map, 2008 BUS_DMASYNC_POSTREAD); 2009 m = cur_rx->xl_mbuf; 2010 2011 /* 2012 * Try to conjure up a new mbuf cluster. If that 2013 * fails, it means we have an out of memory condition and 2014 * should leave the buffer in place and continue. This will 2015 * result in a lost packet, but there's little else we 2016 * can do in this situation. 2017 */ 2018 if (xl_newbuf(sc, cur_rx)) { 2019 ifp->if_ierrors++; 2020 cur_rx->xl_ptr->xl_status = 0; 2021 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, 2022 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 2023 continue; 2024 } 2025 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, 2026 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 2027 2028 ifp->if_ipackets++; 2029 m->m_pkthdr.rcvif = ifp; 2030 m->m_pkthdr.len = m->m_len = total_len; 2031 2032 if (ifp->if_capenable & IFCAP_RXCSUM) { 2033 /* Do IP checksum checking. */ 2034 if (rxstat & XL_RXSTAT_IPCKOK) 2035 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 2036 if (!(rxstat & XL_RXSTAT_IPCKERR)) 2037 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2038 if ((rxstat & XL_RXSTAT_TCPCOK && 2039 !(rxstat & XL_RXSTAT_TCPCKERR)) || 2040 (rxstat & XL_RXSTAT_UDPCKOK && 2041 !(rxstat & XL_RXSTAT_UDPCKERR))) { 2042 m->m_pkthdr.csum_flags |= 2043 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 2044 m->m_pkthdr.csum_data = 0xffff; 2045 } 2046 } 2047 2048 XL_UNLOCK(sc); 2049 (*ifp->if_input)(ifp, m); 2050 XL_LOCK(sc); 2051 2052 /* 2053 * If we are running from the taskqueue, the interface 2054 * might have been stopped while we were passing the last 2055 * packet up the network stack. 2056 */ 2057 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) 2058 return (rx_npkts); 2059 } 2060 2061 /* 2062 * Handle the 'end of channel' condition. When the upload 2063 * engine hits the end of the RX ring, it will stall. This 2064 * is our cue to flush the RX ring, reload the uplist pointer 2065 * register and unstall the engine. 2066 * XXX This is actually a little goofy. With the ThunderLAN 2067 * chip, you get an interrupt when the receiver hits the end 2068 * of the receive ring, which tells you exactly when you 2069 * you need to reload the ring pointer. Here we have to 2070 * fake it. I'm mad at myself for not being clever enough 2071 * to avoid the use of a goto here. 2072 */ 2073 if (CSR_READ_4(sc, XL_UPLIST_PTR) == 0 || 2074 CSR_READ_4(sc, XL_UPLIST_STATUS) & XL_PKTSTAT_UP_STALLED) { 2075 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL); 2076 xl_wait(sc); 2077 CSR_WRITE_4(sc, XL_UPLIST_PTR, sc->xl_ldata.xl_rx_dmaaddr); 2078 sc->xl_cdata.xl_rx_head = &sc->xl_cdata.xl_rx_chain[0]; 2079 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL); 2080 goto again; 2081 } 2082 return (rx_npkts); 2083} 2084 2085/* 2086 * Taskqueue wrapper for xl_rxeof(). 2087 */ 2088static void 2089xl_rxeof_task(void *arg, int pending) 2090{ 2091 struct xl_softc *sc = (struct xl_softc *)arg; 2092 2093 XL_LOCK(sc); 2094 if (sc->xl_ifp->if_drv_flags & IFF_DRV_RUNNING) 2095 xl_rxeof(sc); 2096 XL_UNLOCK(sc); 2097} 2098 2099/* 2100 * A frame was downloaded to the chip. It's safe for us to clean up 2101 * the list buffers. 2102 */ 2103static void 2104xl_txeof(struct xl_softc *sc) 2105{ 2106 struct xl_chain *cur_tx; 2107 struct ifnet *ifp = sc->xl_ifp; 2108 2109 XL_LOCK_ASSERT(sc); 2110 2111 /* 2112 * Go through our tx list and free mbufs for those 2113 * frames that have been uploaded. Note: the 3c905B 2114 * sets a special bit in the status word to let us 2115 * know that a frame has been downloaded, but the 2116 * original 3c900/3c905 adapters don't do that. 2117 * Consequently, we have to use a different test if 2118 * xl_type != XL_TYPE_905B. 2119 */ 2120 while (sc->xl_cdata.xl_tx_head != NULL) { 2121 cur_tx = sc->xl_cdata.xl_tx_head; 2122 2123 if (CSR_READ_4(sc, XL_DOWNLIST_PTR)) 2124 break; 2125 2126 sc->xl_cdata.xl_tx_head = cur_tx->xl_next; 2127 bus_dmamap_sync(sc->xl_mtag, cur_tx->xl_map, 2128 BUS_DMASYNC_POSTWRITE); 2129 bus_dmamap_unload(sc->xl_mtag, cur_tx->xl_map); 2130 m_freem(cur_tx->xl_mbuf); 2131 cur_tx->xl_mbuf = NULL; 2132 ifp->if_opackets++; 2133 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2134 2135 cur_tx->xl_next = sc->xl_cdata.xl_tx_free; 2136 sc->xl_cdata.xl_tx_free = cur_tx; 2137 } 2138 2139 if (sc->xl_cdata.xl_tx_head == NULL) { 2140 sc->xl_wdog_timer = 0; 2141 sc->xl_cdata.xl_tx_tail = NULL; 2142 } else { 2143 if (CSR_READ_4(sc, XL_DMACTL) & XL_DMACTL_DOWN_STALLED || 2144 !CSR_READ_4(sc, XL_DOWNLIST_PTR)) { 2145 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2146 sc->xl_cdata.xl_tx_head->xl_phys); 2147 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2148 } 2149 } 2150} 2151 2152static void 2153xl_txeof_90xB(struct xl_softc *sc) 2154{ 2155 struct xl_chain *cur_tx = NULL; 2156 struct ifnet *ifp = sc->xl_ifp; 2157 int idx; 2158 2159 XL_LOCK_ASSERT(sc); 2160 2161 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap, 2162 BUS_DMASYNC_POSTREAD); 2163 idx = sc->xl_cdata.xl_tx_cons; 2164 while (idx != sc->xl_cdata.xl_tx_prod) { 2165 cur_tx = &sc->xl_cdata.xl_tx_chain[idx]; 2166 2167 if (!(le32toh(cur_tx->xl_ptr->xl_status) & 2168 XL_TXSTAT_DL_COMPLETE)) 2169 break; 2170 2171 if (cur_tx->xl_mbuf != NULL) { 2172 bus_dmamap_sync(sc->xl_mtag, cur_tx->xl_map, 2173 BUS_DMASYNC_POSTWRITE); 2174 bus_dmamap_unload(sc->xl_mtag, cur_tx->xl_map); 2175 m_freem(cur_tx->xl_mbuf); 2176 cur_tx->xl_mbuf = NULL; 2177 } 2178 2179 ifp->if_opackets++; 2180 2181 sc->xl_cdata.xl_tx_cnt--; 2182 XL_INC(idx, XL_TX_LIST_CNT); 2183 } 2184 2185 if (sc->xl_cdata.xl_tx_cnt == 0) 2186 sc->xl_wdog_timer = 0; 2187 sc->xl_cdata.xl_tx_cons = idx; 2188 2189 if (cur_tx != NULL) 2190 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2191} 2192 2193/* 2194 * TX 'end of channel' interrupt handler. Actually, we should 2195 * only get a 'TX complete' interrupt if there's a transmit error, 2196 * so this is really TX error handler. 2197 */ 2198static void 2199xl_txeoc(struct xl_softc *sc) 2200{ 2201 u_int8_t txstat; 2202 2203 XL_LOCK_ASSERT(sc); 2204 2205 while ((txstat = CSR_READ_1(sc, XL_TX_STATUS))) { 2206 if (txstat & XL_TXSTATUS_UNDERRUN || 2207 txstat & XL_TXSTATUS_JABBER || 2208 txstat & XL_TXSTATUS_RECLAIM) { 2209 device_printf(sc->xl_dev, 2210 "transmission error: %x\n", txstat); 2211 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 2212 xl_wait(sc); 2213 if (sc->xl_type == XL_TYPE_905B) { 2214 if (sc->xl_cdata.xl_tx_cnt) { 2215 int i; 2216 struct xl_chain *c; 2217 2218 i = sc->xl_cdata.xl_tx_cons; 2219 c = &sc->xl_cdata.xl_tx_chain[i]; 2220 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2221 c->xl_phys); 2222 CSR_WRITE_1(sc, XL_DOWN_POLL, 64); 2223 } 2224 } else { 2225 if (sc->xl_cdata.xl_tx_head != NULL) 2226 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2227 sc->xl_cdata.xl_tx_head->xl_phys); 2228 } 2229 /* 2230 * Remember to set this for the 2231 * first generation 3c90X chips. 2232 */ 2233 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8); 2234 if (txstat & XL_TXSTATUS_UNDERRUN && 2235 sc->xl_tx_thresh < XL_PACKET_SIZE) { 2236 sc->xl_tx_thresh += XL_MIN_FRAMELEN; 2237 device_printf(sc->xl_dev, 2238"tx underrun, increasing tx start threshold to %d bytes\n", sc->xl_tx_thresh); 2239 } 2240 CSR_WRITE_2(sc, XL_COMMAND, 2241 XL_CMD_TX_SET_START|sc->xl_tx_thresh); 2242 if (sc->xl_type == XL_TYPE_905B) { 2243 CSR_WRITE_2(sc, XL_COMMAND, 2244 XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4)); 2245 } 2246 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE); 2247 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2248 } else { 2249 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE); 2250 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2251 } 2252 /* 2253 * Write an arbitrary byte to the TX_STATUS register 2254 * to clear this interrupt/error and advance to the next. 2255 */ 2256 CSR_WRITE_1(sc, XL_TX_STATUS, 0x01); 2257 } 2258} 2259 2260static void 2261xl_intr(void *arg) 2262{ 2263 struct xl_softc *sc = arg; 2264 struct ifnet *ifp = sc->xl_ifp; 2265 u_int16_t status; 2266 2267 XL_LOCK(sc); 2268 2269#ifdef DEVICE_POLLING 2270 if (ifp->if_capenable & IFCAP_POLLING) { 2271 XL_UNLOCK(sc); 2272 return; 2273 } 2274#endif 2275 2276 for (;;) { 2277 status = CSR_READ_2(sc, XL_STATUS); 2278 if ((status & XL_INTRS) == 0 || status == 0xFFFF) 2279 break; 2280 CSR_WRITE_2(sc, XL_COMMAND, 2281 XL_CMD_INTR_ACK|(status & XL_INTRS)); 2282 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 2283 break; 2284 2285 if (status & XL_STAT_UP_COMPLETE) { 2286 if (xl_rxeof(sc) == 0) { 2287 while (xl_rx_resync(sc)) 2288 xl_rxeof(sc); 2289 } 2290 } 2291 2292 if (status & XL_STAT_DOWN_COMPLETE) { 2293 if (sc->xl_type == XL_TYPE_905B) 2294 xl_txeof_90xB(sc); 2295 else 2296 xl_txeof(sc); 2297 } 2298 2299 if (status & XL_STAT_TX_COMPLETE) { 2300 ifp->if_oerrors++; 2301 xl_txeoc(sc); 2302 } 2303 2304 if (status & XL_STAT_ADFAIL) { 2305 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2306 xl_init_locked(sc); 2307 break; 2308 } 2309 2310 if (status & XL_STAT_STATSOFLOW) { 2311 sc->xl_stats_no_timeout = 1; 2312 xl_stats_update_locked(sc); 2313 sc->xl_stats_no_timeout = 0; 2314 } 2315 } 2316 2317 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 2318 ifp->if_drv_flags & IFF_DRV_RUNNING) { 2319 if (sc->xl_type == XL_TYPE_905B) 2320 xl_start_90xB_locked(ifp); 2321 else 2322 xl_start_locked(ifp); 2323 } 2324 2325 XL_UNLOCK(sc); 2326} 2327 2328#ifdef DEVICE_POLLING 2329static int 2330xl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 2331{ 2332 struct xl_softc *sc = ifp->if_softc; 2333 int rx_npkts = 0; 2334 2335 XL_LOCK(sc); 2336 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2337 rx_npkts = xl_poll_locked(ifp, cmd, count); 2338 XL_UNLOCK(sc); 2339 return (rx_npkts); 2340} 2341 2342static int 2343xl_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) 2344{ 2345 struct xl_softc *sc = ifp->if_softc; 2346 int rx_npkts; 2347 2348 XL_LOCK_ASSERT(sc); 2349 2350 sc->rxcycles = count; 2351 rx_npkts = xl_rxeof(sc); 2352 if (sc->xl_type == XL_TYPE_905B) 2353 xl_txeof_90xB(sc); 2354 else 2355 xl_txeof(sc); 2356 2357 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 2358 if (sc->xl_type == XL_TYPE_905B) 2359 xl_start_90xB_locked(ifp); 2360 else 2361 xl_start_locked(ifp); 2362 } 2363 2364 if (cmd == POLL_AND_CHECK_STATUS) { 2365 u_int16_t status; 2366 2367 status = CSR_READ_2(sc, XL_STATUS); 2368 if (status & XL_INTRS && status != 0xFFFF) { 2369 CSR_WRITE_2(sc, XL_COMMAND, 2370 XL_CMD_INTR_ACK|(status & XL_INTRS)); 2371 2372 if (status & XL_STAT_TX_COMPLETE) { 2373 ifp->if_oerrors++; 2374 xl_txeoc(sc); 2375 } 2376 2377 if (status & XL_STAT_ADFAIL) { 2378 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2379 xl_init_locked(sc); 2380 } 2381 2382 if (status & XL_STAT_STATSOFLOW) { 2383 sc->xl_stats_no_timeout = 1; 2384 xl_stats_update_locked(sc); 2385 sc->xl_stats_no_timeout = 0; 2386 } 2387 } 2388 } 2389 return (rx_npkts); 2390} 2391#endif /* DEVICE_POLLING */ 2392 2393/* 2394 * XXX: This is an entry point for callout which needs to take the lock. 2395 */ 2396static void 2397xl_stats_update(void *xsc) 2398{ 2399 struct xl_softc *sc = xsc; 2400 2401 XL_LOCK_ASSERT(sc); 2402 2403 if (xl_watchdog(sc) == EJUSTRETURN) 2404 return; 2405 2406 xl_stats_update_locked(sc); 2407} 2408 2409static void 2410xl_stats_update_locked(struct xl_softc *sc) 2411{ 2412 struct ifnet *ifp = sc->xl_ifp; 2413 struct xl_stats xl_stats; 2414 u_int8_t *p; 2415 int i; 2416 struct mii_data *mii = NULL; 2417 2418 XL_LOCK_ASSERT(sc); 2419 2420 bzero((char *)&xl_stats, sizeof(struct xl_stats)); 2421 2422 if (sc->xl_miibus != NULL) 2423 mii = device_get_softc(sc->xl_miibus); 2424 2425 p = (u_int8_t *)&xl_stats; 2426 2427 /* Read all the stats registers. */ 2428 XL_SEL_WIN(6); 2429 2430 for (i = 0; i < 16; i++) 2431 *p++ = CSR_READ_1(sc, XL_W6_CARRIER_LOST + i); 2432 2433 ifp->if_ierrors += xl_stats.xl_rx_overrun; 2434 2435 ifp->if_collisions += xl_stats.xl_tx_multi_collision + 2436 xl_stats.xl_tx_single_collision + xl_stats.xl_tx_late_collision; 2437 2438 /* 2439 * Boomerang and cyclone chips have an extra stats counter 2440 * in window 4 (BadSSD). We have to read this too in order 2441 * to clear out all the stats registers and avoid a statsoflow 2442 * interrupt. 2443 */ 2444 XL_SEL_WIN(4); 2445 CSR_READ_1(sc, XL_W4_BADSSD); 2446 2447 if ((mii != NULL) && (!sc->xl_stats_no_timeout)) 2448 mii_tick(mii); 2449 2450 XL_SEL_WIN(7); 2451 2452 if (!sc->xl_stats_no_timeout) 2453 callout_reset(&sc->xl_stat_callout, hz, xl_stats_update, sc); 2454} 2455 2456/* 2457 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 2458 * pointers to the fragment pointers. 2459 */ 2460static int 2461xl_encap(struct xl_softc *sc, struct xl_chain *c, struct mbuf **m_head) 2462{ 2463 struct mbuf *m_new; 2464 struct ifnet *ifp = sc->xl_ifp; 2465 int error, i, nseg, total_len; 2466 u_int32_t status; 2467 2468 XL_LOCK_ASSERT(sc); 2469 2470 error = bus_dmamap_load_mbuf_sg(sc->xl_mtag, c->xl_map, *m_head, 2471 sc->xl_cdata.xl_tx_segs, &nseg, BUS_DMA_NOWAIT); 2472 2473 if (error && error != EFBIG) { 2474 if_printf(ifp, "can't map mbuf (error %d)\n", error); 2475 return (error); 2476 } 2477 2478 /* 2479 * Handle special case: we used up all 63 fragments, 2480 * but we have more mbufs left in the chain. Copy the 2481 * data into an mbuf cluster. Note that we don't 2482 * bother clearing the values in the other fragment 2483 * pointers/counters; it wouldn't gain us anything, 2484 * and would waste cycles. 2485 */ 2486 if (error) { 2487 m_new = m_collapse(*m_head, M_DONTWAIT, XL_MAXFRAGS); 2488 if (m_new == NULL) { 2489 m_freem(*m_head); 2490 *m_head = NULL; 2491 return (ENOBUFS); 2492 } 2493 *m_head = m_new; 2494 2495 error = bus_dmamap_load_mbuf_sg(sc->xl_mtag, c->xl_map, 2496 *m_head, sc->xl_cdata.xl_tx_segs, &nseg, BUS_DMA_NOWAIT); 2497 if (error) { 2498 m_freem(*m_head); 2499 *m_head = NULL; 2500 if_printf(ifp, "can't map mbuf (error %d)\n", error); 2501 return (error); 2502 } 2503 } 2504 2505 KASSERT(nseg <= XL_MAXFRAGS, 2506 ("%s: too many DMA segments (%d)", __func__, nseg)); 2507 if (nseg == 0) { 2508 m_freem(*m_head); 2509 *m_head = NULL; 2510 return (EIO); 2511 } 2512 bus_dmamap_sync(sc->xl_mtag, c->xl_map, BUS_DMASYNC_PREWRITE); 2513 2514 total_len = 0; 2515 for (i = 0; i < nseg; i++) { 2516 KASSERT(sc->xl_cdata.xl_tx_segs[i].ds_len <= MCLBYTES, 2517 ("segment size too large")); 2518 c->xl_ptr->xl_frag[i].xl_addr = 2519 htole32(sc->xl_cdata.xl_tx_segs[i].ds_addr); 2520 c->xl_ptr->xl_frag[i].xl_len = 2521 htole32(sc->xl_cdata.xl_tx_segs[i].ds_len); 2522 total_len += sc->xl_cdata.xl_tx_segs[i].ds_len; 2523 } 2524 c->xl_ptr->xl_frag[nseg - 1].xl_len |= htole32(XL_LAST_FRAG); 2525 2526 if (sc->xl_type == XL_TYPE_905B) { 2527 status = XL_TXSTAT_RND_DEFEAT; 2528 2529#ifndef XL905B_TXCSUM_BROKEN 2530 if ((*m_head)->m_pkthdr.csum_flags) { 2531 if ((*m_head)->m_pkthdr.csum_flags & CSUM_IP) 2532 status |= XL_TXSTAT_IPCKSUM; 2533 if ((*m_head)->m_pkthdr.csum_flags & CSUM_TCP) 2534 status |= XL_TXSTAT_TCPCKSUM; 2535 if ((*m_head)->m_pkthdr.csum_flags & CSUM_UDP) 2536 status |= XL_TXSTAT_UDPCKSUM; 2537 } 2538#endif 2539 } else 2540 status = total_len; 2541 c->xl_ptr->xl_status = htole32(status); 2542 c->xl_ptr->xl_next = 0; 2543 2544 c->xl_mbuf = *m_head; 2545 return (0); 2546} 2547 2548/* 2549 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2550 * to the mbuf data regions directly in the transmit lists. We also save a 2551 * copy of the pointers since the transmit list fragment pointers are 2552 * physical addresses. 2553 */ 2554 2555static void 2556xl_start(struct ifnet *ifp) 2557{ 2558 struct xl_softc *sc = ifp->if_softc; 2559 2560 XL_LOCK(sc); 2561 2562 if (sc->xl_type == XL_TYPE_905B) 2563 xl_start_90xB_locked(ifp); 2564 else 2565 xl_start_locked(ifp); 2566 2567 XL_UNLOCK(sc); 2568} 2569 2570static void 2571xl_start_locked(struct ifnet *ifp) 2572{ 2573 struct xl_softc *sc = ifp->if_softc; 2574 struct mbuf *m_head = NULL; 2575 struct xl_chain *prev = NULL, *cur_tx = NULL, *start_tx; 2576 u_int32_t status; 2577 int error; 2578 2579 XL_LOCK_ASSERT(sc); 2580 2581 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2582 IFF_DRV_RUNNING) 2583 return; 2584 /* 2585 * Check for an available queue slot. If there are none, 2586 * punt. 2587 */ 2588 if (sc->xl_cdata.xl_tx_free == NULL) { 2589 xl_txeoc(sc); 2590 xl_txeof(sc); 2591 if (sc->xl_cdata.xl_tx_free == NULL) { 2592 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2593 return; 2594 } 2595 } 2596 2597 start_tx = sc->xl_cdata.xl_tx_free; 2598 2599 for (; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 2600 sc->xl_cdata.xl_tx_free != NULL;) { 2601 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2602 if (m_head == NULL) 2603 break; 2604 2605 /* Pick a descriptor off the free list. */ 2606 cur_tx = sc->xl_cdata.xl_tx_free; 2607 2608 /* Pack the data into the descriptor. */ 2609 error = xl_encap(sc, cur_tx, &m_head); 2610 if (error) { 2611 if (m_head == NULL) 2612 break; 2613 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2614 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2615 break; 2616 } 2617 2618 sc->xl_cdata.xl_tx_free = cur_tx->xl_next; 2619 cur_tx->xl_next = NULL; 2620 2621 /* Chain it together. */ 2622 if (prev != NULL) { 2623 prev->xl_next = cur_tx; 2624 prev->xl_ptr->xl_next = htole32(cur_tx->xl_phys); 2625 } 2626 prev = cur_tx; 2627 2628 /* 2629 * If there's a BPF listener, bounce a copy of this frame 2630 * to him. 2631 */ 2632 BPF_MTAP(ifp, cur_tx->xl_mbuf); 2633 } 2634 2635 /* 2636 * If there are no packets queued, bail. 2637 */ 2638 if (cur_tx == NULL) 2639 return; 2640 2641 /* 2642 * Place the request for the upload interrupt 2643 * in the last descriptor in the chain. This way, if 2644 * we're chaining several packets at once, we'll only 2645 * get an interrupt once for the whole chain rather than 2646 * once for each packet. 2647 */ 2648 cur_tx->xl_ptr->xl_status |= htole32(XL_TXSTAT_DL_INTR); 2649 2650 /* 2651 * Queue the packets. If the TX channel is clear, update 2652 * the downlist pointer register. 2653 */ 2654 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL); 2655 xl_wait(sc); 2656 2657 if (sc->xl_cdata.xl_tx_head != NULL) { 2658 sc->xl_cdata.xl_tx_tail->xl_next = start_tx; 2659 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_next = 2660 htole32(start_tx->xl_phys); 2661 status = sc->xl_cdata.xl_tx_tail->xl_ptr->xl_status; 2662 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_status &= 2663 htole32(~XL_TXSTAT_DL_INTR); 2664 sc->xl_cdata.xl_tx_tail = cur_tx; 2665 } else { 2666 sc->xl_cdata.xl_tx_head = start_tx; 2667 sc->xl_cdata.xl_tx_tail = cur_tx; 2668 } 2669 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap, 2670 BUS_DMASYNC_PREWRITE); 2671 if (!CSR_READ_4(sc, XL_DOWNLIST_PTR)) 2672 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, start_tx->xl_phys); 2673 2674 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2675 2676 XL_SEL_WIN(7); 2677 2678 /* 2679 * Set a timeout in case the chip goes out to lunch. 2680 */ 2681 sc->xl_wdog_timer = 5; 2682 2683 /* 2684 * XXX Under certain conditions, usually on slower machines 2685 * where interrupts may be dropped, it's possible for the 2686 * adapter to chew up all the buffers in the receive ring 2687 * and stall, without us being able to do anything about it. 2688 * To guard against this, we need to make a pass over the 2689 * RX queue to make sure there aren't any packets pending. 2690 * Doing it here means we can flush the receive ring at the 2691 * same time the chip is DMAing the transmit descriptors we 2692 * just gave it. 2693 * 2694 * 3Com goes to some lengths to emphasize the Parallel Tasking (tm) 2695 * nature of their chips in all their marketing literature; 2696 * we may as well take advantage of it. :) 2697 */ 2698 taskqueue_enqueue(taskqueue_swi, &sc->xl_task); 2699} 2700 2701static void 2702xl_start_90xB_locked(struct ifnet *ifp) 2703{ 2704 struct xl_softc *sc = ifp->if_softc; 2705 struct mbuf *m_head = NULL; 2706 struct xl_chain *prev = NULL, *cur_tx = NULL, *start_tx; 2707 int error, idx; 2708 2709 XL_LOCK_ASSERT(sc); 2710 2711 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2712 IFF_DRV_RUNNING) 2713 return; 2714 2715 idx = sc->xl_cdata.xl_tx_prod; 2716 start_tx = &sc->xl_cdata.xl_tx_chain[idx]; 2717 2718 for (; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 2719 sc->xl_cdata.xl_tx_chain[idx].xl_mbuf == NULL;) { 2720 if ((XL_TX_LIST_CNT - sc->xl_cdata.xl_tx_cnt) < 3) { 2721 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2722 break; 2723 } 2724 2725 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2726 if (m_head == NULL) 2727 break; 2728 2729 cur_tx = &sc->xl_cdata.xl_tx_chain[idx]; 2730 2731 /* Pack the data into the descriptor. */ 2732 error = xl_encap(sc, cur_tx, &m_head); 2733 if (error) { 2734 if (m_head == NULL) 2735 break; 2736 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2737 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2738 break; 2739 } 2740 2741 /* Chain it together. */ 2742 if (prev != NULL) 2743 prev->xl_ptr->xl_next = htole32(cur_tx->xl_phys); 2744 prev = cur_tx; 2745 2746 /* 2747 * If there's a BPF listener, bounce a copy of this frame 2748 * to him. 2749 */ 2750 BPF_MTAP(ifp, cur_tx->xl_mbuf); 2751 2752 XL_INC(idx, XL_TX_LIST_CNT); 2753 sc->xl_cdata.xl_tx_cnt++; 2754 } 2755 2756 /* 2757 * If there are no packets queued, bail. 2758 */ 2759 if (cur_tx == NULL) 2760 return; 2761 2762 /* 2763 * Place the request for the upload interrupt 2764 * in the last descriptor in the chain. This way, if 2765 * we're chaining several packets at once, we'll only 2766 * get an interrupt once for the whole chain rather than 2767 * once for each packet. 2768 */ 2769 cur_tx->xl_ptr->xl_status |= htole32(XL_TXSTAT_DL_INTR); 2770 2771 /* Start transmission */ 2772 sc->xl_cdata.xl_tx_prod = idx; 2773 start_tx->xl_prev->xl_ptr->xl_next = htole32(start_tx->xl_phys); 2774 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap, 2775 BUS_DMASYNC_PREWRITE); 2776 2777 /* 2778 * Set a timeout in case the chip goes out to lunch. 2779 */ 2780 sc->xl_wdog_timer = 5; 2781} 2782 2783static void 2784xl_init(void *xsc) 2785{ 2786 struct xl_softc *sc = xsc; 2787 2788 XL_LOCK(sc); 2789 xl_init_locked(sc); 2790 XL_UNLOCK(sc); 2791} 2792 2793static void 2794xl_init_locked(struct xl_softc *sc) 2795{ 2796 struct ifnet *ifp = sc->xl_ifp; 2797 int error, i; 2798 struct mii_data *mii = NULL; 2799 2800 XL_LOCK_ASSERT(sc); 2801 2802 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2803 return; 2804 /* 2805 * Cancel pending I/O and free all RX/TX buffers. 2806 */ 2807 xl_stop(sc); 2808 2809 /* Reset the chip to a known state. */ 2810 xl_reset(sc); 2811 2812 if (sc->xl_miibus == NULL) { 2813 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 2814 xl_wait(sc); 2815 } 2816 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 2817 xl_wait(sc); 2818 DELAY(10000); 2819 2820 if (sc->xl_miibus != NULL) 2821 mii = device_get_softc(sc->xl_miibus); 2822 2823 /* 2824 * Clear WOL status and disable all WOL feature as WOL 2825 * would interfere Rx operation under normal environments. 2826 */ 2827 if ((sc->xl_flags & XL_FLAG_WOL) != 0) { 2828 XL_SEL_WIN(7); 2829 CSR_READ_2(sc, XL_W7_BM_PME); 2830 CSR_WRITE_2(sc, XL_W7_BM_PME, 0); 2831 } 2832 /* Init our MAC address */ 2833 XL_SEL_WIN(2); 2834 for (i = 0; i < ETHER_ADDR_LEN; i++) { 2835 CSR_WRITE_1(sc, XL_W2_STATION_ADDR_LO + i, 2836 IF_LLADDR(sc->xl_ifp)[i]); 2837 } 2838 2839 /* Clear the station mask. */ 2840 for (i = 0; i < 3; i++) 2841 CSR_WRITE_2(sc, XL_W2_STATION_MASK_LO + (i * 2), 0); 2842#ifdef notdef 2843 /* Reset TX and RX. */ 2844 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 2845 xl_wait(sc); 2846 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 2847 xl_wait(sc); 2848#endif 2849 /* Init circular RX list. */ 2850 error = xl_list_rx_init(sc); 2851 if (error) { 2852 device_printf(sc->xl_dev, "initialization of the rx ring failed (%d)\n", 2853 error); 2854 xl_stop(sc); 2855 return; 2856 } 2857 2858 /* Init TX descriptors. */ 2859 if (sc->xl_type == XL_TYPE_905B) 2860 error = xl_list_tx_init_90xB(sc); 2861 else 2862 error = xl_list_tx_init(sc); 2863 if (error) { 2864 device_printf(sc->xl_dev, "initialization of the tx ring failed (%d)\n", 2865 error); 2866 xl_stop(sc); 2867 return; 2868 } 2869 2870 /* 2871 * Set the TX freethresh value. 2872 * Note that this has no effect on 3c905B "cyclone" 2873 * cards but is required for 3c900/3c905 "boomerang" 2874 * cards in order to enable the download engine. 2875 */ 2876 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8); 2877 2878 /* Set the TX start threshold for best performance. */ 2879 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_SET_START|sc->xl_tx_thresh); 2880 2881 /* 2882 * If this is a 3c905B, also set the tx reclaim threshold. 2883 * This helps cut down on the number of tx reclaim errors 2884 * that could happen on a busy network. The chip multiplies 2885 * the register value by 16 to obtain the actual threshold 2886 * in bytes, so we divide by 16 when setting the value here. 2887 * The existing threshold value can be examined by reading 2888 * the register at offset 9 in window 5. 2889 */ 2890 if (sc->xl_type == XL_TYPE_905B) { 2891 CSR_WRITE_2(sc, XL_COMMAND, 2892 XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4)); 2893 } 2894 2895 /* Set RX filter bits. */ 2896 xl_rxfilter(sc); 2897 2898 /* 2899 * Load the address of the RX list. We have to 2900 * stall the upload engine before we can manipulate 2901 * the uplist pointer register, then unstall it when 2902 * we're finished. We also have to wait for the 2903 * stall command to complete before proceeding. 2904 * Note that we have to do this after any RX resets 2905 * have completed since the uplist register is cleared 2906 * by a reset. 2907 */ 2908 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL); 2909 xl_wait(sc); 2910 CSR_WRITE_4(sc, XL_UPLIST_PTR, sc->xl_ldata.xl_rx_dmaaddr); 2911 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL); 2912 xl_wait(sc); 2913 2914 if (sc->xl_type == XL_TYPE_905B) { 2915 /* Set polling interval */ 2916 CSR_WRITE_1(sc, XL_DOWN_POLL, 64); 2917 /* Load the address of the TX list */ 2918 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL); 2919 xl_wait(sc); 2920 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2921 sc->xl_cdata.xl_tx_chain[0].xl_phys); 2922 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2923 xl_wait(sc); 2924 } 2925 2926 /* 2927 * If the coax transceiver is on, make sure to enable 2928 * the DC-DC converter. 2929 */ 2930 XL_SEL_WIN(3); 2931 if (sc->xl_xcvr == XL_XCVR_COAX) 2932 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START); 2933 else 2934 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 2935 2936 /* 2937 * increase packet size to allow reception of 802.1q or ISL packets. 2938 * For the 3c90x chip, set the 'allow large packets' bit in the MAC 2939 * control register. For 3c90xB/C chips, use the RX packet size 2940 * register. 2941 */ 2942 2943 if (sc->xl_type == XL_TYPE_905B) 2944 CSR_WRITE_2(sc, XL_W3_MAXPKTSIZE, XL_PACKET_SIZE); 2945 else { 2946 u_int8_t macctl; 2947 macctl = CSR_READ_1(sc, XL_W3_MAC_CTRL); 2948 macctl |= XL_MACCTRL_ALLOW_LARGE_PACK; 2949 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, macctl); 2950 } 2951 2952 /* Clear out the stats counters. */ 2953 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE); 2954 sc->xl_stats_no_timeout = 1; 2955 xl_stats_update_locked(sc); 2956 sc->xl_stats_no_timeout = 0; 2957 XL_SEL_WIN(4); 2958 CSR_WRITE_2(sc, XL_W4_NET_DIAG, XL_NETDIAG_UPPER_BYTES_ENABLE); 2959 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_ENABLE); 2960 2961 /* 2962 * Enable interrupts. 2963 */ 2964 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|0xFF); 2965 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|XL_INTRS); 2966#ifdef DEVICE_POLLING 2967 /* Disable interrupts if we are polling. */ 2968 if (ifp->if_capenable & IFCAP_POLLING) 2969 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0); 2970 else 2971#endif 2972 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|XL_INTRS); 2973 if (sc->xl_flags & XL_FLAG_FUNCREG) 2974 bus_space_write_4(sc->xl_ftag, sc->xl_fhandle, 4, 0x8000); 2975 2976 /* Set the RX early threshold */ 2977 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_THRESH|(XL_PACKET_SIZE >>2)); 2978 CSR_WRITE_2(sc, XL_DMACTL, XL_DMACTL_UP_RX_EARLY); 2979 2980 /* Enable receiver and transmitter. */ 2981 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE); 2982 xl_wait(sc); 2983 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_ENABLE); 2984 xl_wait(sc); 2985 2986 /* XXX Downcall to miibus. */ 2987 if (mii != NULL) 2988 mii_mediachg(mii); 2989 2990 /* Select window 7 for normal operations. */ 2991 XL_SEL_WIN(7); 2992 2993 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2994 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2995 2996 sc->xl_wdog_timer = 0; 2997 callout_reset(&sc->xl_stat_callout, hz, xl_stats_update, sc); 2998} 2999 3000/* 3001 * Set media options. 3002 */ 3003static int 3004xl_ifmedia_upd(struct ifnet *ifp) 3005{ 3006 struct xl_softc *sc = ifp->if_softc; 3007 struct ifmedia *ifm = NULL; 3008 struct mii_data *mii = NULL; 3009 3010 XL_LOCK(sc); 3011 3012 if (sc->xl_miibus != NULL) 3013 mii = device_get_softc(sc->xl_miibus); 3014 if (mii == NULL) 3015 ifm = &sc->ifmedia; 3016 else 3017 ifm = &mii->mii_media; 3018 3019 switch (IFM_SUBTYPE(ifm->ifm_media)) { 3020 case IFM_100_FX: 3021 case IFM_10_FL: 3022 case IFM_10_2: 3023 case IFM_10_5: 3024 xl_setmode(sc, ifm->ifm_media); 3025 XL_UNLOCK(sc); 3026 return (0); 3027 } 3028 3029 if (sc->xl_media & XL_MEDIAOPT_MII || 3030 sc->xl_media & XL_MEDIAOPT_BTX || 3031 sc->xl_media & XL_MEDIAOPT_BT4) { 3032 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3033 xl_init_locked(sc); 3034 } else { 3035 xl_setmode(sc, ifm->ifm_media); 3036 } 3037 3038 XL_UNLOCK(sc); 3039 3040 return (0); 3041} 3042 3043/* 3044 * Report current media status. 3045 */ 3046static void 3047xl_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 3048{ 3049 struct xl_softc *sc = ifp->if_softc; 3050 u_int32_t icfg; 3051 u_int16_t status = 0; 3052 struct mii_data *mii = NULL; 3053 3054 XL_LOCK(sc); 3055 3056 if (sc->xl_miibus != NULL) 3057 mii = device_get_softc(sc->xl_miibus); 3058 3059 XL_SEL_WIN(4); 3060 status = CSR_READ_2(sc, XL_W4_MEDIA_STATUS); 3061 3062 XL_SEL_WIN(3); 3063 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG) & XL_ICFG_CONNECTOR_MASK; 3064 icfg >>= XL_ICFG_CONNECTOR_BITS; 3065 3066 ifmr->ifm_active = IFM_ETHER; 3067 ifmr->ifm_status = IFM_AVALID; 3068 3069 if ((status & XL_MEDIASTAT_CARRIER) == 0) 3070 ifmr->ifm_status |= IFM_ACTIVE; 3071 3072 switch (icfg) { 3073 case XL_XCVR_10BT: 3074 ifmr->ifm_active = IFM_ETHER|IFM_10_T; 3075 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX) 3076 ifmr->ifm_active |= IFM_FDX; 3077 else 3078 ifmr->ifm_active |= IFM_HDX; 3079 break; 3080 case XL_XCVR_AUI: 3081 if (sc->xl_type == XL_TYPE_905B && 3082 sc->xl_media == XL_MEDIAOPT_10FL) { 3083 ifmr->ifm_active = IFM_ETHER|IFM_10_FL; 3084 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX) 3085 ifmr->ifm_active |= IFM_FDX; 3086 else 3087 ifmr->ifm_active |= IFM_HDX; 3088 } else 3089 ifmr->ifm_active = IFM_ETHER|IFM_10_5; 3090 break; 3091 case XL_XCVR_COAX: 3092 ifmr->ifm_active = IFM_ETHER|IFM_10_2; 3093 break; 3094 /* 3095 * XXX MII and BTX/AUTO should be separate cases. 3096 */ 3097 3098 case XL_XCVR_100BTX: 3099 case XL_XCVR_AUTO: 3100 case XL_XCVR_MII: 3101 if (mii != NULL) { 3102 mii_pollstat(mii); 3103 ifmr->ifm_active = mii->mii_media_active; 3104 ifmr->ifm_status = mii->mii_media_status; 3105 } 3106 break; 3107 case XL_XCVR_100BFX: 3108 ifmr->ifm_active = IFM_ETHER|IFM_100_FX; 3109 break; 3110 default: 3111 if_printf(ifp, "unknown XCVR type: %d\n", icfg); 3112 break; 3113 } 3114 3115 XL_UNLOCK(sc); 3116} 3117 3118static int 3119xl_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 3120{ 3121 struct xl_softc *sc = ifp->if_softc; 3122 struct ifreq *ifr = (struct ifreq *) data; 3123 int error = 0, mask; 3124 struct mii_data *mii = NULL; 3125 3126 switch (command) { 3127 case SIOCSIFFLAGS: 3128 XL_LOCK(sc); 3129 if (ifp->if_flags & IFF_UP) { 3130 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 3131 (ifp->if_flags ^ sc->xl_if_flags) & 3132 (IFF_PROMISC | IFF_ALLMULTI)) 3133 xl_rxfilter(sc); 3134 else 3135 xl_init_locked(sc); 3136 } else { 3137 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 3138 xl_stop(sc); 3139 } 3140 sc->xl_if_flags = ifp->if_flags; 3141 XL_UNLOCK(sc); 3142 break; 3143 case SIOCADDMULTI: 3144 case SIOCDELMULTI: 3145 /* XXX Downcall from if_addmulti() possibly with locks held. */ 3146 XL_LOCK(sc); 3147 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 3148 xl_rxfilter(sc); 3149 XL_UNLOCK(sc); 3150 break; 3151 case SIOCGIFMEDIA: 3152 case SIOCSIFMEDIA: 3153 if (sc->xl_miibus != NULL) 3154 mii = device_get_softc(sc->xl_miibus); 3155 if (mii == NULL) 3156 error = ifmedia_ioctl(ifp, ifr, 3157 &sc->ifmedia, command); 3158 else 3159 error = ifmedia_ioctl(ifp, ifr, 3160 &mii->mii_media, command); 3161 break; 3162 case SIOCSIFCAP: 3163 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 3164#ifdef DEVICE_POLLING 3165 if ((mask & IFCAP_POLLING) != 0 && 3166 (ifp->if_capabilities & IFCAP_POLLING) != 0) { 3167 ifp->if_capenable ^= IFCAP_POLLING; 3168 if ((ifp->if_capenable & IFCAP_POLLING) != 0) { 3169 error = ether_poll_register(xl_poll, ifp); 3170 if (error) 3171 break; 3172 XL_LOCK(sc); 3173 /* Disable interrupts */ 3174 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0); 3175 ifp->if_capenable |= IFCAP_POLLING; 3176 XL_UNLOCK(sc); 3177 } else { 3178 error = ether_poll_deregister(ifp); 3179 /* Enable interrupts. */ 3180 XL_LOCK(sc); 3181 CSR_WRITE_2(sc, XL_COMMAND, 3182 XL_CMD_INTR_ACK | 0xFF); 3183 CSR_WRITE_2(sc, XL_COMMAND, 3184 XL_CMD_INTR_ENB | XL_INTRS); 3185 if (sc->xl_flags & XL_FLAG_FUNCREG) 3186 bus_space_write_4(sc->xl_ftag, 3187 sc->xl_fhandle, 4, 0x8000); 3188 XL_UNLOCK(sc); 3189 } 3190 } 3191#endif /* DEVICE_POLLING */ 3192 XL_LOCK(sc); 3193 if ((mask & IFCAP_TXCSUM) != 0 && 3194 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 3195 ifp->if_capenable ^= IFCAP_TXCSUM; 3196 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 3197 ifp->if_hwassist |= XL905B_CSUM_FEATURES; 3198 else 3199 ifp->if_hwassist &= ~XL905B_CSUM_FEATURES; 3200 } 3201 if ((mask & IFCAP_RXCSUM) != 0 && 3202 (ifp->if_capabilities & IFCAP_RXCSUM) != 0) 3203 ifp->if_capenable ^= IFCAP_RXCSUM; 3204 if ((mask & IFCAP_WOL_MAGIC) != 0 && 3205 (ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0) 3206 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 3207 XL_UNLOCK(sc); 3208 break; 3209 default: 3210 error = ether_ioctl(ifp, command, data); 3211 break; 3212 } 3213 3214 return (error); 3215} 3216 3217static int 3218xl_watchdog(struct xl_softc *sc) 3219{ 3220 struct ifnet *ifp = sc->xl_ifp; 3221 u_int16_t status = 0; 3222 int misintr; 3223 3224 XL_LOCK_ASSERT(sc); 3225 3226 if (sc->xl_wdog_timer == 0 || --sc->xl_wdog_timer != 0) 3227 return (0); 3228 3229 xl_rxeof(sc); 3230 xl_txeoc(sc); 3231 misintr = 0; 3232 if (sc->xl_type == XL_TYPE_905B) { 3233 xl_txeof_90xB(sc); 3234 if (sc->xl_cdata.xl_tx_cnt == 0) 3235 misintr++; 3236 } else { 3237 xl_txeof(sc); 3238 if (sc->xl_cdata.xl_tx_head == NULL) 3239 misintr++; 3240 } 3241 if (misintr != 0) { 3242 device_printf(sc->xl_dev, 3243 "watchdog timeout (missed Tx interrupts) -- recovering\n"); 3244 return (0); 3245 } 3246 3247 ifp->if_oerrors++; 3248 XL_SEL_WIN(4); 3249 status = CSR_READ_2(sc, XL_W4_MEDIA_STATUS); 3250 device_printf(sc->xl_dev, "watchdog timeout\n"); 3251 3252 if (status & XL_MEDIASTAT_CARRIER) 3253 device_printf(sc->xl_dev, 3254 "no carrier - transceiver cable problem?\n"); 3255 3256 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3257 xl_init_locked(sc); 3258 3259 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 3260 if (sc->xl_type == XL_TYPE_905B) 3261 xl_start_90xB_locked(ifp); 3262 else 3263 xl_start_locked(ifp); 3264 } 3265 3266 return (EJUSTRETURN); 3267} 3268 3269/* 3270 * Stop the adapter and free any mbufs allocated to the 3271 * RX and TX lists. 3272 */ 3273static void 3274xl_stop(struct xl_softc *sc) 3275{ 3276 register int i; 3277 struct ifnet *ifp = sc->xl_ifp; 3278 3279 XL_LOCK_ASSERT(sc); 3280 3281 sc->xl_wdog_timer = 0; 3282 3283 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISABLE); 3284 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE); 3285 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB); 3286 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISCARD); 3287 xl_wait(sc); 3288 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_DISABLE); 3289 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 3290 DELAY(800); 3291 3292#ifdef foo 3293 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 3294 xl_wait(sc); 3295 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 3296 xl_wait(sc); 3297#endif 3298 3299 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|XL_STAT_INTLATCH); 3300 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|0); 3301 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0); 3302 if (sc->xl_flags & XL_FLAG_FUNCREG) 3303 bus_space_write_4(sc->xl_ftag, sc->xl_fhandle, 4, 0x8000); 3304 3305 /* Stop the stats updater. */ 3306 callout_stop(&sc->xl_stat_callout); 3307 3308 /* 3309 * Free data in the RX lists. 3310 */ 3311 for (i = 0; i < XL_RX_LIST_CNT; i++) { 3312 if (sc->xl_cdata.xl_rx_chain[i].xl_mbuf != NULL) { 3313 bus_dmamap_unload(sc->xl_mtag, 3314 sc->xl_cdata.xl_rx_chain[i].xl_map); 3315 bus_dmamap_destroy(sc->xl_mtag, 3316 sc->xl_cdata.xl_rx_chain[i].xl_map); 3317 m_freem(sc->xl_cdata.xl_rx_chain[i].xl_mbuf); 3318 sc->xl_cdata.xl_rx_chain[i].xl_mbuf = NULL; 3319 } 3320 } 3321 if (sc->xl_ldata.xl_rx_list != NULL) 3322 bzero(sc->xl_ldata.xl_rx_list, XL_RX_LIST_SZ); 3323 /* 3324 * Free the TX list buffers. 3325 */ 3326 for (i = 0; i < XL_TX_LIST_CNT; i++) { 3327 if (sc->xl_cdata.xl_tx_chain[i].xl_mbuf != NULL) { 3328 bus_dmamap_unload(sc->xl_mtag, 3329 sc->xl_cdata.xl_tx_chain[i].xl_map); 3330 bus_dmamap_destroy(sc->xl_mtag, 3331 sc->xl_cdata.xl_tx_chain[i].xl_map); 3332 m_freem(sc->xl_cdata.xl_tx_chain[i].xl_mbuf); 3333 sc->xl_cdata.xl_tx_chain[i].xl_mbuf = NULL; 3334 } 3335 } 3336 if (sc->xl_ldata.xl_tx_list != NULL) 3337 bzero(sc->xl_ldata.xl_tx_list, XL_TX_LIST_SZ); 3338 3339 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 3340} 3341 3342/* 3343 * Stop all chip I/O so that the kernel's probe routines don't 3344 * get confused by errant DMAs when rebooting. 3345 */ 3346static int 3347xl_shutdown(device_t dev) 3348{ 3349 3350 return (xl_suspend(dev)); 3351} 3352 3353static int 3354xl_suspend(device_t dev) 3355{ 3356 struct xl_softc *sc; 3357 3358 sc = device_get_softc(dev); 3359 3360 XL_LOCK(sc); 3361 xl_stop(sc); 3362 xl_setwol(sc); 3363 XL_UNLOCK(sc); 3364 3365 return (0); 3366} 3367 3368static int 3369xl_resume(device_t dev) 3370{ 3371 struct xl_softc *sc; 3372 struct ifnet *ifp; 3373 3374 sc = device_get_softc(dev); 3375 ifp = sc->xl_ifp; 3376 3377 XL_LOCK(sc); 3378 3379 if (ifp->if_flags & IFF_UP) { 3380 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3381 xl_init_locked(sc); 3382 } 3383 3384 XL_UNLOCK(sc); 3385 3386 return (0); 3387} 3388 3389static void 3390xl_setwol(struct xl_softc *sc) 3391{ 3392 struct ifnet *ifp; 3393 u_int16_t cfg, pmstat; 3394 3395 if ((sc->xl_flags & XL_FLAG_WOL) == 0) 3396 return; 3397 3398 ifp = sc->xl_ifp; 3399 XL_SEL_WIN(7); 3400 /* Clear any pending PME events. */ 3401 CSR_READ_2(sc, XL_W7_BM_PME); 3402 cfg = 0; 3403 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 3404 cfg |= XL_BM_PME_MAGIC; 3405 CSR_WRITE_2(sc, XL_W7_BM_PME, cfg); 3406 /* Enable RX. */ 3407 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 3408 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_ENABLE); 3409 /* Request PME. */ 3410 pmstat = pci_read_config(sc->xl_dev, 3411 sc->xl_pmcap + PCIR_POWER_STATUS, 2); 3412 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 3413 pmstat |= PCIM_PSTAT_PMEENABLE; 3414 else 3415 pmstat &= ~PCIM_PSTAT_PMEENABLE; 3416 pci_write_config(sc->xl_dev, 3417 sc->xl_pmcap + PCIR_POWER_STATUS, pmstat, 2); 3418} 3419