if_xereg.h revision 47136
147133Sobrien/*- 247133Sobrien * Copyright (c) 1998, 1999 Scott Mitchell 347133Sobrien * All rights reserved. 447133Sobrien * 547133Sobrien * Redistribution and use in source and binary forms, with or without 647133Sobrien * modification, are permitted provided that the following conditions 747133Sobrien * are met: 847133Sobrien * 1. Redistributions of source code must retain the above copyright 947133Sobrien * notice, this list of conditions and the following disclaimer. 1047133Sobrien * 2. Redistributions in binary form must reproduce the above copyright 1147133Sobrien * notice, this list of conditions and the following disclaimer in the 1247133Sobrien * documentation and/or other materials provided with the distribution. 1347133Sobrien * 1447133Sobrien * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 1547133Sobrien * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 1647133Sobrien * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 1747133Sobrien * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 1847133Sobrien * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 1947133Sobrien * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 2047133Sobrien * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2147133Sobrien * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 2247133Sobrien * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 2347133Sobrien * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 2447133Sobrien * SUCH DAMAGE. 2547133Sobrien * 2647136Sobrien * $Id: if_xereg.h,v 1.3 1999/02/22 14:00:53 root Exp $ 2747133Sobrien */ 2847133Sobrien 2947133Sobrien/* 3047133Sobrien * Register definitions for Xircom CreditCard Ethernet adapters. See if_xe.c 3147133Sobrien * for details of supported hardware. Adapted from Werner Koch's 'xirc2ps' 3247136Sobrien * driver for Linux and the FreeBSD 'xl' driver (for the MII support). 3347133Sobrien */ 3447133Sobrien 3547133Sobrien#include "xe.h" 3647133Sobrien#if NXE > 0 3747133Sobrien 3847133Sobrien 3947133Sobrien/* 4047133Sobrien * Common registers 4147133Sobrien */ 4247133Sobrien#define XE_CR 0 /* Command register (write) */ 4347133Sobrien#define XE_ESR 0 /* Ethernet status register (read) */ 4447133Sobrien#define XE_PSR 1 /* Page select register */ 4547133Sobrien#define XE_EDP 4 /* Ethernet data port */ 4647133Sobrien#define XE_ISR 6 /* Interrupt status register */ 4747133Sobrien 4847133Sobrien/* 4947133Sobrien * Command register values 5047133Sobrien */ 5147133Sobrien#define XE_CR_TX_PACKET 0x01 5247133Sobrien#define XE_CR_SOFT_RESET 0x02 5347133Sobrien#define XE_CR_ENABLE_INTR 0x04 5447133Sobrien#define XE_CR_FORCE_INTR 0x08 5547133Sobrien#define XE_CR_CLEAR_FIFO 0x10 5647133Sobrien#define XE_CR_CLEAR_OVERRUN 0x20 5747133Sobrien#define XE_CR_RESTART_TX 0x40 5847133Sobrien 5947133Sobrien/* 6047133Sobrien * Status register values 6147133Sobrien */ 6247133Sobrien#define XE_ESR_FULL_PKT_RX 0x01 6347133Sobrien#define XE_ESR_PKT_REJECT 0x04 6447133Sobrien#define XE_ESR_TX_PENDING 0x08 6547133Sobrien#define XE_ESR_BAD_POLARITY 0x10 6647133Sobrien#define XE_ESR_MEDIA_SELECT 0x20 6747133Sobrien 6847133Sobrien/* 6947133Sobrien * Interrupt register values 7047133Sobrien */ 7147133Sobrien#define XE_ISR_TX_OVERFLOW 0x01 7247133Sobrien#define XE_ISR_TX_PACKET 0x02 7347133Sobrien#define XE_ISR_MAC_INTR 0x04 7447133Sobrien#define XE_ISR_TX_RES 0x08 7547133Sobrien#define XE_ISR_RX_PACKET 0x20 7647133Sobrien#define XE_ISR_RX_REJECT 0x40 7747133Sobrien#define XE_ISR_FORCE_INTR 0x80 7847133Sobrien 7947133Sobrien 8047133Sobrien/* 8147133Sobrien * Page 0 registers 8247133Sobrien */ 8347133Sobrien#define XE_TSO 8 /* Transmit space open */ 8447133Sobrien#define XE_TRS 10 /* Transmit reservation size */ 8547133Sobrien#define XE_DOR 12 /* Data offset register (write) */ 8647133Sobrien#define XE_RSR 12 /* Receive status register (read) */ 8747133Sobrien#define XE_PTR 13 /* Packets transmitted register (read) */ 8847133Sobrien#define XE_RBC 14 /* Received byte count (read) */ 8947133Sobrien 9047133Sobrien/* 9147133Sobrien * RSR values 9247133Sobrien */ 9347133Sobrien#define XE_RSR_PHYS_PKT 0x01 9447133Sobrien#define XE_RSR_BCAST_PKT 0x02 9547133Sobrien#define XE_RSR_LONG_PKT 0x04 9647133Sobrien#define XE_RSR_ALIGN_ERR 0x10 9747133Sobrien#define XE_RSR_CRC_ERR 0x20 9847133Sobrien#define XE_RSR_RX_OK 0x80 9947133Sobrien 10047133Sobrien 10147133Sobrien/* 10247133Sobrien * Page 1 registers 10347133Sobrien */ 10447133Sobrien#define XE_IMR0 12 /* Interrupt mask register, part 1 */ 10547133Sobrien#define XE_IMR1 13 /* Interrupt mask register, part 2 */ 10647133Sobrien#define XE_ECR 14 /* Ethernet configuration register */ 10747133Sobrien 10847133Sobrien/* 10947133Sobrien * ECR values 11047133Sobrien */ 11147133Sobrien#define XE_ECR_FULL_DUPLEX 0x04 11247133Sobrien#define XE_ECR_LONG_TPCABLE 0x08 11347133Sobrien#define XE_ECR_NO_POLCOL 0x10 11447133Sobrien#define XE_ECR_NO_LINKPULSE 0x20 11547133Sobrien#define XE_ECR_NO_AUTOTX 0x40 11647133Sobrien 11747133Sobrien 11847133Sobrien/* 11947133Sobrien * Page 2 registers 12047133Sobrien */ 12147133Sobrien#define XE_RBS 8 /* Receive buffer start */ 12247133Sobrien#define XE_LED 10 /* LED configuration register */ 12347133Sobrien#define XE_MSR 12 /* Mohawk specfic register (Mohawk = CE3) */ 12447133Sobrien#define XE_GPR2 13 /* General purpose register 2 */ 12547133Sobrien 12647133Sobrien 12747133Sobrien/* 12847133Sobrien * Page 4 registers 12947133Sobrien */ 13047133Sobrien#define XE_GPR0 8 /* General purpose register 0 */ 13147133Sobrien#define XE_GPR1 9 /* General purpose register 1 */ 13247133Sobrien#define XE_BOV 10 /* Bonding version register */ 13347133Sobrien#define XE_LMA 12 /* Local memory address */ 13447133Sobrien#define XE_LMD 14 /* Local memory data */ 13547133Sobrien 13647133Sobrien 13747133Sobrien/* 13847133Sobrien * Page 5 registers 13947133Sobrien */ 14047133Sobrien#define XE_RHS 10 /* Receive host start address */ 14147133Sobrien 14247133Sobrien 14347133Sobrien/* 14447133Sobrien * Page 0x40 registers 14547133Sobrien */ 14647133Sobrien#define XE_OCR 8 /* The Other command register */ 14747133Sobrien#define XE_RXS0 9 /* Receive status 0 */ 14847133Sobrien#define XE_TXS0 11 /* Transmit status 0 */ 14947133Sobrien#define XE_TXS1 12 /* Transmit status 1 */ 15047133Sobrien#define XE_RXM0 13 /* Receive mask register 0 */ 15147133Sobrien#define XE_TXM0 14 /* Transmit mask register 0 */ 15247133Sobrien#define XE_TXM1 15 /* Transmit mask register 1 */ 15347133Sobrien 15447133Sobrien/* 15547133Sobrien * OCR values 15647133Sobrien */ 15747133Sobrien#define XE_OCR_TX 0x01 15847133Sobrien#define XE_OCR_RX_ENABLE 0x04 15947133Sobrien#define XE_OCR_RX_DISABLE 0x08 16047133Sobrien#define XE_OCR_ABORT 0x10 16147133Sobrien#define XE_OCR_ONLINE 0x20 16247133Sobrien#define XE_OCR_ACK_INTR 0x40 16347133Sobrien#define XE_OCR_OFFLINE 0x80 16447133Sobrien 16547133Sobrien 16647133Sobrien/* 16747133Sobrien * Page 0x42 registers 16847133Sobrien */ 16947133Sobrien#define XE_SWC0 8 /* Software configuration register 0 */ 17047133Sobrien#define XE_SWC1 9 /* Software configuration register 1 */ 17147133Sobrien#define XE_BOC 10 /* Back-off configuration */ 17247133Sobrien 17347133Sobrien 17447133Sobrien/* 17547133Sobrien * Page 0x44 registers 17647133Sobrien */ 17747133Sobrien#define XE_TDR0 8 /* Time domain reflectometry register 0 */ 17847133Sobrien#define XE_TDR1 9 /* Time domain reflectometry register 1 */ 17947133Sobrien#define XE_RXC0 10 /* Receive byte count low */ 18047133Sobrien#define XE_RXC1 11 /* Receive byte count high */ 18147133Sobrien 18247133Sobrien 18347133Sobrien/* 18447133Sobrien * Page 0x45 registers 18547133Sobrien */ 18647133Sobrien#define XE_REV 15 /* Revision (read) */ 18747133Sobrien 18847133Sobrien 18947133Sobrien/* 19047133Sobrien * Page 0x50 registers 19147133Sobrien */ 19247133Sobrien#define XE_IAR 8 /* Individual address register */ 19347133Sobrien 19447133Sobrien 19547133Sobrien/* 19647133Sobrien * Pages 0x43, 0x46-0x4f and 0x51-0x5e apparently don't exist. 19747133Sobrien * The remainder of 0x0-0x8 and 0x40-0x5f exist, but I have no 19847133Sobrien * idea what's on most of them. 19947133Sobrien */ 20047133Sobrien 20147133Sobrien 20247136Sobrien 20347133Sobrien/* 20447136Sobrien * Definitions for the Micro Linear ML6692 100Base-TX PHY, which handles the 20547136Sobrien * 100Mbit functionality of CE3 type cards, including media autonegotiation. 20647136Sobrien * It appears to be mostly compatible with the National Semiconductor 20747136Sobrien * DP83840A, but with a much smaller register set. Please refer to the data 20847136Sobrien * sheets for these devices for the definitive word on what all this stuff 20947136Sobrien * means :) 21047136Sobrien * 21147136Sobrien * Note that the ML6692 has no 10Mbit capability -- that is handled by another 21247136Sobrien * chip that we don't know anything about. 21347136Sobrien * 21447136Sobrien * Most of these definitions were adapted from the xl driver. 21547133Sobrien */ 21647136Sobrien 21747136Sobrien/* 21847136Sobrien * Masks for the MII-related bits in GPR2. For some reason read and write 21947136Sobrien * data are on separate bits. 22047136Sobrien */ 22147133Sobrien#define XE_MII_CLK 0x01 22247133Sobrien#define XE_MII_DIR 0x08 22347133Sobrien#define XE_MII_WRD 0x02 22447133Sobrien#define XE_MII_RDD 0x20 22547136Sobrien 22647136Sobrien/* 22747136Sobrien * MII command (etc) bit strings. 22847136Sobrien */ 22947133Sobrien#define XE_MII_STARTDELIM 0x01 23047133Sobrien#define XE_MII_READOP 0x02 23147133Sobrien#define XE_MII_WRITEOP 0x01 23247133Sobrien#define XE_MII_TURNAROUND 0x02 23347133Sobrien 23447136Sobrien/* 23547136Sobrien * PHY registers. 23647136Sobrien */ 23747136Sobrien#define PHY_BMCR 0x00 /* Basic Mode Control Register */ 23847136Sobrien#define PHY_BMSR 0x01 /* Basic Mode Status Register */ 23947136Sobrien#define PHY_ANAR 0x04 /* Auto-Negotiation Advertisment Register */ 24047136Sobrien#define PHY_LPAR 0x05 /* Auto-Negotiation Link Partner Ability Register */ 24147136Sobrien#define PHY_ANER 0x06 /* Auto-Negotiation Expansion Register */ 24247133Sobrien 24347136Sobrien#define PHY_BMCR_RESET 0x8000 /* Soft reset PHY. Self-clearing */ 24447136Sobrien#define PHY_BMCR_LOOPBK 0x4000 /* Enable loopback */ 24547136Sobrien#define PHY_BMCR_SPEEDSEL 0x2000 /* 1=100Mbps, 0=10Mbps */ 24647136Sobrien#define PHY_BMCR_AUTONEGENBL 0x1000 /* Auto-negotiation enabled */ 24747136Sobrien#define PHY_BMCR_ISOLATE 0x0400 /* Isolate ML6692 from MII */ 24847136Sobrien#define PHY_BMCR_AUTONEGRSTR 0x0200 /* Restart auto-negotiation. Self-clearing */ 24947136Sobrien#define PHY_BMCR_DUPLEX 0x0100 /* Full duplex operation */ 25047136Sobrien#define PHY_BMCR_COLLTEST 0x0080 /* Enable collision test */ 25147133Sobrien 25247136Sobrien#define PHY_BMSR_100BT4 0x8000 /* 100Base-T4 capable */ 25347136Sobrien#define PHY_BMSR_100BTXFULL 0x4000 /* 100Base-TX full duplex capable */ 25447136Sobrien#define PHY_BMSR_100BTXHALF 0x2000 /* 100Base-TX half duplex capable */ 25547136Sobrien#define PHY_BMSR_10BTFULL 0x1000 /* 10Base-T full duplex capable */ 25647136Sobrien#define PHY_BMSR_10BTHALF 0x0800 /* 10Base-T half duplex capable */ 25747136Sobrien#define PHY_BMSR_AUTONEGCOMP 0x0020 /* Auto-negotiation complete */ 25847136Sobrien#define PHY_BMSR_CANAUTONEG 0x0008 /* Auto-negotiation supported */ 25947136Sobrien#define PHY_BMSR_LINKSTAT 0x0004 /* Link is up */ 26047136Sobrien#define PHY_BMSR_EXTENDED 0x0001 /* Extended register capabilities */ 26147136Sobrien 26247136Sobrien#define PHY_ANAR_NEXTPAGE 0x8000 /* Additional link code word pages */ 26347136Sobrien#define PHY_ANAR_TLRFLT 0x2000 /* Remote wire fault detected */ 26447136Sobrien#define PHY_ANAR_100BT4 0x0200 /* 100Base-T4 capable */ 26547136Sobrien#define PHY_ANAR_100BTXFULL 0x0100 /* 100Base-TX full duplex capable */ 26647136Sobrien#define PHY_ANAR_100BTXHALF 0x0080 /* 100Base-TX half duplex capable */ 26747136Sobrien#define PHY_ANAR_10BTFULL 0x0040 /* 10Base-T full duplex capable */ 26847136Sobrien#define PHY_ANAR_10BTHALF 0x0020 /* 10Base-T half duplex capable */ 26947136Sobrien#define PHY_ANAR_PROTO4 0x0010 /* Protocol selection (00001 = 802.3) */ 27047133Sobrien#define PHY_ANAR_PROTO3 0x0008 27147133Sobrien#define PHY_ANAR_PROTO2 0x0004 27247133Sobrien#define PHY_ANAR_PROTO1 0x0002 27347133Sobrien#define PHY_ANAR_PROTO0 0x0001 27447133Sobrien 27547136Sobrien#define PHY_LPAR_NEXTPAGE 0x8000 /* Additional link code word pages */ 27647136Sobrien#define PHY_LPAR_LPACK 0x4000 /* Link partner acknowledged receipt */ 27747136Sobrien#define PHY_LPAR_TLRFLT 0x2000 /* Remote wire fault detected */ 27847136Sobrien#define PHY_LPAR_100BT4 0x0200 /* 100Base-T4 capable */ 27947136Sobrien#define PHY_LPAR_100BTXFULL 0x0100 /* 100Base-TX full duplex capable */ 28047136Sobrien#define PHY_LPAR_100BTXHALF 0x0080 /* 100Base-TX half duplex capable */ 28147136Sobrien#define PHY_LPAR_10BTFULL 0x0040 /* 10Base-T full duplex capable */ 28247136Sobrien#define PHY_LPAR_10BTHALF 0x0020 /* 10Base-T half duplex capable */ 28347136Sobrien#define PHY_LPAR_PROTO4 0x0010 /* Protocol selection (00001 = 802.3) */ 28447136Sobrien#define PHY_LPAR_PROTO3 0x0008 28547136Sobrien#define PHY_LPAR_PROTO2 0x0004 28647136Sobrien#define PHY_LPAR_PROTO1 0x0002 28747136Sobrien#define PHY_LPAR_PROTO0 0x0001 28847133Sobrien 28947136Sobrien#define PHY_ANER_MLFAULT 0x0010 /* More than one link is up! */ 29047136Sobrien#define PHY_ANER_LPNPABLE 0x0008 /* Link partner supports next page */ 29147136Sobrien#define PHY_ANER_NPABLE 0x0004 /* Local port supports next page */ 29247136Sobrien#define PHY_ANER_PAGERX 0x0002 /* Page received */ 29347136Sobrien#define PHY_ANER_LPAUTONEG 0x0001 /* Link partner can auto-negotiate */ 29447133Sobrien 29547133Sobrien 29647133Sobrien#endif /* NXE > 0 */ 297