1221167Sgnn/*- 2221167Sgnn * Copyright(c) 2002-2011 Exar Corp. 3221167Sgnn * All rights reserved. 4221167Sgnn * 5221167Sgnn * Redistribution and use in source and binary forms, with or without 6221167Sgnn * modification are permitted provided the following conditions are met: 7221167Sgnn * 8221167Sgnn * 1. Redistributions of source code must retain the above copyright notice, 9221167Sgnn * this list of conditions and the following disclaimer. 10221167Sgnn * 11221167Sgnn * 2. Redistributions in binary form must reproduce the above copyright 12221167Sgnn * notice, this list of conditions and the following disclaimer in the 13221167Sgnn * documentation and/or other materials provided with the distribution. 14221167Sgnn * 15221167Sgnn * 3. Neither the name of the Exar Corporation nor the names of its 16221167Sgnn * contributors may be used to endorse or promote products derived from 17221167Sgnn * this software without specific prior written permission. 18221167Sgnn * 19221167Sgnn * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20221167Sgnn * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21221167Sgnn * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22221167Sgnn * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 23221167Sgnn * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24221167Sgnn * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25221167Sgnn * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26221167Sgnn * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27221167Sgnn * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28221167Sgnn * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29221167Sgnn * POSSIBILITY OF SUCH DAMAGE. 30221167Sgnn */ 31221167Sgnn/*$FreeBSD$*/ 32221167Sgnn 33221167Sgnn#include <dev/vxge/vxgehal/vxgehal.h> 34221167Sgnn 35221167Sgnn/* 36221167Sgnn * __hal_srpcim_alarm_process - Process Alarms. 37221167Sgnn * @hldev: HAL Device 38221167Sgnn * @srpcim_id: srpcim index 39221167Sgnn * @skip_alarms: Flag to indicate if not to clear the alarms 40221167Sgnn * 41221167Sgnn * Process srpcim alarms. 42221167Sgnn * 43221167Sgnn */ 44221167Sgnnvxge_hal_status_e 45221167Sgnn__hal_srpcim_alarm_process( 46221167Sgnn __hal_device_t * hldev, 47221167Sgnn u32 srpcim_id, 48221167Sgnn u32 skip_alarms) 49221167Sgnn{ 50221167Sgnn u64 val64; 51221167Sgnn u64 alarm_status; 52221167Sgnn u64 pic_status; 53221167Sgnn u64 xgmac_status; 54221167Sgnn vxge_hal_srpcim_reg_t *srpcim_reg; 55221167Sgnn 56221167Sgnn vxge_assert(hldev != NULL); 57221167Sgnn 58221167Sgnn vxge_hal_trace_log_srpcim_irq("==> %s:%s:%d", 59221167Sgnn __FILE__, __func__, __LINE__); 60221167Sgnn 61221167Sgnn vxge_hal_trace_log_srpcim_irq("hldev = 0x"VXGE_OS_STXFMT, 62221167Sgnn (ptr_t) hldev); 63221167Sgnn 64221167Sgnn srpcim_reg = hldev->srpcim_reg[srpcim_id]; 65221167Sgnn 66221167Sgnn alarm_status = vxge_os_pio_mem_read64(hldev->header.pdev, 67221167Sgnn hldev->header.regh0, 68221167Sgnn &srpcim_reg->srpcim_general_int_status); 69221167Sgnn 70221167Sgnn vxge_hal_info_log_srpcim_irq("alarm_status = 0x"VXGE_OS_STXFMT, 71221167Sgnn (ptr_t) alarm_status); 72221167Sgnn 73221167Sgnn if (alarm_status & VXGE_HAL_SRPCIM_GENERAL_INT_STATUS_XMAC_INT) { 74221167Sgnn 75221167Sgnn xgmac_status = vxge_os_pio_mem_read64(hldev->header.pdev, 76221167Sgnn hldev->header.regh0, 77221167Sgnn &srpcim_reg->xgmac_sr_int_status); 78221167Sgnn 79221167Sgnn vxge_hal_info_log_srpcim_irq("xgmac_status = 0x"VXGE_OS_STXFMT, 80221167Sgnn (ptr_t) xgmac_status); 81221167Sgnn 82221167Sgnn if (xgmac_status & 83221167Sgnn VXGE_HAL_XGMAC_SR_INT_STATUS_ASIC_NTWK_SR_ERR_INT) { 84221167Sgnn 85221167Sgnn val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 86221167Sgnn hldev->header.regh0, 87221167Sgnn &srpcim_reg->asic_ntwk_sr_err_reg); 88221167Sgnn 89221167Sgnn vxge_hal_info_log_srpcim_irq("asic_ntwk_sr_err_reg = \ 90221167Sgnn 0x"VXGE_OS_STXFMT, (ptr_t) val64); 91221167Sgnn 92221167Sgnn if (!skip_alarms) 93221167Sgnn vxge_os_pio_mem_write64(hldev->header.pdev, 94221167Sgnn hldev->header.regh0, 95221167Sgnn VXGE_HAL_INTR_MASK_ALL, 96221167Sgnn &srpcim_reg->asic_ntwk_sr_err_reg); 97221167Sgnn 98221167Sgnn } 99221167Sgnn } 100221167Sgnn 101221167Sgnn if (alarm_status & VXGE_HAL_SRPCIM_GENERAL_INT_STATUS_PIC_INT) { 102221167Sgnn 103221167Sgnn pic_status = vxge_os_pio_mem_read64(hldev->header.pdev, 104221167Sgnn hldev->header.regh0, 105221167Sgnn &srpcim_reg->srpcim_ppif_int_status); 106221167Sgnn 107221167Sgnn vxge_hal_info_log_srpcim_irq("pic_status = 0x"VXGE_OS_STXFMT, 108221167Sgnn (ptr_t) pic_status); 109221167Sgnn 110221167Sgnn if (pic_status & 111221167Sgnn VXGE_HAL_SRPCIM_PPIF_INT_STATUS_SRPCIM_GEN_ERRORS_INT) { 112221167Sgnn 113221167Sgnn val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 114221167Sgnn hldev->header.regh0, 115221167Sgnn &srpcim_reg->srpcim_gen_errors_reg); 116221167Sgnn 117221167Sgnn vxge_hal_info_log_srpcim_irq("srpcim_gen_errors_reg = \ 118221167Sgnn 0x"VXGE_OS_STXFMT, (ptr_t) val64); 119221167Sgnn 120221167Sgnn if (!skip_alarms) 121221167Sgnn vxge_os_pio_mem_write64(hldev->header.pdev, 122221167Sgnn hldev->header.regh0, 123221167Sgnn VXGE_HAL_INTR_MASK_ALL, 124221167Sgnn &srpcim_reg->srpcim_gen_errors_reg); 125221167Sgnn } 126221167Sgnn 127221167Sgnn if (pic_status & 128221167Sgnn VXGE_HAL_SRPCIM_PPIF_INT_STATUS_MRPCIM_TO_SRPCIM_ALARM) { 129221167Sgnn 130221167Sgnn val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 131221167Sgnn hldev->header.regh0, 132221167Sgnn &srpcim_reg->mrpcim_to_srpcim_alarm_reg); 133221167Sgnn 134221167Sgnn vxge_hal_info_log_srpcim_irq("mrpcim_to_srpcim_alarm_reg = \ 135221167Sgnn 0x"VXGE_OS_STXFMT, (ptr_t) val64); 136221167Sgnn 137221167Sgnn if (!skip_alarms) 138221167Sgnn vxge_os_pio_mem_write64(hldev->header.pdev, 139221167Sgnn hldev->header.regh0, 140221167Sgnn VXGE_HAL_INTR_MASK_ALL, 141221167Sgnn &srpcim_reg->mrpcim_to_srpcim_alarm_reg); 142221167Sgnn 143221167Sgnn } 144221167Sgnn } 145221167Sgnn 146221167Sgnn if (alarm_status & ~( 147221167Sgnn VXGE_HAL_SRPCIM_GENERAL_INT_STATUS_PIC_INT | 148221167Sgnn VXGE_HAL_SRPCIM_GENERAL_INT_STATUS_XMAC_INT)) { 149221167Sgnn vxge_hal_trace_log_srpcim_irq("%s:%s:%d Unknown Alarm", 150221167Sgnn __FILE__, __func__, __LINE__); 151221167Sgnn } 152221167Sgnn 153221167Sgnn vxge_hal_trace_log_srpcim_irq("<== %s:%s:%d Result = 0", 154221167Sgnn __FILE__, __func__, __LINE__); 155221167Sgnn 156221167Sgnn return (VXGE_HAL_OK); 157221167Sgnn} 158221167Sgnn 159221167Sgnn/* 160221167Sgnn * vxge_hal_srpcim_alarm_process - Process srpcim Alarms. 161221167Sgnn * @devh: Device Handle. 162221167Sgnn * @skip_alarms: Flag to indicate if not to clear the alarms 163221167Sgnn * 164221167Sgnn * Process srpcim alarms. 165221167Sgnn * 166221167Sgnn */ 167221167Sgnnvxge_hal_status_e 168221167Sgnnvxge_hal_srpcim_alarm_process( 169221167Sgnn vxge_hal_device_h devh, 170221167Sgnn u32 skip_alarms) 171221167Sgnn{ 172221167Sgnn u32 i; 173221167Sgnn u64 val64; 174221167Sgnn vxge_hal_status_e status = VXGE_HAL_OK; 175221167Sgnn __hal_device_t *hldev = (__hal_device_t *) devh; 176221167Sgnn 177221167Sgnn vxge_assert(devh != NULL); 178221167Sgnn 179221167Sgnn vxge_hal_trace_log_srpcim_irq("==> %s:%s:%d", 180221167Sgnn __FILE__, __func__, __LINE__); 181221167Sgnn 182221167Sgnn vxge_hal_trace_log_srpcim_irq("devh = 0x"VXGE_OS_STXFMT, 183221167Sgnn (ptr_t) devh); 184221167Sgnn 185221167Sgnn if (!(hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_SRPCIM)) { 186221167Sgnn vxge_hal_trace_log_srpcim_irq("<== %s:%s:%d Result = %d", 187221167Sgnn __FILE__, __func__, __LINE__, 188221167Sgnn VXGE_HAL_ERR_PRIVILAGED_OPEARATION); 189221167Sgnn 190221167Sgnn return (VXGE_HAL_ERR_PRIVILAGED_OPEARATION); 191221167Sgnn 192221167Sgnn } 193221167Sgnn 194221167Sgnn if (hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM) { 195221167Sgnn 196221167Sgnn val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 197221167Sgnn hldev->header.regh0, 198221167Sgnn &hldev->mrpcim_reg->srpcim_to_mrpcim_alarm_reg); 199221167Sgnn 200221167Sgnn vxge_hal_trace_log_srpcim_irq("srpcim_to_mrpcim_alarm_reg = \ 201221167Sgnn 0x"VXGE_OS_STXFMT, (ptr_t) val64); 202221167Sgnn 203221167Sgnn for (i = 0; i < VXGE_HAL_TITAN_SRPCIM_REG_SPACES; i++) { 204221167Sgnn 205221167Sgnn if (val64 & mBIT(i)) { 206221167Sgnn status = __hal_srpcim_alarm_process(hldev, 207221167Sgnn i, skip_alarms); 208221167Sgnn } 209221167Sgnn } 210221167Sgnn 211221167Sgnn if (!skip_alarms) 212221167Sgnn vxge_os_pio_mem_write64(hldev->header.pdev, 213221167Sgnn hldev->header.regh0, 214221167Sgnn VXGE_HAL_INTR_MASK_ALL, 215221167Sgnn &hldev->mrpcim_reg->srpcim_to_mrpcim_alarm_reg); 216221167Sgnn } else { 217221167Sgnn status = __hal_srpcim_alarm_process(hldev, 218221167Sgnn hldev->srpcim_id, skip_alarms); 219221167Sgnn } 220221167Sgnn 221221167Sgnn vxge_hal_trace_log_srpcim_irq("<== %s:%s:%d Result = %d", 222221167Sgnn __FILE__, __func__, __LINE__, status); 223221167Sgnn 224221167Sgnn return (status); 225221167Sgnn} 226221167Sgnn 227221167Sgnn/* 228221167Sgnn * __hal_srpcim_intr_enable - Enable srpcim interrupts. 229221167Sgnn * @hldev: Hal Device. 230221167Sgnn * @srpcim_id: SRPCIM Id 231221167Sgnn * 232221167Sgnn * Enable srpcim interrupts. 233221167Sgnn * 234221167Sgnn * See also: __hal_srpcim_intr_disable() 235221167Sgnn */ 236221167Sgnnvxge_hal_status_e 237221167Sgnn__hal_srpcim_intr_enable( 238221167Sgnn __hal_device_t * hldev, 239221167Sgnn u32 srpcim_id) 240221167Sgnn{ 241221167Sgnn vxge_hal_srpcim_reg_t *srpcim_reg; 242221167Sgnn 243221167Sgnn vxge_assert(hldev != NULL); 244221167Sgnn 245221167Sgnn vxge_hal_trace_log_srpcim("==> %s:%s:%d", 246221167Sgnn __FILE__, __func__, __LINE__); 247221167Sgnn 248221167Sgnn vxge_hal_trace_log_srpcim("hldev = 0x"VXGE_OS_STXFMT, 249221167Sgnn (ptr_t) hldev); 250221167Sgnn 251221167Sgnn srpcim_reg = hldev->srpcim_reg[srpcim_id]; 252221167Sgnn 253221167Sgnn vxge_os_pio_mem_write64(hldev->header.pdev, 254221167Sgnn hldev->header.regh0, 255221167Sgnn VXGE_HAL_INTR_MASK_ALL, 256221167Sgnn &srpcim_reg->srpcim_gen_errors_reg); 257221167Sgnn 258221167Sgnn vxge_hal_pio_mem_write32_upper(hldev->header.pdev, 259221167Sgnn hldev->header.regh0, 260221167Sgnn (u32) VXGE_HAL_INTR_MASK_ALL, 261221167Sgnn &srpcim_reg->mrpcim_to_srpcim_alarm_reg); 262221167Sgnn 263221167Sgnn vxge_hal_pio_mem_write32_upper(hldev->header.pdev, 264221167Sgnn hldev->header.regh0, 265221167Sgnn (u32) VXGE_HAL_INTR_MASK_ALL, 266221167Sgnn &srpcim_reg->vpath_to_srpcim_alarm_reg); 267221167Sgnn 268221167Sgnn vxge_hal_pio_mem_write32_upper(hldev->header.pdev, 269221167Sgnn hldev->header.regh0, 270221167Sgnn (u32) VXGE_HAL_INTR_MASK_ALL, 271221167Sgnn &srpcim_reg->srpcim_ppif_int_status); 272221167Sgnn 273221167Sgnn vxge_hal_pio_mem_write32_upper(hldev->header.pdev, 274221167Sgnn hldev->header.regh0, 275221167Sgnn (u32) VXGE_HAL_INTR_MASK_ALL, 276221167Sgnn &srpcim_reg->mrpcim_msg_reg); 277221167Sgnn 278221167Sgnn vxge_hal_pio_mem_write32_upper(hldev->header.pdev, 279221167Sgnn hldev->header.regh0, 280221167Sgnn (u32) VXGE_HAL_INTR_MASK_ALL, 281221167Sgnn &srpcim_reg->vpath_msg_reg); 282221167Sgnn 283221167Sgnn vxge_hal_pio_mem_write32_upper(hldev->header.pdev, 284221167Sgnn hldev->header.regh0, 285221167Sgnn (u32) VXGE_HAL_INTR_MASK_ALL, 286221167Sgnn &srpcim_reg->srpcim_pcipif_int_status); 287221167Sgnn 288221167Sgnn vxge_hal_pio_mem_write32_upper(hldev->header.pdev, 289221167Sgnn hldev->header.regh0, 290221167Sgnn (u32) VXGE_HAL_INTR_MASK_ALL, 291221167Sgnn &srpcim_reg->asic_ntwk_sr_err_reg); 292221167Sgnn 293221167Sgnn vxge_hal_pio_mem_write32_upper(hldev->header.pdev, 294221167Sgnn hldev->header.regh0, 295221167Sgnn (u32) VXGE_HAL_INTR_MASK_ALL, 296221167Sgnn &srpcim_reg->xgmac_sr_int_status); 297221167Sgnn 298221167Sgnn vxge_os_pio_mem_read64(hldev->header.pdev, 299221167Sgnn hldev->header.regh0, 300221167Sgnn &srpcim_reg->srpcim_general_int_status); 301221167Sgnn 302221167Sgnn /* Unmask the individual interrupts. */ 303221167Sgnn vxge_hal_pio_mem_write32_upper(hldev->header.pdev, 304221167Sgnn hldev->header.regh0, 305221167Sgnn 0, 306221167Sgnn &srpcim_reg->vpath_msg_mask); 307221167Sgnn 308221167Sgnn vxge_hal_pio_mem_write32_upper(hldev->header.pdev, 309221167Sgnn hldev->header.regh0, 310221167Sgnn 0, 311221167Sgnn &srpcim_reg->srpcim_pcipif_int_mask); 312221167Sgnn 313221167Sgnn vxge_hal_pio_mem_write32_upper(hldev->header.pdev, 314221167Sgnn hldev->header.regh0, 315221167Sgnn (u32) bVAL32(~VXGE_HAL_SRPCIM_GENERAL_INT_MASK_PCI_INT, 0), 316221167Sgnn &srpcim_reg->srpcim_general_int_mask); 317221167Sgnn 318221167Sgnn vxge_hal_trace_log_srpcim("<== %s:%s:%d Result = 0", 319221167Sgnn __FILE__, __func__, __LINE__); 320221167Sgnn 321221167Sgnn return (VXGE_HAL_OK); 322221167Sgnn} 323221167Sgnn 324221167Sgnn/* 325221167Sgnn * vxge_hal_srpcim_intr_enable - Enable srpcim interrupts. 326221167Sgnn * @devh: Hal Device. 327221167Sgnn * 328221167Sgnn * Enable srpcim interrupts. 329221167Sgnn * 330221167Sgnn * See also: vxge_hal_srpcim_intr_disable() 331221167Sgnn */ 332221167Sgnnvxge_hal_status_e 333221167Sgnnvxge_hal_srpcim_intr_enable( 334221167Sgnn vxge_hal_device_h devh) 335221167Sgnn{ 336221167Sgnn u32 i; 337221167Sgnn vxge_hal_status_e status; 338221167Sgnn __hal_device_t *hldev = (__hal_device_t *) devh; 339221167Sgnn 340221167Sgnn vxge_assert(devh != NULL); 341221167Sgnn 342221167Sgnn vxge_hal_trace_log_srpcim("==> %s:%s:%d", 343221167Sgnn __FILE__, __func__, __LINE__); 344221167Sgnn 345221167Sgnn vxge_hal_trace_log_srpcim("devh = 0x"VXGE_OS_STXFMT, 346221167Sgnn (ptr_t) devh); 347221167Sgnn 348221167Sgnn if (!(hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_SRPCIM)) { 349221167Sgnn vxge_hal_trace_log_srpcim("<== %s:%s:%d Result = %d", 350221167Sgnn __FILE__, __func__, __LINE__, 351221167Sgnn VXGE_HAL_ERR_PRIVILAGED_OPEARATION); 352221167Sgnn 353221167Sgnn return (VXGE_HAL_ERR_PRIVILAGED_OPEARATION); 354221167Sgnn 355221167Sgnn } 356221167Sgnn 357221167Sgnn if (hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM) { 358221167Sgnn 359221167Sgnn for (i = 0; i < VXGE_HAL_TITAN_SRPCIM_REG_SPACES; i++) { 360221167Sgnn 361221167Sgnn status = __hal_srpcim_intr_enable(hldev, i); 362221167Sgnn 363221167Sgnn } 364221167Sgnn 365221167Sgnn } else { 366221167Sgnn status = __hal_srpcim_intr_enable(hldev, hldev->srpcim_id); 367221167Sgnn } 368221167Sgnn 369221167Sgnn vxge_hal_trace_log_srpcim("<== %s:%s:%d Result = %d", 370221167Sgnn __FILE__, __func__, __LINE__, status); 371221167Sgnn 372221167Sgnn return (status); 373221167Sgnn} 374221167Sgnn 375221167Sgnn/* 376221167Sgnn * __hal_srpcim_intr_disable - Disable srpcim interrupts. 377221167Sgnn * @hldev: Hal Device. 378221167Sgnn * @srpcim_id: SRPCIM Id 379221167Sgnn * 380221167Sgnn * Disable srpcim interrupts. 381221167Sgnn * 382221167Sgnn * See also: __hal_srpcim_intr_enable() 383221167Sgnn */ 384221167Sgnnvxge_hal_status_e 385221167Sgnn__hal_srpcim_intr_disable( 386221167Sgnn __hal_device_t * hldev, 387221167Sgnn u32 srpcim_id) 388221167Sgnn{ 389221167Sgnn vxge_hal_srpcim_reg_t *srpcim_reg; 390221167Sgnn 391221167Sgnn vxge_assert(hldev != NULL); 392221167Sgnn 393221167Sgnn vxge_hal_trace_log_srpcim("==> %s:%s:%d", 394221167Sgnn __FILE__, __func__, __LINE__); 395221167Sgnn 396221167Sgnn vxge_hal_trace_log_srpcim("hldev = 0x"VXGE_OS_STXFMT, 397221167Sgnn (ptr_t) hldev); 398221167Sgnn 399221167Sgnn srpcim_reg = hldev->srpcim_reg[srpcim_id]; 400221167Sgnn 401221167Sgnn /* Mask the individual interrupts. */ 402221167Sgnn vxge_hal_pio_mem_write32_upper(hldev->header.pdev, 403221167Sgnn hldev->header.regh0, 404221167Sgnn (u32) VXGE_HAL_INTR_MASK_ALL, 405221167Sgnn &srpcim_reg->vpath_msg_mask); 406221167Sgnn 407221167Sgnn vxge_hal_pio_mem_write32_upper(hldev->header.pdev, 408221167Sgnn hldev->header.regh0, 409221167Sgnn (u32) VXGE_HAL_INTR_MASK_ALL, 410221167Sgnn &srpcim_reg->srpcim_pcipif_int_mask); 411221167Sgnn 412221167Sgnn vxge_hal_pio_mem_write32_upper( 413221167Sgnn hldev->header.pdev, 414221167Sgnn hldev->header.regh0, 415221167Sgnn (u32) VXGE_HAL_INTR_MASK_ALL, 416221167Sgnn &srpcim_reg->srpcim_general_int_mask); 417221167Sgnn 418221167Sgnn vxge_hal_trace_log_srpcim("<== %s:%s:%d Result = 0", 419221167Sgnn __FILE__, __func__, __LINE__); 420221167Sgnn 421221167Sgnn return (VXGE_HAL_OK); 422221167Sgnn 423221167Sgnn} 424221167Sgnn 425221167Sgnn/* 426221167Sgnn * vxge_hal_srpcim_intr_disable - Disable srpcim interrupts. 427221167Sgnn * @devh: Hal Device. 428221167Sgnn * 429221167Sgnn * Disable srpcim interrupts. 430221167Sgnn * 431221167Sgnn * See also: vxge_hal_srpcim_intr_enable() 432221167Sgnn */ 433221167Sgnnvxge_hal_status_e 434221167Sgnnvxge_hal_srpcim_intr_disable( 435221167Sgnn vxge_hal_device_h devh) 436221167Sgnn{ 437221167Sgnn u32 i; 438221167Sgnn vxge_hal_status_e status; 439221167Sgnn __hal_device_t *hldev = (__hal_device_t *) devh; 440221167Sgnn 441221167Sgnn vxge_assert(devh != NULL); 442221167Sgnn 443221167Sgnn vxge_hal_trace_log_srpcim("==> %s:%s:%d", 444221167Sgnn __FILE__, __func__, __LINE__); 445221167Sgnn 446221167Sgnn vxge_hal_trace_log_srpcim("devh = 0x"VXGE_OS_STXFMT, 447221167Sgnn (ptr_t) devh); 448221167Sgnn 449221167Sgnn if (!(hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_SRPCIM)) { 450221167Sgnn vxge_hal_trace_log_srpcim("<== %s:%s:%d Result = %d", 451221167Sgnn __FILE__, __func__, __LINE__, 452221167Sgnn VXGE_HAL_ERR_PRIVILAGED_OPEARATION); 453221167Sgnn 454221167Sgnn return (VXGE_HAL_ERR_PRIVILAGED_OPEARATION); 455221167Sgnn 456221167Sgnn } 457221167Sgnn 458221167Sgnn if (hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM) { 459221167Sgnn 460221167Sgnn for (i = 0; i < VXGE_HAL_TITAN_SRPCIM_REG_SPACES; i++) { 461221167Sgnn 462221167Sgnn status = __hal_srpcim_intr_disable(hldev, i); 463221167Sgnn 464221167Sgnn } 465221167Sgnn 466221167Sgnn } else { 467221167Sgnn status = __hal_srpcim_intr_disable(hldev, hldev->srpcim_id); 468221167Sgnn } 469221167Sgnn 470221167Sgnn vxge_hal_trace_log_srpcim("<== %s:%s:%d Result = %d", 471221167Sgnn __FILE__, __func__, __LINE__, status); 472221167Sgnn 473221167Sgnn return (status); 474221167Sgnn} 475221167Sgnn 476221167Sgnn/* 477221167Sgnn * vxge_hal_srpcim_msix_set - Associate MSIX vector with srpcim alarm 478221167Sgnn * @hldev: HAL device. 479221167Sgnn * @alarm_msix_id: MSIX vector for alarm. 480221167Sgnn * 481221167Sgnn * This API will associate a given MSIX vector numbers with srpcim alarm 482221167Sgnn */ 483221167Sgnnvxge_hal_status_e 484221167Sgnnvxge_hal_srpcim_msix_set(vxge_hal_device_h devh, int alarm_msix_id) 485221167Sgnn{ 486221167Sgnn u32 i; 487221167Sgnn vxge_hal_status_e status = VXGE_HAL_OK; 488221167Sgnn __hal_device_t *hldev = (__hal_device_t *) devh; 489221167Sgnn 490221167Sgnn vxge_assert(devh != NULL); 491221167Sgnn 492221167Sgnn vxge_hal_trace_log_srpcim("==> %s:%s:%d", 493221167Sgnn __FILE__, __func__, __LINE__); 494221167Sgnn 495221167Sgnn vxge_hal_trace_log_srpcim("devh = 0x"VXGE_OS_STXFMT, 496221167Sgnn (ptr_t) devh); 497221167Sgnn 498221167Sgnn if (!(hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_SRPCIM)) { 499221167Sgnn vxge_hal_trace_log_srpcim("<== %s:%s:%d Result = %d", 500221167Sgnn __FILE__, __func__, __LINE__, 501221167Sgnn VXGE_HAL_ERR_PRIVILAGED_OPEARATION); 502221167Sgnn 503221167Sgnn return (VXGE_HAL_ERR_PRIVILAGED_OPEARATION); 504221167Sgnn 505221167Sgnn } 506221167Sgnn 507221167Sgnn if (hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM) { 508221167Sgnn 509221167Sgnn for (i = 0; i < VXGE_HAL_TITAN_SRPCIM_REG_SPACES; i++) { 510221167Sgnn 511221167Sgnn vxge_hal_pio_mem_write32_upper(hldev->header.pdev, 512221167Sgnn hldev->header.regh0, 513221167Sgnn (u32) bVAL32( 514221167Sgnn VXGE_HAL_SRPCIM_INTERRUPT_CFG1_ALARM_MAP_TO_MSG( 515221167Sgnn alarm_msix_id), 516221167Sgnn 0), 517221167Sgnn &hldev->srpcim_reg[i]->srpcim_interrupt_cfg1); 518221167Sgnn 519221167Sgnn } 520221167Sgnn 521221167Sgnn } else { 522221167Sgnn vxge_hal_pio_mem_write32_upper(hldev->header.pdev, 523221167Sgnn hldev->header.regh0, 524221167Sgnn (u32) bVAL32( 525221167Sgnn VXGE_HAL_SRPCIM_INTERRUPT_CFG1_ALARM_MAP_TO_MSG( 526221167Sgnn alarm_msix_id), 527221167Sgnn 0), 528221167Sgnn &hldev->srpcim_reg[hldev->srpcim_id]-> 529221167Sgnn srpcim_interrupt_cfg1); 530221167Sgnn } 531221167Sgnn 532221167Sgnn vxge_hal_trace_log_srpcim("<== %s:%s:%d Result = %d", 533221167Sgnn __FILE__, __func__, __LINE__, status); 534221167Sgnn 535221167Sgnn return (status); 536221167Sgnn} 537221167Sgnn 538221167Sgnn/* 539221167Sgnn * vxge_hal_srpcim_msix_mask - Mask MSIX Vector. 540221167Sgnn * @hldev: HAL device. 541221167Sgnn * 542221167Sgnn * The function masks the srpcim msix interrupt 543221167Sgnn * 544221167Sgnn */ 545221167Sgnnvoid 546221167Sgnnvxge_hal_srpcim_msix_mask(vxge_hal_device_h devh) 547221167Sgnn{ 548221167Sgnn u32 i; 549221167Sgnn __hal_device_t *hldev = (__hal_device_t *) devh; 550221167Sgnn 551221167Sgnn vxge_assert(devh != NULL); 552221167Sgnn 553221167Sgnn vxge_hal_trace_log_srpcim("==> %s:%s:%d", 554221167Sgnn __FILE__, __func__, __LINE__); 555221167Sgnn 556221167Sgnn vxge_hal_trace_log_srpcim("devh = 0x"VXGE_OS_STXFMT, 557221167Sgnn (ptr_t) devh); 558221167Sgnn 559221167Sgnn if (!(hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_SRPCIM)) { 560221167Sgnn vxge_hal_trace_log_srpcim("<== %s:%s:%d Result = %d", 561221167Sgnn __FILE__, __func__, __LINE__, 562221167Sgnn VXGE_HAL_ERR_PRIVILAGED_OPEARATION); 563221167Sgnn 564221167Sgnn return; 565221167Sgnn 566221167Sgnn } 567221167Sgnn 568221167Sgnn if (hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM) { 569221167Sgnn 570221167Sgnn for (i = 0; i < VXGE_HAL_TITAN_SRPCIM_REG_SPACES; i++) { 571221167Sgnn 572221167Sgnn vxge_hal_pio_mem_write32_upper(hldev->header.pdev, 573221167Sgnn hldev->header.regh0, 574221167Sgnn (u32) bVAL32( 575221167Sgnn VXGE_HAL_SRPCIM_SET_MSIX_MASK_SRPCIM_SET_MSIX_MASK, 576221167Sgnn 0), 577221167Sgnn &hldev->srpcim_reg[i]->srpcim_set_msix_mask); 578221167Sgnn 579221167Sgnn } 580221167Sgnn 581221167Sgnn } else { 582221167Sgnn vxge_hal_pio_mem_write32_upper(hldev->header.pdev, 583221167Sgnn hldev->header.regh0, 584221167Sgnn (u32) bVAL32( 585221167Sgnn VXGE_HAL_SRPCIM_SET_MSIX_MASK_SRPCIM_SET_MSIX_MASK, 586221167Sgnn 0), 587221167Sgnn &hldev->srpcim_reg[hldev->srpcim_id]->srpcim_set_msix_mask); 588221167Sgnn } 589221167Sgnn 590221167Sgnn vxge_hal_trace_log_srpcim("<== %s:%s:%d Result = 0", 591221167Sgnn __FILE__, __func__, __LINE__); 592221167Sgnn} 593221167Sgnn 594221167Sgnn/* 595221167Sgnn * vxge_hal_srpcim_msix_clear - Clear MSIX Vector. 596221167Sgnn * @hldev: HAL device. 597221167Sgnn * 598221167Sgnn * The function clears the srpcim msix interrupt 599221167Sgnn * 600221167Sgnn */ 601221167Sgnnvoid 602221167Sgnnvxge_hal_srpcim_msix_clear(vxge_hal_device_h devh) 603221167Sgnn{ 604221167Sgnn u32 i; 605221167Sgnn __hal_device_t *hldev = (__hal_device_t *) devh; 606221167Sgnn 607221167Sgnn vxge_assert(devh != NULL); 608221167Sgnn 609221167Sgnn vxge_hal_trace_log_srpcim("==> %s:%s:%d", 610221167Sgnn __FILE__, __func__, __LINE__); 611221167Sgnn 612221167Sgnn vxge_hal_trace_log_srpcim("devh = 0x"VXGE_OS_STXFMT, 613221167Sgnn (ptr_t) devh); 614221167Sgnn 615221167Sgnn if (!(hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_SRPCIM)) { 616221167Sgnn vxge_hal_trace_log_srpcim("<== %s:%s:%d Result = %d", 617221167Sgnn __FILE__, __func__, __LINE__, 618221167Sgnn VXGE_HAL_ERR_PRIVILAGED_OPEARATION); 619221167Sgnn 620221167Sgnn return; 621221167Sgnn 622221167Sgnn } 623221167Sgnn 624221167Sgnn if (hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM) { 625221167Sgnn 626221167Sgnn for (i = 0; i < VXGE_HAL_TITAN_SRPCIM_REG_SPACES; i++) { 627221167Sgnn 628221167Sgnn vxge_hal_pio_mem_write32_upper(hldev->header.pdev, 629221167Sgnn hldev->header.regh0, 630221167Sgnn (u32) bVAL32( 631221167Sgnn VXGE_HAL_SRPCIM_CLEAR_MSIX_MASK_SRPCIM_CLEAR_MSIX_MASK, 632221167Sgnn 0), 633221167Sgnn &hldev->srpcim_reg[i]->srpcim_clear_msix_mask); 634221167Sgnn 635221167Sgnn } 636221167Sgnn 637221167Sgnn } else { 638221167Sgnn vxge_hal_pio_mem_write32_upper(hldev->header.pdev, 639221167Sgnn hldev->header.regh0, 640221167Sgnn (u32) bVAL32( 641221167Sgnn VXGE_HAL_SRPCIM_CLEAR_MSIX_MASK_SRPCIM_CLEAR_MSIX_MASK, 642221167Sgnn 0), 643221167Sgnn &hldev->srpcim_reg[hldev->srpcim_id]-> 644221167Sgnn srpcim_clear_msix_mask); 645221167Sgnn } 646221167Sgnn 647221167Sgnn vxge_hal_trace_log_srpcim("<== %s:%s:%d Result = 0", 648221167Sgnn __FILE__, __func__, __LINE__); 649221167Sgnn} 650221167Sgnn 651221167Sgnn/* 652221167Sgnn * vxge_hal_srpcim_msix_unmask - Unmask MSIX Vector. 653221167Sgnn * @hldev: HAL device. 654221167Sgnn * 655221167Sgnn * The function unmasks the srpcim msix interrupt 656221167Sgnn * 657221167Sgnn */ 658221167Sgnnvoid 659221167Sgnnvxge_hal_srpcim_msix_unmask(vxge_hal_device_h devh) 660221167Sgnn{ 661221167Sgnn u32 i; 662221167Sgnn __hal_device_t *hldev = (__hal_device_t *) devh; 663221167Sgnn 664221167Sgnn vxge_assert(devh != NULL); 665221167Sgnn 666221167Sgnn vxge_hal_trace_log_srpcim("==> %s:%s:%d", 667221167Sgnn __FILE__, __func__, __LINE__); 668221167Sgnn 669221167Sgnn vxge_hal_trace_log_srpcim("devh = 0x"VXGE_OS_STXFMT, 670221167Sgnn (ptr_t) devh); 671221167Sgnn 672221167Sgnn if (!(hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_SRPCIM)) { 673221167Sgnn vxge_hal_trace_log_srpcim("<== %s:%s:%d Result = %d", 674221167Sgnn __FILE__, __func__, __LINE__, 675221167Sgnn VXGE_HAL_ERR_PRIVILAGED_OPEARATION); 676221167Sgnn 677221167Sgnn return; 678221167Sgnn 679221167Sgnn } 680221167Sgnn 681221167Sgnn if (hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM) { 682221167Sgnn 683221167Sgnn for (i = 0; i < VXGE_HAL_TITAN_SRPCIM_REG_SPACES; i++) { 684221167Sgnn 685221167Sgnn vxge_hal_pio_mem_write32_upper(hldev->header.pdev, 686221167Sgnn hldev->header.regh0, 687221167Sgnn (u32) bVAL32( 688221167Sgnn VXGE_HAL_SRPCIM_CLR_MSIX_ONE_SHOT_SRPCIM_CLR_MSIX_ONE_SHOT, 689221167Sgnn 0), 690221167Sgnn &hldev->srpcim_reg[i]->srpcim_clr_msix_one_shot); 691221167Sgnn 692221167Sgnn } 693221167Sgnn 694221167Sgnn } else { 695221167Sgnn vxge_hal_pio_mem_write32_upper(hldev->header.pdev, 696221167Sgnn hldev->header.regh0, 697221167Sgnn (u32) bVAL32( 698221167Sgnn VXGE_HAL_SRPCIM_CLR_MSIX_ONE_SHOT_SRPCIM_CLR_MSIX_ONE_SHOT, 699221167Sgnn 0), 700221167Sgnn &hldev->srpcim_reg[hldev->srpcim_id]-> 701221167Sgnn srpcim_clr_msix_one_shot); 702221167Sgnn } 703221167Sgnn 704221167Sgnn vxge_hal_trace_log_srpcim("<== %s:%s:%d Result = 0", 705221167Sgnn __FILE__, __func__, __LINE__); 706221167Sgnn} 707221167Sgnn 708221167Sgnn/* 709221167Sgnn * __hal_srpcim_initialize - Initialize srpcim. 710221167Sgnn * @hldev: HAL Device 711221167Sgnn * 712221167Sgnn * Initialize srpcim. 713221167Sgnn * 714221167Sgnn */ 715221167Sgnnvxge_hal_status_e 716221167Sgnn__hal_srpcim_initialize( 717221167Sgnn __hal_device_t * hldev) 718221167Sgnn{ 719221167Sgnn vxge_assert(hldev != NULL); 720221167Sgnn 721221167Sgnn vxge_hal_trace_log_srpcim("==> %s:%s:%d", 722221167Sgnn __FILE__, __func__, __LINE__); 723221167Sgnn 724221167Sgnn vxge_hal_trace_log_srpcim("hldev = 0x"VXGE_OS_STXFMT, 725221167Sgnn (ptr_t) hldev); 726221167Sgnn 727221167Sgnn if (!(hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_SRPCIM)) { 728221167Sgnn vxge_hal_trace_log_srpcim("<== %s:%s:%d Result = %d", 729221167Sgnn __FILE__, __func__, __LINE__, 730221167Sgnn VXGE_HAL_ERR_PRIVILAGED_OPEARATION); 731221167Sgnn return (VXGE_HAL_ERR_PRIVILAGED_OPEARATION); 732221167Sgnn } 733221167Sgnn 734221167Sgnn hldev->srpcim = (__hal_srpcim_t *) 735221167Sgnn vxge_os_malloc(hldev->header.pdev, sizeof(__hal_srpcim_t)); 736221167Sgnn 737221167Sgnn if (hldev->srpcim == NULL) { 738221167Sgnn vxge_hal_trace_log_srpcim("<== %s:%s:%d Result = %d", 739221167Sgnn __FILE__, __func__, __LINE__, VXGE_HAL_ERR_OUT_OF_MEMORY); 740221167Sgnn return (VXGE_HAL_ERR_OUT_OF_MEMORY); 741221167Sgnn } 742221167Sgnn 743221167Sgnn vxge_os_memzero(hldev->srpcim, sizeof(__hal_srpcim_t)); 744221167Sgnn 745221167Sgnn vxge_hal_trace_log_srpcim("<== %s:%s:%d Result = 0", 746221167Sgnn __FILE__, __func__, __LINE__); 747221167Sgnn 748221167Sgnn return (VXGE_HAL_OK); 749221167Sgnn} 750221167Sgnn 751221167Sgnn/* 752221167Sgnn * __hal_srpcim_terminate - Terminate srpcim. 753221167Sgnn * @hldev: HAL Device 754221167Sgnn * 755221167Sgnn * Terminate srpcim. 756221167Sgnn * 757221167Sgnn */ 758221167Sgnnvxge_hal_status_e 759221167Sgnn__hal_srpcim_terminate( 760221167Sgnn __hal_device_t * hldev) 761221167Sgnn{ 762221167Sgnn vxge_hal_status_e status = VXGE_HAL_OK; 763221167Sgnn 764221167Sgnn vxge_assert(hldev != NULL); 765221167Sgnn 766221167Sgnn vxge_hal_trace_log_srpcim("==> %s:%s:%d", 767221167Sgnn __FILE__, __func__, __LINE__); 768221167Sgnn 769221167Sgnn vxge_hal_trace_log_srpcim("hldev = 0x"VXGE_OS_STXFMT, 770221167Sgnn (ptr_t) hldev); 771221167Sgnn 772221167Sgnn if (hldev->srpcim == NULL) { 773221167Sgnn vxge_hal_trace_log_srpcim("<== %s:%s:%d Result = %d", 774221167Sgnn __FILE__, __func__, __LINE__, status); 775221167Sgnn return (status); 776221167Sgnn } 777221167Sgnn 778221167Sgnn vxge_os_free(hldev->header.pdev, 779221167Sgnn hldev->srpcim, sizeof(__hal_srpcim_t)); 780221167Sgnn 781221167Sgnn hldev->srpcim = NULL; 782221167Sgnn 783221167Sgnn vxge_hal_trace_log_srpcim("<== %s:%s:%d Result = 0", 784221167Sgnn __FILE__, __func__, __LINE__); 785221167Sgnn 786221167Sgnn return (VXGE_HAL_OK); 787221167Sgnn} 788