1221167Sgnn/*- 2221167Sgnn * Copyright(c) 2002-2011 Exar Corp. 3221167Sgnn * All rights reserved. 4221167Sgnn * 5221167Sgnn * Redistribution and use in source and binary forms, with or without 6221167Sgnn * modification are permitted provided the following conditions are met: 7221167Sgnn * 8221167Sgnn * 1. Redistributions of source code must retain the above copyright notice, 9221167Sgnn * this list of conditions and the following disclaimer. 10221167Sgnn * 11221167Sgnn * 2. Redistributions in binary form must reproduce the above copyright 12221167Sgnn * notice, this list of conditions and the following disclaimer in the 13221167Sgnn * documentation and/or other materials provided with the distribution. 14221167Sgnn * 15221167Sgnn * 3. Neither the name of the Exar Corporation nor the names of its 16221167Sgnn * contributors may be used to endorse or promote products derived from 17221167Sgnn * this software without specific prior written permission. 18221167Sgnn * 19221167Sgnn * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20221167Sgnn * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21221167Sgnn * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22221167Sgnn * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 23221167Sgnn * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24221167Sgnn * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25221167Sgnn * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26221167Sgnn * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27221167Sgnn * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28221167Sgnn * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29221167Sgnn * POSSIBILITY OF SUCH DAMAGE. 30221167Sgnn */ 31221167Sgnn/*$FreeBSD$*/ 32221167Sgnn 33221167Sgnn#include <dev/vxge/vxgehal/vxgehal.h> 34221167Sgnn 35221167Sgnn/* 36221167Sgnn * vxge_hal_mrpcim_serial_number_get - Returns the serial number 37221167Sgnn * @devh: HAL device handle. 38221167Sgnn * 39221167Sgnn * Return the serial number 40221167Sgnn */ 41221167Sgnnconst u8 * 42221167Sgnnvxge_hal_mrpcim_serial_number_get(vxge_hal_device_h devh) 43221167Sgnn{ 44221167Sgnn __hal_device_t *hldev = (__hal_device_t *) devh; 45221167Sgnn 46221167Sgnn vxge_assert(devh); 47221167Sgnn 48221167Sgnn vxge_hal_trace_log_mrpcim("==> %s:%s:%d", 49221167Sgnn __FILE__, __func__, __LINE__); 50221167Sgnn 51221167Sgnn vxge_hal_trace_log_mrpcim("devh = 0x"VXGE_OS_STXFMT, 52221167Sgnn (ptr_t) devh); 53221167Sgnn 54221167Sgnn if (!(hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM)) { 55221167Sgnn vxge_hal_trace_log_stats("<== %s:%s:%d Result = %d", 56221167Sgnn __FILE__, __func__, __LINE__, 57221167Sgnn VXGE_HAL_ERR_PRIVILAGED_OPEARATION); 58221167Sgnn 59221167Sgnn return (NULL); 60221167Sgnn } 61221167Sgnn 62221167Sgnn vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = 0", 63221167Sgnn __FILE__, __func__, __LINE__); 64221167Sgnn 65221167Sgnn return (hldev->mrpcim->vpd_data.serial_num); 66221167Sgnn} 67221167Sgnn 68221167Sgnn/* 69221167Sgnn * vxge_hal_mrpcim_vpath_map_get - Returns the assigned vpaths map 70221167Sgnn * @pdev: PCI device object. 71221167Sgnn * @regh0: BAR0 mapped memory handle (Solaris), or simply PCI device @pdev 72221167Sgnn * (Linux and the rest.) 73221167Sgnn * @bar0: Address of BAR0 in PCI config 74221167Sgnn * @func: Function Number 75221167Sgnn * 76221167Sgnn * Returns the assigned vpaths map 77221167Sgnn */ 78221167Sgnnu64 79221167Sgnnvxge_hal_mrpcim_vpath_map_get( 80221167Sgnn pci_dev_h pdev, 81221167Sgnn pci_reg_h regh0, 82221167Sgnn u8 *bar0, 83221167Sgnn u32 func) 84221167Sgnn{ 85221167Sgnn u64 val64; 86221167Sgnn vxge_hal_legacy_reg_t *legacy_reg; 87221167Sgnn vxge_hal_toc_reg_t *toc_reg; 88221167Sgnn vxge_hal_vpath_reg_t *vpath_reg; 89221167Sgnn 90221167Sgnn vxge_assert(bar0 != NULL); 91221167Sgnn 92221167Sgnn vxge_hal_trace_log_driver("==> %s:%s:%d", 93221167Sgnn __FILE__, __func__, __LINE__); 94221167Sgnn 95221167Sgnn vxge_hal_trace_log_driver( 96221167Sgnn "pdev = 0x"VXGE_OS_STXFMT", regh0 = 0x"VXGE_OS_STXFMT", " 97221167Sgnn "bar0 = 0x"VXGE_OS_STXFMT", func = %d", 98221167Sgnn (ptr_t) pdev, (ptr_t) regh0, (ptr_t) bar0, func); 99221167Sgnn 100221167Sgnn legacy_reg = (vxge_hal_legacy_reg_t *) 101221167Sgnn vxge_hal_device_get_legacy_reg(pdev, regh0, bar0); 102221167Sgnn 103221167Sgnn val64 = vxge_os_pio_mem_read64(pdev, regh0, 104221167Sgnn &legacy_reg->toc_first_pointer); 105221167Sgnn 106221167Sgnn toc_reg = (vxge_hal_toc_reg_t *) ((void *)(bar0 + val64)); 107221167Sgnn 108221167Sgnn val64 = vxge_os_pio_mem_read64(pdev, regh0, 109221167Sgnn &toc_reg->toc_vpath_pointer[0]); 110221167Sgnn 111221167Sgnn vpath_reg = (vxge_hal_vpath_reg_t *) ((void *)(bar0 + val64)); 112221167Sgnn 113221167Sgnn val64 = __hal_vpath_vpath_map_get(pdev, regh0, 0, 0, func, vpath_reg); 114221167Sgnn 115221167Sgnn vxge_hal_trace_log_driver("<== %s:%s:%d Result = 0", 116221167Sgnn __FILE__, __func__, __LINE__); 117221167Sgnn 118221167Sgnn return (val64); 119221167Sgnn} 120221167Sgnn 121221167Sgnn/* 122221167Sgnn * vxge_hal_mrpcim_pcie_func_mode_set - Set PCI-E function mode 123221167Sgnn * @devh: Device Handle. 124221167Sgnn * @func_mode: PCI-E func mode. Please see vxge_hal_pcie_function_mode_e{} 125221167Sgnn * 126221167Sgnn * Set PCI-E function mode. 127221167Sgnn * 128221167Sgnn */ 129221167Sgnnvxge_hal_status_e 130221167Sgnnvxge_hal_mrpcim_pcie_func_mode_set( 131221167Sgnn vxge_hal_device_h devh, 132221167Sgnn vxge_hal_pcie_function_mode_e func_mode) 133221167Sgnn{ 134221167Sgnn __hal_device_t *hldev = (__hal_device_t *) devh; 135221167Sgnn u32 fmode; 136221167Sgnn vxge_hal_status_e status; 137221167Sgnn 138221167Sgnn vxge_assert(hldev != NULL); 139221167Sgnn 140221167Sgnn vxge_hal_trace_log_mrpcim("==> %s:%s:%d", 141221167Sgnn __FILE__, __func__, __LINE__); 142221167Sgnn 143221167Sgnn vxge_hal_trace_log_driver("devh = 0x"VXGE_OS_STXFMT 144221167Sgnn ",func_mode = %d", (ptr_t) devh, func_mode); 145221167Sgnn 146221167Sgnn if (!(hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM)) { 147221167Sgnn vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = %d", 148221167Sgnn __FILE__, __func__, __LINE__, 149221167Sgnn VXGE_HAL_ERR_PRIVILAGED_OPEARATION); 150221167Sgnn 151221167Sgnn return (VXGE_HAL_ERR_PRIVILAGED_OPEARATION); 152221167Sgnn } 153221167Sgnn 154221167Sgnn switch (func_mode) { 155221167Sgnn case VXGE_HAL_PCIE_FUNC_MODE_SF1_VP17: 156221167Sgnn fmode = 157221167Sgnn VXGE_HAL_RTS_ACCESS_STEER_DATA0_FUNC_MODE_SF1_VP17; 158221167Sgnn break; 159221167Sgnn case VXGE_HAL_PCIE_FUNC_MODE_MF8_VP2: 160221167Sgnn fmode = 161221167Sgnn VXGE_HAL_RTS_ACCESS_STEER_DATA0_FUNC_MODE_MF8_VP2; 162221167Sgnn break; 163221167Sgnn case VXGE_HAL_PCIE_FUNC_MODE_SR17_VP1: 164221167Sgnn fmode = 165221167Sgnn VXGE_HAL_RTS_ACCESS_STEER_DATA0_FUNC_MODE_SR17_VP1; 166221167Sgnn break; 167221167Sgnn case VXGE_HAL_PCIE_FUNC_MODE_MR17_VP1: 168221167Sgnn fmode = 169221167Sgnn VXGE_HAL_RTS_ACCESS_STEER_DATA0_FUNC_MODE_MR17_VP1; 170221167Sgnn break; 171221167Sgnn case VXGE_HAL_PCIE_FUNC_MODE_MR8_VP2: 172221167Sgnn fmode = 173221167Sgnn VXGE_HAL_RTS_ACCESS_STEER_DATA0_FUNC_MODE_MR8_VP2; 174221167Sgnn break; 175221167Sgnn case VXGE_HAL_PCIE_FUNC_MODE_MF17_VP1: 176221167Sgnn fmode = 177221167Sgnn VXGE_HAL_RTS_ACCESS_STEER_DATA0_FUNC_MODE_MF17_VP1; 178221167Sgnn break; 179221167Sgnn case VXGE_HAL_PCIE_FUNC_MODE_SR8_VP2: 180221167Sgnn fmode = 181221167Sgnn VXGE_HAL_RTS_ACCESS_STEER_DATA0_FUNC_MODE_SR8_VP2; 182221167Sgnn break; 183221167Sgnn case VXGE_HAL_PCIE_FUNC_MODE_SR4_VP4: 184221167Sgnn fmode = 185221167Sgnn VXGE_HAL_RTS_ACCESS_STEER_DATA0_FUNC_MODE_SR4_VP4; 186221167Sgnn break; 187221167Sgnn case VXGE_HAL_PCIE_FUNC_MODE_MF2_VP8: 188221167Sgnn fmode = 189221167Sgnn VXGE_HAL_RTS_ACCESS_STEER_DATA0_FUNC_MODE_MF2_VP8; 190221167Sgnn break; 191221167Sgnn case VXGE_HAL_PCIE_FUNC_MODE_MF4_VP4: 192221167Sgnn fmode = 193221167Sgnn VXGE_HAL_RTS_ACCESS_STEER_DATA0_FUNC_MODE_MF4_VP4; 194221167Sgnn break; 195221167Sgnn case VXGE_HAL_PCIE_FUNC_MODE_MR4_VP4: 196221167Sgnn fmode = 197221167Sgnn VXGE_HAL_RTS_ACCESS_STEER_DATA0_FUNC_MODE_MR4_VP4; 198221167Sgnn break; 199221167Sgnn case VXGE_HAL_PCIE_FUNC_MODE_MF8P_VP2: 200221167Sgnn fmode = 201221167Sgnn VXGE_HAL_RTS_ACCESS_STEER_DATA0_FUNC_MODE_MF8P_VP2; 202221167Sgnn break; 203221167Sgnn default: 204221167Sgnn vxge_hal_trace_log_driver("<== %s:%s:%d Result = %d", 205221167Sgnn __FILE__, __func__, __LINE__, 206221167Sgnn VXGE_HAL_ERR_INVALID_TYPE); 207221167Sgnn 208221167Sgnn return (VXGE_HAL_ERR_INVALID_TYPE); 209221167Sgnn } 210221167Sgnn 211221167Sgnn status = __hal_vpath_pcie_func_mode_set(hldev, hldev->first_vp_id, fmode); 212221167Sgnn 213221167Sgnn vxge_hal_trace_log_driver("<== %s:%s:%d Result = 0", 214221167Sgnn __FILE__, __func__, __LINE__); 215221167Sgnn 216221167Sgnn return (status); 217221167Sgnn 218221167Sgnn} 219221167Sgnn 220221167Sgnn/* 221221167Sgnn * vxge_hal_mrpcim_fw_upgrade - Upgrade firmware 222221167Sgnn * @pdev: PCI device object. 223221167Sgnn * @regh0: BAR0 mapped memory handle (Solaris), or simply PCI device @pdev 224221167Sgnn * (Linux and the rest.) 225221167Sgnn * @bar0: Address of BAR0 in PCI config 226221167Sgnn * @buffer: Buffer containing F/W image 227221167Sgnn * @length: F/W image length 228221167Sgnn * 229221167Sgnn * Upgrade firmware 230221167Sgnn */ 231221167Sgnnvxge_hal_status_e 232221167Sgnnvxge_hal_mrpcim_fw_upgrade( 233221167Sgnn pci_dev_h pdev, 234221167Sgnn pci_reg_h regh0, 235221167Sgnn u8 *bar0, 236221167Sgnn u8 *buffer, 237221167Sgnn u32 length) 238221167Sgnn{ 239221167Sgnn u64 val64, vpath_mask; 240221167Sgnn u32 host_type, func_id, i; 241221167Sgnn vxge_hal_legacy_reg_t *legacy_reg; 242221167Sgnn vxge_hal_toc_reg_t *toc_reg; 243221167Sgnn vxge_hal_mrpcim_reg_t *mrpcim_reg; 244221167Sgnn vxge_hal_common_reg_t *common_reg; 245221167Sgnn vxge_hal_vpmgmt_reg_t *vpmgmt_reg; 246221167Sgnn vxge_hal_vpath_reg_t *vpath_reg; 247221167Sgnn vxge_hal_status_e status = VXGE_HAL_OK; 248221167Sgnn 249221167Sgnn vxge_assert((bar0 != NULL) && (buffer != NULL)); 250221167Sgnn 251221167Sgnn vxge_hal_trace_log_driver("==> %s:%s:%d", 252221167Sgnn __FILE__, __func__, __LINE__); 253221167Sgnn 254221167Sgnn vxge_hal_trace_log_driver( 255221167Sgnn "pdev = 0x"VXGE_OS_STXFMT", regh0 = 0x"VXGE_OS_STXFMT", " 256221167Sgnn "bar0 = 0x"VXGE_OS_STXFMT", buffer = 0x"VXGE_OS_STXFMT", " 257221167Sgnn "length = %d", (ptr_t) pdev, (ptr_t) regh0, (ptr_t) bar0, 258221167Sgnn (ptr_t) buffer, length); 259221167Sgnn 260221167Sgnn legacy_reg = (vxge_hal_legacy_reg_t *) 261221167Sgnn vxge_hal_device_get_legacy_reg(pdev, regh0, bar0); 262221167Sgnn 263221167Sgnn val64 = vxge_os_pio_mem_read64(pdev, regh0, 264221167Sgnn &legacy_reg->toc_first_pointer); 265221167Sgnn 266221167Sgnn toc_reg = (vxge_hal_toc_reg_t *) ((void *)(bar0 + val64)); 267221167Sgnn 268221167Sgnn val64 = 269221167Sgnn vxge_os_pio_mem_read64(pdev, regh0, &toc_reg->toc_common_pointer); 270221167Sgnn 271221167Sgnn common_reg = (vxge_hal_common_reg_t *) ((void *)(bar0 + val64)); 272221167Sgnn 273221167Sgnn vpath_mask = vxge_os_pio_mem_read64(pdev, regh0, 274221167Sgnn &common_reg->vpath_assignments); 275221167Sgnn 276221167Sgnn val64 = vxge_os_pio_mem_read64(pdev, regh0, 277221167Sgnn &common_reg->host_type_assignments); 278221167Sgnn 279221167Sgnn host_type = (u32) 280221167Sgnn VXGE_HAL_HOST_TYPE_ASSIGNMENTS_GET_HOST_TYPE_ASSIGNMENTS(val64); 281221167Sgnn 282221167Sgnn for (i = 0; i < VXGE_HAL_MAX_VIRTUAL_PATHS; i++) { 283221167Sgnn 284221167Sgnn if (!((vpath_mask) & mBIT(i))) 285221167Sgnn continue; 286221167Sgnn 287221167Sgnn val64 = vxge_os_pio_mem_read64(pdev, regh0, 288221167Sgnn &toc_reg->toc_vpmgmt_pointer[i]); 289221167Sgnn 290221167Sgnn vpmgmt_reg = (vxge_hal_vpmgmt_reg_t *) ((void *)(bar0 + val64)); 291221167Sgnn 292221167Sgnn val64 = vxge_os_pio_mem_read64(pdev, regh0, 293221167Sgnn &vpmgmt_reg->vpath_to_func_map_cfg1); 294221167Sgnn 295221167Sgnn func_id = (u32) VXGE_HAL_VPATH_TO_FUNC_MAP_CFG1_GET_CFG1(val64); 296221167Sgnn 297221167Sgnn if (!(__hal_device_access_rights_get(host_type, func_id) & 298221167Sgnn VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM)) { 299221167Sgnn 300221167Sgnn vxge_hal_trace_log_driver("<== %s:%s:%d Result = %d", 301221167Sgnn __FILE__, __func__, __LINE__, 302221167Sgnn VXGE_HAL_ERR_PRIVILAGED_OPEARATION); 303221167Sgnn 304221167Sgnn return (VXGE_HAL_ERR_PRIVILAGED_OPEARATION); 305221167Sgnn } 306221167Sgnn 307221167Sgnn val64 = vxge_os_pio_mem_read64(pdev, regh0, 308221167Sgnn &toc_reg->toc_vpath_pointer[i]); 309221167Sgnn 310221167Sgnn vpath_reg = (vxge_hal_vpath_reg_t *) ((void *)(bar0 + val64)); 311221167Sgnn 312221167Sgnn status = __hal_vpath_fw_upgrade(pdev, regh0, 313221167Sgnn i, vpath_reg, buffer, length); 314221167Sgnn 315221167Sgnn break; 316221167Sgnn } 317221167Sgnn 318221167Sgnn if (status == VXGE_HAL_OK) { 319221167Sgnn val64 = vxge_os_pio_mem_read64(pdev, regh0, 320221167Sgnn &toc_reg->toc_mrpcim_pointer); 321221167Sgnn 322221167Sgnn mrpcim_reg = (vxge_hal_mrpcim_reg_t *) ((void *)(bar0 + val64)); 323221167Sgnn 324221167Sgnn val64 = vxge_os_pio_mem_read64(pdev, regh0, 325221167Sgnn &mrpcim_reg->sw_reset_cfg1); 326221167Sgnn 327221167Sgnn val64 |= VXGE_HAL_SW_RESET_CFG1_TYPE; 328221167Sgnn 329221167Sgnn vxge_os_pio_mem_write64(pdev, regh0, 330221167Sgnn val64, 331221167Sgnn &mrpcim_reg->sw_reset_cfg1); 332221167Sgnn 333221167Sgnn vxge_os_pio_mem_write64(pdev, regh0, 334221167Sgnn VXGE_HAL_PF_SW_RESET_PF_SW_RESET( 335221167Sgnn VXGE_HAL_PF_SW_RESET_COMMAND), 336221167Sgnn &mrpcim_reg->bf_sw_reset); 337221167Sgnn 338221167Sgnn vxge_os_mdelay(100); 339221167Sgnn } 340221167Sgnn 341221167Sgnn vxge_hal_trace_log_driver("<== %s:%s:%d Result = %d", 342221167Sgnn __FILE__, __func__, __LINE__, status); 343221167Sgnn 344221167Sgnn return (status); 345221167Sgnn} 346221167Sgnn 347221167Sgnn/* 348221167Sgnn * vxge_hal_mrpcim_vpath_qos_set - Set the priority, Guaranteed and maximum 349221167Sgnn * bandwidth for a vpath. 350221167Sgnn * @devh: HAL device handle. 351221167Sgnn * @vp_id: Vpath Id. 352221167Sgnn * @priority: Priority 353221167Sgnn * @min_bandwidth: Minimum Bandwidth 354221167Sgnn * @max_bandwidth: Maximum Bandwidth 355221167Sgnn * 356221167Sgnn * Set the Guaranteed and maximum bandwidth for a given vpath 357221167Sgnn * 358221167Sgnn */ 359221167Sgnnvxge_hal_status_e 360221167Sgnnvxge_hal_mrpcim_vpath_qos_set( 361221167Sgnn vxge_hal_device_h devh, 362221167Sgnn u32 vp_id, 363221167Sgnn u32 priority, 364221167Sgnn u32 min_bandwidth, 365221167Sgnn u32 max_bandwidth) 366221167Sgnn{ 367221167Sgnn vxge_hal_status_e status = VXGE_HAL_OK; 368221167Sgnn vxge_hal_vpath_qos_config_t config; 369221167Sgnn __hal_device_t *hldev = (__hal_device_t *) devh; 370221167Sgnn 371221167Sgnn vxge_assert(devh != NULL); 372221167Sgnn 373221167Sgnn vxge_hal_trace_log_mrpcim("==> %s:%s:%d", 374221167Sgnn __FILE__, __func__, __LINE__); 375221167Sgnn 376221167Sgnn vxge_hal_trace_log_mrpcim("devh = 0x"VXGE_OS_STXFMT", vp_id = %d, " 377221167Sgnn "priority = %d, min_bandwidth = %d, max_bandwidth = %d", 378221167Sgnn (ptr_t) devh, vp_id, priority, min_bandwidth, max_bandwidth); 379221167Sgnn 380221167Sgnn if (!(hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM)) { 381221167Sgnn vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = %d", 382221167Sgnn __FILE__, __func__, __LINE__, 383221167Sgnn VXGE_HAL_ERR_PRIVILAGED_OPEARATION); 384221167Sgnn 385221167Sgnn return (VXGE_HAL_ERR_PRIVILAGED_OPEARATION); 386221167Sgnn } 387221167Sgnn 388221167Sgnn if (vp_id >= VXGE_HAL_MAX_VIRTUAL_PATHS) { 389221167Sgnn vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = %d", 390221167Sgnn __FILE__, __func__, __LINE__, 391221167Sgnn VXGE_HAL_ERR_VPATH_NOT_AVAILABLE); 392221167Sgnn 393221167Sgnn return (VXGE_HAL_ERR_VPATH_NOT_AVAILABLE); 394221167Sgnn } 395221167Sgnn 396221167Sgnn config.priority = priority; 397221167Sgnn config.min_bandwidth = min_bandwidth; 398221167Sgnn config.max_bandwidth = max_bandwidth; 399221167Sgnn 400221167Sgnn if ((status = __hal_vpath_qos_config_check(&config)) != VXGE_HAL_OK) { 401221167Sgnn vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = %d", 402221167Sgnn __FILE__, __func__, __LINE__, status); 403221167Sgnn return (status); 404221167Sgnn } 405221167Sgnn 406221167Sgnn if (status == VXGE_HAL_OK) { 407221167Sgnn hldev->header.config.mrpcim_config.vp_qos[vp_id].priority = 408221167Sgnn priority; 409221167Sgnn hldev->header.config.mrpcim_config.vp_qos[vp_id].min_bandwidth = 410221167Sgnn min_bandwidth; 411221167Sgnn hldev->header.config.mrpcim_config.vp_qos[vp_id].max_bandwidth = 412221167Sgnn max_bandwidth; 413221167Sgnn } 414221167Sgnn 415221167Sgnn vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = %d", 416221167Sgnn __FILE__, __func__, __LINE__, status); 417221167Sgnn return (status); 418221167Sgnn} 419221167Sgnn 420221167Sgnn/* 421221167Sgnn * vxge_hal_mrpcim_vpath_qos_get - Get the priority, Guaranteed and maximum 422221167Sgnn * bandwidth for a vpath. 423221167Sgnn * @devh: HAL device handle. 424221167Sgnn * @vp_id: Vpath Id. 425221167Sgnn * @priority: Buffer to return Priority 426221167Sgnn * @min_bandwidth: Buffer to return Minimum Bandwidth 427221167Sgnn * @max_bandwidth: Buffer to return Maximum Bandwidth 428221167Sgnn * 429221167Sgnn * Get the Guaranteed and maximum bandwidth for a given vpath 430221167Sgnn * 431221167Sgnn */ 432221167Sgnnvxge_hal_status_e 433221167Sgnnvxge_hal_mrpcim_vpath_qos_get( 434221167Sgnn vxge_hal_device_h devh, 435221167Sgnn u32 vp_id, 436221167Sgnn u32 *priority, 437221167Sgnn u32 *min_bandwidth, 438221167Sgnn u32 *max_bandwidth) 439221167Sgnn{ 440221167Sgnn vxge_hal_status_e status = VXGE_HAL_OK; 441221167Sgnn __hal_device_t *hldev = (__hal_device_t *) devh; 442221167Sgnn 443221167Sgnn vxge_assert(devh != NULL); 444221167Sgnn 445221167Sgnn vxge_hal_trace_log_mrpcim("==> %s:%s:%d", 446221167Sgnn __FILE__, __func__, __LINE__); 447221167Sgnn 448221167Sgnn vxge_hal_trace_log_mrpcim( 449221167Sgnn "devh = 0x"VXGE_OS_STXFMT", vp_id = %d, " 450221167Sgnn "priority = 0x"VXGE_OS_STXFMT", " 451221167Sgnn "min_bandwidth = 0x"VXGE_OS_STXFMT", " 452221167Sgnn "max_bandwidth = 0x"VXGE_OS_STXFMT, 453221167Sgnn (ptr_t) devh, vp_id, (ptr_t) priority, 454221167Sgnn (ptr_t) min_bandwidth, (ptr_t) max_bandwidth); 455221167Sgnn 456221167Sgnn if (vp_id >= VXGE_HAL_MAX_VIRTUAL_PATHS) { 457221167Sgnn vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = %d", 458221167Sgnn __FILE__, __func__, __LINE__, 459221167Sgnn VXGE_HAL_ERR_VPATH_NOT_AVAILABLE); 460221167Sgnn 461221167Sgnn return (VXGE_HAL_ERR_VPATH_NOT_AVAILABLE); 462221167Sgnn } 463221167Sgnn 464221167Sgnn *priority = 465221167Sgnn hldev->header.config.mrpcim_config.vp_qos[vp_id].min_bandwidth; 466221167Sgnn 467221167Sgnn *min_bandwidth = 468221167Sgnn hldev->header.config.mrpcim_config.vp_qos[vp_id].min_bandwidth; 469221167Sgnn 470221167Sgnn *max_bandwidth = 471221167Sgnn hldev->header.config.mrpcim_config.vp_qos[vp_id].max_bandwidth; 472221167Sgnn 473221167Sgnn vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = %d", 474221167Sgnn __FILE__, __func__, __LINE__, status); 475221167Sgnn return (status); 476221167Sgnn} 477221167Sgnn 478221167Sgnn/* 479221167Sgnn * __hal_mrpcim_mdio_access - Access the MDIO device 480221167Sgnn * @devh: HAL Device handle. 481221167Sgnn * @port: Port id 482221167Sgnn * @operation: Type of operation 483221167Sgnn * @device: MMD device address 484221167Sgnn * @addr: MMD address 485221167Sgnn * @data: MMD data 486221167Sgnn * 487221167Sgnn * Access the data from a MDIO Device. 488221167Sgnn * 489221167Sgnn */ 490221167Sgnnvxge_hal_status_e 491221167Sgnn__hal_mrpcim_mdio_access( 492221167Sgnn vxge_hal_device_h devh, 493221167Sgnn u32 port, 494221167Sgnn u32 operation, 495221167Sgnn u32 device, 496221167Sgnn u16 addr, 497221167Sgnn u16 *data) 498221167Sgnn{ 499221167Sgnn u64 val64; 500221167Sgnn u32 prtad; 501221167Sgnn vxge_hal_status_e status = VXGE_HAL_OK; 502221167Sgnn __hal_device_t *hldev = (__hal_device_t *) devh; 503221167Sgnn 504221167Sgnn vxge_assert((devh != NULL) && (data != NULL)); 505221167Sgnn 506221167Sgnn vxge_hal_trace_log_mrpcim("==> %s:%s:%d", 507221167Sgnn __FILE__, __func__, __LINE__); 508221167Sgnn 509221167Sgnn vxge_hal_trace_log_mrpcim( 510221167Sgnn "devh = 0x"VXGE_OS_STXFMT", operation = %d, " 511221167Sgnn "device = %d, addr = %d, data = 0x"VXGE_OS_STXFMT, 512221167Sgnn (ptr_t) devh, operation, device, addr, (ptr_t) data); 513221167Sgnn 514221167Sgnn if (!(hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM)) { 515221167Sgnn vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = %d", 516221167Sgnn __FILE__, __func__, __LINE__, 517221167Sgnn VXGE_HAL_ERR_PRIVILAGED_OPEARATION); 518221167Sgnn 519221167Sgnn return (VXGE_HAL_ERR_PRIVILAGED_OPEARATION); 520221167Sgnn } 521221167Sgnn 522221167Sgnn if (device == VXGE_HAL_MDIO_MGR_ACCESS_PORT_DEVAD_DTE_XS) { 523221167Sgnn if (port == 0) 524221167Sgnn prtad = hldev->mrpcim->mdio_dte_prtad0; 525221167Sgnn else 526221167Sgnn prtad = hldev->mrpcim->mdio_dte_prtad1; 527221167Sgnn } else { 528221167Sgnn if (port == 0) 529221167Sgnn prtad = hldev->mrpcim->mdio_phy_prtad0; 530221167Sgnn else 531221167Sgnn prtad = hldev->mrpcim->mdio_phy_prtad1; 532221167Sgnn } 533221167Sgnn 534221167Sgnn val64 = VXGE_HAL_MDIO_MGR_ACCESS_PORT_STROBE_ONE | 535221167Sgnn VXGE_HAL_MDIO_MGR_ACCESS_PORT_OP_TYPE(operation) | 536221167Sgnn VXGE_HAL_MDIO_MGR_ACCESS_PORT_DEVAD(device) | 537221167Sgnn VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR(addr) | 538221167Sgnn VXGE_HAL_MDIO_MGR_ACCESS_PORT_DATA(*data) | 539221167Sgnn VXGE_HAL_MDIO_MGR_ACCESS_PORT_ST_PATTERN(0) | 540221167Sgnn VXGE_HAL_MDIO_MGR_ACCESS_PORT_PREAMBLE | 541221167Sgnn VXGE_HAL_MDIO_MGR_ACCESS_PORT_PRTAD(prtad) | 542221167Sgnn VXGE_HAL_MDIO_MGR_ACCESS_PORT_STROBE_TWO; 543221167Sgnn 544221167Sgnn vxge_os_pio_mem_write64(hldev->header.pdev, 545221167Sgnn hldev->header.regh0, 546221167Sgnn val64, 547221167Sgnn &hldev->mrpcim_reg->mdio_mgr_access_port[port]); 548221167Sgnn 549221167Sgnn vxge_os_wmb(); 550221167Sgnn 551221167Sgnn status = vxge_hal_device_register_poll(hldev->header.pdev, 552221167Sgnn hldev->header.regh0, 553221167Sgnn &hldev->mrpcim_reg->mdio_mgr_access_port[port], 554221167Sgnn 0, 555221167Sgnn VXGE_HAL_MDIO_MGR_ACCESS_PORT_STROBE_ONE | 556221167Sgnn VXGE_HAL_MDIO_MGR_ACCESS_PORT_STROBE_TWO, 557221167Sgnn hldev->header.config.device_poll_millis); 558221167Sgnn 559221167Sgnn if ((status == VXGE_HAL_OK) && 560221167Sgnn ((operation == VXGE_HAL_MDIO_MGR_ACCESS_PORT_OP_TYPE_READ_INCR) || 561221167Sgnn (operation == VXGE_HAL_MDIO_MGR_ACCESS_PORT_OP_TYPE_READ) || 562221167Sgnn (operation == 563221167Sgnn VXGE_HAL_MDIO_MGR_ACCESS_PORT_OP_TYPE_ADDR_READ_INCR) || 564221167Sgnn (operation == VXGE_HAL_MDIO_MGR_ACCESS_PORT_OP_TYPE_ADDR_READ))) { 565221167Sgnn 566221167Sgnn val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 567221167Sgnn hldev->header.regh0, 568221167Sgnn &hldev->mrpcim_reg->mdio_mgr_access_port[port]); 569221167Sgnn 570221167Sgnn *data = (u16) VXGE_HAL_MDIO_MGR_ACCESS_GET_PORT_DATA(val64); 571221167Sgnn 572221167Sgnn } else { 573221167Sgnn *data = 0; 574221167Sgnn } 575221167Sgnn 576221167Sgnn vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = %d", 577221167Sgnn __FILE__, __func__, __LINE__, status); 578221167Sgnn 579221167Sgnn return (VXGE_HAL_OK); 580221167Sgnn} 581221167Sgnn 582221167Sgnn/* 583221167Sgnn * vxge_hal_mrpcim_intr_enable - Enable the interrupts on mrpcim. 584221167Sgnn * @devh: HAL device handle. 585221167Sgnn * 586221167Sgnn * Enable mrpcim interrupts 587221167Sgnn * 588221167Sgnn * See also: vxge_hal_mrpcim_intr_disable(). 589221167Sgnn */ 590221167Sgnnvxge_hal_status_e 591221167Sgnnvxge_hal_mrpcim_intr_enable(vxge_hal_device_h devh) 592221167Sgnn{ 593221167Sgnn u32 i; 594221167Sgnn u64 val64; 595221167Sgnn vxge_hal_status_e status = VXGE_HAL_OK; 596221167Sgnn vxge_hal_mrpcim_reg_t *mrpcim_reg; 597221167Sgnn __hal_device_t *hldev = (__hal_device_t *) devh; 598221167Sgnn 599221167Sgnn vxge_assert(devh); 600221167Sgnn 601221167Sgnn vxge_hal_trace_log_mrpcim("==> %s:%s:%d", 602221167Sgnn __FILE__, __func__, __LINE__); 603221167Sgnn 604221167Sgnn vxge_hal_trace_log_mrpcim("devh = 0x"VXGE_OS_STXFMT, 605221167Sgnn (ptr_t) devh); 606221167Sgnn 607221167Sgnn if (!(hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM)) { 608221167Sgnn vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = %d", 609221167Sgnn __FILE__, __func__, __LINE__, 610221167Sgnn VXGE_HAL_ERR_PRIVILAGED_OPEARATION); 611221167Sgnn 612221167Sgnn return (VXGE_HAL_ERR_PRIVILAGED_OPEARATION); 613221167Sgnn 614221167Sgnn } 615221167Sgnn 616221167Sgnn mrpcim_reg = hldev->mrpcim_reg; 617221167Sgnn 618221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->ini_errors_reg); 619221167Sgnn 620221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->dma_errors_reg); 621221167Sgnn 622221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->tgt_errors_reg); 623221167Sgnn 624221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->config_errors_reg); 625221167Sgnn 626221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->crdt_errors_reg); 627221167Sgnn 628221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->mrpcim_general_errors_reg); 629221167Sgnn 630221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->pll_errors_reg); 631221167Sgnn 632221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->mrpcim_ppif_int_status); 633221167Sgnn 634221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->dbecc_err_reg); 635221167Sgnn 636221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->general_err_reg); 637221167Sgnn 638221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->pcipif_int_status); 639221167Sgnn 640221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->pda_alarm_reg); 641221167Sgnn 642221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->pcc_error_reg); 643221167Sgnn 644221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->lso_error_reg); 645221167Sgnn 646221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->sm_error_reg); 647221167Sgnn 648221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->rtdma_int_status); 649221167Sgnn 650221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->rc_alarm_reg); 651221167Sgnn 652221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->rxdrm_sm_err_reg); 653221167Sgnn 654221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->rxdcm_sm_err_reg); 655221167Sgnn 656221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->rxdwm_sm_err_reg); 657221167Sgnn 658221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->rda_err_reg); 659221167Sgnn 660221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->rda_ecc_db_reg); 661221167Sgnn 662221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->rqa_err_reg); 663221167Sgnn 664221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->frf_alarm_reg); 665221167Sgnn 666221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->rocrc_alarm_reg); 667221167Sgnn 668221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->wde0_alarm_reg); 669221167Sgnn 670221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->wde1_alarm_reg); 671221167Sgnn 672221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->wde2_alarm_reg); 673221167Sgnn 674221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->wde3_alarm_reg); 675221167Sgnn 676221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->wrdma_int_status); 677221167Sgnn 678221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->g3cmct_err_reg); 679221167Sgnn 680221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->g3cmct_int_status); 681221167Sgnn 682221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->gsscc_err_reg); 683221167Sgnn 684221167Sgnn for (i = 0; i < 3; i++) { 685221167Sgnn 686221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->gssc_err0_reg[i]); 687221167Sgnn 688221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->gssc_err1_reg[i]); 689221167Sgnn 690221167Sgnn } 691221167Sgnn 692221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->gcmg1_int_status); 693221167Sgnn 694221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->gxtmc_err_reg); 695221167Sgnn 696221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->gcp_err_reg); 697221167Sgnn 698221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->cmc_err_reg); 699221167Sgnn 700221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->gcmg2_int_status); 701221167Sgnn 702221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->g3ifcmd_cml_err_reg); 703221167Sgnn 704221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->g3ifcmd_cml_int_status); 705221167Sgnn 706221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->g3ifcmd_cmu_err_reg); 707221167Sgnn 708221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->g3ifcmd_cmu_int_status); 709221167Sgnn 710221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->psscc_err_reg); 711221167Sgnn 712221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->pcmg1_int_status); 713221167Sgnn 714221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->pxtmc_err_reg); 715221167Sgnn 716221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->cp_exc_reg); 717221167Sgnn 718221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->cp_err_reg); 719221167Sgnn 720221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->pcmg2_int_status); 721221167Sgnn 722221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->dam_err_reg); 723221167Sgnn 724221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->pcmg3_int_status); 725221167Sgnn 726221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->xmac_gen_err_reg); 727221167Sgnn 728221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->xgxs_gen_err_reg); 729221167Sgnn 730221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->asic_ntwk_err_reg); 731221167Sgnn 732221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->xgmac_int_status); 733221167Sgnn 734221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->rxmac_ecc_err_reg); 735221167Sgnn 736221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->rxmac_various_err_reg); 737221167Sgnn 738221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->rxmac_int_status); 739221167Sgnn 740221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->txmac_gen_err_reg); 741221167Sgnn 742221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->txmac_ecc_err_reg); 743221167Sgnn 744221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->tmac_int_status); 745221167Sgnn 746221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->g3ifcmd_fb_err_reg); 747221167Sgnn 748221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->g3ifcmd_fb_int_status); 749221167Sgnn 750221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->mc_err_reg); 751221167Sgnn 752221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->grocrc_alarm_reg); 753221167Sgnn 754221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->fau_ecc_err_reg); 755221167Sgnn 756221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->mc_int_status); 757221167Sgnn 758221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->g3fbct_err_reg); 759221167Sgnn 760221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->g3fbct_int_status); 761221167Sgnn 762221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->orp_err_reg); 763221167Sgnn 764221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->ptm_alarm_reg); 765221167Sgnn 766221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->tpa_error_reg); 767221167Sgnn 768221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->tpa_int_status); 769221167Sgnn 770221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->kdfc_err_reg); 771221167Sgnn 772221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->doorbell_int_status); 773221167Sgnn 774221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->tim_err_reg); 775221167Sgnn 776221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->msg_exc_reg); 777221167Sgnn 778221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->msg_err_reg); 779221167Sgnn 780221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->msg_err2_reg); 781221167Sgnn 782221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->msg_err3_reg); 783221167Sgnn 784221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->msg_int_status); 785221167Sgnn 786221167Sgnn vxge_os_pio_mem_read64(hldev->header.pdev, 787221167Sgnn hldev->header.regh0, 788221167Sgnn &mrpcim_reg->mrpcim_general_int_status); 789221167Sgnn 790221167Sgnn /* unmask interrupts */ 791221167Sgnn val64 = VXGE_HAL_INI_ERRORS_REG_DCPL_FSM_ERR | 792221167Sgnn VXGE_HAL_INI_ERRORS_REG_INI_BUF_DB_ERR | 793221167Sgnn VXGE_HAL_INI_ERRORS_REG_INI_DATA_OVERFLOW | 794221167Sgnn VXGE_HAL_INI_ERRORS_REG_INI_HDR_OVERFLOW; 795221167Sgnn 796221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->ini_errors_mask); 797221167Sgnn 798221167Sgnn val64 = VXGE_HAL_DMA_ERRORS_REG_RDARB_FSM_ERR | 799221167Sgnn VXGE_HAL_DMA_ERRORS_REG_WRARB_FSM_ERR | 800221167Sgnn VXGE_HAL_DMA_ERRORS_REG_DMA_WRDMA_WR_HDR_OVERFLOW | 801221167Sgnn VXGE_HAL_DMA_ERRORS_REG_DMA_WRDMA_WR_HDR_UNDERFLOW | 802221167Sgnn VXGE_HAL_DMA_ERRORS_REG_DMA_WRDMA_WR_DATA_OVERFLOW | 803221167Sgnn VXGE_HAL_DMA_ERRORS_REG_DMA_WRDMA_WR_DATA_UNDERFLOW | 804221167Sgnn VXGE_HAL_DMA_ERRORS_REG_DMA_MSG_WR_HDR_OVERFLOW | 805221167Sgnn VXGE_HAL_DMA_ERRORS_REG_DMA_MSG_WR_HDR_UNDERFLOW | 806221167Sgnn VXGE_HAL_DMA_ERRORS_REG_DMA_MSG_WR_DATA_OVERFLOW | 807221167Sgnn VXGE_HAL_DMA_ERRORS_REG_DMA_MSG_WR_DATA_UNDERFLOW | 808221167Sgnn VXGE_HAL_DMA_ERRORS_REG_DMA_STATS_WR_HDR_OVERFLOW | 809221167Sgnn VXGE_HAL_DMA_ERRORS_REG_DMA_STATS_WR_HDR_UNDERFLOW | 810221167Sgnn VXGE_HAL_DMA_ERRORS_REG_DMA_STATS_WR_DATA_OVERFLOW | 811221167Sgnn VXGE_HAL_DMA_ERRORS_REG_DMA_STATS_WR_DATA_UNDERFLOW | 812221167Sgnn VXGE_HAL_DMA_ERRORS_REG_DMA_RTDMA_WR_HDR_OVERFLOW | 813221167Sgnn VXGE_HAL_DMA_ERRORS_REG_DMA_RTDMA_WR_HDR_UNDERFLOW | 814221167Sgnn VXGE_HAL_DMA_ERRORS_REG_DMA_RTDMA_WR_DATA_OVERFLOW | 815221167Sgnn VXGE_HAL_DMA_ERRORS_REG_DMA_RTDMA_WR_DATA_UNDERFLOW | 816221167Sgnn VXGE_HAL_DMA_ERRORS_REG_DMA_WRDMA_RD_HDR_OVERFLOW | 817221167Sgnn VXGE_HAL_DMA_ERRORS_REG_DMA_WRDMA_RD_HDR_UNDERFLOW | 818221167Sgnn VXGE_HAL_DMA_ERRORS_REG_DMA_RTDMA_RD_HDR_OVERFLOW | 819221167Sgnn VXGE_HAL_DMA_ERRORS_REG_DMA_RTDMA_RD_HDR_UNDERFLOW | 820221167Sgnn VXGE_HAL_DMA_ERRORS_REG_DBLGEN_FSM_ERR | 821221167Sgnn VXGE_HAL_DMA_ERRORS_REG_DBLGEN_CREDIT_FSM_ERR | 822221167Sgnn VXGE_HAL_DMA_ERRORS_REG_DBLGEN_DMA_WRR_SM_ERR; 823221167Sgnn 824221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->dma_errors_mask); 825221167Sgnn 826221167Sgnn val64 = VXGE_HAL_TGT_ERRORS_REG_TGT_REQ_FSM_ERR | 827221167Sgnn VXGE_HAL_TGT_ERRORS_REG_TGT_CPL_FSM_ERR; 828221167Sgnn 829221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->tgt_errors_mask); 830221167Sgnn 831221167Sgnn val64 = VXGE_HAL_CONFIG_ERRORS_REG_I2C_MAIN_FSM_ERR | 832221167Sgnn VXGE_HAL_CONFIG_ERRORS_REG_I2C_REG_FSM_ERR | 833221167Sgnn VXGE_HAL_CONFIG_ERRORS_REG_CFGM_I2C_TIMEOUT | 834221167Sgnn VXGE_HAL_CONFIG_ERRORS_REG_RIC_I2C_TIMEOUT | 835221167Sgnn VXGE_HAL_CONFIG_ERRORS_REG_CFGM_FSM_ERR | 836221167Sgnn VXGE_HAL_CONFIG_ERRORS_REG_RIC_FSM_ERR | 837221167Sgnn VXGE_HAL_CONFIG_ERRORS_REG_PIFM_TIMEOUT | 838221167Sgnn VXGE_HAL_CONFIG_ERRORS_REG_PIFM_FSM_ERR | 839221167Sgnn VXGE_HAL_CONFIG_ERRORS_REG_PIFM_TO_FSM_ERR | 840221167Sgnn VXGE_HAL_CONFIG_ERRORS_REG_RIC_RIC_RD_TIMEOUT; 841221167Sgnn 842221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, 843221167Sgnn &mrpcim_reg->config_errors_mask); 844221167Sgnn 845221167Sgnn val64 = VXGE_HAL_CRDT_ERRORS_REG_WRCRDTARB_FSM_ERR | 846221167Sgnn VXGE_HAL_CRDT_ERRORS_REG_WRCRDTARB_INTCTL_ILLEGAL_CRD_DEAL | 847221167Sgnn VXGE_HAL_CRDT_ERRORS_REG_WRCRDTARB_PDA_ILLEGAL_CRD_DEAL | 848221167Sgnn VXGE_HAL_CRDT_ERRORS_REG_WRCRDTARB_PCI_MSG_ILLEGAL_CRD_DEAL | 849221167Sgnn VXGE_HAL_CRDT_ERRORS_REG_RDCRDTARB_FSM_ERR | 850221167Sgnn VXGE_HAL_CRDT_ERRORS_REG_RDCRDTARB_RDA_ILLEGAL_CRD_DEAL | 851221167Sgnn VXGE_HAL_CRDT_ERRORS_REG_RDCRDTARB_PDA_ILLEGAL_CRD_DEAL | 852221167Sgnn VXGE_HAL_CRDT_ERRORS_REG_RDCRDTARB_DBLGEN_ILLEGAL_CRD_DEAL; 853221167Sgnn 854221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->crdt_errors_mask); 855221167Sgnn 856221167Sgnn val64 = VXGE_HAL_MRPCIM_GENERAL_ERRORS_REG_STATSB_FSM_ERR | 857221167Sgnn VXGE_HAL_MRPCIM_GENERAL_ERRORS_REG_XGEN_FSM_ERR | 858221167Sgnn VXGE_HAL_MRPCIM_GENERAL_ERRORS_REG_XMEM_FSM_ERR | 859221167Sgnn VXGE_HAL_MRPCIM_GENERAL_ERRORS_REG_KDFCCTL_FSM_ERR | 860221167Sgnn VXGE_HAL_MRPCIM_GENERAL_ERRORS_REG_MRIOVCTL_FSM_ERR | 861221167Sgnn VXGE_HAL_MRPCIM_GENERAL_ERRORS_REG_SPI_FLSH_ERR | 862221167Sgnn VXGE_HAL_MRPCIM_GENERAL_ERRORS_REG_SPI_IIC_ACK_ERR | 863221167Sgnn VXGE_HAL_MRPCIM_GENERAL_ERRORS_REG_SPI_IIC_CHKSUM_ERR | 864221167Sgnn VXGE_HAL_MRPCIM_GENERAL_ERRORS_REG_INI_SERR_DET | 865221167Sgnn VXGE_HAL_MRPCIM_GENERAL_ERRORS_REG_INTCTL_MSIX_FSM_ERR | 866221167Sgnn VXGE_HAL_MRPCIM_GENERAL_ERRORS_REG_INTCTL_MSI_OVERFLOW | 867221167Sgnn VXGE_HAL_MRPCIM_GENERAL_ERRORS_REG_PPIF_PCI_NOT_FLUSH_SW_RESET | 868221167Sgnn VXGE_HAL_MRPCIM_GENERAL_ERRORS_REG_PPIF_SW_RESET_FSM_ERR; 869221167Sgnn 870221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, 871221167Sgnn &mrpcim_reg->mrpcim_general_errors_mask); 872221167Sgnn 873221167Sgnn val64 = VXGE_HAL_PLL_ERRORS_REG_CORE_CMG_PLL_OOL | 874221167Sgnn VXGE_HAL_PLL_ERRORS_REG_CORE_FB_PLL_OOL | 875221167Sgnn VXGE_HAL_PLL_ERRORS_REG_CORE_X_PLL_OOL; 876221167Sgnn 877221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->pll_errors_mask); 878221167Sgnn 879221167Sgnn val64 = VXGE_HAL_MRPCIM_PPIF_INT_STATUS_INI_ERRORS_INI_INT | 880221167Sgnn VXGE_HAL_MRPCIM_PPIF_INT_STATUS_DMA_ERRORS_DMA_INT | 881221167Sgnn VXGE_HAL_MRPCIM_PPIF_INT_STATUS_TGT_ERRORS_TGT_INT | 882221167Sgnn VXGE_HAL_MRPCIM_PPIF_INT_STATUS_CONFIG_ERRORS_CONFIG_INT | 883221167Sgnn VXGE_HAL_MRPCIM_PPIF_INT_STATUS_CRDT_ERRORS_CRDT_INT | 884221167Sgnn VXGE_HAL_MRPCIM_PPIF_INT_STATUS_MRPCIM_GENERAL_ERRORS_GENERAL_INT | 885221167Sgnn VXGE_HAL_MRPCIM_PPIF_INT_STATUS_PLL_ERRORS_PLL_INT; 886221167Sgnn 887221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, 888221167Sgnn &mrpcim_reg->mrpcim_ppif_int_mask); 889221167Sgnn 890221167Sgnn val64 = VXGE_HAL_DBECC_ERR_REG_PCI_RETRY_BUF_DB_ERR | 891221167Sgnn VXGE_HAL_DBECC_ERR_REG_PCI_RETRY_SOT_DB_ERR | 892221167Sgnn VXGE_HAL_DBECC_ERR_REG_PCI_P_HDR_DB_ERR | 893221167Sgnn VXGE_HAL_DBECC_ERR_REG_PCI_P_DATA_DB_ERR | 894221167Sgnn VXGE_HAL_DBECC_ERR_REG_PCI_NP_HDR_DB_ERR | 895221167Sgnn VXGE_HAL_DBECC_ERR_REG_PCI_NP_DATA_DB_ERR; 896221167Sgnn 897221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->dbecc_err_mask); 898221167Sgnn 899221167Sgnn val64 = VXGE_HAL_GENERAL_ERR_REG_PCI_LINK_RST_FSM_ERR; 900221167Sgnn 901221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->general_err_mask); 902221167Sgnn 903221167Sgnn val64 = VXGE_HAL_PCIPIF_INT_STATUS_DBECC_ERR_DBECC_ERR_INT | 904221167Sgnn VXGE_HAL_PCIPIF_INT_STATUS_GENERAL_ERR_GENERAL_ERR_INT; 905221167Sgnn 906221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->pcipif_int_mask); 907221167Sgnn 908221167Sgnn val64 = VXGE_HAL_PDA_ALARM_REG_PDA_SM_ERR; 909221167Sgnn 910221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->pda_alarm_mask); 911221167Sgnn 912221167Sgnn val64 = 0; 913221167Sgnn 914221167Sgnn for (i = 0; i < 8; i++) { 915221167Sgnn val64 |= VXGE_HAL_PCC_ERROR_REG_PCC_PCC_FRM_BUF_DBE(i) | 916221167Sgnn VXGE_HAL_PCC_ERROR_REG_PCC_PCC_TXDO_DBE(i) | 917221167Sgnn VXGE_HAL_PCC_ERROR_REG_PCC_PCC_FSM_ERR_ALARM(i) | 918221167Sgnn VXGE_HAL_PCC_ERROR_REG_PCC_PCC_SERR(i); 919221167Sgnn } 920221167Sgnn 921221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->pcc_error_mask); 922221167Sgnn 923221167Sgnn val64 = 0; 924221167Sgnn 925221167Sgnn for (i = 0; i < 8; i++) { 926221167Sgnn val64 |= VXGE_HAL_LSO_ERROR_REG_PCC_LSO_FSM_ERR_ALARM(i); 927221167Sgnn } 928221167Sgnn 929221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->lso_error_mask); 930221167Sgnn 931221167Sgnn val64 = VXGE_HAL_SM_ERROR_REG_SM_FSM_ERR_ALARM; 932221167Sgnn 933221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->sm_error_mask); 934221167Sgnn 935221167Sgnn val64 = VXGE_HAL_RTDMA_INT_STATUS_PDA_ALARM_PDA_INT | 936221167Sgnn VXGE_HAL_RTDMA_INT_STATUS_PCC_ERROR_PCC_INT | 937221167Sgnn VXGE_HAL_RTDMA_INT_STATUS_LSO_ERROR_LSO_INT | 938221167Sgnn VXGE_HAL_RTDMA_INT_STATUS_SM_ERROR_SM_INT; 939221167Sgnn 940221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->rtdma_int_mask); 941221167Sgnn 942221167Sgnn val64 = VXGE_HAL_RC_ALARM_REG_FTC_SM_ERR | 943221167Sgnn VXGE_HAL_RC_ALARM_REG_FTC_SM_PHASE_ERR | 944221167Sgnn VXGE_HAL_RC_ALARM_REG_BTDWM_SM_ERR | 945221167Sgnn VXGE_HAL_RC_ALARM_REG_BTC_SM_ERR | 946221167Sgnn VXGE_HAL_RC_ALARM_REG_BTDCM_SM_ERR | 947221167Sgnn VXGE_HAL_RC_ALARM_REG_BTDRM_SM_ERR | 948221167Sgnn VXGE_HAL_RC_ALARM_REG_RMM_RXD_RC_ECC_DB_ERR | 949221167Sgnn VXGE_HAL_RC_ALARM_REG_RHS_RXD_RHS_ECC_DB_ERR | 950221167Sgnn VXGE_HAL_RC_ALARM_REG_RMM_SM_ERR | 951221167Sgnn VXGE_HAL_RC_ALARM_REG_BTC_VPATH_MISMATCH_ERR; 952221167Sgnn 953221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->rc_alarm_mask); 954221167Sgnn 955221167Sgnn val64 = 0; 956221167Sgnn 957221167Sgnn for (i = 0; i < 17; i++) { 958221167Sgnn val64 |= VXGE_HAL_RXDRM_SM_ERR_REG_PRC_VP(i); 959221167Sgnn } 960221167Sgnn 961221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->rxdrm_sm_err_mask); 962221167Sgnn 963221167Sgnn val64 = 0; 964221167Sgnn 965221167Sgnn for (i = 0; i < 17; i++) { 966221167Sgnn val64 |= VXGE_HAL_RXDCM_SM_ERR_REG_PRC_VP(i); 967221167Sgnn } 968221167Sgnn 969221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->rxdcm_sm_err_mask); 970221167Sgnn 971221167Sgnn val64 = 0; 972221167Sgnn 973221167Sgnn for (i = 0; i < 17; i++) { 974221167Sgnn val64 |= VXGE_HAL_RXDWM_SM_ERR_REG_PRC_VP(i); 975221167Sgnn } 976221167Sgnn 977221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->rxdwm_sm_err_mask); 978221167Sgnn 979221167Sgnn val64 = VXGE_HAL_RDA_ERR_REG_RDA_SM0_ERR_ALARM | 980221167Sgnn VXGE_HAL_RDA_ERR_REG_RDA_RXD_ECC_DB_ERR | 981221167Sgnn VXGE_HAL_RDA_ERR_REG_RDA_FRM_ECC_DB_ERR | 982221167Sgnn VXGE_HAL_RDA_ERR_REG_RDA_UQM_ECC_DB_ERR | 983221167Sgnn VXGE_HAL_RDA_ERR_REG_RDA_IMM_ECC_DB_ERR | 984221167Sgnn VXGE_HAL_RDA_ERR_REG_RDA_TIM_ECC_DB_ERR; 985221167Sgnn 986221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->rda_err_mask); 987221167Sgnn 988221167Sgnn val64 = 0; 989221167Sgnn 990221167Sgnn for (i = 0; i < 17; i++) { 991221167Sgnn val64 |= VXGE_HAL_RDA_ECC_DB_REG_RDA_RXD_ERR(i); 992221167Sgnn } 993221167Sgnn 994221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->rda_ecc_db_mask); 995221167Sgnn 996221167Sgnn val64 = VXGE_HAL_RQA_ERR_REG_RQA_SM_ERR_ALARM; 997221167Sgnn 998221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->rqa_err_mask); 999221167Sgnn 1000221167Sgnn val64 = 0; 1001221167Sgnn 1002221167Sgnn for (i = 0; i < 17; i++) { 1003221167Sgnn val64 |= VXGE_HAL_FRF_ALARM_REG_PRC_VP_FRF_SM_ERR(i); 1004221167Sgnn } 1005221167Sgnn 1006221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->frf_alarm_mask); 1007221167Sgnn 1008221167Sgnn val64 = VXGE_HAL_ROCRC_ALARM_REG_QCQ_QCC_BYP_ECC_DB | 1009221167Sgnn VXGE_HAL_ROCRC_ALARM_REG_NOA_NMA_SM_ERR | 1010221167Sgnn VXGE_HAL_ROCRC_ALARM_REG_NOA_IMMM_ECC_DB | 1011221167Sgnn VXGE_HAL_ROCRC_ALARM_REG_UDQ_UMQM_ECC_DB | 1012221167Sgnn VXGE_HAL_ROCRC_ALARM_REG_NOA_RCBM_ECC_DB | 1013221167Sgnn VXGE_HAL_ROCRC_ALARM_REG_NOA_WCT_CMD_FIFO_ERR; 1014221167Sgnn 1015221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->rocrc_alarm_mask); 1016221167Sgnn 1017221167Sgnn val64 = VXGE_HAL_WDE0_ALARM_REG_WDE0_DCC_SM_ERR | 1018221167Sgnn VXGE_HAL_WDE0_ALARM_REG_WDE0_PRM_SM_ERR | 1019221167Sgnn VXGE_HAL_WDE0_ALARM_REG_WDE0_CP_SM_ERR | 1020221167Sgnn VXGE_HAL_WDE0_ALARM_REG_WDE0_CP_CMD_ERR | 1021221167Sgnn VXGE_HAL_WDE0_ALARM_REG_WDE0_PCR_SM_ERR; 1022221167Sgnn 1023221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->wde0_alarm_mask); 1024221167Sgnn 1025221167Sgnn val64 = VXGE_HAL_WDE1_ALARM_REG_WDE1_DCC_SM_ERR | 1026221167Sgnn VXGE_HAL_WDE1_ALARM_REG_WDE1_PRM_SM_ERR | 1027221167Sgnn VXGE_HAL_WDE1_ALARM_REG_WDE1_CP_SM_ERR | 1028221167Sgnn VXGE_HAL_WDE1_ALARM_REG_WDE1_CP_CMD_ERR | 1029221167Sgnn VXGE_HAL_WDE1_ALARM_REG_WDE1_PCR_SM_ERR; 1030221167Sgnn 1031221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->wde1_alarm_mask); 1032221167Sgnn 1033221167Sgnn val64 = VXGE_HAL_WDE2_ALARM_REG_WDE2_DCC_SM_ERR | 1034221167Sgnn VXGE_HAL_WDE2_ALARM_REG_WDE2_PRM_SM_ERR | 1035221167Sgnn VXGE_HAL_WDE2_ALARM_REG_WDE2_CP_SM_ERR | 1036221167Sgnn VXGE_HAL_WDE2_ALARM_REG_WDE2_CP_CMD_ERR | 1037221167Sgnn VXGE_HAL_WDE2_ALARM_REG_WDE2_PCR_SM_ERR; 1038221167Sgnn 1039221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->wde2_alarm_mask); 1040221167Sgnn 1041221167Sgnn val64 = VXGE_HAL_WDE3_ALARM_REG_WDE3_DCC_SM_ERR | 1042221167Sgnn VXGE_HAL_WDE3_ALARM_REG_WDE3_PRM_SM_ERR | 1043221167Sgnn VXGE_HAL_WDE3_ALARM_REG_WDE3_CP_SM_ERR | 1044221167Sgnn VXGE_HAL_WDE3_ALARM_REG_WDE3_CP_CMD_ERR | 1045221167Sgnn VXGE_HAL_WDE3_ALARM_REG_WDE3_PCR_SM_ERR; 1046221167Sgnn 1047221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->wde3_alarm_mask); 1048221167Sgnn 1049221167Sgnn val64 = VXGE_HAL_WRDMA_INT_STATUS_RC_ALARM_RC_INT | 1050221167Sgnn VXGE_HAL_WRDMA_INT_STATUS_RXDRM_SM_ERR_RXDRM_INT | 1051221167Sgnn VXGE_HAL_WRDMA_INT_STATUS_RXDCM_SM_ERR_RXDCM_SM_INT | 1052221167Sgnn VXGE_HAL_WRDMA_INT_STATUS_RXDWM_SM_ERR_RXDWM_INT | 1053221167Sgnn VXGE_HAL_WRDMA_INT_STATUS_RDA_ERR_RDA_INT | 1054221167Sgnn VXGE_HAL_WRDMA_INT_STATUS_RDA_ECC_DB_RDA_ECC_DB_INT | 1055221167Sgnn VXGE_HAL_WRDMA_INT_STATUS_FRF_ALARM_FRF_INT | 1056221167Sgnn VXGE_HAL_WRDMA_INT_STATUS_ROCRC_ALARM_ROCRC_INT | 1057221167Sgnn VXGE_HAL_WRDMA_INT_STATUS_WDE0_ALARM_WDE0_INT | 1058221167Sgnn VXGE_HAL_WRDMA_INT_STATUS_WDE1_ALARM_WDE1_INT | 1059221167Sgnn VXGE_HAL_WRDMA_INT_STATUS_WDE2_ALARM_WDE2_INT | 1060221167Sgnn VXGE_HAL_WRDMA_INT_STATUS_WDE3_ALARM_WDE3_INT; 1061221167Sgnn 1062221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->wrdma_int_mask); 1063221167Sgnn 1064221167Sgnn val64 = VXGE_HAL_G3CMCT_ERR_REG_G3IF_SM_ERR | 1065221167Sgnn VXGE_HAL_G3CMCT_ERR_REG_G3IF_GDDR3_DECC | 1066221167Sgnn VXGE_HAL_G3CMCT_ERR_REG_G3IF_GDDR3_U_DECC | 1067221167Sgnn VXGE_HAL_G3CMCT_ERR_REG_G3IF_CTRL_FIFO_DECC; 1068221167Sgnn 1069221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->g3cmct_err_mask); 1070221167Sgnn 1071221167Sgnn val64 = VXGE_HAL_G3CMCT_INT_STATUS_ERR_G3IF_INT; 1072221167Sgnn 1073221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->g3cmct_int_mask); 1074221167Sgnn 1075221167Sgnn val64 = VXGE_HAL_GSSCC_ERR_REG_SSCC_SSR_DB_ERR(0x3) | 1076221167Sgnn VXGE_HAL_GSSCC_ERR_REG_SSCC_TSR_DB_ERR(0x3f) | 1077221167Sgnn VXGE_HAL_GSSCC_ERR_REG_SSCC_CP2STE_UFLOW_ERR | 1078221167Sgnn VXGE_HAL_GSSCC_ERR_REG_SSCC_CP2TTE_UFLOW_ERR; 1079221167Sgnn 1080221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->gsscc_err_mask); 1081221167Sgnn 1082221167Sgnn for (i = 0; i < 3; i++) { 1083221167Sgnn 1084221167Sgnn val64 = VXGE_HAL_GSSC_ERR0_REG_SSCC_STATE_DB_ERR(0xff) | 1085221167Sgnn VXGE_HAL_GSSC_ERR0_REG_SSCC_CM_RESP_DB_ERR(0xf) | 1086221167Sgnn VXGE_HAL_GSSC_ERR0_REG_SSCC_SSR_RESP_DB_ERR(0x3) | 1087221167Sgnn VXGE_HAL_GSSC_ERR0_REG_SSCC_TSR_RESP_DB_ERR(0x3f); 1088221167Sgnn 1089221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, 1090221167Sgnn &mrpcim_reg->gssc_err0_mask[i]); 1091221167Sgnn 1092221167Sgnn val64 = VXGE_HAL_GSSC_ERR1_REG_SSCC_CM_RESP_DB_ERR | 1093221167Sgnn VXGE_HAL_GSSC_ERR1_REG_SSCC_SCREQ_ERR | 1094221167Sgnn VXGE_HAL_GSSC_ERR1_REG_SSCC_CM_RESP_OFLOW_ERR | 1095221167Sgnn VXGE_HAL_GSSC_ERR1_REG_SSCC_CM_RESP_R_WN_ERR | 1096221167Sgnn VXGE_HAL_GSSC_ERR1_REG_SSCC_CM_RESP_UFLOW_ERR | 1097221167Sgnn VXGE_HAL_GSSC_ERR1_REG_SSCC_CM_REQ_OFLOW_ERR | 1098221167Sgnn VXGE_HAL_GSSC_ERR1_REG_SSCC_CM_REQ_UFLOW_ERR | 1099221167Sgnn VXGE_HAL_GSSC_ERR1_REG_SSCC_FSM_OFLOW_ERR | 1100221167Sgnn VXGE_HAL_GSSC_ERR1_REG_SSCC_FSM_UFLOW_ERR | 1101221167Sgnn VXGE_HAL_GSSC_ERR1_REG_SSCC_SSR_REQ_OFLOW_ERR | 1102221167Sgnn VXGE_HAL_GSSC_ERR1_REG_SSCC_SSR_REQ_UFLOW_ERR | 1103221167Sgnn VXGE_HAL_GSSC_ERR1_REG_SSCC_SSR_RESP_OFLOW_ERR | 1104221167Sgnn VXGE_HAL_GSSC_ERR1_REG_SSCC_SSR_RESP_R_WN_ERR | 1105221167Sgnn VXGE_HAL_GSSC_ERR1_REG_SSCC_SSR_RESP_UFLOW_ERR | 1106221167Sgnn VXGE_HAL_GSSC_ERR1_REG_SSCC_TSR_REQ_OFLOW_ERR | 1107221167Sgnn VXGE_HAL_GSSC_ERR1_REG_SSCC_TSR_REQ_UFLOW_ERR | 1108221167Sgnn VXGE_HAL_GSSC_ERR1_REG_SSCC_TSR_RESP_OFLOW_ERR | 1109221167Sgnn VXGE_HAL_GSSC_ERR1_REG_SSCC_TSR_RESP_R_WN_ERR | 1110221167Sgnn VXGE_HAL_GSSC_ERR1_REG_SSCC_TSR_RESP_UFLOW_ERR | 1111221167Sgnn VXGE_HAL_GSSC_ERR1_REG_SSCC_SCRESP_ERR; 1112221167Sgnn 1113221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, 1114221167Sgnn &mrpcim_reg->gssc_err1_mask[i]); 1115221167Sgnn 1116221167Sgnn } 1117221167Sgnn 1118221167Sgnn val64 = VXGE_HAL_GCMG1_INT_STATUS_GSSCC_ERR_GSSCC_INT | 1119221167Sgnn VXGE_HAL_GCMG1_INT_STATUS_GSSC0_ERR0_GSSC0_0_INT | 1120221167Sgnn VXGE_HAL_GCMG1_INT_STATUS_GSSC0_ERR1_GSSC0_1_INT | 1121221167Sgnn VXGE_HAL_GCMG1_INT_STATUS_GSSC1_ERR0_GSSC1_0_INT | 1122221167Sgnn VXGE_HAL_GCMG1_INT_STATUS_GSSC1_ERR1_GSSC1_1_INT | 1123221167Sgnn VXGE_HAL_GCMG1_INT_STATUS_GSSC2_ERR0_GSSC2_0_INT | 1124221167Sgnn VXGE_HAL_GCMG1_INT_STATUS_GSSC2_ERR1_GSSC2_1_INT; 1125221167Sgnn 1126221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->gcmg1_int_mask); 1127221167Sgnn 1128221167Sgnn val64 = VXGE_HAL_GXTMC_ERR_REG_XTMC_BDT_MEM_DB_ERR(0xf) | 1129221167Sgnn VXGE_HAL_GXTMC_ERR_REG_XTMC_CMC_RD_DATA_DB_ERR | 1130221167Sgnn VXGE_HAL_GXTMC_ERR_REG_XTMC_REQ_FIFO_ERR | 1131221167Sgnn VXGE_HAL_GXTMC_ERR_REG_XTMC_REQ_DATA_FIFO_ERR | 1132221167Sgnn VXGE_HAL_GXTMC_ERR_REG_XTMC_WR_RSP_FIFO_ERR | 1133221167Sgnn VXGE_HAL_GXTMC_ERR_REG_XTMC_RD_RSP_FIFO_ERR | 1134221167Sgnn VXGE_HAL_GXTMC_ERR_REG_XTMC_CMI_WRP_FIFO_ERR | 1135221167Sgnn VXGE_HAL_GXTMC_ERR_REG_XTMC_CMI_WRP_ERR | 1136221167Sgnn VXGE_HAL_GXTMC_ERR_REG_XTMC_CMI_RRP_FIFO_ERR | 1137221167Sgnn VXGE_HAL_GXTMC_ERR_REG_XTMC_CMI_RRP_ERR | 1138221167Sgnn VXGE_HAL_GXTMC_ERR_REG_XTMC_CMI_DATA_SM_ERR | 1139221167Sgnn VXGE_HAL_GXTMC_ERR_REG_XTMC_CMI_CMC0_IF_ERR | 1140221167Sgnn VXGE_HAL_GXTMC_ERR_REG_XTMC_BDT_CMI_CFC_SM_ERR | 1141221167Sgnn VXGE_HAL_GXTMC_ERR_REG_XTMC_BDT_CMI_DFETCH_CREDIT_OVERFLOW | 1142221167Sgnn VXGE_HAL_GXTMC_ERR_REG_XTMC_BDT_CMI_DFETCH_CREDIT_UNDERFLOW | 1143221167Sgnn VXGE_HAL_GXTMC_ERR_REG_XTMC_BDT_CMI_DFETCH_SM_ERR | 1144221167Sgnn VXGE_HAL_GXTMC_ERR_REG_XTMC_BDT_CMI_RCTRL_CREDIT_OVERFLOW | 1145221167Sgnn VXGE_HAL_GXTMC_ERR_REG_XTMC_BDT_CMI_RCTRL_CREDIT_UNDERFLOW | 1146221167Sgnn VXGE_HAL_GXTMC_ERR_REG_XTMC_BDT_CMI_RCTRL_SM_ERR | 1147221167Sgnn VXGE_HAL_GXTMC_ERR_REG_XTMC_BDT_CMI_WCOMPL_SM_ERR | 1148221167Sgnn VXGE_HAL_GXTMC_ERR_REG_XTMC_BDT_CMI_WCOMPL_TAG_ERR | 1149221167Sgnn VXGE_HAL_GXTMC_ERR_REG_XTMC_BDT_CMI_WREQ_SM_ERR | 1150221167Sgnn VXGE_HAL_GXTMC_ERR_REG_XTMC_BDT_CMI_WREQ_FIFO_ERR | 1151221167Sgnn VXGE_HAL_GXTMC_ERR_REG_XTMC_CP2BDT_RFIFO_POP_ERR | 1152221167Sgnn VXGE_HAL_GXTMC_ERR_REG_XTMC_XTMC_BDT_CMI_OP_ERR | 1153221167Sgnn VXGE_HAL_GXTMC_ERR_REG_XTMC_XTMC_BDT_DFETCH_OP_ERR | 1154221167Sgnn VXGE_HAL_GXTMC_ERR_REG_XTMC_XTMC_BDT_DFIFO_ERR | 1155221167Sgnn VXGE_HAL_GXTMC_ERR_REG_XTMC_CMI_ARB_SM_ERR; 1156221167Sgnn 1157221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->gxtmc_err_mask); 1158221167Sgnn 1159221167Sgnn val64 = VXGE_HAL_GCP_ERR_REG_CP_H2L2CP_FIFO_ERR | 1160221167Sgnn VXGE_HAL_GCP_ERR_REG_CP_STC2CP_FIFO_ERR | 1161221167Sgnn VXGE_HAL_GCP_ERR_REG_CP_STE2CP_FIFO_ERR | 1162221167Sgnn VXGE_HAL_GCP_ERR_REG_CP_TTE2CP_FIFO_ERR; 1163221167Sgnn 1164221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->gcp_err_mask); 1165221167Sgnn 1166221167Sgnn val64 = VXGE_HAL_CMC_ERR_REG_CMC_CMC_SM_ERR; 1167221167Sgnn 1168221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->cmc_err_mask); 1169221167Sgnn 1170221167Sgnn val64 = VXGE_HAL_GCMG2_INT_STATUS_GXTMC_ERR_GXTMC_INT | 1171221167Sgnn VXGE_HAL_GCMG2_INT_STATUS_GCP_ERR_GCP_INT | 1172221167Sgnn VXGE_HAL_GCMG2_INT_STATUS_CMC_ERR_CMC_INT; 1173221167Sgnn 1174221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->gcmg2_int_mask); 1175221167Sgnn 1176221167Sgnn val64 = VXGE_HAL_G3IFCMD_CML_ERR_REG_G3IF_SM_ERR; 1177221167Sgnn 1178221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, 1179221167Sgnn &mrpcim_reg->g3ifcmd_cml_err_mask); 1180221167Sgnn 1181221167Sgnn val64 = VXGE_HAL_G3IFCMD_CML_INT_STATUS_ERR_G3IF_INT; 1182221167Sgnn 1183221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, 1184221167Sgnn &mrpcim_reg->g3ifcmd_cml_int_mask); 1185221167Sgnn 1186221167Sgnn val64 = VXGE_HAL_G3IFCMD_CMU_ERR_REG_G3IF_SM_ERR; 1187221167Sgnn 1188221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, 1189221167Sgnn &mrpcim_reg->g3ifcmd_cmu_err_mask); 1190221167Sgnn 1191221167Sgnn val64 = VXGE_HAL_G3IFCMD_CMU_INT_STATUS_ERR_G3IF_INT; 1192221167Sgnn 1193221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, 1194221167Sgnn &mrpcim_reg->g3ifcmd_cmu_int_mask); 1195221167Sgnn 1196221167Sgnn val64 = VXGE_HAL_PSSCC_ERR_REG_SSCC_CP2STE_OFLOW_ERR | 1197221167Sgnn VXGE_HAL_PSSCC_ERR_REG_SSCC_CP2TTE_OFLOW_ERR; 1198221167Sgnn 1199221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, 1200221167Sgnn &mrpcim_reg->psscc_err_mask); 1201221167Sgnn 1202221167Sgnn val64 = VXGE_HAL_PCMG1_INT_STATUS_PSSCC_ERR_PSSCC_INT; 1203221167Sgnn 1204221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, 1205221167Sgnn &mrpcim_reg->pcmg1_int_mask); 1206221167Sgnn 1207221167Sgnn val64 = VXGE_HAL_PXTMC_ERR_REG_XTMC_XT_PIF_SRAM_DB_ERR(0x3) | 1208221167Sgnn VXGE_HAL_PXTMC_ERR_REG_XTMC_MPT_REQ_FIFO_ERR | 1209221167Sgnn VXGE_HAL_PXTMC_ERR_REG_XTMC_MPT_PRSP_FIFO_ERR | 1210221167Sgnn VXGE_HAL_PXTMC_ERR_REG_XTMC_MPT_WRSP_FIFO_ERR | 1211221167Sgnn VXGE_HAL_PXTMC_ERR_REG_XTMC_UPT_REQ_FIFO_ERR | 1212221167Sgnn VXGE_HAL_PXTMC_ERR_REG_XTMC_UPT_PRSP_FIFO_ERR | 1213221167Sgnn VXGE_HAL_PXTMC_ERR_REG_XTMC_UPT_WRSP_FIFO_ERR | 1214221167Sgnn VXGE_HAL_PXTMC_ERR_REG_XTMC_CPT_REQ_FIFO_ERR | 1215221167Sgnn VXGE_HAL_PXTMC_ERR_REG_XTMC_CPT_PRSP_FIFO_ERR | 1216221167Sgnn VXGE_HAL_PXTMC_ERR_REG_XTMC_CPT_WRSP_FIFO_ERR | 1217221167Sgnn VXGE_HAL_PXTMC_ERR_REG_XTMC_REQ_FIFO_ERR | 1218221167Sgnn VXGE_HAL_PXTMC_ERR_REG_XTMC_REQ_DATA_FIFO_ERR | 1219221167Sgnn VXGE_HAL_PXTMC_ERR_REG_XTMC_WR_RSP_FIFO_ERR | 1220221167Sgnn VXGE_HAL_PXTMC_ERR_REG_XTMC_RD_RSP_FIFO_ERR | 1221221167Sgnn VXGE_HAL_PXTMC_ERR_REG_XTMC_MPT_REQ_SHADOW_ERR | 1222221167Sgnn VXGE_HAL_PXTMC_ERR_REG_XTMC_MPT_RSP_SHADOW_ERR | 1223221167Sgnn VXGE_HAL_PXTMC_ERR_REG_XTMC_UPT_REQ_SHADOW_ERR | 1224221167Sgnn VXGE_HAL_PXTMC_ERR_REG_XTMC_UPT_RSP_SHADOW_ERR | 1225221167Sgnn VXGE_HAL_PXTMC_ERR_REG_XTMC_CPT_REQ_SHADOW_ERR | 1226221167Sgnn VXGE_HAL_PXTMC_ERR_REG_XTMC_CPT_RSP_SHADOW_ERR | 1227221167Sgnn VXGE_HAL_PXTMC_ERR_REG_XTMC_XIL_SHADOW_ERR | 1228221167Sgnn VXGE_HAL_PXTMC_ERR_REG_XTMC_ARB_SHADOW_ERR | 1229221167Sgnn VXGE_HAL_PXTMC_ERR_REG_XTMC_RAM_SHADOW_ERR | 1230221167Sgnn VXGE_HAL_PXTMC_ERR_REG_XTMC_CMW_SHADOW_ERR | 1231221167Sgnn VXGE_HAL_PXTMC_ERR_REG_XTMC_CMR_SHADOW_ERR | 1232221167Sgnn VXGE_HAL_PXTMC_ERR_REG_XTMC_MPT_REQ_FSM_ERR | 1233221167Sgnn VXGE_HAL_PXTMC_ERR_REG_XTMC_MPT_RSP_FSM_ERR | 1234221167Sgnn VXGE_HAL_PXTMC_ERR_REG_XTMC_UPT_REQ_FSM_ERR | 1235221167Sgnn VXGE_HAL_PXTMC_ERR_REG_XTMC_UPT_RSP_FSM_ERR | 1236221167Sgnn VXGE_HAL_PXTMC_ERR_REG_XTMC_CPT_REQ_FSM_ERR | 1237221167Sgnn VXGE_HAL_PXTMC_ERR_REG_XTMC_CPT_RSP_FSM_ERR | 1238221167Sgnn VXGE_HAL_PXTMC_ERR_REG_XTMC_XIL_FSM_ERR | 1239221167Sgnn VXGE_HAL_PXTMC_ERR_REG_XTMC_ARB_FSM_ERR | 1240221167Sgnn VXGE_HAL_PXTMC_ERR_REG_XTMC_CMW_FSM_ERR | 1241221167Sgnn VXGE_HAL_PXTMC_ERR_REG_XTMC_CMR_FSM_ERR | 1242221167Sgnn VXGE_HAL_PXTMC_ERR_REG_XTMC_MXP_RD_PROT_ERR | 1243221167Sgnn VXGE_HAL_PXTMC_ERR_REG_XTMC_UXP_RD_PROT_ERR | 1244221167Sgnn VXGE_HAL_PXTMC_ERR_REG_XTMC_CXP_RD_PROT_ERR | 1245221167Sgnn VXGE_HAL_PXTMC_ERR_REG_XTMC_MXP_WR_PROT_ERR | 1246221167Sgnn VXGE_HAL_PXTMC_ERR_REG_XTMC_UXP_WR_PROT_ERR | 1247221167Sgnn VXGE_HAL_PXTMC_ERR_REG_XTMC_CXP_WR_PROT_ERR | 1248221167Sgnn VXGE_HAL_PXTMC_ERR_REG_XTMC_MXP_INV_ADDR_ERR | 1249221167Sgnn VXGE_HAL_PXTMC_ERR_REG_XTMC_UXP_INV_ADDR_ERR | 1250221167Sgnn VXGE_HAL_PXTMC_ERR_REG_XTMC_CXP_INV_ADDR_ERR | 1251221167Sgnn VXGE_HAL_PXTMC_ERR_REG_XTMC_CP2BDT_DFIFO_PUSH_ERR | 1252221167Sgnn VXGE_HAL_PXTMC_ERR_REG_XTMC_CP2BDT_RFIFO_PUSH_ERR; 1253221167Sgnn 1254221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->pxtmc_err_mask); 1255221167Sgnn 1256221167Sgnn val64 = VXGE_HAL_CP_EXC_REG_CP_CP_CAUSE_CRIT_INT | 1257221167Sgnn VXGE_HAL_CP_EXC_REG_CP_CP_SERR; 1258221167Sgnn 1259221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->cp_exc_mask); 1260221167Sgnn 1261221167Sgnn val64 = VXGE_HAL_CP_ERR_REG_CP_CP_DCACHE_DB_ERR(0xff) | 1262221167Sgnn VXGE_HAL_CP_ERR_REG_CP_CP_ICACHE_DB_ERR(0x3) | 1263221167Sgnn VXGE_HAL_CP_ERR_REG_CP_CP_DTAG_DB_ERR | 1264221167Sgnn VXGE_HAL_CP_ERR_REG_CP_CP_ITAG_DB_ERR | 1265221167Sgnn VXGE_HAL_CP_ERR_REG_CP_CP_TRACE_DB_ERR | 1266221167Sgnn VXGE_HAL_CP_ERR_REG_CP_DMA2CP_DB_ERR | 1267221167Sgnn VXGE_HAL_CP_ERR_REG_CP_MP2CP_DB_ERR | 1268221167Sgnn VXGE_HAL_CP_ERR_REG_CP_QCC2CP_DB_ERR | 1269221167Sgnn VXGE_HAL_CP_ERR_REG_CP_STC2CP_DB_ERR(0x3) | 1270221167Sgnn VXGE_HAL_CP_ERR_REG_CP_H2L2CP_FIFO_ERR | 1271221167Sgnn VXGE_HAL_CP_ERR_REG_CP_STC2CP_FIFO_ERR | 1272221167Sgnn VXGE_HAL_CP_ERR_REG_CP_STE2CP_FIFO_ERR | 1273221167Sgnn VXGE_HAL_CP_ERR_REG_CP_TTE2CP_FIFO_ERR | 1274221167Sgnn VXGE_HAL_CP_ERR_REG_CP_SWIF2CP_FIFO_ERR | 1275221167Sgnn VXGE_HAL_CP_ERR_REG_CP_CP2DMA_FIFO_ERR | 1276221167Sgnn VXGE_HAL_CP_ERR_REG_CP_DAM2CP_FIFO_ERR | 1277221167Sgnn VXGE_HAL_CP_ERR_REG_CP_MP2CP_FIFO_ERR | 1278221167Sgnn VXGE_HAL_CP_ERR_REG_CP_QCC2CP_FIFO_ERR | 1279221167Sgnn VXGE_HAL_CP_ERR_REG_CP_DMA2CP_FIFO_ERR | 1280221167Sgnn VXGE_HAL_CP_ERR_REG_CP_CP_WAKE_FSM_INTEGRITY_ERR | 1281221167Sgnn VXGE_HAL_CP_ERR_REG_CP_CP_PMON_FSM_INTEGRITY_ERR | 1282221167Sgnn VXGE_HAL_CP_ERR_REG_CP_DMA_RD_SHADOW_ERR | 1283221167Sgnn VXGE_HAL_CP_ERR_REG_CP_PIFT_CREDIT_ERR; 1284221167Sgnn 1285221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->cp_err_mask); 1286221167Sgnn 1287221167Sgnn val64 = VXGE_HAL_PCMG2_INT_STATUS_PXTMC_ERR_PXTMC_INT | 1288221167Sgnn VXGE_HAL_PCMG2_INT_STATUS_CP_EXC_CP_XT_EXC_INT | 1289221167Sgnn VXGE_HAL_PCMG2_INT_STATUS_CP_ERR_CP_ERR_INT; 1290221167Sgnn 1291221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->pcmg2_int_mask); 1292221167Sgnn 1293221167Sgnn val64 = VXGE_HAL_DAM_ERR_REG_DAM_RDSB_ECC_DB_ERR | 1294221167Sgnn VXGE_HAL_DAM_ERR_REG_DAM_WRSB_ECC_DB_ERR | 1295221167Sgnn VXGE_HAL_DAM_ERR_REG_DAM_HPPEDAT_ECC_DB_ERR | 1296221167Sgnn VXGE_HAL_DAM_ERR_REG_DAM_LPPEDAT_ECC_DB_ERR | 1297221167Sgnn VXGE_HAL_DAM_ERR_REG_DAM_WRRESP_ECC_DB_ERR | 1298221167Sgnn VXGE_HAL_DAM_ERR_REG_DAM_HPRD_ERR | 1299221167Sgnn VXGE_HAL_DAM_ERR_REG_DAM_LPRD_0_ERR | 1300221167Sgnn VXGE_HAL_DAM_ERR_REG_DAM_LPRD_1_ERR | 1301221167Sgnn VXGE_HAL_DAM_ERR_REG_DAM_HPPEDAT_OVERFLOW_ERR | 1302221167Sgnn VXGE_HAL_DAM_ERR_REG_DAM_LPPEDAT_OVERFLOW_ERR | 1303221167Sgnn VXGE_HAL_DAM_ERR_REG_DAM_WRRESP_OVERFLOW_ERR | 1304221167Sgnn VXGE_HAL_DAM_ERR_REG_DAM_SM_ERR; 1305221167Sgnn 1306221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->dam_err_mask); 1307221167Sgnn 1308221167Sgnn val64 = VXGE_HAL_PCMG3_INT_STATUS_DAM_ERR_DAM_INT; 1309221167Sgnn 1310221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->pcmg3_int_mask); 1311221167Sgnn 1312221167Sgnn val64 = VXGE_HAL_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE0_DB_ERR(0x3) | 1313221167Sgnn VXGE_HAL_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE1_DB_ERR(0x3) | 1314221167Sgnn VXGE_HAL_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE2_DB_ERR(0x3) | 1315221167Sgnn VXGE_HAL_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE3_DB_ERR(0x3) | 1316221167Sgnn VXGE_HAL_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE4_DB_ERR(0x3) | 1317221167Sgnn VXGE_HAL_XMAC_GEN_ERR_REG_XMACJ_XMAC_FSM_ERR; 1318221167Sgnn 1319221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->xmac_gen_err_mask); 1320221167Sgnn 1321221167Sgnn val64 = VXGE_HAL_XGXS_GEN_ERR_REG_XGXS_XGXS_FSM_ERR; 1322221167Sgnn 1323221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->xgxs_gen_err_mask); 1324221167Sgnn 1325221167Sgnn val64 = VXGE_HAL_ASIC_NTWK_ERR_REG_XMACJ_NTWK_DOWN | 1326221167Sgnn VXGE_HAL_ASIC_NTWK_ERR_REG_XMACJ_NTWK_UP | 1327221167Sgnn VXGE_HAL_ASIC_NTWK_ERR_REG_XMACJ_NTWK_WENT_DOWN | 1328221167Sgnn VXGE_HAL_ASIC_NTWK_ERR_REG_XMACJ_NTWK_WENT_UP | 1329221167Sgnn VXGE_HAL_ASIC_NTWK_ERR_REG_XMACJ_NTWK_REAFFIRMED_FAULT | 1330221167Sgnn VXGE_HAL_ASIC_NTWK_ERR_REG_XMACJ_NTWK_REAFFIRMED_OK; 1331221167Sgnn 1332221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, 1333221167Sgnn &mrpcim_reg->asic_ntwk_err_mask); 1334221167Sgnn 1335221167Sgnn val64 = VXGE_HAL_XGMAC_INT_STATUS_XMAC_GEN_ERR_XMAC_GEN_INT | 1336221167Sgnn VXGE_HAL_XGMAC_INT_STATUS_XGXS_GEN_ERR_XGXS_GEN_INT | 1337221167Sgnn VXGE_HAL_XGMAC_INT_STATUS_ASIC_NTWK_ERR_ASIC_NTWK_INT; 1338221167Sgnn 1339221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->xgmac_int_mask); 1340221167Sgnn 1341221167Sgnn val64 = 1342221167Sgnn VXGE_HAL_RXMAC_ECC_ERR_REG_RMAC_PORT0_RMAC_RTS_PART_DB_ERR(0xf) | 1343221167Sgnn VXGE_HAL_RXMAC_ECC_ERR_REG_RMAC_PORT1_RMAC_RTS_PART_DB_ERR(0xf) | 1344221167Sgnn VXGE_HAL_RXMAC_ECC_ERR_REG_RMAC_PORT2_RMAC_RTS_PART_DB_ERR(0xf) | 1345221167Sgnn VXGE_HAL_RXMAC_ECC_ERR_REG_RTSJ_RMAC_DA_LKP_PRT0_DB_ERR(0x3) | 1346221167Sgnn VXGE_HAL_RXMAC_ECC_ERR_REG_RTSJ_RMAC_DA_LKP_PRT1_DB_ERR(0x3) | 1347221167Sgnn VXGE_HAL_RXMAC_ECC_ERR_REG_RTSJ_RMAC_VID_LKP_DB_ERR | 1348221167Sgnn VXGE_HAL_RXMAC_ECC_ERR_REG_RTSJ_RMAC_PN_LKP_PRT0_DB_ERR | 1349221167Sgnn VXGE_HAL_RXMAC_ECC_ERR_REG_RTSJ_RMAC_PN_LKP_PRT1_DB_ERR | 1350221167Sgnn VXGE_HAL_RXMAC_ECC_ERR_REG_RTSJ_RMAC_PN_LKP_PRT2_DB_ERR | 1351221167Sgnn VXGE_HAL_RXMAC_ECC_ERR_REG_RTSJ_RMAC_RTH_MASK_DB_ERR(0x3f) | 1352221167Sgnn VXGE_HAL_RXMAC_ECC_ERR_REG_RTSJ_RMAC_RTH_LKP_DB_ERR(0x7) | 1353221167Sgnn VXGE_HAL_RXMAC_ECC_ERR_REG_RTSJ_RMAC_DS_LKP_DB_ERR; 1354221167Sgnn 1355221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, 1356221167Sgnn &mrpcim_reg->rxmac_ecc_err_mask); 1357221167Sgnn 1358221167Sgnn val64 = VXGE_HAL_RXMAC_VARIOUS_ERR_REG_RMAC_RMAC_PORT0_FSM_ERR | 1359221167Sgnn VXGE_HAL_RXMAC_VARIOUS_ERR_REG_RMAC_RMAC_PORT1_FSM_ERR | 1360221167Sgnn VXGE_HAL_RXMAC_VARIOUS_ERR_REG_RMAC_RMAC_PORT2_FSM_ERR | 1361221167Sgnn VXGE_HAL_RXMAC_VARIOUS_ERR_REG_RMACJ_RMACJ_FSM_ERR; 1362221167Sgnn 1363221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, 1364221167Sgnn &mrpcim_reg->rxmac_various_err_mask); 1365221167Sgnn 1366221167Sgnn val64 = VXGE_HAL_RXMAC_INT_STATUS_RXMAC_ECC_ERR_RXMAC_ECC_INT | 1367221167Sgnn VXGE_HAL_RXMAC_INT_STATUS_RXMAC_VARIOUS_ERR_RXMAC_VARIOUS_INT; 1368221167Sgnn 1369221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->rxmac_int_mask); 1370221167Sgnn 1371221167Sgnn val64 = VXGE_HAL_TXMAC_GEN_ERR_REG_TMACJ_PERMANENT_STOP; 1372221167Sgnn 1373221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, 1374221167Sgnn &mrpcim_reg->txmac_gen_err_mask); 1375221167Sgnn 1376221167Sgnn val64 = VXGE_HAL_TXMAC_ECC_ERR_REG_TMACJ_TMAC_TPA2MAC_DB_ERR | 1377221167Sgnn VXGE_HAL_TXMAC_ECC_ERR_REG_TMACJ_TMAC_TPA2M_SB_DB_ERR | 1378221167Sgnn VXGE_HAL_TXMAC_ECC_ERR_REG_TMACJ_TMAC_TPA2M_DA_DB_ERR | 1379221167Sgnn VXGE_HAL_TXMAC_ECC_ERR_REG_TMAC_TMAC_PORT0_FSM_ERR | 1380221167Sgnn VXGE_HAL_TXMAC_ECC_ERR_REG_TMAC_TMAC_PORT1_FSM_ERR | 1381221167Sgnn VXGE_HAL_TXMAC_ECC_ERR_REG_TMAC_TMAC_PORT2_FSM_ERR | 1382221167Sgnn VXGE_HAL_TXMAC_ECC_ERR_REG_TMACJ_TMACJ_FSM_ERR; 1383221167Sgnn 1384221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, 1385221167Sgnn &mrpcim_reg->txmac_ecc_err_mask); 1386221167Sgnn 1387221167Sgnn val64 = VXGE_HAL_TMAC_INT_STATUS_TXMAC_GEN_ERR_TXMAC_GEN_INT | 1388221167Sgnn VXGE_HAL_TMAC_INT_STATUS_TXMAC_ECC_ERR_TXMAC_ECC_INT; 1389221167Sgnn 1390221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->tmac_int_mask); 1391221167Sgnn 1392221167Sgnn val64 = VXGE_HAL_G3IFCMD_FB_ERR_REG_G3IF_SM_ERR; 1393221167Sgnn 1394221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, 1395221167Sgnn &mrpcim_reg->g3ifcmd_fb_err_mask); 1396221167Sgnn 1397221167Sgnn val64 = VXGE_HAL_G3IFCMD_FB_INT_STATUS_ERR_G3IF_INT; 1398221167Sgnn 1399221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, 1400221167Sgnn &mrpcim_reg->g3ifcmd_fb_int_mask); 1401221167Sgnn 1402221167Sgnn val64 = VXGE_HAL_MC_ERR_REG_MC_XFMD_MEM_ECC_DB_ERR_A | 1403221167Sgnn VXGE_HAL_MC_ERR_REG_MC_XFMD_MEM_ECC_DB_ERR_B | 1404221167Sgnn VXGE_HAL_MC_ERR_REG_MC_G3IF_RD_FIFO_ECC_DB_ERR | 1405221167Sgnn VXGE_HAL_MC_ERR_REG_MC_MIRI_ECC_DB_ERR_0 | 1406221167Sgnn VXGE_HAL_MC_ERR_REG_MC_MIRI_ECC_DB_ERR_1 | 1407221167Sgnn VXGE_HAL_MC_ERR_REG_MC_SM_ERR; 1408221167Sgnn 1409221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->mc_err_mask); 1410221167Sgnn 1411221167Sgnn val64 = VXGE_HAL_GROCRC_ALARM_REG_XFMD_WR_FIFO_ERR | 1412221167Sgnn VXGE_HAL_GROCRC_ALARM_REG_WDE2MSR_RD_FIFO_ERR; 1413221167Sgnn 1414221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->grocrc_alarm_mask); 1415221167Sgnn 1416221167Sgnn val64 = VXGE_HAL_FAU_ECC_ERR_REG_FAU_PORT0_FAU_MAC2F_N_DB_ERR | 1417221167Sgnn VXGE_HAL_FAU_ECC_ERR_REG_FAU_PORT0_FAU_MAC2F_W_DB_ERR(0x3) | 1418221167Sgnn VXGE_HAL_FAU_ECC_ERR_REG_FAU_PORT1_FAU_MAC2F_N_DB_ERR | 1419221167Sgnn VXGE_HAL_FAU_ECC_ERR_REG_FAU_PORT1_FAU_MAC2F_W_DB_ERR(0x3) | 1420221167Sgnn VXGE_HAL_FAU_ECC_ERR_REG_FAU_PORT2_FAU_MAC2F_N_DB_ERR | 1421221167Sgnn VXGE_HAL_FAU_ECC_ERR_REG_FAU_PORT2_FAU_MAC2F_W_DB_ERR(0x3) | 1422221167Sgnn VXGE_HAL_FAU_ECC_ERR_REG_FAU_FAU_XFMD_INS_DB_ERR(0x3) | 1423221167Sgnn VXGE_HAL_FAU_ECC_ERR_REG_FAUJ_FAU_FSM_ERR; 1424221167Sgnn 1425221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->fau_ecc_err_mask); 1426221167Sgnn 1427221167Sgnn val64 = VXGE_HAL_MC_INT_STATUS_MC_ERR_MC_INT | 1428221167Sgnn VXGE_HAL_MC_INT_STATUS_GROCRC_ALARM_ROCRC_INT | 1429221167Sgnn VXGE_HAL_MC_INT_STATUS_FAU_ECC_ERR_FAU_ECC_INT; 1430221167Sgnn 1431221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->mc_int_mask); 1432221167Sgnn 1433221167Sgnn val64 = VXGE_HAL_G3FBCT_ERR_REG_G3IF_SM_ERR | 1434221167Sgnn VXGE_HAL_G3FBCT_ERR_REG_G3IF_GDDR3_DECC | 1435221167Sgnn VXGE_HAL_G3FBCT_ERR_REG_G3IF_GDDR3_U_DECC | 1436221167Sgnn VXGE_HAL_G3FBCT_ERR_REG_G3IF_CTRL_FIFO_DECC; 1437221167Sgnn 1438221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->g3fbct_err_mask); 1439221167Sgnn 1440221167Sgnn val64 = VXGE_HAL_G3FBCT_INT_STATUS_ERR_G3IF_INT; 1441221167Sgnn 1442221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->g3fbct_int_mask); 1443221167Sgnn 1444221167Sgnn val64 = VXGE_HAL_ORP_ERR_REG_ORP_FIFO_DB_ERR | 1445221167Sgnn VXGE_HAL_ORP_ERR_REG_ORP_XFMD_FIFO_UFLOW_ERR | 1446221167Sgnn VXGE_HAL_ORP_ERR_REG_ORP_FRM_FIFO_UFLOW_ERR | 1447221167Sgnn VXGE_HAL_ORP_ERR_REG_ORP_XFMD_RCV_FSM_ERR | 1448221167Sgnn VXGE_HAL_ORP_ERR_REG_ORP_OUTREAD_FSM_ERR | 1449221167Sgnn VXGE_HAL_ORP_ERR_REG_ORP_OUTQEM_FSM_ERR | 1450221167Sgnn VXGE_HAL_ORP_ERR_REG_ORP_XFMD_RCV_SHADOW_ERR | 1451221167Sgnn VXGE_HAL_ORP_ERR_REG_ORP_OUTREAD_SHADOW_ERR | 1452221167Sgnn VXGE_HAL_ORP_ERR_REG_ORP_OUTQEM_SHADOW_ERR | 1453221167Sgnn VXGE_HAL_ORP_ERR_REG_ORP_OUTFRM_SHADOW_ERR | 1454221167Sgnn VXGE_HAL_ORP_ERR_REG_ORP_OPTPRS_SHADOW_ERR; 1455221167Sgnn 1456221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->orp_err_mask); 1457221167Sgnn 1458221167Sgnn val64 = VXGE_HAL_PTM_ALARM_REG_PTM_RDCTRL_SYNC_ERR | 1459221167Sgnn VXGE_HAL_PTM_ALARM_REG_PTM_RDCTRL_FIFO_ERR | 1460221167Sgnn VXGE_HAL_PTM_ALARM_REG_XFMD_RD_FIFO_ERR | 1461221167Sgnn VXGE_HAL_PTM_ALARM_REG_WDE2MSR_WR_FIFO_ERR | 1462221167Sgnn VXGE_HAL_PTM_ALARM_REG_PTM_FRMM_ECC_DB_ERR(0x3); 1463221167Sgnn 1464221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->ptm_alarm_mask); 1465221167Sgnn 1466221167Sgnn val64 = VXGE_HAL_TPA_ERROR_REG_TPA_FSM_ERR_ALARM | 1467221167Sgnn VXGE_HAL_TPA_ERROR_REG_TPA_TPA_DA_LKUP_PRT0_DB_ERR; 1468221167Sgnn 1469221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->tpa_error_mask); 1470221167Sgnn 1471221167Sgnn val64 = VXGE_HAL_TPA_INT_STATUS_ORP_ERR_ORP_INT | 1472221167Sgnn VXGE_HAL_TPA_INT_STATUS_PTM_ALARM_PTM_INT | 1473221167Sgnn VXGE_HAL_TPA_INT_STATUS_TPA_ERROR_TPA_INT; 1474221167Sgnn 1475221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->tpa_int_mask); 1476221167Sgnn 1477221167Sgnn val64 = VXGE_HAL_KDFC_ERR_REG_KDFC_KDFC_ECC_DB_ERR | 1478221167Sgnn VXGE_HAL_KDFC_ERR_REG_KDFC_KDFC_SM_ERR_ALARM; 1479221167Sgnn 1480221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->kdfc_err_mask); 1481221167Sgnn 1482221167Sgnn val64 = VXGE_HAL_DOORBELL_INT_STATUS_KDFC_ERR_REG_TXDMA_KDFC_INT; 1483221167Sgnn 1484221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->doorbell_int_mask); 1485221167Sgnn 1486221167Sgnn val64 = VXGE_HAL_TIM_ERR_REG_TIM_VBLS_DB_ERR | 1487221167Sgnn VXGE_HAL_TIM_ERR_REG_TIM_BMAP_PA_DB_ERR | 1488221167Sgnn VXGE_HAL_TIM_ERR_REG_TIM_BMAP_PB_DB_ERR | 1489221167Sgnn VXGE_HAL_TIM_ERR_REG_TIM_BMAP_MSG_DB_ERR | 1490221167Sgnn VXGE_HAL_TIM_ERR_REG_TIM_BMAP_MEM_CNTRL_SM_ERR | 1491221167Sgnn VXGE_HAL_TIM_ERR_REG_TIM_BMAP_MSG_MEM_CNTRL_SM_ERR | 1492221167Sgnn VXGE_HAL_TIM_ERR_REG_TIM_MPIF_PCIWR_ERR | 1493221167Sgnn VXGE_HAL_TIM_ERR_REG_TIM_ROCRC_BMAP_UPDT_FIFO_ERR | 1494221167Sgnn VXGE_HAL_TIM_ERR_REG_TIM_CREATE_BMAPMSG_FIFO_ERR; 1495221167Sgnn 1496221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->tim_err_mask); 1497221167Sgnn 1498221167Sgnn val64 = VXGE_HAL_MSG_EXC_REG_MP_MXP_CAUSE_CRIT_INT | 1499221167Sgnn VXGE_HAL_MSG_EXC_REG_UP_UXP_CAUSE_CRIT_INT | 1500221167Sgnn VXGE_HAL_MSG_EXC_REG_MP_MXP_SERR | 1501221167Sgnn VXGE_HAL_MSG_EXC_REG_UP_UXP_SERR; 1502221167Sgnn 1503221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->msg_exc_mask); 1504221167Sgnn 1505221167Sgnn val64 = VXGE_HAL_MSG_ERR_REG_UP_UXP_WAKE_FSM_INTEGRITY_ERR | 1506221167Sgnn VXGE_HAL_MSG_ERR_REG_MP_MXP_WAKE_FSM_INTEGRITY_ERR | 1507221167Sgnn VXGE_HAL_MSG_ERR_REG_MSG_QUE_DMQ_DMA_READ_CMD_FSM_INTEGRITY_ERR | 1508221167Sgnn VXGE_HAL_MSG_ERR_REG_MSG_QUE_DMQ_DMA_RESP_FSM_INTEGRITY_ERR | 1509221167Sgnn VXGE_HAL_MSG_ERR_REG_MSG_QUE_DMQ_OWN_FSM_INTEGRITY_ERR | 1510221167Sgnn VXGE_HAL_MSG_ERR_REG_MSG_QUE_PDA_ACC_FSM_INTEGRITY_ERR | 1511221167Sgnn VXGE_HAL_MSG_ERR_REG_MP_MXP_PMON_FSM_INTEGRITY_ERR | 1512221167Sgnn VXGE_HAL_MSG_ERR_REG_UP_UXP_PMON_FSM_INTEGRITY_ERR | 1513221167Sgnn VXGE_HAL_MSG_ERR_REG_MSG_XFMDQRY_FSM_INTEGRITY_ERR | 1514221167Sgnn VXGE_HAL_MSG_ERR_REG_MSG_FRMQRY_FSM_INTEGRITY_ERR | 1515221167Sgnn VXGE_HAL_MSG_ERR_REG_MSG_QUE_UMQ_WRITE_FSM_INTEGRITY_ERR | 1516221167Sgnn VXGE_HAL_MSG_ERR_REG_MSG_QUE_UMQ_BWR_PF_FSM_INTEGRITY_ERR | 1517221167Sgnn VXGE_HAL_MSG_ERR_REG_MSG_QUE_REG_RESP_FIFO_ERR | 1518221167Sgnn VXGE_HAL_MSG_ERR_REG_UP_UXP_DTAG_DB_ERR | 1519221167Sgnn VXGE_HAL_MSG_ERR_REG_UP_UXP_ITAG_DB_ERR | 1520221167Sgnn VXGE_HAL_MSG_ERR_REG_MP_MXP_DTAG_DB_ERR | 1521221167Sgnn VXGE_HAL_MSG_ERR_REG_MP_MXP_ITAG_DB_ERR | 1522221167Sgnn VXGE_HAL_MSG_ERR_REG_UP_UXP_TRACE_DB_ERR | 1523221167Sgnn VXGE_HAL_MSG_ERR_REG_MP_MXP_TRACE_DB_ERR | 1524221167Sgnn VXGE_HAL_MSG_ERR_REG_MSG_QUE_CMG2MSG_DB_ERR | 1525221167Sgnn VXGE_HAL_MSG_ERR_REG_MSG_QUE_TXPE2MSG_DB_ERR | 1526221167Sgnn VXGE_HAL_MSG_ERR_REG_MSG_QUE_RXPE2MSG_DB_ERR | 1527221167Sgnn VXGE_HAL_MSG_ERR_REG_MSG_QUE_RPE2MSG_DB_ERR | 1528221167Sgnn VXGE_HAL_MSG_ERR_REG_MSG_QUE_REG_READ_FIFO_ERR | 1529221167Sgnn VXGE_HAL_MSG_ERR_REG_MSG_QUE_MXP2UXP_FIFO_ERR | 1530221167Sgnn VXGE_HAL_MSG_ERR_REG_MSG_QUE_KDFC_SIF_FIFO_ERR | 1531221167Sgnn VXGE_HAL_MSG_ERR_REG_MSG_QUE_CXP2SWIF_FIFO_ERR | 1532221167Sgnn VXGE_HAL_MSG_ERR_REG_MSG_QUE_UMQ_DB_ERR | 1533221167Sgnn VXGE_HAL_MSG_ERR_REG_MSG_QUE_BWR_PF_DB_ERR | 1534221167Sgnn VXGE_HAL_MSG_ERR_REG_MSG_QUE_BWR_SIF_FIFO_ERR | 1535221167Sgnn VXGE_HAL_MSG_ERR_REG_MSG_QUE_DMQ_ECC_DB_ERR | 1536221167Sgnn VXGE_HAL_MSG_ERR_REG_MSG_QUE_DMA_READ_FIFO_ERR | 1537221167Sgnn VXGE_HAL_MSG_ERR_REG_MSG_QUE_DMA_RESP_ECC_DB_ERR | 1538221167Sgnn VXGE_HAL_MSG_ERR_REG_MSG_QUE_UXP2MXP_FIFO_ERR; 1539221167Sgnn 1540221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->msg_err_mask); 1541221167Sgnn 1542221167Sgnn val64 = 1543221167Sgnn VXGE_HAL_MSG_ERR2_REG_MSG_QUE_CMG2MSG_DISPATCH_FSM_INTEGRITY_ERR | 1544221167Sgnn VXGE_HAL_MSG_ERR2_REG_MSG_QUE_DMQ_DISPATCH_FSM_INTEGRITY_ERR | 1545221167Sgnn VXGE_HAL_MSG_ERR2_REG_MSG_QUE_SWIF_DISPATCH_FSM_INTEGRITY_ERR | 1546221167Sgnn VXGE_HAL_MSG_ERR2_REG_MSG_QUE_PIC_WRITE_FSM_INTEGRITY_ERR | 1547221167Sgnn VXGE_HAL_MSG_ERR2_REG_MSG_QUE_SWIFREG_FSM_INTEGRITY_ERR | 1548221167Sgnn VXGE_HAL_MSG_ERR2_REG_MSG_QUE_TIM_WRITE_FSM_INTEGRITY_ERR | 1549221167Sgnn VXGE_HAL_MSG_ERR2_REG_MSG_QUE_UMQ_TA_FSM_INTEGRITY_ERR | 1550221167Sgnn VXGE_HAL_MSG_ERR2_REG_MSG_QUE_TXPE_TA_FSM_INTEGRITY_ERR | 1551221167Sgnn VXGE_HAL_MSG_ERR2_REG_MSG_QUE_RXPE_TA_FSM_INTEGRITY_ERR | 1552221167Sgnn VXGE_HAL_MSG_ERR2_REG_MSG_QUE_SWIF_TA_FSM_INTEGRITY_ERR | 1553221167Sgnn VXGE_HAL_MSG_ERR2_REG_MSG_QUE_DMA_TA_FSM_INTEGRITY_ERR | 1554221167Sgnn VXGE_HAL_MSG_ERR2_REG_MSG_QUE_CP_TA_FSM_INTEGRITY_ERR | 1555221167Sgnn VXGE_HAL_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA16_FSM_INTEGRITY_ERR | 1556221167Sgnn VXGE_HAL_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA15_FSM_INTEGRITY_ERR | 1557221167Sgnn VXGE_HAL_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA14_FSM_INTEGRITY_ERR | 1558221167Sgnn VXGE_HAL_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA13_FSM_INTEGRITY_ERR | 1559221167Sgnn VXGE_HAL_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA12_FSM_INTEGRITY_ERR | 1560221167Sgnn VXGE_HAL_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA11_FSM_INTEGRITY_ERR | 1561221167Sgnn VXGE_HAL_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA10_FSM_INTEGRITY_ERR | 1562221167Sgnn VXGE_HAL_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA9_FSM_INTEGRITY_ERR | 1563221167Sgnn VXGE_HAL_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA8_FSM_INTEGRITY_ERR | 1564221167Sgnn VXGE_HAL_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA7_FSM_INTEGRITY_ERR | 1565221167Sgnn VXGE_HAL_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA6_FSM_INTEGRITY_ERR | 1566221167Sgnn VXGE_HAL_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA5_FSM_INTEGRITY_ERR | 1567221167Sgnn VXGE_HAL_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA4_FSM_INTEGRITY_ERR | 1568221167Sgnn VXGE_HAL_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA3_FSM_INTEGRITY_ERR | 1569221167Sgnn VXGE_HAL_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA2_FSM_INTEGRITY_ERR | 1570221167Sgnn VXGE_HAL_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA1_FSM_INTEGRITY_ERR | 1571221167Sgnn VXGE_HAL_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA0_FSM_INTEGRITY_ERR | 1572221167Sgnn VXGE_HAL_MSG_ERR2_REG_MSG_QUE_FBMC_OWN_FSM_INTEGRITY_ERR | 1573221167Sgnn VXGE_HAL_MSG_ERR2_REG_MSG_QUE_TXPE2MSG_DISPATCH_FSM_INTEGRITY_ERR | 1574221167Sgnn VXGE_HAL_MSG_ERR2_REG_MSG_QUE_RXPE2MSG_DISPATCH_FSM_INTEGRITY_ERR | 1575221167Sgnn VXGE_HAL_MSG_ERR2_REG_MSG_QUE_RPE2MSG_DISPATCH_FSM_INTEGRITY_ERR | 1576221167Sgnn VXGE_HAL_MSG_ERR2_REG_MP_MP_PIFT_IF_CREDIT_CNT_ERR | 1577221167Sgnn VXGE_HAL_MSG_ERR2_REG_UP_UP_PIFT_IF_CREDIT_CNT_ERR | 1578221167Sgnn VXGE_HAL_MSG_ERR2_REG_MSG_QUE_UMQ2PIC_CMD_FIFO_ERR | 1579221167Sgnn VXGE_HAL_MSG_ERR2_REG_TIM_TIM2MSG_CMD_FIFO_ERR; 1580221167Sgnn 1581221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->msg_err2_mask); 1582221167Sgnn 1583221167Sgnn val64 = VXGE_HAL_MSG_ERR3_REG_UP_UXP_DCACHE_DB_ERR0 | 1584221167Sgnn VXGE_HAL_MSG_ERR3_REG_UP_UXP_DCACHE_DB_ERR1 | 1585221167Sgnn VXGE_HAL_MSG_ERR3_REG_UP_UXP_DCACHE_DB_ERR2 | 1586221167Sgnn VXGE_HAL_MSG_ERR3_REG_UP_UXP_DCACHE_DB_ERR3 | 1587221167Sgnn VXGE_HAL_MSG_ERR3_REG_UP_UXP_DCACHE_DB_ERR4 | 1588221167Sgnn VXGE_HAL_MSG_ERR3_REG_UP_UXP_DCACHE_DB_ERR5 | 1589221167Sgnn VXGE_HAL_MSG_ERR3_REG_UP_UXP_DCACHE_DB_ERR6 | 1590221167Sgnn VXGE_HAL_MSG_ERR3_REG_UP_UXP_DCACHE_DB_ERR7 | 1591221167Sgnn VXGE_HAL_MSG_ERR3_REG_UP_UXP_ICACHE_DB_ERR0 | 1592221167Sgnn VXGE_HAL_MSG_ERR3_REG_UP_UXP_ICACHE_DB_ERR1 | 1593221167Sgnn VXGE_HAL_MSG_ERR3_REG_MP_MXP_DCACHE_DB_ERR0 | 1594221167Sgnn VXGE_HAL_MSG_ERR3_REG_MP_MXP_DCACHE_DB_ERR1 | 1595221167Sgnn VXGE_HAL_MSG_ERR3_REG_MP_MXP_DCACHE_DB_ERR2 | 1596221167Sgnn VXGE_HAL_MSG_ERR3_REG_MP_MXP_DCACHE_DB_ERR3 | 1597221167Sgnn VXGE_HAL_MSG_ERR3_REG_MP_MXP_DCACHE_DB_ERR4 | 1598221167Sgnn VXGE_HAL_MSG_ERR3_REG_MP_MXP_DCACHE_DB_ERR5 | 1599221167Sgnn VXGE_HAL_MSG_ERR3_REG_MP_MXP_DCACHE_DB_ERR6 | 1600221167Sgnn VXGE_HAL_MSG_ERR3_REG_MP_MXP_DCACHE_DB_ERR7 | 1601221167Sgnn VXGE_HAL_MSG_ERR3_REG_MP_MXP_ICACHE_DB_ERR0 | 1602221167Sgnn VXGE_HAL_MSG_ERR3_REG_MP_MXP_ICACHE_DB_ERR1; 1603221167Sgnn 1604221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->msg_err3_mask); 1605221167Sgnn 1606221167Sgnn val64 = VXGE_HAL_MSG_INT_STATUS_TIM_ERR_TIM_INT | 1607221167Sgnn VXGE_HAL_MSG_INT_STATUS_MSG_EXC_MSG_XT_EXC_INT | 1608221167Sgnn VXGE_HAL_MSG_INT_STATUS_MSG_ERR3_MSG_ERR3_INT | 1609221167Sgnn VXGE_HAL_MSG_INT_STATUS_MSG_ERR2_MSG_ERR2_INT | 1610221167Sgnn VXGE_HAL_MSG_INT_STATUS_MSG_ERR_MSG_ERR_INT; 1611221167Sgnn 1612221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->msg_int_mask); 1613221167Sgnn 1614221167Sgnn val64 = VXGE_HAL_MRPCIM_GENERAL_INT_STATUS_PIC_INT | 1615221167Sgnn VXGE_HAL_MRPCIM_GENERAL_INT_STATUS_PCI_INT | 1616221167Sgnn VXGE_HAL_MRPCIM_GENERAL_INT_STATUS_RTDMA_INT | 1617221167Sgnn VXGE_HAL_MRPCIM_GENERAL_INT_STATUS_WRDMA_INT | 1618221167Sgnn VXGE_HAL_MRPCIM_GENERAL_INT_STATUS_G3CMCT_INT | 1619221167Sgnn VXGE_HAL_MRPCIM_GENERAL_INT_STATUS_GCMG1_INT | 1620221167Sgnn VXGE_HAL_MRPCIM_GENERAL_INT_STATUS_GCMG2_INT | 1621221167Sgnn VXGE_HAL_MRPCIM_GENERAL_INT_STATUS_G3CMIFL_INT | 1622221167Sgnn VXGE_HAL_MRPCIM_GENERAL_INT_STATUS_G3CMIFU_INT | 1623221167Sgnn VXGE_HAL_MRPCIM_GENERAL_INT_STATUS_PCMG1_INT | 1624221167Sgnn VXGE_HAL_MRPCIM_GENERAL_INT_STATUS_PCMG2_INT | 1625221167Sgnn VXGE_HAL_MRPCIM_GENERAL_INT_STATUS_PCMG3_INT | 1626221167Sgnn VXGE_HAL_MRPCIM_GENERAL_INT_STATUS_XMAC_INT | 1627221167Sgnn VXGE_HAL_MRPCIM_GENERAL_INT_STATUS_RXMAC_INT | 1628221167Sgnn VXGE_HAL_MRPCIM_GENERAL_INT_STATUS_TMAC_INT | 1629221167Sgnn VXGE_HAL_MRPCIM_GENERAL_INT_STATUS_G3FBIF_INT | 1630221167Sgnn VXGE_HAL_MRPCIM_GENERAL_INT_STATUS_FBMC_INT | 1631221167Sgnn VXGE_HAL_MRPCIM_GENERAL_INT_STATUS_G3FBCT_INT | 1632221167Sgnn VXGE_HAL_MRPCIM_GENERAL_INT_STATUS_TPA_INT | 1633221167Sgnn VXGE_HAL_MRPCIM_GENERAL_INT_STATUS_DRBELL_INT | 1634221167Sgnn VXGE_HAL_MRPCIM_GENERAL_INT_STATUS_MSG_INT; 1635221167Sgnn 1636221167Sgnn vxge_hal_pio_mem_write32_upper( 1637221167Sgnn hldev->header.pdev, 1638221167Sgnn hldev->header.regh0, 1639221167Sgnn (u32) bVAL32(~val64, 0), 1640221167Sgnn &mrpcim_reg->mrpcim_general_int_mask); 1641221167Sgnn 1642221167Sgnn vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = %d", 1643221167Sgnn __FILE__, __func__, __LINE__, status); 1644221167Sgnn 1645221167Sgnn return (status); 1646221167Sgnn} 1647221167Sgnn 1648221167Sgnn/* 1649221167Sgnn * vxge_hal_mrpcim_intr_disable - Disable the interrupts on mrpcim. 1650221167Sgnn * @devh: HAL device handle. 1651221167Sgnn * 1652221167Sgnn * Disable mrpcim interrupts 1653221167Sgnn * 1654221167Sgnn * See also: vxge_hal_mrpcim_intr_enable(). 1655221167Sgnn */ 1656221167Sgnnvxge_hal_status_e 1657221167Sgnnvxge_hal_mrpcim_intr_disable(vxge_hal_device_h devh) 1658221167Sgnn{ 1659221167Sgnn u32 i; 1660221167Sgnn vxge_hal_status_e status = VXGE_HAL_OK; 1661221167Sgnn vxge_hal_mrpcim_reg_t *mrpcim_reg; 1662221167Sgnn __hal_device_t *hldev = (__hal_device_t *) devh; 1663221167Sgnn 1664221167Sgnn vxge_assert(devh); 1665221167Sgnn 1666221167Sgnn vxge_hal_trace_log_mrpcim("==> %s:%s:%d", 1667221167Sgnn __FILE__, __func__, __LINE__); 1668221167Sgnn 1669221167Sgnn vxge_hal_trace_log_mrpcim("devh = 0x"VXGE_OS_STXFMT, 1670221167Sgnn (ptr_t) devh); 1671221167Sgnn 1672221167Sgnn if (!(hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM)) { 1673221167Sgnn vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = %d", 1674221167Sgnn __FILE__, __func__, __LINE__, 1675221167Sgnn VXGE_HAL_ERR_PRIVILAGED_OPEARATION); 1676221167Sgnn 1677221167Sgnn return (VXGE_HAL_ERR_PRIVILAGED_OPEARATION); 1678221167Sgnn 1679221167Sgnn } 1680221167Sgnn 1681221167Sgnn mrpcim_reg = hldev->mrpcim_reg; 1682221167Sgnn 1683221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->ini_errors_mask); 1684221167Sgnn 1685221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->dma_errors_mask); 1686221167Sgnn 1687221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->tgt_errors_mask); 1688221167Sgnn 1689221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->config_errors_mask); 1690221167Sgnn 1691221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->crdt_errors_mask); 1692221167Sgnn 1693221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->mrpcim_general_errors_mask); 1694221167Sgnn 1695221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->pll_errors_mask); 1696221167Sgnn 1697221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->mrpcim_ppif_int_mask); 1698221167Sgnn 1699221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->dbecc_err_mask); 1700221167Sgnn 1701221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->general_err_mask); 1702221167Sgnn 1703221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->pcipif_int_mask); 1704221167Sgnn 1705221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->pda_alarm_mask); 1706221167Sgnn 1707221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->pcc_error_mask); 1708221167Sgnn 1709221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->lso_error_mask); 1710221167Sgnn 1711221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->sm_error_mask); 1712221167Sgnn 1713221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->rtdma_int_mask); 1714221167Sgnn 1715221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->rc_alarm_mask); 1716221167Sgnn 1717221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->rxdrm_sm_err_mask); 1718221167Sgnn 1719221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->rxdcm_sm_err_mask); 1720221167Sgnn 1721221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->rxdwm_sm_err_mask); 1722221167Sgnn 1723221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->rda_err_mask); 1724221167Sgnn 1725221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->rda_ecc_db_mask); 1726221167Sgnn 1727221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->rqa_err_mask); 1728221167Sgnn 1729221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->frf_alarm_mask); 1730221167Sgnn 1731221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->rocrc_alarm_mask); 1732221167Sgnn 1733221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->wde0_alarm_mask); 1734221167Sgnn 1735221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->wde1_alarm_mask); 1736221167Sgnn 1737221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->wde2_alarm_mask); 1738221167Sgnn 1739221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->wde3_alarm_mask); 1740221167Sgnn 1741221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->wrdma_int_mask); 1742221167Sgnn 1743221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->g3cmct_err_mask); 1744221167Sgnn 1745221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->g3cmct_int_mask); 1746221167Sgnn 1747221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->gsscc_err_mask); 1748221167Sgnn 1749221167Sgnn for (i = 0; i < 3; i++) { 1750221167Sgnn 1751221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->gssc_err0_mask[i]); 1752221167Sgnn 1753221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->gssc_err1_mask[i]); 1754221167Sgnn 1755221167Sgnn } 1756221167Sgnn 1757221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->gcmg1_int_mask); 1758221167Sgnn 1759221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->gxtmc_err_mask); 1760221167Sgnn 1761221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->gcp_err_mask); 1762221167Sgnn 1763221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->cmc_err_mask); 1764221167Sgnn 1765221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->gcmg2_int_mask); 1766221167Sgnn 1767221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->g3ifcmd_cml_err_mask); 1768221167Sgnn 1769221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->g3ifcmd_cml_int_mask); 1770221167Sgnn 1771221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->g3ifcmd_cmu_err_mask); 1772221167Sgnn 1773221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->g3ifcmd_cmu_int_mask); 1774221167Sgnn 1775221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->psscc_err_mask); 1776221167Sgnn 1777221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->pcmg1_int_mask); 1778221167Sgnn 1779221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->pxtmc_err_mask); 1780221167Sgnn 1781221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->cp_exc_mask); 1782221167Sgnn 1783221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->cp_err_mask); 1784221167Sgnn 1785221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->pcmg2_int_mask); 1786221167Sgnn 1787221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->dam_err_mask); 1788221167Sgnn 1789221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->pcmg3_int_mask); 1790221167Sgnn 1791221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->xmac_gen_err_mask); 1792221167Sgnn 1793221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->xgxs_gen_err_mask); 1794221167Sgnn 1795221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->asic_ntwk_err_mask); 1796221167Sgnn 1797221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->xgmac_int_mask); 1798221167Sgnn 1799221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->rxmac_ecc_err_mask); 1800221167Sgnn 1801221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->rxmac_various_err_mask); 1802221167Sgnn 1803221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->rxmac_int_mask); 1804221167Sgnn 1805221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->txmac_gen_err_mask); 1806221167Sgnn 1807221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->txmac_ecc_err_mask); 1808221167Sgnn 1809221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->tmac_int_mask); 1810221167Sgnn 1811221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->g3ifcmd_fb_err_mask); 1812221167Sgnn 1813221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->g3ifcmd_fb_int_mask); 1814221167Sgnn 1815221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->mc_err_mask); 1816221167Sgnn 1817221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->grocrc_alarm_mask); 1818221167Sgnn 1819221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->fau_ecc_err_mask); 1820221167Sgnn 1821221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->mc_int_mask); 1822221167Sgnn 1823221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->g3fbct_err_mask); 1824221167Sgnn 1825221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->g3fbct_int_mask); 1826221167Sgnn 1827221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->orp_err_mask); 1828221167Sgnn 1829221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->ptm_alarm_mask); 1830221167Sgnn 1831221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->tpa_error_mask); 1832221167Sgnn 1833221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->tpa_int_mask); 1834221167Sgnn 1835221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->kdfc_err_mask); 1836221167Sgnn 1837221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->doorbell_int_mask); 1838221167Sgnn 1839221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->tim_err_mask); 1840221167Sgnn 1841221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->msg_exc_mask); 1842221167Sgnn 1843221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->msg_err_mask); 1844221167Sgnn 1845221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->msg_err2_mask); 1846221167Sgnn 1847221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->msg_err3_mask); 1848221167Sgnn 1849221167Sgnn VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->msg_int_mask); 1850221167Sgnn 1851221167Sgnn vxge_hal_pio_mem_write32_upper( 1852221167Sgnn hldev->header.pdev, 1853221167Sgnn hldev->header.regh0, 1854221167Sgnn (u32) VXGE_HAL_INTR_MASK_ALL, 1855221167Sgnn &mrpcim_reg->mrpcim_general_int_mask); 1856221167Sgnn 1857221167Sgnn vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = %d", 1858221167Sgnn __FILE__, __func__, __LINE__, status); 1859221167Sgnn 1860221167Sgnn return (status); 1861221167Sgnn} 1862221167Sgnn 1863221167Sgnn/* 1864221167Sgnn * vxge_hal_mrpcim_reset - Reset the entire device. 1865221167Sgnn * @devh: HAL device handle. 1866221167Sgnn * 1867221167Sgnn * Soft-reset the device, reset the device stats except reset_cnt. 1868221167Sgnn * 1869221167Sgnn * 1870221167Sgnn * Returns: VXGE_HAL_OK - success. 1871221167Sgnn * VXGE_HAL_ERR_DEVICE_NOT_INITIALIZED - Device is not initialized. 1872221167Sgnn * VXGE_HAL_ERR_RESET_FAILED - Reset failed. 1873221167Sgnn * 1874221167Sgnn * See also: vxge_hal_status_e {}. 1875221167Sgnn */ 1876221167Sgnnvxge_hal_status_e 1877221167Sgnnvxge_hal_mrpcim_reset(vxge_hal_device_h devh) 1878221167Sgnn{ 1879221167Sgnn u64 val64; 1880221167Sgnn __hal_device_t *hldev = (__hal_device_t *) devh; 1881221167Sgnn 1882221167Sgnn vxge_assert(devh); 1883221167Sgnn 1884221167Sgnn vxge_hal_trace_log_mrpcim("==> %s:%s:%d", 1885221167Sgnn __FILE__, __func__, __LINE__); 1886221167Sgnn 1887221167Sgnn vxge_hal_trace_log_mrpcim("devh = 0x"VXGE_OS_STXFMT, 1888221167Sgnn (ptr_t) devh); 1889221167Sgnn 1890221167Sgnn if (!(hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM)) { 1891221167Sgnn vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = %d", 1892221167Sgnn __FILE__, __func__, __LINE__, 1893221167Sgnn VXGE_HAL_ERR_PRIVILAGED_OPEARATION); 1894221167Sgnn 1895221167Sgnn return (VXGE_HAL_ERR_PRIVILAGED_OPEARATION); 1896221167Sgnn 1897221167Sgnn } 1898221167Sgnn 1899221167Sgnn if (!hldev->header.is_initialized) 1900221167Sgnn return (VXGE_HAL_ERR_DEVICE_NOT_INITIALIZED); 1901221167Sgnn 1902221167Sgnn if (hldev->device_resetting == 1) { 1903221167Sgnn vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = %d", 1904221167Sgnn __FILE__, __func__, __LINE__, 1905221167Sgnn VXGE_HAL_ERR_RESET_IN_PROGRESS); 1906221167Sgnn 1907221167Sgnn return (VXGE_HAL_ERR_RESET_IN_PROGRESS); 1908221167Sgnn } 1909221167Sgnn 1910221167Sgnn (void) __hal_ifmsg_wmsg_post(hldev, 1911221167Sgnn hldev->first_vp_id, 1912221167Sgnn VXGE_HAL_RTS_ACCESS_STEER_MSG_DEST_BROADCAST, 1913221167Sgnn VXGE_HAL_RTS_ACCESS_STEER_DATA0_MSG_TYPE_DEVICE_RESET_BEGIN, 1914221167Sgnn 0); 1915221167Sgnn 1916221167Sgnn vxge_os_mdelay(100); 1917221167Sgnn 1918221167Sgnn val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 1919221167Sgnn hldev->header.regh0, 1920221167Sgnn &hldev->mrpcim_reg->sw_reset_cfg1); 1921221167Sgnn 1922221167Sgnn val64 |= VXGE_HAL_SW_RESET_CFG1_TYPE; 1923221167Sgnn 1924221167Sgnn vxge_os_pio_mem_write64(hldev->header.pdev, 1925221167Sgnn hldev->header.regh0, 1926221167Sgnn val64, 1927221167Sgnn &hldev->mrpcim_reg->sw_reset_cfg1); 1928221167Sgnn 1929221167Sgnn vxge_os_pio_mem_write64(hldev->header.pdev, 1930221167Sgnn hldev->header.regh0, 1931221167Sgnn VXGE_HAL_PF_SW_RESET_PF_SW_RESET( 1932221167Sgnn VXGE_HAL_PF_SW_RESET_COMMAND), 1933221167Sgnn &hldev->mrpcim_reg->bf_sw_reset); 1934221167Sgnn 1935221167Sgnn hldev->stats.sw_dev_info_stats.soft_reset_cnt++; 1936221167Sgnn 1937221167Sgnn hldev->device_resetting = 1; 1938221167Sgnn 1939221167Sgnn vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = %d", 1940221167Sgnn __FILE__, __func__, __LINE__, VXGE_HAL_PENDING); 1941221167Sgnn 1942221167Sgnn return (VXGE_HAL_PENDING); 1943221167Sgnn} 1944221167Sgnn 1945221167Sgnn/* 1946221167Sgnn * vxge_hal_mrpcim_reset_poll - Poll the device for reset complete. 1947221167Sgnn * @devh: HAL device handle. 1948221167Sgnn * 1949221167Sgnn * Soft-reset the device, reset the device stats except reset_cnt. 1950221167Sgnn * 1951221167Sgnn * After reset is done, will try to re-initialize HW. 1952221167Sgnn * 1953221167Sgnn * Returns: VXGE_HAL_OK - success. 1954221167Sgnn * VXGE_HAL_ERR_DEVICE_NOT_INITIALIZED - Device is not initialized. 1955221167Sgnn * VXGE_HAL_ERR_RESET_FAILED - Reset failed. 1956221167Sgnn * 1957221167Sgnn * See also: vxge_hal_status_e {}. 1958221167Sgnn */ 1959221167Sgnnvxge_hal_status_e 1960221167Sgnnvxge_hal_mrpcim_reset_poll(vxge_hal_device_h devh) 1961221167Sgnn{ 1962221167Sgnn u64 val64; 1963221167Sgnn vxge_hal_status_e status = VXGE_HAL_OK; 1964221167Sgnn __hal_device_t *hldev = (__hal_device_t *) devh; 1965221167Sgnn 1966221167Sgnn vxge_assert(devh); 1967221167Sgnn 1968221167Sgnn vxge_hal_trace_log_mrpcim("==> %s:%s:%d", __FILE__, __func__, __LINE__); 1969221167Sgnn 1970221167Sgnn vxge_hal_trace_log_mrpcim("devh = 0x"VXGE_OS_STXFMT, 1971221167Sgnn (ptr_t) devh); 1972221167Sgnn 1973221167Sgnn if (!(hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM)) { 1974221167Sgnn vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = %d", 1975221167Sgnn __FILE__, __func__, __LINE__, 1976221167Sgnn VXGE_HAL_ERR_PRIVILAGED_OPEARATION); 1977221167Sgnn 1978221167Sgnn return (VXGE_HAL_ERR_PRIVILAGED_OPEARATION); 1979221167Sgnn 1980221167Sgnn } 1981221167Sgnn 1982221167Sgnn if (!hldev->header.is_initialized) { 1983221167Sgnn vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = %d", 1984221167Sgnn __FILE__, __func__, __LINE__, 1985221167Sgnn VXGE_HAL_ERR_DEVICE_NOT_INITIALIZED); 1986221167Sgnn return (VXGE_HAL_ERR_DEVICE_NOT_INITIALIZED); 1987221167Sgnn } 1988221167Sgnn 1989221167Sgnn if ((status = __hal_device_reg_addr_get(hldev)) != VXGE_HAL_OK) { 1990221167Sgnn vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = %d", 1991221167Sgnn __FILE__, __func__, __LINE__, status); 1992221167Sgnn hldev->device_resetting = 0; 1993221167Sgnn return (status); 1994221167Sgnn } 1995221167Sgnn 1996221167Sgnn __hal_device_id_get(hldev); 1997221167Sgnn 1998221167Sgnn __hal_device_host_info_get(hldev); 1999221167Sgnn 2000221167Sgnn hldev->hw_is_initialized = 0; 2001221167Sgnn 2002221167Sgnn hldev->device_resetting = 0; 2003221167Sgnn 2004221167Sgnn vxge_os_memzero(hldev->mrpcim->mrpcim_stats, 2005221167Sgnn sizeof(vxge_hal_mrpcim_stats_hw_info_t)); 2006221167Sgnn 2007221167Sgnn vxge_os_memzero(&hldev->mrpcim->mrpcim_stats_sav, 2008221167Sgnn sizeof(vxge_hal_mrpcim_stats_hw_info_t)); 2009221167Sgnn 2010221167Sgnn status = __hal_mrpcim_mac_configure(hldev); 2011221167Sgnn 2012221167Sgnn if (status != VXGE_HAL_OK) { 2013221167Sgnn vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = %d", 2014221167Sgnn __FILE__, __func__, __LINE__, status); 2015221167Sgnn return (status); 2016221167Sgnn } 2017221167Sgnn 2018221167Sgnn status = __hal_mrpcim_lag_configure(hldev); 2019221167Sgnn 2020221167Sgnn if (status != VXGE_HAL_OK) { 2021221167Sgnn vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = %d", 2022221167Sgnn __FILE__, __func__, __LINE__, status); 2023221167Sgnn return (status); 2024221167Sgnn } 2025221167Sgnn 2026221167Sgnn val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 2027221167Sgnn hldev->header.regh0, 2028221167Sgnn &hldev->mrpcim_reg->mdio_gen_cfg_port[0]); 2029221167Sgnn 2030221167Sgnn hldev->mrpcim->mdio_phy_prtad0 = 2031221167Sgnn (u32) VXGE_HAL_MDIO_GEN_CFG_PORT_GET_MDIO_PHY_PRTAD(val64); 2032221167Sgnn 2033221167Sgnn val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 2034221167Sgnn hldev->header.regh0, 2035221167Sgnn &hldev->mrpcim_reg->mdio_gen_cfg_port[1]); 2036221167Sgnn 2037221167Sgnn hldev->mrpcim->mdio_phy_prtad1 = 2038221167Sgnn (u32) VXGE_HAL_MDIO_GEN_CFG_PORT_GET_MDIO_PHY_PRTAD(val64); 2039221167Sgnn 2040221167Sgnn val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 2041221167Sgnn hldev->header.regh0, 2042221167Sgnn &hldev->mrpcim_reg->xgxs_static_cfg_port[0]); 2043221167Sgnn 2044221167Sgnn hldev->mrpcim->mdio_dte_prtad0 = 2045221167Sgnn (u32) VXGE_HAL_XGXS_STATIC_CFG_PORT_GET_MDIO_DTE_PRTAD(val64); 2046221167Sgnn 2047221167Sgnn val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 2048221167Sgnn hldev->header.regh0, 2049221167Sgnn &hldev->mrpcim_reg->xgxs_static_cfg_port[1]); 2050221167Sgnn 2051221167Sgnn hldev->mrpcim->mdio_dte_prtad1 = 2052221167Sgnn (u32) VXGE_HAL_XGXS_STATIC_CFG_PORT_GET_MDIO_DTE_PRTAD(val64); 2053221167Sgnn 2054221167Sgnn vxge_os_pio_mem_write64(hldev->header.pdev, 2055221167Sgnn hldev->header.regh0, 2056221167Sgnn hldev->mrpcim->mrpcim_stats_block->dma_addr, 2057221167Sgnn &hldev->mrpcim_reg->mrpcim_stats_start_host_addr); 2058221167Sgnn 2059221167Sgnn vxge_os_pio_mem_write64(hldev->header.pdev, 2060221167Sgnn hldev->header.regh0, 2061221167Sgnn hldev->vpath_assignments, 2062221167Sgnn &hldev->mrpcim_reg->rxmac_authorize_all_addr); 2063221167Sgnn 2064221167Sgnn vxge_os_pio_mem_write64(hldev->header.pdev, 2065221167Sgnn hldev->header.regh0, 2066221167Sgnn hldev->vpath_assignments, 2067221167Sgnn &hldev->mrpcim_reg->rxmac_authorize_all_vid); 2068221167Sgnn 2069221167Sgnn (void) __hal_ifmsg_wmsg_post(hldev, 2070221167Sgnn hldev->first_vp_id, 2071221167Sgnn VXGE_HAL_RTS_ACCESS_STEER_MSG_DEST_BROADCAST, 2072221167Sgnn VXGE_HAL_RTS_ACCESS_STEER_DATA0_MSG_TYPE_DEVICE_RESET_END, 2073221167Sgnn 0); 2074221167Sgnn 2075221167Sgnn (void) vxge_hal_device_reset_poll(devh); 2076221167Sgnn 2077221167Sgnn vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = %d", 2078221167Sgnn __FILE__, __func__, __LINE__, status); 2079221167Sgnn 2080221167Sgnn return (status); 2081221167Sgnn} 2082221167Sgnn 2083221167Sgnn/* 2084221167Sgnn * __hal_mrpcim_xpak_counter_check - check the Xpak error count and log the msg 2085221167Sgnn * @hldev: pointer to __hal_device_t structure 2086221167Sgnn * @port: Port number 2087221167Sgnn * @type: xpak stats error type 2088221167Sgnn * @value: xpak stats value 2089221167Sgnn * 2090221167Sgnn * It is used to log the error message based on the xpak stats value 2091221167Sgnn * Return value: 2092221167Sgnn * None 2093221167Sgnn */ 2094221167Sgnnvoid 2095221167Sgnn__hal_mrpcim_xpak_counter_check(__hal_device_t *hldev, 2096221167Sgnn u32 port, u32 type, u32 value) 2097221167Sgnn{ 2098221167Sgnn vxge_assert(hldev != NULL); 2099221167Sgnn 2100221167Sgnn vxge_hal_trace_log_stats("==> %s:%s:%d", 2101221167Sgnn __FILE__, __func__, __LINE__); 2102221167Sgnn 2103221167Sgnn vxge_hal_trace_log_stats( 2104221167Sgnn "hldev = 0x"VXGE_OS_STXFMT", port = %d, type = %d, value = %d", 2105221167Sgnn (ptr_t) hldev, port, type, value); 2106221167Sgnn 2107221167Sgnn if (!(hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM)) { 2108221167Sgnn 2109221167Sgnn vxge_hal_trace_log_stats("<== %s:%s:%d Result: %d", 2110221167Sgnn __FILE__, __func__, 2111221167Sgnn __LINE__, VXGE_HAL_ERR_PRIVILAGED_OPEARATION); 2112221167Sgnn return; 2113221167Sgnn 2114221167Sgnn } 2115221167Sgnn 2116221167Sgnn /* 2117221167Sgnn * If the value is high for three consecutive cylce, 2118221167Sgnn * log a error message 2119221167Sgnn */ 2120221167Sgnn if (value == 3) { 2121221167Sgnn switch (type) { 2122221167Sgnn case VXGE_HAL_XPAK_ALARM_EXCESS_TEMP: 2123221167Sgnn hldev->mrpcim->xpak_stats[port].excess_temp = 0; 2124221167Sgnn 2125221167Sgnn /* 2126221167Sgnn * Notify the ULD on Excess Xpak temperature alarm msg 2127221167Sgnn */ 2128221167Sgnn if (g_vxge_hal_driver->uld_callbacks.xpak_alarm_log) { 2129221167Sgnn g_vxge_hal_driver->uld_callbacks.xpak_alarm_log( 2130221167Sgnn hldev->header.upper_layer_data, 2131221167Sgnn port, 2132221167Sgnn VXGE_HAL_XPAK_ALARM_EXCESS_TEMP); 2133221167Sgnn } 2134221167Sgnn break; 2135221167Sgnn case VXGE_HAL_XPAK_ALARM_EXCESS_BIAS_CURRENT: 2136221167Sgnn hldev->mrpcim->xpak_stats[port].excess_bias_current = 0; 2137221167Sgnn 2138221167Sgnn /* 2139221167Sgnn * Notify the ULD on Excess xpak bias current alarm msg 2140221167Sgnn */ 2141221167Sgnn if (g_vxge_hal_driver->uld_callbacks.xpak_alarm_log) { 2142221167Sgnn g_vxge_hal_driver->uld_callbacks.xpak_alarm_log( 2143221167Sgnn hldev->header.upper_layer_data, 2144221167Sgnn port, 2145221167Sgnn VXGE_HAL_XPAK_ALARM_EXCESS_BIAS_CURRENT); 2146221167Sgnn } 2147221167Sgnn break; 2148221167Sgnn case VXGE_HAL_XPAK_ALARM_EXCESS_LASER_OUTPUT: 2149221167Sgnn hldev->mrpcim->xpak_stats[port].excess_laser_output = 0; 2150221167Sgnn 2151221167Sgnn /* 2152221167Sgnn * Notify the ULD on Excess Xpak Laser o/p power 2153221167Sgnn * alarm msg 2154221167Sgnn */ 2155221167Sgnn if (g_vxge_hal_driver->uld_callbacks.xpak_alarm_log) { 2156221167Sgnn g_vxge_hal_driver->uld_callbacks.xpak_alarm_log( 2157221167Sgnn hldev->header.upper_layer_data, 2158221167Sgnn port, 2159221167Sgnn VXGE_HAL_XPAK_ALARM_EXCESS_LASER_OUTPUT); 2160221167Sgnn } 2161221167Sgnn break; 2162221167Sgnn default: 2163221167Sgnn vxge_hal_info_log_stats("%s", 2164221167Sgnn "Incorrect XPAK Alarm type"); 2165221167Sgnn } 2166221167Sgnn } 2167221167Sgnn 2168221167Sgnn vxge_hal_trace_log_stats("<== %s:%s:%d Result = 0", 2169221167Sgnn __FILE__, __func__, __LINE__); 2170221167Sgnn} 2171221167Sgnn 2172221167Sgnn/* 2173221167Sgnn * vxge_hal_mrpcim_xpak_stats_poll - Poll and update the Xpak error count. 2174221167Sgnn * @devh: HAL device handle 2175221167Sgnn * @port: Port number 2176221167Sgnn * 2177221167Sgnn * It is used to update the xpak stats value 2178221167Sgnn */ 2179221167Sgnnvxge_hal_status_e 2180221167Sgnnvxge_hal_mrpcim_xpak_stats_poll( 2181221167Sgnn vxge_hal_device_h devh, u32 port) 2182221167Sgnn{ 2183221167Sgnn u16 val; 2184221167Sgnn vxge_hal_status_e status = VXGE_HAL_OK; 2185221167Sgnn __hal_device_t *hldev = (__hal_device_t *) devh; 2186221167Sgnn 2187221167Sgnn vxge_assert(hldev != NULL); 2188221167Sgnn 2189221167Sgnn vxge_hal_trace_log_stats("==> %s:%s:%d", 2190221167Sgnn __FILE__, __func__, __LINE__); 2191221167Sgnn 2192221167Sgnn vxge_hal_trace_log_stats("hldev = 0x"VXGE_OS_STXFMT", port = %d", 2193221167Sgnn (ptr_t) hldev, port); 2194221167Sgnn 2195221167Sgnn if (!(hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM)) { 2196221167Sgnn 2197221167Sgnn vxge_hal_trace_log_stats("<== %s:%s:%d Result: %d", 2198221167Sgnn __FILE__, __func__, __LINE__, 2199221167Sgnn VXGE_HAL_ERR_PRIVILAGED_OPEARATION); 2200221167Sgnn return (VXGE_HAL_ERR_PRIVILAGED_OPEARATION); 2201221167Sgnn 2202221167Sgnn } 2203221167Sgnn 2204221167Sgnn /* Loading the DOM register to MDIO register */ 2205221167Sgnn 2206221167Sgnn val = 0; 2207221167Sgnn 2208221167Sgnn status = __hal_mrpcim_mdio_access(devh, port, 2209221167Sgnn VXGE_HAL_MDIO_MGR_ACCESS_PORT_OP_TYPE_ADDR_WRITE, 2210221167Sgnn VXGE_HAL_MDIO_MGR_ACCESS_PORT_DEVAD_PMA_PMD, 2211221167Sgnn VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_CMD_STAT, 2212221167Sgnn &val); 2213221167Sgnn 2214221167Sgnn if (status != VXGE_HAL_OK) { 2215221167Sgnn vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result: %d", 2216221167Sgnn __FILE__, __func__, __LINE__, status); 2217221167Sgnn return (status); 2218221167Sgnn } 2219221167Sgnn 2220221167Sgnn status = __hal_mrpcim_mdio_access(devh, port, 2221221167Sgnn VXGE_HAL_MDIO_MGR_ACCESS_PORT_OP_TYPE_ADDR_READ, 2222221167Sgnn VXGE_HAL_MDIO_MGR_ACCESS_PORT_DEVAD_PMA_PMD, 2223221167Sgnn VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_CMD_STAT, 2224221167Sgnn &val); 2225221167Sgnn 2226221167Sgnn if (status != VXGE_HAL_OK) { 2227221167Sgnn vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result: %d", 2228221167Sgnn __FILE__, __func__, __LINE__, status); 2229221167Sgnn return (status); 2230221167Sgnn } 2231221167Sgnn 2232221167Sgnn /* 2233221167Sgnn * Reading the Alarm flags 2234221167Sgnn */ 2235221167Sgnn status = __hal_mrpcim_mdio_access(devh, port, 2236221167Sgnn VXGE_HAL_MDIO_MGR_ACCESS_PORT_OP_TYPE_ADDR_READ, 2237221167Sgnn VXGE_HAL_MDIO_MGR_ACCESS_PORT_DEVAD_PMA_PMD, 2238221167Sgnn VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_TX_ALARM_FLAG, 2239221167Sgnn &val); 2240221167Sgnn 2241221167Sgnn if (status != VXGE_HAL_OK) { 2242221167Sgnn vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result: %d", 2243221167Sgnn __FILE__, __func__, __LINE__, status); 2244221167Sgnn return (status); 2245221167Sgnn } 2246221167Sgnn 2247221167Sgnn if (val & 2248221167Sgnn VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_TX_ALARM_FLAG_TEMP_HIGH) { 2249221167Sgnn hldev->mrpcim->xpak_stats[port].alarm_transceiver_temp_high++; 2250221167Sgnn hldev->mrpcim->xpak_stats[port].excess_temp++; 2251221167Sgnn __hal_mrpcim_xpak_counter_check(hldev, port, 2252221167Sgnn VXGE_HAL_XPAK_ALARM_EXCESS_TEMP, 2253221167Sgnn hldev->mrpcim->xpak_stats[port].excess_temp); 2254221167Sgnn } else { 2255221167Sgnn hldev->mrpcim->xpak_stats[port].excess_temp = 0; 2256221167Sgnn } 2257221167Sgnn 2258221167Sgnn if (val & 2259221167Sgnn VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_TX_ALARM_FLAG_TEMP_LOW) { 2260221167Sgnn hldev->mrpcim->xpak_stats[port].alarm_transceiver_temp_low++; 2261221167Sgnn } 2262221167Sgnn 2263221167Sgnn if (val & 2264221167Sgnn VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_TX_ALARM_FLAG_CUR_HIGH) { 2265221167Sgnn hldev->mrpcim->xpak_stats[port].alarm_laser_bias_current_high++; 2266221167Sgnn hldev->mrpcim->xpak_stats[port].excess_bias_current++; 2267221167Sgnn __hal_mrpcim_xpak_counter_check(hldev, port, 2268221167Sgnn VXGE_HAL_XPAK_ALARM_EXCESS_BIAS_CURRENT, 2269221167Sgnn hldev->mrpcim->xpak_stats[port].excess_bias_current); 2270221167Sgnn } else { 2271221167Sgnn hldev->mrpcim->xpak_stats[port].excess_bias_current = 0; 2272221167Sgnn } 2273221167Sgnn 2274221167Sgnn if (val & 2275221167Sgnn VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_TX_ALARM_FLAG_CUR_LOW) { 2276221167Sgnn hldev->mrpcim->xpak_stats[port].alarm_laser_bias_current_low++; 2277221167Sgnn } 2278221167Sgnn 2279221167Sgnn if (val & 2280221167Sgnn VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_TX_ALARM_FLAG_PWR_HIGH) { 2281221167Sgnn hldev->mrpcim->xpak_stats[port].alarm_laser_output_power_high++; 2282221167Sgnn hldev->mrpcim->xpak_stats[port].excess_laser_output++; 2283221167Sgnn __hal_mrpcim_xpak_counter_check(hldev, port, 2284221167Sgnn VXGE_HAL_XPAK_ALARM_EXCESS_LASER_OUTPUT, 2285221167Sgnn hldev->mrpcim->xpak_stats[port].excess_laser_output); 2286221167Sgnn } else { 2287221167Sgnn hldev->mrpcim->xpak_stats[port].excess_laser_output = 0; 2288221167Sgnn } 2289221167Sgnn 2290221167Sgnn if (val & 2291221167Sgnn VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_TX_ALARM_FLAG_PWR_LOW) { 2292221167Sgnn hldev->mrpcim->xpak_stats[port].alarm_laser_output_power_low++; 2293221167Sgnn } 2294221167Sgnn 2295221167Sgnn /* 2296221167Sgnn * Reading the warning flags 2297221167Sgnn */ 2298221167Sgnn status = __hal_mrpcim_mdio_access(devh, port, 2299221167Sgnn VXGE_HAL_MDIO_MGR_ACCESS_PORT_OP_TYPE_ADDR_READ, 2300221167Sgnn VXGE_HAL_MDIO_MGR_ACCESS_PORT_DEVAD_PMA_PMD, 2301221167Sgnn VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_TX_WARN_FLAG, 2302221167Sgnn &val); 2303221167Sgnn 2304221167Sgnn if (status != VXGE_HAL_OK) { 2305221167Sgnn vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result: %d", 2306221167Sgnn __FILE__, __func__, __LINE__, status); 2307221167Sgnn return (status); 2308221167Sgnn } 2309221167Sgnn 2310221167Sgnn if (val & VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_TX_WARN_FLAG_TEMP_HIGH) 2311221167Sgnn hldev->mrpcim->xpak_stats[port].warn_transceiver_temp_high++; 2312221167Sgnn if (val & VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_TX_WARN_FLAG_TEMP_LOW) 2313221167Sgnn hldev->mrpcim->xpak_stats[port].warn_transceiver_temp_low++; 2314221167Sgnn if (val & VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_TX_WARN_FLAG_CUR_HIGH) 2315221167Sgnn hldev->mrpcim->xpak_stats[port].warn_laser_bias_current_high++; 2316221167Sgnn if (val & VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_TX_WARN_FLAG_CUR_LOW) 2317221167Sgnn hldev->mrpcim->xpak_stats[port].warn_laser_bias_current_low++; 2318221167Sgnn if (val & VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_TX_WARN_FLAG_PWR_HIGH) 2319221167Sgnn hldev->mrpcim->xpak_stats[port].warn_laser_output_power_high++; 2320221167Sgnn if (val & VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_TX_WARN_FLAG_PWR_LOW) 2321221167Sgnn hldev->mrpcim->xpak_stats[port].warn_laser_output_power_low++; 2322221167Sgnn 2323221167Sgnn vxge_hal_trace_log_stats("<== %s:%s:%d Result = %d", 2324221167Sgnn __FILE__, __func__, __LINE__, status); 2325221167Sgnn return (status); 2326221167Sgnn} 2327221167Sgnn 2328221167Sgnn/* 2329221167Sgnn * vxge_hal_mrpcim_stats_enable - Enable mrpcim statistics. 2330221167Sgnn * @devh: HAL Device. 2331221167Sgnn * 2332221167Sgnn * Enable the DMA mrpcim statistics for the device. The function is to be called 2333221167Sgnn * to re-enable the adapter to update stats into the host memory 2334221167Sgnn * 2335221167Sgnn * See also: vxge_hal_mrpcim_stats_disable() 2336221167Sgnn */ 2337221167Sgnnvxge_hal_status_e 2338221167Sgnnvxge_hal_mrpcim_stats_enable(vxge_hal_device_h devh) 2339221167Sgnn{ 2340221167Sgnn u64 val64; 2341221167Sgnn vxge_hal_status_e status = VXGE_HAL_OK; 2342221167Sgnn __hal_device_t *hldev = (__hal_device_t *) devh; 2343221167Sgnn 2344221167Sgnn vxge_assert(devh != NULL); 2345221167Sgnn 2346221167Sgnn vxge_hal_trace_log_stats("==> %s:%s:%d", 2347221167Sgnn __FILE__, __func__, __LINE__); 2348221167Sgnn 2349221167Sgnn vxge_hal_trace_log_stats("devh = 0x"VXGE_OS_STXFMT, 2350221167Sgnn (ptr_t) devh); 2351221167Sgnn 2352221167Sgnn if (!(hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM)) { 2353221167Sgnn 2354221167Sgnn vxge_hal_trace_log_stats("<== %s:%s:%d Result: %d", 2355221167Sgnn __FILE__, __func__, __LINE__, 2356221167Sgnn VXGE_HAL_ERR_PRIVILAGED_OPEARATION); 2357221167Sgnn return (VXGE_HAL_ERR_PRIVILAGED_OPEARATION); 2358221167Sgnn 2359221167Sgnn } 2360221167Sgnn 2361221167Sgnn vxge_os_memcpy(&hldev->mrpcim->mrpcim_stats_sav, 2362221167Sgnn hldev->mrpcim->mrpcim_stats, 2363221167Sgnn sizeof(vxge_hal_mrpcim_stats_hw_info_t)); 2364221167Sgnn 2365221167Sgnn if (hldev->header.config.stats_read_method == 2366221167Sgnn VXGE_HAL_STATS_READ_METHOD_DMA) { 2367221167Sgnn 2368221167Sgnn val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 2369221167Sgnn hldev->header.regh0, 2370221167Sgnn &hldev->mrpcim_reg->mrpcim_general_cfg2); 2371221167Sgnn 2372221167Sgnn val64 |= VXGE_HAL_MRPCIM_GENERAL_CFG2_MRPCIM_STATS_ENABLE; 2373221167Sgnn 2374221167Sgnn vxge_os_pio_mem_write64(hldev->header.pdev, 2375221167Sgnn hldev->header.regh0, 2376221167Sgnn val64, 2377221167Sgnn &hldev->mrpcim_reg->mrpcim_general_cfg2); 2378221167Sgnn 2379221167Sgnn val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 2380221167Sgnn hldev->header.regh0, 2381221167Sgnn &hldev->common_reg->stats_cfg0); 2382221167Sgnn 2383221167Sgnn val64 |= VXGE_HAL_STATS_CFG0_STATS_ENABLE( 2384221167Sgnn (1 << (16 - hldev->first_vp_id))); 2385221167Sgnn 2386221167Sgnn vxge_hal_pio_mem_write32_upper(hldev->header.pdev, 2387221167Sgnn hldev->header.regh0, 2388221167Sgnn (u32) bVAL32(val64, 0), 2389221167Sgnn &hldev->common_reg->stats_cfg0); 2390221167Sgnn } else { 2391221167Sgnn status = __hal_mrpcim_stats_get( 2392221167Sgnn hldev, 2393221167Sgnn hldev->mrpcim->mrpcim_stats); 2394221167Sgnn } 2395221167Sgnn 2396221167Sgnn vxge_hal_trace_log_stats("<== %s:%s:%d Result = %d", 2397221167Sgnn __FILE__, __func__, __LINE__, status); 2398221167Sgnn return (status); 2399221167Sgnn} 2400221167Sgnn 2401221167Sgnn/* 2402221167Sgnn * vxge_hal_mrpcim_stats_disable - Disable mrpcim statistics. 2403221167Sgnn * @devh: HAL Device. 2404221167Sgnn * 2405221167Sgnn * Enable the DMA mrpcim statistics for the device. The function is to be called 2406221167Sgnn * to disable the adapter to update stats into the host memory. This function 2407221167Sgnn * is not needed to be called, normally. 2408221167Sgnn * 2409221167Sgnn * See also: vxge_hal_mrpcim_stats_enable() 2410221167Sgnn */ 2411221167Sgnnvxge_hal_status_e 2412221167Sgnnvxge_hal_mrpcim_stats_disable(vxge_hal_device_h devh) 2413221167Sgnn{ 2414221167Sgnn u64 val64; 2415221167Sgnn vxge_hal_status_e status = VXGE_HAL_OK; 2416221167Sgnn __hal_device_t *hldev = (__hal_device_t *) devh; 2417221167Sgnn 2418221167Sgnn vxge_assert(devh != NULL); 2419221167Sgnn 2420221167Sgnn vxge_hal_trace_log_stats("==> %s:%s:%d", 2421221167Sgnn __FILE__, __func__, __LINE__); 2422221167Sgnn 2423221167Sgnn vxge_hal_trace_log_stats("devh = 0x"VXGE_OS_STXFMT, 2424221167Sgnn (ptr_t) devh); 2425221167Sgnn 2426221167Sgnn if (!(hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM)) { 2427221167Sgnn 2428221167Sgnn vxge_hal_trace_log_stats("<== %s:%s:%d Result: %d", 2429221167Sgnn __FILE__, __func__, __LINE__, 2430221167Sgnn VXGE_HAL_ERR_PRIVILAGED_OPEARATION); 2431221167Sgnn return (VXGE_HAL_ERR_PRIVILAGED_OPEARATION); 2432221167Sgnn 2433221167Sgnn } 2434221167Sgnn 2435221167Sgnn val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 2436221167Sgnn hldev->header.regh0, 2437221167Sgnn &hldev->mrpcim_reg->mrpcim_general_cfg2); 2438221167Sgnn 2439221167Sgnn val64 &= ~VXGE_HAL_MRPCIM_GENERAL_CFG2_MRPCIM_STATS_ENABLE; 2440221167Sgnn 2441221167Sgnn vxge_os_pio_mem_write64(hldev->header.pdev, 2442221167Sgnn hldev->header.regh0, 2443221167Sgnn val64, 2444221167Sgnn &hldev->mrpcim_reg->mrpcim_general_cfg2); 2445221167Sgnn 2446221167Sgnn vxge_hal_trace_log_stats("<== %s:%s:%d Result = %d", 2447221167Sgnn __FILE__, __func__, __LINE__, status); 2448221167Sgnn return (status); 2449221167Sgnn} 2450221167Sgnn 2451221167Sgnn/* 2452221167Sgnn * vxge_hal_mrpcim_stats_get - Get the device mrpcim statistics. 2453221167Sgnn * @devh: HAL Device. 2454221167Sgnn * @stats: mrpcim stats 2455221167Sgnn * 2456221167Sgnn * Returns the device mrpcim stats for the device. 2457221167Sgnn * 2458221167Sgnn * See also: vxge_hal_device_stats_get() 2459221167Sgnn */ 2460221167Sgnnvxge_hal_status_e 2461221167Sgnnvxge_hal_mrpcim_stats_get( 2462221167Sgnn vxge_hal_device_h devh, 2463221167Sgnn vxge_hal_mrpcim_stats_hw_info_t *stats) 2464221167Sgnn{ 2465221167Sgnn u64 val64; 2466221167Sgnn vxge_hal_status_e status = VXGE_HAL_OK; 2467221167Sgnn __hal_device_t *hldev = (__hal_device_t *) devh; 2468221167Sgnn 2469221167Sgnn vxge_assert((hldev != NULL) && (stats != NULL)); 2470221167Sgnn 2471221167Sgnn vxge_hal_trace_log_stats("==> %s:%s:%d", 2472221167Sgnn __FILE__, __func__, __LINE__); 2473221167Sgnn 2474221167Sgnn vxge_hal_trace_log_stats( 2475221167Sgnn "devh = 0x"VXGE_OS_STXFMT", stats = 0x"VXGE_OS_STXFMT, 2476221167Sgnn (ptr_t) devh, (ptr_t) stats); 2477221167Sgnn 2478221167Sgnn if (!(hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM)) { 2479221167Sgnn 2480221167Sgnn vxge_hal_trace_log_stats("<== %s:%s:%d Result: %d", 2481221167Sgnn __FILE__, __func__, __LINE__, 2482221167Sgnn VXGE_HAL_ERR_PRIVILAGED_OPEARATION); 2483221167Sgnn return (VXGE_HAL_ERR_PRIVILAGED_OPEARATION); 2484221167Sgnn 2485221167Sgnn } 2486221167Sgnn 2487221167Sgnn if (hldev->header.config.stats_read_method == 2488221167Sgnn VXGE_HAL_STATS_READ_METHOD_DMA) { 2489221167Sgnn 2490221167Sgnn status = vxge_hal_device_register_poll(hldev->header.pdev, 2491221167Sgnn hldev->header.regh0, 2492221167Sgnn &hldev->common_reg->stats_cfg0, 2493221167Sgnn 0, 2494221167Sgnn VXGE_HAL_STATS_CFG0_STATS_ENABLE( 2495221167Sgnn (1 << (16 - hldev->first_vp_id))), 2496221167Sgnn hldev->header.config.device_poll_millis); 2497221167Sgnn 2498221167Sgnn val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 2499221167Sgnn hldev->header.regh0, 2500221167Sgnn &hldev->mrpcim_reg->mrpcim_general_cfg2); 2501221167Sgnn 2502221167Sgnn val64 &= ~VXGE_HAL_MRPCIM_GENERAL_CFG2_MRPCIM_STATS_ENABLE; 2503221167Sgnn 2504221167Sgnn vxge_os_pio_mem_write64(hldev->header.pdev, 2505221167Sgnn hldev->header.regh0, 2506221167Sgnn val64, 2507221167Sgnn &hldev->mrpcim_reg->mrpcim_general_cfg2); 2508221167Sgnn } 2509221167Sgnn 2510221167Sgnn if (status == VXGE_HAL_OK) { 2511221167Sgnn vxge_os_memcpy(stats, 2512221167Sgnn hldev->mrpcim->mrpcim_stats, 2513221167Sgnn sizeof(vxge_hal_mrpcim_stats_hw_info_t)); 2514221167Sgnn } 2515221167Sgnn 2516221167Sgnn vxge_hal_trace_log_stats("<== %s:%s:%d Result = %d", 2517221167Sgnn __FILE__, __func__, __LINE__, status); 2518221167Sgnn return (status); 2519221167Sgnn} 2520221167Sgnn 2521221167Sgnn/* 2522221167Sgnn * vxge_hal_mrpcim_stats_access - Access the statistics from the given location 2523221167Sgnn * and offset and perform an operation 2524221167Sgnn * @devh: HAL Device handle. 2525221167Sgnn * @operation: Operation to be performed 2526221167Sgnn * @location: Location (one of vpath id, aggregate or port) 2527221167Sgnn * @offset: Offset with in the location 2528221167Sgnn * @stat: Pointer to a buffer to return the value 2529221167Sgnn * 2530221167Sgnn * Get the statistics from the given location and offset. 2531221167Sgnn * 2532221167Sgnn */ 2533221167Sgnnvxge_hal_status_e 2534221167Sgnnvxge_hal_mrpcim_stats_access( 2535221167Sgnn vxge_hal_device_h devh, 2536221167Sgnn u32 operation, 2537221167Sgnn u32 location, 2538221167Sgnn u32 offset, 2539221167Sgnn u64 *stat) 2540221167Sgnn{ 2541221167Sgnn u64 val64; 2542221167Sgnn vxge_hal_status_e status = VXGE_HAL_OK; 2543221167Sgnn __hal_device_t *hldev = (__hal_device_t *) devh; 2544221167Sgnn 2545221167Sgnn vxge_assert((devh != NULL) && (stat != NULL)); 2546221167Sgnn 2547221167Sgnn vxge_hal_trace_log_stats("==> %s:%s:%d", 2548221167Sgnn __FILE__, __func__, __LINE__); 2549221167Sgnn 2550221167Sgnn vxge_hal_trace_log_stats("devh = 0x"VXGE_OS_STXFMT", operation = %d, " 2551221167Sgnn "location = %d, offset = %d, stat = 0x"VXGE_OS_STXFMT, 2552221167Sgnn (ptr_t) devh, operation, location, offset, (ptr_t) stat); 2553221167Sgnn 2554221167Sgnn if (!(hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM)) { 2555221167Sgnn vxge_hal_trace_log_stats("<== %s:%s:%d Result = %d", 2556221167Sgnn __FILE__, __func__, __LINE__, 2557221167Sgnn VXGE_HAL_ERR_PRIVILAGED_OPEARATION); 2558221167Sgnn 2559221167Sgnn return (VXGE_HAL_ERR_PRIVILAGED_OPEARATION); 2560221167Sgnn } 2561221167Sgnn 2562221167Sgnn val64 = VXGE_HAL_XMAC_STATS_SYS_CMD_OP(operation) | 2563221167Sgnn VXGE_HAL_XMAC_STATS_SYS_CMD_STROBE | 2564221167Sgnn VXGE_HAL_XMAC_STATS_SYS_CMD_LOC_SEL(location) | 2565221167Sgnn VXGE_HAL_XMAC_STATS_SYS_CMD_OFFSET_SEL(offset); 2566221167Sgnn 2567221167Sgnn 2568221167Sgnn vxge_hal_pio_mem_write32_lower(hldev->header.pdev, 2569221167Sgnn hldev->header.regh0, 2570221167Sgnn (u32) bVAL32(val64, 32), 2571221167Sgnn &hldev->mrpcim_reg->xmac_stats_sys_cmd); 2572221167Sgnn 2573221167Sgnn vxge_os_wmb(); 2574221167Sgnn 2575221167Sgnn vxge_hal_pio_mem_write32_upper(hldev->header.pdev, 2576221167Sgnn hldev->header.regh0, 2577221167Sgnn (u32) bVAL32(val64, 0), 2578221167Sgnn &hldev->mrpcim_reg->xmac_stats_sys_cmd); 2579221167Sgnn 2580221167Sgnn vxge_os_wmb(); 2581221167Sgnn 2582221167Sgnn status = vxge_hal_device_register_poll(hldev->header.pdev, 2583221167Sgnn hldev->header.regh0, 2584221167Sgnn &hldev->mrpcim_reg->xmac_stats_sys_cmd, 2585221167Sgnn 0, 2586221167Sgnn VXGE_HAL_XMAC_STATS_SYS_CMD_STROBE, 2587221167Sgnn hldev->header.config.device_poll_millis); 2588221167Sgnn 2589221167Sgnn if ((status == VXGE_HAL_OK) && (operation == VXGE_HAL_STATS_OP_READ)) { 2590221167Sgnn 2591221167Sgnn *stat = vxge_os_pio_mem_read64(hldev->header.pdev, 2592221167Sgnn hldev->header.regh0, 2593221167Sgnn &hldev->mrpcim_reg->xmac_stats_sys_data); 2594221167Sgnn 2595221167Sgnn } else { 2596221167Sgnn *stat = 0; 2597221167Sgnn } 2598221167Sgnn 2599221167Sgnn vxge_hal_trace_log_stats("<== %s:%s:%d Result = %d", 2600221167Sgnn __FILE__, __func__, __LINE__, status); 2601221167Sgnn return (VXGE_HAL_OK); 2602221167Sgnn} 2603221167Sgnn 2604221167Sgnn/* 2605221167Sgnn * vxge_hal_mrpcim_xmac_aggr_stats_get - Get the Statistics on aggregate port 2606221167Sgnn * @devh: HAL device handle. 2607221167Sgnn * @port: Number of the port (0 or 1) 2608221167Sgnn * @aggr_stats: Buffer to return Statistics on aggregate port. 2609221167Sgnn * 2610221167Sgnn * Get the Statistics on aggregate port 2611221167Sgnn * 2612221167Sgnn */ 2613221167Sgnnvxge_hal_status_e 2614221167Sgnnvxge_hal_mrpcim_xmac_aggr_stats_get(vxge_hal_device_h devh, 2615221167Sgnn u32 port, 2616221167Sgnn vxge_hal_xmac_aggr_stats_t *aggr_stats) 2617221167Sgnn{ 2618221167Sgnn u64 val64; 2619221167Sgnn vxge_hal_status_e status = VXGE_HAL_OK; 2620221167Sgnn __hal_device_t *hldev = (__hal_device_t *) devh; 2621221167Sgnn 2622221167Sgnn vxge_assert((devh != NULL) && (aggr_stats != NULL)); 2623221167Sgnn 2624221167Sgnn vxge_hal_trace_log_stats("==> %s:%s:%d", 2625221167Sgnn __FILE__, __func__, __LINE__); 2626221167Sgnn 2627221167Sgnn vxge_hal_trace_log_stats("devh = 0x"VXGE_OS_STXFMT", port = %d, " 2628221167Sgnn "aggr_stats = 0x"VXGE_OS_STXFMT, 2629221167Sgnn (ptr_t) devh, port, (ptr_t) aggr_stats); 2630221167Sgnn 2631221167Sgnn if (!(hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM)) { 2632221167Sgnn vxge_hal_trace_log_stats("<== %s:%s:%d Result = %d", 2633221167Sgnn __FILE__, __func__, __LINE__, 2634221167Sgnn VXGE_HAL_ERR_PRIVILAGED_OPEARATION); 2635221167Sgnn 2636221167Sgnn return (VXGE_HAL_ERR_PRIVILAGED_OPEARATION); 2637221167Sgnn } 2638221167Sgnn 2639221167Sgnn VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_AGGR, 2640221167Sgnn VXGE_HAL_STATS_AGGRn_TX_FRMS_OFFSET(port)); 2641221167Sgnn 2642221167Sgnn aggr_stats->tx_frms = 2643221167Sgnn VXGE_HAL_STATS_GET_AGGRn_TX_FRMS(val64); 2644221167Sgnn 2645221167Sgnn VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_AGGR, 2646221167Sgnn VXGE_HAL_STATS_AGGRn_TX_DATA_OCTETS_OFFSET(port)); 2647221167Sgnn 2648221167Sgnn aggr_stats->tx_data_octets = 2649221167Sgnn VXGE_HAL_STATS_GET_AGGRn_TX_DATA_OCTETS(val64); 2650221167Sgnn 2651221167Sgnn VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_AGGR, 2652221167Sgnn VXGE_HAL_STATS_AGGRn_TX_MCAST_FRMS_OFFSET(port)); 2653221167Sgnn 2654221167Sgnn aggr_stats->tx_mcast_frms = 2655221167Sgnn VXGE_HAL_STATS_GET_AGGRn_TX_MCAST_FRMS(val64); 2656221167Sgnn 2657221167Sgnn VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_AGGR, 2658221167Sgnn VXGE_HAL_STATS_AGGRn_TX_BCAST_FRMS_OFFSET(port)); 2659221167Sgnn 2660221167Sgnn aggr_stats->tx_bcast_frms = 2661221167Sgnn VXGE_HAL_STATS_GET_AGGRn_TX_BCAST_FRMS(val64); 2662221167Sgnn 2663221167Sgnn VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_AGGR, 2664221167Sgnn VXGE_HAL_STATS_AGGRn_TX_DISCARDED_FRMS_OFFSET(port)); 2665221167Sgnn 2666221167Sgnn aggr_stats->tx_discarded_frms = 2667221167Sgnn VXGE_HAL_STATS_GET_AGGRn_TX_DISCARDED_FRMS(val64); 2668221167Sgnn 2669221167Sgnn VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_AGGR, 2670221167Sgnn VXGE_HAL_STATS_AGGRn_TX_ERRORED_FRMS_OFFSET(port)); 2671221167Sgnn 2672221167Sgnn aggr_stats->tx_errored_frms = 2673221167Sgnn VXGE_HAL_STATS_GET_AGGRn_TX_ERRORED_FRMS(val64); 2674221167Sgnn 2675221167Sgnn VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_AGGR, 2676221167Sgnn VXGE_HAL_STATS_AGGRn_RX_FRMS_OFFSET(port)); 2677221167Sgnn 2678221167Sgnn aggr_stats->rx_frms = 2679221167Sgnn VXGE_HAL_STATS_GET_AGGRn_RX_FRMS(val64); 2680221167Sgnn 2681221167Sgnn VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_AGGR, 2682221167Sgnn VXGE_HAL_STATS_AGGRn_RX_DATA_OCTETS_OFFSET(port)); 2683221167Sgnn 2684221167Sgnn aggr_stats->rx_data_octets = 2685221167Sgnn VXGE_HAL_STATS_GET_AGGRn_RX_DATA_OCTETS(val64); 2686221167Sgnn 2687221167Sgnn VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_AGGR, 2688221167Sgnn VXGE_HAL_STATS_AGGRn_RX_MCAST_FRMS_OFFSET(port)); 2689221167Sgnn 2690221167Sgnn aggr_stats->rx_mcast_frms = 2691221167Sgnn VXGE_HAL_STATS_GET_AGGRn_RX_MCAST_FRMS(val64); 2692221167Sgnn 2693221167Sgnn VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_AGGR, 2694221167Sgnn VXGE_HAL_STATS_AGGRn_RX_BCAST_FRMS_OFFSET(port)); 2695221167Sgnn 2696221167Sgnn aggr_stats->rx_bcast_frms = 2697221167Sgnn VXGE_HAL_STATS_GET_AGGRn_RX_BCAST_FRMS(val64); 2698221167Sgnn 2699221167Sgnn VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_AGGR, 2700221167Sgnn VXGE_HAL_STATS_AGGRn_RX_DISCARDED_FRMS_OFFSET(port)); 2701221167Sgnn 2702221167Sgnn aggr_stats->rx_discarded_frms = 2703221167Sgnn VXGE_HAL_STATS_GET_AGGRn_RX_DISCARDED_FRMS(val64); 2704221167Sgnn 2705221167Sgnn VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_AGGR, 2706221167Sgnn VXGE_HAL_STATS_AGGRn_RX_ERRORED_FRMS_OFFSET(port)); 2707221167Sgnn 2708221167Sgnn aggr_stats->rx_errored_frms = 2709221167Sgnn VXGE_HAL_STATS_GET_AGGRn_RX_ERRORED_FRMS(val64); 2710221167Sgnn 2711221167Sgnn VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_AGGR, 2712221167Sgnn VXGE_HAL_STATS_AGGRn_RX_U_SLOW_PROTO_FRMS_OFFSET(port)); 2713221167Sgnn 2714221167Sgnn aggr_stats->rx_unknown_slow_proto_frms = 2715221167Sgnn VXGE_HAL_STATS_GET_AGGRn_RX_U_SLOW_PROTO_FRMS(val64); 2716221167Sgnn 2717221167Sgnn vxge_hal_trace_log_stats("<== %s:%s:%d Result = %d", 2718221167Sgnn __FILE__, __func__, __LINE__, status); 2719221167Sgnn return (VXGE_HAL_OK); 2720221167Sgnn} 2721221167Sgnn 2722221167Sgnn 2723221167Sgnn/* 2724221167Sgnn * vxge_hal_mrpcim_xmac_port_stats_get - Get the Statistics on a port 2725221167Sgnn * @devh: HAL device handle. 2726221167Sgnn * @port: Number of the port (wire 0, wire 1 or LAG) 2727221167Sgnn * @port_stats: Buffer to return Statistics on a port. 2728221167Sgnn * 2729221167Sgnn * Get the Statistics on port 2730221167Sgnn * 2731221167Sgnn */ 2732221167Sgnnvxge_hal_status_e 2733221167Sgnnvxge_hal_mrpcim_xmac_port_stats_get(vxge_hal_device_h devh, 2734221167Sgnn u32 port, 2735221167Sgnn vxge_hal_xmac_port_stats_t *port_stats) 2736221167Sgnn{ 2737221167Sgnn u64 val64; 2738221167Sgnn vxge_hal_status_e status = VXGE_HAL_OK; 2739221167Sgnn __hal_device_t *hldev = (__hal_device_t *) devh; 2740221167Sgnn 2741221167Sgnn vxge_assert((devh != NULL) && (port_stats != NULL)); 2742221167Sgnn 2743221167Sgnn vxge_hal_trace_log_stats("==> %s:%s:%d", 2744221167Sgnn __FILE__, __func__, __LINE__); 2745221167Sgnn 2746221167Sgnn vxge_hal_trace_log_stats("devh = 0x"VXGE_OS_STXFMT", port = %d, " 2747221167Sgnn "port_stats = 0x"VXGE_OS_STXFMT, 2748221167Sgnn (ptr_t) devh, port, (ptr_t) port_stats); 2749221167Sgnn 2750221167Sgnn if (!(hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM)) { 2751221167Sgnn vxge_hal_trace_log_stats("<== %s:%s:%d Result = %d", 2752221167Sgnn __FILE__, __func__, __LINE__, 2753221167Sgnn VXGE_HAL_ERR_PRIVILAGED_OPEARATION); 2754221167Sgnn 2755221167Sgnn return (VXGE_HAL_ERR_PRIVILAGED_OPEARATION); 2756221167Sgnn } 2757221167Sgnn 2758221167Sgnn VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 2759221167Sgnn VXGE_HAL_STATS_PORTn_TX_TTL_FRMS_OFFSET(port)); 2760221167Sgnn 2761221167Sgnn port_stats->tx_ttl_frms = 2762221167Sgnn VXGE_HAL_STATS_GET_PORTn_TX_TTL_FRMS(val64); 2763221167Sgnn 2764221167Sgnn VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 2765221167Sgnn VXGE_HAL_STATS_PORTn_TX_TTL_FRMS_OFFSET(port)); 2766221167Sgnn 2767221167Sgnn port_stats->tx_ttl_octets = 2768221167Sgnn VXGE_HAL_STATS_GET_PORTn_TX_TTL_OCTETS(val64); 2769221167Sgnn 2770221167Sgnn VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 2771221167Sgnn VXGE_HAL_STATS_PORTn_TX_DATA_OCTETS_OFFSET(port)); 2772221167Sgnn 2773221167Sgnn port_stats->tx_data_octets = 2774221167Sgnn VXGE_HAL_STATS_GET_PORTn_TX_DATA_OCTETS(val64); 2775221167Sgnn 2776221167Sgnn VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 2777221167Sgnn VXGE_HAL_STATS_PORTn_TX_MCAST_FRMS_OFFSET(port)); 2778221167Sgnn 2779221167Sgnn port_stats->tx_mcast_frms = 2780221167Sgnn VXGE_HAL_STATS_GET_PORTn_TX_MCAST_FRMS(val64); 2781221167Sgnn 2782221167Sgnn VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 2783221167Sgnn VXGE_HAL_STATS_PORTn_TX_BCAST_FRMS_OFFSET(port)); 2784221167Sgnn 2785221167Sgnn port_stats->tx_bcast_frms = 2786221167Sgnn VXGE_HAL_STATS_GET_PORTn_TX_BCAST_FRMS(val64); 2787221167Sgnn 2788221167Sgnn VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 2789221167Sgnn VXGE_HAL_STATS_PORTn_TX_UCAST_FRMS_OFFSET(port)); 2790221167Sgnn 2791221167Sgnn port_stats->tx_ucast_frms = 2792221167Sgnn VXGE_HAL_STATS_GET_PORTn_TX_UCAST_FRMS(val64); 2793221167Sgnn 2794221167Sgnn VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 2795221167Sgnn VXGE_HAL_STATS_PORTn_TX_TAGGED_FRMS_OFFSET(port)); 2796221167Sgnn 2797221167Sgnn port_stats->tx_tagged_frms = 2798221167Sgnn VXGE_HAL_STATS_GET_PORTn_TX_TAGGED_FRMS(val64); 2799221167Sgnn 2800221167Sgnn VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 2801221167Sgnn VXGE_HAL_STATS_PORTn_TX_VLD_IP_OFFSET(port)); 2802221167Sgnn 2803221167Sgnn port_stats->tx_vld_ip = 2804221167Sgnn VXGE_HAL_STATS_GET_PORTn_TX_VLD_IP(val64); 2805221167Sgnn 2806221167Sgnn VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 2807221167Sgnn VXGE_HAL_STATS_PORTn_TX_VLD_IP_OCTETS_OFFSET(port)); 2808221167Sgnn 2809221167Sgnn port_stats->tx_vld_ip_octets = 2810221167Sgnn VXGE_HAL_STATS_GET_PORTn_TX_VLD_IP_OCTETS(val64); 2811221167Sgnn 2812221167Sgnn VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 2813221167Sgnn VXGE_HAL_STATS_PORTn_TX_ICMP_OFFSET(port)); 2814221167Sgnn 2815221167Sgnn port_stats->tx_icmp = 2816221167Sgnn VXGE_HAL_STATS_GET_PORTn_TX_ICMP(val64); 2817221167Sgnn 2818221167Sgnn VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 2819221167Sgnn VXGE_HAL_STATS_PORTn_TX_TCP_OFFSET(port)); 2820221167Sgnn 2821221167Sgnn port_stats->tx_tcp = 2822221167Sgnn VXGE_HAL_STATS_GET_PORTn_TX_TCP(val64); 2823221167Sgnn 2824221167Sgnn VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 2825221167Sgnn VXGE_HAL_STATS_PORTn_TX_RST_TCP_OFFSET(port)); 2826221167Sgnn 2827221167Sgnn port_stats->tx_rst_tcp = 2828221167Sgnn VXGE_HAL_STATS_GET_PORTn_TX_RST_TCP(val64); 2829221167Sgnn 2830221167Sgnn VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 2831221167Sgnn VXGE_HAL_STATS_PORTn_TX_UDP_OFFSET(port)); 2832221167Sgnn 2833221167Sgnn port_stats->tx_udp = 2834221167Sgnn VXGE_HAL_STATS_GET_PORTn_TX_UDP(val64); 2835221167Sgnn 2836221167Sgnn VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 2837221167Sgnn VXGE_HAL_STATS_PORTn_TX_UNKNOWN_PROTOCOL_OFFSET(port)); 2838221167Sgnn 2839221167Sgnn port_stats->tx_unknown_protocol = 2840221167Sgnn (u32) VXGE_HAL_STATS_GET_PORTn_TX_UNKNOWN_PROTOCOL(val64); 2841221167Sgnn 2842221167Sgnn VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 2843221167Sgnn VXGE_HAL_STATS_PORTn_TX_PARSE_ERROR_OFFSET(port)); 2844221167Sgnn 2845221167Sgnn port_stats->tx_parse_error = 2846221167Sgnn (u32) VXGE_HAL_STATS_GET_PORTn_TX_PARSE_ERROR(val64); 2847221167Sgnn 2848221167Sgnn VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 2849221167Sgnn VXGE_HAL_STATS_PORTn_TX_PAUSE_CTRL_FRMS_OFFSET(port)); 2850221167Sgnn 2851221167Sgnn port_stats->tx_pause_ctrl_frms = 2852221167Sgnn VXGE_HAL_STATS_GET_PORTn_TX_PAUSE_CTRL_FRMS(val64); 2853221167Sgnn 2854221167Sgnn VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 2855221167Sgnn VXGE_HAL_STATS_PORTn_TX_LACPDU_FRMS_OFFSET(port)); 2856221167Sgnn 2857221167Sgnn port_stats->tx_lacpdu_frms = 2858221167Sgnn (u32) VXGE_HAL_STATS_GET_PORTn_TX_LACPDU_FRMS(val64); 2859221167Sgnn 2860221167Sgnn VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 2861221167Sgnn VXGE_HAL_STATS_PORTn_TX_MRKR_PDU_FRMS_OFFSET(port)); 2862221167Sgnn 2863221167Sgnn port_stats->tx_marker_pdu_frms = 2864221167Sgnn (u32) VXGE_HAL_STATS_GET_PORTn_TX_MRKR_PDU_FRMS(val64); 2865221167Sgnn 2866221167Sgnn VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 2867221167Sgnn VXGE_HAL_STATS_PORTn_TX_MRKR_RESP_PDU_FRMS_OFFSET(port)); 2868221167Sgnn 2869221167Sgnn port_stats->tx_marker_resp_pdu_frms = 2870221167Sgnn (u32) VXGE_HAL_STATS_GET_PORTn_TX_MRKR_RESP_PDU_FRMS(val64); 2871221167Sgnn 2872221167Sgnn VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 2873221167Sgnn VXGE_HAL_STATS_PORTn_TX_DROP_IP_OFFSET(port)); 2874221167Sgnn 2875221167Sgnn port_stats->tx_drop_ip = 2876221167Sgnn (u32) VXGE_HAL_STATS_GET_PORTn_TX_DROP_IP(val64); 2877221167Sgnn 2878221167Sgnn VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 2879221167Sgnn VXGE_HAL_STATS_PORTn_TX_XGMII_CHAR1_MATCH_OFFSET(port)); 2880221167Sgnn 2881221167Sgnn port_stats->tx_xgmii_char1_match = 2882221167Sgnn (u32) VXGE_HAL_STATS_GET_PORTn_TX_XGMII_CHAR1_MATCH(val64); 2883221167Sgnn 2884221167Sgnn VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 2885221167Sgnn VXGE_HAL_STATS_PORTn_TX_XGMII_CHAR2_MATCH_OFFSET(port)); 2886221167Sgnn 2887221167Sgnn port_stats->tx_xgmii_char2_match = 2888221167Sgnn (u32) VXGE_HAL_STATS_GET_PORTn_TX_XGMII_CHAR2_MATCH(val64); 2889221167Sgnn 2890221167Sgnn VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 2891221167Sgnn VXGE_HAL_STATS_PORTn_TX_XGMII_COL1_MATCH_OFFSET(port)); 2892221167Sgnn 2893221167Sgnn port_stats->tx_xgmii_column1_match = 2894221167Sgnn (u32) VXGE_HAL_STATS_GET_PORTn_TX_XGMII_COL1_MATCH(val64); 2895221167Sgnn 2896221167Sgnn VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 2897221167Sgnn VXGE_HAL_STATS_PORTn_TX_XGMII_COL2_MATCH_OFFSET(port)); 2898221167Sgnn 2899221167Sgnn port_stats->tx_xgmii_column2_match = 2900221167Sgnn (u32) VXGE_HAL_STATS_GET_PORTn_TX_XGMII_COL2_MATCH(val64); 2901221167Sgnn 2902221167Sgnn VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 2903221167Sgnn VXGE_HAL_STATS_PORTn_TX_DROP_FRMS_OFFSET(port)); 2904221167Sgnn 2905221167Sgnn port_stats->tx_drop_frms = 2906221167Sgnn (u16) VXGE_HAL_STATS_GET_PORTn_TX_DROP_FRMS(val64); 2907221167Sgnn 2908221167Sgnn VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 2909221167Sgnn VXGE_HAL_STATS_PORTn_TX_ANY_ERR_FRMS_OFFSET(port)); 2910221167Sgnn 2911221167Sgnn port_stats->tx_any_err_frms = 2912221167Sgnn (u16) VXGE_HAL_STATS_GET_PORTn_TX_ANY_ERR_FRMS(val64); 2913221167Sgnn 2914221167Sgnn VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 2915221167Sgnn VXGE_HAL_STATS_PORTn_RX_TTL_FRMS_OFFSET(port)); 2916221167Sgnn 2917221167Sgnn port_stats->rx_ttl_frms = 2918221167Sgnn VXGE_HAL_STATS_GET_PORTn_RX_TTL_FRMS(val64); 2919221167Sgnn 2920221167Sgnn VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 2921221167Sgnn VXGE_HAL_STATS_PORTn_RX_VLD_FRMS_OFFSET(port)); 2922221167Sgnn 2923221167Sgnn port_stats->rx_vld_frms = 2924221167Sgnn VXGE_HAL_STATS_GET_PORTn_RX_VLD_FRMS(val64); 2925221167Sgnn 2926221167Sgnn VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 2927221167Sgnn VXGE_HAL_STATS_PORTn_RX_OFFLOAD_FRMS_OFFSET(port)); 2928221167Sgnn 2929221167Sgnn port_stats->rx_offload_frms = 2930221167Sgnn VXGE_HAL_STATS_GET_PORTn_RX_OFFLOAD_FRMS(val64); 2931221167Sgnn 2932221167Sgnn VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 2933221167Sgnn VXGE_HAL_STATS_PORTn_RX_TTL_OCTETS_OFFSET(port)); 2934221167Sgnn 2935221167Sgnn port_stats->rx_ttl_octets = 2936221167Sgnn VXGE_HAL_STATS_GET_PORTn_RX_TTL_OCTETS(val64); 2937221167Sgnn 2938221167Sgnn VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 2939221167Sgnn VXGE_HAL_STATS_PORTn_RX_DATA_OCTETS_OFFSET(port)); 2940221167Sgnn 2941221167Sgnn port_stats->rx_data_octets = 2942221167Sgnn VXGE_HAL_STATS_GET_PORTn_RX_DATA_OCTETS(val64); 2943221167Sgnn 2944221167Sgnn VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 2945221167Sgnn VXGE_HAL_STATS_PORTn_RX_OFFLOAD_OCTETS_OFFSET(port)); 2946221167Sgnn 2947221167Sgnn port_stats->rx_offload_octets = 2948221167Sgnn VXGE_HAL_STATS_GET_PORTn_RX_OFFLOAD_OCTETS(val64); 2949221167Sgnn 2950221167Sgnn VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 2951221167Sgnn VXGE_HAL_STATS_PORTn_RX_VLD_MCAST_FRMS_OFFSET(port)); 2952221167Sgnn 2953221167Sgnn port_stats->rx_vld_mcast_frms = 2954221167Sgnn VXGE_HAL_STATS_GET_PORTn_RX_VLD_MCAST_FRMS(val64); 2955221167Sgnn 2956221167Sgnn VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 2957221167Sgnn VXGE_HAL_STATS_PORTn_RX_VLD_BCAST_FRMS_OFFSET(port)); 2958221167Sgnn 2959221167Sgnn port_stats->rx_vld_bcast_frms = 2960221167Sgnn VXGE_HAL_STATS_GET_PORTn_RX_VLD_BCAST_FRMS(val64); 2961221167Sgnn 2962221167Sgnn VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 2963221167Sgnn VXGE_HAL_STATS_PORTn_RX_ACC_UCAST_FRMS_OFFSET(port)); 2964221167Sgnn 2965221167Sgnn port_stats->rx_accepted_ucast_frms = 2966221167Sgnn VXGE_HAL_STATS_GET_PORTn_RX_ACC_UCAST_FRMS(val64); 2967221167Sgnn 2968221167Sgnn VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 2969221167Sgnn VXGE_HAL_STATS_PORTn_RX_ACC_NUCAST_FRMS_OFFSET(port)); 2970221167Sgnn 2971221167Sgnn port_stats->rx_accepted_nucast_frms = 2972221167Sgnn VXGE_HAL_STATS_GET_PORTn_RX_ACC_NUCAST_FRMS(val64); 2973221167Sgnn 2974221167Sgnn VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 2975221167Sgnn VXGE_HAL_STATS_PORTn_RX_TAGGED_FRMS_OFFSET(port)); 2976221167Sgnn 2977221167Sgnn port_stats->rx_tagged_frms = 2978221167Sgnn VXGE_HAL_STATS_GET_PORTn_RX_TAGGED_FRMS(val64); 2979221167Sgnn 2980221167Sgnn VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 2981221167Sgnn VXGE_HAL_STATS_PORTn_RX_LONG_FRMS_OFFSET(port)); 2982221167Sgnn 2983221167Sgnn port_stats->rx_long_frms = 2984221167Sgnn VXGE_HAL_STATS_GET_PORTn_RX_LONG_FRMS(val64); 2985221167Sgnn 2986221167Sgnn VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 2987221167Sgnn VXGE_HAL_STATS_PORTn_RX_USIZED_FRMS_OFFSET(port)); 2988221167Sgnn 2989221167Sgnn port_stats->rx_usized_frms = 2990221167Sgnn VXGE_HAL_STATS_GET_PORTn_RX_USIZED_FRMS(val64); 2991221167Sgnn 2992221167Sgnn VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 2993221167Sgnn VXGE_HAL_STATS_PORTn_RX_OSIZED_FRMS_OFFSET(port)); 2994221167Sgnn 2995221167Sgnn port_stats->rx_osized_frms = 2996221167Sgnn VXGE_HAL_STATS_GET_PORTn_RX_OSIZED_FRMS(val64); 2997221167Sgnn 2998221167Sgnn VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 2999221167Sgnn VXGE_HAL_STATS_PORTn_RX_FRAG_FRMS_OFFSET(port)); 3000221167Sgnn 3001221167Sgnn port_stats->rx_frag_frms = 3002221167Sgnn VXGE_HAL_STATS_GET_PORTn_RX_FRAG_FRMS(val64); 3003221167Sgnn 3004221167Sgnn VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 3005221167Sgnn VXGE_HAL_STATS_PORTn_RX_JABBER_FRMS_OFFSET(port)); 3006221167Sgnn 3007221167Sgnn port_stats->rx_jabber_frms = 3008221167Sgnn VXGE_HAL_STATS_GET_PORTn_RX_JABBER_FRMS(val64); 3009221167Sgnn 3010221167Sgnn VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 3011221167Sgnn VXGE_HAL_STATS_PORTn_RX_TTL_64_FRMS_OFFSET(port)); 3012221167Sgnn 3013221167Sgnn port_stats->rx_ttl_64_frms = 3014221167Sgnn VXGE_HAL_STATS_GET_PORTn_RX_TTL_64_FRMS(val64); 3015221167Sgnn 3016221167Sgnn VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 3017221167Sgnn VXGE_HAL_STATS_PORTn_RX_TTL_65_127_FRMS_OFFSET(port)); 3018221167Sgnn 3019221167Sgnn port_stats->rx_ttl_65_127_frms = 3020221167Sgnn VXGE_HAL_STATS_GET_PORTn_RX_TTL_65_127_FRMS(val64); 3021221167Sgnn 3022221167Sgnn VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 3023221167Sgnn VXGE_HAL_STATS_PORTn_RX_TTL_128_255_FRMS_OFFSET(port)); 3024221167Sgnn 3025221167Sgnn port_stats->rx_ttl_128_255_frms = 3026221167Sgnn VXGE_HAL_STATS_GET_PORTn_RX_TTL_128_255_FRMS(val64); 3027221167Sgnn 3028221167Sgnn VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 3029221167Sgnn VXGE_HAL_STATS_PORTn_RX_TTL_256_511_FRMS_OFFSET(port)); 3030221167Sgnn 3031221167Sgnn port_stats->rx_ttl_256_511_frms = 3032221167Sgnn VXGE_HAL_STATS_GET_PORTn_RX_TTL_256_511_FRMS(val64); 3033221167Sgnn 3034221167Sgnn VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 3035221167Sgnn VXGE_HAL_STATS_PORTn_RX_TTL_512_1023_FRMS_OFFSET(port)); 3036221167Sgnn 3037221167Sgnn port_stats->rx_ttl_512_1023_frms = 3038221167Sgnn VXGE_HAL_STATS_GET_PORTn_RX_TTL_512_1023_FRMS(val64); 3039221167Sgnn 3040221167Sgnn VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 3041221167Sgnn VXGE_HAL_STATS_PORTn_RX_TTL_1024_1518_FRMS_OFFSET(port)); 3042221167Sgnn 3043221167Sgnn port_stats->rx_ttl_1024_1518_frms = 3044221167Sgnn VXGE_HAL_STATS_GET_PORTn_RX_TTL_1024_1518_FRMS(val64); 3045221167Sgnn 3046221167Sgnn VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 3047221167Sgnn VXGE_HAL_STATS_PORTn_RX_TTL_1519_4095_FRMS_OFFSET(port)); 3048221167Sgnn 3049221167Sgnn port_stats->rx_ttl_1519_4095_frms = 3050221167Sgnn VXGE_HAL_STATS_GET_PORTn_RX_TTL_1519_4095_FRMS(val64); 3051221167Sgnn 3052221167Sgnn VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 3053221167Sgnn VXGE_HAL_STATS_PORTn_RX_TTL_4096_81915_FRMS_OFFSET(port)); 3054221167Sgnn 3055221167Sgnn port_stats->rx_ttl_4096_8191_frms = 3056221167Sgnn VXGE_HAL_STATS_GET_PORTn_RX_TTL_4096_8191_FRMS(val64); 3057221167Sgnn 3058221167Sgnn VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 3059221167Sgnn VXGE_HAL_STATS_PORTn_RX_TTL_8192_MAX_FRMS_OFFSET(port)); 3060221167Sgnn 3061221167Sgnn port_stats->rx_ttl_8192_max_frms = 3062221167Sgnn VXGE_HAL_STATS_GET_PORTn_RX_TTL_8192_MAX_FRMS(val64); 3063221167Sgnn 3064221167Sgnn VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 3065221167Sgnn VXGE_HAL_STATS_PORTn_RX_TTL_GT_MAX_FRMS_OFFSET(port)); 3066221167Sgnn 3067221167Sgnn port_stats->rx_ttl_gt_max_frms = 3068221167Sgnn VXGE_HAL_STATS_GET_PORTn_RX_TTL_GT_MAX_FRMS(val64); 3069221167Sgnn 3070221167Sgnn VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 3071221167Sgnn VXGE_HAL_STATS_PORTn_RX_IP_OFFSET(port)); 3072221167Sgnn 3073221167Sgnn port_stats->rx_ip = VXGE_HAL_STATS_GET_PORTn_RX_IP(val64); 3074221167Sgnn 3075221167Sgnn VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 3076221167Sgnn VXGE_HAL_STATS_PORTn_RX_ACC_IP_OFFSET(port)); 3077221167Sgnn 3078221167Sgnn port_stats->rx_accepted_ip = 3079221167Sgnn VXGE_HAL_STATS_GET_PORTn_RX_ACC_IP(val64); 3080221167Sgnn 3081221167Sgnn VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 3082221167Sgnn VXGE_HAL_STATS_PORTn_RX_IP_OCTETS_OFFSET(port)); 3083221167Sgnn 3084221167Sgnn port_stats->rx_ip_octets = 3085221167Sgnn VXGE_HAL_STATS_GET_PORTn_RX_IP_OCTETS(val64); 3086221167Sgnn 3087221167Sgnn VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 3088221167Sgnn VXGE_HAL_STATS_PORTn_RX_ERR_IP_OFFSET(port)); 3089221167Sgnn 3090221167Sgnn port_stats->rx_err_ip = 3091221167Sgnn VXGE_HAL_STATS_GET_PORTn_RX_ERR_IP(val64); 3092221167Sgnn 3093221167Sgnn VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 3094221167Sgnn VXGE_HAL_STATS_PORTn_RX_ICMP_OFFSET(port)); 3095221167Sgnn 3096221167Sgnn port_stats->rx_icmp = VXGE_HAL_STATS_GET_PORTn_RX_ICMP(val64); 3097221167Sgnn 3098221167Sgnn VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 3099221167Sgnn VXGE_HAL_STATS_PORTn_RX_TCP_OFFSET(port)); 3100221167Sgnn 3101221167Sgnn port_stats->rx_tcp = VXGE_HAL_STATS_GET_PORTn_RX_TCP(val64); 3102221167Sgnn 3103221167Sgnn VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 3104221167Sgnn VXGE_HAL_STATS_PORTn_RX_UDP_OFFSET(port)); 3105221167Sgnn 3106221167Sgnn port_stats->rx_udp = VXGE_HAL_STATS_GET_PORTn_RX_UDP(val64); 3107221167Sgnn 3108221167Sgnn VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 3109221167Sgnn VXGE_HAL_STATS_PORTn_RX_ERR_TCP_OFFSET(port)); 3110221167Sgnn 3111221167Sgnn port_stats->rx_err_tcp = VXGE_HAL_STATS_GET_PORTn_RX_ERR_TCP(val64); 3112221167Sgnn 3113221167Sgnn VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 3114221167Sgnn VXGE_HAL_STATS_PORTn_RX_PAUSE_CNT_OFFSET(port)); 3115221167Sgnn 3116221167Sgnn port_stats->rx_pause_count = 3117221167Sgnn VXGE_HAL_STATS_GET_PORTn_RX_PAUSE_CNT(val64); 3118221167Sgnn 3119221167Sgnn VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 3120221167Sgnn VXGE_HAL_STATS_PORTn_RX_PAUSE_CTRL_FRMS_OFFSET(port)); 3121221167Sgnn 3122221167Sgnn port_stats->rx_pause_ctrl_frms = 3123221167Sgnn VXGE_HAL_STATS_GET_PORTn_RX_PAUSE_CTRL_FRMS(val64); 3124221167Sgnn 3125221167Sgnn VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 3126221167Sgnn VXGE_HAL_STATS_PORTn_RX_UNSUP_CTRL_FRMS_OFFSET(port)); 3127221167Sgnn 3128221167Sgnn port_stats->rx_unsup_ctrl_frms = 3129221167Sgnn VXGE_HAL_STATS_GET_PORTn_RX_UNSUP_CTRL_FRMS(val64); 3130221167Sgnn 3131221167Sgnn VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 3132221167Sgnn VXGE_HAL_STATS_PORTn_RX_FCS_ERR_FRMS_OFFSET(port)); 3133221167Sgnn 3134221167Sgnn port_stats->rx_fcs_err_frms = 3135221167Sgnn VXGE_HAL_STATS_GET_PORTn_RX_FCS_ERR_FRMS(val64); 3136221167Sgnn 3137221167Sgnn VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 3138221167Sgnn VXGE_HAL_STATS_PORTn_RX_IN_RNG_LEN_ERR_FRMS_OFFSET(port)); 3139221167Sgnn 3140221167Sgnn port_stats->rx_in_rng_len_err_frms = 3141221167Sgnn VXGE_HAL_STATS_GET_PORTn_RX_IN_RNG_LEN_ERR_FRMS(val64); 3142221167Sgnn 3143221167Sgnn VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 3144221167Sgnn VXGE_HAL_STATS_PORTn_RX_OUT_RNG_LEN_ERR_FRMS_OFFSET(port)); 3145221167Sgnn 3146221167Sgnn port_stats->rx_out_rng_len_err_frms = 3147221167Sgnn VXGE_HAL_STATS_GET_PORTn_RX_OUT_RNG_LEN_ERR_FRMS(val64); 3148221167Sgnn 3149221167Sgnn VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 3150221167Sgnn VXGE_HAL_STATS_PORTn_RX_DROP_FRMS_OFFSET(port)); 3151221167Sgnn 3152221167Sgnn port_stats->rx_drop_frms = 3153221167Sgnn VXGE_HAL_STATS_GET_PORTn_RX_DROP_FRMS(val64); 3154221167Sgnn 3155221167Sgnn VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 3156221167Sgnn VXGE_HAL_STATS_PORTn_RX_DISCARDED_FRMS_OFFSET(port)); 3157221167Sgnn 3158221167Sgnn port_stats->rx_discarded_frms = 3159221167Sgnn VXGE_HAL_STATS_GET_PORTn_RX_DISCARDED_FRMS(val64); 3160221167Sgnn 3161221167Sgnn VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 3162221167Sgnn VXGE_HAL_STATS_PORTn_RX_DROP_IP_OFFSET(port)); 3163221167Sgnn 3164221167Sgnn port_stats->rx_drop_ip = 3165221167Sgnn VXGE_HAL_STATS_GET_PORTn_RX_DROP_IP(val64); 3166221167Sgnn 3167221167Sgnn VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 3168221167Sgnn VXGE_HAL_STATS_PORTn_RX_DRP_UDP_OFFSET(port)); 3169221167Sgnn 3170221167Sgnn port_stats->rx_drop_udp = 3171221167Sgnn VXGE_HAL_STATS_GET_PORTn_RX_DRP_UDP(val64); 3172221167Sgnn 3173221167Sgnn VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 3174221167Sgnn VXGE_HAL_STATS_PORTn_RX_LACPDU_FRMS_OFFSET(port)); 3175221167Sgnn 3176221167Sgnn port_stats->rx_lacpdu_frms = 3177221167Sgnn (u32) VXGE_HAL_STATS_GET_PORTn_RX_LACPDU_FRMS(val64); 3178221167Sgnn 3179221167Sgnn VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 3180221167Sgnn VXGE_HAL_STATS_PORTn_RX_MRKR_PDU_FRMS_OFFSET(port)); 3181221167Sgnn 3182221167Sgnn port_stats->rx_marker_pdu_frms = 3183221167Sgnn (u32) VXGE_HAL_STATS_GET_PORTn_RX_MRKR_PDU_FRMS(val64); 3184221167Sgnn 3185221167Sgnn VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 3186221167Sgnn VXGE_HAL_STATS_PORTn_RX_MRKR_RESP_PDU_FRMS_OFFSET(port)); 3187221167Sgnn 3188221167Sgnn port_stats->rx_marker_resp_pdu_frms = 3189221167Sgnn (u32) VXGE_HAL_STATS_GET_PORTn_RX_MRKR_RESP_PDU_FRMS(val64); 3190221167Sgnn 3191221167Sgnn VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 3192221167Sgnn VXGE_HAL_STATS_PORTn_RX_UNKNOWN_PDU_FRMS_OFFSET(port)); 3193221167Sgnn 3194221167Sgnn port_stats->rx_unknown_pdu_frms = 3195221167Sgnn (u32) VXGE_HAL_STATS_GET_PORTn_RX_UNKNOWN_PDU_FRMS(val64); 3196221167Sgnn 3197221167Sgnn VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 3198221167Sgnn VXGE_HAL_STATS_PORTn_RX_ILLEGAL_PDU_FRMS_OFFSET(port)); 3199221167Sgnn 3200221167Sgnn port_stats->rx_illegal_pdu_frms = 3201221167Sgnn (u32) VXGE_HAL_STATS_GET_PORTn_RX_ILLEGAL_PDU_FRMS(val64); 3202221167Sgnn 3203221167Sgnn VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 3204221167Sgnn VXGE_HAL_STATS_PORTn_RX_FCS_DISCARD_OFFSET(port)); 3205221167Sgnn 3206221167Sgnn port_stats->rx_fcs_discard = 3207221167Sgnn (u32) VXGE_HAL_STATS_GET_PORTn_RX_FCS_DISCARD(val64); 3208221167Sgnn 3209221167Sgnn VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 3210221167Sgnn VXGE_HAL_STATS_PORTn_RX_LEN_DISCARD_OFFSET(port)); 3211221167Sgnn 3212221167Sgnn port_stats->rx_len_discard = 3213221167Sgnn (u32) VXGE_HAL_STATS_GET_PORTn_RX_LEN_DISCARD(val64); 3214221167Sgnn 3215221167Sgnn VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 3216221167Sgnn VXGE_HAL_STATS_PORTn_RX_SWITCH_DISCARD_OFFSET(port)); 3217221167Sgnn 3218221167Sgnn port_stats->rx_switch_discard = 3219221167Sgnn (u32) VXGE_HAL_STATS_GET_PORTn_RX_SWITCH_DISCARD(val64); 3220221167Sgnn 3221221167Sgnn VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 3222221167Sgnn VXGE_HAL_STATS_PORTn_RX_L2_MGMT_DISCARD_OFFSET(port)); 3223221167Sgnn 3224221167Sgnn port_stats->rx_l2_mgmt_discard = 3225221167Sgnn (u32) VXGE_HAL_STATS_GET_PORTn_RX_L2_MGMT_DISCARD(val64); 3226221167Sgnn 3227221167Sgnn VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 3228221167Sgnn VXGE_HAL_STATS_PORTn_RX_RPA_DISCARD_OFFSET(port)); 3229221167Sgnn 3230221167Sgnn port_stats->rx_rpa_discard = 3231221167Sgnn (u32) VXGE_HAL_STATS_GET_PORTn_RX_RPA_DISCARD(val64); 3232221167Sgnn 3233221167Sgnn VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 3234221167Sgnn VXGE_HAL_STATS_PORTn_RX_TRASH_DISCARD_OFFSET(port)); 3235221167Sgnn 3236221167Sgnn port_stats->rx_trash_discard = 3237221167Sgnn (u32) VXGE_HAL_STATS_GET_PORTn_RX_TRASH_DISCARD(val64); 3238221167Sgnn 3239221167Sgnn VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 3240221167Sgnn VXGE_HAL_STATS_PORTn_RX_RTS_DISCARD_OFFSET(port)); 3241221167Sgnn 3242221167Sgnn port_stats->rx_rts_discard = 3243221167Sgnn (u32) VXGE_HAL_STATS_GET_PORTn_RX_RTS_DISCARD(val64); 3244221167Sgnn 3245221167Sgnn VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 3246221167Sgnn VXGE_HAL_STATS_PORTn_RX_RED_DISCARD_OFFSET(port)); 3247221167Sgnn 3248221167Sgnn port_stats->rx_red_discard = 3249221167Sgnn (u32) VXGE_HAL_STATS_GET_PORTn_RX_RED_DISCARD(val64); 3250221167Sgnn 3251221167Sgnn VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 3252221167Sgnn VXGE_HAL_STATS_PORTn_RX_BUFF_FULL_DISCARD_OFFSET(port)); 3253221167Sgnn 3254221167Sgnn port_stats->rx_buff_full_discard = 3255221167Sgnn (u32) VXGE_HAL_STATS_GET_PORTn_RX_BUFF_FULL_DISCARD(val64); 3256221167Sgnn 3257221167Sgnn VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 3258221167Sgnn VXGE_HAL_STATS_PORTn_RX_XGMII_DATA_ERR_CNT_OFFSET(port)); 3259221167Sgnn 3260221167Sgnn port_stats->rx_xgmii_data_err_cnt = 3261221167Sgnn (u32) VXGE_HAL_STATS_GET_PORTn_RX_XGMII_DATA_ERR_CNT(val64); 3262221167Sgnn 3263221167Sgnn VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 3264221167Sgnn VXGE_HAL_STATS_PORTn_RX_XGMII_CTRL_ERR_CNT_OFFSET(port)); 3265221167Sgnn 3266221167Sgnn port_stats->rx_xgmii_ctrl_err_cnt = 3267221167Sgnn (u32) VXGE_HAL_STATS_GET_PORTn_RX_XGMII_CTRL_ERR_CNT(val64); 3268221167Sgnn 3269221167Sgnn VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 3270221167Sgnn VXGE_HAL_STATS_PORTn_RX_XGMII_ERR_SYM_OFFSET(port)); 3271221167Sgnn 3272221167Sgnn port_stats->rx_xgmii_err_sym = 3273221167Sgnn (u32) VXGE_HAL_STATS_GET_PORTn_RX_XGMII_ERR_SYM(val64); 3274221167Sgnn 3275221167Sgnn VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 3276221167Sgnn VXGE_HAL_STATS_PORTn_RX_XGMII_CHAR1_MATCH_OFFSET(port)); 3277221167Sgnn 3278221167Sgnn port_stats->rx_xgmii_char1_match = 3279221167Sgnn (u32) VXGE_HAL_STATS_GET_PORTn_RX_XGMII_CHAR1_MATCH(val64); 3280221167Sgnn 3281221167Sgnn VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 3282221167Sgnn VXGE_HAL_STATS_PORTn_RX_XGMII_CHAR2_MATCH_OFFSET(port)); 3283221167Sgnn 3284221167Sgnn port_stats->rx_xgmii_char2_match = 3285221167Sgnn (u32) VXGE_HAL_STATS_GET_PORTn_RX_XGMII_CHAR2_MATCH(val64); 3286221167Sgnn 3287221167Sgnn VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 3288221167Sgnn VXGE_HAL_STATS_PORTn_RX_XGMII_COL1_MATCH_OFFSET(port)); 3289221167Sgnn 3290221167Sgnn port_stats->rx_xgmii_column1_match = 3291221167Sgnn (u32) VXGE_HAL_STATS_GET_PORTn_RX_XGMII_COL1_MATCH(val64); 3292221167Sgnn 3293221167Sgnn VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 3294221167Sgnn VXGE_HAL_STATS_PORTn_RX_XGMII_COL2_MATCH_OFFSET(port)); 3295221167Sgnn 3296221167Sgnn port_stats->rx_xgmii_column2_match = 3297221167Sgnn (u32) VXGE_HAL_STATS_GET_PORTn_RX_XGMII_COL2_MATCH(val64); 3298221167Sgnn 3299221167Sgnn VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 3300221167Sgnn VXGE_HAL_STATS_PORTn_RX_LOCAL_FAULT_OFFSET(port)); 3301221167Sgnn 3302221167Sgnn port_stats->rx_local_fault = 3303221167Sgnn (u32) VXGE_HAL_STATS_GET_PORTn_RX_LOCAL_FAULT(val64); 3304221167Sgnn 3305221167Sgnn VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 3306221167Sgnn VXGE_HAL_STATS_PORTn_RX_REMOTE_FAULT_OFFSET(port)); 3307221167Sgnn 3308221167Sgnn port_stats->rx_remote_fault = 3309221167Sgnn (u32) VXGE_HAL_STATS_GET_PORTn_RX_REMOTE_FAULT(val64); 3310221167Sgnn 3311221167Sgnn VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 3312221167Sgnn VXGE_HAL_STATS_PORTn_RX_JETTISON_OFFSET(port)); 3313221167Sgnn 3314221167Sgnn port_stats->rx_jettison = 3315221167Sgnn (u32) VXGE_HAL_STATS_GET_PORTn_RX_JETTISON(val64); 3316221167Sgnn 3317221167Sgnn 3318221167Sgnn vxge_hal_trace_log_stats("<== %s:%s:%d Result = %d", 3319221167Sgnn __FILE__, __func__, __LINE__, status); 3320221167Sgnn return (VXGE_HAL_OK); 3321221167Sgnn} 3322221167Sgnn 3323221167Sgnn 3324221167Sgnn/* 3325221167Sgnn * vxge_hal_mrpcim_xmac_stats_get - Get the XMAC Statistics 3326221167Sgnn * @devh: HAL device handle. 3327221167Sgnn * @xmac_stats: Buffer to return XMAC Statistics. 3328221167Sgnn * 3329221167Sgnn * Get the XMAC Statistics 3330221167Sgnn * 3331221167Sgnn */ 3332221167Sgnnvxge_hal_status_e 3333221167Sgnnvxge_hal_mrpcim_xmac_stats_get(vxge_hal_device_h devh, 3334221167Sgnn vxge_hal_mrpcim_xmac_stats_t *xmac_stats) 3335221167Sgnn{ 3336221167Sgnn u32 i; 3337221167Sgnn __hal_device_t *hldev = (__hal_device_t *) devh; 3338221167Sgnn vxge_hal_status_e status = VXGE_HAL_OK; 3339221167Sgnn 3340221167Sgnn vxge_assert((devh != NULL) && (xmac_stats != NULL)); 3341221167Sgnn 3342221167Sgnn vxge_hal_trace_log_stats("==> %s:%s:%d", 3343221167Sgnn __FILE__, __func__, __LINE__); 3344221167Sgnn 3345221167Sgnn vxge_hal_trace_log_stats( 3346221167Sgnn "hldev = 0x"VXGE_OS_STXFMT", mrpcim_stats = 0x"VXGE_OS_STXFMT, 3347221167Sgnn (ptr_t) devh, (ptr_t) xmac_stats); 3348221167Sgnn 3349221167Sgnn 3350221167Sgnn if (!(hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM)) { 3351221167Sgnn vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = %d", 3352221167Sgnn __FILE__, __func__, __LINE__, 3353221167Sgnn VXGE_HAL_ERR_PRIVILAGED_OPEARATION); 3354221167Sgnn 3355221167Sgnn return (VXGE_HAL_ERR_PRIVILAGED_OPEARATION); 3356221167Sgnn } 3357221167Sgnn 3358221167Sgnn status = vxge_hal_mrpcim_xmac_aggr_stats_get(devh, 3359221167Sgnn 0, 3360221167Sgnn &xmac_stats->aggr_stats[0]); 3361221167Sgnn 3362221167Sgnn if (status != VXGE_HAL_OK) { 3363221167Sgnn vxge_hal_trace_log_stats("<== %s:%s:%d Result = %d", 3364221167Sgnn __FILE__, __func__, __LINE__, status); 3365221167Sgnn return (status); 3366221167Sgnn } 3367221167Sgnn 3368221167Sgnn status = vxge_hal_mrpcim_xmac_aggr_stats_get(devh, 3369221167Sgnn 1, 3370221167Sgnn &xmac_stats->aggr_stats[1]); 3371221167Sgnn 3372221167Sgnn if (status != VXGE_HAL_OK) { 3373221167Sgnn vxge_hal_trace_log_stats("<== %s:%s:%d Result = %d", 3374221167Sgnn __FILE__, __func__, __LINE__, status); 3375221167Sgnn return (status); 3376221167Sgnn } 3377221167Sgnn 3378221167Sgnn for (i = 0; i < VXGE_HAL_MAC_MAX_PORTS; i++) { 3379221167Sgnn 3380221167Sgnn status = vxge_hal_mrpcim_xmac_port_stats_get(devh, 3381221167Sgnn i, 3382221167Sgnn &xmac_stats->port_stats[i]); 3383221167Sgnn 3384221167Sgnn if (status != VXGE_HAL_OK) { 3385221167Sgnn vxge_hal_trace_log_stats("<== %s:%s:%d Result = %d", 3386221167Sgnn __FILE__, __func__, __LINE__, status); 3387221167Sgnn return (status); 3388221167Sgnn } 3389221167Sgnn 3390221167Sgnn } 3391221167Sgnn 3392221167Sgnn vxge_hal_trace_log_stats("<== %s:%s:%d Result = %d", 3393221167Sgnn __FILE__, __func__, __LINE__, status); 3394221167Sgnn return (status); 3395221167Sgnn} 3396221167Sgnn 3397221167Sgnn/* 3398221167Sgnn * _hal_mrpcim_stats_get - Get the mrpcim statistics using PIO 3399221167Sgnn * @hldev: hal device. 3400221167Sgnn * @mrpcim_stats: MRPCIM stats 3401221167Sgnn * 3402221167Sgnn * Returns the mrpcim stats. 3403221167Sgnn * 3404221167Sgnn * See also: vxge_hal_mrpcim_stats_enable(), vxge_hal_mrpcim_stats_disable() 3405221167Sgnn */ 3406221167Sgnnvxge_hal_status_e 3407221167Sgnn__hal_mrpcim_stats_get( 3408221167Sgnn __hal_device_t *hldev, 3409221167Sgnn vxge_hal_mrpcim_stats_hw_info_t *mrpcim_stats) 3410221167Sgnn{ 3411221167Sgnn u32 i; 3412221167Sgnn u64 val64; 3413221167Sgnn vxge_hal_device_h devh = (vxge_hal_device_h) hldev; 3414221167Sgnn vxge_hal_status_e status = VXGE_HAL_OK; 3415221167Sgnn 3416221167Sgnn vxge_assert((hldev != NULL) && (mrpcim_stats != NULL)); 3417221167Sgnn 3418221167Sgnn vxge_hal_trace_log_stats("==> %s:%s:%d", 3419221167Sgnn __FILE__, __func__, __LINE__); 3420221167Sgnn 3421221167Sgnn vxge_hal_trace_log_stats( 3422221167Sgnn "hldev = 0x"VXGE_OS_STXFMT", mrpcim_stats = 0x"VXGE_OS_STXFMT, 3423221167Sgnn (ptr_t) hldev, (ptr_t) mrpcim_stats); 3424221167Sgnn 3425221167Sgnn val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 3426221167Sgnn hldev->header.regh0, 3427221167Sgnn &hldev->mrpcim_reg->mrpcim_debug_stats0); 3428221167Sgnn 3429221167Sgnn mrpcim_stats->pic_ini_rd_drop = 3430221167Sgnn (u32) VXGE_HAL_MRPCIM_DEBUG_STATS0_GET_INI_RD_DROP(val64); 3431221167Sgnn 3432221167Sgnn mrpcim_stats->pic_ini_wr_drop = 3433221167Sgnn (u32) VXGE_HAL_MRPCIM_DEBUG_STATS0_GET_INI_WR_DROP(val64); 3434221167Sgnn 3435221167Sgnn for (i = 0; i < VXGE_HAL_MAX_VIRTUAL_PATHS; i++) { 3436221167Sgnn val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 3437221167Sgnn hldev->header.regh0, 3438221167Sgnn &hldev->mrpcim_reg->mrpcim_debug_stats1_vplane[i]); 3439221167Sgnn 3440221167Sgnn mrpcim_stats->pic_wrcrdtarb_ph_crdt_depleted_vplane[i]. 3441221167Sgnn pic_wrcrdtarb_ph_crdt_depleted = (u32) 3442221167Sgnn VXGE_HAL_MRPCIM_DEBUG_STATS1_GET_VPLANE_WRCRDTARB_PH_CRDT_DEPLETED( 3443221167Sgnn val64); 3444221167Sgnn 3445221167Sgnn val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 3446221167Sgnn hldev->header.regh0, 3447221167Sgnn &hldev->mrpcim_reg->mrpcim_debug_stats2_vplane[i]); 3448221167Sgnn 3449221167Sgnn mrpcim_stats->pic_wrcrdtarb_pd_crdt_depleted_vplane[i]. 3450221167Sgnn pic_wrcrdtarb_pd_crdt_depleted = (u32) 3451221167Sgnn VXGE_HAL_MRPCIM_DEBUG_STATS2_GET_VPLANE_WRCRDTARB_PD_CRDT_DEPLETED( 3452221167Sgnn val64); 3453221167Sgnn 3454221167Sgnn val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 3455221167Sgnn hldev->header.regh0, 3456221167Sgnn &hldev->mrpcim_reg->mrpcim_debug_stats3_vplane[i]); 3457221167Sgnn 3458221167Sgnn mrpcim_stats->pic_rdcrdtarb_nph_crdt_depleted_vplane[i]. 3459221167Sgnn pic_rdcrdtarb_nph_crdt_depleted = (u32) 3460221167Sgnn VXGE_HAL_MRPCIM_DEBUG_STATS3_GET_VPLANE_RDCRDTARB_NPH_CRDT_DEPLETED( 3461221167Sgnn val64); 3462221167Sgnn } 3463221167Sgnn 3464221167Sgnn val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 3465221167Sgnn hldev->header.regh0, 3466221167Sgnn &hldev->mrpcim_reg->mrpcim_debug_stats4); 3467221167Sgnn 3468221167Sgnn mrpcim_stats->pic_ini_rd_vpin_drop = 3469221167Sgnn (u32) VXGE_HAL_MRPCIM_DEBUG_STATS4_GET_INI_RD_VPIN_DROP(val64); 3470221167Sgnn 3471221167Sgnn mrpcim_stats->pic_ini_wr_vpin_drop = 3472221167Sgnn (u32) VXGE_HAL_MRPCIM_DEBUG_STATS4_GET_INI_WR_VPIN_DROP(val64); 3473221167Sgnn 3474221167Sgnn val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 3475221167Sgnn hldev->header.regh0, 3476221167Sgnn &hldev->mrpcim_reg->genstats_count01); 3477221167Sgnn 3478221167Sgnn mrpcim_stats->pic_genstats_count0 = 3479221167Sgnn (u32) VXGE_HAL_GENSTATS_COUNT01_GET_GENSTATS_COUNT0(val64); 3480221167Sgnn 3481221167Sgnn mrpcim_stats->pic_genstats_count1 = 3482221167Sgnn (u32) VXGE_HAL_GENSTATS_COUNT01_GET_GENSTATS_COUNT1(val64); 3483221167Sgnn 3484221167Sgnn val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 3485221167Sgnn hldev->header.regh0, 3486221167Sgnn &hldev->mrpcim_reg->genstats_count23); 3487221167Sgnn 3488221167Sgnn mrpcim_stats->pic_genstats_count2 = 3489221167Sgnn (u32) VXGE_HAL_GENSTATS_COUNT23_GET_GENSTATS_COUNT2(val64); 3490221167Sgnn 3491221167Sgnn mrpcim_stats->pic_genstats_count3 = 3492221167Sgnn (u32) VXGE_HAL_GENSTATS_COUNT23_GET_GENSTATS_COUNT3(val64); 3493221167Sgnn 3494221167Sgnn val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 3495221167Sgnn hldev->header.regh0, 3496221167Sgnn &hldev->mrpcim_reg->genstats_count4); 3497221167Sgnn 3498221167Sgnn mrpcim_stats->pic_genstats_count4 = 3499221167Sgnn (u32) VXGE_HAL_GENSTATS_COUNT4_GET_GENSTATS_COUNT4(val64); 3500221167Sgnn 3501221167Sgnn val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 3502221167Sgnn hldev->header.regh0, 3503221167Sgnn &hldev->mrpcim_reg->genstats_count5); 3504221167Sgnn 3505221167Sgnn mrpcim_stats->pic_genstats_count5 = 3506221167Sgnn (u32) VXGE_HAL_GENSTATS_COUNT5_GET_GENSTATS_COUNT5(val64); 3507221167Sgnn 3508221167Sgnn val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 3509221167Sgnn hldev->header.regh0, 3510221167Sgnn &hldev->mrpcim_reg->debug_stats0); 3511221167Sgnn 3512221167Sgnn mrpcim_stats->pci_rstdrop_cpl = 3513221167Sgnn (u32) VXGE_HAL_DEBUG_STATS0_GET_RSTDROP_CPL(val64); 3514221167Sgnn 3515221167Sgnn mrpcim_stats->pci_rstdrop_msg = 3516221167Sgnn (u32) VXGE_HAL_DEBUG_STATS0_GET_RSTDROP_MSG(val64); 3517221167Sgnn 3518221167Sgnn val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 3519221167Sgnn hldev->header.regh0, 3520221167Sgnn &hldev->mrpcim_reg->debug_stats1); 3521221167Sgnn 3522221167Sgnn mrpcim_stats->pci_rstdrop_client0 = 3523221167Sgnn (u32) VXGE_HAL_DEBUG_STATS1_GET_RSTDROP_CLIENT0(val64); 3524221167Sgnn 3525221167Sgnn mrpcim_stats->pci_rstdrop_client1 = 3526221167Sgnn (u32) VXGE_HAL_DEBUG_STATS1_GET_RSTDROP_CLIENT1(val64); 3527221167Sgnn 3528221167Sgnn val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 3529221167Sgnn hldev->header.regh0, 3530221167Sgnn &hldev->mrpcim_reg->debug_stats2); 3531221167Sgnn 3532221167Sgnn mrpcim_stats->pci_rstdrop_client2 = 3533221167Sgnn (u32) VXGE_HAL_DEBUG_STATS2_GET_RSTDROP_CLIENT2(val64); 3534221167Sgnn 3535221167Sgnn for (i = 0; i < VXGE_HAL_MAX_VIRTUAL_PATHS; i++) { 3536221167Sgnn val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 3537221167Sgnn hldev->header.regh0, 3538221167Sgnn &hldev->mrpcim_reg->debug_stats3_vplane); 3539221167Sgnn 3540221167Sgnn mrpcim_stats->pci_depl_h_vplane[i].pci_depl_cplh = 3541221167Sgnn (u16) VXGE_HAL_DEBUG_STATS3_GET_VPLANE_DEPL_CPLH(val64); 3542221167Sgnn 3543221167Sgnn mrpcim_stats->pci_depl_h_vplane[i].pci_depl_nph = 3544221167Sgnn (u16) VXGE_HAL_DEBUG_STATS3_GET_VPLANE_DEPL_NPH(val64); 3545221167Sgnn 3546221167Sgnn mrpcim_stats->pci_depl_h_vplane[i].pci_depl_ph = 3547221167Sgnn (u16) VXGE_HAL_DEBUG_STATS3_GET_VPLANE_DEPL_PH(val64); 3548221167Sgnn 3549221167Sgnn val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 3550221167Sgnn hldev->header.regh0, 3551221167Sgnn &hldev->mrpcim_reg->debug_stats4_vplane); 3552221167Sgnn 3553221167Sgnn mrpcim_stats->pci_depl_d_vplane[i].pci_depl_cpld = 3554221167Sgnn (u16) VXGE_HAL_DEBUG_STATS4_GET_VPLANE_DEPL_CPLD(val64); 3555221167Sgnn 3556221167Sgnn mrpcim_stats->pci_depl_d_vplane[i].pci_depl_npd = 3557221167Sgnn (u16) VXGE_HAL_DEBUG_STATS4_GET_VPLANE_DEPL_NPD(val64); 3558221167Sgnn 3559221167Sgnn mrpcim_stats->pci_depl_d_vplane[i].pci_depl_pd = 3560221167Sgnn (u16) VXGE_HAL_DEBUG_STATS4_GET_VPLANE_DEPL_PD(val64); 3561221167Sgnn } 3562221167Sgnn 3563221167Sgnn status = vxge_hal_mrpcim_xmac_aggr_stats_get(hldev, 3564221167Sgnn 0, 3565221167Sgnn &mrpcim_stats->xgmac_aggr[0]); 3566221167Sgnn 3567221167Sgnn if (status != VXGE_HAL_OK) { 3568221167Sgnn vxge_hal_trace_log_stats("<== %s:%s:%d Result = %d", 3569221167Sgnn __FILE__, __func__, __LINE__, status); 3570221167Sgnn return (status); 3571221167Sgnn } 3572221167Sgnn 3573221167Sgnn status = vxge_hal_mrpcim_xmac_aggr_stats_get(hldev, 3574221167Sgnn 1, 3575221167Sgnn &mrpcim_stats->xgmac_aggr[1]); 3576221167Sgnn 3577221167Sgnn if (status != VXGE_HAL_OK) { 3578221167Sgnn vxge_hal_trace_log_stats("<== %s:%s:%d Result = %d", 3579221167Sgnn __FILE__, __func__, __LINE__, status); 3580221167Sgnn return (status); 3581221167Sgnn } 3582221167Sgnn 3583221167Sgnn for (i = 0; i < VXGE_HAL_MAC_MAX_PORTS; i++) { 3584221167Sgnn 3585221167Sgnn status = vxge_hal_mrpcim_xmac_port_stats_get(hldev, 3586221167Sgnn i, 3587221167Sgnn &mrpcim_stats->xgmac_port[i]); 3588221167Sgnn 3589221167Sgnn if (status != VXGE_HAL_OK) { 3590221167Sgnn vxge_hal_trace_log_stats("<== %s:%s:%d Result = %d", 3591221167Sgnn __FILE__, __func__, __LINE__, status); 3592221167Sgnn return (status); 3593221167Sgnn } 3594221167Sgnn 3595221167Sgnn } 3596221167Sgnn 3597221167Sgnn VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_AGGR, 3598221167Sgnn VXGE_HAL_STATS_GLOBAL_PROG_EVENT_GNUM0_OFFSET); 3599221167Sgnn 3600221167Sgnn mrpcim_stats->xgmac_global_prog_event_gnum0 = 3601221167Sgnn VXGE_HAL_STATS_GET_GLOBAL_PROG_EVENT_GNUM0(val64); 3602221167Sgnn 3603221167Sgnn VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_AGGR, 3604221167Sgnn VXGE_HAL_STATS_GLOBAL_PROG_EVENT_GNUM1_OFFSET); 3605221167Sgnn 3606221167Sgnn mrpcim_stats->xgmac_global_prog_event_gnum1 = 3607221167Sgnn VXGE_HAL_STATS_GET_GLOBAL_PROG_EVENT_GNUM1(val64); 3608221167Sgnn 3609221167Sgnn val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 3610221167Sgnn hldev->header.regh0, 3611221167Sgnn &hldev->mrpcim_reg->orp_lro_events); 3612221167Sgnn 3613221167Sgnn mrpcim_stats->xgmac_orp_lro_events = 3614221167Sgnn VXGE_HAL_ORP_LRO_EVENTS_GET_ORP_LRO_EVENTS(val64); 3615221167Sgnn 3616221167Sgnn val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 3617221167Sgnn hldev->header.regh0, 3618221167Sgnn &hldev->mrpcim_reg->orp_bs_events); 3619221167Sgnn 3620221167Sgnn mrpcim_stats->xgmac_orp_bs_events = 3621221167Sgnn VXGE_HAL_ORP_BS_EVENTS_GET_ORP_BS_EVENTS(val64); 3622221167Sgnn 3623221167Sgnn val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 3624221167Sgnn hldev->header.regh0, 3625221167Sgnn &hldev->mrpcim_reg->orp_iwarp_events); 3626221167Sgnn 3627221167Sgnn mrpcim_stats->xgmac_orp_iwarp_events = 3628221167Sgnn VXGE_HAL_ORP_IWARP_EVENTS_GET_ORP_IWARP_EVENTS(val64); 3629221167Sgnn 3630221167Sgnn val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 3631221167Sgnn hldev->header.regh0, 3632221167Sgnn &hldev->mrpcim_reg->dbg_stats_tpa_tx_path); 3633221167Sgnn 3634221167Sgnn mrpcim_stats->xgmac_tx_permitted_frms = 3635221167Sgnn (u32) VXGE_HAL_DBG_STATS_TPA_TX_PATH_GET_TX_PERMITTED_FRMS(val64); 3636221167Sgnn 3637221167Sgnn val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 3638221167Sgnn hldev->header.regh0, 3639221167Sgnn &hldev->mrpcim_reg->dbg_stat_tx_any_frms); 3640221167Sgnn 3641221167Sgnn mrpcim_stats->xgmac_port0_tx_any_frms = 3642221167Sgnn (u8) VXGE_HAL_DBG_STAT_TX_ANY_FRMS_GET_PORT0_TX_ANY_FRMS(val64); 3643221167Sgnn 3644221167Sgnn mrpcim_stats->xgmac_port1_tx_any_frms = 3645221167Sgnn (u8) VXGE_HAL_DBG_STAT_TX_ANY_FRMS_GET_PORT1_TX_ANY_FRMS(val64); 3646221167Sgnn 3647221167Sgnn mrpcim_stats->xgmac_port2_tx_any_frms = 3648221167Sgnn (u8) VXGE_HAL_DBG_STAT_TX_ANY_FRMS_GET_PORT2_TX_ANY_FRMS(val64); 3649221167Sgnn 3650221167Sgnn val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 3651221167Sgnn hldev->header.regh0, 3652221167Sgnn &hldev->mrpcim_reg->dbg_stat_rx_any_frms); 3653221167Sgnn 3654221167Sgnn mrpcim_stats->xgmac_port0_rx_any_frms = 3655221167Sgnn (u8) VXGE_HAL_DBG_STAT_RX_ANY_FRMS_GET_PORT0_RX_ANY_FRMS(val64); 3656221167Sgnn 3657221167Sgnn mrpcim_stats->xgmac_port1_rx_any_frms = 3658221167Sgnn (u8) VXGE_HAL_DBG_STAT_RX_ANY_FRMS_GET_PORT1_RX_ANY_FRMS(val64); 3659221167Sgnn 3660221167Sgnn mrpcim_stats->xgmac_port2_rx_any_frms = 3661221167Sgnn (u8) VXGE_HAL_DBG_STAT_RX_ANY_FRMS_GET_PORT2_RX_ANY_FRMS(val64); 3662221167Sgnn 3663221167Sgnn vxge_hal_trace_log_stats("<== %s:%s:%d Result = %d", 3664221167Sgnn __FILE__, __func__, __LINE__, status); 3665221167Sgnn return (status); 3666221167Sgnn} 3667221167Sgnn 3668221167Sgnn/* 3669221167Sgnn * vxge_hal_mrpcim_stats_clear - Clear the statistics of the device 3670221167Sgnn * @devh: HAL Device handle. 3671221167Sgnn * 3672221167Sgnn * Clear the statistics of the given Device. 3673221167Sgnn * 3674221167Sgnn */ 3675221167Sgnnvxge_hal_status_e 3676221167Sgnnvxge_hal_mrpcim_stats_clear(vxge_hal_device_h devh) 3677221167Sgnn{ 3678221167Sgnn u32 i; 3679221167Sgnn u64 stat; 3680221167Sgnn vxge_hal_status_e status; 3681221167Sgnn __hal_device_t *hldev = (__hal_device_t *) devh; 3682221167Sgnn 3683221167Sgnn vxge_assert(hldev != NULL); 3684221167Sgnn 3685221167Sgnn vxge_hal_trace_log_stats("==> %s:%s:%d", 3686221167Sgnn __FILE__, __func__, __LINE__); 3687221167Sgnn 3688221167Sgnn vxge_hal_trace_log_stats("devh = 0x"VXGE_OS_STXFMT, 3689221167Sgnn (ptr_t) devh); 3690221167Sgnn 3691221167Sgnn if (!(hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM)) { 3692221167Sgnn vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = %d", 3693221167Sgnn __FILE__, __func__, __LINE__, 3694221167Sgnn VXGE_HAL_ERR_PRIVILAGED_OPEARATION); 3695221167Sgnn 3696221167Sgnn return (VXGE_HAL_ERR_PRIVILAGED_OPEARATION); 3697221167Sgnn } 3698221167Sgnn 3699221167Sgnn vxge_os_memcpy(&hldev->mrpcim->mrpcim_stats_sav, 3700221167Sgnn hldev->mrpcim->mrpcim_stats, 3701221167Sgnn sizeof(vxge_hal_mrpcim_stats_hw_info_t)); 3702221167Sgnn 3703221167Sgnn vxge_os_memzero(hldev->mrpcim->mrpcim_stats, 3704221167Sgnn sizeof(vxge_hal_mrpcim_stats_hw_info_t)); 3705221167Sgnn 3706221167Sgnn vxge_os_memzero(&hldev->stats.sw_dev_err_stats, 3707221167Sgnn sizeof(vxge_hal_device_stats_sw_err_t)); 3708221167Sgnn 3709221167Sgnn hldev->stats.sw_dev_info_stats.soft_reset_cnt = 0; 3710221167Sgnn 3711221167Sgnn for (i = 0; i < VXGE_HAL_MAX_VIRTUAL_PATHS; i++) { 3712221167Sgnn 3713221167Sgnn if (!(hldev->vpaths_deployed & mBIT(i))) 3714221167Sgnn continue; 3715221167Sgnn 3716221167Sgnn (void) vxge_hal_vpath_stats_clear( 3717221167Sgnn VXGE_HAL_VIRTUAL_PATH_HANDLE(&hldev->virtual_paths[i])); 3718221167Sgnn 3719221167Sgnn } 3720221167Sgnn 3721221167Sgnn status = vxge_hal_mrpcim_stats_access( 3722221167Sgnn devh, 3723221167Sgnn VXGE_HAL_STATS_OP_CLEAR_ALL_STATS, 3724221167Sgnn 0, 3725221167Sgnn 0, 3726221167Sgnn &stat); 3727221167Sgnn 3728221167Sgnn vxge_hal_trace_log_stats("<== %s:%s:%d Result = %d", 3729221167Sgnn __FILE__, __func__, __LINE__, status); 3730221167Sgnn 3731221167Sgnn return (status); 3732221167Sgnn} 3733221167Sgnn 3734221167Sgnn/* 3735221167Sgnn * vxge_hal_mrpcim_udp_rth_enable - Enable UDP/RTH. 3736221167Sgnn * @devh: HAL device handle. 3737221167Sgnn * 3738221167Sgnn * enable udp rth 3739221167Sgnn * 3740221167Sgnn */ 3741221167Sgnnvxge_hal_status_e 3742221167Sgnnvxge_hal_mrpcim_udp_rth_enable( 3743221167Sgnn vxge_hal_device_h devh) 3744221167Sgnn{ 3745221167Sgnn vxge_hal_status_e status = VXGE_HAL_OK; 3746221167Sgnn __hal_device_t *hldev = (__hal_device_t *) devh; 3747221167Sgnn 3748221167Sgnn vxge_assert(devh != NULL); 3749221167Sgnn 3750221167Sgnn vxge_hal_trace_log_stats("==> %s:%s:%d", 3751221167Sgnn __FILE__, __func__, __LINE__); 3752221167Sgnn 3753221167Sgnn vxge_hal_trace_log_stats("devh = 0x"VXGE_OS_STXFMT, 3754221167Sgnn (ptr_t) devh); 3755221167Sgnn 3756221167Sgnn if (!(hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM)) { 3757221167Sgnn 3758221167Sgnn vxge_hal_trace_log_stats("<== %s:%s:%d Result: %d", 3759221167Sgnn __FILE__, __func__, __LINE__, 3760221167Sgnn VXGE_HAL_ERR_PRIVILAGED_OPEARATION); 3761221167Sgnn return (VXGE_HAL_ERR_PRIVILAGED_OPEARATION); 3762221167Sgnn 3763221167Sgnn } 3764221167Sgnn 3765221167Sgnn status = __hal_vpath_udp_rth_set(hldev, 3766221167Sgnn hldev->first_vp_id, 3767221167Sgnn TRUE); 3768221167Sgnn 3769221167Sgnn vxge_hal_trace_log_stats("<== %s:%s:%d Result = %d", 3770221167Sgnn __FILE__, __func__, __LINE__, status); 3771221167Sgnn return (status); 3772221167Sgnn} 3773221167Sgnn 3774221167Sgnn/* 3775221167Sgnn * __hal_mrpcim_mac_configure - Initialize mac 3776221167Sgnn * @hldev: hal device. 3777221167Sgnn * 3778221167Sgnn * Initializes mac 3779221167Sgnn * 3780221167Sgnn */ 3781221167Sgnnvxge_hal_status_e 3782221167Sgnn__hal_mrpcim_mac_configure(__hal_device_t *hldev) 3783221167Sgnn{ 3784221167Sgnn u64 val64; 3785221167Sgnn u32 i, port_id; 3786221167Sgnn vxge_hal_status_e status = VXGE_HAL_OK; 3787221167Sgnn vxge_hal_mac_config_t *mac_config = 3788221167Sgnn &hldev->header.config.mrpcim_config.mac_config; 3789221167Sgnn 3790221167Sgnn vxge_assert(hldev != NULL); 3791221167Sgnn 3792221167Sgnn vxge_hal_trace_log_mrpcim("==> %s:%s:%d", 3793221167Sgnn __FILE__, __func__, __LINE__); 3794221167Sgnn 3795221167Sgnn vxge_hal_trace_log_mrpcim("hldev = 0x"VXGE_OS_STXFMT, 3796221167Sgnn (ptr_t) hldev); 3797221167Sgnn 3798221167Sgnn for (i = 0; i < VXGE_HAL_MAC_MAX_WIRE_PORTS; i++) { 3799221167Sgnn 3800221167Sgnn port_id = mac_config->wire_port_config[i].port_id; 3801221167Sgnn 3802221167Sgnn if (mac_config->wire_port_config[i].tmac_en == 3803221167Sgnn VXGE_HAL_WIRE_PORT_TMAC_DEFAULT) { 3804221167Sgnn val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 3805221167Sgnn hldev->header.regh0, 3806221167Sgnn &hldev->mrpcim_reg->txmac_cfg0_port[port_id]); 3807221167Sgnn 3808221167Sgnn if (val64 & VXGE_HAL_TXMAC_CFG0_PORT_TMAC_EN) { 3809221167Sgnn mac_config->wire_port_config[i].tmac_en = 3810221167Sgnn VXGE_HAL_WIRE_PORT_TMAC_ENABLE; 3811221167Sgnn } else { 3812221167Sgnn mac_config->wire_port_config[i].tmac_en = 3813221167Sgnn VXGE_HAL_WIRE_PORT_TMAC_DISABLE; 3814221167Sgnn } 3815221167Sgnn 3816221167Sgnn } 3817221167Sgnn 3818221167Sgnn if (mac_config->wire_port_config[i].rmac_en == 3819221167Sgnn VXGE_HAL_WIRE_PORT_RMAC_DEFAULT) { 3820221167Sgnn val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 3821221167Sgnn hldev->header.regh0, 3822221167Sgnn &hldev->mrpcim_reg->rxmac_cfg0_port[port_id]); 3823221167Sgnn 3824221167Sgnn if (val64 & VXGE_HAL_RXMAC_CFG0_PORT_RMAC_EN) { 3825221167Sgnn mac_config->wire_port_config[i].rmac_en = 3826221167Sgnn VXGE_HAL_WIRE_PORT_RMAC_ENABLE; 3827221167Sgnn } else { 3828221167Sgnn mac_config->wire_port_config[i].rmac_en = 3829221167Sgnn VXGE_HAL_WIRE_PORT_RMAC_DISABLE; 3830221167Sgnn } 3831221167Sgnn 3832221167Sgnn } 3833221167Sgnn 3834221167Sgnn if ((!(mac_config->wire_port_config[i].rmac_en)) && 3835221167Sgnn (!(mac_config->wire_port_config[i].tmac_en))) 3836221167Sgnn val64 = 0; 3837221167Sgnn else 3838221167Sgnn val64 = VXGE_HAL_XGMAC_MAIN_CFG_PORT_PORT_EN; 3839221167Sgnn 3840221167Sgnn vxge_os_pio_mem_write64(hldev->header.pdev, 3841221167Sgnn hldev->header.regh0, 3842221167Sgnn val64, 3843221167Sgnn &hldev->mrpcim_reg->xgmac_main_cfg_port[port_id]); 3844221167Sgnn 3845221167Sgnn if (!val64) 3846221167Sgnn continue; 3847221167Sgnn 3848221167Sgnn val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 3849221167Sgnn hldev->header.regh0, 3850221167Sgnn &hldev->mrpcim_reg->rxmac_cfg0_port[port_id]); 3851221167Sgnn 3852221167Sgnn if (mac_config->wire_port_config[i].rmac_en) 3853221167Sgnn val64 |= VXGE_HAL_RXMAC_CFG0_PORT_RMAC_EN; 3854221167Sgnn else 3855221167Sgnn val64 &= ~VXGE_HAL_RXMAC_CFG0_PORT_RMAC_EN; 3856221167Sgnn 3857221167Sgnn if (mac_config->wire_port_config[i].rmac_strip_fcs != 3858221167Sgnn VXGE_HAL_WIRE_PORT_RMAC_STRIP_FCS_DEFAULT) { 3859221167Sgnn if (mac_config->wire_port_config[i].rmac_strip_fcs) 3860221167Sgnn val64 |= VXGE_HAL_RXMAC_CFG0_PORT_STRIP_FCS; 3861221167Sgnn else 3862221167Sgnn val64 &= ~VXGE_HAL_RXMAC_CFG0_PORT_STRIP_FCS; 3863221167Sgnn } 3864221167Sgnn 3865221167Sgnn if (mac_config->wire_port_config[i].rmac_discard_pfrm != 3866221167Sgnn VXGE_HAL_WIRE_PORT_RMAC_DISCARD_PFRM_DEFAULT) { 3867221167Sgnn if (mac_config->wire_port_config[i].rmac_discard_pfrm) 3868221167Sgnn val64 |= VXGE_HAL_RXMAC_CFG0_PORT_DISCARD_PFRM; 3869221167Sgnn else 3870221167Sgnn val64 &= ~VXGE_HAL_RXMAC_CFG0_PORT_DISCARD_PFRM; 3871221167Sgnn } 3872221167Sgnn 3873221167Sgnn if (mac_config->wire_port_config[i].mtu != 3874221167Sgnn VXGE_HAL_WIRE_PORT_DEF_INITIAL_MTU) { 3875221167Sgnn 3876221167Sgnn val64 &= 3877221167Sgnn ~VXGE_HAL_RXMAC_CFG0_PORT_MAX_PYLD_LEN(0x3fff); 3878221167Sgnn 3879221167Sgnn val64 |= VXGE_HAL_RXMAC_CFG0_PORT_MAX_PYLD_LEN( 3880221167Sgnn mac_config->wire_port_config[i].mtu); 3881221167Sgnn 3882221167Sgnn } 3883221167Sgnn 3884221167Sgnn vxge_os_pio_mem_write64(hldev->header.pdev, 3885221167Sgnn hldev->header.regh0, 3886221167Sgnn val64, 3887221167Sgnn &hldev->mrpcim_reg->rxmac_cfg0_port[port_id]); 3888221167Sgnn 3889221167Sgnn val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 3890221167Sgnn hldev->header.regh0, 3891221167Sgnn &hldev->mrpcim_reg->rxmac_cfg2_port[port_id]); 3892221167Sgnn 3893221167Sgnn if (mac_config->wire_port_config[i].rmac_prom_en != 3894221167Sgnn VXGE_HAL_WIRE_PORT_RMAC_PROM_EN_DEFAULT) { 3895221167Sgnn if (mac_config->wire_port_config[i].rmac_prom_en) 3896221167Sgnn val64 |= VXGE_HAL_RXMAC_CFG2_PORT_PROM_EN; 3897221167Sgnn else 3898221167Sgnn val64 &= ~VXGE_HAL_RXMAC_CFG2_PORT_PROM_EN; 3899221167Sgnn } 3900221167Sgnn 3901221167Sgnn vxge_os_pio_mem_write64(hldev->header.pdev, 3902221167Sgnn hldev->header.regh0, 3903221167Sgnn val64, 3904221167Sgnn &hldev->mrpcim_reg->rxmac_cfg2_port[port_id]); 3905221167Sgnn 3906221167Sgnn val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 3907221167Sgnn hldev->header.regh0, 3908221167Sgnn &hldev->mrpcim_reg->rxmac_pause_cfg_port[port_id]); 3909221167Sgnn 3910221167Sgnn if (mac_config->wire_port_config[i].rmac_pause_gen_en != 3911221167Sgnn VXGE_HAL_WIRE_PORT_RMAC_PAUSE_GEN_EN_DEFAULT) { 3912221167Sgnn if (mac_config->wire_port_config[i].rmac_pause_gen_en) 3913221167Sgnn val64 |= VXGE_HAL_RXMAC_PAUSE_CFG_PORT_GEN_EN; 3914221167Sgnn else 3915221167Sgnn val64 &= ~VXGE_HAL_RXMAC_PAUSE_CFG_PORT_GEN_EN; 3916221167Sgnn 3917221167Sgnn } 3918221167Sgnn 3919221167Sgnn if (mac_config->wire_port_config[i].rmac_pause_rcv_en != 3920221167Sgnn VXGE_HAL_WIRE_PORT_RMAC_PAUSE_RCV_EN_DEFAULT) { 3921221167Sgnn if (mac_config->wire_port_config[i].rmac_pause_rcv_en) 3922221167Sgnn val64 |= VXGE_HAL_RXMAC_PAUSE_CFG_PORT_RCV_EN; 3923221167Sgnn else 3924221167Sgnn val64 &= ~VXGE_HAL_RXMAC_PAUSE_CFG_PORT_RCV_EN; 3925221167Sgnn 3926221167Sgnn } 3927221167Sgnn 3928221167Sgnn if (mac_config->wire_port_config[i].rmac_pause_time != 3929221167Sgnn VXGE_HAL_WIRE_PORT_DEF_RMAC_HIGH_PTIME) { 3930221167Sgnn val64 &= 3931221167Sgnn ~VXGE_HAL_RXMAC_PAUSE_CFG_PORT_HIGH_PTIME(0xffff); 3932221167Sgnn 3933221167Sgnn val64 |= VXGE_HAL_RXMAC_PAUSE_CFG_PORT_HIGH_PTIME( 3934221167Sgnn mac_config->wire_port_config[i].rmac_pause_time); 3935221167Sgnn 3936221167Sgnn } 3937221167Sgnn 3938221167Sgnn if (mac_config->wire_port_config[i].rmac_pause_time != 3939221167Sgnn VXGE_HAL_WIRE_PORT_RMAC_PAUSE_LIMITER_DEFAULT) { 3940221167Sgnn if (mac_config->wire_port_config[i].limiter_en) 3941221167Sgnn val64 |= 3942221167Sgnn VXGE_HAL_RXMAC_PAUSE_CFG_PORT_LIMITER_EN; 3943221167Sgnn else 3944221167Sgnn val64 &= 3945221167Sgnn ~VXGE_HAL_RXMAC_PAUSE_CFG_PORT_LIMITER_EN; 3946221167Sgnn 3947221167Sgnn } 3948221167Sgnn 3949221167Sgnn if (mac_config->wire_port_config[i].max_limit != 3950221167Sgnn VXGE_HAL_WIRE_PORT_DEF_RMAC_MAX_LIMIT) { 3951221167Sgnn val64 &= ~VXGE_HAL_RXMAC_PAUSE_CFG_PORT_MAX_LIMIT(0xff); 3952221167Sgnn 3953221167Sgnn val64 |= VXGE_HAL_RXMAC_PAUSE_CFG_PORT_MAX_LIMIT( 3954221167Sgnn mac_config->wire_port_config[i].max_limit); 3955221167Sgnn 3956221167Sgnn } 3957221167Sgnn 3958221167Sgnn vxge_os_pio_mem_write64(hldev->header.pdev, 3959221167Sgnn hldev->header.regh0, 3960221167Sgnn val64, 3961221167Sgnn &hldev->mrpcim_reg->rxmac_pause_cfg_port[port_id]); 3962221167Sgnn 3963221167Sgnn val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 3964221167Sgnn hldev->header.regh0, 3965221167Sgnn &hldev->mrpcim_reg->rxmac_link_util_port[port_id]); 3966221167Sgnn 3967221167Sgnn if (mac_config->wire_port_config[i].rmac_util_period != 3968221167Sgnn VXGE_HAL_WIRE_PORT_DEF_TMAC_UTIL_PERIOD) { 3969221167Sgnn val64 &= 3970221167Sgnn ~VXGE_HAL_RXMAC_LINK_UTIL_PORT_RMAC_UTIL_CFG(0xf); 3971221167Sgnn 3972221167Sgnn val64 |= VXGE_HAL_RXMAC_LINK_UTIL_PORT_RMAC_UTIL_CFG( 3973221167Sgnn mac_config->wire_port_config[i].rmac_util_period); 3974221167Sgnn } 3975221167Sgnn 3976221167Sgnn vxge_os_pio_mem_write64(hldev->header.pdev, 3977221167Sgnn hldev->header.regh0, 3978221167Sgnn val64, 3979221167Sgnn &hldev->mrpcim_reg->rxmac_link_util_port[port_id]); 3980221167Sgnn 3981221167Sgnn val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 3982221167Sgnn hldev->header.regh0, 3983221167Sgnn &hldev->mrpcim_reg->xgmac_debounce_port[port_id]); 3984221167Sgnn 3985221167Sgnn if (mac_config->wire_port_config[i].link_stability_period != 3986221167Sgnn VXGE_HAL_WIRE_PORT_DEF_LINK_STABILITY_PERIOD) { 3987221167Sgnn val64 &= 3988221167Sgnn ~(VXGE_HAL_XGMAC_DEBOUNCE_PORT_PERIOD_LINK_UP(0xf) | 3989221167Sgnn VXGE_HAL_XGMAC_DEBOUNCE_PORT_PERIOD_LINK_DOWN(0xf)); 3990221167Sgnn 3991221167Sgnn val64 |= VXGE_HAL_XGMAC_DEBOUNCE_PORT_PERIOD_LINK_UP( 3992221167Sgnn mac_config->wire_port_config[i].link_stability_period) | 3993221167Sgnn VXGE_HAL_XGMAC_DEBOUNCE_PORT_PERIOD_LINK_DOWN( 3994221167Sgnn mac_config->wire_port_config[i].link_stability_period); 3995221167Sgnn } 3996221167Sgnn 3997221167Sgnn if (mac_config->wire_port_config[i].port_stability_period != 3998221167Sgnn VXGE_HAL_WIRE_PORT_DEF_PORT_STABILITY_PERIOD) { 3999221167Sgnn val64 &= 4000221167Sgnn ~(VXGE_HAL_XGMAC_DEBOUNCE_PORT_PERIOD_PORT_UP(0xf) | 4001221167Sgnn VXGE_HAL_XGMAC_DEBOUNCE_PORT_PERIOD_PORT_DOWN(0xf)); 4002221167Sgnn 4003221167Sgnn val64 |= VXGE_HAL_XGMAC_DEBOUNCE_PORT_PERIOD_PORT_UP( 4004221167Sgnn mac_config->wire_port_config[i].port_stability_period) | 4005221167Sgnn VXGE_HAL_XGMAC_DEBOUNCE_PORT_PERIOD_PORT_DOWN( 4006221167Sgnn mac_config->wire_port_config[i].port_stability_period); 4007221167Sgnn } 4008221167Sgnn 4009221167Sgnn vxge_os_pio_mem_write64(hldev->header.pdev, 4010221167Sgnn hldev->header.regh0, 4011221167Sgnn val64, 4012221167Sgnn &hldev->mrpcim_reg->xgmac_debounce_port[port_id]); 4013221167Sgnn 4014221167Sgnn val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 4015221167Sgnn hldev->header.regh0, 4016221167Sgnn &hldev->mrpcim_reg->txmac_cfg0_port[port_id]); 4017221167Sgnn 4018221167Sgnn if (mac_config->wire_port_config[i].tmac_en) 4019221167Sgnn val64 |= VXGE_HAL_TXMAC_CFG0_PORT_TMAC_EN; 4020221167Sgnn else 4021221167Sgnn val64 &= ~VXGE_HAL_TXMAC_CFG0_PORT_TMAC_EN; 4022221167Sgnn 4023221167Sgnn if (mac_config->wire_port_config[i].tmac_pad != 4024221167Sgnn VXGE_HAL_WIRE_PORT_TMAC_PAD_DEFAULT) { 4025221167Sgnn if (mac_config->wire_port_config[i].tmac_pad) 4026221167Sgnn val64 |= VXGE_HAL_TXMAC_CFG0_PORT_APPEND_PAD; 4027221167Sgnn else 4028221167Sgnn val64 &= ~VXGE_HAL_TXMAC_CFG0_PORT_APPEND_PAD; 4029221167Sgnn } 4030221167Sgnn 4031221167Sgnn if (mac_config->wire_port_config[i].tmac_pad_byte != 4032221167Sgnn VXGE_HAL_WIRE_PORT_TMAC_PAD_DEFAULT) { 4033221167Sgnn val64 &= ~VXGE_HAL_TXMAC_CFG0_PORT_PAD_BYTE(0xff); 4034221167Sgnn 4035221167Sgnn val64 |= VXGE_HAL_TXMAC_CFG0_PORT_PAD_BYTE( 4036221167Sgnn mac_config->wire_port_config[i].tmac_pad_byte); 4037221167Sgnn } 4038221167Sgnn 4039221167Sgnn vxge_os_pio_mem_write64(hldev->header.pdev, 4040221167Sgnn hldev->header.regh0, 4041221167Sgnn val64, 4042221167Sgnn &hldev->mrpcim_reg->txmac_cfg0_port[port_id]); 4043221167Sgnn 4044221167Sgnn val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 4045221167Sgnn hldev->header.regh0, 4046221167Sgnn &hldev->mrpcim_reg->txmac_link_util_port); 4047221167Sgnn 4048221167Sgnn if (mac_config->wire_port_config[i].tmac_util_period != 4049221167Sgnn VXGE_HAL_WIRE_PORT_DEF_TMAC_UTIL_PERIOD) { 4050221167Sgnn val64 &= 4051221167Sgnn ~VXGE_HAL_TXMAC_LINK_UTIL_PORT_TMAC_UTIL_CFG(0xf); 4052221167Sgnn 4053221167Sgnn val64 |= VXGE_HAL_TXMAC_LINK_UTIL_PORT_TMAC_UTIL_CFG( 4054221167Sgnn mac_config->wire_port_config[i].tmac_util_period); 4055221167Sgnn } 4056221167Sgnn 4057221167Sgnn vxge_os_pio_mem_write64(hldev->header.pdev, 4058221167Sgnn hldev->header.regh0, 4059221167Sgnn val64, 4060221167Sgnn &hldev->mrpcim_reg->txmac_link_util_port[port_id]); 4061221167Sgnn 4062221167Sgnn val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 4063221167Sgnn hldev->header.regh0, 4064221167Sgnn &hldev->mrpcim_reg->ratemgmt_cfg_port); 4065221167Sgnn 4066221167Sgnn if (mac_config->wire_port_config[i].autoneg_mode != 4067221167Sgnn VXGE_HAL_WIRE_PORT_AUTONEG_MODE_DEFAULT) { 4068221167Sgnn 4069221167Sgnn val64 &= ~VXGE_HAL_RATEMGMT_CFG_PORT_MODE(0x3); 4070221167Sgnn 4071221167Sgnn val64 |= VXGE_HAL_RATEMGMT_CFG_PORT_MODE( 4072221167Sgnn mac_config->wire_port_config[i].autoneg_mode); 4073221167Sgnn } 4074221167Sgnn 4075221167Sgnn if (mac_config->wire_port_config[i].autoneg_rate != 4076221167Sgnn VXGE_HAL_WIRE_PORT_AUTONEG_RATE_DEFAULT) { 4077221167Sgnn 4078221167Sgnn if (mac_config->wire_port_config[i].autoneg_rate) 4079221167Sgnn val64 |= VXGE_HAL_RATEMGMT_CFG_PORT_RATE; 4080221167Sgnn else 4081221167Sgnn val64 &= ~VXGE_HAL_RATEMGMT_CFG_PORT_RATE; 4082221167Sgnn 4083221167Sgnn } 4084221167Sgnn 4085221167Sgnn if (mac_config->wire_port_config[i].fixed_use_fsm != 4086221167Sgnn VXGE_HAL_WIRE_PORT_FIXED_USE_FSM_DEFAULT) { 4087221167Sgnn 4088221167Sgnn if (mac_config->wire_port_config[i].fixed_use_fsm) 4089221167Sgnn val64 |= 4090221167Sgnn VXGE_HAL_RATEMGMT_CFG_PORT_FIXED_USE_FSM; 4091221167Sgnn else 4092221167Sgnn val64 &= 4093221167Sgnn ~VXGE_HAL_RATEMGMT_CFG_PORT_FIXED_USE_FSM; 4094221167Sgnn 4095221167Sgnn } 4096221167Sgnn 4097221167Sgnn if (mac_config->wire_port_config[i].antp_use_fsm != 4098221167Sgnn VXGE_HAL_WIRE_PORT_ANTP_USE_FSM_DEFAULT) { 4099221167Sgnn 4100221167Sgnn if (mac_config->wire_port_config[i].antp_use_fsm) 4101221167Sgnn val64 |= 4102221167Sgnn VXGE_HAL_RATEMGMT_CFG_PORT_ANTP_USE_FSM; 4103221167Sgnn else 4104221167Sgnn val64 &= 4105221167Sgnn ~VXGE_HAL_RATEMGMT_CFG_PORT_ANTP_USE_FSM; 4106221167Sgnn 4107221167Sgnn } 4108221167Sgnn 4109221167Sgnn if (mac_config->wire_port_config[i].anbe_use_fsm != 4110221167Sgnn VXGE_HAL_WIRE_PORT_ANBE_USE_FSM_DEFAULT) { 4111221167Sgnn 4112221167Sgnn if (mac_config->wire_port_config[i].anbe_use_fsm) 4113221167Sgnn val64 |= 4114221167Sgnn VXGE_HAL_RATEMGMT_CFG_PORT_ANBE_USE_FSM; 4115221167Sgnn else 4116221167Sgnn val64 &= 4117221167Sgnn ~VXGE_HAL_RATEMGMT_CFG_PORT_ANBE_USE_FSM; 4118221167Sgnn 4119221167Sgnn } 4120221167Sgnn 4121221167Sgnn vxge_os_pio_mem_write64(hldev->header.pdev, 4122221167Sgnn hldev->header.regh0, 4123221167Sgnn val64, 4124221167Sgnn &hldev->mrpcim_reg->ratemgmt_cfg_port[port_id]); 4125221167Sgnn 4126221167Sgnn } 4127221167Sgnn 4128221167Sgnn if (mac_config->switch_port_config.tmac_en == 4129221167Sgnn VXGE_HAL_SWITCH_PORT_TMAC_DEFAULT) { 4130221167Sgnn val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 4131221167Sgnn hldev->header.regh0, 4132221167Sgnn &hldev->mrpcim_reg->txmac_cfg0_port[ 4133221167Sgnn VXGE_HAL_MAC_SWITCH_PORT]); 4134221167Sgnn 4135221167Sgnn if (val64 & VXGE_HAL_TXMAC_CFG0_PORT_TMAC_EN) { 4136221167Sgnn mac_config->switch_port_config.tmac_en = 4137221167Sgnn VXGE_HAL_SWITCH_PORT_TMAC_ENABLE; 4138221167Sgnn } else { 4139221167Sgnn mac_config->switch_port_config.tmac_en = 4140221167Sgnn VXGE_HAL_SWITCH_PORT_TMAC_DISABLE; 4141221167Sgnn } 4142221167Sgnn 4143221167Sgnn } 4144221167Sgnn 4145221167Sgnn if (mac_config->switch_port_config.rmac_en == 4146221167Sgnn VXGE_HAL_SWITCH_PORT_RMAC_DEFAULT) { 4147221167Sgnn val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 4148221167Sgnn hldev->header.regh0, 4149221167Sgnn &hldev->mrpcim_reg->rxmac_cfg0_port[ 4150221167Sgnn VXGE_HAL_MAC_SWITCH_PORT]); 4151221167Sgnn 4152221167Sgnn if (val64 & VXGE_HAL_RXMAC_CFG0_PORT_RMAC_EN) { 4153221167Sgnn mac_config->switch_port_config.rmac_en = 4154221167Sgnn VXGE_HAL_SWITCH_PORT_RMAC_ENABLE; 4155221167Sgnn } else { 4156221167Sgnn mac_config->switch_port_config.rmac_en = 4157221167Sgnn VXGE_HAL_SWITCH_PORT_RMAC_DISABLE; 4158221167Sgnn } 4159221167Sgnn 4160221167Sgnn } 4161221167Sgnn 4162221167Sgnn if (mac_config->switch_port_config.rmac_en || 4163221167Sgnn mac_config->switch_port_config.tmac_en) { 4164221167Sgnn 4165221167Sgnn val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 4166221167Sgnn hldev->header.regh0, 4167221167Sgnn &hldev->mrpcim_reg->rxmac_cfg0_port[ 4168221167Sgnn VXGE_HAL_MAC_SWITCH_PORT]); 4169221167Sgnn 4170221167Sgnn if (mac_config->switch_port_config.rmac_en) 4171221167Sgnn val64 |= VXGE_HAL_RXMAC_CFG0_PORT_RMAC_EN; 4172221167Sgnn else 4173221167Sgnn val64 &= ~VXGE_HAL_RXMAC_CFG0_PORT_RMAC_EN; 4174221167Sgnn 4175221167Sgnn if (mac_config->switch_port_config.rmac_strip_fcs != 4176221167Sgnn VXGE_HAL_SWITCH_PORT_RMAC_STRIP_FCS_DEFAULT) { 4177221167Sgnn if (mac_config->switch_port_config.rmac_strip_fcs) 4178221167Sgnn val64 |= VXGE_HAL_RXMAC_CFG0_PORT_STRIP_FCS; 4179221167Sgnn else 4180221167Sgnn val64 &= ~VXGE_HAL_RXMAC_CFG0_PORT_STRIP_FCS; 4181221167Sgnn } 4182221167Sgnn 4183221167Sgnn if (mac_config->switch_port_config.rmac_discard_pfrm != 4184221167Sgnn VXGE_HAL_SWITCH_PORT_RMAC_DISCARD_PFRM_DEFAULT) { 4185221167Sgnn if (mac_config->switch_port_config.rmac_discard_pfrm) 4186221167Sgnn val64 |= VXGE_HAL_RXMAC_CFG0_PORT_DISCARD_PFRM; 4187221167Sgnn else 4188221167Sgnn val64 &= ~VXGE_HAL_RXMAC_CFG0_PORT_DISCARD_PFRM; 4189221167Sgnn } 4190221167Sgnn 4191221167Sgnn if (mac_config->switch_port_config.mtu != 4192221167Sgnn VXGE_HAL_SWITCH_PORT_DEF_INITIAL_MTU) { 4193221167Sgnn 4194221167Sgnn val64 &= ~VXGE_HAL_RXMAC_CFG0_PORT_MAX_PYLD_LEN(0x3fff); 4195221167Sgnn 4196221167Sgnn val64 |= VXGE_HAL_RXMAC_CFG0_PORT_MAX_PYLD_LEN( 4197221167Sgnn mac_config->switch_port_config.mtu); 4198221167Sgnn 4199221167Sgnn } 4200221167Sgnn 4201221167Sgnn vxge_os_pio_mem_write64(hldev->header.pdev, 4202221167Sgnn hldev->header.regh0, 4203221167Sgnn val64, 4204221167Sgnn &hldev->mrpcim_reg->rxmac_cfg0_port[ 4205221167Sgnn VXGE_HAL_MAC_SWITCH_PORT]); 4206221167Sgnn 4207221167Sgnn val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 4208221167Sgnn hldev->header.regh0, 4209221167Sgnn &hldev->mrpcim_reg->rxmac_cfg2_port[ 4210221167Sgnn VXGE_HAL_MAC_SWITCH_PORT]); 4211221167Sgnn 4212221167Sgnn if (mac_config->switch_port_config.rmac_prom_en != 4213221167Sgnn VXGE_HAL_SWITCH_PORT_RMAC_PROM_EN_DEFAULT) { 4214221167Sgnn if (mac_config->switch_port_config.rmac_prom_en) 4215221167Sgnn val64 |= VXGE_HAL_RXMAC_CFG2_PORT_PROM_EN; 4216221167Sgnn else 4217221167Sgnn val64 &= ~VXGE_HAL_RXMAC_CFG2_PORT_PROM_EN; 4218221167Sgnn } 4219221167Sgnn 4220221167Sgnn vxge_os_pio_mem_write64(hldev->header.pdev, 4221221167Sgnn hldev->header.regh0, 4222221167Sgnn val64, 4223221167Sgnn &hldev->mrpcim_reg->rxmac_cfg2_port[ 4224221167Sgnn VXGE_HAL_MAC_SWITCH_PORT]); 4225221167Sgnn 4226221167Sgnn val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 4227221167Sgnn hldev->header.regh0, 4228221167Sgnn &hldev->mrpcim_reg->rxmac_pause_cfg_port[ 4229221167Sgnn VXGE_HAL_MAC_SWITCH_PORT]); 4230221167Sgnn 4231221167Sgnn if (mac_config->switch_port_config.rmac_pause_gen_en != 4232221167Sgnn VXGE_HAL_SWITCH_PORT_RMAC_PAUSE_GEN_EN_DEFAULT) { 4233221167Sgnn if (mac_config->switch_port_config.rmac_pause_gen_en) 4234221167Sgnn val64 |= VXGE_HAL_RXMAC_PAUSE_CFG_PORT_GEN_EN; 4235221167Sgnn else 4236221167Sgnn val64 &= ~VXGE_HAL_RXMAC_PAUSE_CFG_PORT_GEN_EN; 4237221167Sgnn 4238221167Sgnn } 4239221167Sgnn 4240221167Sgnn if (mac_config->switch_port_config.rmac_pause_rcv_en != 4241221167Sgnn VXGE_HAL_SWITCH_PORT_RMAC_PAUSE_RCV_EN_DEFAULT) { 4242221167Sgnn if (mac_config->switch_port_config.rmac_pause_rcv_en) 4243221167Sgnn val64 |= VXGE_HAL_RXMAC_PAUSE_CFG_PORT_RCV_EN; 4244221167Sgnn else 4245221167Sgnn val64 &= ~VXGE_HAL_RXMAC_PAUSE_CFG_PORT_RCV_EN; 4246221167Sgnn 4247221167Sgnn } 4248221167Sgnn 4249221167Sgnn if (mac_config->switch_port_config.rmac_pause_time != 4250221167Sgnn VXGE_HAL_SWITCH_PORT_DEF_RMAC_HIGH_PTIME) { 4251221167Sgnn val64 &= 4252221167Sgnn ~VXGE_HAL_RXMAC_PAUSE_CFG_PORT_HIGH_PTIME(0xffff); 4253221167Sgnn 4254221167Sgnn val64 |= VXGE_HAL_RXMAC_PAUSE_CFG_PORT_HIGH_PTIME( 4255221167Sgnn mac_config->switch_port_config.rmac_pause_time); 4256221167Sgnn 4257221167Sgnn } 4258221167Sgnn 4259221167Sgnn if (mac_config->switch_port_config.rmac_pause_time != 4260221167Sgnn VXGE_HAL_SWITCH_PORT_RMAC_PAUSE_LIMITER_DEFAULT) { 4261221167Sgnn if (mac_config->switch_port_config.limiter_en) 4262221167Sgnn val64 |= 4263221167Sgnn VXGE_HAL_RXMAC_PAUSE_CFG_PORT_LIMITER_EN; 4264221167Sgnn else 4265221167Sgnn val64 &= 4266221167Sgnn ~VXGE_HAL_RXMAC_PAUSE_CFG_PORT_LIMITER_EN; 4267221167Sgnn 4268221167Sgnn } 4269221167Sgnn 4270221167Sgnn if (mac_config->switch_port_config.max_limit != 4271221167Sgnn VXGE_HAL_SWITCH_PORT_DEF_RMAC_MAX_LIMIT) { 4272221167Sgnn val64 &= ~VXGE_HAL_RXMAC_PAUSE_CFG_PORT_MAX_LIMIT(0xff); 4273221167Sgnn 4274221167Sgnn val64 |= VXGE_HAL_RXMAC_PAUSE_CFG_PORT_MAX_LIMIT( 4275221167Sgnn mac_config->switch_port_config.max_limit); 4276221167Sgnn 4277221167Sgnn } 4278221167Sgnn 4279221167Sgnn vxge_os_pio_mem_write64(hldev->header.pdev, 4280221167Sgnn hldev->header.regh0, 4281221167Sgnn val64, 4282221167Sgnn &hldev->mrpcim_reg->rxmac_pause_cfg_port[ 4283221167Sgnn VXGE_HAL_MAC_SWITCH_PORT]); 4284221167Sgnn 4285221167Sgnn val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 4286221167Sgnn hldev->header.regh0, 4287221167Sgnn &hldev->mrpcim_reg->rxmac_link_util_port[ 4288221167Sgnn VXGE_HAL_MAC_SWITCH_PORT]); 4289221167Sgnn 4290221167Sgnn if (mac_config->switch_port_config.rmac_util_period != 4291221167Sgnn VXGE_HAL_SWITCH_PORT_DEF_TMAC_UTIL_PERIOD) { 4292221167Sgnn val64 &= 4293221167Sgnn ~VXGE_HAL_RXMAC_LINK_UTIL_PORT_RMAC_UTIL_CFG(0xf); 4294221167Sgnn 4295221167Sgnn val64 |= VXGE_HAL_RXMAC_LINK_UTIL_PORT_RMAC_UTIL_CFG( 4296221167Sgnn mac_config->switch_port_config.rmac_util_period); 4297221167Sgnn } 4298221167Sgnn 4299221167Sgnn vxge_os_pio_mem_write64(hldev->header.pdev, 4300221167Sgnn hldev->header.regh0, 4301221167Sgnn val64, 4302221167Sgnn &hldev->mrpcim_reg->rxmac_link_util_port[ 4303221167Sgnn VXGE_HAL_MAC_SWITCH_PORT]); 4304221167Sgnn 4305221167Sgnn val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 4306221167Sgnn hldev->header.regh0, 4307221167Sgnn &hldev->mrpcim_reg->txmac_cfg0_port[ 4308221167Sgnn VXGE_HAL_MAC_SWITCH_PORT]); 4309221167Sgnn 4310221167Sgnn if (mac_config->switch_port_config.tmac_en) 4311221167Sgnn val64 |= VXGE_HAL_TXMAC_CFG0_PORT_TMAC_EN; 4312221167Sgnn else 4313221167Sgnn val64 &= ~VXGE_HAL_TXMAC_CFG0_PORT_TMAC_EN; 4314221167Sgnn 4315221167Sgnn if (mac_config->switch_port_config.tmac_pad != 4316221167Sgnn VXGE_HAL_SWITCH_PORT_TMAC_PAD_DEFAULT) { 4317221167Sgnn if (mac_config->switch_port_config.tmac_pad) 4318221167Sgnn val64 |= VXGE_HAL_TXMAC_CFG0_PORT_APPEND_PAD; 4319221167Sgnn else 4320221167Sgnn val64 &= ~VXGE_HAL_TXMAC_CFG0_PORT_APPEND_PAD; 4321221167Sgnn } 4322221167Sgnn 4323221167Sgnn if (mac_config->switch_port_config.tmac_pad_byte != 4324221167Sgnn VXGE_HAL_SWITCH_PORT_TMAC_PAD_DEFAULT) { 4325221167Sgnn val64 &= ~VXGE_HAL_TXMAC_CFG0_PORT_PAD_BYTE(0xff); 4326221167Sgnn 4327221167Sgnn val64 |= VXGE_HAL_TXMAC_CFG0_PORT_PAD_BYTE( 4328221167Sgnn mac_config->switch_port_config.tmac_pad_byte); 4329221167Sgnn } 4330221167Sgnn 4331221167Sgnn vxge_os_pio_mem_write64(hldev->header.pdev, 4332221167Sgnn hldev->header.regh0, 4333221167Sgnn val64, 4334221167Sgnn &hldev->mrpcim_reg->txmac_cfg0_port[ 4335221167Sgnn VXGE_HAL_MAC_SWITCH_PORT]); 4336221167Sgnn 4337221167Sgnn val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 4338221167Sgnn hldev->header.regh0, 4339221167Sgnn &hldev->mrpcim_reg->txmac_link_util_port); 4340221167Sgnn 4341221167Sgnn if (mac_config->switch_port_config.tmac_util_period != 4342221167Sgnn VXGE_HAL_SWITCH_PORT_DEF_TMAC_UTIL_PERIOD) { 4343221167Sgnn val64 &= 4344221167Sgnn ~VXGE_HAL_TXMAC_LINK_UTIL_PORT_TMAC_UTIL_CFG(0xf); 4345221167Sgnn 4346221167Sgnn val64 |= VXGE_HAL_TXMAC_LINK_UTIL_PORT_TMAC_UTIL_CFG( 4347221167Sgnn mac_config->switch_port_config.tmac_util_period); 4348221167Sgnn } 4349221167Sgnn 4350221167Sgnn vxge_os_pio_mem_write64(hldev->header.pdev, 4351221167Sgnn hldev->header.regh0, 4352221167Sgnn val64, 4353221167Sgnn &hldev->mrpcim_reg->txmac_link_util_port[ 4354221167Sgnn VXGE_HAL_MAC_SWITCH_PORT]); 4355221167Sgnn 4356221167Sgnn } 4357221167Sgnn 4358221167Sgnn val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 4359221167Sgnn hldev->header.regh0, 4360221167Sgnn &hldev->mrpcim_reg->txmac_gen_cfg1); 4361221167Sgnn 4362221167Sgnn if (mac_config->tmac_perma_stop_en != 4363221167Sgnn VXGE_HAL_MAC_TMAC_PERMA_STOP_DEFAULT) { 4364221167Sgnn 4365221167Sgnn if (mac_config->tmac_perma_stop_en) 4366221167Sgnn val64 |= VXGE_HAL_TXMAC_GEN_CFG1_TMAC_PERMA_STOP_EN; 4367221167Sgnn else 4368221167Sgnn val64 &= ~VXGE_HAL_TXMAC_GEN_CFG1_TMAC_PERMA_STOP_EN; 4369221167Sgnn 4370221167Sgnn } 4371221167Sgnn 4372221167Sgnn if (mac_config->tmac_tx_switch_dis != 4373221167Sgnn VXGE_HAL_MAC_TMAC_TX_SWITCH_DEFAULT) { 4374221167Sgnn 4375221167Sgnn if (mac_config->tmac_tx_switch_dis) 4376221167Sgnn val64 |= VXGE_HAL_TXMAC_GEN_CFG1_TX_SWITCH_DISABLE; 4377221167Sgnn else 4378221167Sgnn val64 &= ~VXGE_HAL_TXMAC_GEN_CFG1_TX_SWITCH_DISABLE; 4379221167Sgnn 4380221167Sgnn } 4381221167Sgnn 4382221167Sgnn if (mac_config->tmac_lossy_switch_en != 4383221167Sgnn VXGE_HAL_MAC_TMAC_LOSSY_SWITCH_DEFAULT) { 4384221167Sgnn 4385221167Sgnn if (mac_config->tmac_lossy_switch_en) 4386221167Sgnn val64 |= VXGE_HAL_TXMAC_GEN_CFG1_LOSSY_SWITCH; 4387221167Sgnn else 4388221167Sgnn val64 &= ~VXGE_HAL_TXMAC_GEN_CFG1_LOSSY_SWITCH; 4389221167Sgnn 4390221167Sgnn } 4391221167Sgnn 4392221167Sgnn if (mac_config->tmac_lossy_switch_en != 4393221167Sgnn VXGE_HAL_MAC_TMAC_LOSSY_WIRE_DEFAULT) { 4394221167Sgnn 4395221167Sgnn if (mac_config->tmac_lossy_wire_en) 4396221167Sgnn val64 |= VXGE_HAL_TXMAC_GEN_CFG1_LOSSY_WIRE; 4397221167Sgnn else 4398221167Sgnn val64 &= ~VXGE_HAL_TXMAC_GEN_CFG1_LOSSY_WIRE; 4399221167Sgnn 4400221167Sgnn } 4401221167Sgnn 4402221167Sgnn if (mac_config->tmac_bcast_to_wire_dis != 4403221167Sgnn VXGE_HAL_MAC_TMAC_BCAST_TO_WIRE_DEFAULT) { 4404221167Sgnn 4405221167Sgnn if (mac_config->tmac_bcast_to_wire_dis) 4406221167Sgnn val64 |= VXGE_HAL_TXMAC_GEN_CFG1_BLOCK_BCAST_TO_WIRE; 4407221167Sgnn else 4408221167Sgnn val64 &= ~VXGE_HAL_TXMAC_GEN_CFG1_BLOCK_BCAST_TO_WIRE; 4409221167Sgnn 4410221167Sgnn } 4411221167Sgnn 4412221167Sgnn if (mac_config->tmac_bcast_to_wire_dis != 4413221167Sgnn VXGE_HAL_MAC_TMAC_BCAST_TO_SWITCH_DEFAULT) { 4414221167Sgnn 4415221167Sgnn if (mac_config->tmac_bcast_to_switch_dis) 4416221167Sgnn val64 |= VXGE_HAL_TXMAC_GEN_CFG1_BLOCK_BCAST_TO_SWITCH; 4417221167Sgnn else 4418221167Sgnn val64 &= ~VXGE_HAL_TXMAC_GEN_CFG1_BLOCK_BCAST_TO_SWITCH; 4419221167Sgnn 4420221167Sgnn } 4421221167Sgnn 4422221167Sgnn if (mac_config->tmac_host_append_fcs_en != 4423221167Sgnn VXGE_HAL_MAC_TMAC_HOST_APPEND_FCS_DEFAULT) { 4424221167Sgnn 4425221167Sgnn if (mac_config->tmac_host_append_fcs_en) 4426221167Sgnn val64 |= VXGE_HAL_TXMAC_GEN_CFG1_HOST_APPEND_FCS; 4427221167Sgnn else 4428221167Sgnn val64 &= ~VXGE_HAL_TXMAC_GEN_CFG1_HOST_APPEND_FCS; 4429221167Sgnn 4430221167Sgnn } 4431221167Sgnn 4432221167Sgnn vxge_os_pio_mem_write64(hldev->header.pdev, 4433221167Sgnn hldev->header.regh0, 4434221167Sgnn val64, 4435221167Sgnn &hldev->mrpcim_reg->txmac_gen_cfg1); 4436221167Sgnn 4437221167Sgnn val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 4438221167Sgnn hldev->header.regh0, 4439221167Sgnn &hldev->mrpcim_reg->rxmac_rx_pa_cfg0); 4440221167Sgnn 4441221167Sgnn if (mac_config->rpa_ignore_frame_err != 4442221167Sgnn VXGE_HAL_MAC_RPA_IGNORE_FRAME_ERR_DEFAULT) { 4443221167Sgnn 4444221167Sgnn if (mac_config->rpa_ignore_frame_err) 4445221167Sgnn val64 |= VXGE_HAL_RXMAC_RX_PA_CFG0_IGNORE_FRAME_ERR; 4446221167Sgnn else 4447221167Sgnn val64 &= ~VXGE_HAL_RXMAC_RX_PA_CFG0_IGNORE_FRAME_ERR; 4448221167Sgnn 4449221167Sgnn } 4450221167Sgnn 4451221167Sgnn if (mac_config->rpa_support_snap_ab_n != 4452221167Sgnn VXGE_HAL_MAC_RPA_SUPPORT_SNAP_AB_N_DEFAULT) { 4453221167Sgnn 4454221167Sgnn if (mac_config->rpa_support_snap_ab_n) 4455221167Sgnn val64 |= VXGE_HAL_RXMAC_RX_PA_CFG0_SUPPORT_SNAP_AB_N; 4456221167Sgnn else 4457221167Sgnn val64 &= ~VXGE_HAL_RXMAC_RX_PA_CFG0_SUPPORT_SNAP_AB_N; 4458221167Sgnn 4459221167Sgnn } 4460221167Sgnn 4461221167Sgnn if (mac_config->rpa_search_for_hao != 4462221167Sgnn VXGE_HAL_MAC_RPA_SEARCH_FOR_HAO_DEFAULT) { 4463221167Sgnn 4464221167Sgnn if (mac_config->rpa_search_for_hao) 4465221167Sgnn val64 |= VXGE_HAL_RXMAC_RX_PA_CFG0_SEARCH_FOR_HAO; 4466221167Sgnn else 4467221167Sgnn val64 &= ~VXGE_HAL_RXMAC_RX_PA_CFG0_SEARCH_FOR_HAO; 4468221167Sgnn 4469221167Sgnn } 4470221167Sgnn 4471221167Sgnn if (mac_config->rpa_support_ipv6_mobile_hdrs != 4472221167Sgnn VXGE_HAL_MAC_RPA_SUPPORT_IPV6_MOBILE_HDRS_DEFAULT) { 4473221167Sgnn 4474221167Sgnn if (mac_config->rpa_support_ipv6_mobile_hdrs) 4475221167Sgnn val64 |= 4476221167Sgnn VXGE_HAL_RXMAC_RX_PA_CFG0_SUPPORT_MOBILE_IPV6_HDRS; 4477221167Sgnn else 4478221167Sgnn val64 &= 4479221167Sgnn ~VXGE_HAL_RXMAC_RX_PA_CFG0_SUPPORT_MOBILE_IPV6_HDRS; 4480221167Sgnn 4481221167Sgnn } 4482221167Sgnn 4483221167Sgnn if (mac_config->rpa_ipv6_stop_searching != 4484221167Sgnn VXGE_HAL_MAC_RPA_IPV6_STOP_SEARCHING_DEFAULT) { 4485221167Sgnn 4486221167Sgnn if (mac_config->rpa_ipv6_stop_searching) 4487221167Sgnn val64 |= VXGE_HAL_RXMAC_RX_PA_CFG0_IPV6_STOP_SEARCHING; 4488221167Sgnn else 4489221167Sgnn val64 &= ~VXGE_HAL_RXMAC_RX_PA_CFG0_IPV6_STOP_SEARCHING; 4490221167Sgnn 4491221167Sgnn } 4492221167Sgnn 4493221167Sgnn if (mac_config->rpa_no_ps_if_unknown != 4494221167Sgnn VXGE_HAL_MAC_RPA_NO_PS_IF_UNKNOWN_DEFAULT) { 4495221167Sgnn 4496221167Sgnn if (mac_config->rpa_no_ps_if_unknown) 4497221167Sgnn val64 |= VXGE_HAL_RXMAC_RX_PA_CFG0_NO_PS_IF_UNKNOWN; 4498221167Sgnn else 4499221167Sgnn val64 &= ~VXGE_HAL_RXMAC_RX_PA_CFG0_NO_PS_IF_UNKNOWN; 4500221167Sgnn 4501221167Sgnn } 4502221167Sgnn 4503221167Sgnn if (mac_config->rpa_search_for_etype != 4504221167Sgnn VXGE_HAL_MAC_RPA_SEARCH_FOR_ETYPE_DEFAULT) { 4505221167Sgnn 4506221167Sgnn if (mac_config->rpa_search_for_etype) 4507221167Sgnn val64 |= VXGE_HAL_RXMAC_RX_PA_CFG0_SEARCH_FOR_ETYPE; 4508221167Sgnn else 4509221167Sgnn val64 &= ~VXGE_HAL_RXMAC_RX_PA_CFG0_SEARCH_FOR_ETYPE; 4510221167Sgnn 4511221167Sgnn } 4512221167Sgnn 4513221167Sgnn vxge_os_pio_mem_write64(hldev->header.pdev, 4514221167Sgnn hldev->header.regh0, 4515221167Sgnn val64, 4516221167Sgnn &hldev->mrpcim_reg->rxmac_rx_pa_cfg0); 4517221167Sgnn 4518221167Sgnn val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 4519221167Sgnn hldev->header.regh0, 4520221167Sgnn &hldev->mrpcim_reg->fau_pa_cfg); 4521221167Sgnn 4522221167Sgnn if (mac_config->rpa_repl_l4_comp_csum != 4523221167Sgnn VXGE_HAL_MAC_RPA_REPL_l4_COMP_CSUM_DEFAULT) { 4524221167Sgnn 4525221167Sgnn if (mac_config->rpa_repl_l4_comp_csum) 4526221167Sgnn val64 |= VXGE_HAL_FAU_PA_CFG_REPL_L4_COMP_CSUM; 4527221167Sgnn else 4528221167Sgnn val64 &= ~VXGE_HAL_FAU_PA_CFG_REPL_L4_COMP_CSUM; 4529221167Sgnn 4530221167Sgnn } 4531221167Sgnn 4532221167Sgnn if (mac_config->rpa_repl_l3_incl_cf != 4533221167Sgnn VXGE_HAL_MAC_RPA_REPL_L3_INCL_CF_DEFAULT) { 4534221167Sgnn 4535221167Sgnn if (mac_config->rpa_repl_l3_incl_cf) 4536221167Sgnn val64 |= VXGE_HAL_FAU_PA_CFG_REPL_L3_INCL_CF; 4537221167Sgnn else 4538221167Sgnn val64 &= ~VXGE_HAL_FAU_PA_CFG_REPL_L3_INCL_CF; 4539221167Sgnn 4540221167Sgnn } 4541221167Sgnn 4542221167Sgnn if (mac_config->rpa_repl_l3_comp_csum != 4543221167Sgnn VXGE_HAL_MAC_RPA_REPL_l3_COMP_CSUM_DEFAULT) { 4544221167Sgnn 4545221167Sgnn if (mac_config->rpa_repl_l3_comp_csum) 4546221167Sgnn val64 |= VXGE_HAL_FAU_PA_CFG_REPL_L3_COMP_CSUM; 4547221167Sgnn else 4548221167Sgnn val64 &= ~VXGE_HAL_FAU_PA_CFG_REPL_L3_COMP_CSUM; 4549221167Sgnn 4550221167Sgnn } 4551221167Sgnn 4552221167Sgnn vxge_os_pio_mem_write64(hldev->header.pdev, 4553221167Sgnn hldev->header.regh0, 4554221167Sgnn val64, 4555221167Sgnn &hldev->mrpcim_reg->fau_pa_cfg); 4556221167Sgnn 4557221167Sgnn val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 4558221167Sgnn hldev->header.regh0, 4559221167Sgnn &hldev->mrpcim_reg->rxmac_rx_pa_cfg1); 4560221167Sgnn 4561221167Sgnn if (mac_config->rpa_repl_ipv4_tcp_incl_ph != 4562221167Sgnn VXGE_HAL_MAC_RPA_REPL_IPV4_TCP_INCL_PH_DEFAULT) { 4563221167Sgnn 4564221167Sgnn if (mac_config->rpa_repl_ipv4_tcp_incl_ph) 4565221167Sgnn val64 |= 4566221167Sgnn VXGE_HAL_RXMAC_RX_PA_CFG1_REPL_IPV4_TCP_INCL_PH; 4567221167Sgnn else 4568221167Sgnn val64 &= 4569221167Sgnn ~VXGE_HAL_RXMAC_RX_PA_CFG1_REPL_IPV4_TCP_INCL_PH; 4570221167Sgnn 4571221167Sgnn } 4572221167Sgnn 4573221167Sgnn if (mac_config->rpa_repl_ipv6_tcp_incl_ph != 4574221167Sgnn VXGE_HAL_MAC_RPA_REPL_IPV6_TCP_INCL_PH_DEFAULT) { 4575221167Sgnn 4576221167Sgnn if (mac_config->rpa_repl_ipv6_tcp_incl_ph) 4577221167Sgnn val64 |= 4578221167Sgnn VXGE_HAL_RXMAC_RX_PA_CFG1_REPL_IPV6_TCP_INCL_PH; 4579221167Sgnn else 4580221167Sgnn val64 &= 4581221167Sgnn ~VXGE_HAL_RXMAC_RX_PA_CFG1_REPL_IPV6_TCP_INCL_PH; 4582221167Sgnn 4583221167Sgnn } 4584221167Sgnn 4585221167Sgnn if (mac_config->rpa_repl_ipv4_udp_incl_ph != 4586221167Sgnn VXGE_HAL_MAC_RPA_REPL_IPV4_UDP_INCL_PH_DEFAULT) { 4587221167Sgnn 4588221167Sgnn if (mac_config->rpa_repl_ipv4_udp_incl_ph) 4589221167Sgnn val64 |= 4590221167Sgnn VXGE_HAL_RXMAC_RX_PA_CFG1_REPL_IPV4_UDP_INCL_PH; 4591221167Sgnn else 4592221167Sgnn val64 &= 4593221167Sgnn ~VXGE_HAL_RXMAC_RX_PA_CFG1_REPL_IPV4_UDP_INCL_PH; 4594221167Sgnn 4595221167Sgnn } 4596221167Sgnn 4597221167Sgnn if (mac_config->rpa_repl_ipv6_udp_incl_ph != 4598221167Sgnn VXGE_HAL_MAC_RPA_REPL_IPV6_UDP_INCL_PH_DEFAULT) { 4599221167Sgnn 4600221167Sgnn if (mac_config->rpa_repl_ipv6_udp_incl_ph) 4601221167Sgnn val64 |= 4602221167Sgnn VXGE_HAL_RXMAC_RX_PA_CFG1_REPL_IPV6_UDP_INCL_PH; 4603221167Sgnn else 4604221167Sgnn val64 &= 4605221167Sgnn ~VXGE_HAL_RXMAC_RX_PA_CFG1_REPL_IPV6_UDP_INCL_PH; 4606221167Sgnn 4607221167Sgnn } 4608221167Sgnn 4609221167Sgnn if (mac_config->rpa_repl_l4_incl_cf != 4610221167Sgnn VXGE_HAL_MAC_RPA_REPL_L4_INCL_CF_DEFAULT) { 4611221167Sgnn 4612221167Sgnn if (mac_config->rpa_repl_l4_incl_cf) 4613221167Sgnn val64 |= VXGE_HAL_RXMAC_RX_PA_CFG1_REPL_L4_INCL_CF; 4614221167Sgnn else 4615221167Sgnn val64 &= ~VXGE_HAL_RXMAC_RX_PA_CFG1_REPL_L4_INCL_CF; 4616221167Sgnn 4617221167Sgnn } 4618221167Sgnn 4619221167Sgnn if (mac_config->rpa_repl_strip_vlan_tag != 4620221167Sgnn VXGE_HAL_MAC_RPA_REPL_STRIP_VLAN_TAG_DEFAULT) { 4621221167Sgnn 4622221167Sgnn if (mac_config->rpa_repl_strip_vlan_tag) 4623221167Sgnn val64 |= VXGE_HAL_RXMAC_RX_PA_CFG1_REPL_STRIP_VLAN_TAG; 4624221167Sgnn else 4625221167Sgnn val64 &= ~VXGE_HAL_RXMAC_RX_PA_CFG1_REPL_STRIP_VLAN_TAG; 4626221167Sgnn 4627221167Sgnn 4628221167Sgnn } 4629221167Sgnn 4630221167Sgnn vxge_os_pio_mem_write64(hldev->header.pdev, 4631221167Sgnn hldev->header.regh0, 4632221167Sgnn val64, 4633221167Sgnn &hldev->mrpcim_reg->rxmac_rx_pa_cfg1); 4634221167Sgnn 4635221167Sgnn val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 4636221167Sgnn hldev->header.regh0, 4637221167Sgnn &hldev->mrpcim_reg->xmac_gen_cfg); 4638221167Sgnn 4639221167Sgnn if (mac_config->network_stability_period != 4640221167Sgnn VXGE_HAL_MAC_DEF_NETWORK_STABILITY_PERIOD) { 4641221167Sgnn 4642221167Sgnn val64 &= ~(VXGE_HAL_XMAC_GEN_CFG_PERIOD_NTWK_DOWN(0xf) | 4643221167Sgnn VXGE_HAL_XMAC_GEN_CFG_PERIOD_NTWK_UP(0xf)); 4644221167Sgnn 4645221167Sgnn val64 |= VXGE_HAL_XMAC_GEN_CFG_PERIOD_NTWK_DOWN( 4646221167Sgnn mac_config->network_stability_period) | 4647221167Sgnn VXGE_HAL_XMAC_GEN_CFG_PERIOD_NTWK_UP( 4648221167Sgnn mac_config->network_stability_period); 4649221167Sgnn 4650221167Sgnn } 4651221167Sgnn 4652221167Sgnn vxge_os_pio_mem_write64(hldev->header.pdev, 4653221167Sgnn hldev->header.regh0, 4654221167Sgnn val64, 4655221167Sgnn &hldev->mrpcim_reg->xmac_gen_cfg); 4656221167Sgnn 4657221167Sgnn val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 4658221167Sgnn hldev->header.regh0, 4659221167Sgnn &hldev->mrpcim_reg->tpa_global_cfg); 4660221167Sgnn 4661221167Sgnn if (mac_config->tpa_support_snap_ab_n != 4662221167Sgnn VXGE_HAL_MAC_TPA_SUPPORT_SNAP_AB_N_DEFAULT) { 4663221167Sgnn 4664221167Sgnn if (mac_config->tpa_support_snap_ab_n) 4665221167Sgnn val64 |= VXGE_HAL_TPA_GLOBAL_CFG_SUPPORT_SNAP_AB_N; 4666221167Sgnn else 4667221167Sgnn val64 &= ~VXGE_HAL_TPA_GLOBAL_CFG_SUPPORT_SNAP_AB_N; 4668221167Sgnn 4669221167Sgnn } 4670221167Sgnn 4671221167Sgnn if (mac_config->tpa_ecc_enable_n != 4672221167Sgnn VXGE_HAL_MAC_TPA_ECC_ENABLE_N_DEFAULT) { 4673221167Sgnn 4674221167Sgnn if (mac_config->tpa_ecc_enable_n) 4675221167Sgnn val64 |= VXGE_HAL_TPA_GLOBAL_CFG_ECC_ENABLE_N; 4676221167Sgnn else 4677221167Sgnn val64 &= ~VXGE_HAL_TPA_GLOBAL_CFG_ECC_ENABLE_N; 4678221167Sgnn 4679221167Sgnn } 4680221167Sgnn 4681221167Sgnn vxge_os_pio_mem_write64(hldev->header.pdev, 4682221167Sgnn hldev->header.regh0, 4683221167Sgnn val64, 4684221167Sgnn &hldev->mrpcim_reg->tpa_global_cfg); 4685221167Sgnn 4686221167Sgnn vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = %d", 4687221167Sgnn __FILE__, __func__, __LINE__, status); 4688221167Sgnn return (status); 4689221167Sgnn 4690221167Sgnn} 4691221167Sgnn 4692221167Sgnn/* 4693221167Sgnn * __hal_mrpcim_lag_configure - Initialize LAG registers 4694221167Sgnn * @hldev: hal device. 4695221167Sgnn * 4696221167Sgnn * Initializes LAG registers 4697221167Sgnn * 4698221167Sgnn */ 4699221167Sgnnvxge_hal_status_e 4700221167Sgnn__hal_mrpcim_lag_configure(__hal_device_t *hldev) 4701221167Sgnn{ 4702221167Sgnn u64 val64; 4703221167Sgnn u64 mac_addr; 4704221167Sgnn u32 i, j; 4705221167Sgnn vxge_hal_status_e status = VXGE_HAL_OK; 4706221167Sgnn vxge_hal_lag_config_t *lag_config = 4707221167Sgnn &hldev->header.config.mrpcim_config.lag_config; 4708221167Sgnn 4709221167Sgnn vxge_assert(hldev != NULL); 4710221167Sgnn 4711221167Sgnn vxge_hal_trace_log_mrpcim("==> %s:%s:%d", 4712221167Sgnn __FILE__, __func__, __LINE__); 4713221167Sgnn 4714221167Sgnn vxge_hal_trace_log_mrpcim("hldev = 0x"VXGE_OS_STXFMT, 4715221167Sgnn (ptr_t) hldev); 4716221167Sgnn 4717221167Sgnn 4718221167Sgnn val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 4719221167Sgnn hldev->header.regh0, 4720221167Sgnn &hldev->mrpcim_reg->lag_cfg); 4721221167Sgnn 4722221167Sgnn if (lag_config->lag_en == VXGE_HAL_LAG_LAG_EN_DEFAULT) { 4723221167Sgnn 4724221167Sgnn if (val64 & VXGE_HAL_LAG_CFG_EN) 4725221167Sgnn lag_config->lag_en = VXGE_HAL_LAG_LAG_EN_ENABLE; 4726221167Sgnn else 4727221167Sgnn lag_config->lag_en = VXGE_HAL_LAG_LAG_EN_DISABLE; 4728221167Sgnn 4729221167Sgnn } 4730221167Sgnn 4731221167Sgnn if (lag_config->lag_en == VXGE_HAL_LAG_LAG_EN_DISABLE) { 4732221167Sgnn 4733221167Sgnn if (val64 & VXGE_HAL_LAG_CFG_EN) { 4734221167Sgnn val64 &= ~VXGE_HAL_LAG_CFG_EN; 4735221167Sgnn vxge_os_pio_mem_write64(hldev->header.pdev, 4736221167Sgnn hldev->header.regh0, 4737221167Sgnn val64, 4738221167Sgnn &hldev->mrpcim_reg->lag_cfg); 4739221167Sgnn } 4740221167Sgnn 4741221167Sgnn vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = 0", 4742221167Sgnn __FILE__, __func__, __LINE__); 4743221167Sgnn 4744221167Sgnn return (VXGE_HAL_OK); 4745221167Sgnn 4746221167Sgnn } 4747221167Sgnn 4748221167Sgnn if (lag_config->lag_mode != VXGE_HAL_LAG_LAG_MODE_DEFAULT) { 4749221167Sgnn val64 &= ~VXGE_HAL_LAG_CFG_MODE(0x3); 4750221167Sgnn val64 |= VXGE_HAL_LAG_CFG_MODE(lag_config->lag_mode); 4751221167Sgnn } else { 4752221167Sgnn lag_config->lag_mode = (u32) VXGE_HAL_LAG_CFG_GET_MODE(val64); 4753221167Sgnn } 4754221167Sgnn 4755221167Sgnn if (lag_config->la_mode_config.tx_discard != 4756221167Sgnn VXGE_HAL_LAG_TX_DISCARD_DEFAULT) { 4757221167Sgnn if (lag_config->la_mode_config.tx_discard == 4758221167Sgnn VXGE_HAL_LAG_TX_DISCARD_ENABLE) 4759221167Sgnn val64 |= VXGE_HAL_LAG_CFG_TX_DISCARD_BEHAV; 4760221167Sgnn else 4761221167Sgnn val64 &= ~VXGE_HAL_LAG_CFG_TX_DISCARD_BEHAV; 4762221167Sgnn } 4763221167Sgnn 4764221167Sgnn if (lag_config->la_mode_config.rx_discard != 4765221167Sgnn VXGE_HAL_LAG_RX_DISCARD_DEFAULT) { 4766221167Sgnn if (lag_config->la_mode_config.rx_discard == 4767221167Sgnn VXGE_HAL_LAG_RX_DISCARD_ENABLE) 4768221167Sgnn val64 |= VXGE_HAL_LAG_CFG_RX_DISCARD_BEHAV; 4769221167Sgnn else 4770221167Sgnn val64 &= ~VXGE_HAL_LAG_CFG_RX_DISCARD_BEHAV; 4771221167Sgnn } 4772221167Sgnn 4773221167Sgnn if (lag_config->sl_mode_config.pref_indiv_port != 4774221167Sgnn VXGE_HAL_LAG_PREF_INDIV_PORT_DEFAULT) { 4775221167Sgnn if (lag_config->sl_mode_config.pref_indiv_port == 4776221167Sgnn VXGE_HAL_LAG_RX_DISCARD_ENABLE) 4777221167Sgnn val64 |= VXGE_HAL_LAG_CFG_PREF_INDIV_PORT_NUM; 4778221167Sgnn else 4779221167Sgnn val64 &= ~VXGE_HAL_LAG_CFG_PREF_INDIV_PORT_NUM; 4780221167Sgnn } 4781221167Sgnn 4782221167Sgnn vxge_os_pio_mem_write64(hldev->header.pdev, 4783221167Sgnn hldev->header.regh0, 4784221167Sgnn val64, 4785221167Sgnn &hldev->mrpcim_reg->lag_cfg); 4786221167Sgnn 4787221167Sgnn val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 4788221167Sgnn hldev->header.regh0, 4789221167Sgnn &hldev->mrpcim_reg->lag_tx_cfg); 4790221167Sgnn 4791221167Sgnn if (lag_config->incr_tx_aggr_stats != 4792221167Sgnn VXGE_HAL_LAG_INCR_TX_AGGR_STATS_DEFAULT) { 4793221167Sgnn if (lag_config->incr_tx_aggr_stats == 4794221167Sgnn VXGE_HAL_LAG_INCR_TX_AGGR_STATS_ENABLE) 4795221167Sgnn val64 |= VXGE_HAL_LAG_TX_CFG_INCR_TX_AGGR_STATS; 4796221167Sgnn else 4797221167Sgnn val64 &= ~VXGE_HAL_LAG_TX_CFG_INCR_TX_AGGR_STATS; 4798221167Sgnn } 4799221167Sgnn 4800221167Sgnn if (lag_config->la_mode_config.distrib_alg_sel != 4801221167Sgnn VXGE_HAL_LAG_DISTRIB_ALG_SEL_DEFAULT) { 4802221167Sgnn val64 &= ~VXGE_HAL_LAG_TX_CFG_DISTRIB_ALG_SEL(0x3); 4803221167Sgnn val64 |= VXGE_HAL_LAG_TX_CFG_DISTRIB_ALG_SEL( 4804221167Sgnn lag_config->la_mode_config.distrib_alg_sel); 4805221167Sgnn vxge_os_pio_mem_write64(hldev->header.pdev, 4806221167Sgnn hldev->header.regh0, 4807221167Sgnn lag_config->la_mode_config.distrib_dest, 4808221167Sgnn &hldev->mrpcim_reg->lag_distrib_dest); 4809221167Sgnn } else { 4810221167Sgnn lag_config->la_mode_config.distrib_alg_sel = 4811221167Sgnn (u32) VXGE_HAL_LAG_TX_CFG_GET_DISTRIB_ALG_SEL(val64); 4812221167Sgnn lag_config->la_mode_config.distrib_dest = 4813221167Sgnn vxge_os_pio_mem_read64(hldev->header.pdev, 4814221167Sgnn hldev->header.regh0, 4815221167Sgnn &hldev->mrpcim_reg->lag_distrib_dest); 4816221167Sgnn } 4817221167Sgnn 4818221167Sgnn if (lag_config->la_mode_config.distrib_remap_if_fail != 4819221167Sgnn VXGE_HAL_LAG_DISTRIB_REMAP_IF_FAIL_DEFAULT) { 4820221167Sgnn if (lag_config->la_mode_config.distrib_remap_if_fail == 4821221167Sgnn VXGE_HAL_LAG_DISTRIB_REMAP_IF_FAIL_ENABLE) 4822221167Sgnn val64 |= VXGE_HAL_LAG_TX_CFG_DISTRIB_REMAP_IF_FAIL; 4823221167Sgnn else 4824221167Sgnn val64 &= ~VXGE_HAL_LAG_TX_CFG_DISTRIB_REMAP_IF_FAIL; 4825221167Sgnn } 4826221167Sgnn 4827221167Sgnn if (lag_config->la_mode_config.coll_max_delay != 4828221167Sgnn VXGE_HAL_LAG_DEF_COLL_MAX_DELAY) { 4829221167Sgnn val64 &= ~VXGE_HAL_LAG_TX_CFG_COLL_MAX_DELAY(0xffff); 4830221167Sgnn val64 |= VXGE_HAL_LAG_TX_CFG_DISTRIB_ALG_SEL( 4831221167Sgnn lag_config->la_mode_config.coll_max_delay); 4832221167Sgnn } 4833221167Sgnn 4834221167Sgnn vxge_os_pio_mem_write64(hldev->header.pdev, 4835221167Sgnn hldev->header.regh0, 4836221167Sgnn val64, 4837221167Sgnn &hldev->mrpcim_reg->lag_tx_cfg); 4838221167Sgnn 4839221167Sgnn val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 4840221167Sgnn hldev->header.regh0, 4841221167Sgnn &hldev->mrpcim_reg->lag_active_passive_cfg); 4842221167Sgnn 4843221167Sgnn if (lag_config->ap_mode_config.hot_standby != 4844221167Sgnn VXGE_HAL_LAG_HOT_STANDBY_DEFAULT) { 4845221167Sgnn if (lag_config->ap_mode_config.hot_standby == 4846221167Sgnn VXGE_HAL_LAG_HOT_STANDBY_KEEP_UP_PORT) 4847221167Sgnn val64 |= VXGE_HAL_LAG_ACTIVE_PASSIVE_CFG_HOT_STANDBY; 4848221167Sgnn else 4849221167Sgnn val64 &= ~VXGE_HAL_LAG_ACTIVE_PASSIVE_CFG_HOT_STANDBY; 4850221167Sgnn } 4851221167Sgnn 4852221167Sgnn if (lag_config->ap_mode_config.lacp_decides != 4853221167Sgnn VXGE_HAL_LAG_LACP_DECIDES_DEFAULT) { 4854221167Sgnn if (lag_config->ap_mode_config.lacp_decides == 4855221167Sgnn VXGE_HAL_LAG_LACP_DECIDES_ENBALE) 4856221167Sgnn val64 |= VXGE_HAL_LAG_ACTIVE_PASSIVE_CFG_LACP_DECIDES; 4857221167Sgnn else 4858221167Sgnn val64 &= ~VXGE_HAL_LAG_ACTIVE_PASSIVE_CFG_LACP_DECIDES; 4859221167Sgnn } 4860221167Sgnn 4861221167Sgnn if (lag_config->ap_mode_config.pref_active_port != 4862221167Sgnn VXGE_HAL_LAG_PREF_ACTIVE_PORT_DEFAULT) { 4863221167Sgnn if (lag_config->ap_mode_config.pref_active_port == 4864221167Sgnn VXGE_HAL_LAG_PREF_ACTIVE_PORT_1) 4865221167Sgnn val64 |= 4866221167Sgnn VXGE_HAL_LAG_ACTIVE_PASSIVE_CFG_PREF_ACTIVE_PORT_NUM; 4867221167Sgnn else 4868221167Sgnn val64 &= 4869221167Sgnn ~VXGE_HAL_LAG_ACTIVE_PASSIVE_CFG_PREF_ACTIVE_PORT_NUM; 4870221167Sgnn } 4871221167Sgnn 4872221167Sgnn if (lag_config->ap_mode_config.auto_failback != 4873221167Sgnn VXGE_HAL_LAG_AUTO_FAILBACK_DEFAULT) { 4874221167Sgnn if (lag_config->ap_mode_config.auto_failback == 4875221167Sgnn VXGE_HAL_LAG_AUTO_FAILBACK_ENBALE) 4876221167Sgnn val64 |= VXGE_HAL_LAG_ACTIVE_PASSIVE_CFG_AUTO_FAILBACK; 4877221167Sgnn else 4878221167Sgnn val64 &= ~VXGE_HAL_LAG_ACTIVE_PASSIVE_CFG_AUTO_FAILBACK; 4879221167Sgnn } 4880221167Sgnn 4881221167Sgnn if (lag_config->ap_mode_config.failback_en != 4882221167Sgnn VXGE_HAL_LAG_FAILBACK_EN_DEFAULT) { 4883221167Sgnn if (lag_config->ap_mode_config.failback_en == 4884221167Sgnn VXGE_HAL_LAG_FAILBACK_EN_ENBALE) 4885221167Sgnn val64 |= VXGE_HAL_LAG_ACTIVE_PASSIVE_CFG_FAILBACK_EN; 4886221167Sgnn else 4887221167Sgnn val64 &= ~VXGE_HAL_LAG_ACTIVE_PASSIVE_CFG_FAILBACK_EN; 4888221167Sgnn } 4889221167Sgnn 4890221167Sgnn if (lag_config->ap_mode_config.cold_failover_timeout != 4891221167Sgnn VXGE_HAL_LAG_DEF_COLD_FAILOVER_TIMEOUT) { 4892221167Sgnn val64 &= ~VXGE_HAL_LAG_ACTIVE_PASSIVE_CFG_COLD_FAILOVER_TIMEOUT( 4893221167Sgnn 0xffff); 4894221167Sgnn val64 |= VXGE_HAL_LAG_ACTIVE_PASSIVE_CFG_COLD_FAILOVER_TIMEOUT( 4895221167Sgnn lag_config->ap_mode_config.cold_failover_timeout); 4896221167Sgnn } 4897221167Sgnn 4898221167Sgnn vxge_os_pio_mem_write64(hldev->header.pdev, 4899221167Sgnn hldev->header.regh0, 4900221167Sgnn val64, 4901221167Sgnn &hldev->mrpcim_reg->lag_active_passive_cfg); 4902221167Sgnn 4903221167Sgnn val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 4904221167Sgnn hldev->header.regh0, 4905221167Sgnn &hldev->mrpcim_reg->lag_lacp_cfg); 4906221167Sgnn 4907221167Sgnn if (lag_config->lacp_config.lacp_en != 4908221167Sgnn VXGE_HAL_LAG_LACP_EN_DEFAULT) { 4909221167Sgnn if (lag_config->lacp_config.lacp_en == 4910221167Sgnn VXGE_HAL_LAG_LACP_EN_ENABLE) 4911221167Sgnn val64 |= VXGE_HAL_LAG_LACP_CFG_EN; 4912221167Sgnn else 4913221167Sgnn val64 &= ~VXGE_HAL_LAG_LACP_CFG_EN; 4914221167Sgnn } 4915221167Sgnn 4916221167Sgnn if (lag_config->lacp_config.lacp_begin != 4917221167Sgnn VXGE_HAL_LAG_LACP_BEGIN_DEFAULT) { 4918221167Sgnn if (lag_config->lacp_config.lacp_begin == 4919221167Sgnn VXGE_HAL_LAG_LACP_BEGIN_RESET) 4920221167Sgnn val64 |= VXGE_HAL_LAG_LACP_CFG_LACP_BEGIN; 4921221167Sgnn else 4922221167Sgnn val64 &= ~VXGE_HAL_LAG_LACP_CFG_LACP_BEGIN; 4923221167Sgnn } 4924221167Sgnn 4925221167Sgnn if (lag_config->lacp_config.discard_lacp != 4926221167Sgnn VXGE_HAL_LAG_DISCARD_LACP_DEFAULT) { 4927221167Sgnn if (lag_config->lacp_config.discard_lacp == 4928221167Sgnn VXGE_HAL_LAG_DISCARD_LACP_ENABLE) 4929221167Sgnn val64 |= VXGE_HAL_LAG_LACP_CFG_DISCARD_LACP; 4930221167Sgnn else 4931221167Sgnn val64 &= ~VXGE_HAL_LAG_LACP_CFG_DISCARD_LACP; 4932221167Sgnn } 4933221167Sgnn 4934221167Sgnn if (lag_config->lacp_config.liberal_len_chk != 4935221167Sgnn VXGE_HAL_LAG_LIBERAL_LEN_CHK_DEFAULT) { 4936221167Sgnn if (lag_config->lacp_config.liberal_len_chk == 4937221167Sgnn VXGE_HAL_LAG_LIBERAL_LEN_CHK_ENABLE) 4938221167Sgnn val64 |= VXGE_HAL_LAG_LACP_CFG_LIBERAL_LEN_CHK; 4939221167Sgnn else 4940221167Sgnn val64 &= ~VXGE_HAL_LAG_LACP_CFG_LIBERAL_LEN_CHK; 4941221167Sgnn } 4942221167Sgnn 4943221167Sgnn vxge_os_pio_mem_write64(hldev->header.pdev, 4944221167Sgnn hldev->header.regh0, 4945221167Sgnn val64, 4946221167Sgnn &hldev->mrpcim_reg->lag_lacp_cfg); 4947221167Sgnn 4948221167Sgnn val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 4949221167Sgnn hldev->header.regh0, 4950221167Sgnn &hldev->mrpcim_reg->lag_marker_cfg); 4951221167Sgnn 4952221167Sgnn if (lag_config->lacp_config.marker_gen_recv_en != 4953221167Sgnn VXGE_HAL_LAG_MARKER_GEN_RECV_EN_DEFAULT) { 4954221167Sgnn if (lag_config->lacp_config.marker_gen_recv_en == 4955221167Sgnn VXGE_HAL_LAG_MARKER_GEN_RECV_EN_ENABLE) 4956221167Sgnn val64 |= VXGE_HAL_LAG_MARKER_CFG_GEN_RCVR_EN; 4957221167Sgnn else 4958221167Sgnn val64 &= ~VXGE_HAL_LAG_MARKER_CFG_GEN_RCVR_EN; 4959221167Sgnn } 4960221167Sgnn 4961221167Sgnn if (lag_config->lacp_config.marker_resp_en != 4962221167Sgnn VXGE_HAL_LAG_MARKER_RESP_EN_DEFAULT) { 4963221167Sgnn if (lag_config->lacp_config.marker_resp_en == 4964221167Sgnn VXGE_HAL_LAG_MARKER_RESP_EN_ENABLE) 4965221167Sgnn val64 |= VXGE_HAL_LAG_MARKER_CFG_RESP_EN; 4966221167Sgnn else 4967221167Sgnn val64 &= ~VXGE_HAL_LAG_MARKER_CFG_RESP_EN; 4968221167Sgnn } 4969221167Sgnn 4970221167Sgnn if (lag_config->lacp_config.marker_resp_timeout != 4971221167Sgnn VXGE_HAL_LAG_DEF_MARKER_RESP_TIMEOUT) { 4972221167Sgnn val64 &= ~VXGE_HAL_LAG_MARKER_CFG_RESP_TIMEOUT(0xffff); 4973221167Sgnn val64 |= VXGE_HAL_LAG_MARKER_CFG_RESP_TIMEOUT( 4974221167Sgnn lag_config->lacp_config.marker_resp_timeout); 4975221167Sgnn } 4976221167Sgnn 4977221167Sgnn if (lag_config->lacp_config.slow_proto_mrkr_min_interval != 4978221167Sgnn VXGE_HAL_LAG_DEF_SLOW_PROTO_MRKR_MIN_INTERVAL) { 4979221167Sgnn val64 &= ~VXGE_HAL_LAG_MARKER_CFG_SLOW_PROTO_MRKR_MIN_INTERVAL( 4980221167Sgnn 0xffff); 4981221167Sgnn val64 |= VXGE_HAL_LAG_MARKER_CFG_SLOW_PROTO_MRKR_MIN_INTERVAL( 4982221167Sgnn lag_config->lacp_config.slow_proto_mrkr_min_interval); 4983221167Sgnn } 4984221167Sgnn 4985221167Sgnn if (lag_config->lacp_config.throttle_mrkr_resp != 4986221167Sgnn VXGE_HAL_LAG_THROTTLE_MRKR_RESP_DEFAULT) { 4987221167Sgnn if (lag_config->lacp_config.throttle_mrkr_resp == 4988221167Sgnn VXGE_HAL_LAG_THROTTLE_MRKR_RESP_ENABLE) 4989221167Sgnn val64 |= VXGE_HAL_LAG_MARKER_CFG_THROTTLE_MRKR_RESP; 4990221167Sgnn else 4991221167Sgnn val64 &= ~VXGE_HAL_LAG_MARKER_CFG_THROTTLE_MRKR_RESP; 4992221167Sgnn } 4993221167Sgnn 4994221167Sgnn vxge_os_pio_mem_write64(hldev->header.pdev, 4995221167Sgnn hldev->header.regh0, 4996221167Sgnn val64, 4997221167Sgnn &hldev->mrpcim_reg->lag_marker_cfg); 4998221167Sgnn 4999221167Sgnn for (i = 0; i < VXGE_HAL_LAG_PORT_MAX_PORTS; i++) { 5000221167Sgnn 5001221167Sgnn val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 5002221167Sgnn hldev->header.regh0, 5003221167Sgnn &hldev->mrpcim_reg->lag_port_cfg[i]); 5004221167Sgnn 5005221167Sgnn if (lag_config->port_config[i].lag_en != 5006221167Sgnn VXGE_HAL_LAG_PORT_LAG_EN_DEFAULT) { 5007221167Sgnn if (lag_config->port_config[i].lag_en == 5008221167Sgnn VXGE_HAL_LAG_PORT_LAG_EN_ENABLE) 5009221167Sgnn val64 |= VXGE_HAL_LAG_PORT_CFG_EN; 5010221167Sgnn else 5011221167Sgnn val64 &= ~VXGE_HAL_LAG_PORT_CFG_EN; 5012221167Sgnn } 5013221167Sgnn 5014221167Sgnn if (lag_config->port_config[i].discard_slow_proto != 5015221167Sgnn VXGE_HAL_LAG_PORT_DISCARD_SLOW_PROTO_DEFAULT) { 5016221167Sgnn if (lag_config->port_config[i].discard_slow_proto == 5017221167Sgnn VXGE_HAL_LAG_PORT_DISCARD_SLOW_PROTO_ENABLE) 5018221167Sgnn val64 |= 5019221167Sgnn VXGE_HAL_LAG_PORT_CFG_DISCARD_SLOW_PROTO; 5020221167Sgnn else 5021221167Sgnn val64 &= 5022221167Sgnn ~VXGE_HAL_LAG_PORT_CFG_DISCARD_SLOW_PROTO; 5023221167Sgnn } 5024221167Sgnn 5025221167Sgnn if (lag_config->port_config[i].host_chosen_aggr != 5026221167Sgnn VXGE_HAL_LAG_PORT_HOST_CHOSEN_AGGR_DEFAULT) { 5027221167Sgnn if (lag_config->port_config[i].host_chosen_aggr == 5028221167Sgnn VXGE_HAL_LAG_PORT_HOST_CHOSEN_AGGR_1) 5029221167Sgnn val64 |= 5030221167Sgnn VXGE_HAL_LAG_PORT_CFG_HOST_CHOSEN_AGGR; 5031221167Sgnn else 5032221167Sgnn val64 &= 5033221167Sgnn ~VXGE_HAL_LAG_PORT_CFG_HOST_CHOSEN_AGGR; 5034221167Sgnn } 5035221167Sgnn 5036221167Sgnn if (lag_config->port_config[i].discard_unknown_slow_proto != 5037221167Sgnn VXGE_HAL_LAG_PORT_DISCARD_UNKNOWN_SLOW_PROTO_DEFAULT) { 5038221167Sgnn if (lag_config->port_config[i].discard_unknown_slow_proto == 5039221167Sgnn VXGE_HAL_LAG_PORT_DISCARD_UNKNOWN_SLOW_PROTO_ENABLE) 5040221167Sgnn val64 |= 5041221167Sgnn VXGE_HAL_LAG_PORT_CFG_DISCARD_UNKNOWN_SLOW_PROTO; 5042221167Sgnn else 5043221167Sgnn val64 &= 5044221167Sgnn ~VXGE_HAL_LAG_PORT_CFG_DISCARD_UNKNOWN_SLOW_PROTO; 5045221167Sgnn } 5046221167Sgnn 5047221167Sgnn vxge_os_pio_mem_write64(hldev->header.pdev, 5048221167Sgnn hldev->header.regh0, 5049221167Sgnn val64, 5050221167Sgnn &hldev->mrpcim_reg->lag_port_cfg[i]); 5051221167Sgnn 5052221167Sgnn val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 5053221167Sgnn hldev->header.regh0, 5054221167Sgnn &hldev->mrpcim_reg->lag_port_actor_admin_cfg[i]); 5055221167Sgnn 5056221167Sgnn if (lag_config->port_config[i].actor_port_num != 5057221167Sgnn VXGE_HAL_LAG_PORT_DEF_ACTOR_PORT_NUM) { 5058221167Sgnn val64 &= ~VXGE_HAL_LAG_PORT_ACTOR_ADMIN_CFG_PORT_NUM( 5059221167Sgnn 0xffff); 5060221167Sgnn val64 |= VXGE_HAL_LAG_PORT_ACTOR_ADMIN_CFG_PORT_NUM( 5061221167Sgnn lag_config->port_config[i].actor_port_num); 5062221167Sgnn } 5063221167Sgnn 5064221167Sgnn if (lag_config->port_config[i].actor_port_priority != 5065221167Sgnn VXGE_HAL_LAG_PORT_DEF_ACTOR_PORT_PRIORITY) { 5066221167Sgnn val64 &= ~VXGE_HAL_LAG_PORT_ACTOR_ADMIN_CFG_PORT_PRI( 5067221167Sgnn 0xffff); 5068221167Sgnn val64 |= VXGE_HAL_LAG_PORT_ACTOR_ADMIN_CFG_PORT_PRI( 5069221167Sgnn lag_config->port_config[i].actor_port_priority); 5070221167Sgnn } 5071221167Sgnn 5072221167Sgnn if (lag_config->port_config[i].actor_key_10g != 5073221167Sgnn VXGE_HAL_LAG_PORT_DEF_ACTOR_KEY_10G) { 5074221167Sgnn val64 &= ~VXGE_HAL_LAG_PORT_ACTOR_ADMIN_CFG_KEY_10G( 5075221167Sgnn 0xffff); 5076221167Sgnn val64 |= VXGE_HAL_LAG_PORT_ACTOR_ADMIN_CFG_KEY_10G( 5077221167Sgnn lag_config->port_config[i].actor_key_10g); 5078221167Sgnn } 5079221167Sgnn 5080221167Sgnn if (lag_config->port_config[i].actor_key_1g != 5081221167Sgnn VXGE_HAL_LAG_PORT_DEF_ACTOR_KEY_1G) { 5082221167Sgnn val64 &= ~VXGE_HAL_LAG_PORT_ACTOR_ADMIN_CFG_KEY_1G( 5083221167Sgnn 0xffff); 5084221167Sgnn val64 |= VXGE_HAL_LAG_PORT_ACTOR_ADMIN_CFG_KEY_1G( 5085221167Sgnn lag_config->port_config[i].actor_key_1g); 5086221167Sgnn } 5087221167Sgnn 5088221167Sgnn vxge_os_pio_mem_write64(hldev->header.pdev, 5089221167Sgnn hldev->header.regh0, 5090221167Sgnn val64, 5091221167Sgnn &hldev->mrpcim_reg->lag_port_actor_admin_cfg[i]); 5092221167Sgnn 5093221167Sgnn val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 5094221167Sgnn hldev->header.regh0, 5095221167Sgnn &hldev->mrpcim_reg->lag_port_actor_admin_state[i]); 5096221167Sgnn 5097221167Sgnn if (lag_config->port_config[i].actor_lacp_activity != 5098221167Sgnn VXGE_HAL_LAG_PORT_ACTOR_LACP_ACTIVITY_DEFAULT) { 5099221167Sgnn if (lag_config->port_config[i].actor_lacp_activity == 5100221167Sgnn VXGE_HAL_LAG_PORT_ACTOR_LACP_ACTIVITY_ACTIVE) 5101221167Sgnn val64 |= 5102221167Sgnn VXGE_HAL_LAG_PORT_ACTOR_ADMIN_STATE_LACP_ACTIVITY; 5103221167Sgnn else 5104221167Sgnn val64 &= 5105221167Sgnn ~VXGE_HAL_LAG_PORT_ACTOR_ADMIN_STATE_LACP_ACTIVITY; 5106221167Sgnn } 5107221167Sgnn 5108221167Sgnn if (lag_config->port_config[i].actor_lacp_timeout != 5109221167Sgnn VXGE_HAL_LAG_PORT_ACTOR_LACP_ACTIVITY_DEFAULT) { 5110221167Sgnn if (lag_config->port_config[i].actor_lacp_timeout == 5111221167Sgnn VXGE_HAL_LAG_PORT_ACTOR_LACP_TIMEOUT_SHORT) 5112221167Sgnn val64 |= 5113221167Sgnn VXGE_HAL_LAG_PORT_ACTOR_ADMIN_STATE_LACP_TIMEOUT; 5114221167Sgnn else 5115221167Sgnn val64 &= 5116221167Sgnn ~VXGE_HAL_LAG_PORT_ACTOR_ADMIN_STATE_LACP_TIMEOUT; 5117221167Sgnn } 5118221167Sgnn 5119221167Sgnn if (lag_config->port_config[i].actor_aggregation != 5120221167Sgnn VXGE_HAL_LAG_PORT_ACTOR_AGGREGATION_DEFAULT) { 5121221167Sgnn if (lag_config->port_config[i].actor_aggregation == 5122221167Sgnn VXGE_HAL_LAG_PORT_ACTOR_AGGREGATION_AGGREGATEABLE) 5123221167Sgnn val64 |= 5124221167Sgnn VXGE_HAL_LAG_PORT_ACTOR_ADMIN_STATE_AGGREGATION; 5125221167Sgnn else 5126221167Sgnn val64 &= 5127221167Sgnn ~VXGE_HAL_LAG_PORT_ACTOR_ADMIN_STATE_AGGREGATION; 5128221167Sgnn } 5129221167Sgnn 5130221167Sgnn if (lag_config->port_config[i].actor_synchronization != 5131221167Sgnn VXGE_HAL_LAG_PORT_ACTOR_SYNCHRONIZATION_DEFAULT) { 5132221167Sgnn if (lag_config->port_config[i].actor_aggregation == 5133221167Sgnn VXGE_HAL_LAG_PORT_ACTOR_SYNCHRONIZATION_IN_SYNC) 5134221167Sgnn val64 |= VXGE_HAL_LAG_PORT_ACTOR_ADMIN_STATE_SYNCHRONIZATION; 5135221167Sgnn else 5136221167Sgnn val64 &= ~VXGE_HAL_LAG_PORT_ACTOR_ADMIN_STATE_SYNCHRONIZATION; 5137221167Sgnn } 5138221167Sgnn 5139221167Sgnn if (lag_config->port_config[i].actor_collecting != 5140221167Sgnn VXGE_HAL_LAG_PORT_ACTOR_COLLECTING_DEFAULT) { 5141221167Sgnn if (lag_config->port_config[i].actor_collecting == 5142221167Sgnn VXGE_HAL_LAG_PORT_ACTOR_COLLECTING_ENABLE) 5143221167Sgnn val64 |= 5144221167Sgnn VXGE_HAL_LAG_PORT_ACTOR_ADMIN_STATE_COLLECTING; 5145221167Sgnn else 5146221167Sgnn val64 &= 5147221167Sgnn ~VXGE_HAL_LAG_PORT_ACTOR_ADMIN_STATE_COLLECTING; 5148221167Sgnn } 5149221167Sgnn 5150221167Sgnn if (lag_config->port_config[i].actor_distributing != 5151221167Sgnn VXGE_HAL_LAG_PORT_ACTOR_DISTRIBUTING_DEFAULT) { 5152221167Sgnn if (lag_config->port_config[i].actor_distributing == 5153221167Sgnn VXGE_HAL_LAG_PORT_ACTOR_DISTRIBUTING_ENABLE) 5154221167Sgnn val64 |= 5155221167Sgnn VXGE_HAL_LAG_PORT_ACTOR_ADMIN_STATE_DISTRIBUTING; 5156221167Sgnn else 5157221167Sgnn val64 &= 5158221167Sgnn ~VXGE_HAL_LAG_PORT_ACTOR_ADMIN_STATE_DISTRIBUTING; 5159221167Sgnn } 5160221167Sgnn 5161221167Sgnn if (lag_config->port_config[i].actor_defaulted != 5162221167Sgnn VXGE_HAL_LAG_PORT_ACTOR_DEFAULTED_DEFAULT) { 5163221167Sgnn if (lag_config->port_config[i].actor_defaulted == 5164221167Sgnn VXGE_HAL_LAG_PORT_ACTOR_NOT_DEFAULTED) 5165221167Sgnn val64 |= VXGE_HAL_LAG_PORT_ACTOR_ADMIN_STATE_DEFAULTED; 5166221167Sgnn else 5167221167Sgnn val64 &= ~VXGE_HAL_LAG_PORT_ACTOR_ADMIN_STATE_DEFAULTED; 5168221167Sgnn } 5169221167Sgnn 5170221167Sgnn if (lag_config->port_config[i].actor_expired != 5171221167Sgnn VXGE_HAL_LAG_PORT_ACTOR_EXPIRED_DEFAULT) { 5172221167Sgnn if (lag_config->port_config[i].actor_expired == 5173221167Sgnn VXGE_HAL_LAG_PORT_ACTOR_NOT_EXPIRED) 5174221167Sgnn val64 |= VXGE_HAL_LAG_PORT_ACTOR_ADMIN_STATE_EXPIRED; 5175221167Sgnn else 5176221167Sgnn val64 &= ~VXGE_HAL_LAG_PORT_ACTOR_ADMIN_STATE_EXPIRED; 5177221167Sgnn } 5178221167Sgnn 5179221167Sgnn vxge_os_pio_mem_write64(hldev->header.pdev, 5180221167Sgnn hldev->header.regh0, 5181221167Sgnn val64, 5182221167Sgnn &hldev->mrpcim_reg->lag_port_actor_admin_state[i]); 5183221167Sgnn 5184221167Sgnn val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 5185221167Sgnn hldev->header.regh0, 5186221167Sgnn &hldev->mrpcim_reg->lag_port_partner_admin_cfg[i]); 5187221167Sgnn 5188221167Sgnn if (lag_config->port_config[i].partner_sys_pri != 5189221167Sgnn VXGE_HAL_LAG_PORT_DEF_PARTNER_SYS_PRI) { 5190221167Sgnn val64 &= ~VXGE_HAL_LAG_PORT_PARTNER_ADMIN_CFG_SYS_PRI( 5191221167Sgnn 0xffff); 5192221167Sgnn val64 |= VXGE_HAL_LAG_PORT_PARTNER_ADMIN_CFG_SYS_PRI( 5193221167Sgnn lag_config->port_config[i].partner_sys_pri); 5194221167Sgnn } 5195221167Sgnn 5196221167Sgnn if (lag_config->port_config[i].partner_key != 5197221167Sgnn VXGE_HAL_LAG_PORT_DEF_PARTNER_KEY) { 5198221167Sgnn val64 &= ~VXGE_HAL_LAG_PORT_PARTNER_ADMIN_CFG_KEY( 5199221167Sgnn 0xffff); 5200221167Sgnn val64 |= VXGE_HAL_LAG_PORT_PARTNER_ADMIN_CFG_KEY( 5201221167Sgnn lag_config->port_config[i].partner_key); 5202221167Sgnn } 5203221167Sgnn 5204221167Sgnn if (lag_config->port_config[i].partner_port_num != 5205221167Sgnn VXGE_HAL_LAG_PORT_DEF_PARTNER_PORT_NUM) { 5206221167Sgnn val64 &= ~VXGE_HAL_LAG_PORT_PARTNER_ADMIN_CFG_PORT_NUM( 5207221167Sgnn 0xffff); 5208221167Sgnn val64 |= VXGE_HAL_LAG_PORT_PARTNER_ADMIN_CFG_PORT_NUM( 5209221167Sgnn lag_config->port_config[i].partner_port_num); 5210221167Sgnn } 5211221167Sgnn 5212221167Sgnn if (lag_config->port_config[i].partner_port_priority != 5213221167Sgnn VXGE_HAL_LAG_PORT_DEF_PARTNER_PORT_PRIORITY) { 5214221167Sgnn val64 &= ~VXGE_HAL_LAG_PORT_PARTNER_ADMIN_CFG_PORT_PRI( 5215221167Sgnn 0xffff); 5216221167Sgnn val64 |= VXGE_HAL_LAG_PORT_PARTNER_ADMIN_CFG_PORT_PRI( 5217221167Sgnn lag_config->port_config[i].actor_port_priority); 5218221167Sgnn } 5219221167Sgnn 5220221167Sgnn vxge_os_pio_mem_write64(hldev->header.pdev, 5221221167Sgnn hldev->header.regh0, 5222221167Sgnn val64, 5223221167Sgnn &hldev->mrpcim_reg->lag_port_partner_admin_cfg[i]); 5224221167Sgnn 5225221167Sgnn val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 5226221167Sgnn hldev->header.regh0, 5227221167Sgnn &hldev->mrpcim_reg->lag_port_partner_admin_state[i]); 5228221167Sgnn 5229221167Sgnn if (lag_config->port_config[i].partner_lacp_activity != 5230221167Sgnn VXGE_HAL_LAG_PORT_PARTNER_LACP_ACTIVITY_DEFAULT) { 5231221167Sgnn if (lag_config->port_config[i].partner_lacp_activity == 5232221167Sgnn VXGE_HAL_LAG_PORT_PARTNER_LACP_ACTIVITY_ACTIVE) 5233221167Sgnn val64 |= VXGE_HAL_LAG_PORT_PARTNER_ADMIN_STATE_LACP_ACTIVITY; 5234221167Sgnn else 5235221167Sgnn val64 &= ~VXGE_HAL_LAG_PORT_PARTNER_ADMIN_STATE_LACP_ACTIVITY; 5236221167Sgnn } 5237221167Sgnn 5238221167Sgnn if (lag_config->port_config[i].partner_lacp_timeout != 5239221167Sgnn VXGE_HAL_LAG_PORT_PARTNER_LACP_ACTIVITY_DEFAULT) { 5240221167Sgnn if (lag_config->port_config[i].partner_lacp_timeout == 5241221167Sgnn VXGE_HAL_LAG_PORT_PARTNER_LACP_TIMEOUT_SHORT) 5242221167Sgnn val64 |= 5243221167Sgnn VXGE_HAL_LAG_PORT_PARTNER_ADMIN_STATE_LACP_TIMEOUT; 5244221167Sgnn else 5245221167Sgnn val64 &= 5246221167Sgnn ~VXGE_HAL_LAG_PORT_PARTNER_ADMIN_STATE_LACP_TIMEOUT; 5247221167Sgnn } 5248221167Sgnn 5249221167Sgnn if (lag_config->port_config[i].partner_aggregation != 5250221167Sgnn VXGE_HAL_LAG_PORT_PARTNER_AGGREGATION_DEFAULT) { 5251221167Sgnn if (lag_config->port_config[i].partner_aggregation == 5252221167Sgnn VXGE_HAL_LAG_PORT_PARTNER_AGGREGATION_AGGREGATEABLE) 5253221167Sgnn val64 |= 5254221167Sgnn VXGE_HAL_LAG_PORT_PARTNER_ADMIN_STATE_AGGREGATION; 5255221167Sgnn else 5256221167Sgnn val64 &= 5257221167Sgnn ~VXGE_HAL_LAG_PORT_PARTNER_ADMIN_STATE_AGGREGATION; 5258221167Sgnn } 5259221167Sgnn 5260221167Sgnn if (lag_config->port_config[i].partner_synchronization != 5261221167Sgnn VXGE_HAL_LAG_PORT_PARTNER_SYNCHRONIZATION_DEFAULT) { 5262221167Sgnn if (lag_config->port_config[i].partner_aggregation == 5263221167Sgnn VXGE_HAL_LAG_PORT_PARTNER_SYNCHRONIZATION_IN_SYNC) 5264221167Sgnn val64 |= VXGE_HAL_LAG_PORT_PARTNER_ADMIN_STATE_SYNCHRONIZATION; 5265221167Sgnn else 5266221167Sgnn val64 &= ~VXGE_HAL_LAG_PORT_PARTNER_ADMIN_STATE_SYNCHRONIZATION; 5267221167Sgnn } 5268221167Sgnn 5269221167Sgnn if (lag_config->port_config[i].partner_collecting != 5270221167Sgnn VXGE_HAL_LAG_PORT_PARTNER_COLLECTING_DEFAULT) { 5271221167Sgnn if (lag_config->port_config[i].partner_collecting == 5272221167Sgnn VXGE_HAL_LAG_PORT_PARTNER_COLLECTING_ENABLE) 5273221167Sgnn val64 |= 5274221167Sgnn VXGE_HAL_LAG_PORT_PARTNER_ADMIN_STATE_COLLECTING; 5275221167Sgnn else 5276221167Sgnn val64 &= 5277221167Sgnn ~VXGE_HAL_LAG_PORT_PARTNER_ADMIN_STATE_COLLECTING; 5278221167Sgnn } 5279221167Sgnn 5280221167Sgnn if (lag_config->port_config[i].partner_distributing != 5281221167Sgnn VXGE_HAL_LAG_PORT_PARTNER_DISTRIBUTING_DEFAULT) { 5282221167Sgnn if (lag_config->port_config[i].partner_distributing == 5283221167Sgnn VXGE_HAL_LAG_PORT_PARTNER_DISTRIBUTING_ENABLE) 5284221167Sgnn val64 |= 5285221167Sgnn VXGE_HAL_LAG_PORT_PARTNER_ADMIN_STATE_DISTRIBUTING; 5286221167Sgnn else 5287221167Sgnn val64 &= 5288221167Sgnn ~VXGE_HAL_LAG_PORT_PARTNER_ADMIN_STATE_DISTRIBUTING; 5289221167Sgnn } 5290221167Sgnn 5291221167Sgnn if (lag_config->port_config[i].partner_defaulted != 5292221167Sgnn VXGE_HAL_LAG_PORT_PARTNER_DEFAULTED_DEFAULT) { 5293221167Sgnn if (lag_config->port_config[i].partner_defaulted == 5294221167Sgnn VXGE_HAL_LAG_PORT_PARTNER_NOT_DEFAULTED) 5295221167Sgnn val64 |= 5296221167Sgnn VXGE_HAL_LAG_PORT_PARTNER_ADMIN_STATE_DEFAULTED; 5297221167Sgnn else 5298221167Sgnn val64 &= 5299221167Sgnn ~VXGE_HAL_LAG_PORT_PARTNER_ADMIN_STATE_DEFAULTED; 5300221167Sgnn } 5301221167Sgnn 5302221167Sgnn if (lag_config->port_config[i].partner_expired != 5303221167Sgnn VXGE_HAL_LAG_PORT_PARTNER_EXPIRED_DEFAULT) { 5304221167Sgnn if (lag_config->port_config[i].partner_expired == 5305221167Sgnn VXGE_HAL_LAG_PORT_PARTNER_NOT_EXPIRED) 5306221167Sgnn val64 |= VXGE_HAL_LAG_PORT_PARTNER_ADMIN_STATE_EXPIRED; 5307221167Sgnn else 5308221167Sgnn val64 &= ~VXGE_HAL_LAG_PORT_PARTNER_ADMIN_STATE_EXPIRED; 5309221167Sgnn } 5310221167Sgnn 5311221167Sgnn vxge_os_pio_mem_write64(hldev->header.pdev, 5312221167Sgnn hldev->header.regh0, 5313221167Sgnn val64, 5314221167Sgnn &hldev->mrpcim_reg->lag_port_partner_admin_state[i]); 5315221167Sgnn 5316221167Sgnn val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 5317221167Sgnn hldev->header.regh0, 5318221167Sgnn &hldev->mrpcim_reg->lag_port_partner_admin_sys_id[i]); 5319221167Sgnn 5320221167Sgnn mac_addr = 0; 5321221167Sgnn 5322221167Sgnn for (j = 0; j < VXGE_HAL_ETH_ALEN; j++) { 5323221167Sgnn mac_addr <<= 8; 5324221167Sgnn mac_addr |= 5325221167Sgnn (u8) lag_config->port_config[i].partner_mac_addr[j]; 5326221167Sgnn } 5327221167Sgnn 5328221167Sgnn if (mac_addr != 0xffffffffffffULL) { 5329221167Sgnn val64 &= ~VXGE_HAL_LAG_PORT_PARTNER_ADMIN_SYS_ID_ADDR( 5330221167Sgnn 0xffffffffffffULL); 5331221167Sgnn val64 |= VXGE_HAL_LAG_PORT_PARTNER_ADMIN_SYS_ID_ADDR( 5332221167Sgnn mac_addr); 5333221167Sgnn } 5334221167Sgnn 5335221167Sgnn vxge_os_pio_mem_write64(hldev->header.pdev, 5336221167Sgnn hldev->header.regh0, 5337221167Sgnn val64, 5338221167Sgnn &hldev->mrpcim_reg->lag_port_partner_admin_sys_id[i]); 5339221167Sgnn 5340221167Sgnn } 5341221167Sgnn 5342221167Sgnn for (i = 0; i < VXGE_HAL_LAG_AGGR_MAX_PORTS; i++) { 5343221167Sgnn 5344221167Sgnn val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 5345221167Sgnn hldev->header.regh0, 5346221167Sgnn &hldev->mrpcim_reg->lag_aggr_id_cfg[i]); 5347221167Sgnn 5348221167Sgnn val64 &= ~VXGE_HAL_LAG_AGGR_ID_CFG_ID(0xffff); 5349221167Sgnn val64 |= VXGE_HAL_LAG_AGGR_ID_CFG_ID( 5350221167Sgnn lag_config->aggr_config[i].aggr_id); 5351221167Sgnn 5352221167Sgnn vxge_os_pio_mem_write64(hldev->header.pdev, 5353221167Sgnn hldev->header.regh0, 5354221167Sgnn val64, 5355221167Sgnn &hldev->mrpcim_reg->lag_aggr_id_cfg[i]); 5356221167Sgnn 5357221167Sgnn val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 5358221167Sgnn hldev->header.regh0, 5359221167Sgnn &hldev->mrpcim_reg->lag_aggr_addr_cfg[i]); 5360221167Sgnn 5361221167Sgnn mac_addr = 0; 5362221167Sgnn 5363221167Sgnn for (j = 0; j < VXGE_HAL_ETH_ALEN; j++) { 5364221167Sgnn mac_addr <<= 8; 5365221167Sgnn mac_addr |= (u8) lag_config->aggr_config[i].mac_addr[j]; 5366221167Sgnn } 5367221167Sgnn 5368221167Sgnn if (mac_addr != 0xffffffffffffULL) { 5369221167Sgnn val64 &= 5370221167Sgnn ~VXGE_HAL_LAG_AGGR_ADDR_CFG_ADDR(0xffffffffffffULL); 5371221167Sgnn val64 |= VXGE_HAL_LAG_AGGR_ADDR_CFG_ADDR(mac_addr); 5372221167Sgnn } 5373221167Sgnn 5374221167Sgnn if (lag_config->aggr_config[i].use_port_mac_addr != 5375221167Sgnn VXGE_HAL_LAG_AGGR_USE_PORT_MAC_ADDR_DEFAULT) { 5376221167Sgnn if (lag_config->aggr_config[i].use_port_mac_addr == 5377221167Sgnn VXGE_HAL_LAG_AGGR_USE_PORT_MAC_ADDR_ENABLE) 5378221167Sgnn val64 |= 5379221167Sgnn VXGE_HAL_LAG_AGGR_ADDR_CFG_USE_PORT_ADDR; 5380221167Sgnn else 5381221167Sgnn val64 &= 5382221167Sgnn ~VXGE_HAL_LAG_AGGR_ADDR_CFG_USE_PORT_ADDR; 5383221167Sgnn } 5384221167Sgnn 5385221167Sgnn if (lag_config->aggr_config[i].mac_addr_sel != 5386221167Sgnn VXGE_HAL_LAG_AGGR_MAC_ADDR_SEL_DEFAULT) { 5387221167Sgnn if (lag_config->aggr_config[i].mac_addr_sel == 5388221167Sgnn VXGE_HAL_LAG_AGGR_MAC_ADDR_SEL_PORT_1) 5389221167Sgnn val64 |= VXGE_HAL_LAG_AGGR_ADDR_CFG_ADDR_SEL; 5390221167Sgnn else 5391221167Sgnn val64 &= ~VXGE_HAL_LAG_AGGR_ADDR_CFG_ADDR_SEL; 5392221167Sgnn } 5393221167Sgnn 5394221167Sgnn vxge_os_pio_mem_write64(hldev->header.pdev, 5395221167Sgnn hldev->header.regh0, 5396221167Sgnn val64, 5397221167Sgnn &hldev->mrpcim_reg->lag_aggr_addr_cfg[i]); 5398221167Sgnn 5399221167Sgnn if (lag_config->aggr_config[i].admin_key == 5400221167Sgnn VXGE_HAL_LAG_AGGR_DEF_ADMIN_KEY) { 5401221167Sgnn val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 5402221167Sgnn hldev->header.regh0, 5403221167Sgnn &hldev->mrpcim_reg->lag_aggr_admin_key[i]); 5404221167Sgnn 5405221167Sgnn val64 &= ~VXGE_HAL_LAG_AGGR_ADMIN_KEY_KEY(0xffff); 5406221167Sgnn val64 |= VXGE_HAL_LAG_AGGR_ADMIN_KEY_KEY( 5407221167Sgnn lag_config->aggr_config[i].admin_key); 5408221167Sgnn 5409221167Sgnn vxge_os_pio_mem_write64(hldev->header.pdev, 5410221167Sgnn hldev->header.regh0, 5411221167Sgnn val64, 5412221167Sgnn &hldev->mrpcim_reg->lag_aggr_admin_key[i]); 5413221167Sgnn } 5414221167Sgnn } 5415221167Sgnn 5416221167Sgnn if (lag_config->sys_pri != VXGE_HAL_LAG_DEF_SYS_PRI) { 5417221167Sgnn val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 5418221167Sgnn hldev->header.regh0, 5419221167Sgnn &hldev->mrpcim_reg->lag_sys_cfg); 5420221167Sgnn 5421221167Sgnn val64 &= ~VXGE_HAL_LAG_SYS_CFG_SYS_PRI(0xffff); 5422221167Sgnn val64 |= VXGE_HAL_LAG_SYS_CFG_SYS_PRI( 5423221167Sgnn lag_config->sys_pri); 5424221167Sgnn 5425221167Sgnn vxge_os_pio_mem_write64(hldev->header.pdev, 5426221167Sgnn hldev->header.regh0, 5427221167Sgnn val64, 5428221167Sgnn &hldev->mrpcim_reg->lag_sys_cfg); 5429221167Sgnn } 5430221167Sgnn 5431221167Sgnn val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 5432221167Sgnn hldev->header.regh0, 5433221167Sgnn &hldev->mrpcim_reg->lag_sys_id); 5434221167Sgnn 5435221167Sgnn mac_addr = 0; 5436221167Sgnn 5437221167Sgnn for (j = 0; j < VXGE_HAL_ETH_ALEN; j++) { 5438221167Sgnn mac_addr <<= 8; 5439221167Sgnn mac_addr |= (u8) lag_config->mac_addr[j]; 5440221167Sgnn } 5441221167Sgnn 5442221167Sgnn if (mac_addr != 0xffffffffffffULL) { 5443221167Sgnn val64 &= ~VXGE_HAL_LAG_SYS_ID_ADDR(0xffffffffffffULL); 5444221167Sgnn val64 |= VXGE_HAL_LAG_SYS_ID_ADDR(mac_addr); 5445221167Sgnn } 5446221167Sgnn 5447221167Sgnn if (lag_config->use_port_mac_addr != 5448221167Sgnn VXGE_HAL_LAG_USE_PORT_MAC_ADDR_DEFAULT) { 5449221167Sgnn if (lag_config->use_port_mac_addr == 5450221167Sgnn VXGE_HAL_LAG_USE_PORT_MAC_ADDR_ENABLE) 5451221167Sgnn val64 |= VXGE_HAL_LAG_SYS_ID_USE_PORT_ADDR; 5452221167Sgnn else 5453221167Sgnn val64 &= ~VXGE_HAL_LAG_SYS_ID_USE_PORT_ADDR; 5454221167Sgnn } 5455221167Sgnn 5456221167Sgnn if (lag_config->mac_addr_sel != VXGE_HAL_LAG_MAC_ADDR_SEL_DEFAULT) { 5457221167Sgnn if (lag_config->mac_addr_sel == 5458221167Sgnn VXGE_HAL_LAG_MAC_ADDR_SEL_PORT_1) 5459221167Sgnn val64 |= VXGE_HAL_LAG_SYS_ID_ADDR_SEL; 5460221167Sgnn else 5461221167Sgnn val64 &= ~VXGE_HAL_LAG_SYS_ID_ADDR_SEL; 5462221167Sgnn } 5463221167Sgnn 5464221167Sgnn vxge_os_pio_mem_write64(hldev->header.pdev, 5465221167Sgnn hldev->header.regh0, 5466221167Sgnn val64, 5467221167Sgnn &hldev->mrpcim_reg->lag_sys_id); 5468221167Sgnn 5469221167Sgnn 5470221167Sgnn val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 5471221167Sgnn hldev->header.regh0, 5472221167Sgnn &hldev->mrpcim_reg->lag_aggr_alt_admin_key); 5473221167Sgnn 5474221167Sgnn if (lag_config->ap_mode_config.alt_admin_key != 5475221167Sgnn VXGE_HAL_LAG_DEF_ALT_ADMIN_KEY) { 5476221167Sgnn val64 &= ~VXGE_HAL_LAG_AGGR_ALT_ADMIN_KEY_KEY(0xffff); 5477221167Sgnn val64 |= VXGE_HAL_LAG_AGGR_ALT_ADMIN_KEY_KEY( 5478221167Sgnn lag_config->ap_mode_config.alt_admin_key); 5479221167Sgnn } 5480221167Sgnn 5481221167Sgnn if (lag_config->ap_mode_config.alt_aggr != 5482221167Sgnn VXGE_HAL_LAG_ALT_AGGR_DEFAULT) { 5483221167Sgnn if (lag_config->ap_mode_config.alt_aggr == 5484221167Sgnn VXGE_HAL_LAG_ALT_AGGR_1) 5485221167Sgnn val64 |= VXGE_HAL_LAG_AGGR_ALT_ADMIN_KEY_ALT_AGGR; 5486221167Sgnn else 5487221167Sgnn val64 &= ~VXGE_HAL_LAG_AGGR_ALT_ADMIN_KEY_ALT_AGGR; 5488221167Sgnn } 5489221167Sgnn 5490221167Sgnn vxge_os_pio_mem_write64(hldev->header.pdev, 5491221167Sgnn hldev->header.regh0, 5492221167Sgnn val64, 5493221167Sgnn &hldev->mrpcim_reg->lag_aggr_alt_admin_key); 5494221167Sgnn 5495221167Sgnn val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 5496221167Sgnn hldev->header.regh0, 5497221167Sgnn &hldev->mrpcim_reg->lag_timer_cfg_1); 5498221167Sgnn 5499221167Sgnn if (lag_config->fast_per_time != VXGE_HAL_LAG_DEF_FAST_PER_TIME) { 5500221167Sgnn val64 &= ~VXGE_HAL_LAG_TIMER_CFG_1_FAST_PER(0xffff); 5501221167Sgnn val64 |= VXGE_HAL_LAG_TIMER_CFG_1_FAST_PER( 5502221167Sgnn lag_config->fast_per_time); 5503221167Sgnn } 5504221167Sgnn 5505221167Sgnn if (lag_config->slow_per_time != VXGE_HAL_LAG_DEF_SLOW_PER_TIME) { 5506221167Sgnn val64 &= ~VXGE_HAL_LAG_TIMER_CFG_1_SLOW_PER(0xffff); 5507221167Sgnn val64 |= VXGE_HAL_LAG_TIMER_CFG_1_SLOW_PER( 5508221167Sgnn lag_config->slow_per_time); 5509221167Sgnn } 5510221167Sgnn 5511221167Sgnn if (lag_config->short_timeout != VXGE_HAL_LAG_DEF_SHORT_TIMEOUT) { 5512221167Sgnn val64 &= ~VXGE_HAL_LAG_TIMER_CFG_1_SHORT_TIMEOUT(0xffff); 5513221167Sgnn val64 |= VXGE_HAL_LAG_TIMER_CFG_1_SHORT_TIMEOUT( 5514221167Sgnn lag_config->short_timeout); 5515221167Sgnn } 5516221167Sgnn 5517221167Sgnn if (lag_config->long_timeout != VXGE_HAL_LAG_DEF_LONG_TIMEOUT) { 5518221167Sgnn val64 &= ~VXGE_HAL_LAG_TIMER_CFG_1_LONG_TIMEOUT(0xffff); 5519221167Sgnn val64 |= VXGE_HAL_LAG_TIMER_CFG_1_LONG_TIMEOUT( 5520221167Sgnn lag_config->short_timeout); 5521221167Sgnn } 5522221167Sgnn 5523221167Sgnn vxge_os_pio_mem_write64(hldev->header.pdev, 5524221167Sgnn hldev->header.regh0, 5525221167Sgnn val64, 5526221167Sgnn &hldev->mrpcim_reg->lag_timer_cfg_1); 5527221167Sgnn 5528221167Sgnn val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 5529221167Sgnn hldev->header.regh0, 5530221167Sgnn &hldev->mrpcim_reg->lag_timer_cfg_2); 5531221167Sgnn 5532221167Sgnn if (lag_config->churn_det_time != VXGE_HAL_LAG_DEF_CHURN_DET_TIME) { 5533221167Sgnn val64 &= ~VXGE_HAL_LAG_TIMER_CFG_2_CHURN_DET(0xffff); 5534221167Sgnn val64 |= VXGE_HAL_LAG_TIMER_CFG_2_CHURN_DET( 5535221167Sgnn lag_config->churn_det_time); 5536221167Sgnn } 5537221167Sgnn 5538221167Sgnn if (lag_config->aggr_wait_time != VXGE_HAL_LAG_DEF_AGGR_WAIT_TIME) { 5539221167Sgnn val64 &= ~VXGE_HAL_LAG_TIMER_CFG_2_AGGR_WAIT(0xffff); 5540221167Sgnn val64 |= VXGE_HAL_LAG_TIMER_CFG_2_AGGR_WAIT( 5541221167Sgnn lag_config->slow_per_time); 5542221167Sgnn } 5543221167Sgnn 5544221167Sgnn if (lag_config->short_timer_scale != 5545221167Sgnn VXGE_HAL_LAG_SHORT_TIMER_SCALE_DEFAULT) { 5546221167Sgnn val64 &= ~VXGE_HAL_LAG_TIMER_CFG_2_SHORT_TIMER_SCALE(0xffff); 5547221167Sgnn val64 |= VXGE_HAL_LAG_TIMER_CFG_2_SHORT_TIMER_SCALE( 5548221167Sgnn lag_config->short_timer_scale); 5549221167Sgnn } 5550221167Sgnn 5551221167Sgnn if (lag_config->long_timer_scale != 5552221167Sgnn VXGE_HAL_LAG_LONG_TIMER_SCALE_DEFAULT) { 5553221167Sgnn val64 &= ~VXGE_HAL_LAG_TIMER_CFG_2_LONG_TIMER_SCALE(0xffff); 5554221167Sgnn val64 |= VXGE_HAL_LAG_TIMER_CFG_2_LONG_TIMER_SCALE( 5555221167Sgnn lag_config->long_timer_scale); 5556221167Sgnn } 5557221167Sgnn 5558221167Sgnn vxge_os_pio_mem_write64(hldev->header.pdev, 5559221167Sgnn hldev->header.regh0, 5560221167Sgnn val64, 5561221167Sgnn &hldev->mrpcim_reg->lag_timer_cfg_2); 5562221167Sgnn 5563221167Sgnn vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = %d", 5564221167Sgnn __FILE__, __func__, __LINE__, status); 5565221167Sgnn return (status); 5566221167Sgnn 5567221167Sgnn} 5568221167Sgnn 5569221167Sgnn/* 5570221167Sgnn * __hal_mrpcim_get_vpd_data - Getting vpd_data. 5571221167Sgnn * 5572221167Sgnn * @hldev: HAL device handle. 5573221167Sgnn * 5574221167Sgnn * Getting product name and serial number from vpd capabilites structure 5575221167Sgnn * 5576221167Sgnn */ 5577221167Sgnnvoid 5578221167Sgnn__hal_mrpcim_get_vpd_data(__hal_device_t *hldev) 5579221167Sgnn{ 5580221167Sgnn u8 *vpd_data; 5581221167Sgnn u16 data; 5582221167Sgnn u32 data32; 5583221167Sgnn u32 i, j, count, fail = 0; 5584221167Sgnn u32 addr_offset, data_offset; 5585221167Sgnn u32 max_count = hldev->header.config.device_poll_millis * 10; 5586221167Sgnn 5587221167Sgnn vxge_assert(hldev); 5588221167Sgnn 5589221167Sgnn vxge_hal_trace_log_mrpcim("==> %s:%s:%d", 5590221167Sgnn __FILE__, __func__, __LINE__); 5591221167Sgnn 5592221167Sgnn vxge_hal_trace_log_mrpcim("hldev = 0x"VXGE_OS_STXFMT, 5593221167Sgnn (ptr_t) hldev); 5594221167Sgnn 5595221167Sgnn addr_offset = hldev->pci_caps.vpd_cap_offset + 5596221167Sgnn vxge_offsetof(vxge_hal_vpid_capability_le_t, vpd_address); 5597221167Sgnn 5598221167Sgnn data_offset = hldev->pci_caps.vpd_cap_offset + 5599221167Sgnn vxge_offsetof(vxge_hal_vpid_capability_le_t, vpd_data); 5600221167Sgnn 5601221167Sgnn vxge_os_strlcpy((char *) hldev->mrpcim->vpd_data.product_name, 5602221167Sgnn "10 Gigabit Ethernet Adapter", 5603221167Sgnn sizeof(hldev->mrpcim->vpd_data.product_name)); 5604221167Sgnn vxge_os_strlcpy((char *) hldev->mrpcim->vpd_data.serial_num, 5605221167Sgnn "not available", 5606221167Sgnn sizeof(hldev->mrpcim->vpd_data.serial_num)); 5607221167Sgnn 5608221167Sgnn if (hldev->func_id != 0) { 5609221167Sgnn vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = %d", 5610221167Sgnn __FILE__, __func__, __LINE__, 5611221167Sgnn VXGE_HAL_ERR_PRIVILAGED_OPEARATION); 5612221167Sgnn return; 5613221167Sgnn } 5614221167Sgnn vpd_data = (u8 *) vxge_os_malloc(hldev->header.pdev, 5615221167Sgnn VXGE_HAL_VPD_BUFFER_SIZE + 16); 5616221167Sgnn if (vpd_data == 0) 5617221167Sgnn return; 5618221167Sgnn 5619221167Sgnn for (i = 0; i < VXGE_HAL_VPD_BUFFER_SIZE; i += 4) { 5620221167Sgnn vxge_os_pci_write16(hldev->header.pdev, 5621221167Sgnn hldev->header.cfgh, 5622221167Sgnn addr_offset, (u16) i); 5623221167Sgnn for (count = 0; count < max_count; count++) { 5624221167Sgnn vxge_os_udelay(100); 5625221167Sgnn (void) __hal_vpath_pci_read(hldev, 5626221167Sgnn hldev->first_vp_id, 5627221167Sgnn addr_offset, 2, &data); 5628221167Sgnn if (data & VXGE_HAL_PCI_VPID_COMPL_FALG) 5629221167Sgnn break; 5630221167Sgnn } 5631221167Sgnn 5632221167Sgnn if (count >= max_count) { 5633221167Sgnn vxge_hal_info_log_device("%s:ERR, \ 5634221167Sgnn Reading VPD data failed", __func__); 5635221167Sgnn fail = 1; 5636221167Sgnn break; 5637221167Sgnn } 5638221167Sgnn (void) __hal_vpath_pci_read(hldev, 5639221167Sgnn hldev->first_vp_id, 5640221167Sgnn data_offset, 5641221167Sgnn 4, 5642221167Sgnn &data32); 5643221167Sgnn 5644221167Sgnn for (j = 0; j < 4; j++) { 5645221167Sgnn vpd_data[i + j] = (u8) (data32 & 0xff); 5646221167Sgnn data32 >>= 8; 5647221167Sgnn } 5648221167Sgnn } 5649221167Sgnn 5650221167Sgnn if (!fail) { 5651221167Sgnn 5652221167Sgnn /* read serial number of adapter */ 5653221167Sgnn for (count = 0; count < VXGE_HAL_VPD_BUFFER_SIZE; count++) { 5654221167Sgnn if ((vpd_data[count] == 'S') && 5655221167Sgnn (vpd_data[count + 1] == 'N') && 5656221167Sgnn (vpd_data[count + 2] < VXGE_HAL_VPD_LENGTH)) { 5657221167Sgnn (void) vxge_os_memzero( 5658221167Sgnn hldev->mrpcim->vpd_data.serial_num, 5659221167Sgnn VXGE_HAL_VPD_LENGTH); 5660221167Sgnn (void) vxge_os_memcpy( 5661221167Sgnn hldev->mrpcim->vpd_data.serial_num, 5662221167Sgnn &vpd_data[count + 3], 5663221167Sgnn vpd_data[count + 2]); 5664221167Sgnn break; 5665221167Sgnn } 5666221167Sgnn } 5667221167Sgnn 5668221167Sgnn if (vpd_data[1] < VXGE_HAL_VPD_LENGTH) { 5669221167Sgnn (void) vxge_os_memzero( 5670221167Sgnn hldev->mrpcim->vpd_data.product_name, vpd_data[1]); 5671221167Sgnn (void) vxge_os_memcpy(hldev->mrpcim->vpd_data.product_name, 5672221167Sgnn &vpd_data[3], vpd_data[1]); 5673221167Sgnn } 5674221167Sgnn } 5675221167Sgnn 5676221167Sgnn vxge_os_free(hldev->header.pdev, 5677221167Sgnn vpd_data, 5678221167Sgnn VXGE_HAL_VPD_BUFFER_SIZE + 16); 5679221167Sgnn 5680221167Sgnn vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = %d", 5681221167Sgnn __FILE__, __func__, __LINE__, fail); 5682221167Sgnn} 5683221167Sgnn 5684221167Sgnn/* 5685221167Sgnn * __hal_mrpcim_rts_table_access - Get/Set the entries from RTS access tables 5686221167Sgnn * @devh: Device handle. 5687221167Sgnn * @action: Write Enable. 0 - Read Operation; 1 - Write Operation 5688221167Sgnn * @rts_table: Data structure select. Identifies the RTS data structure 5689221167Sgnn * (i.e. lookup table) to access. 5690221167Sgnn * 0; DA; Destination Address 5691221167Sgnn * 1; VID; VLAN ID 5692221167Sgnn * 2; ETYPE; Ethertype 5693221167Sgnn * 3; PN; Layer 4 Port Number 5694221167Sgnn * 4; RANGE_PN; Range of Layer 4 Port Numbers 5695221167Sgnn * 5; RTH_GEN_CFG; Receive-Traffic Hashing General Configuration 5696221167Sgnn * 6; RTH_SOLO_IT; Receive-Traffic Hashing Indirection Table 5697221167Sgnn * (Single Bucket Programming) 5698221167Sgnn * 7; RTH_JHASH_CFG; Receive-Traffic Hashing Jenkins Hash Config 5699221167Sgnn * 8; RTH_MASK; Receive-Traffic Hashing Mask 5700221167Sgnn * 9; RTH_KEY; Receive-Traffic Hashing Key 5701221167Sgnn * 10; QOS; VLAN Quality of Service 5702221167Sgnn * 11; DS; IP Differentiated Services 5703221167Sgnn * @offset: Offset (into the data structure) to execute the command on. 5704221167Sgnn * @data1: Pointer to the data 1 to be read from the table 5705221167Sgnn * @data2: Pointer to the data 2 to be read from the table 5706221167Sgnn * @vpath_vector: Identifies the candidate VPATH(s) for the given entry. 5707221167Sgnn * These VPATH(s) determine the set of target destinations for 5708221167Sgnn * a frame that matches this steering entry. Any or all bits 5709221167Sgnn * can be set, which handles 16+1 virtual paths in an 'n-hot' 5710221167Sgnn * basis. VPATH 0 is the MSbit. 5711221167Sgnn * 5712221167Sgnn * Read from the RTS table 5713221167Sgnn * 5714221167Sgnn */ 5715221167Sgnnvxge_hal_status_e 5716221167Sgnn__hal_mrpcim_rts_table_access( 5717221167Sgnn vxge_hal_device_h devh, 5718221167Sgnn u32 action, 5719221167Sgnn u32 rts_table, 5720221167Sgnn u32 offset, 5721221167Sgnn u64 *data1, 5722221167Sgnn u64 *data2, 5723221167Sgnn u64 *vpath_vector) 5724221167Sgnn{ 5725221167Sgnn u64 val64; 5726221167Sgnn __hal_device_t *hldev; 5727221167Sgnn vxge_hal_status_e status = VXGE_HAL_OK; 5728221167Sgnn 5729221167Sgnn vxge_assert((devh != NULL) && (data1 != NULL) && 5730221167Sgnn (data2 != NULL) && (vpath_vector != NULL)); 5731221167Sgnn 5732221167Sgnn hldev = (__hal_device_t *) devh; 5733221167Sgnn 5734221167Sgnn vxge_hal_trace_log_mrpcim("==> %s:%s:%d", 5735221167Sgnn __FILE__, __func__, __LINE__); 5736221167Sgnn 5737221167Sgnn vxge_hal_trace_log_mrpcim( 5738221167Sgnn "devh = 0x"VXGE_OS_STXFMT", action = %d, rts_table = %d, " 5739221167Sgnn "offset = %d, data1 = 0x"VXGE_OS_STXFMT", " 5740221167Sgnn "data2 = 0x"VXGE_OS_STXFMT", vpath_vector = 0x"VXGE_OS_STXFMT, 5741221167Sgnn (ptr_t) devh, action, rts_table, offset, (ptr_t) data1, 5742221167Sgnn (ptr_t) data2, (ptr_t) vpath_vector); 5743221167Sgnn 5744221167Sgnn val64 = VXGE_HAL_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL(rts_table) | 5745221167Sgnn VXGE_HAL_RTS_MGR_STEER_CTRL_STROBE | 5746221167Sgnn VXGE_HAL_RTS_MGR_STEER_CTRL_OFFSET(offset); 5747221167Sgnn 5748221167Sgnn if (action == VXGE_HAL_RTS_MGR_STEER_CTRL_WE_WRITE) 5749221167Sgnn val64 = VXGE_HAL_RTS_MGR_STEER_CTRL_WE; 5750221167Sgnn 5751221167Sgnn if ((rts_table == 5752221167Sgnn VXGE_HAL_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_RTH_SOLO_IT) || 5753221167Sgnn (rts_table == 5754221167Sgnn VXGE_HAL_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_RTH_MULTI_IT) || 5755221167Sgnn (rts_table == 5756221167Sgnn VXGE_HAL_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_RTH_MASK) || 5757221167Sgnn (rts_table == 5758221167Sgnn VXGE_HAL_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_RTH_KEY)) { 5759221167Sgnn val64 |= VXGE_HAL_RTS_MGR_STEER_CTRL_TABLE_SEL; 5760221167Sgnn } 5761221167Sgnn 5762221167Sgnn vxge_hal_pio_mem_write32_lower(hldev->header.pdev, 5763221167Sgnn hldev->header.regh0, 5764221167Sgnn (u32) bVAL32(val64, 32), 5765221167Sgnn &hldev->mrpcim_reg->rts_mgr_steer_ctrl); 5766221167Sgnn 5767221167Sgnn vxge_os_wmb(); 5768221167Sgnn 5769221167Sgnn vxge_hal_pio_mem_write32_upper(hldev->header.pdev, 5770221167Sgnn hldev->header.regh0, 5771221167Sgnn (u32) bVAL32(val64, 0), 5772221167Sgnn &hldev->mrpcim_reg->rts_mgr_steer_ctrl); 5773221167Sgnn 5774221167Sgnn vxge_os_wmb(); 5775221167Sgnn 5776221167Sgnn status = vxge_hal_device_register_poll( 5777221167Sgnn hldev->header.pdev, 5778221167Sgnn hldev->header.regh0, 5779221167Sgnn &hldev->mrpcim_reg->rts_mgr_steer_ctrl, 0, 5780221167Sgnn VXGE_HAL_RTS_MGR_STEER_CTRL_STROBE, 5781221167Sgnn WAIT_FACTOR * hldev->header.config.device_poll_millis); 5782221167Sgnn 5783221167Sgnn if (status != VXGE_HAL_OK) { 5784221167Sgnn 5785221167Sgnn vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result: %d", 5786221167Sgnn __FILE__, __func__, __LINE__, status); 5787221167Sgnn return (status); 5788221167Sgnn } 5789221167Sgnn 5790221167Sgnn val64 = vxge_os_pio_mem_read64( 5791221167Sgnn hldev->header.pdev, 5792221167Sgnn hldev->header.regh0, 5793221167Sgnn &hldev->mrpcim_reg->rts_mgr_steer_ctrl); 5794221167Sgnn 5795221167Sgnn if ((val64 & VXGE_HAL_RTS_MGR_STEER_CTRL_RMACJ_STATUS) && 5796221167Sgnn (action == VXGE_HAL_RTS_MGR_STEER_CTRL_WE_READ)) { 5797221167Sgnn 5798221167Sgnn *data1 = vxge_os_pio_mem_read64( 5799221167Sgnn hldev->header.pdev, 5800221167Sgnn hldev->header.regh0, 5801221167Sgnn &hldev->mrpcim_reg->rts_mgr_steer_data0); 5802221167Sgnn 5803221167Sgnn *data2 = vxge_os_pio_mem_read64( 5804221167Sgnn hldev->header.pdev, 5805221167Sgnn hldev->header.regh0, 5806221167Sgnn &hldev->mrpcim_reg->rts_mgr_steer_data1); 5807221167Sgnn 5808221167Sgnn *vpath_vector = vxge_os_pio_mem_read64( 5809221167Sgnn hldev->header.pdev, 5810221167Sgnn hldev->header.regh0, 5811221167Sgnn &hldev->mrpcim_reg->rts_mgr_steer_vpath_vector); 5812221167Sgnn 5813221167Sgnn status = VXGE_HAL_OK; 5814221167Sgnn 5815221167Sgnn } else { 5816221167Sgnn status = VXGE_HAL_FAIL; 5817221167Sgnn } 5818221167Sgnn 5819221167Sgnn 5820221167Sgnn vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result: %d", 5821221167Sgnn __FILE__, __func__, __LINE__, 5822221167Sgnn status); 5823221167Sgnn return (status); 5824221167Sgnn} 5825221167Sgnn 5826221167Sgnn/* 5827221167Sgnn * vxge_hal_mrpcim_mac_addr_add - Add the mac address entry 5828221167Sgnn * into MAC address table. 5829221167Sgnn * @devh: Device handle. 5830221167Sgnn * @offset: Index into the DA table to add the mac address. 5831221167Sgnn * @macaddr: MAC address to be added for this vpath into the list 5832221167Sgnn * @macaddr_mask: MAC address mask for macaddr 5833221167Sgnn * @vpath_vector: Bit mask specifying the vpaths to which 5834221167Sgnn * the mac address applies 5835221167Sgnn * @duplicate_mode: Duplicate MAC address add mode. Please see 5836221167Sgnn * vxge_hal_vpath_mac_addr_add_mode_e {} 5837221167Sgnn * 5838221167Sgnn * Adds the given mac address, mac address mask and vpath vector into the list 5839221167Sgnn * 5840221167Sgnn * see also: vxge_hal_mrpcim_mac_addr_get 5841221167Sgnn * 5842221167Sgnn */ 5843221167Sgnnvxge_hal_status_e 5844221167Sgnnvxge_hal_mrpcim_mac_addr_add( 5845221167Sgnn vxge_hal_device_h devh, 5846221167Sgnn u32 offset, 5847221167Sgnn macaddr_t macaddr, 5848221167Sgnn macaddr_t macaddr_mask, 5849221167Sgnn u64 vpath_vector, 5850221167Sgnn u32 duplicate_mode) 5851221167Sgnn{ 5852221167Sgnn u32 i; 5853221167Sgnn u64 data1 = 0ULL; 5854221167Sgnn u64 data2 = 0ULL; 5855221167Sgnn __hal_device_t *hldev; 5856221167Sgnn vxge_hal_status_e status = VXGE_HAL_OK; 5857221167Sgnn 5858221167Sgnn vxge_assert(devh != NULL); 5859221167Sgnn 5860221167Sgnn hldev = (__hal_device_t *) devh; 5861221167Sgnn 5862221167Sgnn vxge_hal_trace_log_mrpcim("==> %s:%s:%d", 5863221167Sgnn __FILE__, __func__, __LINE__); 5864221167Sgnn 5865221167Sgnn vxge_hal_trace_log_mrpcim( 5866221167Sgnn "devh = 0x"VXGE_OS_STXFMT", offset = %d, " 5867221167Sgnn "macaddr = %02x-%02x-%02x-%02x-%02x-%02x, " 5868221167Sgnn "macaddr_mask = %02x-%02x-%02x-%02x-%02x-%02x, " 5869221167Sgnn "vpath_vector = 0x"VXGE_OS_LLXFMT, 5870221167Sgnn (ptr_t) devh, offset, macaddr[0], macaddr[1], macaddr[2], 5871221167Sgnn macaddr[3], macaddr[4], macaddr[5], macaddr_mask[0], 5872221167Sgnn macaddr_mask[1], macaddr_mask[2], macaddr_mask[3], 5873221167Sgnn macaddr_mask[4], macaddr_mask[5], vpath_vector); 5874221167Sgnn 5875221167Sgnn for (i = 0; i < VXGE_HAL_ETH_ALEN; i++) { 5876221167Sgnn data1 <<= 8; 5877221167Sgnn data1 |= (u8) macaddr[i]; 5878221167Sgnn } 5879221167Sgnn 5880221167Sgnn data1 = VXGE_HAL_RTS_MGR_STEER_DATA0_DA_MAC_ADDR(data1); 5881221167Sgnn 5882221167Sgnn for (i = 0; i < VXGE_HAL_ETH_ALEN; i++) { 5883221167Sgnn data2 <<= 8; 5884221167Sgnn data2 |= (u8) macaddr_mask[i]; 5885221167Sgnn } 5886221167Sgnn 5887221167Sgnn switch (duplicate_mode) { 5888221167Sgnn case VXGE_HAL_VPATH_MAC_ADDR_ADD_DUPLICATE: 5889221167Sgnn i = 0; 5890221167Sgnn break; 5891221167Sgnn case VXGE_HAL_VPATH_MAC_ADDR_DISCARD_DUPLICATE: 5892221167Sgnn i = 1; 5893221167Sgnn break; 5894221167Sgnn case VXGE_HAL_VPATH_MAC_ADDR_REPLACE_DUPLICATE: 5895221167Sgnn i = 2; 5896221167Sgnn break; 5897221167Sgnn default: 5898221167Sgnn i = 0; 5899221167Sgnn break; 5900221167Sgnn } 5901221167Sgnn 5902221167Sgnn data2 = VXGE_HAL_RTS_MGR_STEER_DATA1_DA_MAC_ADDR_MASK(data2) | 5903221167Sgnn VXGE_HAL_RTS_MGR_STEER_DATA1_DA_MAC_ADDR_MODE(i); 5904221167Sgnn 5905221167Sgnn status = __hal_mrpcim_rts_table_access(devh, 5906221167Sgnn VXGE_HAL_RTS_MGR_STEER_CTRL_WE_WRITE, 5907221167Sgnn VXGE_HAL_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_DA, 5908221167Sgnn offset, 5909221167Sgnn &data1, 5910221167Sgnn &data2, 5911221167Sgnn &vpath_vector); 5912221167Sgnn 5913221167Sgnn vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result: %d", 5914221167Sgnn __FILE__, __func__, __LINE__, status); 5915221167Sgnn 5916221167Sgnn return (status); 5917221167Sgnn} 5918221167Sgnn 5919221167Sgnn/* 5920221167Sgnn * vxge_hal_mrpcim_mac_addr_get - Read the mac address entry into 5921221167Sgnn * MAC address table. 5922221167Sgnn * @devh: Device handle. 5923221167Sgnn * @offset: Index into the DA table to execute the command on. 5924221167Sgnn * @macaddr: Buffer to return MAC address to be added for this vpath 5925221167Sgnn * into the list 5926221167Sgnn * @macaddr_mask: Buffer to return MAC address mask for macaddr 5927221167Sgnn * @vpath_vector: Buffer to return Bit mask specifying the vpaths 5928221167Sgnn * to which the mac address applies 5929221167Sgnn * 5930221167Sgnn * Reads the mac address, mac address mask and vpath vector from 5931221167Sgnn * the given offset 5932221167Sgnn * 5933221167Sgnn * see also: vxge_hal_mrpcim_mac_addr_add 5934221167Sgnn * 5935221167Sgnn */ 5936221167Sgnnvxge_hal_status_e 5937221167Sgnnvxge_hal_mrpcim_mac_addr_get( 5938221167Sgnn vxge_hal_device_h devh, 5939221167Sgnn u32 offset, 5940221167Sgnn macaddr_t macaddr, 5941221167Sgnn macaddr_t macaddr_mask, 5942221167Sgnn u64 *vpath_vector) 5943221167Sgnn{ 5944221167Sgnn u32 i; 5945221167Sgnn u64 data1 = 0ULL; 5946221167Sgnn u64 data2 = 0ULL; 5947221167Sgnn __hal_device_t *hldev; 5948221167Sgnn vxge_hal_status_e status = VXGE_HAL_OK; 5949221167Sgnn 5950221167Sgnn vxge_assert(devh != NULL); 5951221167Sgnn 5952221167Sgnn hldev = (__hal_device_t *) devh; 5953221167Sgnn 5954221167Sgnn vxge_hal_trace_log_mrpcim("==> %s:%s:%d", 5955221167Sgnn __FILE__, __func__, __LINE__); 5956221167Sgnn 5957221167Sgnn vxge_hal_trace_log_mrpcim("hldev = 0x"VXGE_OS_STXFMT, 5958221167Sgnn (ptr_t) hldev); 5959221167Sgnn 5960221167Sgnn status = __hal_mrpcim_rts_table_access(devh, 5961221167Sgnn VXGE_HAL_RTS_MGR_STEER_CTRL_WE_WRITE, 5962221167Sgnn VXGE_HAL_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_DA, 5963221167Sgnn offset, 5964221167Sgnn &data1, 5965221167Sgnn &data2, 5966221167Sgnn vpath_vector); 5967221167Sgnn 5968221167Sgnn if (status != VXGE_HAL_OK) { 5969221167Sgnn 5970221167Sgnn vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result: %d", 5971221167Sgnn __FILE__, __func__, __LINE__, status); 5972221167Sgnn return (status); 5973221167Sgnn } 5974221167Sgnn 5975221167Sgnn data1 = VXGE_HAL_RTS_MGR_STEER_DATA0_GET_DA_MAC_ADDR(data1); 5976221167Sgnn 5977221167Sgnn data2 = VXGE_HAL_RTS_MGR_STEER_DATA1_GET_DA_MAC_ADDR_MASK(data2); 5978221167Sgnn 5979221167Sgnn for (i = VXGE_HAL_ETH_ALEN; i > 0; i--) { 5980221167Sgnn macaddr[i - 1] = (u8) (data1 & 0xFF); 5981221167Sgnn data1 >>= 8; 5982221167Sgnn } 5983221167Sgnn 5984221167Sgnn for (i = VXGE_HAL_ETH_ALEN; i > 0; i--) { 5985221167Sgnn macaddr_mask[i - 1] = (u8) (data2 & 0xFF); 5986221167Sgnn data2 >>= 8; 5987221167Sgnn } 5988221167Sgnn 5989221167Sgnn vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result: %d", 5990221167Sgnn __FILE__, __func__, __LINE__, status); 5991221167Sgnn 5992221167Sgnn return (status); 5993221167Sgnn} 5994221167Sgnn 5995221167Sgnn/* 5996221167Sgnn * vxge_hal_mrpcim_strip_repl_vlan_tag_enable - Enable strip Repl vlan tag. 5997221167Sgnn * @devh: Device handle. 5998221167Sgnn * 5999221167Sgnn * Enable X3100 strip Repl vlan tag. 6000221167Sgnn * Returns: VXGE_HAL_OK on success. 6001221167Sgnn * 6002221167Sgnn */ 6003221167Sgnnvxge_hal_status_e 6004221167Sgnnvxge_hal_mrpcim_strip_repl_vlan_tag_enable( 6005221167Sgnn vxge_hal_device_h devh) 6006221167Sgnn{ 6007221167Sgnn u64 val64; 6008221167Sgnn __hal_device_t *hldev = (__hal_device_t *) devh; 6009221167Sgnn 6010221167Sgnn vxge_assert(hldev != NULL); 6011221167Sgnn 6012221167Sgnn vxge_hal_trace_log_mrpcim("==> %s:%s:%d", 6013221167Sgnn __FILE__, __func__, __LINE__); 6014221167Sgnn 6015221167Sgnn vxge_hal_trace_log_mrpcim("devh = 0x"VXGE_OS_STXFMT, 6016221167Sgnn (ptr_t) devh); 6017221167Sgnn 6018221167Sgnn if (!(hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM)) { 6019221167Sgnn vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = %d", 6020221167Sgnn __FILE__, __func__, __LINE__, 6021221167Sgnn VXGE_HAL_ERR_PRIVILAGED_OPEARATION); 6022221167Sgnn 6023221167Sgnn return (VXGE_HAL_ERR_PRIVILAGED_OPEARATION); 6024221167Sgnn } 6025221167Sgnn 6026221167Sgnn if (hldev->header.config.mrpcim_config.mac_config. 6027221167Sgnn rpa_repl_strip_vlan_tag == 6028221167Sgnn VXGE_HAL_MAC_RPA_REPL_STRIP_VLAN_TAG_ENABLE) { 6029221167Sgnn vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = 0", 6030221167Sgnn __FILE__, __func__, __LINE__); 6031221167Sgnn return (VXGE_HAL_OK); 6032221167Sgnn } 6033221167Sgnn 6034221167Sgnn val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 6035221167Sgnn hldev->header.regh0, 6036221167Sgnn &hldev->mrpcim_reg->rxmac_rx_pa_cfg1); 6037221167Sgnn 6038221167Sgnn val64 |= VXGE_HAL_RXMAC_RX_PA_CFG1_REPL_STRIP_VLAN_TAG; 6039221167Sgnn 6040221167Sgnn vxge_os_pio_mem_write64(hldev->header.pdev, 6041221167Sgnn hldev->header.regh0, 6042221167Sgnn val64, 6043221167Sgnn &hldev->mrpcim_reg->rxmac_rx_pa_cfg1); 6044221167Sgnn 6045221167Sgnn hldev->header.config.mrpcim_config.mac_config.rpa_repl_strip_vlan_tag = 6046221167Sgnn VXGE_HAL_MAC_RPA_REPL_STRIP_VLAN_TAG_ENABLE; 6047221167Sgnn 6048221167Sgnn vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = 0", 6049221167Sgnn __FILE__, __func__, __LINE__); 6050221167Sgnn 6051221167Sgnn return (VXGE_HAL_OK); 6052221167Sgnn} 6053221167Sgnn 6054221167Sgnn/* 6055221167Sgnn * vxge_hal_mrpcim_strip_repl_vlan_tag_disable - Disable strip Repl vlan tag. 6056221167Sgnn * @devh: Device handle. 6057221167Sgnn * 6058221167Sgnn * Disable X3100 strip Repl vlan tag. 6059221167Sgnn * Returns: VXGE_HAL_OK on success. 6060221167Sgnn * 6061221167Sgnn */ 6062221167Sgnnvxge_hal_status_e 6063221167Sgnnvxge_hal_mrpcim_strip_repl_vlan_tag_disable( 6064221167Sgnn vxge_hal_device_h devh) 6065221167Sgnn{ 6066221167Sgnn u64 val64; 6067221167Sgnn __hal_device_t *hldev = (__hal_device_t *) devh; 6068221167Sgnn 6069221167Sgnn vxge_assert(hldev != NULL); 6070221167Sgnn 6071221167Sgnn vxge_hal_trace_log_mrpcim("==> %s:%s:%d", 6072221167Sgnn __FILE__, __func__, __LINE__); 6073221167Sgnn 6074221167Sgnn vxge_hal_trace_log_mrpcim("devh = 0x"VXGE_OS_STXFMT, 6075221167Sgnn (ptr_t) devh); 6076221167Sgnn 6077221167Sgnn if (!(hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM)) { 6078221167Sgnn vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = %d", 6079221167Sgnn __FILE__, __func__, __LINE__, 6080221167Sgnn VXGE_HAL_ERR_PRIVILAGED_OPEARATION); 6081221167Sgnn 6082221167Sgnn return (VXGE_HAL_ERR_PRIVILAGED_OPEARATION); 6083221167Sgnn } 6084221167Sgnn 6085221167Sgnn if (hldev->header.config.mrpcim_config.mac_config. 6086221167Sgnn rpa_repl_strip_vlan_tag == 6087221167Sgnn VXGE_HAL_MAC_RPA_REPL_STRIP_VLAN_TAG_DISABLE) { 6088221167Sgnn vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = 0", 6089221167Sgnn __FILE__, __func__, __LINE__); 6090221167Sgnn return (VXGE_HAL_OK); 6091221167Sgnn } 6092221167Sgnn 6093221167Sgnn val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 6094221167Sgnn hldev->header.regh0, 6095221167Sgnn &hldev->mrpcim_reg->rxmac_rx_pa_cfg1); 6096221167Sgnn 6097221167Sgnn val64 &= ~VXGE_HAL_RXMAC_RX_PA_CFG1_REPL_STRIP_VLAN_TAG; 6098221167Sgnn 6099221167Sgnn vxge_os_pio_mem_write64(hldev->header.pdev, 6100221167Sgnn hldev->header.regh0, 6101221167Sgnn val64, 6102221167Sgnn &hldev->mrpcim_reg->rxmac_rx_pa_cfg1); 6103221167Sgnn 6104221167Sgnn hldev->header.config.mrpcim_config.mac_config.rpa_repl_strip_vlan_tag = 6105221167Sgnn VXGE_HAL_MAC_RPA_REPL_STRIP_VLAN_TAG_DISABLE; 6106221167Sgnn 6107221167Sgnn vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = 0", 6108221167Sgnn __FILE__, __func__, __LINE__); 6109221167Sgnn 6110221167Sgnn return (VXGE_HAL_OK); 6111221167Sgnn} 6112221167Sgnn 6113221167Sgnn/* 6114221167Sgnn * vxge_hal_mrpcim_lag_config_get - Get the LAG config. 6115221167Sgnn * @devh: Device handle. 6116221167Sgnn * @lconfig: LAG Configuration 6117221167Sgnn * 6118221167Sgnn * Returns the current LAG configuration. 6119221167Sgnn * Returns: VXGE_HAL_OK on success. 6120221167Sgnn * 6121221167Sgnn */ 6122221167Sgnnvxge_hal_status_e 6123221167Sgnnvxge_hal_mrpcim_lag_config_get( 6124221167Sgnn vxge_hal_device_h devh, 6125221167Sgnn vxge_hal_lag_config_t *lconfig) 6126221167Sgnn{ 6127221167Sgnn __hal_device_t *hldev = (__hal_device_t *) devh; 6128221167Sgnn 6129221167Sgnn vxge_assert(hldev != NULL); 6130221167Sgnn 6131221167Sgnn vxge_hal_trace_log_mrpcim("==> %s:%s:%d", 6132221167Sgnn __FILE__, __func__, __LINE__); 6133221167Sgnn 6134221167Sgnn vxge_hal_trace_log_mrpcim( 6135221167Sgnn "devh = 0x"VXGE_OS_STXFMT", lconfig = 0x"VXGE_OS_STXFMT, 6136221167Sgnn (ptr_t) devh, (ptr_t) lconfig); 6137221167Sgnn 6138221167Sgnn if (!(hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM)) { 6139221167Sgnn vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = %d", 6140221167Sgnn __FILE__, __func__, __LINE__, 6141221167Sgnn VXGE_HAL_ERR_PRIVILAGED_OPEARATION); 6142221167Sgnn 6143221167Sgnn return (VXGE_HAL_ERR_PRIVILAGED_OPEARATION); 6144221167Sgnn } 6145221167Sgnn 6146221167Sgnn vxge_os_memcpy(lconfig, 6147221167Sgnn &hldev->header.config.mrpcim_config.lag_config, 6148221167Sgnn sizeof(vxge_hal_lag_config_t)); 6149221167Sgnn 6150221167Sgnn vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = 0", 6151221167Sgnn __FILE__, __func__, __LINE__); 6152221167Sgnn 6153221167Sgnn return (VXGE_HAL_OK); 6154221167Sgnn} 6155221167Sgnn 6156221167Sgnn/* 6157221167Sgnn * vxge_hal_mrpcim_lag_config_set - Set the LAG config. 6158221167Sgnn * @devh: Device handle. 6159221167Sgnn * @lconfig: LAG Configuration 6160221167Sgnn * 6161221167Sgnn * Sets the LAG configuration. 6162221167Sgnn * Returns: VXGE_HAL_OK on success. 6163221167Sgnn * 6164221167Sgnn */ 6165221167Sgnnvxge_hal_status_e 6166221167Sgnnvxge_hal_mrpcim_lag_config_set( 6167221167Sgnn vxge_hal_device_h devh, 6168221167Sgnn vxge_hal_lag_config_t *lconfig) 6169221167Sgnn{ 6170221167Sgnn vxge_hal_status_e status; 6171221167Sgnn __hal_device_t *hldev = (__hal_device_t *) devh; 6172221167Sgnn 6173221167Sgnn vxge_assert(hldev != NULL); 6174221167Sgnn 6175221167Sgnn vxge_hal_trace_log_mrpcim("==> %s:%s:%d", 6176221167Sgnn __FILE__, __func__, __LINE__); 6177221167Sgnn 6178221167Sgnn vxge_hal_trace_log_mrpcim( 6179221167Sgnn "devh = 0x"VXGE_OS_STXFMT", lconfig = 0x"VXGE_OS_STXFMT, 6180221167Sgnn (ptr_t) devh, (ptr_t) lconfig); 6181221167Sgnn 6182221167Sgnn if (!(hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM)) { 6183221167Sgnn vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = %d", 6184221167Sgnn __FILE__, __func__, __LINE__, 6185221167Sgnn VXGE_HAL_ERR_PRIVILAGED_OPEARATION); 6186221167Sgnn 6187221167Sgnn return (VXGE_HAL_ERR_PRIVILAGED_OPEARATION); 6188221167Sgnn } 6189221167Sgnn 6190221167Sgnn status = __hal_device_lag_config_check(lconfig); 6191221167Sgnn 6192221167Sgnn if (status != VXGE_HAL_OK) { 6193221167Sgnn vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = %d", 6194221167Sgnn __FILE__, __func__, __LINE__, status); 6195221167Sgnn return (status); 6196221167Sgnn } 6197221167Sgnn 6198221167Sgnn vxge_os_memcpy(&hldev->header.config.mrpcim_config.lag_config, 6199221167Sgnn lconfig, 6200221167Sgnn sizeof(vxge_hal_lag_config_t)); 6201221167Sgnn 6202221167Sgnn status = __hal_mrpcim_lag_configure(hldev); 6203221167Sgnn 6204221167Sgnn if (status != VXGE_HAL_OK) { 6205221167Sgnn vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = %d", 6206221167Sgnn __FILE__, __func__, __LINE__, status); 6207221167Sgnn return (status); 6208221167Sgnn } 6209221167Sgnn 6210221167Sgnn vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = 0", 6211221167Sgnn __FILE__, __func__, __LINE__); 6212221167Sgnn 6213221167Sgnn return (VXGE_HAL_OK); 6214221167Sgnn} 6215221167Sgnn 6216221167Sgnn/* 6217221167Sgnn * vxge_hal_mrpcim_getpause_data -Pause frame frame generation and reception. 6218221167Sgnn * @devh: HAL device handle. 6219221167Sgnn * @port : Port number 0, 1, or 2 6220221167Sgnn * @tx : A field to return the pause generation capability of the NIC. 6221221167Sgnn * @rx : A field to return the pause reception capability of the NIC. 6222221167Sgnn * 6223221167Sgnn * Returns the Pause frame generation and reception capability of the NIC. 6224221167Sgnn * Return value: 6225221167Sgnn * status 6226221167Sgnn */ 6227221167Sgnnvxge_hal_status_e 6228221167Sgnnvxge_hal_mrpcim_getpause_data( 6229221167Sgnn vxge_hal_device_h devh, 6230221167Sgnn u32 port, 6231221167Sgnn u32 *tx, 6232221167Sgnn u32 *rx) 6233221167Sgnn{ 6234221167Sgnn u64 val64; 6235221167Sgnn __hal_device_t *hldev = (__hal_device_t *) devh; 6236221167Sgnn 6237221167Sgnn vxge_assert(devh != NULL); 6238221167Sgnn 6239221167Sgnn vxge_hal_trace_log_mrpcim("==> %s:%s:%d", 6240221167Sgnn __FILE__, __func__, __LINE__); 6241221167Sgnn 6242221167Sgnn vxge_hal_trace_log_mrpcim( 6243221167Sgnn "devh = 0x"VXGE_OS_STXFMT", port = %d, tx = 0x"VXGE_OS_STXFMT", " 6244221167Sgnn "rx = 0x"VXGE_OS_STXFMT, (ptr_t) devh, port, (ptr_t) tx, 6245221167Sgnn (ptr_t) rx); 6246221167Sgnn 6247221167Sgnn if (hldev->header.magic != VXGE_HAL_DEVICE_MAGIC) { 6248221167Sgnn vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result: %d", 6249221167Sgnn __FILE__, __func__, __LINE__, VXGE_HAL_ERR_INVALID_DEVICE); 6250221167Sgnn return (VXGE_HAL_ERR_INVALID_DEVICE); 6251221167Sgnn } 6252221167Sgnn 6253221167Sgnn if (port >= VXGE_HAL_MAC_MAX_PORTS) { 6254221167Sgnn vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result: %d", 6255221167Sgnn __FILE__, __func__, __LINE__, VXGE_HAL_ERR_INVALID_PORT); 6256221167Sgnn return (VXGE_HAL_ERR_INVALID_PORT); 6257221167Sgnn } 6258221167Sgnn 6259221167Sgnn if (!(hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM)) { 6260221167Sgnn vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result: %d", 6261221167Sgnn __FILE__, __func__, __LINE__, 6262221167Sgnn VXGE_HAL_ERR_PRIVILAGED_OPEARATION); 6263221167Sgnn return (VXGE_HAL_ERR_PRIVILAGED_OPEARATION); 6264221167Sgnn } 6265221167Sgnn 6266221167Sgnn val64 = vxge_os_pio_mem_read64(hldev->header.pdev, hldev->header.regh0, 6267221167Sgnn &hldev->mrpcim_reg->rxmac_pause_cfg_port[port]); 6268221167Sgnn 6269221167Sgnn if (val64 & VXGE_HAL_RXMAC_PAUSE_CFG_PORT_GEN_EN) 6270221167Sgnn *tx = 1; 6271221167Sgnn 6272221167Sgnn if (val64 & VXGE_HAL_RXMAC_PAUSE_CFG_PORT_RCV_EN) 6273221167Sgnn *rx = 1; 6274221167Sgnn 6275221167Sgnn 6276221167Sgnn vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result: 0", 6277221167Sgnn __FILE__, __func__, __LINE__); 6278221167Sgnn 6279221167Sgnn return (VXGE_HAL_OK); 6280221167Sgnn} 6281221167Sgnn 6282221167Sgnn/* 6283221167Sgnn * vxge_hal_mrpcim_setpause_data - set/reset pause frame generation. 6284221167Sgnn * @devh: HAL device handle. 6285221167Sgnn * @port : Port number 0, 1, or 2 6286221167Sgnn * @tx: A field that indicates the pause generation capability to be 6287221167Sgnn * set on the NIC. 6288221167Sgnn * @rx: A field that indicates the pause reception capability to be 6289221167Sgnn * set on the NIC. 6290221167Sgnn * 6291221167Sgnn * It can be used to set or reset Pause frame generation or reception 6292221167Sgnn * support of the NIC. 6293221167Sgnn * Return value: 6294221167Sgnn * int, returns 0 on Success 6295221167Sgnn */ 6296221167Sgnn 6297221167Sgnnvxge_hal_status_e 6298221167Sgnnvxge_hal_mrpcim_setpause_data( 6299221167Sgnn vxge_hal_device_h devh, 6300221167Sgnn u32 port, 6301221167Sgnn u32 tx, 6302221167Sgnn u32 rx) 6303221167Sgnn{ 6304221167Sgnn u64 val64; 6305221167Sgnn __hal_device_t *hldev = (__hal_device_t *) devh; 6306221167Sgnn 6307221167Sgnn vxge_assert(devh != NULL); 6308221167Sgnn 6309221167Sgnn vxge_hal_trace_log_mrpcim("==> %s:%s:%d", 6310221167Sgnn __FILE__, __func__, __LINE__); 6311221167Sgnn 6312221167Sgnn vxge_hal_trace_log_mrpcim( 6313221167Sgnn "devh = 0x"VXGE_OS_STXFMT", port = %d, tx = %d, rx = %d", 6314221167Sgnn (ptr_t) devh, port, tx, rx); 6315221167Sgnn 6316221167Sgnn if (hldev->header.magic != VXGE_HAL_DEVICE_MAGIC) { 6317221167Sgnn vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result: %d", 6318221167Sgnn __FILE__, __func__, __LINE__, VXGE_HAL_ERR_INVALID_DEVICE); 6319221167Sgnn return (VXGE_HAL_ERR_INVALID_DEVICE); 6320221167Sgnn } 6321221167Sgnn 6322221167Sgnn if (port >= VXGE_HAL_MAC_MAX_PORTS) { 6323221167Sgnn vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result: %d", 6324221167Sgnn __FILE__, __func__, __LINE__, VXGE_HAL_ERR_INVALID_PORT); 6325221167Sgnn return (VXGE_HAL_ERR_INVALID_PORT); 6326221167Sgnn } 6327221167Sgnn 6328221167Sgnn if (!(hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM)) { 6329221167Sgnn vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result: %d", 6330221167Sgnn __FILE__, __func__, __LINE__, 6331221167Sgnn VXGE_HAL_ERR_PRIVILAGED_OPEARATION); 6332221167Sgnn return (VXGE_HAL_ERR_PRIVILAGED_OPEARATION); 6333221167Sgnn } 6334221167Sgnn 6335221167Sgnn val64 = vxge_os_pio_mem_read64(hldev->header.pdev, hldev->header.regh0, 6336221167Sgnn &hldev->mrpcim_reg->rxmac_pause_cfg_port[port]); 6337221167Sgnn if (tx) 6338221167Sgnn val64 |= VXGE_HAL_RXMAC_PAUSE_CFG_PORT_GEN_EN; 6339221167Sgnn else 6340221167Sgnn val64 &= ~VXGE_HAL_RXMAC_PAUSE_CFG_PORT_GEN_EN; 6341221167Sgnn if (rx) 6342221167Sgnn val64 |= VXGE_HAL_RXMAC_PAUSE_CFG_PORT_RCV_EN; 6343221167Sgnn else 6344221167Sgnn val64 &= ~VXGE_HAL_RXMAC_PAUSE_CFG_PORT_RCV_EN; 6345221167Sgnn 6346221167Sgnn vxge_os_pio_mem_write64(hldev->header.pdev, hldev->header.regh0, 6347221167Sgnn val64, &hldev->mrpcim_reg->rxmac_pause_cfg_port[port]); 6348221167Sgnn 6349221167Sgnn vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result: 0", 6350221167Sgnn __FILE__, __func__, __LINE__); 6351221167Sgnn return (VXGE_HAL_OK); 6352221167Sgnn} 6353221167Sgnn 6354221167Sgnn/* 6355221167Sgnn * vxge_hal_mrpcim_bist_test - invokes the MemBist test of the card . 6356221167Sgnn * @devh: HAL device handle. 6357221167Sgnn * vxge_nic structure. 6358221167Sgnn * @data:variable that returns the result of each of the test conducted by 6359221167Sgnn * the driver. 6360221167Sgnn * 6361221167Sgnn * This invokes the MemBist test of the card. We give around 6362221167Sgnn * 2 secs time for the Test to complete. If it's still not complete 6363221167Sgnn * within this peiod, we consider that the test failed. 6364221167Sgnn * Return value: 6365221167Sgnn * 0 on success and -1 on failure. 6366221167Sgnn */ 6367221167Sgnnvxge_hal_status_e 6368221167Sgnnvxge_hal_mrpcim_bist_test(vxge_hal_device_h devh, u64 *data) 6369221167Sgnn{ 6370221167Sgnn __hal_device_t *hldev = (__hal_device_t *) devh; 6371221167Sgnn u8 bist = 0; 6372221167Sgnn int retry = 0; 6373221167Sgnn vxge_hal_status_e status = VXGE_HAL_FAIL; 6374221167Sgnn 6375221167Sgnn vxge_assert(devh != NULL); 6376221167Sgnn 6377221167Sgnn vxge_hal_trace_log_mrpcim("==> %s:%s:%d", 6378221167Sgnn __FILE__, __func__, __LINE__); 6379221167Sgnn 6380221167Sgnn vxge_hal_trace_log_mrpcim("devh = 0x"VXGE_OS_STXFMT, 6381221167Sgnn (ptr_t)devh); 6382221167Sgnn 6383221167Sgnn if (hldev->header.magic != VXGE_HAL_DEVICE_MAGIC) { 6384221167Sgnn vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result: %d", 6385221167Sgnn __FILE__, __func__, __LINE__, VXGE_HAL_ERR_INVALID_DEVICE); 6386221167Sgnn return (VXGE_HAL_ERR_INVALID_DEVICE); 6387221167Sgnn } 6388221167Sgnn 6389221167Sgnn if (!(hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM)) { 6390221167Sgnn vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result: %d", 6391221167Sgnn __FILE__, __func__, __LINE__, 6392221167Sgnn VXGE_HAL_ERR_PRIVILAGED_OPEARATION); 6393221167Sgnn return (VXGE_HAL_ERR_PRIVILAGED_OPEARATION); 6394221167Sgnn } 6395221167Sgnn 6396221167Sgnn (void) __hal_vpath_pci_read(hldev, 6397221167Sgnn hldev->first_vp_id, 6398221167Sgnn vxge_offsetof(vxge_hal_pci_config_le_t, bist), 6399221167Sgnn 1, 6400221167Sgnn &bist); 6401221167Sgnn bist |= 0x40; 6402221167Sgnn vxge_os_pci_write8(hldev->header.pdev, hldev->header.cfgh, 6403221167Sgnn vxge_offsetof(vxge_hal_pci_config_le_t, bist), bist); 6404221167Sgnn 6405221167Sgnn while (retry < 20) { 6406221167Sgnn (void) __hal_vpath_pci_read(hldev, 6407221167Sgnn hldev->first_vp_id, 6408221167Sgnn vxge_offsetof(vxge_hal_pci_config_le_t, bist), 6409221167Sgnn 1, 6410221167Sgnn &bist); 6411221167Sgnn if (!(bist & 0x40)) { 6412221167Sgnn *data = (bist & 0x0f); 6413221167Sgnn status = VXGE_HAL_OK; 6414221167Sgnn break; 6415221167Sgnn } 6416221167Sgnn vxge_os_mdelay(100); 6417221167Sgnn retry++; 6418221167Sgnn } 6419221167Sgnn 6420221167Sgnn vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result: %d", 6421221167Sgnn __FILE__, __func__, __LINE__, status); 6422221167Sgnn return (status); 6423221167Sgnn} 6424221167Sgnn 6425221167Sgnn/* 6426221167Sgnn * __hal_mrpcim_initialize - Initialize mrpcim 6427221167Sgnn * @hldev: hal device. 6428221167Sgnn * 6429221167Sgnn * Initializes mrpcim 6430221167Sgnn * 6431221167Sgnn * See also: __hal_mrpcim_terminate() 6432221167Sgnn */ 6433221167Sgnnvxge_hal_status_e 6434221167Sgnn__hal_mrpcim_initialize(__hal_device_t *hldev) 6435221167Sgnn{ 6436221167Sgnn u64 val64; 6437221167Sgnn vxge_hal_status_e status = VXGE_HAL_OK; 6438221167Sgnn 6439221167Sgnn vxge_assert(hldev != NULL); 6440221167Sgnn 6441221167Sgnn vxge_hal_trace_log_mrpcim("==> %s:%s:%d", 6442221167Sgnn __FILE__, __func__, __LINE__); 6443221167Sgnn 6444221167Sgnn vxge_hal_trace_log_mrpcim("hldev = 0x"VXGE_OS_STXFMT, 6445221167Sgnn (ptr_t)hldev); 6446221167Sgnn 6447221167Sgnn if (!(hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM)) { 6448221167Sgnn vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = %d", 6449221167Sgnn __FILE__, __func__, __LINE__, 6450221167Sgnn VXGE_HAL_ERR_PRIVILAGED_OPEARATION); 6451221167Sgnn return (VXGE_HAL_ERR_PRIVILAGED_OPEARATION); 6452221167Sgnn } 6453221167Sgnn 6454221167Sgnn hldev->mrpcim = (__hal_mrpcim_t *) 6455221167Sgnn vxge_os_malloc(hldev->header.pdev, sizeof(__hal_mrpcim_t)); 6456221167Sgnn 6457221167Sgnn if (hldev->mrpcim == NULL) { 6458221167Sgnn vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = %d", 6459221167Sgnn __FILE__, __func__, __LINE__, VXGE_HAL_ERR_OUT_OF_MEMORY); 6460221167Sgnn return (VXGE_HAL_ERR_OUT_OF_MEMORY); 6461221167Sgnn } 6462221167Sgnn 6463221167Sgnn vxge_os_memzero(hldev->mrpcim, sizeof(__hal_mrpcim_t)); 6464221167Sgnn 6465221167Sgnn __hal_mrpcim_get_vpd_data(hldev); 6466221167Sgnn 6467221167Sgnn hldev->mrpcim->mrpcim_stats_block = 6468221167Sgnn __hal_blockpool_block_allocate(hldev, VXGE_OS_HOST_PAGE_SIZE); 6469221167Sgnn 6470221167Sgnn if (hldev->mrpcim->mrpcim_stats_block == NULL) { 6471221167Sgnn 6472221167Sgnn vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = %d", 6473221167Sgnn __FILE__, __func__, __LINE__, VXGE_HAL_ERR_OUT_OF_MEMORY); 6474221167Sgnn 6475221167Sgnn return (VXGE_HAL_ERR_OUT_OF_MEMORY); 6476221167Sgnn 6477221167Sgnn } 6478221167Sgnn 6479221167Sgnn hldev->mrpcim->mrpcim_stats = (vxge_hal_mrpcim_stats_hw_info_t *) 6480221167Sgnn hldev->mrpcim->mrpcim_stats_block->memblock; 6481221167Sgnn 6482221167Sgnn vxge_os_memzero(hldev->mrpcim->mrpcim_stats, 6483221167Sgnn sizeof(vxge_hal_mrpcim_stats_hw_info_t)); 6484221167Sgnn 6485221167Sgnn vxge_os_memzero(&hldev->mrpcim->mrpcim_stats_sav, 6486221167Sgnn sizeof(vxge_hal_mrpcim_stats_hw_info_t)); 6487221167Sgnn 6488221167Sgnn status = __hal_mrpcim_mac_configure(hldev); 6489221167Sgnn 6490221167Sgnn if (status != VXGE_HAL_OK) { 6491221167Sgnn vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = %d", 6492221167Sgnn __FILE__, __func__, __LINE__, status); 6493221167Sgnn return (status); 6494221167Sgnn } 6495221167Sgnn 6496221167Sgnn status = __hal_mrpcim_lag_configure(hldev); 6497221167Sgnn 6498221167Sgnn if (status != VXGE_HAL_OK) { 6499221167Sgnn vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = %d", 6500221167Sgnn __FILE__, __func__, __LINE__, status); 6501221167Sgnn return (status); 6502221167Sgnn } 6503221167Sgnn 6504221167Sgnn val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 6505221167Sgnn hldev->header.regh0, 6506221167Sgnn &hldev->mrpcim_reg->mdio_gen_cfg_port[0]); 6507221167Sgnn 6508221167Sgnn hldev->mrpcim->mdio_phy_prtad0 = 6509221167Sgnn (u32) VXGE_HAL_MDIO_GEN_CFG_PORT_GET_MDIO_PHY_PRTAD(val64); 6510221167Sgnn 6511221167Sgnn val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 6512221167Sgnn hldev->header.regh0, 6513221167Sgnn &hldev->mrpcim_reg->mdio_gen_cfg_port[1]); 6514221167Sgnn 6515221167Sgnn hldev->mrpcim->mdio_phy_prtad1 = 6516221167Sgnn (u32) VXGE_HAL_MDIO_GEN_CFG_PORT_GET_MDIO_PHY_PRTAD(val64); 6517221167Sgnn 6518221167Sgnn val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 6519221167Sgnn hldev->header.regh0, 6520221167Sgnn &hldev->mrpcim_reg->xgxs_static_cfg_port[0]); 6521221167Sgnn 6522221167Sgnn hldev->mrpcim->mdio_dte_prtad0 = 6523221167Sgnn (u32) VXGE_HAL_XGXS_STATIC_CFG_PORT_GET_MDIO_DTE_PRTAD(val64); 6524221167Sgnn 6525221167Sgnn val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 6526221167Sgnn hldev->header.regh0, 6527221167Sgnn &hldev->mrpcim_reg->xgxs_static_cfg_port[1]); 6528221167Sgnn 6529221167Sgnn hldev->mrpcim->mdio_dte_prtad1 = 6530221167Sgnn (u32) VXGE_HAL_XGXS_STATIC_CFG_PORT_GET_MDIO_DTE_PRTAD(val64); 6531221167Sgnn 6532221167Sgnn vxge_os_pio_mem_write64(hldev->header.pdev, 6533221167Sgnn hldev->header.regh0, 6534221167Sgnn hldev->mrpcim->mrpcim_stats_block->dma_addr, 6535221167Sgnn &hldev->mrpcim_reg->mrpcim_stats_start_host_addr); 6536221167Sgnn 6537221167Sgnn val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 6538221167Sgnn hldev->header.regh0, 6539221167Sgnn &hldev->mrpcim_reg->mrpcim_general_cfg2); 6540221167Sgnn 6541221167Sgnn val64 &= ~VXGE_HAL_MRPCIM_GENERAL_CFG2_MRPCIM_STATS_MAP_TO_VPATH(0x1f); 6542221167Sgnn val64 |= VXGE_HAL_MRPCIM_GENERAL_CFG2_MRPCIM_STATS_MAP_TO_VPATH( 6543221167Sgnn hldev->first_vp_id); 6544221167Sgnn 6545221167Sgnn vxge_os_pio_mem_write64(hldev->header.pdev, 6546221167Sgnn hldev->header.regh0, 6547221167Sgnn val64, 6548221167Sgnn &hldev->mrpcim_reg->mrpcim_general_cfg2); 6549221167Sgnn 6550221167Sgnn vxge_os_pio_mem_write64(hldev->header.pdev, 6551221167Sgnn hldev->header.regh0, 6552221167Sgnn vBIT(0xFFFFFFFFFFFFFFFFULL, 0, VXGE_HAL_MAX_VIRTUAL_PATHS), 6553221167Sgnn &hldev->mrpcim_reg->rxmac_authorize_all_addr); 6554221167Sgnn 6555221167Sgnn vxge_os_pio_mem_write64(hldev->header.pdev, 6556221167Sgnn hldev->header.regh0, 6557221167Sgnn vBIT(0xFFFFFFFFFFFFFFFFULL, 0, VXGE_HAL_MAX_VIRTUAL_PATHS), 6558221167Sgnn &hldev->mrpcim_reg->rxmac_authorize_all_vid); 6559221167Sgnn 6560221167Sgnn if (hldev->header.config.intr_mode == 6561221167Sgnn VXGE_HAL_INTR_MODE_EMULATED_INTA) { 6562221167Sgnn 6563221167Sgnn val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 6564221167Sgnn hldev->header.regh0, 6565221167Sgnn &hldev->mrpcim_reg->rdcrdtarb_cfg0); 6566221167Sgnn 6567221167Sgnn /* Set MOST to 8 for HP-ISS platform */ 6568221167Sgnn val64 &= ~VXGE_HAL_RDCRDTARB_CFG0_MAX_OUTSTANDING_RDS(0x3f); 6569221167Sgnn 6570221167Sgnn val64 |= VXGE_HAL_RDCRDTARB_CFG0_MAX_OUTSTANDING_RDS(8); 6571221167Sgnn 6572221167Sgnn vxge_os_pio_mem_write64(hldev->header.pdev, 6573221167Sgnn hldev->header.regh0, 6574221167Sgnn val64, 6575221167Sgnn &hldev->mrpcim_reg->rdcrdtarb_cfg0); 6576221167Sgnn } 6577221167Sgnn 6578221167Sgnn (void) __hal_ifmsg_wmsg_post(hldev, 6579221167Sgnn hldev->first_vp_id, 6580221167Sgnn VXGE_HAL_RTS_ACCESS_STEER_MSG_DEST_BROADCAST, 6581221167Sgnn VXGE_HAL_RTS_ACCESS_STEER_DATA0_MSG_TYPE_PRIV_DRIVER_UP, 6582221167Sgnn 0); 6583221167Sgnn 6584221167Sgnn vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = %d", 6585221167Sgnn __FILE__, __func__, __LINE__, status); 6586221167Sgnn return (status); 6587221167Sgnn 6588221167Sgnn} 6589221167Sgnn 6590221167Sgnn/* 6591221167Sgnn * __hal_mrpcim_terminate - Terminates mrpcim 6592221167Sgnn * @hldev: hal device. 6593221167Sgnn * 6594221167Sgnn * Terminates mrpcim. 6595221167Sgnn * 6596221167Sgnn * See also: __hal_mrpcim_initialize() 6597221167Sgnn */ 6598221167Sgnnvxge_hal_status_e 6599221167Sgnn__hal_mrpcim_terminate(__hal_device_t *hldev) 6600221167Sgnn{ 6601221167Sgnn vxge_hal_device_h devh = (vxge_hal_device_h) hldev; 6602221167Sgnn vxge_hal_status_e status = VXGE_HAL_OK; 6603221167Sgnn 6604221167Sgnn vxge_assert((hldev != NULL) && (hldev->mrpcim != NULL)); 6605221167Sgnn 6606221167Sgnn vxge_hal_trace_log_mrpcim("==> %s:%s:%d", 6607221167Sgnn __FILE__, __func__, __LINE__); 6608221167Sgnn 6609221167Sgnn vxge_hal_trace_log_mrpcim("hldev = 0x"VXGE_OS_STXFMT, 6610221167Sgnn (ptr_t) hldev); 6611221167Sgnn 6612221167Sgnn if (hldev->mrpcim == NULL) { 6613221167Sgnn vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = %d", 6614221167Sgnn __FILE__, __func__, __LINE__, status); 6615221167Sgnn return (status); 6616221167Sgnn } 6617221167Sgnn 6618221167Sgnn (void) __hal_ifmsg_wmsg_post(hldev, 6619221167Sgnn hldev->first_vp_id, 6620221167Sgnn VXGE_HAL_RTS_ACCESS_STEER_MSG_DEST_BROADCAST, 6621221167Sgnn VXGE_HAL_RTS_ACCESS_STEER_DATA0_MSG_TYPE_PRIV_DRIVER_DOWN, 6622221167Sgnn 0); 6623221167Sgnn 6624221167Sgnn if (hldev->mrpcim->mrpcim_stats_block != NULL) { 6625221167Sgnn __hal_blockpool_block_free(devh, 6626221167Sgnn hldev->mrpcim->mrpcim_stats_block); 6627221167Sgnn hldev->mrpcim->mrpcim_stats_block = NULL; 6628221167Sgnn } 6629221167Sgnn 6630221167Sgnn vxge_os_free(hldev->header.pdev, 6631221167Sgnn hldev->mrpcim, sizeof(__hal_mrpcim_t)); 6632221167Sgnn 6633221167Sgnn hldev->mrpcim = NULL; 6634221167Sgnn 6635221167Sgnn vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = %d", 6636221167Sgnn __FILE__, __func__, __LINE__, status); 6637221167Sgnn return (status); 6638221167Sgnn} 6639