1221167Sgnn/*- 2221167Sgnn * Copyright(c) 2002-2011 Exar Corp. 3221167Sgnn * All rights reserved. 4221167Sgnn * 5221167Sgnn * Redistribution and use in source and binary forms, with or without 6221167Sgnn * modification are permitted provided the following conditions are met: 7221167Sgnn * 8221167Sgnn * 1. Redistributions of source code must retain the above copyright notice, 9221167Sgnn * this list of conditions and the following disclaimer. 10221167Sgnn * 11221167Sgnn * 2. Redistributions in binary form must reproduce the above copyright 12221167Sgnn * notice, this list of conditions and the following disclaimer in the 13221167Sgnn * documentation and/or other materials provided with the distribution. 14221167Sgnn * 15221167Sgnn * 3. Neither the name of the Exar Corporation nor the names of its 16221167Sgnn * contributors may be used to endorse or promote products derived from 17221167Sgnn * this software without specific prior written permission. 18221167Sgnn * 19221167Sgnn * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20221167Sgnn * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21221167Sgnn * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22221167Sgnn * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 23221167Sgnn * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24221167Sgnn * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25221167Sgnn * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26221167Sgnn * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27221167Sgnn * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28221167Sgnn * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29221167Sgnn * POSSIBILITY OF SUCH DAMAGE. 30221167Sgnn */ 31221167Sgnn/*$FreeBSD$*/ 32221167Sgnn 33221167Sgnn#include <dev/vxge/vxgehal/vxgehal.h> 34221167Sgnn 35221167Sgnn/* 36221167Sgnn * vxge_hal_driver_config_check - Check driver configuration. 37221167Sgnn * @config: Driver configuration information 38221167Sgnn * 39221167Sgnn * Check the driver configuration 40221167Sgnn * 41221167Sgnn * Returns: VXGE_HAL_OK - success, 42221167Sgnn * otherwise one of the vxge_hal_status_e {} enumerated error codes. 43221167Sgnn * 44221167Sgnn */ 45221167Sgnnvxge_hal_status_e 46221167Sgnnvxge_hal_driver_config_check(vxge_hal_driver_config_t *config) 47221167Sgnn{ 48221167Sgnn if (config->level > VXGE_TRACE) 49221167Sgnn return (VXGE_HAL_BADCFG_LOG_LEVEL); 50221167Sgnn return (VXGE_HAL_OK); 51221167Sgnn} 52221167Sgnn 53221167Sgnn/* 54221167Sgnn * __hal_device_wire_port_config_check - Check wire port configuration. 55221167Sgnn * @port_config: Port configuration information 56221167Sgnn * 57221167Sgnn * Check wire port configuration 58221167Sgnn * 59221167Sgnn * Returns: VXGE_HAL_OK - success, 60221167Sgnn * otherwise one of the vxge_hal_status_e enumerated error codes. 61221167Sgnn * 62221167Sgnn */ 63221167Sgnnvxge_hal_status_e 64221167Sgnn__hal_device_wire_port_config_check(vxge_hal_wire_port_config_t *port_config) 65221167Sgnn{ 66221167Sgnn if (port_config->port_id > VXGE_HAL_WIRE_PORT_MAX_PORTS) 67221167Sgnn return (VXGE_HAL_BADCFG_WIRE_PORT_PORT_ID); 68221167Sgnn 69221167Sgnn if ((port_config->media > VXGE_HAL_WIRE_PORT_MAX_MEDIA) && 70221167Sgnn (port_config->media != VXGE_HAL_WIRE_PORT_MEDIA_DEFAULT)) 71221167Sgnn return (VXGE_HAL_BADCFG_WIRE_PORT_MAX_MEDIA); 72221167Sgnn 73221167Sgnn if (((port_config->mtu < VXGE_HAL_WIRE_PORT_MIN_INITIAL_MTU) || 74221167Sgnn (port_config->mtu > VXGE_HAL_WIRE_PORT_MAX_INITIAL_MTU)) && 75221167Sgnn (port_config->mtu != VXGE_HAL_WIRE_PORT_DEF_INITIAL_MTU)) 76221167Sgnn return (VXGE_HAL_BADCFG_WIRE_PORT_MAX_INITIAL_MTU); 77221167Sgnn 78221167Sgnn if ((port_config->autoneg_mode > 79221167Sgnn VXGE_HAL_WIRE_PORT_AUTONEG_MODE_RESERVED) && 80221167Sgnn (port_config->autoneg_mode != 81221167Sgnn VXGE_HAL_WIRE_PORT_AUTONEG_MODE_DEFAULT)) 82221167Sgnn return (VXGE_HAL_BADCFG_WIRE_PORT_AUTONEG_MODE); 83221167Sgnn 84221167Sgnn if ((port_config->autoneg_rate > 85221167Sgnn VXGE_HAL_WIRE_PORT_AUTONEG_RATE_10G) && 86221167Sgnn (port_config->autoneg_rate != 87221167Sgnn VXGE_HAL_WIRE_PORT_AUTONEG_RATE_DEFAULT)) 88221167Sgnn return (VXGE_HAL_BADCFG_WIRE_PORT_AUTONEG_RATE); 89221167Sgnn 90221167Sgnn if ((port_config->fixed_use_fsm != 91221167Sgnn VXGE_HAL_WIRE_PORT_FIXED_USE_FSM_PROCESSOR) && 92221167Sgnn (port_config->fixed_use_fsm != 93221167Sgnn VXGE_HAL_WIRE_PORT_FIXED_USE_FSM_HW) && 94221167Sgnn (port_config->fixed_use_fsm != 95221167Sgnn VXGE_HAL_WIRE_PORT_FIXED_USE_FSM_DEFAULT)) 96221167Sgnn return (VXGE_HAL_BADCFG_WIRE_PORT_FIXED_USE_FSM); 97221167Sgnn 98221167Sgnn if ((port_config->antp_use_fsm != 99221167Sgnn VXGE_HAL_WIRE_PORT_ANTP_USE_FSM_PROCESSOR) && 100221167Sgnn (port_config->antp_use_fsm != 101221167Sgnn VXGE_HAL_WIRE_PORT_ANTP_USE_FSM_HW) && 102221167Sgnn (port_config->antp_use_fsm != 103221167Sgnn VXGE_HAL_WIRE_PORT_ANTP_USE_FSM_DEFAULT)) 104221167Sgnn return (VXGE_HAL_BADCFG_WIRE_PORT_ANTP_USE_FSM); 105221167Sgnn 106221167Sgnn if ((port_config->anbe_use_fsm != 107221167Sgnn VXGE_HAL_WIRE_PORT_ANBE_USE_FSM_PROCESSOR) && 108221167Sgnn (port_config->anbe_use_fsm != 109221167Sgnn VXGE_HAL_WIRE_PORT_ANBE_USE_FSM_HW) && 110221167Sgnn (port_config->anbe_use_fsm != 111221167Sgnn VXGE_HAL_WIRE_PORT_ANBE_USE_FSM_DEFAULT)) 112221167Sgnn return (VXGE_HAL_BADCFG_WIRE_PORT_ANBE_USE_FSM); 113221167Sgnn 114221167Sgnn if ((port_config->link_stability_period > 115221167Sgnn VXGE_HAL_WIRE_PORT_MAX_LINK_STABILITY_PERIOD) && 116221167Sgnn (port_config->link_stability_period != 117221167Sgnn VXGE_HAL_WIRE_PORT_DEF_LINK_STABILITY_PERIOD)) 118221167Sgnn return (VXGE_HAL_BADCFG_WIRE_PORT_LINK_STABILITY_PERIOD); 119221167Sgnn 120221167Sgnn if ((port_config->port_stability_period > 121221167Sgnn VXGE_HAL_WIRE_PORT_MAX_PORT_STABILITY_PERIOD) && 122221167Sgnn (port_config->port_stability_period != 123221167Sgnn VXGE_HAL_WIRE_PORT_DEF_PORT_STABILITY_PERIOD)) 124221167Sgnn return (VXGE_HAL_BADCFG_WIRE_PORT_PORT_STABILITY_PERIOD); 125221167Sgnn 126221167Sgnn if ((port_config->tmac_en != VXGE_HAL_WIRE_PORT_TMAC_ENABLE) && 127221167Sgnn (port_config->tmac_en != VXGE_HAL_WIRE_PORT_TMAC_DISABLE) && 128221167Sgnn (port_config->tmac_en != VXGE_HAL_WIRE_PORT_TMAC_DEFAULT)) 129221167Sgnn return (VXGE_HAL_BADCFG_WIRE_PORT_TMAC_EN); 130221167Sgnn 131221167Sgnn if ((port_config->rmac_en != VXGE_HAL_WIRE_PORT_RMAC_ENABLE) && 132221167Sgnn (port_config->rmac_en != VXGE_HAL_WIRE_PORT_RMAC_DISABLE) && 133221167Sgnn (port_config->rmac_en != VXGE_HAL_WIRE_PORT_RMAC_DEFAULT)) 134221167Sgnn return (VXGE_HAL_BADCFG_WIRE_PORT_RMAC_EN); 135221167Sgnn 136221167Sgnn if ((port_config->tmac_pad != VXGE_HAL_WIRE_PORT_TMAC_NO_PAD) && 137221167Sgnn (port_config->tmac_pad != VXGE_HAL_WIRE_PORT_TMAC_64B_PAD) && 138221167Sgnn (port_config->tmac_pad != VXGE_HAL_WIRE_PORT_TMAC_PAD_DEFAULT)) 139221167Sgnn return (VXGE_HAL_BADCFG_WIRE_PORT_TMAC_PAD); 140221167Sgnn 141221167Sgnn if ((port_config->tmac_pad_byte > 142221167Sgnn VXGE_HAL_WIRE_PORT_MAX_TMAC_PAD_BYTE) && 143221167Sgnn (port_config->tmac_pad_byte != 144221167Sgnn VXGE_HAL_WIRE_PORT_DEF_TMAC_PAD_BYTE)) 145221167Sgnn return (VXGE_HAL_BADCFG_WIRE_PORT_TMAC_PAD_BYTE); 146221167Sgnn 147221167Sgnn if ((port_config->tmac_util_period > 148221167Sgnn VXGE_HAL_WIRE_PORT_MAX_TMAC_UTIL_PERIOD) && 149221167Sgnn (port_config->tmac_util_period != 150221167Sgnn VXGE_HAL_WIRE_PORT_DEF_TMAC_UTIL_PERIOD)) 151221167Sgnn return (VXGE_HAL_BADCFG_WIRE_PORT_TMAC_UTIL_PERIOD); 152221167Sgnn 153221167Sgnn if ((port_config->rmac_strip_fcs != 154221167Sgnn VXGE_HAL_WIRE_PORT_RMAC_STRIP_FCS) && 155221167Sgnn (port_config->rmac_strip_fcs != 156221167Sgnn VXGE_HAL_WIRE_PORT_RMAC_SEND_FCS_TO_HOST) && 157221167Sgnn (port_config->rmac_strip_fcs != 158221167Sgnn VXGE_HAL_WIRE_PORT_RMAC_STRIP_FCS_DEFAULT)) 159221167Sgnn return (VXGE_HAL_BADCFG_WIRE_PORT_RMAC_STRIP_FCS); 160221167Sgnn 161221167Sgnn if ((port_config->rmac_prom_en != 162221167Sgnn VXGE_HAL_WIRE_PORT_RMAC_PROM_EN_ENABLE) && 163221167Sgnn (port_config->rmac_prom_en != 164221167Sgnn VXGE_HAL_WIRE_PORT_RMAC_PROM_EN_DISABLE) && 165221167Sgnn (port_config->rmac_prom_en != 166221167Sgnn VXGE_HAL_WIRE_PORT_RMAC_PROM_EN_DEFAULT)) 167221167Sgnn return (VXGE_HAL_BADCFG_WIRE_PORT_RMAC_PROM_EN); 168221167Sgnn 169221167Sgnn if ((port_config->rmac_discard_pfrm != 170221167Sgnn VXGE_HAL_WIRE_PORT_RMAC_DISCARD_PFRM) && 171221167Sgnn (port_config->rmac_discard_pfrm != 172221167Sgnn VXGE_HAL_WIRE_PORT_RMAC_SEND_PFRM_TO_HOST) && 173221167Sgnn (port_config->rmac_discard_pfrm != 174221167Sgnn VXGE_HAL_WIRE_PORT_RMAC_DISCARD_PFRM_DEFAULT)) 175221167Sgnn return (VXGE_HAL_BADCFG_WIRE_PORT_RMAC_DISCARD_PFRM); 176221167Sgnn 177221167Sgnn if ((port_config->rmac_util_period > 178221167Sgnn VXGE_HAL_WIRE_PORT_MAX_RMAC_UTIL_PERIOD) && 179221167Sgnn (port_config->rmac_util_period != 180221167Sgnn VXGE_HAL_WIRE_PORT_DEF_RMAC_UTIL_PERIOD)) 181221167Sgnn return (VXGE_HAL_BADCFG_WIRE_PORT_RMAC_UTIL_PERIOD); 182221167Sgnn 183221167Sgnn if ((port_config->rmac_pause_gen_en != 184221167Sgnn VXGE_HAL_WIRE_PORT_RMAC_PAUSE_GEN_EN_ENABLE) && 185221167Sgnn (port_config->rmac_pause_gen_en != 186221167Sgnn VXGE_HAL_WIRE_PORT_RMAC_PAUSE_GEN_EN_DISABLE) && 187221167Sgnn (port_config->rmac_pause_gen_en != 188221167Sgnn VXGE_HAL_WIRE_PORT_RMAC_PAUSE_GEN_EN_DEFAULT)) 189221167Sgnn return (VXGE_HAL_BADCFG_WIRE_PORT_RMAC_PAUSE_GEN_EN); 190221167Sgnn 191221167Sgnn if ((port_config->rmac_pause_rcv_en != 192221167Sgnn VXGE_HAL_WIRE_PORT_RMAC_PAUSE_RCV_EN_ENABLE) && 193221167Sgnn (port_config->rmac_pause_rcv_en != 194221167Sgnn VXGE_HAL_WIRE_PORT_RMAC_PAUSE_RCV_EN_DISABLE) && 195221167Sgnn (port_config->rmac_pause_rcv_en != 196221167Sgnn VXGE_HAL_WIRE_PORT_RMAC_PAUSE_RCV_EN_DEFAULT)) 197221167Sgnn return (VXGE_HAL_BADCFG_WIRE_PORT_RMAC_PAUSE_RCV_EN); 198221167Sgnn 199221167Sgnn if (((port_config->rmac_pause_time < 200221167Sgnn VXGE_HAL_WIRE_PORT_MIN_RMAC_HIGH_PTIME) || 201221167Sgnn (port_config->rmac_pause_time > 202221167Sgnn VXGE_HAL_WIRE_PORT_MAX_RMAC_HIGH_PTIME)) && 203221167Sgnn (port_config->rmac_pause_time != 204221167Sgnn VXGE_HAL_WIRE_PORT_DEF_RMAC_HIGH_PTIME)) 205221167Sgnn return (VXGE_HAL_BADCFG_WIRE_PORT_RMAC_HIGH_PTIME); 206221167Sgnn 207221167Sgnn if ((port_config->limiter_en != 208221167Sgnn VXGE_HAL_WIRE_PORT_RMAC_PAUSE_LIMITER_ENABLE) && 209221167Sgnn (port_config->limiter_en != 210221167Sgnn VXGE_HAL_WIRE_PORT_RMAC_PAUSE_LIMITER_DISABLE) && 211221167Sgnn (port_config->limiter_en != 212221167Sgnn VXGE_HAL_WIRE_PORT_RMAC_PAUSE_LIMITER_DEFAULT)) 213221167Sgnn return (VXGE_HAL_BADCFG_WIRE_PORT_RMAC_PAUSE_LIMITER_EN); 214221167Sgnn 215221167Sgnn if ((port_config->max_limit > VXGE_HAL_WIRE_PORT_MAX_RMAC_MAX_LIMIT) && 216221167Sgnn (port_config->max_limit != VXGE_HAL_WIRE_PORT_DEF_RMAC_MAX_LIMIT)) 217221167Sgnn return (VXGE_HAL_BADCFG_WIRE_PORT_RMAC_MAX_LIMIT); 218221167Sgnn 219221167Sgnn return (VXGE_HAL_OK); 220221167Sgnn} 221221167Sgnn 222221167Sgnn 223221167Sgnn/* 224221167Sgnn * __hal_device_switch_port_config_check - Check switch port configuration. 225221167Sgnn * @port_config: Port configuration information 226221167Sgnn * 227221167Sgnn * Check switch port configuration 228221167Sgnn * 229221167Sgnn * Returns: VXGE_HAL_OK - success, 230221167Sgnn * otherwise one of the vxge_hal_status_e enumerated error codes. 231221167Sgnn * 232221167Sgnn */ 233221167Sgnnvxge_hal_status_e 234221167Sgnn__hal_device_switch_port_config_check( 235221167Sgnn vxge_hal_switch_port_config_t *port_config) 236221167Sgnn{ 237221167Sgnn if (((port_config->mtu < VXGE_HAL_SWITCH_PORT_MIN_INITIAL_MTU) || 238221167Sgnn (port_config->mtu > VXGE_HAL_SWITCH_PORT_MAX_INITIAL_MTU)) && 239221167Sgnn (port_config->mtu != VXGE_HAL_SWITCH_PORT_DEF_INITIAL_MTU)) 240221167Sgnn return (VXGE_HAL_BADCFG_SWITCH_PORT_MAX_INITIAL_MTU); 241221167Sgnn 242221167Sgnn if ((port_config->tmac_en != VXGE_HAL_SWITCH_PORT_TMAC_ENABLE) && 243221167Sgnn (port_config->tmac_en != VXGE_HAL_SWITCH_PORT_TMAC_DISABLE) && 244221167Sgnn (port_config->tmac_en != VXGE_HAL_SWITCH_PORT_TMAC_DEFAULT)) 245221167Sgnn return (VXGE_HAL_BADCFG_SWITCH_PORT_TMAC_EN); 246221167Sgnn 247221167Sgnn if ((port_config->rmac_en != VXGE_HAL_SWITCH_PORT_RMAC_ENABLE) && 248221167Sgnn (port_config->rmac_en != VXGE_HAL_SWITCH_PORT_RMAC_DISABLE) && 249221167Sgnn (port_config->rmac_en != VXGE_HAL_SWITCH_PORT_RMAC_DEFAULT)) 250221167Sgnn return (VXGE_HAL_BADCFG_SWITCH_PORT_RMAC_EN); 251221167Sgnn 252221167Sgnn if ((port_config->tmac_pad != VXGE_HAL_SWITCH_PORT_TMAC_NO_PAD) && 253221167Sgnn (port_config->tmac_pad != VXGE_HAL_SWITCH_PORT_TMAC_64B_PAD) && 254221167Sgnn (port_config->tmac_pad != VXGE_HAL_SWITCH_PORT_TMAC_PAD_DEFAULT)) 255221167Sgnn return (VXGE_HAL_BADCFG_SWITCH_PORT_TMAC_PAD); 256221167Sgnn 257221167Sgnn if ((port_config->tmac_pad_byte > 258221167Sgnn VXGE_HAL_SWITCH_PORT_MAX_TMAC_PAD_BYTE) && 259221167Sgnn (port_config->tmac_pad_byte != 260221167Sgnn VXGE_HAL_SWITCH_PORT_DEF_TMAC_PAD_BYTE)) 261221167Sgnn return (VXGE_HAL_BADCFG_SWITCH_PORT_TMAC_PAD_BYTE); 262221167Sgnn 263221167Sgnn if ((port_config->tmac_util_period > 264221167Sgnn VXGE_HAL_SWITCH_PORT_MAX_TMAC_UTIL_PERIOD) && 265221167Sgnn (port_config->tmac_util_period != 266221167Sgnn VXGE_HAL_SWITCH_PORT_DEF_TMAC_UTIL_PERIOD)) 267221167Sgnn return (VXGE_HAL_BADCFG_SWITCH_PORT_TMAC_UTIL_PERIOD); 268221167Sgnn 269221167Sgnn if ((port_config->rmac_strip_fcs != 270221167Sgnn VXGE_HAL_SWITCH_PORT_RMAC_STRIP_FCS) && 271221167Sgnn (port_config->rmac_strip_fcs != 272221167Sgnn VXGE_HAL_SWITCH_PORT_RMAC_SEND_FCS_TO_HOST) && 273221167Sgnn (port_config->rmac_strip_fcs != 274221167Sgnn VXGE_HAL_SWITCH_PORT_RMAC_STRIP_FCS_DEFAULT)) 275221167Sgnn return (VXGE_HAL_BADCFG_SWITCH_PORT_RMAC_STRIP_FCS); 276221167Sgnn 277221167Sgnn if ((port_config->rmac_prom_en != 278221167Sgnn VXGE_HAL_SWITCH_PORT_RMAC_PROM_EN_ENABLE) && 279221167Sgnn (port_config->rmac_prom_en != 280221167Sgnn VXGE_HAL_SWITCH_PORT_RMAC_PROM_EN_DISABLE) && 281221167Sgnn (port_config->rmac_prom_en != 282221167Sgnn VXGE_HAL_SWITCH_PORT_RMAC_PROM_EN_DEFAULT)) 283221167Sgnn return (VXGE_HAL_BADCFG_SWITCH_PORT_RMAC_PROM_EN); 284221167Sgnn 285221167Sgnn if ((port_config->rmac_discard_pfrm != 286221167Sgnn VXGE_HAL_SWITCH_PORT_RMAC_DISCARD_PFRM) && 287221167Sgnn (port_config->rmac_discard_pfrm != 288221167Sgnn VXGE_HAL_SWITCH_PORT_RMAC_SEND_PFRM_TO_HOST) && 289221167Sgnn (port_config->rmac_discard_pfrm != 290221167Sgnn VXGE_HAL_SWITCH_PORT_RMAC_DISCARD_PFRM_DEFAULT)) 291221167Sgnn return (VXGE_HAL_BADCFG_SWITCH_PORT_RMAC_DISCARD_PFRM); 292221167Sgnn 293221167Sgnn if ((port_config->rmac_util_period > 294221167Sgnn VXGE_HAL_SWITCH_PORT_MAX_RMAC_UTIL_PERIOD) && 295221167Sgnn (port_config->rmac_util_period != 296221167Sgnn VXGE_HAL_SWITCH_PORT_DEF_RMAC_UTIL_PERIOD)) 297221167Sgnn return (VXGE_HAL_BADCFG_SWITCH_PORT_RMAC_UTIL_PERIOD); 298221167Sgnn 299221167Sgnn if ((port_config->rmac_pause_gen_en != 300221167Sgnn VXGE_HAL_SWITCH_PORT_RMAC_PAUSE_GEN_EN_ENABLE) && 301221167Sgnn (port_config->rmac_pause_gen_en != 302221167Sgnn VXGE_HAL_SWITCH_PORT_RMAC_PAUSE_GEN_EN_DISABLE) && 303221167Sgnn (port_config->rmac_pause_gen_en != 304221167Sgnn VXGE_HAL_SWITCH_PORT_RMAC_PAUSE_GEN_EN_DEFAULT)) 305221167Sgnn return (VXGE_HAL_BADCFG_SWITCH_PORT_RMAC_PAUSE_GEN_EN); 306221167Sgnn 307221167Sgnn if ((port_config->rmac_pause_rcv_en != 308221167Sgnn VXGE_HAL_SWITCH_PORT_RMAC_PAUSE_RCV_EN_ENABLE) && 309221167Sgnn (port_config->rmac_pause_rcv_en != 310221167Sgnn VXGE_HAL_SWITCH_PORT_RMAC_PAUSE_RCV_EN_DISABLE) && 311221167Sgnn (port_config->rmac_pause_rcv_en != 312221167Sgnn VXGE_HAL_SWITCH_PORT_RMAC_PAUSE_RCV_EN_DEFAULT)) 313221167Sgnn return (VXGE_HAL_BADCFG_SWITCH_PORT_RMAC_PAUSE_RCV_EN); 314221167Sgnn 315221167Sgnn if (((port_config->rmac_pause_time < 316221167Sgnn VXGE_HAL_SWITCH_PORT_MIN_RMAC_HIGH_PTIME) || 317221167Sgnn (port_config->rmac_pause_time > 318221167Sgnn VXGE_HAL_SWITCH_PORT_MAX_RMAC_HIGH_PTIME)) && 319221167Sgnn (port_config->rmac_pause_time != 320221167Sgnn VXGE_HAL_SWITCH_PORT_DEF_RMAC_HIGH_PTIME)) 321221167Sgnn return (VXGE_HAL_BADCFG_SWITCH_PORT_RMAC_HIGH_PTIME); 322221167Sgnn 323221167Sgnn if ((port_config->limiter_en != 324221167Sgnn VXGE_HAL_SWITCH_PORT_RMAC_PAUSE_LIMITER_ENABLE) && 325221167Sgnn (port_config->limiter_en != 326221167Sgnn VXGE_HAL_SWITCH_PORT_RMAC_PAUSE_LIMITER_DISABLE) && 327221167Sgnn (port_config->limiter_en != 328221167Sgnn VXGE_HAL_SWITCH_PORT_RMAC_PAUSE_LIMITER_DEFAULT)) 329221167Sgnn return (VXGE_HAL_BADCFG_SWITCH_PORT_RMAC_PAUSE_LIMITER_EN); 330221167Sgnn 331221167Sgnn if ((port_config->max_limit > 332221167Sgnn VXGE_HAL_SWITCH_PORT_MAX_RMAC_MAX_LIMIT) && 333221167Sgnn (port_config->max_limit != 334221167Sgnn VXGE_HAL_SWITCH_PORT_DEF_RMAC_MAX_LIMIT)) 335221167Sgnn return (VXGE_HAL_BADCFG_SWITCH_PORT_RMAC_MAX_LIMIT); 336221167Sgnn 337221167Sgnn return (VXGE_HAL_OK); 338221167Sgnn} 339221167Sgnn 340221167Sgnn/* 341221167Sgnn * __hal_device_mac_config_check - Check mac port configuration. 342221167Sgnn * @mac_config: MAC configuration information 343221167Sgnn * 344221167Sgnn * Check mac port configuration 345221167Sgnn * 346221167Sgnn * Returns: VXGE_HAL_OK - success, 347221167Sgnn * otherwise one of the vxge_hal_status_e enumerated error codes. 348221167Sgnn * 349221167Sgnn */ 350221167Sgnnvxge_hal_status_e 351221167Sgnn__hal_device_mac_config_check(vxge_hal_mac_config_t *mac_config) 352221167Sgnn{ 353221167Sgnn u32 i; 354221167Sgnn vxge_hal_status_e status; 355221167Sgnn 356221167Sgnn status = __hal_device_wire_port_config_check( 357221167Sgnn &mac_config->wire_port_config[0]); 358221167Sgnn 359221167Sgnn if (status != VXGE_HAL_OK) 360221167Sgnn return (status); 361221167Sgnn 362221167Sgnn status = __hal_device_wire_port_config_check( 363221167Sgnn &mac_config->wire_port_config[1]); 364221167Sgnn 365221167Sgnn if (status != VXGE_HAL_OK) 366221167Sgnn return (status); 367221167Sgnn 368221167Sgnn status = __hal_device_switch_port_config_check( 369221167Sgnn &mac_config->switch_port_config); 370221167Sgnn 371221167Sgnn if (status != VXGE_HAL_OK) 372221167Sgnn return (status); 373221167Sgnn 374221167Sgnn if ((mac_config->network_stability_period > 375221167Sgnn VXGE_HAL_MAC_MAX_NETWORK_STABILITY_PERIOD) && 376221167Sgnn (mac_config->network_stability_period != 377221167Sgnn VXGE_HAL_MAC_DEF_NETWORK_STABILITY_PERIOD)) 378221167Sgnn return (VXGE_HAL_BADCFG_MAC_NETWORK_STABILITY_PERIOD); 379221167Sgnn 380221167Sgnn for (i = 0; i < 16; i++) { 381221167Sgnn 382221167Sgnn if ((mac_config->mc_pause_threshold[i] > 383221167Sgnn VXGE_HAL_MAC_MAX_MC_PAUSE_THRESHOLD) && 384221167Sgnn (mac_config->mc_pause_threshold[i] != 385221167Sgnn VXGE_HAL_MAC_DEF_MC_PAUSE_THRESHOLD)) 386221167Sgnn return (VXGE_HAL_BADCFG_MAC_MC_PAUSE_THRESHOLD); 387221167Sgnn 388221167Sgnn } 389221167Sgnn 390221167Sgnn if ((mac_config->tmac_perma_stop_en != 391221167Sgnn VXGE_HAL_MAC_TMAC_PERMA_STOP_ENABLE) && 392221167Sgnn (mac_config->tmac_perma_stop_en != 393221167Sgnn VXGE_HAL_MAC_TMAC_PERMA_STOP_DISABLE) && 394221167Sgnn (mac_config->tmac_perma_stop_en != 395221167Sgnn VXGE_HAL_MAC_TMAC_PERMA_STOP_DEFAULT)) 396221167Sgnn return (VXGE_HAL_BADCFG_MAC_PERMA_STOP_EN); 397221167Sgnn 398221167Sgnn if ((mac_config->tmac_tx_switch_dis != 399221167Sgnn VXGE_HAL_MAC_TMAC_TX_SWITCH_ENABLE) && 400221167Sgnn (mac_config->tmac_tx_switch_dis != 401221167Sgnn VXGE_HAL_MAC_TMAC_TX_SWITCH_DISABLE) && 402221167Sgnn (mac_config->tmac_tx_switch_dis != 403221167Sgnn VXGE_HAL_MAC_TMAC_TX_SWITCH_DEFAULT)) 404221167Sgnn return (VXGE_HAL_BADCFG_MAC_TMAC_TX_SWITCH_DIS); 405221167Sgnn 406221167Sgnn if ((mac_config->tmac_lossy_switch_en != 407221167Sgnn VXGE_HAL_MAC_TMAC_LOSSY_SWITCH_ENABLE) && 408221167Sgnn (mac_config->tmac_lossy_switch_en != 409221167Sgnn VXGE_HAL_MAC_TMAC_LOSSY_SWITCH_DISABLE) && 410221167Sgnn (mac_config->tmac_lossy_switch_en != 411221167Sgnn VXGE_HAL_MAC_TMAC_LOSSY_SWITCH_DEFAULT)) 412221167Sgnn return (VXGE_HAL_BADCFG_MAC_TMAC_LOSSY_SWITCH_EN); 413221167Sgnn 414221167Sgnn if ((mac_config->tmac_lossy_wire_en != 415221167Sgnn VXGE_HAL_MAC_TMAC_LOSSY_WIRE_ENABLE) && 416221167Sgnn (mac_config->tmac_lossy_wire_en != 417221167Sgnn VXGE_HAL_MAC_TMAC_LOSSY_WIRE_DISABLE) && 418221167Sgnn (mac_config->tmac_lossy_wire_en != 419221167Sgnn VXGE_HAL_MAC_TMAC_LOSSY_WIRE_DEFAULT)) 420221167Sgnn return (VXGE_HAL_BADCFG_MAC_TMAC_LOSSY_WIRE_EN); 421221167Sgnn 422221167Sgnn if ((mac_config->tmac_bcast_to_wire_dis != 423221167Sgnn VXGE_HAL_MAC_TMAC_BCAST_TO_WIRE_DISABLE) && 424221167Sgnn (mac_config->tmac_bcast_to_wire_dis != 425221167Sgnn VXGE_HAL_MAC_TMAC_BCAST_TO_WIRE_ENABLE) && 426221167Sgnn (mac_config->tmac_bcast_to_wire_dis != 427221167Sgnn VXGE_HAL_MAC_TMAC_BCAST_TO_WIRE_DEFAULT)) 428221167Sgnn return (VXGE_HAL_BADCFG_MAC_TMAC_BCAST_TO_WIRE_DIS); 429221167Sgnn 430221167Sgnn if ((mac_config->tmac_bcast_to_switch_dis != 431221167Sgnn VXGE_HAL_MAC_TMAC_BCAST_TO_SWITCH_DISABLE) && 432221167Sgnn (mac_config->tmac_bcast_to_switch_dis != 433221167Sgnn VXGE_HAL_MAC_TMAC_BCAST_TO_SWITCH_ENABLE) && 434221167Sgnn (mac_config->tmac_bcast_to_switch_dis != 435221167Sgnn VXGE_HAL_MAC_TMAC_BCAST_TO_SWITCH_DEFAULT)) 436221167Sgnn return (VXGE_HAL_BADCFG_MAC_TMAC_BCAST_TO_SWITCH_DIS); 437221167Sgnn 438221167Sgnn if ((mac_config->tmac_host_append_fcs_en != 439221167Sgnn VXGE_HAL_MAC_TMAC_HOST_APPEND_FCS_ENABLE) && 440221167Sgnn (mac_config->tmac_host_append_fcs_en != 441221167Sgnn VXGE_HAL_MAC_TMAC_HOST_APPEND_FCS_DISABLE) && 442221167Sgnn (mac_config->tmac_host_append_fcs_en != 443221167Sgnn VXGE_HAL_MAC_TMAC_HOST_APPEND_FCS_DEFAULT)) 444221167Sgnn return (VXGE_HAL_BADCFG_MAC_TMAC_HOST_APPEND_FCS_EN); 445221167Sgnn 446221167Sgnn if ((mac_config->tpa_support_snap_ab_n != 447221167Sgnn VXGE_HAL_MAC_TPA_SUPPORT_SNAP_AB_N_LLC_SAP_AB) && 448221167Sgnn (mac_config->tpa_support_snap_ab_n != 449221167Sgnn VXGE_HAL_MAC_TPA_SUPPORT_SNAP_AB_N_LLC_SAP_AA) && 450221167Sgnn (mac_config->tpa_support_snap_ab_n != 451221167Sgnn VXGE_HAL_MAC_TPA_SUPPORT_SNAP_AB_N_DEFAULT)) 452221167Sgnn return (VXGE_HAL_BADCFG_MAC_TPA_SUPPORT_SNAP_AB_N); 453221167Sgnn 454221167Sgnn if ((mac_config->tpa_ecc_enable_n != 455221167Sgnn VXGE_HAL_MAC_TPA_ECC_ENABLE_N_ENABLE) && 456221167Sgnn (mac_config->tpa_ecc_enable_n != 457221167Sgnn VXGE_HAL_MAC_TPA_ECC_ENABLE_N_DISABLE) && 458221167Sgnn (mac_config->tpa_ecc_enable_n != 459221167Sgnn VXGE_HAL_MAC_TPA_ECC_ENABLE_N_DEFAULT)) 460221167Sgnn return (VXGE_HAL_BADCFG_MAC_TPA_ECC_ENABLE_N); 461221167Sgnn 462221167Sgnn if ((mac_config->rpa_ignore_frame_err != 463221167Sgnn VXGE_HAL_MAC_RPA_IGNORE_FRAME_ERR_ENABLE) && 464221167Sgnn (mac_config->rpa_ignore_frame_err != 465221167Sgnn VXGE_HAL_MAC_RPA_IGNORE_FRAME_ERR_DISABLE) && 466221167Sgnn (mac_config->rpa_ignore_frame_err != 467221167Sgnn VXGE_HAL_MAC_RPA_IGNORE_FRAME_ERR_DEFAULT)) 468221167Sgnn return (VXGE_HAL_BADCFG_MAC_RPA_IGNORE_FRAME_ERR); 469221167Sgnn 470221167Sgnn if ((mac_config->rpa_support_snap_ab_n != 471221167Sgnn VXGE_HAL_MAC_RPA_SUPPORT_SNAP_AB_N_ENABLE) && 472221167Sgnn (mac_config->rpa_support_snap_ab_n != 473221167Sgnn VXGE_HAL_MAC_RPA_SUPPORT_SNAP_AB_N_DISABLE) && 474221167Sgnn (mac_config->rpa_support_snap_ab_n != 475221167Sgnn VXGE_HAL_MAC_RPA_SUPPORT_SNAP_AB_N_DEFAULT)) 476221167Sgnn return (VXGE_HAL_BADCFG_MAC_RPA_SNAP_AB_N); 477221167Sgnn 478221167Sgnn if ((mac_config->rpa_search_for_hao != 479221167Sgnn VXGE_HAL_MAC_RPA_SEARCH_FOR_HAO_ENABLE) && 480221167Sgnn (mac_config->rpa_search_for_hao != 481221167Sgnn VXGE_HAL_MAC_RPA_SEARCH_FOR_HAO_DISABLE) && 482221167Sgnn (mac_config->rpa_search_for_hao != 483221167Sgnn VXGE_HAL_MAC_RPA_SEARCH_FOR_HAO_DEFAULT)) 484221167Sgnn return (VXGE_HAL_BADCFG_MAC_RPA_SEARCH_FOR_HAO); 485221167Sgnn 486221167Sgnn if ((mac_config->rpa_support_ipv6_mobile_hdrs != 487221167Sgnn VXGE_HAL_MAC_RPA_SUPPORT_IPV6_MOBILE_HDRS_ENABLE) && 488221167Sgnn (mac_config->rpa_support_ipv6_mobile_hdrs != 489221167Sgnn VXGE_HAL_MAC_RPA_SUPPORT_IPV6_MOBILE_HDRS_DISABLE) && 490221167Sgnn (mac_config->rpa_support_ipv6_mobile_hdrs != 491221167Sgnn VXGE_HAL_MAC_RPA_SUPPORT_IPV6_MOBILE_HDRS_DEFAULT)) 492221167Sgnn return (VXGE_HAL_BADCFG_MAC_RPA_SUPPORT_IPV6_MOBILE_HDRS); 493221167Sgnn 494221167Sgnn if ((mac_config->rpa_ipv6_stop_searching != 495221167Sgnn VXGE_HAL_MAC_RPA_IPV6_STOP_SEARCHING) && 496221167Sgnn (mac_config->rpa_ipv6_stop_searching != 497221167Sgnn VXGE_HAL_MAC_RPA_IPV6_DONT_STOP_SEARCHING) && 498221167Sgnn (mac_config->rpa_ipv6_stop_searching != 499221167Sgnn VXGE_HAL_MAC_RPA_IPV6_STOP_SEARCHING_DEFAULT)) 500221167Sgnn return (VXGE_HAL_BADCFG_MAC_RPA_IPV6_STOP_SEARCHING); 501221167Sgnn 502221167Sgnn if ((mac_config->rpa_no_ps_if_unknown != 503221167Sgnn VXGE_HAL_MAC_RPA_NO_PS_IF_UNKNOWN_ENABLE) && 504221167Sgnn (mac_config->rpa_no_ps_if_unknown != 505221167Sgnn VXGE_HAL_MAC_RPA_NO_PS_IF_UNKNOWN_DISABLE) && 506221167Sgnn (mac_config->rpa_no_ps_if_unknown != 507221167Sgnn VXGE_HAL_MAC_RPA_NO_PS_IF_UNKNOWN_DEFAULT)) 508221167Sgnn return (VXGE_HAL_BADCFG_MAC_RPA_NO_PS_IF_UNKNOWN); 509221167Sgnn 510221167Sgnn if ((mac_config->rpa_search_for_etype != 511221167Sgnn VXGE_HAL_MAC_RPA_SEARCH_FOR_ETYPE_ENABLE) && 512221167Sgnn (mac_config->rpa_search_for_etype != 513221167Sgnn VXGE_HAL_MAC_RPA_SEARCH_FOR_ETYPE_DISABLE) && 514221167Sgnn (mac_config->rpa_search_for_etype != 515221167Sgnn VXGE_HAL_MAC_RPA_SEARCH_FOR_ETYPE_DEFAULT)) 516221167Sgnn return (VXGE_HAL_BADCFG_MAC_RPA_SEARCH_FOR_ETYPE); 517221167Sgnn 518221167Sgnn if ((mac_config->rpa_repl_l4_comp_csum != 519221167Sgnn VXGE_HAL_MAC_RPA_REPL_L4_COMP_CSUM_ENABLE) && 520221167Sgnn (mac_config->rpa_repl_l4_comp_csum != 521221167Sgnn VXGE_HAL_MAC_RPA_REPL_L4_COMP_CSUM_DISABLE) && 522221167Sgnn (mac_config->rpa_repl_l4_comp_csum != 523221167Sgnn VXGE_HAL_MAC_RPA_REPL_l4_COMP_CSUM_DEFAULT)) 524221167Sgnn return (VXGE_HAL_BADCFG_MAC_RPA_REPL_L4_COMP_CSUM); 525221167Sgnn 526221167Sgnn if ((mac_config->rpa_repl_l3_incl_cf != 527221167Sgnn VXGE_HAL_MAC_RPA_REPL_L3_INCL_CF_ENABLE) && 528221167Sgnn (mac_config->rpa_repl_l3_incl_cf != 529221167Sgnn VXGE_HAL_MAC_RPA_REPL_L3_INCL_CF_DISABLE) && 530221167Sgnn (mac_config->rpa_repl_l3_incl_cf != 531221167Sgnn VXGE_HAL_MAC_RPA_REPL_L3_INCL_CF_DEFAULT)) 532221167Sgnn return (VXGE_HAL_BADCFG_MAC_RPA_REPL_L3_INCL_CF); 533221167Sgnn 534221167Sgnn if ((mac_config->rpa_repl_l3_comp_csum != 535221167Sgnn VXGE_HAL_MAC_RPA_REPL_L3_COMP_CSUM_ENABLE) && 536221167Sgnn (mac_config->rpa_repl_l3_comp_csum != 537221167Sgnn VXGE_HAL_MAC_RPA_REPL_L3_COMP_CSUM_DISABLE) && 538221167Sgnn (mac_config->rpa_repl_l3_comp_csum != 539221167Sgnn VXGE_HAL_MAC_RPA_REPL_l3_COMP_CSUM_DEFAULT)) 540221167Sgnn return (VXGE_HAL_BADCFG_MAC_RPA_REPL_L3_COMP_CSUM); 541221167Sgnn 542221167Sgnn if ((mac_config->rpa_repl_ipv4_tcp_incl_ph != 543221167Sgnn VXGE_HAL_MAC_RPA_REPL_IPV4_TCP_INCL_PH_ENABLE) && 544221167Sgnn (mac_config->rpa_repl_ipv4_tcp_incl_ph != 545221167Sgnn VXGE_HAL_MAC_RPA_REPL_IPV4_TCP_INCL_PH_DISABLE) && 546221167Sgnn (mac_config->rpa_repl_ipv4_tcp_incl_ph != 547221167Sgnn VXGE_HAL_MAC_RPA_REPL_IPV4_TCP_INCL_PH_DEFAULT)) 548221167Sgnn return (VXGE_HAL_BADCFG_MAC_RPA_REPL_IPV4_TCP_INCL_PH); 549221167Sgnn 550221167Sgnn if ((mac_config->rpa_repl_ipv6_tcp_incl_ph != 551221167Sgnn VXGE_HAL_MAC_RPA_REPL_IPV6_TCP_INCL_PH_ENABLE) && 552221167Sgnn (mac_config->rpa_repl_ipv6_tcp_incl_ph != 553221167Sgnn VXGE_HAL_MAC_RPA_REPL_IPV6_TCP_INCL_PH_DISABLE) && 554221167Sgnn (mac_config->rpa_repl_ipv6_tcp_incl_ph != 555221167Sgnn VXGE_HAL_MAC_RPA_REPL_IPV6_TCP_INCL_PH_DEFAULT)) 556221167Sgnn return (VXGE_HAL_BADCFG_MAC_RPA_REPL_IPV6_TCP_INCL_PH); 557221167Sgnn 558221167Sgnn if ((mac_config->rpa_repl_ipv4_udp_incl_ph != 559221167Sgnn VXGE_HAL_MAC_RPA_REPL_IPV4_UDP_INCL_PH_ENABLE) && 560221167Sgnn (mac_config->rpa_repl_ipv4_udp_incl_ph != 561221167Sgnn VXGE_HAL_MAC_RPA_REPL_IPV4_UDP_INCL_PH_DISABLE) && 562221167Sgnn (mac_config->rpa_repl_ipv4_udp_incl_ph != 563221167Sgnn VXGE_HAL_MAC_RPA_REPL_IPV4_UDP_INCL_PH_DEFAULT)) 564221167Sgnn return (VXGE_HAL_BADCFG_MAC_RPA_REPL_IPV4_UDP_INCL_PH); 565221167Sgnn 566221167Sgnn if ((mac_config->rpa_repl_ipv6_udp_incl_ph != 567221167Sgnn VXGE_HAL_MAC_RPA_REPL_IPV6_UDP_INCL_PH_ENABLE) && 568221167Sgnn (mac_config->rpa_repl_ipv6_udp_incl_ph != 569221167Sgnn VXGE_HAL_MAC_RPA_REPL_IPV6_UDP_INCL_PH_DISABLE) && 570221167Sgnn (mac_config->rpa_repl_ipv6_udp_incl_ph != 571221167Sgnn VXGE_HAL_MAC_RPA_REPL_IPV6_UDP_INCL_PH_DEFAULT)) 572221167Sgnn return (VXGE_HAL_BADCFG_MAC_RPA_REPL_IPV6_UDP_INCL_PH); 573221167Sgnn 574221167Sgnn if ((mac_config->rpa_repl_l4_incl_cf != 575221167Sgnn VXGE_HAL_MAC_RPA_REPL_L4_INCL_CF_ENABLE) && 576221167Sgnn (mac_config->rpa_repl_l4_incl_cf != 577221167Sgnn VXGE_HAL_MAC_RPA_REPL_L4_INCL_CF_DISABLE) && 578221167Sgnn (mac_config->rpa_repl_l4_incl_cf != 579221167Sgnn VXGE_HAL_MAC_RPA_REPL_L4_INCL_CF_DEFAULT)) 580221167Sgnn return (VXGE_HAL_BADCFG_MAC_RPA_REPL_L4_INCL_CF); 581221167Sgnn 582221167Sgnn if ((mac_config->rpa_repl_strip_vlan_tag != 583221167Sgnn VXGE_HAL_MAC_RPA_REPL_STRIP_VLAN_TAG_ENABLE) && 584221167Sgnn (mac_config->rpa_repl_strip_vlan_tag != 585221167Sgnn VXGE_HAL_MAC_RPA_REPL_STRIP_VLAN_TAG_DISABLE) && 586221167Sgnn (mac_config->rpa_repl_strip_vlan_tag != 587221167Sgnn VXGE_HAL_MAC_RPA_REPL_STRIP_VLAN_TAG_DEFAULT)) 588221167Sgnn return (VXGE_HAL_BADCFG_MAC_RPA_REPL_STRIP_VLAN_TAG); 589221167Sgnn 590221167Sgnn return (VXGE_HAL_OK); 591221167Sgnn} 592221167Sgnn 593221167Sgnn/* 594221167Sgnn * __hal_device_lag_port_config_check - Check LAG port configuration. 595221167Sgnn * @aggr_config: LAG port configuration information 596221167Sgnn * 597221167Sgnn * Check LAG port configuration 598221167Sgnn * 599221167Sgnn * Returns: VXGE_HAL_OK - success, 600221167Sgnn * otherwise one of the vxge_hal_status_e enumerated error codes. 601221167Sgnn * 602221167Sgnn */ 603221167Sgnnvxge_hal_status_e 604221167Sgnn__hal_device_lag_port_config_check(vxge_hal_lag_port_config_t *port_config) 605221167Sgnn{ 606221167Sgnn if ((port_config->port_id != VXGE_HAL_LAG_PORT_PORT_ID_0) && 607221167Sgnn (port_config->port_id != VXGE_HAL_LAG_PORT_PORT_ID_1)) 608221167Sgnn return (VXGE_HAL_BADCFG_LAG_PORT_PORT_ID); 609221167Sgnn 610221167Sgnn if ((port_config->lag_en != 611221167Sgnn VXGE_HAL_LAG_PORT_LAG_EN_DISABLE) && 612221167Sgnn (port_config->lag_en != 613221167Sgnn VXGE_HAL_LAG_PORT_LAG_EN_ENABLE) && 614221167Sgnn (port_config->lag_en != 615221167Sgnn VXGE_HAL_LAG_PORT_LAG_EN_DEFAULT)) 616221167Sgnn return (VXGE_HAL_BADCFG_LAG_PORT_LAG_EN); 617221167Sgnn 618221167Sgnn if ((port_config->discard_slow_proto != 619221167Sgnn VXGE_HAL_LAG_PORT_DISCARD_SLOW_PROTO_DISABLE) && 620221167Sgnn (port_config->discard_slow_proto != 621221167Sgnn VXGE_HAL_LAG_PORT_DISCARD_SLOW_PROTO_ENABLE) && 622221167Sgnn (port_config->discard_slow_proto != 623221167Sgnn VXGE_HAL_LAG_PORT_DISCARD_SLOW_PROTO_DEFAULT)) 624221167Sgnn return (VXGE_HAL_BADCFG_LAG_PORT_DISCARD_SLOW_PROTO); 625221167Sgnn 626221167Sgnn if ((port_config->host_chosen_aggr != 627221167Sgnn VXGE_HAL_LAG_PORT_HOST_CHOSEN_AGGR_0) && 628221167Sgnn (port_config->host_chosen_aggr != 629221167Sgnn VXGE_HAL_LAG_PORT_HOST_CHOSEN_AGGR_1) && 630221167Sgnn (port_config->host_chosen_aggr != 631221167Sgnn VXGE_HAL_LAG_PORT_HOST_CHOSEN_AGGR_DEFAULT)) 632221167Sgnn return (VXGE_HAL_BADCFG_LAG_PORT_HOST_CHOSEN_AGGR); 633221167Sgnn 634221167Sgnn if ((port_config->discard_unknown_slow_proto != 635221167Sgnn VXGE_HAL_LAG_PORT_DISCARD_UNKNOWN_SLOW_PROTO_DISABLE) && 636221167Sgnn (port_config->discard_unknown_slow_proto != 637221167Sgnn VXGE_HAL_LAG_PORT_DISCARD_UNKNOWN_SLOW_PROTO_ENABLE) && 638221167Sgnn (port_config->discard_unknown_slow_proto != 639221167Sgnn VXGE_HAL_LAG_PORT_DISCARD_UNKNOWN_SLOW_PROTO_DEFAULT)) 640221167Sgnn return (VXGE_HAL_BADCFG_LAG_PORT_DISCARD_UNKNOWN_SLOW_PROTO); 641221167Sgnn 642221167Sgnn if ((port_config->actor_port_num > 643221167Sgnn VXGE_HAL_LAG_PORT_MAX_ACTOR_PORT_NUM) && 644221167Sgnn (port_config->actor_port_num != 645221167Sgnn VXGE_HAL_LAG_PORT_DEF_ACTOR_PORT_NUM)) 646221167Sgnn return (VXGE_HAL_BADCFG_LAG_PORT_ACTOR_PORT_NUM); 647221167Sgnn 648221167Sgnn if ((port_config->actor_port_priority > 649221167Sgnn VXGE_HAL_LAG_PORT_MAX_ACTOR_PORT_PRIORITY) && 650221167Sgnn (port_config->actor_port_priority != 651221167Sgnn VXGE_HAL_LAG_PORT_DEF_ACTOR_PORT_PRIORITY)) 652221167Sgnn return (VXGE_HAL_BADCFG_LAG_PORT_ACTOR_PORT_PRIORITY); 653221167Sgnn 654221167Sgnn if ((port_config->actor_key_10g > 655221167Sgnn VXGE_HAL_LAG_PORT_MAX_ACTOR_KEY_10G) && 656221167Sgnn (port_config->actor_key_10g != 657221167Sgnn VXGE_HAL_LAG_PORT_DEF_ACTOR_KEY_10G)) 658221167Sgnn return (VXGE_HAL_BADCFG_LAG_PORT_ACTOR_KEY_10G); 659221167Sgnn 660221167Sgnn if ((port_config->actor_key_1g > VXGE_HAL_LAG_PORT_MAX_ACTOR_KEY_1G) && 661221167Sgnn (port_config->actor_key_1g != VXGE_HAL_LAG_PORT_DEF_ACTOR_KEY_1G)) 662221167Sgnn return (VXGE_HAL_BADCFG_LAG_PORT_ACTOR_KEY_1G); 663221167Sgnn 664221167Sgnn if ((port_config->actor_lacp_activity != 665221167Sgnn VXGE_HAL_LAG_PORT_ACTOR_LACP_ACTIVITY_PASSIVE) && 666221167Sgnn (port_config->actor_lacp_activity != 667221167Sgnn VXGE_HAL_LAG_PORT_ACTOR_LACP_ACTIVITY_ACTIVE) && 668221167Sgnn (port_config->actor_lacp_activity != 669221167Sgnn VXGE_HAL_LAG_PORT_ACTOR_LACP_ACTIVITY_DEFAULT)) 670221167Sgnn return (VXGE_HAL_BADCFG_LAG_PORT_ACTOR_LACP_ACTIVITY); 671221167Sgnn 672221167Sgnn if ((port_config->actor_lacp_timeout != 673221167Sgnn VXGE_HAL_LAG_PORT_ACTOR_LACP_TIMEOUT_LONG) && 674221167Sgnn (port_config->actor_lacp_timeout != 675221167Sgnn VXGE_HAL_LAG_PORT_ACTOR_LACP_TIMEOUT_SHORT) && 676221167Sgnn (port_config->actor_lacp_timeout != 677221167Sgnn VXGE_HAL_LAG_PORT_ACTOR_LACP_TIMEOUT_DEFAULT)) 678221167Sgnn return (VXGE_HAL_BADCFG_LAG_PORT_ACTOR_LACP_TIMEOUT); 679221167Sgnn 680221167Sgnn if ((port_config->actor_aggregation != 681221167Sgnn VXGE_HAL_LAG_PORT_ACTOR_AGGREGATION_INDIVIDUAL) && 682221167Sgnn (port_config->actor_aggregation != 683221167Sgnn VXGE_HAL_LAG_PORT_ACTOR_AGGREGATION_AGGREGATEABLE) && 684221167Sgnn (port_config->actor_aggregation != 685221167Sgnn VXGE_HAL_LAG_PORT_ACTOR_AGGREGATION_DEFAULT)) 686221167Sgnn return (VXGE_HAL_BADCFG_LAG_PORT_ACTOR_AGGREGATION); 687221167Sgnn 688221167Sgnn if ((port_config->actor_synchronization != 689221167Sgnn VXGE_HAL_LAG_PORT_ACTOR_SYNCHRONIZATION_OUT_OF_SYNC) && 690221167Sgnn (port_config->actor_synchronization != 691221167Sgnn VXGE_HAL_LAG_PORT_ACTOR_SYNCHRONIZATION_IN_SYNC) && 692221167Sgnn (port_config->actor_synchronization != 693221167Sgnn VXGE_HAL_LAG_PORT_ACTOR_SYNCHRONIZATION_DEFAULT)) 694221167Sgnn return (VXGE_HAL_BADCFG_LAG_PORT_ACTOR_SYNCHRONIZATION); 695221167Sgnn 696221167Sgnn if ((port_config->actor_collecting != 697221167Sgnn VXGE_HAL_LAG_PORT_ACTOR_COLLECTING_DISABLE) && 698221167Sgnn (port_config->actor_collecting != 699221167Sgnn VXGE_HAL_LAG_PORT_ACTOR_COLLECTING_ENABLE) && 700221167Sgnn (port_config->actor_collecting != 701221167Sgnn VXGE_HAL_LAG_PORT_ACTOR_COLLECTING_DEFAULT)) 702221167Sgnn return (VXGE_HAL_BADCFG_LAG_PORT_ACTOR_COLLECTING); 703221167Sgnn 704221167Sgnn if ((port_config->actor_distributing != 705221167Sgnn VXGE_HAL_LAG_PORT_ACTOR_DISTRIBUTING_DISABLE) && 706221167Sgnn (port_config->actor_distributing != 707221167Sgnn VXGE_HAL_LAG_PORT_ACTOR_DISTRIBUTING_ENABLE) && 708221167Sgnn (port_config->actor_distributing != 709221167Sgnn VXGE_HAL_LAG_PORT_ACTOR_DISTRIBUTING_DEFAULT)) 710221167Sgnn return (VXGE_HAL_BADCFG_LAG_PORT_ACTOR_DISTRIBUTING); 711221167Sgnn 712221167Sgnn if ((port_config->actor_distributing != 713221167Sgnn VXGE_HAL_LAG_PORT_ACTOR_DISTRIBUTING_DISABLE) && 714221167Sgnn (port_config->actor_distributing != 715221167Sgnn VXGE_HAL_LAG_PORT_ACTOR_DISTRIBUTING_ENABLE) && 716221167Sgnn (port_config->actor_distributing != 717221167Sgnn VXGE_HAL_LAG_PORT_ACTOR_DISTRIBUTING_DEFAULT)) 718221167Sgnn return (VXGE_HAL_BADCFG_LAG_PORT_ACTOR_DISTRIBUTING); 719221167Sgnn 720221167Sgnn if ((port_config->actor_defaulted != 721221167Sgnn VXGE_HAL_LAG_PORT_ACTOR_DEFAULTED) && 722221167Sgnn (port_config->actor_defaulted != 723221167Sgnn VXGE_HAL_LAG_PORT_ACTOR_NOT_DEFAULTED) && 724221167Sgnn (port_config->actor_defaulted != 725221167Sgnn VXGE_HAL_LAG_PORT_ACTOR_DEFAULTED_DEFAULT)) 726221167Sgnn return (VXGE_HAL_BADCFG_LAG_PORT_ACTOR_DEFAULTED); 727221167Sgnn 728221167Sgnn if ((port_config->actor_expired != 729221167Sgnn VXGE_HAL_LAG_PORT_ACTOR_EXPIRED) && 730221167Sgnn (port_config->actor_expired != 731221167Sgnn VXGE_HAL_LAG_PORT_ACTOR_NOT_EXPIRED) && 732221167Sgnn (port_config->actor_expired != 733221167Sgnn VXGE_HAL_LAG_PORT_ACTOR_EXPIRED_DEFAULT)) 734221167Sgnn return (VXGE_HAL_BADCFG_LAG_PORT_ACTOR_EXPIRED); 735221167Sgnn 736221167Sgnn if ((port_config->partner_sys_pri > 737221167Sgnn VXGE_HAL_LAG_PORT_MAX_PARTNER_SYS_PRI) && 738221167Sgnn (port_config->partner_sys_pri != 739221167Sgnn VXGE_HAL_LAG_PORT_DEF_PARTNER_SYS_PRI)) 740221167Sgnn return (VXGE_HAL_BADCFG_LAG_PORT_PARTNER_SYS_PRI); 741221167Sgnn 742221167Sgnn if ((port_config->partner_key > VXGE_HAL_LAG_PORT_MAX_PARTNER_KEY) && 743221167Sgnn (port_config->partner_key != VXGE_HAL_LAG_PORT_DEF_PARTNER_KEY)) 744221167Sgnn return (VXGE_HAL_BADCFG_LAG_PORT_PARTNER_KEY); 745221167Sgnn 746221167Sgnn if ((port_config->partner_port_num > 747221167Sgnn VXGE_HAL_LAG_PORT_MAX_PARTNER_PORT_NUM) && 748221167Sgnn (port_config->partner_port_num != 749221167Sgnn VXGE_HAL_LAG_PORT_DEF_PARTNER_PORT_NUM)) 750221167Sgnn return (VXGE_HAL_BADCFG_LAG_PORT_PARTNER_NUM); 751221167Sgnn 752221167Sgnn if ((port_config->partner_port_priority > 753221167Sgnn VXGE_HAL_LAG_PORT_MAX_PARTNER_PORT_PRIORITY) && 754221167Sgnn (port_config->partner_port_priority != 755221167Sgnn VXGE_HAL_LAG_PORT_DEF_PARTNER_PORT_PRIORITY)) 756221167Sgnn return (VXGE_HAL_BADCFG_LAG_PORT_PARTNER_PORT_PRIORITY); 757221167Sgnn 758221167Sgnn if ((port_config->partner_lacp_activity != 759221167Sgnn VXGE_HAL_LAG_PORT_PARTNER_LACP_ACTIVITY_PASSIVE) && 760221167Sgnn (port_config->partner_lacp_activity != 761221167Sgnn VXGE_HAL_LAG_PORT_PARTNER_LACP_ACTIVITY_ACTIVE) && 762221167Sgnn (port_config->partner_lacp_activity != 763221167Sgnn VXGE_HAL_LAG_PORT_PARTNER_LACP_ACTIVITY_DEFAULT)) 764221167Sgnn return (VXGE_HAL_BADCFG_LAG_PORT_PARTNER_LACP_ACTIVITY); 765221167Sgnn 766221167Sgnn if ((port_config->partner_lacp_timeout != 767221167Sgnn VXGE_HAL_LAG_PORT_PARTNER_LACP_TIMEOUT_LONG) && 768221167Sgnn (port_config->partner_lacp_timeout != 769221167Sgnn VXGE_HAL_LAG_PORT_PARTNER_LACP_TIMEOUT_SHORT) && 770221167Sgnn (port_config->partner_lacp_timeout != 771221167Sgnn VXGE_HAL_LAG_PORT_PARTNER_LACP_TIMEOUT_DEFAULT)) 772221167Sgnn return (VXGE_HAL_BADCFG_LAG_PORT_PARTNER_LACP_TIMEOUT); 773221167Sgnn 774221167Sgnn if ((port_config->partner_aggregation != 775221167Sgnn VXGE_HAL_LAG_PORT_PARTNER_AGGREGATION_INDIVIDUAL) && 776221167Sgnn (port_config->partner_aggregation != 777221167Sgnn VXGE_HAL_LAG_PORT_PARTNER_AGGREGATION_AGGREGATEABLE) && 778221167Sgnn (port_config->partner_aggregation != 779221167Sgnn VXGE_HAL_LAG_PORT_PARTNER_AGGREGATION_DEFAULT)) 780221167Sgnn return (VXGE_HAL_BADCFG_LAG_PORT_PARTNER_AGGREGATION); 781221167Sgnn 782221167Sgnn if ((port_config->partner_synchronization != 783221167Sgnn VXGE_HAL_LAG_PORT_PARTNER_SYNCHRONIZATION_OUT_OF_SYNC) && 784221167Sgnn (port_config->partner_synchronization != 785221167Sgnn VXGE_HAL_LAG_PORT_PARTNER_SYNCHRONIZATION_IN_SYNC) && 786221167Sgnn (port_config->partner_synchronization != 787221167Sgnn VXGE_HAL_LAG_PORT_PARTNER_SYNCHRONIZATION_DEFAULT)) 788221167Sgnn return (VXGE_HAL_BADCFG_LAG_PORT_PARTNER_SYNCHRONIZATION); 789221167Sgnn 790221167Sgnn if ((port_config->partner_collecting != 791221167Sgnn VXGE_HAL_LAG_PORT_PARTNER_COLLECTING_DISABLE) && 792221167Sgnn (port_config->partner_collecting != 793221167Sgnn VXGE_HAL_LAG_PORT_PARTNER_COLLECTING_ENABLE) && 794221167Sgnn (port_config->partner_collecting != 795221167Sgnn VXGE_HAL_LAG_PORT_PARTNER_COLLECTING_DEFAULT)) 796221167Sgnn return (VXGE_HAL_BADCFG_LAG_PORT_PARTNER_COLLECTING); 797221167Sgnn 798221167Sgnn if ((port_config->partner_distributing != 799221167Sgnn VXGE_HAL_LAG_PORT_PARTNER_DISTRIBUTING_DISABLE) && 800221167Sgnn (port_config->partner_distributing != 801221167Sgnn VXGE_HAL_LAG_PORT_PARTNER_DISTRIBUTING_ENABLE) && 802221167Sgnn (port_config->partner_distributing != 803221167Sgnn VXGE_HAL_LAG_PORT_PARTNER_DISTRIBUTING_DEFAULT)) 804221167Sgnn return (VXGE_HAL_BADCFG_LAG_PORT_PARTNER_DISTRIBUTING); 805221167Sgnn 806221167Sgnn if ((port_config->partner_distributing != 807221167Sgnn VXGE_HAL_LAG_PORT_PARTNER_DISTRIBUTING_DISABLE) && 808221167Sgnn (port_config->partner_distributing != 809221167Sgnn VXGE_HAL_LAG_PORT_PARTNER_DISTRIBUTING_ENABLE) && 810221167Sgnn (port_config->partner_distributing != 811221167Sgnn VXGE_HAL_LAG_PORT_PARTNER_DISTRIBUTING_DEFAULT)) 812221167Sgnn return (VXGE_HAL_BADCFG_LAG_PORT_PARTNER_DISTRIBUTING); 813221167Sgnn 814221167Sgnn if ((port_config->partner_defaulted != 815221167Sgnn VXGE_HAL_LAG_PORT_PARTNER_DEFAULTED) && 816221167Sgnn (port_config->partner_defaulted != 817221167Sgnn VXGE_HAL_LAG_PORT_PARTNER_NOT_DEFAULTED) && 818221167Sgnn (port_config->partner_defaulted != 819221167Sgnn VXGE_HAL_LAG_PORT_PARTNER_DEFAULTED_DEFAULT)) 820221167Sgnn return (VXGE_HAL_BADCFG_LAG_PORT_PARTNER_DEFAULTED); 821221167Sgnn 822221167Sgnn if ((port_config->partner_expired != 823221167Sgnn VXGE_HAL_LAG_PORT_PARTNER_EXPIRED) && 824221167Sgnn (port_config->partner_expired != 825221167Sgnn VXGE_HAL_LAG_PORT_PARTNER_NOT_EXPIRED) && 826221167Sgnn (port_config->partner_expired != 827221167Sgnn VXGE_HAL_LAG_PORT_PARTNER_EXPIRED_DEFAULT)) 828221167Sgnn return (VXGE_HAL_BADCFG_LAG_PORT_PARTNER_EXPIRED); 829221167Sgnn 830221167Sgnn return (VXGE_HAL_OK); 831221167Sgnn} 832221167Sgnn 833221167Sgnn/* 834221167Sgnn * __hal_device_lag_aggr_config_check - Check aggregator configuration. 835221167Sgnn * @aggr_config: Aggregator configuration information 836221167Sgnn * 837221167Sgnn * Check aggregator configuration 838221167Sgnn * 839221167Sgnn * Returns: VXGE_HAL_OK - success, 840221167Sgnn * otherwise one of the vxge_hal_status_e enumerated error codes. 841221167Sgnn * 842221167Sgnn */ 843221167Sgnnvxge_hal_status_e 844221167Sgnn__hal_device_lag_aggr_config_check(vxge_hal_lag_aggr_config_t *aggr_config) 845221167Sgnn{ 846221167Sgnn if ((aggr_config->aggr_id != VXGE_HAL_LAG_AGGR_AGGR_ID_1) && 847221167Sgnn (aggr_config->aggr_id != VXGE_HAL_LAG_AGGR_AGGR_ID_2)) 848221167Sgnn return (VXGE_HAL_BADCFG_LAG_AGGR_AGGR_ID); 849221167Sgnn 850221167Sgnn if ((aggr_config->use_port_mac_addr != 851221167Sgnn VXGE_HAL_LAG_AGGR_USE_PORT_MAC_ADDR_DISBALE) && 852221167Sgnn (aggr_config->use_port_mac_addr != 853221167Sgnn VXGE_HAL_LAG_AGGR_USE_PORT_MAC_ADDR_ENABLE) && 854221167Sgnn (aggr_config->use_port_mac_addr != 855221167Sgnn VXGE_HAL_LAG_AGGR_USE_PORT_MAC_ADDR_DEFAULT)) 856221167Sgnn return (VXGE_HAL_BADCFG_LAG_AGGR_USE_PORT_MAC_ADDR); 857221167Sgnn 858221167Sgnn if ((aggr_config->mac_addr_sel != 859221167Sgnn VXGE_HAL_LAG_AGGR_MAC_ADDR_SEL_PORT_0) && 860221167Sgnn (aggr_config->mac_addr_sel != 861221167Sgnn VXGE_HAL_LAG_AGGR_MAC_ADDR_SEL_PORT_1) && 862221167Sgnn (aggr_config->mac_addr_sel != 863221167Sgnn VXGE_HAL_LAG_AGGR_MAC_ADDR_SEL_DEFAULT)) 864221167Sgnn return (VXGE_HAL_BADCFG_LAG_AGGR_MAC_ADDR_SEL); 865221167Sgnn 866221167Sgnn if ((aggr_config->admin_key > VXGE_HAL_LAG_AGGR_MAX_ADMIN_KEY) && 867221167Sgnn (aggr_config->admin_key != VXGE_HAL_LAG_AGGR_DEF_ADMIN_KEY)) 868221167Sgnn return (VXGE_HAL_BADCFG_LAG_AGGR_ADMIN_KEY); 869221167Sgnn 870221167Sgnn return (VXGE_HAL_OK); 871221167Sgnn} 872221167Sgnn 873221167Sgnn/* 874221167Sgnn * __hal_device_lag_la_config_check 875221167Sgnn * Check LAG link aggregation mode configuration. 876221167Sgnn * @la_config: LAG configuration information 877221167Sgnn * 878221167Sgnn * Check LAG link aggregation mode configuration 879221167Sgnn * 880221167Sgnn * Returns: VXGE_HAL_OK - success, 881221167Sgnn * otherwise one of the vxge_hal_status_e enumerated error codes. 882221167Sgnn * 883221167Sgnn */ 884221167Sgnnvxge_hal_status_e 885221167Sgnn__hal_device_lag_la_config_check(vxge_hal_lag_la_config_t *la_config) 886221167Sgnn{ 887221167Sgnn if ((la_config->tx_discard != VXGE_HAL_LAG_TX_DISCARD_DISBALE) && 888221167Sgnn (la_config->tx_discard != VXGE_HAL_LAG_TX_DISCARD_ENABLE) && 889221167Sgnn (la_config->tx_discard != VXGE_HAL_LAG_TX_DISCARD_DEFAULT)) 890221167Sgnn return (VXGE_HAL_BADCFG_LAG_TX_DISCARD); 891221167Sgnn 892221167Sgnn if ((la_config->distrib_alg_sel != 893221167Sgnn VXGE_HAL_LAG_DISTRIB_ALG_SEL_SRC_VPATH) && 894221167Sgnn (la_config->distrib_alg_sel != 895221167Sgnn VXGE_HAL_LAG_DISTRIB_ALG_SEL_DEST_MAC_ADDR) && 896221167Sgnn (la_config->distrib_alg_sel != 897221167Sgnn VXGE_HAL_LAG_DISTRIB_ALG_SEL_SRC_MAC_ADDR) && 898221167Sgnn (la_config->distrib_alg_sel != 899221167Sgnn VXGE_HAL_LAG_DISTRIB_ALG_SEL_BOTH_MAC_ADDR) && 900221167Sgnn (la_config->distrib_alg_sel != 901221167Sgnn VXGE_HAL_LAG_DISTRIB_ALG_SEL_DEFAULT)) 902221167Sgnn return (VXGE_HAL_BADCFG_LAG_DISTRIB_ALG_SEL); 903221167Sgnn 904221167Sgnn if ((la_config->distrib_remap_if_fail != 905221167Sgnn VXGE_HAL_LAG_DISTRIB_REMAP_IF_FAIL_DISBALE) && 906221167Sgnn (la_config->distrib_remap_if_fail != 907221167Sgnn VXGE_HAL_LAG_DISTRIB_REMAP_IF_FAIL_ENABLE) && 908221167Sgnn (la_config->distrib_remap_if_fail != 909221167Sgnn VXGE_HAL_LAG_DISTRIB_REMAP_IF_FAIL_DEFAULT)) 910221167Sgnn return (VXGE_HAL_BADCFG_LAG_DISTRIB_REMAP_IF_FAIL); 911221167Sgnn 912221167Sgnn if ((la_config->coll_max_delay > VXGE_HAL_LAG_MAX_COLL_MAX_DELAY) && 913221167Sgnn (la_config->coll_max_delay != VXGE_HAL_LAG_DEF_COLL_MAX_DELAY)) 914221167Sgnn return (VXGE_HAL_BADCFG_LAG_COLL_MAX_DELAY); 915221167Sgnn 916221167Sgnn if ((la_config->rx_discard != VXGE_HAL_LAG_RX_DISCARD_DISBALE) && 917221167Sgnn (la_config->rx_discard != VXGE_HAL_LAG_RX_DISCARD_ENABLE) && 918221167Sgnn (la_config->rx_discard != VXGE_HAL_LAG_RX_DISCARD_DEFAULT)) 919221167Sgnn return (VXGE_HAL_BADCFG_LAG_RX_DISCARD); 920221167Sgnn 921221167Sgnn return (VXGE_HAL_OK); 922221167Sgnn} 923221167Sgnn 924221167Sgnn/* 925221167Sgnn * __hal_device_lag_ap_config_check - Check LAG a/p mode configuration. 926221167Sgnn * @ap_config: LAG configuration information 927221167Sgnn * 928221167Sgnn * Check LAG a/p mode configuration 929221167Sgnn * 930221167Sgnn * Returns: VXGE_HAL_OK - success, 931221167Sgnn * otherwise one of the vxge_hal_status_e enumerated error codes. 932221167Sgnn * 933221167Sgnn */ 934221167Sgnnvxge_hal_status_e 935221167Sgnn__hal_device_lag_ap_config_check(vxge_hal_lag_ap_config_t *ap_config) 936221167Sgnn{ 937221167Sgnn if ((ap_config->hot_standby != 938221167Sgnn VXGE_HAL_LAG_HOT_STANDBY_DISBALE_PORT) && 939221167Sgnn (ap_config->hot_standby != 940221167Sgnn VXGE_HAL_LAG_HOT_STANDBY_KEEP_UP_PORT) && 941221167Sgnn (ap_config->hot_standby != 942221167Sgnn VXGE_HAL_LAG_HOT_STANDBY_DEFAULT)) 943221167Sgnn return (VXGE_HAL_BADCFG_LAG_HOT_STANDBY); 944221167Sgnn 945221167Sgnn if ((ap_config->lacp_decides != VXGE_HAL_LAG_LACP_DECIDES_DISBALE) && 946221167Sgnn (ap_config->lacp_decides != VXGE_HAL_LAG_LACP_DECIDES_ENBALE) && 947221167Sgnn (ap_config->lacp_decides != VXGE_HAL_LAG_LACP_DECIDES_DEFAULT)) 948221167Sgnn return (VXGE_HAL_BADCFG_LAG_LACP_DECIDES); 949221167Sgnn 950221167Sgnn if ((ap_config->pref_active_port != 951221167Sgnn VXGE_HAL_LAG_PREF_ACTIVE_PORT_0) && 952221167Sgnn (ap_config->pref_active_port != 953221167Sgnn VXGE_HAL_LAG_PREF_ACTIVE_PORT_1) && 954221167Sgnn (ap_config->pref_active_port != 955221167Sgnn VXGE_HAL_LAG_PREF_ACTIVE_PORT_DEFAULT)) 956221167Sgnn return (VXGE_HAL_BADCFG_LAG_PREF_ACTIVE_PORT); 957221167Sgnn 958221167Sgnn if ((ap_config->auto_failback != VXGE_HAL_LAG_AUTO_FAILBACK_DISBALE) && 959221167Sgnn (ap_config->auto_failback != VXGE_HAL_LAG_AUTO_FAILBACK_ENBALE) && 960221167Sgnn (ap_config->auto_failback != VXGE_HAL_LAG_AUTO_FAILBACK_DEFAULT)) 961221167Sgnn return (VXGE_HAL_BADCFG_LAG_AUTO_FAILBACK); 962221167Sgnn 963221167Sgnn if ((ap_config->failback_en != VXGE_HAL_LAG_FAILBACK_EN_DISBALE) && 964221167Sgnn (ap_config->failback_en != VXGE_HAL_LAG_FAILBACK_EN_ENBALE) && 965221167Sgnn (ap_config->failback_en != VXGE_HAL_LAG_FAILBACK_EN_DEFAULT)) 966221167Sgnn return (VXGE_HAL_BADCFG_LAG_FAILBACK_EN); 967221167Sgnn 968221167Sgnn if ((ap_config->cold_failover_timeout != 969221167Sgnn VXGE_HAL_LAG_MIN_COLD_FAILOVER_TIMEOUT) && 970221167Sgnn (ap_config->cold_failover_timeout != 971221167Sgnn VXGE_HAL_LAG_MAX_COLD_FAILOVER_TIMEOUT) && 972221167Sgnn (ap_config->cold_failover_timeout != 973221167Sgnn VXGE_HAL_LAG_DEF_COLD_FAILOVER_TIMEOUT)) 974221167Sgnn return (VXGE_HAL_BADCFG_LAG_COLD_FAILOVER_TIMEOUT); 975221167Sgnn 976221167Sgnn if ((ap_config->alt_admin_key != 977221167Sgnn VXGE_HAL_LAG_MIN_ALT_ADMIN_KEY) && 978221167Sgnn (ap_config->alt_admin_key != 979221167Sgnn VXGE_HAL_LAG_MAX_ALT_ADMIN_KEY) && 980221167Sgnn (ap_config->alt_admin_key != 981221167Sgnn VXGE_HAL_LAG_DEF_ALT_ADMIN_KEY)) 982221167Sgnn return (VXGE_HAL_BADCFG_LAG_ALT_ADMIN_KEY); 983221167Sgnn 984221167Sgnn if ((ap_config->alt_aggr != 985221167Sgnn VXGE_HAL_LAG_ALT_AGGR_0) && 986221167Sgnn (ap_config->alt_aggr != 987221167Sgnn VXGE_HAL_LAG_ALT_AGGR_1) && 988221167Sgnn (ap_config->alt_aggr != 989221167Sgnn VXGE_HAL_LAG_ALT_AGGR_DEFAULT)) 990221167Sgnn return (VXGE_HAL_BADCFG_LAG_ALT_AGGR); 991221167Sgnn 992221167Sgnn return (VXGE_HAL_OK); 993221167Sgnn} 994221167Sgnn 995221167Sgnn/* 996221167Sgnn * __hal_device_lag_sl_config_check - Check LAG Single Link mode configuration. 997221167Sgnn * @sl_config: LAG configuration information 998221167Sgnn * 999221167Sgnn * Check LAG Single link mode configuration 1000221167Sgnn * 1001221167Sgnn * Returns: VXGE_HAL_OK - success, 1002221167Sgnn * otherwise one of the vxge_hal_status_e enumerated error codes. 1003221167Sgnn * 1004221167Sgnn */ 1005221167Sgnnvxge_hal_status_e 1006221167Sgnn__hal_device_lag_sl_config_check(vxge_hal_lag_sl_config_t *sl_config) 1007221167Sgnn{ 1008221167Sgnn if ((sl_config->pref_indiv_port != 1009221167Sgnn VXGE_HAL_LAG_PREF_INDIV_PORT_0) && 1010221167Sgnn (sl_config->pref_indiv_port != 1011221167Sgnn VXGE_HAL_LAG_PREF_INDIV_PORT_1) && 1012221167Sgnn (sl_config->pref_indiv_port != 1013221167Sgnn VXGE_HAL_LAG_PREF_INDIV_PORT_DEFAULT)) 1014221167Sgnn return (VXGE_HAL_BADCFG_LAG_PREF_INDIV_PORT); 1015221167Sgnn 1016221167Sgnn return (VXGE_HAL_OK); 1017221167Sgnn} 1018221167Sgnn 1019221167Sgnn/* 1020221167Sgnn * __hal_device_lag_lacp_config_check - Check LACP configuration. 1021221167Sgnn * @lacp_config: LAG configuration information 1022221167Sgnn * 1023221167Sgnn * Check LACP configuration 1024221167Sgnn * 1025221167Sgnn * Returns: VXGE_HAL_OK - success, 1026221167Sgnn * otherwise one of the vxge_hal_status_e enumerated error codes. 1027221167Sgnn * 1028221167Sgnn */ 1029221167Sgnnvxge_hal_status_e 1030221167Sgnn__hal_device_lag_lacp_config_check(vxge_hal_lag_lacp_config_t *lacp_config) 1031221167Sgnn{ 1032221167Sgnn if ((lacp_config->lacp_en != VXGE_HAL_LAG_LACP_EN_DISBALE) && 1033221167Sgnn (lacp_config->lacp_en != VXGE_HAL_LAG_LACP_EN_ENABLE) && 1034221167Sgnn (lacp_config->lacp_en != VXGE_HAL_LAG_LACP_EN_DEFAULT)) 1035221167Sgnn return (VXGE_HAL_BADCFG_LAG_LACP_EN); 1036221167Sgnn 1037221167Sgnn if ((lacp_config->lacp_begin != VXGE_HAL_LAG_LACP_BEGIN_NORMAL) && 1038221167Sgnn (lacp_config->lacp_begin != VXGE_HAL_LAG_LACP_BEGIN_RESET) && 1039221167Sgnn (lacp_config->lacp_begin != VXGE_HAL_LAG_LACP_BEGIN_DEFAULT)) 1040221167Sgnn return (VXGE_HAL_BADCFG_LAG_LACP_BEGIN); 1041221167Sgnn 1042221167Sgnn if ((lacp_config->discard_lacp != VXGE_HAL_LAG_DISCARD_LACP_DISBALE) && 1043221167Sgnn (lacp_config->discard_lacp != VXGE_HAL_LAG_DISCARD_LACP_ENABLE) && 1044221167Sgnn (lacp_config->discard_lacp != VXGE_HAL_LAG_DISCARD_LACP_DEFAULT)) 1045221167Sgnn return (VXGE_HAL_BADCFG_LAG_DISCARD_LACP); 1046221167Sgnn 1047221167Sgnn if ((lacp_config->liberal_len_chk != 1048221167Sgnn VXGE_HAL_LAG_LIBERAL_LEN_CHK_DISBALE) && 1049221167Sgnn (lacp_config->liberal_len_chk != 1050221167Sgnn VXGE_HAL_LAG_LIBERAL_LEN_CHK_ENABLE) && 1051221167Sgnn (lacp_config->liberal_len_chk != 1052221167Sgnn VXGE_HAL_LAG_LIBERAL_LEN_CHK_DEFAULT)) 1053221167Sgnn return (VXGE_HAL_BADCFG_LAG_LIBERAL_LEN_CHK); 1054221167Sgnn 1055221167Sgnn if ((lacp_config->marker_gen_recv_en != 1056221167Sgnn VXGE_HAL_LAG_MARKER_GEN_RECV_EN_DISBALE) && 1057221167Sgnn (lacp_config->marker_gen_recv_en != 1058221167Sgnn VXGE_HAL_LAG_MARKER_GEN_RECV_EN_ENABLE) && 1059221167Sgnn (lacp_config->marker_gen_recv_en != 1060221167Sgnn VXGE_HAL_LAG_MARKER_GEN_RECV_EN_DEFAULT)) 1061221167Sgnn return (VXGE_HAL_BADCFG_LAG_MARKER_GEN_RECV_EN); 1062221167Sgnn 1063221167Sgnn if ((lacp_config->marker_resp_en != 1064221167Sgnn VXGE_HAL_LAG_MARKER_RESP_EN_DISBALE) && 1065221167Sgnn (lacp_config->marker_resp_en != 1066221167Sgnn VXGE_HAL_LAG_MARKER_RESP_EN_ENABLE) && 1067221167Sgnn (lacp_config->marker_resp_en != 1068221167Sgnn VXGE_HAL_LAG_MARKER_RESP_EN_DEFAULT)) 1069221167Sgnn return (VXGE_HAL_BADCFG_LAG_MARKER_RESP_EN); 1070221167Sgnn 1071221167Sgnn if ((lacp_config->marker_resp_timeout != 1072221167Sgnn VXGE_HAL_LAG_MIN_MARKER_RESP_TIMEOUT) && 1073221167Sgnn (lacp_config->marker_resp_timeout != 1074221167Sgnn VXGE_HAL_LAG_MAX_MARKER_RESP_TIMEOUT) && 1075221167Sgnn (lacp_config->marker_resp_timeout != 1076221167Sgnn VXGE_HAL_LAG_DEF_MARKER_RESP_TIMEOUT)) 1077221167Sgnn return (VXGE_HAL_BADCFG_LAG_MARKER_RESP_TIMEOUT); 1078221167Sgnn 1079221167Sgnn if ((lacp_config->slow_proto_mrkr_min_interval != 1080221167Sgnn VXGE_HAL_LAG_MIN_SLOW_PROTO_MRKR_MIN_INTERVAL) && 1081221167Sgnn (lacp_config->slow_proto_mrkr_min_interval != 1082221167Sgnn VXGE_HAL_LAG_MAX_SLOW_PROTO_MRKR_MIN_INTERVAL) && 1083221167Sgnn (lacp_config->slow_proto_mrkr_min_interval != 1084221167Sgnn VXGE_HAL_LAG_DEF_SLOW_PROTO_MRKR_MIN_INTERVAL)) 1085221167Sgnn return (VXGE_HAL_BADCFG_LAG_SLOW_PROTO_MRKR_MIN_INTERVAL); 1086221167Sgnn 1087221167Sgnn if ((lacp_config->throttle_mrkr_resp != 1088221167Sgnn VXGE_HAL_LAG_THROTTLE_MRKR_RESP_DISBALE) && 1089221167Sgnn (lacp_config->throttle_mrkr_resp != 1090221167Sgnn VXGE_HAL_LAG_THROTTLE_MRKR_RESP_ENABLE) && 1091221167Sgnn (lacp_config->throttle_mrkr_resp != 1092221167Sgnn VXGE_HAL_LAG_THROTTLE_MRKR_RESP_DEFAULT)) 1093221167Sgnn return (VXGE_HAL_BADCFG_LAG_THROTTLE_MRKR_RESP); 1094221167Sgnn 1095221167Sgnn return (VXGE_HAL_OK); 1096221167Sgnn} 1097221167Sgnn 1098221167Sgnn/* 1099221167Sgnn * __hal_device_lag_config_check - Check link aggregation configuration. 1100221167Sgnn * @lag_config: LAG configuration information 1101221167Sgnn * 1102221167Sgnn * Check link aggregation configuration 1103221167Sgnn * 1104221167Sgnn * Returns: VXGE_HAL_OK - success, 1105221167Sgnn * otherwise one of the vxge_hal_status_e enumerated error codes. 1106221167Sgnn * 1107221167Sgnn */ 1108221167Sgnnvxge_hal_status_e 1109221167Sgnn__hal_device_lag_config_check(vxge_hal_lag_config_t *lag_config) 1110221167Sgnn{ 1111221167Sgnn u32 i; 1112221167Sgnn vxge_hal_status_e status; 1113221167Sgnn 1114221167Sgnn if ((lag_config->lag_en != VXGE_HAL_LAG_LAG_EN_DISABLE) && 1115221167Sgnn (lag_config->lag_en != VXGE_HAL_LAG_LAG_EN_ENABLE) && 1116221167Sgnn (lag_config->lag_en != VXGE_HAL_LAG_LAG_EN_DEFAULT)) 1117221167Sgnn return (VXGE_HAL_BADCFG_LAG_LAG_EN); 1118221167Sgnn 1119221167Sgnn if ((lag_config->lag_mode != VXGE_HAL_LAG_LAG_MODE_LAG) && 1120221167Sgnn (lag_config->lag_mode != 1121221167Sgnn VXGE_HAL_LAG_LAG_MODE_ACTIVE_PASSIVE_FAILOVER) && 1122221167Sgnn (lag_config->lag_mode != VXGE_HAL_LAG_LAG_MODE_SINGLE_LINK) && 1123221167Sgnn (lag_config->lag_mode != VXGE_HAL_LAG_LAG_MODE_DEFAULT)) 1124221167Sgnn return (VXGE_HAL_BADCFG_LAG_LAG_MODE); 1125221167Sgnn 1126221167Sgnn status = __hal_device_lag_la_config_check(&lag_config->la_mode_config); 1127221167Sgnn if (status == VXGE_HAL_OK) 1128221167Sgnn return (status); 1129221167Sgnn 1130221167Sgnn status = __hal_device_lag_ap_config_check(&lag_config->ap_mode_config); 1131221167Sgnn if (status == VXGE_HAL_OK) 1132221167Sgnn return (status); 1133221167Sgnn 1134221167Sgnn status = __hal_device_lag_sl_config_check(&lag_config->sl_mode_config); 1135221167Sgnn if (status == VXGE_HAL_OK) 1136221167Sgnn return (status); 1137221167Sgnn 1138221167Sgnn status = __hal_device_lag_lacp_config_check(&lag_config->lacp_config); 1139221167Sgnn if (status == VXGE_HAL_OK) 1140221167Sgnn return (status); 1141221167Sgnn 1142221167Sgnn if ((lag_config->incr_tx_aggr_stats != 1143221167Sgnn VXGE_HAL_LAG_INCR_TX_AGGR_STATS_DISBALE) && 1144221167Sgnn (lag_config->incr_tx_aggr_stats != 1145221167Sgnn VXGE_HAL_LAG_INCR_TX_AGGR_STATS_ENABLE) && 1146221167Sgnn (lag_config->incr_tx_aggr_stats != 1147221167Sgnn VXGE_HAL_LAG_INCR_TX_AGGR_STATS_DEFAULT)) 1148221167Sgnn return (VXGE_HAL_BADCFG_LAG_TX_AGGR_STATS); 1149221167Sgnn 1150221167Sgnn for (i = 0; i < VXGE_HAL_LAG_PORT_MAX_PORTS; i++) { 1151221167Sgnn 1152221167Sgnn if ((status = __hal_device_lag_port_config_check( 1153221167Sgnn &lag_config->port_config[i])) != VXGE_HAL_OK) 1154221167Sgnn return (status); 1155221167Sgnn 1156221167Sgnn } 1157221167Sgnn 1158221167Sgnn for (i = 0; i < VXGE_HAL_LAG_AGGR_MAX_PORTS; i++) { 1159221167Sgnn 1160221167Sgnn if ((status = __hal_device_lag_aggr_config_check( 1161221167Sgnn &lag_config->aggr_config[i])) != VXGE_HAL_OK) 1162221167Sgnn return (status); 1163221167Sgnn 1164221167Sgnn } 1165221167Sgnn 1166221167Sgnn if ((lag_config->sys_pri > VXGE_HAL_LAG_MAX_SYS_PRI) && 1167221167Sgnn (lag_config->sys_pri != VXGE_HAL_LAG_DEF_SYS_PRI)) 1168221167Sgnn return (VXGE_HAL_BADCFG_LAG_SYS_PRI); 1169221167Sgnn 1170221167Sgnn if ((lag_config->use_port_mac_addr != 1171221167Sgnn VXGE_HAL_LAG_USE_PORT_MAC_ADDR_DISBALE) && 1172221167Sgnn (lag_config->use_port_mac_addr != 1173221167Sgnn VXGE_HAL_LAG_USE_PORT_MAC_ADDR_ENABLE) && 1174221167Sgnn (lag_config->use_port_mac_addr != 1175221167Sgnn VXGE_HAL_LAG_USE_PORT_MAC_ADDR_DEFAULT)) 1176221167Sgnn return (VXGE_HAL_BADCFG_LAG_USE_PORT_MAC_ADDR); 1177221167Sgnn 1178221167Sgnn if ((lag_config->mac_addr_sel != 1179221167Sgnn VXGE_HAL_LAG_MAC_ADDR_SEL_PORT_0) && 1180221167Sgnn (lag_config->mac_addr_sel != 1181221167Sgnn VXGE_HAL_LAG_MAC_ADDR_SEL_PORT_1) && 1182221167Sgnn (lag_config->mac_addr_sel != 1183221167Sgnn VXGE_HAL_LAG_MAC_ADDR_SEL_DEFAULT)) 1184221167Sgnn return (VXGE_HAL_BADCFG_LAG_MAC_ADDR_SEL); 1185221167Sgnn 1186221167Sgnn if ((lag_config->fast_per_time > VXGE_HAL_LAG_MAX_FAST_PER_TIME) && 1187221167Sgnn (lag_config->fast_per_time != VXGE_HAL_LAG_DEF_FAST_PER_TIME)) 1188221167Sgnn return (VXGE_HAL_BADCFG_LAG_FAST_PER_TIME); 1189221167Sgnn 1190221167Sgnn if ((lag_config->slow_per_time > VXGE_HAL_LAG_MAX_SLOW_PER_TIME) && 1191221167Sgnn (lag_config->slow_per_time != VXGE_HAL_LAG_DEF_SLOW_PER_TIME)) 1192221167Sgnn return (VXGE_HAL_BADCFG_LAG_SLOW_PER_TIME); 1193221167Sgnn 1194221167Sgnn if ((lag_config->short_timeout > VXGE_HAL_LAG_MAX_SHORT_TIMEOUT) && 1195221167Sgnn (lag_config->short_timeout != VXGE_HAL_LAG_DEF_SHORT_TIMEOUT)) 1196221167Sgnn return (VXGE_HAL_BADCFG_LAG_SHORT_TIMEOUT); 1197221167Sgnn 1198221167Sgnn if ((lag_config->long_timeout > VXGE_HAL_LAG_MAX_LONG_TIMEOUT) && 1199221167Sgnn (lag_config->long_timeout != VXGE_HAL_LAG_DEF_LONG_TIMEOUT)) 1200221167Sgnn return (VXGE_HAL_BADCFG_LAG_LONG_TIMEOUT); 1201221167Sgnn 1202221167Sgnn if ((lag_config->churn_det_time > VXGE_HAL_LAG_MAX_CHURN_DET_TIME) && 1203221167Sgnn (lag_config->churn_det_time != VXGE_HAL_LAG_DEF_CHURN_DET_TIME)) 1204221167Sgnn return (VXGE_HAL_BADCFG_LAG_CHURN_DET_TIME); 1205221167Sgnn 1206221167Sgnn if ((lag_config->aggr_wait_time > VXGE_HAL_LAG_MAX_AGGR_WAIT_TIME) && 1207221167Sgnn (lag_config->aggr_wait_time != VXGE_HAL_LAG_DEF_AGGR_WAIT_TIME)) 1208221167Sgnn return (VXGE_HAL_BADCFG_LAG_AGGR_WAIT_TIME); 1209221167Sgnn 1210221167Sgnn if ((lag_config->short_timer_scale != 1211221167Sgnn VXGE_HAL_LAG_SHORT_TIMER_SCALE_1X) && 1212221167Sgnn (lag_config->short_timer_scale != 1213221167Sgnn VXGE_HAL_LAG_SHORT_TIMER_SCALE_10X) && 1214221167Sgnn (lag_config->short_timer_scale != 1215221167Sgnn VXGE_HAL_LAG_SHORT_TIMER_SCALE_100X) && 1216221167Sgnn (lag_config->short_timer_scale != 1217221167Sgnn VXGE_HAL_LAG_SHORT_TIMER_SCALE_1000X) && 1218221167Sgnn (lag_config->short_timer_scale != 1219221167Sgnn VXGE_HAL_LAG_SHORT_TIMER_SCALE_DEFAULT)) 1220221167Sgnn return (VXGE_HAL_BADCFG_LAG_SHORT_TIMER_SCALE); 1221221167Sgnn 1222221167Sgnn if ((lag_config->long_timer_scale != 1223221167Sgnn VXGE_HAL_LAG_LONG_TIMER_SCALE_1X) && 1224221167Sgnn (lag_config->long_timer_scale != 1225221167Sgnn VXGE_HAL_LAG_LONG_TIMER_SCALE_10X) && 1226221167Sgnn (lag_config->long_timer_scale != 1227221167Sgnn VXGE_HAL_LAG_LONG_TIMER_SCALE_100X) && 1228221167Sgnn (lag_config->long_timer_scale != 1229221167Sgnn VXGE_HAL_LAG_LONG_TIMER_SCALE_1000X) && 1230221167Sgnn (lag_config->long_timer_scale != 1231221167Sgnn VXGE_HAL_LAG_LONG_TIMER_SCALE_10000X) && 1232221167Sgnn (lag_config->long_timer_scale != 1233221167Sgnn VXGE_HAL_LAG_LONG_TIMER_SCALE_100000X) && 1234221167Sgnn (lag_config->long_timer_scale != 1235221167Sgnn VXGE_HAL_LAG_LONG_TIMER_SCALE_1000000X) && 1236221167Sgnn (lag_config->long_timer_scale != 1237221167Sgnn VXGE_HAL_LAG_LONG_TIMER_SCALE_DEFAULT)) 1238221167Sgnn return (VXGE_HAL_BADCFG_LAG_LONG_TIMER_SCALE); 1239221167Sgnn 1240221167Sgnn return (VXGE_HAL_OK); 1241221167Sgnn} 1242221167Sgnn 1243221167Sgnn/* 1244221167Sgnn * __hal_vpath_qos_config_check - Check vpath QOS configuration. 1245221167Sgnn * @config: Vpath QOS configuration information 1246221167Sgnn * 1247221167Sgnn * Check the vpath QOS configuration 1248221167Sgnn * 1249221167Sgnn * Returns: VXGE_HAL_OK - success, 1250221167Sgnn * otherwise one of the vxge_hal_status_e {} enumerated error codes. 1251221167Sgnn * 1252221167Sgnn */ 1253221167Sgnnvxge_hal_status_e 1254221167Sgnn__hal_vpath_qos_config_check(vxge_hal_vpath_qos_config_t *config) 1255221167Sgnn{ 1256221167Sgnn if ((config->priority > VXGE_HAL_VPATH_QOS_PRIORITY_MAX) && 1257221167Sgnn (config->priority != VXGE_HAL_VPATH_QOS_PRIORITY_DEFAULT)) 1258221167Sgnn return (VXGE_HAL_BADCFG_VPATH_QOS_PRIORITY); 1259221167Sgnn 1260221167Sgnn if ((config->min_bandwidth > 1261221167Sgnn VXGE_HAL_VPATH_QOS_MIN_BANDWIDTH_MAX) && 1262221167Sgnn (config->min_bandwidth != 1263221167Sgnn VXGE_HAL_VPATH_QOS_MIN_BANDWIDTH_DEFAULT)) 1264221167Sgnn return (VXGE_HAL_BADCFG_VPATH_QOS_MIN_BANDWIDTH); 1265221167Sgnn 1266221167Sgnn if ((config->max_bandwidth > 1267221167Sgnn VXGE_HAL_VPATH_QOS_MAX_BANDWIDTH_MAX) && 1268221167Sgnn (config->max_bandwidth != 1269221167Sgnn VXGE_HAL_VPATH_QOS_MAX_BANDWIDTH_DEFAULT)) 1270221167Sgnn return (VXGE_HAL_BADCFG_VPATH_QOS_MAX_BANDWIDTH); 1271221167Sgnn 1272221167Sgnn return (VXGE_HAL_OK); 1273221167Sgnn} 1274221167Sgnn 1275221167Sgnn/* 1276221167Sgnn * __hal_mrpcim_config_check - Check mrpcim configuration. 1277221167Sgnn * @config: mrpcim configuration information 1278221167Sgnn * 1279221167Sgnn * Check the mrpcim configuration 1280221167Sgnn * 1281221167Sgnn * Returns: VXGE_HAL_OK - success, 1282221167Sgnn * otherwise one of the vxge_hal_status_e {} enumerated error codes. 1283221167Sgnn * 1284221167Sgnn */ 1285221167Sgnnvxge_hal_status_e 1286221167Sgnn__hal_mrpcim_config_check(vxge_hal_mrpcim_config_t *config) 1287221167Sgnn{ 1288221167Sgnn u32 i; 1289221167Sgnn vxge_hal_status_e status = VXGE_HAL_OK; 1290221167Sgnn 1291221167Sgnn if ((status = __hal_device_mac_config_check(&config->mac_config)) != 1292221167Sgnn VXGE_HAL_OK) 1293221167Sgnn return (status); 1294221167Sgnn 1295221167Sgnn if ((status = __hal_device_lag_config_check(&config->lag_config)) != 1296221167Sgnn VXGE_HAL_OK) 1297221167Sgnn return (status); 1298221167Sgnn 1299221167Sgnn for (i = 0; i < VXGE_HAL_MAX_VIRTUAL_PATHS; i++) { 1300221167Sgnn 1301221167Sgnn if ((status = __hal_vpath_qos_config_check( 1302221167Sgnn &config->vp_qos[i])) != VXGE_HAL_OK) 1303221167Sgnn return (status); 1304221167Sgnn 1305221167Sgnn } 1306221167Sgnn 1307221167Sgnn return (VXGE_HAL_OK); 1308221167Sgnn} 1309221167Sgnn 1310221167Sgnn/* 1311221167Sgnn * __hal_device_ring_config_check - Check ring configuration. 1312221167Sgnn * @ring_config: Device configuration information 1313221167Sgnn * 1314221167Sgnn * Check the ring configuration 1315221167Sgnn * 1316221167Sgnn * Returns: VXGE_HAL_OK - success, 1317221167Sgnn * otherwise one of the vxge_hal_status_e {} enumerated error codes. 1318221167Sgnn * 1319221167Sgnn */ 1320221167Sgnnvxge_hal_status_e 1321221167Sgnn__hal_device_ring_config_check(vxge_hal_ring_config_t *ring_config) 1322221167Sgnn{ 1323221167Sgnn if ((ring_config->enable != VXGE_HAL_RING_ENABLE) && 1324221167Sgnn (ring_config->enable != VXGE_HAL_RING_DISABLE)) 1325221167Sgnn return (VXGE_HAL_BADCFG_RING_ENABLE); 1326221167Sgnn 1327221167Sgnn if ((ring_config->ring_length < VXGE_HAL_MIN_RING_LENGTH) || 1328221167Sgnn (ring_config->ring_length > VXGE_HAL_MAX_RING_LENGTH)) 1329221167Sgnn return (VXGE_HAL_BADCFG_RING_LENGTH); 1330221167Sgnn 1331221167Sgnn if ((ring_config->buffer_mode < VXGE_HAL_RING_RXD_BUFFER_MODE_1) || 1332221167Sgnn (ring_config->buffer_mode > VXGE_HAL_RING_RXD_BUFFER_MODE_5)) 1333221167Sgnn return (VXGE_HAL_BADCFG_RING_RXD_BUFFER_MODE); 1334221167Sgnn 1335221167Sgnn if ((ring_config->scatter_mode != VXGE_HAL_RING_SCATTER_MODE_A) && 1336221167Sgnn (ring_config->scatter_mode != VXGE_HAL_RING_SCATTER_MODE_B) && 1337221167Sgnn (ring_config->scatter_mode != VXGE_HAL_RING_SCATTER_MODE_C) && 1338221167Sgnn (ring_config->scatter_mode != 1339221167Sgnn VXGE_HAL_RING_SCATTER_MODE_USE_FLASH_DEFAULT)) 1340221167Sgnn return (VXGE_HAL_BADCFG_RING_SCATTER_MODE); 1341221167Sgnn 1342221167Sgnn if ((ring_config->post_mode != VXGE_HAL_RING_POST_MODE_LEGACY) && 1343221167Sgnn (ring_config->post_mode != VXGE_HAL_RING_POST_MODE_DOORBELL) && 1344221167Sgnn (ring_config->post_mode != 1345221167Sgnn VXGE_HAL_RING_POST_MODE_USE_FLASH_DEFAULT)) 1346221167Sgnn return (VXGE_HAL_BADCFG_RING_POST_MODE); 1347221167Sgnn 1348221167Sgnn if ((ring_config->max_frm_len > VXGE_HAL_MAX_RING_MAX_FRM_LEN) && 1349221167Sgnn (ring_config->max_frm_len != VXGE_HAL_MAX_RING_FRM_LEN_USE_MTU)) 1350221167Sgnn return (VXGE_HAL_BADCFG_RING_MAX_FRM_LEN); 1351221167Sgnn 1352221167Sgnn if ((ring_config->no_snoop_bits > VXGE_HAL_RING_NO_SNOOP_ALL) && 1353221167Sgnn (ring_config->no_snoop_bits != 1354221167Sgnn VXGE_HAL_RING_NO_SNOOP_USE_FLASH_DEFAULT)) 1355221167Sgnn return (VXGE_HAL_BADCFG_RING_NO_SNOOP_ALL); 1356221167Sgnn 1357221167Sgnn if ((ring_config->rx_timer_val > VXGE_HAL_RING_MAX_RX_TIMER_VAL) && 1358221167Sgnn (ring_config->rx_timer_val != 1359221167Sgnn VXGE_HAL_RING_USE_FLASH_DEFAULT_RX_TIMER_VAL)) 1360221167Sgnn return (VXGE_HAL_BADCFG_RING_TIMER_VAL); 1361221167Sgnn 1362221167Sgnn if ((ring_config->greedy_return != 1363221167Sgnn VXGE_HAL_RING_GREEDY_RETURN_ENABLE) && 1364221167Sgnn (ring_config->greedy_return != 1365221167Sgnn VXGE_HAL_RING_GREEDY_RETURN_DISABLE) && 1366221167Sgnn (ring_config->greedy_return != 1367221167Sgnn VXGE_HAL_RING_GREEDY_RETURN_USE_FLASH_DEFAULT)) 1368221167Sgnn return (VXGE_HAL_BADCFG_RING_GREEDY_RETURN); 1369221167Sgnn 1370221167Sgnn if ((ring_config->rx_timer_ci != 1371221167Sgnn VXGE_HAL_RING_RX_TIMER_CI_ENABLE) && 1372221167Sgnn (ring_config->rx_timer_ci != 1373221167Sgnn VXGE_HAL_RING_RX_TIMER_CI_DISABLE) && 1374221167Sgnn (ring_config->rx_timer_ci != 1375221167Sgnn VXGE_HAL_RING_RX_TIMER_CI_USE_FLASH_DEFAULT)) 1376221167Sgnn return (VXGE_HAL_BADCFG_RING_TIMER_CI); 1377221167Sgnn 1378221167Sgnn if (((ring_config->backoff_interval_us < 1379221167Sgnn VXGE_HAL_MIN_BACKOFF_INTERVAL_US) || 1380221167Sgnn (ring_config->backoff_interval_us > 1381221167Sgnn VXGE_HAL_MAX_BACKOFF_INTERVAL_US)) && 1382221167Sgnn (ring_config->backoff_interval_us != 1383221167Sgnn VXGE_HAL_USE_FLASH_DEFAULT_BACKOFF_INTERVAL_US)) 1384221167Sgnn return (VXGE_HAL_BADCFG_RING_BACKOFF_INTERVAL_US); 1385221167Sgnn 1386221167Sgnn if ((ring_config->indicate_max_pkts < 1387221167Sgnn VXGE_HAL_MIN_RING_INDICATE_MAX_PKTS) || 1388221167Sgnn (ring_config->indicate_max_pkts > 1389221167Sgnn VXGE_HAL_MAX_RING_INDICATE_MAX_PKTS)) 1390221167Sgnn return (VXGE_HAL_BADCFG_RING_INDICATE_MAX_PKTS); 1391221167Sgnn 1392221167Sgnn return (VXGE_HAL_OK); 1393221167Sgnn} 1394221167Sgnn 1395221167Sgnn/* 1396221167Sgnn * __hal_device_fifo_config_check - Check fifo configuration. 1397221167Sgnn * @fifo_config: Fifo configuration information 1398221167Sgnn * 1399221167Sgnn * Check the fifo configuration 1400221167Sgnn * 1401221167Sgnn * Returns: VXGE_HAL_OK - success, 1402221167Sgnn * otherwise one of the vxge_hal_status_e {} enumerated error codes. 1403221167Sgnn * 1404221167Sgnn */ 1405221167Sgnnvxge_hal_status_e 1406221167Sgnn__hal_device_fifo_config_check(vxge_hal_fifo_config_t *fifo_config) 1407221167Sgnn{ 1408221167Sgnn if ((fifo_config->enable != VXGE_HAL_FIFO_ENABLE) && 1409221167Sgnn (fifo_config->enable != VXGE_HAL_FIFO_DISABLE)) 1410221167Sgnn return (VXGE_HAL_BADCFG_FIFO_ENABLE); 1411221167Sgnn 1412221167Sgnn if ((fifo_config->fifo_length < VXGE_HAL_MIN_FIFO_LENGTH) || 1413221167Sgnn (fifo_config->fifo_length > VXGE_HAL_MAX_FIFO_LENGTH)) 1414221167Sgnn return (VXGE_HAL_BADCFG_FIFO_LENGTH); 1415221167Sgnn 1416221167Sgnn if ((fifo_config->max_frags < VXGE_HAL_MIN_FIFO_FRAGS) || 1417221167Sgnn (fifo_config->max_frags > VXGE_HAL_MAX_FIFO_FRAGS)) 1418221167Sgnn return (VXGE_HAL_BADCFG_FIFO_FRAGS); 1419221167Sgnn 1420221167Sgnn if (fifo_config->alignment_size > VXGE_HAL_MAX_FIFO_ALIGNMENT_SIZE) 1421221167Sgnn return (VXGE_HAL_BADCFG_FIFO_ALIGNMENT_SIZE); 1422221167Sgnn 1423221167Sgnn if (fifo_config->max_aligned_frags > fifo_config->max_frags) 1424221167Sgnn return (VXGE_HAL_BADCFG_FIFO_MAX_FRAGS); 1425221167Sgnn 1426221167Sgnn if ((fifo_config->intr != VXGE_HAL_FIFO_QUEUE_INTR_ENABLE) && 1427221167Sgnn (fifo_config->intr != VXGE_HAL_FIFO_QUEUE_INTR_DISABLE)) 1428221167Sgnn return (VXGE_HAL_BADCFG_FIFO_QUEUE_INTR); 1429221167Sgnn 1430221167Sgnn if (fifo_config->no_snoop_bits > VXGE_HAL_FIFO_NO_SNOOP_ALL) 1431221167Sgnn return (VXGE_HAL_BADCFG_FIFO_NO_SNOOP_ALL); 1432221167Sgnn 1433221167Sgnn return (VXGE_HAL_OK); 1434221167Sgnn} 1435221167Sgnn 1436221167Sgnn 1437221167Sgnn/* 1438221167Sgnn * __hal_device_tim_intr_config_check - Check tim intr configuration. 1439221167Sgnn * @tim_intr_config: tim intr configuration information 1440221167Sgnn * 1441221167Sgnn * Check the tim intr configuration 1442221167Sgnn * 1443221167Sgnn * Returns: VXGE_HAL_OK - success, 1444221167Sgnn * otherwise one of the vxge_hal_status_e {} enumerated error codes. 1445221167Sgnn * 1446221167Sgnn */ 1447221167Sgnnvxge_hal_status_e 1448221167Sgnn__hal_device_tim_intr_config_check(vxge_hal_tim_intr_config_t *tim_intr_config) 1449221167Sgnn{ 1450221167Sgnn if ((tim_intr_config->intr_enable != VXGE_HAL_TIM_INTR_ENABLE) && 1451221167Sgnn (tim_intr_config->intr_enable != VXGE_HAL_TIM_INTR_DISABLE)) 1452221167Sgnn return (VXGE_HAL_BADCFG_TIM_INTR_ENABLE); 1453221167Sgnn 1454221167Sgnn if ((tim_intr_config->btimer_val > 1455221167Sgnn VXGE_HAL_MAX_TIM_BTIMER_VAL) && 1456221167Sgnn (tim_intr_config->btimer_val != 1457221167Sgnn VXGE_HAL_USE_FLASH_DEFAULT_TIM_BTIMER_VAL)) 1458221167Sgnn return (VXGE_HAL_BADCFG_TIM_BTIMER_VAL); 1459221167Sgnn 1460221167Sgnn if ((tim_intr_config->timer_ac_en != 1461221167Sgnn VXGE_HAL_TIM_TIMER_AC_ENABLE) && 1462221167Sgnn (tim_intr_config->timer_ac_en != 1463221167Sgnn VXGE_HAL_TIM_TIMER_AC_DISABLE) && 1464221167Sgnn (tim_intr_config->timer_ac_en != 1465221167Sgnn VXGE_HAL_TIM_TIMER_AC_USE_FLASH_DEFAULT)) 1466221167Sgnn return (VXGE_HAL_BADCFG_TIM_TIMER_AC_EN); 1467221167Sgnn 1468221167Sgnn if ((tim_intr_config->timer_ci_en != 1469221167Sgnn VXGE_HAL_TIM_TIMER_CI_ENABLE) && 1470221167Sgnn (tim_intr_config->timer_ci_en != 1471221167Sgnn VXGE_HAL_TIM_TIMER_CI_DISABLE) && 1472221167Sgnn (tim_intr_config->timer_ci_en != 1473221167Sgnn VXGE_HAL_TIM_TIMER_CI_USE_FLASH_DEFAULT)) 1474221167Sgnn return (VXGE_HAL_BADCFG_TIM_TIMER_CI_EN); 1475221167Sgnn 1476221167Sgnn if ((tim_intr_config->timer_ri_en != 1477221167Sgnn VXGE_HAL_TIM_TIMER_RI_ENABLE) && 1478221167Sgnn (tim_intr_config->timer_ri_en != 1479221167Sgnn VXGE_HAL_TIM_TIMER_RI_DISABLE) && 1480221167Sgnn (tim_intr_config->timer_ri_en != 1481221167Sgnn VXGE_HAL_TIM_TIMER_RI_USE_FLASH_DEFAULT)) 1482221167Sgnn return (VXGE_HAL_BADCFG_TIM_TIMER_RI_EN); 1483221167Sgnn 1484221167Sgnn if ((tim_intr_config->rtimer_event_sf > 1485221167Sgnn VXGE_HAL_MAX_TIM_RTIMER_EVENT_SF) && 1486221167Sgnn (tim_intr_config->rtimer_event_sf != 1487221167Sgnn VXGE_HAL_USE_FLASH_DEFAULT_TIM_RTIMER_EVENT_SF)) 1488221167Sgnn return (VXGE_HAL_BADCFG_TIM_BTIMER_EVENT_SF); 1489221167Sgnn 1490221167Sgnn if ((tim_intr_config->rtimer_val > 1491221167Sgnn VXGE_HAL_MAX_TIM_RTIMER_VAL) && 1492221167Sgnn (tim_intr_config->rtimer_val != 1493221167Sgnn VXGE_HAL_USE_FLASH_DEFAULT_TIM_RTIMER_VAL)) 1494221167Sgnn return (VXGE_HAL_BADCFG_TIM_RTIMER_VAL); 1495221167Sgnn 1496221167Sgnn if ((((tim_intr_config->util_sel > 19) && 1497221167Sgnn (tim_intr_config->util_sel < 32)) || 1498221167Sgnn ((tim_intr_config->util_sel > 48) && 1499221167Sgnn (tim_intr_config->util_sel < 63))) && 1500221167Sgnn (tim_intr_config->util_sel != 1501221167Sgnn VXGE_HAL_TIM_UTIL_SEL_USE_FLASH_DEFAULT)) 1502221167Sgnn return (VXGE_HAL_BADCFG_TIM_UTIL_SEL); 1503221167Sgnn 1504221167Sgnn if ((tim_intr_config->ltimer_val > 1505221167Sgnn VXGE_HAL_MAX_TIM_LTIMER_VAL) && 1506221167Sgnn (tim_intr_config->ltimer_val != 1507221167Sgnn VXGE_HAL_USE_FLASH_DEFAULT_TIM_LTIMER_VAL)) 1508221167Sgnn return (VXGE_HAL_BADCFG_TIM_LTIMER_VAL); 1509221167Sgnn 1510221167Sgnn if ((tim_intr_config->txfrm_cnt_en != 1511221167Sgnn VXGE_HAL_TXFRM_CNT_EN_ENABLE) && 1512221167Sgnn (tim_intr_config->txfrm_cnt_en != 1513221167Sgnn VXGE_HAL_TXFRM_CNT_EN_DISABLE) && 1514221167Sgnn (tim_intr_config->txfrm_cnt_en != 1515221167Sgnn VXGE_HAL_TXFRM_CNT_EN_USE_FLASH_DEFAULT)) 1516221167Sgnn return (VXGE_HAL_BADCFG_TXFRM_CNT_EN); 1517221167Sgnn 1518221167Sgnn if ((tim_intr_config->txd_cnt_en != 1519221167Sgnn VXGE_HAL_TXD_CNT_EN_ENABLE) && 1520221167Sgnn (tim_intr_config->txd_cnt_en != 1521221167Sgnn VXGE_HAL_TXD_CNT_EN_DISABLE) && 1522221167Sgnn (tim_intr_config->txd_cnt_en != 1523221167Sgnn VXGE_HAL_TXD_CNT_EN_USE_FLASH_DEFAULT)) 1524221167Sgnn return (VXGE_HAL_BADCFG_TXD_CNT_EN); 1525221167Sgnn 1526221167Sgnn if ((tim_intr_config->urange_a > 1527221167Sgnn VXGE_HAL_MAX_TIM_URANGE_A) && 1528221167Sgnn (tim_intr_config->urange_a != 1529221167Sgnn VXGE_HAL_USE_FLASH_DEFAULT_TIM_URANGE_A)) 1530221167Sgnn return (VXGE_HAL_BADCFG_TIM_URANGE_A); 1531221167Sgnn 1532221167Sgnn if ((tim_intr_config->uec_a > 1533221167Sgnn VXGE_HAL_MAX_TIM_UEC_A) && 1534221167Sgnn (tim_intr_config->uec_a != 1535221167Sgnn VXGE_HAL_USE_FLASH_DEFAULT_TIM_UEC_A)) 1536221167Sgnn return (VXGE_HAL_BADCFG_TIM_UEC_A); 1537221167Sgnn 1538221167Sgnn if ((tim_intr_config->urange_b > 1539221167Sgnn VXGE_HAL_MAX_TIM_URANGE_B) && 1540221167Sgnn (tim_intr_config->urange_b != 1541221167Sgnn VXGE_HAL_USE_FLASH_DEFAULT_TIM_URANGE_B)) 1542221167Sgnn return (VXGE_HAL_BADCFG_TIM_URANGE_B); 1543221167Sgnn 1544221167Sgnn if ((tim_intr_config->uec_b > 1545221167Sgnn VXGE_HAL_MAX_TIM_UEC_B) && 1546221167Sgnn (tim_intr_config->uec_b != 1547221167Sgnn VXGE_HAL_USE_FLASH_DEFAULT_TIM_UEC_B)) 1548221167Sgnn return (VXGE_HAL_BADCFG_TIM_UEC_B); 1549221167Sgnn 1550221167Sgnn if ((tim_intr_config->urange_c > 1551221167Sgnn VXGE_HAL_MAX_TIM_URANGE_C) && 1552221167Sgnn (tim_intr_config->urange_c != 1553221167Sgnn VXGE_HAL_USE_FLASH_DEFAULT_TIM_URANGE_C)) 1554221167Sgnn return (VXGE_HAL_BADCFG_TIM_URANGE_C); 1555221167Sgnn 1556221167Sgnn if ((tim_intr_config->uec_c > 1557221167Sgnn VXGE_HAL_MAX_TIM_UEC_C) && 1558221167Sgnn (tim_intr_config->uec_c != 1559221167Sgnn VXGE_HAL_USE_FLASH_DEFAULT_TIM_UEC_C)) 1560221167Sgnn return (VXGE_HAL_BADCFG_TIM_UEC_C); 1561221167Sgnn 1562221167Sgnn if ((tim_intr_config->uec_d > 1563221167Sgnn VXGE_HAL_MAX_TIM_UEC_D) && 1564221167Sgnn (tim_intr_config->uec_d != 1565221167Sgnn VXGE_HAL_USE_FLASH_DEFAULT_TIM_UEC_D)) 1566221167Sgnn return (VXGE_HAL_BADCFG_TIM_UEC_D); 1567221167Sgnn 1568221167Sgnn if (((tim_intr_config->ufca_intr_thres < 1569221167Sgnn VXGE_HAL_MIN_UFCA_INTR_THRES) || 1570221167Sgnn (tim_intr_config->ufca_intr_thres > 1571221167Sgnn VXGE_HAL_MAX_UFCA_INTR_THRES)) && 1572221167Sgnn (tim_intr_config->ufca_intr_thres != 1573221167Sgnn VXGE_HAL_USE_FLASH_DEFAULT_UFCA_INTR_THRES)) 1574221167Sgnn return (VXGE_HAL_BADCFG_UFCA_INTR_THRES); 1575221167Sgnn 1576221167Sgnn if (((tim_intr_config->ufca_lo_lim < 1577221167Sgnn VXGE_HAL_MIN_UFCA_LO_LIM) || 1578221167Sgnn (tim_intr_config->ufca_lo_lim > 1579221167Sgnn VXGE_HAL_MAX_UFCA_LO_LIM)) && 1580221167Sgnn (tim_intr_config->ufca_lo_lim != 1581221167Sgnn VXGE_HAL_USE_FLASH_DEFAULT_UFCA_LO_LIM)) 1582221167Sgnn return (VXGE_HAL_BADCFG_UFCA_LO_LIM); 1583221167Sgnn 1584221167Sgnn if (((tim_intr_config->ufca_hi_lim < 1585221167Sgnn VXGE_HAL_MIN_UFCA_HI_LIM) || 1586221167Sgnn (tim_intr_config->ufca_hi_lim > 1587221167Sgnn VXGE_HAL_MAX_UFCA_HI_LIM)) && 1588221167Sgnn (tim_intr_config->ufca_hi_lim != 1589221167Sgnn VXGE_HAL_USE_FLASH_DEFAULT_UFCA_HI_LIM)) 1590221167Sgnn return (VXGE_HAL_BADCFG_UFCA_HI_LIM); 1591221167Sgnn 1592221167Sgnn if (((tim_intr_config->ufca_lbolt_period < 1593221167Sgnn VXGE_HAL_MIN_UFCA_LBOLT_PERIOD) || 1594221167Sgnn (tim_intr_config->ufca_lbolt_period > 1595221167Sgnn VXGE_HAL_MAX_UFCA_LBOLT_PERIOD)) && 1596221167Sgnn (tim_intr_config->ufca_lbolt_period != 1597221167Sgnn VXGE_HAL_USE_FLASH_DEFAULT_UFCA_LBOLT_PERIOD)) 1598221167Sgnn return (VXGE_HAL_BADCFG_UFCA_LBOLT_PERIOD); 1599221167Sgnn 1600221167Sgnn return (VXGE_HAL_OK); 1601221167Sgnn} 1602221167Sgnn 1603221167Sgnn/* 1604221167Sgnn * __hal_device_vpath_config_check - Check vpath configuration. 1605221167Sgnn * @vp_config: Vpath configuration information 1606221167Sgnn * 1607221167Sgnn * Check the vpath configuration 1608221167Sgnn * 1609221167Sgnn * Returns: VXGE_HAL_OK - success, 1610221167Sgnn * otherwise one of the vxge_hal_status_e {} enumerated error codes. 1611221167Sgnn * 1612221167Sgnn */ 1613221167Sgnnvxge_hal_status_e 1614221167Sgnn__hal_device_vpath_config_check(vxge_hal_vp_config_t *vp_config) 1615221167Sgnn{ 1616221167Sgnn vxge_hal_status_e status; 1617221167Sgnn 1618221167Sgnn if (vp_config->vp_id > VXGE_HAL_MAX_VIRTUAL_PATHS) 1619221167Sgnn return (VXGE_HAL_BADCFG_VPATH_ID); 1620221167Sgnn 1621221167Sgnn if ((vp_config->wire_port != VXGE_HAL_VPATH_USE_PORT0) && 1622221167Sgnn (vp_config->wire_port != VXGE_HAL_VPATH_USE_PORT1) && 1623221167Sgnn (vp_config->wire_port != VXGE_HAL_VPATH_USE_BOTH) && 1624221167Sgnn (vp_config->wire_port != VXGE_HAL_VPATH_USE_DEFAULT_PORT)) 1625221167Sgnn return (VXGE_HAL_BADCFG_VPATH_WIRE_PORT); 1626221167Sgnn 1627221167Sgnn if ((vp_config->priority != VXGE_HAL_VPATH_PRIORITY_DEFAULT) && 1628221167Sgnn (((int)vp_config->priority < VXGE_HAL_VPATH_PRIORITY_MIN) || 1629221167Sgnn (vp_config->priority > VXGE_HAL_VPATH_PRIORITY_MAX))) 1630221167Sgnn return (VXGE_HAL_BADCFG_VPATH_PRIORITY); 1631221167Sgnn 1632221167Sgnn if ((vp_config->bandwidth != VXGE_HAL_VPATH_BW_LIMIT_DEFAULT) && 1633221167Sgnn ((vp_config->bandwidth < VXGE_HAL_VPATH_BW_LIMIT_MIN) || 1634221167Sgnn (vp_config->bandwidth > VXGE_HAL_VPATH_BW_LIMIT_MAX))) 1635221167Sgnn return (VXGE_HAL_BADCFG_VPATH_BANDWIDTH_LIMIT); 1636221167Sgnn 1637221167Sgnn if ((vp_config->no_snoop != VXGE_HAL_VPATH_NO_SNOOP_ENABLE) && 1638221167Sgnn (vp_config->no_snoop != VXGE_HAL_VPATH_NO_SNOOP_DISABLE) && 1639221167Sgnn (vp_config->no_snoop != VXGE_HAL_VPATH_NO_SNOOP_USE_FLASH_DEFAULT)) 1640221167Sgnn return (VXGE_HAL_BADCFG_VPATH_NO_SNOOP); 1641221167Sgnn 1642221167Sgnn status = __hal_device_ring_config_check(&vp_config->ring); 1643221167Sgnn if (status != VXGE_HAL_OK) 1644221167Sgnn return (status); 1645221167Sgnn 1646221167Sgnn status = __hal_device_fifo_config_check(&vp_config->fifo); 1647221167Sgnn if (status != VXGE_HAL_OK) 1648221167Sgnn return (status); 1649221167Sgnn 1650221167Sgnn 1651221167Sgnn status = __hal_device_tim_intr_config_check(&vp_config->tti); 1652221167Sgnn if (status != VXGE_HAL_OK) 1653221167Sgnn return (status); 1654221167Sgnn 1655221167Sgnn status = __hal_device_tim_intr_config_check(&vp_config->rti); 1656221167Sgnn if (status != VXGE_HAL_OK) 1657221167Sgnn return (status); 1658221167Sgnn 1659221167Sgnn if ((vp_config->mtu != VXGE_HAL_VPATH_USE_FLASH_DEFAULT_INITIAL_MTU) && 1660221167Sgnn ((vp_config->mtu < VXGE_HAL_VPATH_MIN_INITIAL_MTU) || 1661221167Sgnn (vp_config->mtu > VXGE_HAL_VPATH_MAX_INITIAL_MTU))) 1662221167Sgnn return (VXGE_HAL_BADCFG_VPATH_MTU); 1663221167Sgnn 1664221167Sgnn if ((vp_config->tpa_lsov2_en != 1665221167Sgnn VXGE_HAL_VPATH_TPA_LSOV2_EN_USE_FLASH_DEFAULT) && 1666221167Sgnn (vp_config->tpa_lsov2_en != 1667221167Sgnn VXGE_HAL_VPATH_TPA_LSOV2_EN_ENABLE) && 1668221167Sgnn (vp_config->tpa_lsov2_en != 1669221167Sgnn VXGE_HAL_VPATH_TPA_LSOV2_EN_DISABLE)) 1670221167Sgnn return (VXGE_HAL_BADCFG_VPATH_TPA_LSOV2_EN); 1671221167Sgnn 1672221167Sgnn if ((vp_config->tpa_ignore_frame_error != 1673221167Sgnn VXGE_HAL_VPATH_TPA_IGNORE_FRAME_ERROR_USE_FLASH_DEFAULT) && 1674221167Sgnn (vp_config->tpa_ignore_frame_error != 1675221167Sgnn VXGE_HAL_VPATH_TPA_IGNORE_FRAME_ERROR_ENABLE) && 1676221167Sgnn (vp_config->tpa_ignore_frame_error != 1677221167Sgnn VXGE_HAL_VPATH_TPA_IGNORE_FRAME_ERROR_DISABLE)) 1678221167Sgnn return (VXGE_HAL_BADCFG_VPATH_TPA_IGNORE_FRAME_ERROR); 1679221167Sgnn 1680221167Sgnn if ((vp_config->tpa_ipv6_keep_searching != 1681221167Sgnn VXGE_HAL_VPATH_TPA_IPV6_KEEP_SEARCHING_USE_FLASH_DEFAULT) && 1682221167Sgnn (vp_config->tpa_ipv6_keep_searching != 1683221167Sgnn VXGE_HAL_VPATH_TPA_IPV6_KEEP_SEARCHING_ENABLE) && 1684221167Sgnn (vp_config->tpa_ipv6_keep_searching != 1685221167Sgnn VXGE_HAL_VPATH_TPA_IPV6_KEEP_SEARCHING_DISABLE)) 1686221167Sgnn return (VXGE_HAL_BADCFG_VPATH_TPA_IPV6_KEEP_SEARCHING); 1687221167Sgnn 1688221167Sgnn if ((vp_config->tpa_l4_pshdr_present != 1689221167Sgnn VXGE_HAL_VPATH_TPA_L4_PSHDR_PRESENT_USE_FLASH_DEFAULT) && 1690221167Sgnn (vp_config->tpa_l4_pshdr_present != 1691221167Sgnn VXGE_HAL_VPATH_TPA_L4_PSHDR_PRESENT_ENABLE) && 1692221167Sgnn (vp_config->tpa_l4_pshdr_present != 1693221167Sgnn VXGE_HAL_VPATH_TPA_L4_PSHDR_PRESENT_DISABLE)) 1694221167Sgnn return (VXGE_HAL_BADCFG_VPATH_TPA_L4_PSHDR_PRESENT); 1695221167Sgnn 1696221167Sgnn if ((vp_config->tpa_support_mobile_ipv6_hdrs != 1697221167Sgnn VXGE_HAL_VPATH_TPA_SUPPORT_MOBILE_IPV6_HDRS_USE_FLASH_DEFAULT) && 1698221167Sgnn (vp_config->tpa_support_mobile_ipv6_hdrs != 1699221167Sgnn VXGE_HAL_VPATH_TPA_SUPPORT_MOBILE_IPV6_HDRS_ENABLE) && 1700221167Sgnn (vp_config->tpa_support_mobile_ipv6_hdrs != 1701221167Sgnn VXGE_HAL_VPATH_TPA_SUPPORT_MOBILE_IPV6_HDRS_DISABLE)) 1702221167Sgnn return (VXGE_HAL_BADCFG_VPATH_TPA_SUPPORT_MOBILE_IPV6_HDRS); 1703221167Sgnn 1704221167Sgnn if ((vp_config->rpa_ipv4_tcp_incl_ph != 1705221167Sgnn VXGE_HAL_VPATH_RPA_IPV4_TCP_INCL_PH_USE_FLASH_DEFAULT) && 1706221167Sgnn (vp_config->rpa_ipv4_tcp_incl_ph != 1707221167Sgnn VXGE_HAL_VPATH_RPA_IPV4_TCP_INCL_PH_ENABLE) && 1708221167Sgnn (vp_config->rpa_ipv4_tcp_incl_ph != 1709221167Sgnn VXGE_HAL_VPATH_RPA_IPV4_TCP_INCL_PH_DISABLE)) 1710221167Sgnn return (VXGE_HAL_BADCFG_VPATH_RPA_IPV4_TCP_INCL_PH); 1711221167Sgnn 1712221167Sgnn if ((vp_config->rpa_ipv6_tcp_incl_ph != 1713221167Sgnn VXGE_HAL_VPATH_RPA_IPV6_TCP_INCL_PH_USE_FLASH_DEFAULT) && 1714221167Sgnn (vp_config->rpa_ipv6_tcp_incl_ph != 1715221167Sgnn VXGE_HAL_VPATH_RPA_IPV6_TCP_INCL_PH_ENABLE) && 1716221167Sgnn (vp_config->rpa_ipv6_tcp_incl_ph != 1717221167Sgnn VXGE_HAL_VPATH_RPA_IPV6_TCP_INCL_PH_DISABLE)) 1718221167Sgnn return (VXGE_HAL_BADCFG_VPATH_RPA_IPV6_TCP_INCL_PH); 1719221167Sgnn 1720221167Sgnn if ((vp_config->rpa_ipv4_udp_incl_ph != 1721221167Sgnn VXGE_HAL_VPATH_RPA_IPV4_UDP_INCL_PH_USE_FLASH_DEFAULT) && 1722221167Sgnn (vp_config->rpa_ipv4_udp_incl_ph != 1723221167Sgnn VXGE_HAL_VPATH_RPA_IPV4_UDP_INCL_PH_ENABLE) && 1724221167Sgnn (vp_config->rpa_ipv4_udp_incl_ph != 1725221167Sgnn VXGE_HAL_VPATH_RPA_IPV4_UDP_INCL_PH_DISABLE)) 1726221167Sgnn return (VXGE_HAL_BADCFG_VPATH_RPA_IPV4_UDP_INCL_PH); 1727221167Sgnn 1728221167Sgnn if ((vp_config->rpa_ipv6_udp_incl_ph != 1729221167Sgnn VXGE_HAL_VPATH_RPA_IPV6_UDP_INCL_PH_USE_FLASH_DEFAULT) && 1730221167Sgnn (vp_config->rpa_ipv6_udp_incl_ph != 1731221167Sgnn VXGE_HAL_VPATH_RPA_IPV6_UDP_INCL_PH_ENABLE) && 1732221167Sgnn (vp_config->rpa_ipv6_udp_incl_ph != 1733221167Sgnn VXGE_HAL_VPATH_RPA_IPV6_UDP_INCL_PH_DISABLE)) 1734221167Sgnn return (VXGE_HAL_BADCFG_VPATH_RPA_IPV4_UDP_INCL_PH); 1735221167Sgnn 1736221167Sgnn if ((vp_config->rpa_l4_incl_cf != 1737221167Sgnn VXGE_HAL_VPATH_RPA_L4_INCL_CF_USE_FLASH_DEFAULT) && 1738221167Sgnn (vp_config->rpa_l4_incl_cf != 1739221167Sgnn VXGE_HAL_VPATH_RPA_L4_INCL_CF_ENABLE) && 1740221167Sgnn (vp_config->rpa_l4_incl_cf != 1741221167Sgnn VXGE_HAL_VPATH_RPA_L4_INCL_CF_DISABLE)) 1742221167Sgnn return (VXGE_HAL_BADCFG_VPATH_RPA_L4_INCL_CF); 1743221167Sgnn 1744221167Sgnn if ((vp_config->rpa_strip_vlan_tag != 1745221167Sgnn VXGE_HAL_VPATH_RPA_STRIP_VLAN_TAG_USE_FLASH_DEFAULT) && 1746221167Sgnn (vp_config->rpa_strip_vlan_tag != 1747221167Sgnn VXGE_HAL_VPATH_RPA_STRIP_VLAN_TAG_ENABLE) && 1748221167Sgnn (vp_config->rpa_strip_vlan_tag != 1749221167Sgnn VXGE_HAL_VPATH_RPA_STRIP_VLAN_TAG_DISABLE)) 1750221167Sgnn return (VXGE_HAL_BADCFG_VPATH_RPA_STRIP_VLAN_TAG); 1751221167Sgnn 1752221167Sgnn if ((vp_config->rpa_l4_comp_csum != 1753221167Sgnn VXGE_HAL_VPATH_RPA_L4_COMP_CSUM_USE_FLASH_DEFAULT) && 1754221167Sgnn (vp_config->rpa_l4_comp_csum != 1755221167Sgnn VXGE_HAL_VPATH_RPA_L4_COMP_CSUM_ENABLE) && 1756221167Sgnn (vp_config->rpa_l4_comp_csum != 1757221167Sgnn VXGE_HAL_VPATH_RPA_L4_COMP_CSUM_DISABLE)) 1758221167Sgnn return (VXGE_HAL_BADCFG_VPATH_RPA_L4_COMP_CSUM); 1759221167Sgnn 1760221167Sgnn if ((vp_config->rpa_l3_incl_cf != 1761221167Sgnn VXGE_HAL_VPATH_RPA_L3_INCL_CF_USE_FLASH_DEFAULT) && 1762221167Sgnn (vp_config->rpa_l3_incl_cf != 1763221167Sgnn VXGE_HAL_VPATH_RPA_L3_INCL_CF_ENABLE) && 1764221167Sgnn (vp_config->rpa_l3_incl_cf != 1765221167Sgnn VXGE_HAL_VPATH_RPA_L3_INCL_CF_DISABLE)) 1766221167Sgnn return (VXGE_HAL_BADCFG_VPATH_RPA_L3_INCL_CF); 1767221167Sgnn 1768221167Sgnn if ((vp_config->rpa_l3_comp_csum != 1769221167Sgnn VXGE_HAL_VPATH_RPA_L3_COMP_CSUM_USE_FLASH_DEFAULT) && 1770221167Sgnn (vp_config->rpa_l3_comp_csum != 1771221167Sgnn VXGE_HAL_VPATH_RPA_L3_COMP_CSUM_ENABLE) && 1772221167Sgnn (vp_config->rpa_l3_comp_csum != 1773221167Sgnn VXGE_HAL_VPATH_RPA_L3_COMP_CSUM_DISABLE)) 1774221167Sgnn return (VXGE_HAL_BADCFG_VPATH_RPA_L3_COMP_CSUM); 1775221167Sgnn 1776221167Sgnn if ((vp_config->rpa_ucast_all_addr_en != 1777221167Sgnn VXGE_HAL_VPATH_RPA_UCAST_ALL_ADDR_USE_FLASH_DEFAULT) && 1778221167Sgnn (vp_config->rpa_ucast_all_addr_en != 1779221167Sgnn VXGE_HAL_VPATH_RPA_UCAST_ALL_ADDR_ENABLE) && 1780221167Sgnn (vp_config->rpa_ucast_all_addr_en != 1781221167Sgnn VXGE_HAL_VPATH_RPA_UCAST_ALL_ADDR_DISABLE)) 1782221167Sgnn return (VXGE_HAL_BADCFG_VPATH_RPA_UCAST_ALL_ADDR_EN); 1783221167Sgnn 1784221167Sgnn if ((vp_config->rpa_mcast_all_addr_en != 1785221167Sgnn VXGE_HAL_VPATH_RPA_MCAST_ALL_ADDR_USE_FLASH_DEFAULT) && 1786221167Sgnn (vp_config->rpa_mcast_all_addr_en != 1787221167Sgnn VXGE_HAL_VPATH_RPA_MCAST_ALL_ADDR_ENABLE) && 1788221167Sgnn (vp_config->rpa_mcast_all_addr_en != 1789221167Sgnn VXGE_HAL_VPATH_RPA_MCAST_ALL_ADDR_DISABLE)) 1790221167Sgnn return (VXGE_HAL_BADCFG_VPATH_RPA_MCAST_ALL_ADDR_EN); 1791221167Sgnn 1792221167Sgnn if ((vp_config->rpa_bcast_en != 1793221167Sgnn VXGE_HAL_VPATH_RPA_BCAST_USE_FLASH_DEFAULT) && 1794221167Sgnn (vp_config->rpa_bcast_en != 1795221167Sgnn VXGE_HAL_VPATH_RPA_BCAST_ENABLE) && 1796221167Sgnn (vp_config->rpa_bcast_en != 1797221167Sgnn VXGE_HAL_VPATH_RPA_BCAST_DISABLE)) 1798221167Sgnn return (VXGE_HAL_BADCFG_VPATH_RPA_CAST_EN); 1799221167Sgnn 1800221167Sgnn if ((vp_config->rpa_all_vid_en != 1801221167Sgnn VXGE_HAL_VPATH_RPA_ALL_VID_USE_FLASH_DEFAULT) && 1802221167Sgnn (vp_config->rpa_all_vid_en != 1803221167Sgnn VXGE_HAL_VPATH_RPA_ALL_VID_ENABLE) && 1804221167Sgnn (vp_config->rpa_all_vid_en != 1805221167Sgnn VXGE_HAL_VPATH_RPA_ALL_VID_DISABLE)) 1806221167Sgnn return (VXGE_HAL_BADCFG_VPATH_RPA_ALL_VID_EN); 1807221167Sgnn 1808221167Sgnn if ((vp_config->vp_queue_l2_flow != 1809221167Sgnn VXGE_HAL_VPATH_VP_Q_L2_FLOW_ENABLE) && 1810221167Sgnn (vp_config->vp_queue_l2_flow != 1811221167Sgnn VXGE_HAL_VPATH_VP_Q_L2_FLOW_DISABLE) && 1812221167Sgnn (vp_config->vp_queue_l2_flow != 1813221167Sgnn VXGE_HAL_VPATH_VP_Q_L2_FLOW_USE_FLASH_DEFAULT)) 1814221167Sgnn return (VXGE_HAL_BADCFG_VPATH_VP_Q_L2_FLOW); 1815221167Sgnn 1816221167Sgnn return (VXGE_HAL_OK); 1817221167Sgnn} 1818221167Sgnn 1819221167Sgnn/* 1820221167Sgnn * __hal_device_config_check - Check device configuration. 1821221167Sgnn * @new_config: Device configuration information 1822221167Sgnn * 1823221167Sgnn * Check the device configuration 1824221167Sgnn * 1825221167Sgnn * Returns: VXGE_HAL_OK - success, 1826221167Sgnn * otherwise one of the vxge_hal_status_e {} enumerated error codes. 1827221167Sgnn * 1828221167Sgnn */ 1829221167Sgnnvxge_hal_status_e 1830221167Sgnn__hal_device_config_check(vxge_hal_device_config_t *new_config) 1831221167Sgnn{ 1832221167Sgnn u32 i; 1833221167Sgnn vxge_hal_status_e status; 1834221167Sgnn 1835221167Sgnn if (new_config->dma_blockpool_incr < 1836221167Sgnn VXGE_HAL_INCR_DMA_BLOCK_POOL_SIZE) 1837221167Sgnn return (VXGE_HAL_BADCFG_BLOCKPOOL_INCR); 1838221167Sgnn 1839221167Sgnn if (new_config->dma_blockpool_max < 1840221167Sgnn VXGE_HAL_MAX_DMA_BLOCK_POOL_SIZE) 1841221167Sgnn return (VXGE_HAL_BADCFG_BLOCKPOOL_MAX); 1842221167Sgnn 1843221167Sgnn if ((status = __hal_mrpcim_config_check(&new_config->mrpcim_config)) != 1844221167Sgnn VXGE_HAL_OK) 1845221167Sgnn return (status); 1846221167Sgnn 1847221167Sgnn if (new_config->isr_polling_cnt > VXGE_HAL_MAX_ISR_POLLING_CNT) 1848221167Sgnn return (VXGE_HAL_BADCFG_ISR_POLLING_CNT); 1849221167Sgnn 1850221167Sgnn if ((new_config->max_payload_size > 1851221167Sgnn VXGE_HAL_MAX_PAYLOAD_SIZE_4096) && 1852221167Sgnn (new_config->max_payload_size != 1853221167Sgnn VXGE_HAL_USE_BIOS_DEFAULT_PAYLOAD_SIZE)) 1854221167Sgnn return (VXGE_HAL_BADCFG_MAX_PAYLOAD_SIZE); 1855221167Sgnn 1856221167Sgnn if ((new_config->mmrb_count > VXGE_HAL_MMRB_COUNT_4096) && 1857221167Sgnn (new_config->mmrb_count != VXGE_HAL_USE_BIOS_DEFAULT_MMRB_COUNT)) 1858221167Sgnn return (VXGE_HAL_BADCFG_MAX_PAYLOAD_SIZE); 1859221167Sgnn 1860221167Sgnn if (((new_config->stats_refresh_time_sec < 1861221167Sgnn VXGE_HAL_MIN_STATS_REFRESH_TIME) || 1862221167Sgnn (new_config->stats_refresh_time_sec > 1863221167Sgnn VXGE_HAL_MAX_STATS_REFRESH_TIME)) && 1864221167Sgnn (new_config->stats_refresh_time_sec != 1865221167Sgnn VXGE_HAL_STATS_REFRESH_DISABLE)) 1866221167Sgnn return (VXGE_HAL_BADCFG_STATS_REFRESH_TIME); 1867221167Sgnn 1868221167Sgnn if ((new_config->intr_mode != VXGE_HAL_INTR_MODE_IRQLINE) && 1869221167Sgnn (new_config->intr_mode != VXGE_HAL_INTR_MODE_MSIX) && 1870221167Sgnn (new_config->intr_mode != VXGE_HAL_INTR_MODE_MSIX_ONE_SHOT) && 1871221167Sgnn (new_config->intr_mode != VXGE_HAL_INTR_MODE_EMULATED_INTA) && 1872221167Sgnn (new_config->intr_mode != VXGE_HAL_INTR_MODE_DEF)) 1873221167Sgnn return (VXGE_HAL_BADCFG_INTR_MODE); 1874221167Sgnn 1875221167Sgnn if ((new_config->dump_on_unknown != 1876221167Sgnn VXGE_HAL_DUMP_ON_UNKNOWN_DISABLE) && 1877221167Sgnn (new_config->dump_on_unknown != 1878221167Sgnn VXGE_HAL_DUMP_ON_UNKNOWN_ENABLE)) 1879221167Sgnn return (VXGE_HAL_BADCFG_DUMP_ON_UNKNOWN); 1880221167Sgnn 1881221167Sgnn if ((new_config->dump_on_serr != VXGE_HAL_DUMP_ON_SERR_DISABLE) && 1882221167Sgnn (new_config->dump_on_serr != VXGE_HAL_DUMP_ON_SERR_ENABLE)) 1883221167Sgnn return (VXGE_HAL_BADCFG_DUMP_ON_SERR); 1884221167Sgnn 1885221167Sgnn if ((new_config->dump_on_critical != 1886221167Sgnn VXGE_HAL_DUMP_ON_CRITICAL_DISABLE) && 1887221167Sgnn (new_config->dump_on_critical != 1888221167Sgnn VXGE_HAL_DUMP_ON_CRITICAL_ENABLE)) 1889221167Sgnn return (VXGE_HAL_BADCFG_DUMP_ON_CRITICAL); 1890221167Sgnn 1891221167Sgnn if ((new_config->dump_on_eccerr != VXGE_HAL_DUMP_ON_ECCERR_DISABLE) && 1892221167Sgnn (new_config->dump_on_eccerr != VXGE_HAL_DUMP_ON_ECCERR_ENABLE)) 1893221167Sgnn return (VXGE_HAL_BADCFG_DUMP_ON_ECCERR); 1894221167Sgnn 1895221167Sgnn if ((new_config->rth_en != VXGE_HAL_RTH_DISABLE) && 1896221167Sgnn (new_config->rth_en != VXGE_HAL_RTH_ENABLE)) 1897221167Sgnn return (VXGE_HAL_BADCFG_RTH_EN); 1898221167Sgnn 1899221167Sgnn if ((new_config->rth_it_type != VXGE_HAL_RTH_IT_TYPE_SOLO_IT) && 1900221167Sgnn (new_config->rth_it_type != VXGE_HAL_RTH_IT_TYPE_MULTI_IT)) 1901221167Sgnn return (VXGE_HAL_BADCFG_RTH_IT_TYPE); 1902221167Sgnn 1903221167Sgnn if ((new_config->rts_mac_en != VXGE_HAL_RTS_MAC_DISABLE) && 1904221167Sgnn (new_config->rts_mac_en != VXGE_HAL_RTS_MAC_ENABLE)) 1905221167Sgnn return (VXGE_HAL_BADCFG_RTS_MAC_EN); 1906221167Sgnn 1907221167Sgnn if ((new_config->rts_qos_en != VXGE_HAL_RTS_QOS_DISABLE) && 1908221167Sgnn (new_config->rts_qos_en != VXGE_HAL_RTS_QOS_ENABLE)) 1909221167Sgnn return (VXGE_HAL_BADCFG_RTS_QOS_EN); 1910221167Sgnn 1911221167Sgnn if ((new_config->rts_port_en != VXGE_HAL_RTS_PORT_DISABLE) && 1912221167Sgnn (new_config->rts_port_en != VXGE_HAL_RTS_PORT_ENABLE)) 1913221167Sgnn return (VXGE_HAL_BADCFG_RTS_PORT_EN); 1914221167Sgnn 1915221167Sgnn for (i = 0; i < VXGE_HAL_MAX_VIRTUAL_PATHS; i++) { 1916221167Sgnn if ((status = __hal_device_vpath_config_check( 1917221167Sgnn &new_config->vp_config[i])) != VXGE_HAL_OK) 1918221167Sgnn return (status); 1919221167Sgnn } 1920221167Sgnn 1921221167Sgnn if ((new_config->max_cqe_groups < VXGE_HAL_MIN_MAX_CQE_GROUPS) || 1922221167Sgnn (new_config->max_cqe_groups > VXGE_HAL_MAX_MAX_CQE_GROUPS)) 1923221167Sgnn return (VXGE_HAL_BADCFG_MAX_CQE_GROUPS); 1924221167Sgnn 1925221167Sgnn if ((new_config->max_num_wqe_od_groups < 1926221167Sgnn VXGE_HAL_MIN_MAX_NUM_OD_GROUPS) || 1927221167Sgnn (new_config->max_num_wqe_od_groups > 1928221167Sgnn VXGE_HAL_MAX_MAX_NUM_OD_GROUPS)) 1929221167Sgnn return (VXGE_HAL_BADCFG_MAX_NUM_OD_GROUPS); 1930221167Sgnn 1931221167Sgnn if ((new_config->no_wqe_threshold < VXGE_HAL_MIN_NO_WQE_THRESHOLD) || 1932221167Sgnn (new_config->no_wqe_threshold > VXGE_HAL_MAX_NO_WQE_THRESHOLD)) 1933221167Sgnn return (VXGE_HAL_BADCFG_NO_WQE_THRESHOLD); 1934221167Sgnn 1935221167Sgnn if ((new_config->refill_threshold_high < 1936221167Sgnn VXGE_HAL_MIN_REFILL_THRESHOLD_HIGH) || 1937221167Sgnn (new_config->refill_threshold_high > 1938221167Sgnn VXGE_HAL_MAX_REFILL_THRESHOLD_HIGH)) 1939221167Sgnn return (VXGE_HAL_BADCFG_REFILL_THRESHOLD_HIGH); 1940221167Sgnn 1941221167Sgnn if ((new_config->refill_threshold_low < 1942221167Sgnn VXGE_HAL_MIN_REFILL_THRESHOLD_LOW) || 1943221167Sgnn (new_config->refill_threshold_low > 1944221167Sgnn VXGE_HAL_MAX_REFILL_THRESHOLD_LOW)) 1945221167Sgnn return (VXGE_HAL_BADCFG_REFILL_THRESHOLD_LOW); 1946221167Sgnn 1947221167Sgnn if ((new_config->ack_blk_limit < VXGE_HAL_MIN_ACK_BLOCK_LIMIT) || 1948221167Sgnn (new_config->ack_blk_limit > VXGE_HAL_MAX_ACK_BLOCK_LIMIT)) 1949221167Sgnn return (VXGE_HAL_BADCFG_ACK_BLOCK_LIMIT); 1950221167Sgnn 1951221167Sgnn if ((new_config->stats_read_method != 1952221167Sgnn VXGE_HAL_STATS_READ_METHOD_DMA) && 1953221167Sgnn (new_config->stats_read_method != 1954221167Sgnn VXGE_HAL_STATS_READ_METHOD_PIO)) 1955221167Sgnn return (VXGE_HAL_BADCFG_STATS_READ_METHOD); 1956221167Sgnn 1957221167Sgnn if ((new_config->poll_or_doorbell != 1958221167Sgnn VXGE_HAL_POLL_OR_DOORBELL_POLL) && 1959221167Sgnn (new_config->poll_or_doorbell != 1960221167Sgnn VXGE_HAL_POLL_OR_DOORBELL_DOORBELL)) 1961221167Sgnn return (VXGE_HAL_BADCFG_POLL_OR_DOOR_BELL); 1962221167Sgnn 1963221167Sgnn if ((new_config->device_poll_millis < 1964221167Sgnn VXGE_HAL_MIN_DEVICE_POLL_MILLIS) || 1965221167Sgnn (new_config->device_poll_millis > 1966221167Sgnn VXGE_HAL_MAX_DEVICE_POLL_MILLIS)) 1967221167Sgnn return (VXGE_HAL_BADCFG_DEVICE_POLL_MILLIS); 1968221167Sgnn 1969221167Sgnn 1970221167Sgnn return (VXGE_HAL_OK); 1971221167Sgnn} 1972221167Sgnn 1973221167Sgnn/* 1974221167Sgnn * vxge_hal_device_config_default_get - Initialize device config with defaults. 1975221167Sgnn * @device_config: Configuration structure to be initialized, 1976221167Sgnn * For the X3100 configuration "knobs" please 1977221167Sgnn * refer to vxge_hal_device_config_t and X3100 1978221167Sgnn * User Guide. 1979221167Sgnn * 1980221167Sgnn * Initialize X3100 device config with default values. 1981221167Sgnn * 1982221167Sgnn * See also: vxge_hal_device_initialize(), vxge_hal_device_terminate(), 1983221167Sgnn * vxge_hal_status_e {} vxge_hal_device_attr_t {}. 1984221167Sgnn */ 1985221167Sgnnvxge_hal_status_e 1986221167Sgnnvxge_hal_device_config_default_get( 1987221167Sgnn vxge_hal_device_config_t *device_config) 1988221167Sgnn{ 1989221167Sgnn u32 i; 1990221167Sgnn vxge_hal_mac_config_t *mac_config; 1991221167Sgnn vxge_hal_wire_port_config_t *wire_port_config; 1992221167Sgnn vxge_hal_switch_port_config_t *switch_port_config; 1993221167Sgnn 1994221167Sgnn vxge_hal_trace_log_driver("==> %s:%s:%d", 1995221167Sgnn __FILE__, __func__, __LINE__); 1996221167Sgnn 1997221167Sgnn vxge_hal_trace_log_driver("device_config = 0x"VXGE_OS_STXFMT, 1998221167Sgnn (ptr_t) device_config); 1999221167Sgnn 2000221167Sgnn device_config->dma_blockpool_min = VXGE_HAL_MIN_DMA_BLOCK_POOL_SIZE; 2001221167Sgnn device_config->dma_blockpool_initial = 2002221167Sgnn VXGE_HAL_INITIAL_DMA_BLOCK_POOL_SIZE; 2003221167Sgnn device_config->dma_blockpool_incr = VXGE_HAL_INCR_DMA_BLOCK_POOL_SIZE; 2004221167Sgnn device_config->dma_blockpool_max = VXGE_HAL_MAX_DMA_BLOCK_POOL_SIZE; 2005221167Sgnn 2006221167Sgnn mac_config = &device_config->mrpcim_config.mac_config; 2007221167Sgnn 2008221167Sgnn for (i = 0; i < VXGE_HAL_MAC_MAX_WIRE_PORTS; i++) { 2009221167Sgnn 2010221167Sgnn wire_port_config = &mac_config->wire_port_config[i]; 2011221167Sgnn 2012221167Sgnn wire_port_config->port_id = i; 2013221167Sgnn 2014221167Sgnn wire_port_config->media = VXGE_HAL_WIRE_PORT_MEDIA_DEFAULT; 2015221167Sgnn 2016221167Sgnn wire_port_config->mtu = VXGE_HAL_WIRE_PORT_DEF_INITIAL_MTU; 2017221167Sgnn 2018221167Sgnn wire_port_config->autoneg_mode = 2019221167Sgnn VXGE_HAL_WIRE_PORT_AUTONEG_MODE_DEFAULT; 2020221167Sgnn 2021221167Sgnn wire_port_config->autoneg_rate = 2022221167Sgnn VXGE_HAL_WIRE_PORT_AUTONEG_RATE_DEFAULT; 2023221167Sgnn 2024221167Sgnn wire_port_config->fixed_use_fsm = 2025221167Sgnn VXGE_HAL_WIRE_PORT_FIXED_USE_FSM_DEFAULT; 2026221167Sgnn 2027221167Sgnn wire_port_config->antp_use_fsm = 2028221167Sgnn VXGE_HAL_WIRE_PORT_ANTP_USE_FSM_DEFAULT; 2029221167Sgnn 2030221167Sgnn wire_port_config->anbe_use_fsm = 2031221167Sgnn VXGE_HAL_WIRE_PORT_ANBE_USE_FSM_DEFAULT; 2032221167Sgnn 2033221167Sgnn wire_port_config->link_stability_period = 2034221167Sgnn VXGE_HAL_WIRE_PORT_DEF_LINK_STABILITY_PERIOD; 2035221167Sgnn 2036221167Sgnn wire_port_config->port_stability_period = 2037221167Sgnn VXGE_HAL_WIRE_PORT_DEF_PORT_STABILITY_PERIOD; 2038221167Sgnn 2039221167Sgnn wire_port_config->tmac_en = 2040221167Sgnn VXGE_HAL_WIRE_PORT_TMAC_DEFAULT; 2041221167Sgnn 2042221167Sgnn wire_port_config->rmac_en = 2043221167Sgnn VXGE_HAL_WIRE_PORT_RMAC_DEFAULT; 2044221167Sgnn 2045221167Sgnn wire_port_config->tmac_pad = 2046221167Sgnn VXGE_HAL_WIRE_PORT_TMAC_PAD_DEFAULT; 2047221167Sgnn 2048221167Sgnn wire_port_config->tmac_pad_byte = 2049221167Sgnn VXGE_HAL_WIRE_PORT_DEF_TMAC_PAD_BYTE; 2050221167Sgnn 2051221167Sgnn wire_port_config->tmac_util_period = 2052221167Sgnn VXGE_HAL_WIRE_PORT_DEF_TMAC_UTIL_PERIOD; 2053221167Sgnn 2054221167Sgnn wire_port_config->rmac_strip_fcs = 2055221167Sgnn VXGE_HAL_WIRE_PORT_RMAC_STRIP_FCS_DEFAULT; 2056221167Sgnn 2057221167Sgnn wire_port_config->rmac_prom_en = 2058221167Sgnn VXGE_HAL_WIRE_PORT_RMAC_PROM_EN_DEFAULT; 2059221167Sgnn 2060221167Sgnn wire_port_config->rmac_discard_pfrm = 2061221167Sgnn VXGE_HAL_WIRE_PORT_RMAC_DISCARD_PFRM_DEFAULT; 2062221167Sgnn 2063221167Sgnn wire_port_config->rmac_util_period = 2064221167Sgnn VXGE_HAL_WIRE_PORT_DEF_RMAC_UTIL_PERIOD; 2065221167Sgnn 2066221167Sgnn wire_port_config->rmac_pause_gen_en = 2067221167Sgnn VXGE_HAL_WIRE_PORT_RMAC_PAUSE_GEN_EN_DEFAULT; 2068221167Sgnn 2069221167Sgnn wire_port_config->rmac_pause_rcv_en = 2070221167Sgnn VXGE_HAL_WIRE_PORT_RMAC_PAUSE_RCV_EN_DEFAULT; 2071221167Sgnn 2072221167Sgnn wire_port_config->rmac_pause_time = 2073221167Sgnn VXGE_HAL_WIRE_PORT_DEF_RMAC_HIGH_PTIME; 2074221167Sgnn 2075221167Sgnn wire_port_config->limiter_en = 2076221167Sgnn VXGE_HAL_WIRE_PORT_RMAC_PAUSE_LIMITER_DEFAULT; 2077221167Sgnn 2078221167Sgnn wire_port_config->max_limit = 2079221167Sgnn VXGE_HAL_WIRE_PORT_DEF_RMAC_MAX_LIMIT; 2080221167Sgnn } 2081221167Sgnn 2082221167Sgnn switch_port_config = &mac_config->switch_port_config; 2083221167Sgnn 2084221167Sgnn switch_port_config->mtu = 2085221167Sgnn VXGE_HAL_SWITCH_PORT_DEF_INITIAL_MTU; 2086221167Sgnn 2087221167Sgnn switch_port_config->tmac_en = 2088221167Sgnn VXGE_HAL_SWITCH_PORT_TMAC_DEFAULT; 2089221167Sgnn 2090221167Sgnn switch_port_config->rmac_en = 2091221167Sgnn VXGE_HAL_SWITCH_PORT_RMAC_DEFAULT; 2092221167Sgnn 2093221167Sgnn switch_port_config->tmac_pad = 2094221167Sgnn VXGE_HAL_SWITCH_PORT_TMAC_PAD_DEFAULT; 2095221167Sgnn 2096221167Sgnn switch_port_config->tmac_pad_byte = 2097221167Sgnn VXGE_HAL_SWITCH_PORT_DEF_TMAC_PAD_BYTE; 2098221167Sgnn 2099221167Sgnn switch_port_config->tmac_util_period = 2100221167Sgnn VXGE_HAL_SWITCH_PORT_DEF_TMAC_UTIL_PERIOD; 2101221167Sgnn 2102221167Sgnn switch_port_config->rmac_strip_fcs = 2103221167Sgnn VXGE_HAL_SWITCH_PORT_RMAC_STRIP_FCS_DEFAULT; 2104221167Sgnn 2105221167Sgnn switch_port_config->rmac_prom_en = 2106221167Sgnn VXGE_HAL_SWITCH_PORT_RMAC_PROM_EN_DEFAULT; 2107221167Sgnn 2108221167Sgnn switch_port_config->rmac_discard_pfrm = 2109221167Sgnn VXGE_HAL_SWITCH_PORT_RMAC_DISCARD_PFRM_DEFAULT; 2110221167Sgnn 2111221167Sgnn switch_port_config->rmac_util_period = 2112221167Sgnn VXGE_HAL_SWITCH_PORT_DEF_RMAC_UTIL_PERIOD; 2113221167Sgnn 2114221167Sgnn switch_port_config->rmac_pause_gen_en = 2115221167Sgnn VXGE_HAL_SWITCH_PORT_RMAC_PAUSE_GEN_EN_DEFAULT; 2116221167Sgnn 2117221167Sgnn switch_port_config->rmac_pause_rcv_en = 2118221167Sgnn VXGE_HAL_SWITCH_PORT_RMAC_PAUSE_RCV_EN_DEFAULT; 2119221167Sgnn 2120221167Sgnn switch_port_config->rmac_pause_time = 2121221167Sgnn VXGE_HAL_SWITCH_PORT_DEF_RMAC_HIGH_PTIME; 2122221167Sgnn 2123221167Sgnn switch_port_config->limiter_en = 2124221167Sgnn VXGE_HAL_SWITCH_PORT_RMAC_PAUSE_LIMITER_DEFAULT; 2125221167Sgnn 2126221167Sgnn switch_port_config->max_limit = 2127221167Sgnn VXGE_HAL_SWITCH_PORT_DEF_RMAC_MAX_LIMIT; 2128221167Sgnn 2129221167Sgnn mac_config->network_stability_period = 2130221167Sgnn VXGE_HAL_MAC_DEF_NETWORK_STABILITY_PERIOD; 2131221167Sgnn 2132221167Sgnn for (i = 0; i < 16; i++) { 2133221167Sgnn 2134221167Sgnn mac_config->mc_pause_threshold[i] = 2135221167Sgnn VXGE_HAL_MAC_DEF_MC_PAUSE_THRESHOLD; 2136221167Sgnn 2137221167Sgnn } 2138221167Sgnn 2139221167Sgnn mac_config->tmac_perma_stop_en = 2140221167Sgnn VXGE_HAL_MAC_TMAC_PERMA_STOP_DEFAULT; 2141221167Sgnn 2142221167Sgnn mac_config->tmac_tx_switch_dis = 2143221167Sgnn VXGE_HAL_MAC_TMAC_TX_SWITCH_DEFAULT; 2144221167Sgnn 2145221167Sgnn mac_config->tmac_lossy_switch_en = 2146221167Sgnn VXGE_HAL_MAC_TMAC_LOSSY_SWITCH_DEFAULT; 2147221167Sgnn 2148221167Sgnn mac_config->tmac_lossy_wire_en = 2149221167Sgnn VXGE_HAL_MAC_TMAC_LOSSY_WIRE_DEFAULT; 2150221167Sgnn 2151221167Sgnn mac_config->tmac_bcast_to_wire_dis = 2152221167Sgnn VXGE_HAL_MAC_TMAC_BCAST_TO_WIRE_DEFAULT; 2153221167Sgnn 2154221167Sgnn mac_config->tmac_bcast_to_switch_dis = 2155221167Sgnn VXGE_HAL_MAC_TMAC_BCAST_TO_SWITCH_DEFAULT; 2156221167Sgnn 2157221167Sgnn mac_config->tmac_host_append_fcs_en = 2158221167Sgnn VXGE_HAL_MAC_TMAC_HOST_APPEND_FCS_DEFAULT; 2159221167Sgnn 2160221167Sgnn mac_config->tpa_support_snap_ab_n = 2161221167Sgnn VXGE_HAL_MAC_TPA_SUPPORT_SNAP_AB_N_DEFAULT; 2162221167Sgnn 2163221167Sgnn mac_config->tpa_ecc_enable_n = 2164221167Sgnn VXGE_HAL_MAC_TPA_ECC_ENABLE_N_DEFAULT; 2165221167Sgnn 2166221167Sgnn mac_config->rpa_ignore_frame_err = 2167221167Sgnn VXGE_HAL_MAC_RPA_IGNORE_FRAME_ERR_DEFAULT; 2168221167Sgnn 2169221167Sgnn mac_config->rpa_support_snap_ab_n = 2170221167Sgnn VXGE_HAL_MAC_RPA_SUPPORT_SNAP_AB_N_DEFAULT; 2171221167Sgnn 2172221167Sgnn mac_config->rpa_search_for_hao = 2173221167Sgnn VXGE_HAL_MAC_RPA_SEARCH_FOR_HAO_DEFAULT; 2174221167Sgnn 2175221167Sgnn mac_config->rpa_support_ipv6_mobile_hdrs = 2176221167Sgnn VXGE_HAL_MAC_RPA_SUPPORT_IPV6_MOBILE_HDRS_DEFAULT; 2177221167Sgnn 2178221167Sgnn mac_config->rpa_ipv6_stop_searching = 2179221167Sgnn VXGE_HAL_MAC_RPA_IPV6_STOP_SEARCHING_DEFAULT; 2180221167Sgnn 2181221167Sgnn mac_config->rpa_no_ps_if_unknown = 2182221167Sgnn VXGE_HAL_MAC_RPA_NO_PS_IF_UNKNOWN_DEFAULT; 2183221167Sgnn 2184221167Sgnn mac_config->rpa_search_for_etype = 2185221167Sgnn VXGE_HAL_MAC_RPA_SEARCH_FOR_ETYPE_DEFAULT; 2186221167Sgnn 2187221167Sgnn mac_config->rpa_repl_l4_comp_csum = 2188221167Sgnn VXGE_HAL_MAC_RPA_REPL_l4_COMP_CSUM_DEFAULT; 2189221167Sgnn 2190221167Sgnn mac_config->rpa_repl_l3_incl_cf = 2191221167Sgnn VXGE_HAL_MAC_RPA_REPL_L3_INCL_CF_DEFAULT; 2192221167Sgnn 2193221167Sgnn mac_config->rpa_repl_l3_comp_csum = 2194221167Sgnn VXGE_HAL_MAC_RPA_REPL_l3_COMP_CSUM_DEFAULT; 2195221167Sgnn 2196221167Sgnn mac_config->rpa_repl_ipv4_tcp_incl_ph = 2197221167Sgnn VXGE_HAL_MAC_RPA_REPL_IPV4_TCP_INCL_PH_DEFAULT; 2198221167Sgnn 2199221167Sgnn mac_config->rpa_repl_ipv6_tcp_incl_ph = 2200221167Sgnn VXGE_HAL_MAC_RPA_REPL_IPV6_TCP_INCL_PH_DEFAULT; 2201221167Sgnn 2202221167Sgnn mac_config->rpa_repl_ipv4_udp_incl_ph = 2203221167Sgnn VXGE_HAL_MAC_RPA_REPL_IPV4_UDP_INCL_PH_DEFAULT; 2204221167Sgnn 2205221167Sgnn mac_config->rpa_repl_ipv6_udp_incl_ph = 2206221167Sgnn VXGE_HAL_MAC_RPA_REPL_IPV6_UDP_INCL_PH_DEFAULT; 2207221167Sgnn 2208221167Sgnn mac_config->rpa_repl_l4_incl_cf = 2209221167Sgnn VXGE_HAL_MAC_RPA_REPL_L4_INCL_CF_DEFAULT; 2210221167Sgnn 2211221167Sgnn mac_config->rpa_repl_strip_vlan_tag = 2212221167Sgnn VXGE_HAL_MAC_RPA_REPL_STRIP_VLAN_TAG_DEFAULT; 2213221167Sgnn 2214221167Sgnn device_config->mrpcim_config.lag_config.lag_en = 2215221167Sgnn VXGE_HAL_LAG_LAG_EN_DEFAULT; 2216221167Sgnn 2217221167Sgnn device_config->mrpcim_config.lag_config.lag_mode = 2218221167Sgnn VXGE_HAL_LAG_LAG_MODE_DEFAULT; 2219221167Sgnn 2220221167Sgnn device_config->mrpcim_config.lag_config.la_mode_config.tx_discard = 2221221167Sgnn VXGE_HAL_LAG_TX_DISCARD_DEFAULT; 2222221167Sgnn 2223221167Sgnn device_config->mrpcim_config.lag_config.la_mode_config.distrib_alg_sel = 2224221167Sgnn VXGE_HAL_LAG_DISTRIB_ALG_SEL_DEFAULT; 2225221167Sgnn 2226221167Sgnn device_config->mrpcim_config.lag_config.la_mode_config.distrib_dest = 2227221167Sgnn VXGE_HAL_LAG_DISTRIB_DEST_DEFAULT; 2228221167Sgnn 2229221167Sgnn device_config-> 2230221167Sgnn mrpcim_config.lag_config.la_mode_config.distrib_remap_if_fail = 2231221167Sgnn VXGE_HAL_LAG_DISTRIB_REMAP_IF_FAIL_DEFAULT; 2232221167Sgnn 2233221167Sgnn device_config->mrpcim_config.lag_config.la_mode_config.coll_max_delay = 2234221167Sgnn VXGE_HAL_LAG_DEF_COLL_MAX_DELAY; 2235221167Sgnn 2236221167Sgnn device_config->mrpcim_config.lag_config.la_mode_config.rx_discard = 2237221167Sgnn VXGE_HAL_LAG_RX_DISCARD_DEFAULT; 2238221167Sgnn 2239221167Sgnn device_config->mrpcim_config.lag_config.ap_mode_config.hot_standby = 2240221167Sgnn VXGE_HAL_LAG_HOT_STANDBY_DEFAULT; 2241221167Sgnn 2242221167Sgnn device_config->mrpcim_config.lag_config.ap_mode_config.lacp_decides = 2243221167Sgnn VXGE_HAL_LAG_LACP_DECIDES_DEFAULT; 2244221167Sgnn 2245221167Sgnn device_config-> 2246221167Sgnn mrpcim_config.lag_config.ap_mode_config.pref_active_port = 2247221167Sgnn VXGE_HAL_LAG_PREF_ACTIVE_PORT_DEFAULT; 2248221167Sgnn 2249221167Sgnn device_config->mrpcim_config.lag_config.ap_mode_config.auto_failback = 2250221167Sgnn VXGE_HAL_LAG_AUTO_FAILBACK_DEFAULT; 2251221167Sgnn 2252221167Sgnn device_config->mrpcim_config.lag_config.ap_mode_config.failback_en = 2253221167Sgnn VXGE_HAL_LAG_FAILBACK_EN_DEFAULT; 2254221167Sgnn 2255221167Sgnn device_config-> 2256221167Sgnn mrpcim_config.lag_config.ap_mode_config.cold_failover_timeout = 2257221167Sgnn VXGE_HAL_LAG_DEF_COLD_FAILOVER_TIMEOUT; 2258221167Sgnn 2259221167Sgnn device_config->mrpcim_config.lag_config.ap_mode_config.alt_admin_key = 2260221167Sgnn VXGE_HAL_LAG_DEF_ALT_ADMIN_KEY; 2261221167Sgnn 2262221167Sgnn device_config->mrpcim_config.lag_config.ap_mode_config.alt_aggr = 2263221167Sgnn VXGE_HAL_LAG_ALT_AGGR_DEFAULT; 2264221167Sgnn 2265221167Sgnn device_config->mrpcim_config.lag_config.sl_mode_config.pref_indiv_port = 2266221167Sgnn VXGE_HAL_LAG_PREF_INDIV_PORT_DEFAULT; 2267221167Sgnn 2268221167Sgnn device_config->mrpcim_config.lag_config.lacp_config.lacp_en = 2269221167Sgnn VXGE_HAL_LAG_LACP_EN_DEFAULT; 2270221167Sgnn 2271221167Sgnn device_config->mrpcim_config.lag_config.lacp_config.lacp_begin = 2272221167Sgnn VXGE_HAL_LAG_LACP_BEGIN_DEFAULT; 2273221167Sgnn 2274221167Sgnn device_config->mrpcim_config.lag_config.lacp_config.discard_lacp = 2275221167Sgnn VXGE_HAL_LAG_DISCARD_LACP_DEFAULT; 2276221167Sgnn 2277221167Sgnn device_config->mrpcim_config.lag_config.lacp_config.liberal_len_chk = 2278221167Sgnn VXGE_HAL_LAG_LIBERAL_LEN_CHK_DEFAULT; 2279221167Sgnn 2280221167Sgnn device_config->mrpcim_config.lag_config.lacp_config.marker_gen_recv_en = 2281221167Sgnn VXGE_HAL_LAG_MARKER_GEN_RECV_EN_DEFAULT; 2282221167Sgnn 2283221167Sgnn device_config->mrpcim_config.lag_config.lacp_config.marker_resp_en = 2284221167Sgnn VXGE_HAL_LAG_MARKER_RESP_EN_DEFAULT; 2285221167Sgnn 2286221167Sgnn device_config-> 2287221167Sgnn mrpcim_config.lag_config.lacp_config.marker_resp_timeout = 2288221167Sgnn VXGE_HAL_LAG_DEF_MARKER_RESP_TIMEOUT; 2289221167Sgnn 2290221167Sgnn device_config-> 2291221167Sgnn mrpcim_config.lag_config.lacp_config.slow_proto_mrkr_min_interval = 2292221167Sgnn VXGE_HAL_LAG_DEF_SLOW_PROTO_MRKR_MIN_INTERVAL; 2293221167Sgnn 2294221167Sgnn device_config->mrpcim_config.lag_config.lacp_config.throttle_mrkr_resp = 2295221167Sgnn VXGE_HAL_LAG_THROTTLE_MRKR_RESP_DEFAULT; 2296221167Sgnn 2297221167Sgnn device_config->mrpcim_config.lag_config.incr_tx_aggr_stats = 2298221167Sgnn VXGE_HAL_LAG_INCR_TX_AGGR_STATS_DEFAULT; 2299221167Sgnn 2300221167Sgnn for (i = 0; i < VXGE_HAL_LAG_PORT_MAX_PORTS; i++) { 2301221167Sgnn 2302221167Sgnn vxge_hal_lag_port_config_t *port_config = 2303221167Sgnn &device_config->mrpcim_config.lag_config.port_config[i]; 2304221167Sgnn 2305221167Sgnn port_config->port_id = i; 2306221167Sgnn 2307221167Sgnn port_config->lag_en = VXGE_HAL_LAG_PORT_LAG_EN_DEFAULT; 2308221167Sgnn 2309221167Sgnn port_config->discard_slow_proto = 2310221167Sgnn VXGE_HAL_LAG_PORT_DISCARD_SLOW_PROTO_DEFAULT; 2311221167Sgnn 2312221167Sgnn port_config->host_chosen_aggr = 2313221167Sgnn VXGE_HAL_LAG_PORT_HOST_CHOSEN_AGGR_DEFAULT; 2314221167Sgnn 2315221167Sgnn port_config->host_chosen_aggr = 2316221167Sgnn VXGE_HAL_LAG_PORT_HOST_CHOSEN_AGGR_DEFAULT; 2317221167Sgnn 2318221167Sgnn port_config->discard_unknown_slow_proto = 2319221167Sgnn VXGE_HAL_LAG_PORT_DISCARD_UNKNOWN_SLOW_PROTO_DEFAULT; 2320221167Sgnn 2321221167Sgnn port_config->actor_port_num = 2322221167Sgnn VXGE_HAL_LAG_PORT_DEF_ACTOR_PORT_NUM; 2323221167Sgnn 2324221167Sgnn port_config->actor_port_priority = 2325221167Sgnn VXGE_HAL_LAG_PORT_DEF_ACTOR_PORT_PRIORITY; 2326221167Sgnn 2327221167Sgnn port_config->actor_key_10g = 2328221167Sgnn VXGE_HAL_LAG_PORT_DEF_ACTOR_KEY_10G; 2329221167Sgnn 2330221167Sgnn port_config->actor_key_1g = 2331221167Sgnn VXGE_HAL_LAG_PORT_DEF_ACTOR_KEY_1G; 2332221167Sgnn 2333221167Sgnn port_config->actor_lacp_activity = 2334221167Sgnn VXGE_HAL_LAG_PORT_ACTOR_LACP_ACTIVITY_DEFAULT; 2335221167Sgnn 2336221167Sgnn port_config->actor_lacp_timeout = 2337221167Sgnn VXGE_HAL_LAG_PORT_ACTOR_LACP_TIMEOUT_DEFAULT; 2338221167Sgnn 2339221167Sgnn port_config->actor_aggregation = 2340221167Sgnn VXGE_HAL_LAG_PORT_ACTOR_AGGREGATION_DEFAULT; 2341221167Sgnn 2342221167Sgnn port_config->actor_synchronization = 2343221167Sgnn VXGE_HAL_LAG_PORT_ACTOR_SYNCHRONIZATION_DEFAULT; 2344221167Sgnn 2345221167Sgnn port_config->actor_collecting = 2346221167Sgnn VXGE_HAL_LAG_PORT_ACTOR_COLLECTING_DEFAULT; 2347221167Sgnn 2348221167Sgnn port_config->actor_distributing = 2349221167Sgnn VXGE_HAL_LAG_PORT_ACTOR_DISTRIBUTING_DEFAULT; 2350221167Sgnn 2351221167Sgnn port_config->actor_distributing = 2352221167Sgnn VXGE_HAL_LAG_PORT_ACTOR_DISTRIBUTING_DEFAULT; 2353221167Sgnn 2354221167Sgnn port_config->actor_defaulted = 2355221167Sgnn VXGE_HAL_LAG_PORT_ACTOR_DEFAULTED_DEFAULT; 2356221167Sgnn 2357221167Sgnn port_config->actor_expired = 2358221167Sgnn VXGE_HAL_LAG_PORT_ACTOR_EXPIRED_DEFAULT; 2359221167Sgnn 2360221167Sgnn port_config->partner_sys_pri = 2361221167Sgnn VXGE_HAL_LAG_PORT_DEF_PARTNER_SYS_PRI; 2362221167Sgnn 2363221167Sgnn port_config->partner_key = 2364221167Sgnn VXGE_HAL_LAG_PORT_DEF_PARTNER_KEY; 2365221167Sgnn 2366221167Sgnn port_config->partner_port_num = 2367221167Sgnn VXGE_HAL_LAG_PORT_DEF_PARTNER_PORT_NUM; 2368221167Sgnn 2369221167Sgnn port_config->partner_port_priority = 2370221167Sgnn VXGE_HAL_LAG_PORT_DEF_PARTNER_PORT_PRIORITY; 2371221167Sgnn 2372221167Sgnn port_config->partner_lacp_activity = 2373221167Sgnn VXGE_HAL_LAG_PORT_PARTNER_LACP_ACTIVITY_DEFAULT; 2374221167Sgnn 2375221167Sgnn port_config->partner_lacp_timeout = 2376221167Sgnn VXGE_HAL_LAG_PORT_PARTNER_LACP_TIMEOUT_DEFAULT; 2377221167Sgnn 2378221167Sgnn port_config->partner_aggregation = 2379221167Sgnn VXGE_HAL_LAG_PORT_PARTNER_AGGREGATION_DEFAULT; 2380221167Sgnn 2381221167Sgnn port_config->partner_synchronization = 2382221167Sgnn VXGE_HAL_LAG_PORT_PARTNER_SYNCHRONIZATION_DEFAULT; 2383221167Sgnn 2384221167Sgnn port_config->partner_collecting = 2385221167Sgnn VXGE_HAL_LAG_PORT_PARTNER_COLLECTING_DEFAULT; 2386221167Sgnn 2387221167Sgnn port_config->partner_distributing = 2388221167Sgnn VXGE_HAL_LAG_PORT_PARTNER_DISTRIBUTING_DEFAULT; 2389221167Sgnn 2390221167Sgnn port_config->partner_distributing = 2391221167Sgnn VXGE_HAL_LAG_PORT_PARTNER_DISTRIBUTING_DEFAULT; 2392221167Sgnn 2393221167Sgnn port_config->partner_defaulted = 2394221167Sgnn VXGE_HAL_LAG_PORT_PARTNER_DEFAULTED_DEFAULT; 2395221167Sgnn 2396221167Sgnn port_config->partner_expired = 2397221167Sgnn VXGE_HAL_LAG_PORT_PARTNER_EXPIRED_DEFAULT; 2398221167Sgnn 2399221167Sgnn } 2400221167Sgnn 2401221167Sgnn for (i = 0; i < VXGE_HAL_LAG_AGGR_MAX_PORTS; i++) { 2402221167Sgnn 2403221167Sgnn device_config-> 2404221167Sgnn mrpcim_config.lag_config.aggr_config[i].aggr_id = i + 1; 2405221167Sgnn 2406221167Sgnn device_config-> 2407221167Sgnn mrpcim_config.lag_config.aggr_config[i].use_port_mac_addr = 2408221167Sgnn VXGE_HAL_LAG_AGGR_USE_PORT_MAC_ADDR_DEFAULT; 2409221167Sgnn 2410221167Sgnn device_config-> 2411221167Sgnn mrpcim_config.lag_config.aggr_config[i].mac_addr_sel = 2412221167Sgnn VXGE_HAL_LAG_AGGR_MAC_ADDR_SEL_DEFAULT; 2413221167Sgnn 2414221167Sgnn device_config-> 2415221167Sgnn mrpcim_config.lag_config.aggr_config[i].admin_key = 2416221167Sgnn VXGE_HAL_LAG_AGGR_DEF_ADMIN_KEY; 2417221167Sgnn 2418221167Sgnn } 2419221167Sgnn 2420221167Sgnn device_config->mrpcim_config.lag_config.sys_pri = 2421221167Sgnn VXGE_HAL_LAG_DEF_SYS_PRI; 2422221167Sgnn 2423221167Sgnn device_config->mrpcim_config.lag_config.use_port_mac_addr = 2424221167Sgnn VXGE_HAL_LAG_USE_PORT_MAC_ADDR_DEFAULT; 2425221167Sgnn 2426221167Sgnn device_config->mrpcim_config.lag_config.mac_addr_sel = 2427221167Sgnn VXGE_HAL_LAG_MAC_ADDR_SEL_DEFAULT; 2428221167Sgnn 2429221167Sgnn device_config->mrpcim_config.lag_config.fast_per_time = 2430221167Sgnn VXGE_HAL_LAG_DEF_FAST_PER_TIME; 2431221167Sgnn 2432221167Sgnn device_config->mrpcim_config.lag_config.slow_per_time = 2433221167Sgnn VXGE_HAL_LAG_DEF_SLOW_PER_TIME; 2434221167Sgnn 2435221167Sgnn device_config->mrpcim_config.lag_config.short_timeout = 2436221167Sgnn VXGE_HAL_LAG_DEF_SHORT_TIMEOUT; 2437221167Sgnn 2438221167Sgnn device_config->mrpcim_config.lag_config.long_timeout = 2439221167Sgnn VXGE_HAL_LAG_DEF_LONG_TIMEOUT; 2440221167Sgnn 2441221167Sgnn device_config->mrpcim_config.lag_config.churn_det_time = 2442221167Sgnn VXGE_HAL_LAG_DEF_CHURN_DET_TIME; 2443221167Sgnn 2444221167Sgnn device_config->mrpcim_config.lag_config.aggr_wait_time = 2445221167Sgnn VXGE_HAL_LAG_DEF_AGGR_WAIT_TIME; 2446221167Sgnn 2447221167Sgnn device_config->mrpcim_config.lag_config.short_timer_scale = 2448221167Sgnn VXGE_HAL_LAG_SHORT_TIMER_SCALE_DEFAULT; 2449221167Sgnn 2450221167Sgnn device_config->mrpcim_config.lag_config.long_timer_scale = 2451221167Sgnn VXGE_HAL_LAG_LONG_TIMER_SCALE_DEFAULT; 2452221167Sgnn 2453221167Sgnn for (i = 0; i < VXGE_HAL_MAX_VIRTUAL_PATHS; i++) { 2454221167Sgnn 2455221167Sgnn device_config->mrpcim_config.vp_qos[i].priority = 2456221167Sgnn VXGE_HAL_VPATH_QOS_PRIORITY_DEFAULT; 2457221167Sgnn 2458221167Sgnn device_config->mrpcim_config.vp_qos[i].min_bandwidth = 2459221167Sgnn VXGE_HAL_VPATH_QOS_MIN_BANDWIDTH_DEFAULT; 2460221167Sgnn 2461221167Sgnn device_config->mrpcim_config.vp_qos[i].max_bandwidth = 2462221167Sgnn VXGE_HAL_VPATH_QOS_MAX_BANDWIDTH_DEFAULT; 2463221167Sgnn 2464221167Sgnn } 2465221167Sgnn 2466221167Sgnn device_config->isr_polling_cnt = VXGE_HAL_DEF_ISR_POLLING_CNT; 2467221167Sgnn 2468221167Sgnn device_config->max_payload_size = 2469221167Sgnn VXGE_HAL_USE_BIOS_DEFAULT_PAYLOAD_SIZE; 2470221167Sgnn 2471221167Sgnn device_config->mmrb_count = VXGE_HAL_USE_BIOS_DEFAULT_MMRB_COUNT; 2472221167Sgnn 2473221167Sgnn device_config->stats_refresh_time_sec = 2474221167Sgnn VXGE_HAL_USE_FLASH_DEFAULT_STATS_REFRESH_TIME; 2475221167Sgnn 2476221167Sgnn device_config->intr_mode = VXGE_HAL_INTR_MODE_DEF; 2477221167Sgnn 2478221167Sgnn device_config->dump_on_unknown = VXGE_HAL_DUMP_ON_UNKNOWN_DEFAULT; 2479221167Sgnn 2480221167Sgnn device_config->dump_on_serr = VXGE_HAL_DUMP_ON_SERR_DEFAULT; 2481221167Sgnn 2482221167Sgnn device_config->dump_on_critical = VXGE_HAL_DUMP_ON_CRITICAL_DEFAULT; 2483221167Sgnn 2484221167Sgnn device_config->dump_on_eccerr = VXGE_HAL_DUMP_ON_ECCERR_DEFAULT; 2485221167Sgnn 2486221167Sgnn device_config->rth_en = VXGE_HAL_RTH_DEFAULT; 2487221167Sgnn 2488221167Sgnn device_config->rth_it_type = VXGE_HAL_RTH_IT_TYPE_DEFAULT; 2489221167Sgnn 2490221167Sgnn device_config->device_poll_millis = VXGE_HAL_DEF_DEVICE_POLL_MILLIS; 2491221167Sgnn 2492221167Sgnn device_config->rts_mac_en = VXGE_HAL_RTS_MAC_DEFAULT; 2493221167Sgnn 2494221167Sgnn device_config->rts_qos_en = VXGE_HAL_RTS_QOS_DEFAULT; 2495221167Sgnn 2496221167Sgnn device_config->rts_port_en = VXGE_HAL_RTS_PORT_DEFAULT; 2497221167Sgnn 2498221167Sgnn for (i = 0; i < VXGE_HAL_MAX_VIRTUAL_PATHS; i++) { 2499221167Sgnn 2500221167Sgnn device_config->vp_config[i].vp_id = i; 2501221167Sgnn 2502221167Sgnn device_config->vp_config[i].wire_port = 2503221167Sgnn VXGE_HAL_VPATH_USE_DEFAULT_PORT; 2504221167Sgnn 2505221167Sgnn device_config->vp_config[i].priority = 2506221167Sgnn VXGE_HAL_VPATH_PRIORITY_DEFAULT; 2507221167Sgnn 2508221167Sgnn device_config->vp_config[i].bandwidth = 2509221167Sgnn VXGE_HAL_VPATH_BW_LIMIT_DEFAULT; 2510221167Sgnn 2511221167Sgnn device_config->vp_config[i].no_snoop = 2512221167Sgnn VXGE_HAL_VPATH_NO_SNOOP_USE_FLASH_DEFAULT; 2513221167Sgnn 2514221167Sgnn device_config->vp_config[i].ring.enable = 2515221167Sgnn VXGE_HAL_RING_DEFAULT; 2516221167Sgnn 2517221167Sgnn device_config->vp_config[i].ring.ring_length = 2518221167Sgnn VXGE_HAL_DEF_RING_LENGTH; 2519221167Sgnn 2520221167Sgnn device_config->vp_config[i].ring.buffer_mode = 2521221167Sgnn VXGE_HAL_RING_RXD_BUFFER_MODE_DEFAULT; 2522221167Sgnn 2523221167Sgnn device_config->vp_config[i].ring.scatter_mode = 2524221167Sgnn VXGE_HAL_RING_SCATTER_MODE_USE_FLASH_DEFAULT; 2525221167Sgnn 2526221167Sgnn device_config->vp_config[i].ring.post_mode = 2527221167Sgnn VXGE_HAL_RING_POST_MODE_USE_FLASH_DEFAULT; 2528221167Sgnn 2529221167Sgnn device_config->vp_config[i].ring.max_frm_len = 2530221167Sgnn VXGE_HAL_MAX_RING_FRM_LEN_USE_MTU; 2531221167Sgnn 2532221167Sgnn device_config->vp_config[i].ring.no_snoop_bits = 2533221167Sgnn VXGE_HAL_RING_NO_SNOOP_USE_FLASH_DEFAULT; 2534221167Sgnn 2535221167Sgnn device_config->vp_config[i].ring.rx_timer_val = 2536221167Sgnn VXGE_HAL_RING_USE_FLASH_DEFAULT_RX_TIMER_VAL; 2537221167Sgnn 2538221167Sgnn device_config->vp_config[i].ring.greedy_return = 2539221167Sgnn VXGE_HAL_RING_GREEDY_RETURN_USE_FLASH_DEFAULT; 2540221167Sgnn 2541221167Sgnn device_config->vp_config[i].ring.rx_timer_ci = 2542221167Sgnn VXGE_HAL_RING_RX_TIMER_CI_USE_FLASH_DEFAULT; 2543221167Sgnn 2544221167Sgnn device_config->vp_config[i].ring.backoff_interval_us = 2545221167Sgnn VXGE_HAL_USE_FLASH_DEFAULT_BACKOFF_INTERVAL_US; 2546221167Sgnn 2547221167Sgnn device_config->vp_config[i].ring.indicate_max_pkts = 2548221167Sgnn VXGE_HAL_DEF_RING_INDICATE_MAX_PKTS; 2549221167Sgnn 2550221167Sgnn 2551221167Sgnn device_config->vp_config[i].fifo.enable = 2552221167Sgnn VXGE_HAL_FIFO_DEFAULT; 2553221167Sgnn 2554221167Sgnn device_config->vp_config[i].fifo.fifo_length = 2555221167Sgnn VXGE_HAL_DEF_FIFO_LENGTH; 2556221167Sgnn 2557221167Sgnn device_config->vp_config[i].fifo.max_frags = 2558221167Sgnn VXGE_HAL_DEF_FIFO_FRAGS; 2559221167Sgnn 2560221167Sgnn device_config->vp_config[i].fifo.alignment_size = 2561221167Sgnn VXGE_HAL_DEF_FIFO_ALIGNMENT_SIZE; 2562221167Sgnn 2563221167Sgnn device_config->vp_config[i].fifo.max_aligned_frags = 0; 2564221167Sgnn 2565221167Sgnn device_config->vp_config[i].fifo.intr = 2566221167Sgnn VXGE_HAL_FIFO_QUEUE_INTR_DEFAULT; 2567221167Sgnn 2568221167Sgnn device_config->vp_config[i].fifo.no_snoop_bits = 2569221167Sgnn VXGE_HAL_FIFO_NO_SNOOP_DEFAULT; 2570221167Sgnn 2571221167Sgnn 2572221167Sgnn device_config->vp_config[i].tti.intr_enable = 2573221167Sgnn VXGE_HAL_TIM_INTR_DEFAULT; 2574221167Sgnn 2575221167Sgnn device_config->vp_config[i].tti.btimer_val = 2576221167Sgnn VXGE_HAL_USE_FLASH_DEFAULT_TIM_BTIMER_VAL; 2577221167Sgnn 2578221167Sgnn device_config->vp_config[i].tti.timer_ac_en = 2579221167Sgnn VXGE_HAL_TIM_TIMER_AC_USE_FLASH_DEFAULT; 2580221167Sgnn 2581221167Sgnn device_config->vp_config[i].tti.timer_ci_en = 2582221167Sgnn VXGE_HAL_TIM_TIMER_CI_USE_FLASH_DEFAULT; 2583221167Sgnn 2584221167Sgnn device_config->vp_config[i].tti.timer_ri_en = 2585221167Sgnn VXGE_HAL_TIM_TIMER_RI_USE_FLASH_DEFAULT; 2586221167Sgnn 2587221167Sgnn device_config->vp_config[i].tti.rtimer_event_sf = 2588221167Sgnn VXGE_HAL_USE_FLASH_DEFAULT_TIM_RTIMER_EVENT_SF; 2589221167Sgnn 2590221167Sgnn device_config->vp_config[i].tti.rtimer_val = 2591221167Sgnn VXGE_HAL_USE_FLASH_DEFAULT_TIM_RTIMER_VAL; 2592221167Sgnn 2593221167Sgnn device_config->vp_config[i].tti.util_sel = 2594221167Sgnn VXGE_HAL_TIM_UTIL_SEL_USE_FLASH_DEFAULT; 2595221167Sgnn 2596221167Sgnn device_config->vp_config[i].tti.ltimer_val = 2597221167Sgnn VXGE_HAL_USE_FLASH_DEFAULT_TIM_LTIMER_VAL; 2598221167Sgnn 2599221167Sgnn device_config->vp_config[i].tti.txfrm_cnt_en = 2600221167Sgnn VXGE_HAL_TXFRM_CNT_EN_USE_FLASH_DEFAULT; 2601221167Sgnn 2602221167Sgnn device_config->vp_config[i].tti.txd_cnt_en = 2603221167Sgnn VXGE_HAL_TXD_CNT_EN_USE_FLASH_DEFAULT; 2604221167Sgnn 2605221167Sgnn device_config->vp_config[i].tti.urange_a = 2606221167Sgnn VXGE_HAL_USE_FLASH_DEFAULT_TIM_URANGE_A; 2607221167Sgnn 2608221167Sgnn device_config->vp_config[i].tti.uec_a = 2609221167Sgnn VXGE_HAL_USE_FLASH_DEFAULT_TIM_UEC_A; 2610221167Sgnn 2611221167Sgnn device_config->vp_config[i].tti.urange_b = 2612221167Sgnn VXGE_HAL_USE_FLASH_DEFAULT_TIM_URANGE_B; 2613221167Sgnn 2614221167Sgnn device_config->vp_config[i].tti.uec_b = 2615221167Sgnn VXGE_HAL_USE_FLASH_DEFAULT_TIM_UEC_B; 2616221167Sgnn 2617221167Sgnn device_config->vp_config[i].tti.urange_c = 2618221167Sgnn VXGE_HAL_USE_FLASH_DEFAULT_TIM_URANGE_C; 2619221167Sgnn 2620221167Sgnn device_config->vp_config[i].tti.uec_c = 2621221167Sgnn VXGE_HAL_USE_FLASH_DEFAULT_TIM_UEC_C; 2622221167Sgnn 2623221167Sgnn device_config->vp_config[i].tti.uec_d = 2624221167Sgnn VXGE_HAL_USE_FLASH_DEFAULT_TIM_UEC_D; 2625221167Sgnn 2626221167Sgnn device_config->vp_config[i].tti.ufca_intr_thres = 2627221167Sgnn VXGE_HAL_USE_FLASH_DEFAULT_UFCA_INTR_THRES; 2628221167Sgnn 2629221167Sgnn device_config->vp_config[i].tti.ufca_lo_lim = 2630221167Sgnn VXGE_HAL_USE_FLASH_DEFAULT_UFCA_LO_LIM; 2631221167Sgnn 2632221167Sgnn device_config->vp_config[i].tti.ufca_hi_lim = 2633221167Sgnn VXGE_HAL_USE_FLASH_DEFAULT_UFCA_HI_LIM; 2634221167Sgnn 2635221167Sgnn device_config->vp_config[i].tti.ufca_lbolt_period = 2636221167Sgnn VXGE_HAL_USE_FLASH_DEFAULT_UFCA_LBOLT_PERIOD; 2637221167Sgnn 2638221167Sgnn device_config->vp_config[i].rti.intr_enable = 2639221167Sgnn VXGE_HAL_TIM_INTR_DEFAULT; 2640221167Sgnn 2641221167Sgnn device_config->vp_config[i].rti.btimer_val = 2642221167Sgnn VXGE_HAL_USE_FLASH_DEFAULT_TIM_BTIMER_VAL; 2643221167Sgnn 2644221167Sgnn device_config->vp_config[i].rti.timer_ac_en = 2645221167Sgnn VXGE_HAL_TIM_TIMER_AC_USE_FLASH_DEFAULT; 2646221167Sgnn 2647221167Sgnn device_config->vp_config[i].rti.timer_ci_en = 2648221167Sgnn VXGE_HAL_TIM_TIMER_CI_USE_FLASH_DEFAULT; 2649221167Sgnn 2650221167Sgnn device_config->vp_config[i].rti.timer_ri_en = 2651221167Sgnn VXGE_HAL_TIM_TIMER_RI_USE_FLASH_DEFAULT; 2652221167Sgnn 2653221167Sgnn device_config->vp_config[i].rti.rtimer_event_sf = 2654221167Sgnn VXGE_HAL_USE_FLASH_DEFAULT_TIM_RTIMER_EVENT_SF; 2655221167Sgnn 2656221167Sgnn device_config->vp_config[i].rti.rtimer_val = 2657221167Sgnn VXGE_HAL_USE_FLASH_DEFAULT_TIM_RTIMER_VAL; 2658221167Sgnn 2659221167Sgnn device_config->vp_config[i].rti.util_sel = 2660221167Sgnn VXGE_HAL_TIM_UTIL_SEL_USE_FLASH_DEFAULT; 2661221167Sgnn 2662221167Sgnn device_config->vp_config[i].rti.ltimer_val = 2663221167Sgnn VXGE_HAL_USE_FLASH_DEFAULT_TIM_LTIMER_VAL; 2664221167Sgnn 2665221167Sgnn device_config->vp_config[i].rti.txfrm_cnt_en = 2666221167Sgnn VXGE_HAL_TXFRM_CNT_EN_USE_FLASH_DEFAULT; 2667221167Sgnn 2668221167Sgnn device_config->vp_config[i].rti.txd_cnt_en = 2669221167Sgnn VXGE_HAL_TXD_CNT_EN_USE_FLASH_DEFAULT; 2670221167Sgnn 2671221167Sgnn device_config->vp_config[i].rti.urange_a = 2672221167Sgnn VXGE_HAL_USE_FLASH_DEFAULT_TIM_URANGE_A; 2673221167Sgnn 2674221167Sgnn device_config->vp_config[i].rti.uec_a = 2675221167Sgnn VXGE_HAL_USE_FLASH_DEFAULT_TIM_UEC_A; 2676221167Sgnn 2677221167Sgnn device_config->vp_config[i].rti.urange_b = 2678221167Sgnn VXGE_HAL_USE_FLASH_DEFAULT_TIM_URANGE_B; 2679221167Sgnn 2680221167Sgnn device_config->vp_config[i].rti.uec_b = 2681221167Sgnn VXGE_HAL_USE_FLASH_DEFAULT_TIM_UEC_B; 2682221167Sgnn 2683221167Sgnn device_config->vp_config[i].rti.urange_c = 2684221167Sgnn VXGE_HAL_USE_FLASH_DEFAULT_TIM_URANGE_C; 2685221167Sgnn 2686221167Sgnn device_config->vp_config[i].rti.uec_c = 2687221167Sgnn VXGE_HAL_USE_FLASH_DEFAULT_TIM_UEC_C; 2688221167Sgnn 2689221167Sgnn device_config->vp_config[i].rti.uec_d = 2690221167Sgnn VXGE_HAL_USE_FLASH_DEFAULT_TIM_UEC_D; 2691221167Sgnn 2692221167Sgnn device_config->vp_config[i].rti.ufca_intr_thres = 2693221167Sgnn VXGE_HAL_USE_FLASH_DEFAULT_UFCA_INTR_THRES; 2694221167Sgnn 2695221167Sgnn device_config->vp_config[i].rti.ufca_lo_lim = 2696221167Sgnn VXGE_HAL_USE_FLASH_DEFAULT_UFCA_LO_LIM; 2697221167Sgnn 2698221167Sgnn device_config->vp_config[i].rti.ufca_hi_lim = 2699221167Sgnn VXGE_HAL_USE_FLASH_DEFAULT_UFCA_HI_LIM; 2700221167Sgnn 2701221167Sgnn device_config->vp_config[i].rti.ufca_lbolt_period = 2702221167Sgnn VXGE_HAL_USE_FLASH_DEFAULT_UFCA_LBOLT_PERIOD; 2703221167Sgnn 2704221167Sgnn device_config->vp_config[i].mtu = 2705221167Sgnn VXGE_HAL_VPATH_USE_FLASH_DEFAULT_INITIAL_MTU; 2706221167Sgnn 2707221167Sgnn device_config->vp_config[i].tpa_lsov2_en = 2708221167Sgnn VXGE_HAL_VPATH_TPA_LSOV2_EN_USE_FLASH_DEFAULT; 2709221167Sgnn 2710221167Sgnn device_config->vp_config[i].tpa_ignore_frame_error = 2711221167Sgnn VXGE_HAL_VPATH_TPA_IGNORE_FRAME_ERROR_USE_FLASH_DEFAULT; 2712221167Sgnn 2713221167Sgnn device_config->vp_config[i].tpa_ipv6_keep_searching = 2714221167Sgnn VXGE_HAL_VPATH_TPA_IPV6_KEEP_SEARCHING_USE_FLASH_DEFAULT; 2715221167Sgnn 2716221167Sgnn device_config->vp_config[i].tpa_l4_pshdr_present = 2717221167Sgnn VXGE_HAL_VPATH_TPA_L4_PSHDR_PRESENT_USE_FLASH_DEFAULT; 2718221167Sgnn 2719221167Sgnn device_config->vp_config[i].tpa_support_mobile_ipv6_hdrs = 2720221167Sgnn VXGE_HAL_VPATH_TPA_SUPPORT_MOBILE_IPV6_HDRS_DEFAULT; 2721221167Sgnn 2722221167Sgnn device_config->vp_config[i].rpa_ipv4_tcp_incl_ph = 2723221167Sgnn VXGE_HAL_VPATH_RPA_IPV4_TCP_INCL_PH_USE_FLASH_DEFAULT; 2724221167Sgnn 2725221167Sgnn device_config->vp_config[i].rpa_ipv6_tcp_incl_ph = 2726221167Sgnn VXGE_HAL_VPATH_RPA_IPV6_TCP_INCL_PH_USE_FLASH_DEFAULT; 2727221167Sgnn 2728221167Sgnn device_config->vp_config[i].rpa_ipv4_udp_incl_ph = 2729221167Sgnn VXGE_HAL_VPATH_RPA_IPV4_UDP_INCL_PH_USE_FLASH_DEFAULT; 2730221167Sgnn 2731221167Sgnn device_config->vp_config[i].rpa_ipv6_udp_incl_ph = 2732221167Sgnn VXGE_HAL_VPATH_RPA_IPV6_UDP_INCL_PH_USE_FLASH_DEFAULT; 2733221167Sgnn 2734221167Sgnn device_config->vp_config[i].rpa_l4_incl_cf = 2735221167Sgnn VXGE_HAL_VPATH_RPA_L4_INCL_CF_USE_FLASH_DEFAULT; 2736221167Sgnn 2737221167Sgnn device_config->vp_config[i].rpa_strip_vlan_tag = 2738221167Sgnn VXGE_HAL_VPATH_RPA_STRIP_VLAN_TAG_USE_FLASH_DEFAULT; 2739221167Sgnn 2740221167Sgnn device_config->vp_config[i].rpa_l4_comp_csum = 2741221167Sgnn VXGE_HAL_VPATH_RPA_L4_COMP_CSUM_USE_FLASH_DEFAULT; 2742221167Sgnn 2743221167Sgnn device_config->vp_config[i].rpa_l3_incl_cf = 2744221167Sgnn VXGE_HAL_VPATH_RPA_L3_INCL_CF_USE_FLASH_DEFAULT; 2745221167Sgnn 2746221167Sgnn device_config->vp_config[i].rpa_l3_comp_csum = 2747221167Sgnn VXGE_HAL_VPATH_RPA_L3_COMP_CSUM_USE_FLASH_DEFAULT; 2748221167Sgnn 2749221167Sgnn device_config->vp_config[i].rpa_ucast_all_addr_en = 2750221167Sgnn VXGE_HAL_VPATH_RPA_UCAST_ALL_ADDR_USE_FLASH_DEFAULT; 2751221167Sgnn 2752221167Sgnn device_config->vp_config[i].rpa_mcast_all_addr_en = 2753221167Sgnn VXGE_HAL_VPATH_RPA_MCAST_ALL_ADDR_USE_FLASH_DEFAULT; 2754221167Sgnn 2755221167Sgnn device_config->vp_config[i].rpa_bcast_en = 2756221167Sgnn VXGE_HAL_VPATH_RPA_BCAST_USE_FLASH_DEFAULT; 2757221167Sgnn 2758221167Sgnn device_config->vp_config[i].rpa_all_vid_en = 2759221167Sgnn VXGE_HAL_VPATH_RPA_ALL_VID_USE_FLASH_DEFAULT; 2760221167Sgnn 2761221167Sgnn device_config->vp_config[i].vp_queue_l2_flow = 2762221167Sgnn VXGE_HAL_VPATH_VP_Q_L2_FLOW_USE_FLASH_DEFAULT; 2763221167Sgnn 2764221167Sgnn } 2765221167Sgnn 2766221167Sgnn device_config->max_cqe_groups = VXGE_HAL_DEF_MAX_CQE_GROUPS; 2767221167Sgnn 2768221167Sgnn device_config->max_num_wqe_od_groups = VXGE_HAL_DEF_MAX_NUM_OD_GROUPS; 2769221167Sgnn 2770221167Sgnn device_config->no_wqe_threshold = VXGE_HAL_DEF_NO_WQE_THRESHOLD; 2771221167Sgnn 2772221167Sgnn device_config->refill_threshold_high = 2773221167Sgnn VXGE_HAL_DEF_REFILL_THRESHOLD_HIGH; 2774221167Sgnn 2775221167Sgnn device_config->refill_threshold_low = VXGE_HAL_DEF_REFILL_THRESHOLD_LOW; 2776221167Sgnn 2777221167Sgnn device_config->ack_blk_limit = VXGE_HAL_DEF_ACK_BLOCK_LIMIT; 2778221167Sgnn 2779221167Sgnn device_config->poll_or_doorbell = VXGE_HAL_POLL_OR_DOORBELL_DEFAULT; 2780221167Sgnn 2781221167Sgnn device_config->stats_read_method = VXGE_HAL_STATS_READ_METHOD_DEFAULT; 2782221167Sgnn 2783221167Sgnn device_config->debug_level = VXGE_DEBUG_LEVEL_DEF; 2784221167Sgnn 2785221167Sgnn device_config->debug_mask = VXGE_DEBUG_MODULE_MASK_DEF; 2786221167Sgnn 2787221167Sgnn#if defined(VXGE_TRACE_INTO_CIRCULAR_ARR) 2788221167Sgnn device_config->tracebuf_size = VXGE_HAL_DEF_CIRCULAR_ARR; 2789221167Sgnn#endif 2790221167Sgnn vxge_hal_trace_log_driver("<== %s:%s:%d Result = 0", 2791221167Sgnn __FILE__, __func__, __LINE__); 2792221167Sgnn 2793221167Sgnn return (VXGE_HAL_OK); 2794221167Sgnn} 2795221167Sgnn 2796221167Sgnnvoid 2797221167Sgnnvxge_hw_vpath_set_zero_rx_frm_len(vxge_hal_device_h devh, u32 vp_id) 2798221167Sgnn{ 2799221167Sgnn u64 val64; 2800221167Sgnn __hal_device_t *hldev = (__hal_device_t *) devh; 2801221167Sgnn __hal_virtualpath_t *vpath; 2802221167Sgnn 2803221167Sgnn vxge_assert(devh != NULL); 2804221167Sgnn 2805221167Sgnn vpath = (__hal_virtualpath_t *) &hldev->virtual_paths[vp_id]; 2806221167Sgnn 2807221167Sgnn vxge_hal_trace_log_vpath("==> %s:%s:%d", 2808221167Sgnn __FILE__, __func__, __LINE__); 2809221167Sgnn 2810221167Sgnn vxge_hal_trace_log_vpath("devh = 0x"VXGE_OS_STXFMT", vp_id = %d", 2811221167Sgnn (ptr_t) devh, vp_id); 2812221167Sgnn 2813221167Sgnn val64 = vxge_os_pio_mem_read64(vpath->hldev->header.pdev, 2814221167Sgnn vpath->hldev->header.regh0, 2815221167Sgnn &vpath->vp_reg->rxmac_vcfg0); 2816221167Sgnn 2817221167Sgnn val64 &= ~VXGE_HAL_RXMAC_VCFG0_RTS_MAX_FRM_LEN(0x3fff); 2818221167Sgnn 2819221167Sgnn vxge_os_pio_mem_write64(vpath->hldev->header.pdev, 2820221167Sgnn vpath->hldev->header.regh0, 2821221167Sgnn val64, 2822221167Sgnn &vpath->vp_reg->rxmac_vcfg0); 2823221167Sgnn 2824221167Sgnn vxge_hal_trace_log_ring("<== %s:%s:%d Result: 0", 2825221167Sgnn __FILE__, __func__, __LINE__); 2826221167Sgnn 2827221167Sgnn vxge_os_pio_mem_read64(vpath->hldev->header.pdev, 2828221167Sgnn vpath->hldev->header.regh0, 2829221167Sgnn &vpath->vp_reg->rxmac_vcfg0); 2830221167Sgnn} 2831221167Sgnn 2832221167Sgnn/* 2833221167Sgnn * vxge_hw_vpath_wait_receive_idle - Wait for Rx to become idle 2834221167Sgnn * 2835221167Sgnn * Bug: Receive path stuck during small frames blast test after numerous vpath 2836221167Sgnn * reset cycle 2837221167Sgnn * 2838221167Sgnn * Fix: Driver work-around is to ensure that the vpath queue in the FB(frame 2839221167Sgnn * buffer) is empty before reset is asserted. In order to do this driver needs 2840221167Sgnn * to stop RxMAC from sending frames to the queue, e.g., by configuring the 2841221167Sgnn * max frame length for the vpath to 0 or some small value. Driver then polls 2842221167Sgnn * WRDMA registers to check that the ring controller for the vpath is not 2843221167Sgnn * processing frames for a period of time(while having enough RxDs to do so). 2844221167Sgnn * 2845221167Sgnn * Poll 2 registers in the WRDMA, namely the FRM_IN_PROGRESS_CNT_VPn register 2846221167Sgnn * and the PRC_RXD_DOORBELL_VPn register. There is no per-vpath register in 2847221167Sgnn * the frame buffer that indicates if the vpath queue is empty, so determine 2848221167Sgnn * the empty state with 2 conditions: 2849221167Sgnn * 1. There are no frames currently being processed in the WRDMA for 2850221167Sgnn * the vpath, and 2851221167Sgnn * 2. The ring controller for the vpath is not being starved of RxDs 2852221167Sgnn * (otherwise it will not be able to process frames even though the FB vpath 2853221167Sgnn * queue is not empty). 2854221167Sgnn * 2855221167Sgnn * For the second condition, compare the read value of PRC_RXD_DOORBELL_VPn 2856221167Sgnn * register against the RXD_SPAT value for the vpath. 2857221167Sgnn * The ring controller will not attempt to fetch RxDs until it has at least 2858221167Sgnn * RXD_SPAT qwords in the doorbell. A factor of 2 is used just to be safe. 2859221167Sgnn * Additionally, it is also possible that the ring controller is not 2860221167Sgnn * processing frames because of arbitration. The chance of this is very small, 2861221167Sgnn * and we try to reduce it even further by checking that the 2 conditions above 2862221167Sgnn * hold in 3 successive polls. This bug does not occur when frames from the 2863221167Sgnn * reset vpath are not selected back-to-back due to arbitration. 2864221167Sgnn * @hldev: HW device handle. 2865221167Sgnn * @vp_id: Vpath ID. 2866221167Sgnn * Returns: void 2867221167Sgnn */ 2868221167Sgnnvoid 2869221167Sgnnvxge_hw_vpath_wait_receive_idle(vxge_hal_device_h devh, u32 vp_id, 2870221167Sgnn u32 *count, u32 *total_count) 2871221167Sgnn{ 2872221167Sgnn u64 val64; 2873221167Sgnn u32 new_qw_count, rxd_spat; 2874221167Sgnn __hal_device_t *hldev = (__hal_device_t *) devh; 2875221167Sgnn __hal_virtualpath_t *vpath; 2876221167Sgnn 2877221167Sgnn vpath = &hldev->virtual_paths[vp_id]; 2878221167Sgnn 2879221167Sgnn vxge_assert(vpath != NULL); 2880221167Sgnn 2881221167Sgnn vxge_hal_trace_log_vpath("==> %s:%s:%d", 2882221167Sgnn __FILE__, __func__, __LINE__); 2883221167Sgnn 2884221167Sgnn vxge_hal_trace_log_vpath("vpath_handle = 0x"VXGE_OS_STXFMT, 2885221167Sgnn (ptr_t) devh); 2886221167Sgnn 2887221167Sgnn if (vpath->vp_config->ring.enable == VXGE_HAL_RING_DISABLE) { 2888221167Sgnn vxge_hal_trace_log_vpath("<== %s:%s:%d ", 2889221167Sgnn __FILE__, __func__, __LINE__); 2890221167Sgnn return; 2891221167Sgnn } 2892221167Sgnn 2893221167Sgnn do { 2894221167Sgnn vxge_os_mdelay(10); 2895221167Sgnn 2896221167Sgnn val64 = vxge_os_pio_mem_read64( 2897221167Sgnn hldev->header.pdev, 2898221167Sgnn hldev->header.regh0, 2899221167Sgnn &vpath->vp_reg->prc_rxd_doorbell); 2900221167Sgnn 2901221167Sgnn new_qw_count = 2902221167Sgnn (u32) VXGE_HAL_PRC_RXD_DOORBELL_GET_NEW_QW_CNT(val64); 2903221167Sgnn 2904221167Sgnn val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 2905221167Sgnn hldev->header.regh0, 2906221167Sgnn &vpath->vp_reg->prc_cfg6); 2907221167Sgnn 2908221167Sgnn rxd_spat = (u32) VXGE_HAL_PRC_CFG6_GET_RXD_SPAT(val64) + 1; 2909221167Sgnn 2910221167Sgnn val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 2911221167Sgnn hldev->header.regh0, 2912221167Sgnn &vpath->vp_reg->frm_in_progress_cnt); 2913221167Sgnn 2914221167Sgnn /* 2915221167Sgnn * Check if there is enough RxDs with HW AND 2916221167Sgnn * it is not processing any frames. 2917221167Sgnn */ 2918221167Sgnn 2919221167Sgnn if ((new_qw_count <= 2 * rxd_spat) || (val64 > 0)) 2920221167Sgnn *count = 0; 2921221167Sgnn else 2922221167Sgnn (*count)++; 2923221167Sgnn (*total_count)++; 2924221167Sgnn 2925221167Sgnn } while ((*count < VXGE_HW_MIN_SUCCESSIVE_IDLE_COUNT) && 2926221167Sgnn (*total_count < VXGE_HW_MAX_POLLING_COUNT)); 2927221167Sgnn 2928221167Sgnn vxge_hal_trace_log_vpath("<== %s:%s:%d", 2929221167Sgnn __FILE__, __func__, __LINE__); 2930221167Sgnn 2931221167Sgnn vxge_assert(*total_count < VXGE_HW_MAX_POLLING_COUNT); 2932221167Sgnn} 2933