vga.c revision 219888
1/*- 2 * Copyright (c) 2005 Marcel Moolenaar 3 * All rights reserved. 4 * 5 * Copyright (c) 2009 The FreeBSD Foundation 6 * All rights reserved. 7 * 8 * Portions of this software were developed by Ed Schouten 9 * under sponsorship from the FreeBSD Foundation. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: user/ed/newcons/sys/dev/vt/hw/vga/vga.c 219888 2011-03-22 21:31:31Z ed $"); 35 36#include <sys/param.h> 37#include <sys/kernel.h> 38#include <sys/systm.h> 39 40#include <dev/vt/vt.h> 41#include <dev/vt/hw/vga/vga_reg.h> 42 43#include <machine/bus.h> 44 45#if defined(__amd64__) || defined(__i386__) 46#include <vm/vm.h> 47#include <vm/pmap.h> 48#include <machine/pmap.h> 49#include <machine/vmparam.h> 50#endif /* __amd64__ || __i386__ */ 51 52struct vga_softc { 53 bus_space_tag_t vga_fb_tag; 54 bus_space_handle_t vga_fb_handle; 55 bus_space_tag_t vga_reg_tag; 56 bus_space_handle_t vga_reg_handle; 57 int vga_curcolor; 58}; 59 60/* Convenience macros. */ 61#define MEM_READ1(sc, ofs) \ 62 bus_space_read_1(sc->vga_fb_tag, sc->vga_fb_handle, ofs) 63#define MEM_WRITE1(sc, ofs, val) \ 64 bus_space_write_1(sc->vga_fb_tag, sc->vga_fb_handle, ofs, val) 65#define REG_READ1(sc, reg) \ 66 bus_space_read_1(sc->vga_reg_tag, sc->vga_reg_handle, reg) 67#define REG_WRITE1(sc, reg, val) \ 68 bus_space_write_1(sc->vga_reg_tag, sc->vga_reg_handle, reg, val) 69 70#define VT_VGA_WIDTH 640 71#define VT_VGA_HEIGHT 480 72#define VT_VGA_MEMSIZE (VT_VGA_WIDTH * VT_VGA_HEIGHT / 8) 73 74static vd_init_t vga_init; 75static vd_blank_t vga_blank; 76static vd_bitblt_t vga_bitblt; 77static vd_putchar_t vga_putchar; 78 79static const struct vt_driver vt_vga_driver = { 80 .vd_init = vga_init, 81 .vd_blank = vga_blank, 82 .vd_bitblt = vga_bitblt, 83 .vd_putchar = vga_putchar, 84}; 85 86/* 87 * Driver supports both text mode and graphics mode. Make sure the 88 * buffer is always big enough to support both. 89 */ 90static struct vga_softc vga_conssoftc; 91VT_CONSDEV_DECLARE(vt_vga_driver, MAX(80, PIXEL_WIDTH(VT_VGA_WIDTH)), 92 MAX(25, PIXEL_HEIGHT(VT_VGA_HEIGHT)), &vga_conssoftc); 93 94static inline void 95vga_setcolor(struct vt_device *vd, term_color_t color) 96{ 97 struct vga_softc *sc = vd->vd_softc; 98 99 if (sc->vga_curcolor != color) { 100 REG_WRITE1(sc, VGA_GC_ADDRESS, VGA_GC_SET_RESET); 101 REG_WRITE1(sc, VGA_GC_DATA, color); 102 sc->vga_curcolor = color; 103 } 104} 105 106static void 107vga_blank(struct vt_device *vd, term_color_t color) 108{ 109 struct vga_softc *sc = vd->vd_softc; 110 u_int ofs; 111 112 vga_setcolor(vd, color); 113 for (ofs = 0; ofs < VT_VGA_MEMSIZE; ofs++) 114 MEM_WRITE1(sc, ofs, 0xff); 115} 116 117static inline void 118vga_bitblt_put(struct vt_device *vd, u_long dst, term_color_t color, 119 uint8_t v) 120{ 121 struct vga_softc *sc = vd->vd_softc; 122 123 /* Skip empty writes, in order to avoid palette changes. */ 124 if (v != 0x00) { 125 vga_setcolor(vd, color); 126 /* 127 * When this MEM_READ1() gets disabled, all sorts of 128 * artifacts occur. This is because this read loads the 129 * set of 8 pixels that are about to be changed. There 130 * is one scenario where we can avoid the read, namely 131 * if all pixels are about to be overwritten anyway. 132 */ 133 if (v != 0xff) 134 MEM_READ1(sc, dst); 135 MEM_WRITE1(sc, dst, v); 136 } 137} 138 139static inline void 140vga_bitblt_draw(struct vt_device *vd, const uint8_t *src, 141 u_long ldst, uint8_t shift, unsigned int width, unsigned int height, 142 term_color_t color, int negate) 143{ 144 u_long dst; 145 int w; 146 uint8_t b, r, out; 147 148 for (; height > 0; height--) { 149 dst = ldst; 150 ldst += VT_VGA_WIDTH / 8; 151 r = 0; 152 for (w = width; w > 0; w -= 8) { 153 b = *src++; 154 if (negate) { 155 b = ~b; 156 /* Don't go too far. */ 157 if (w < 8) 158 b &= 0xff << (8 - w); 159 } 160 /* Reintroduce bits from previous column. */ 161 out = (b >> shift) | r; 162 r = b << (8 - shift); 163 vga_bitblt_put(vd, dst++, color, out); 164 } 165 /* Print the remainder. */ 166 vga_bitblt_put(vd, dst, color, r); 167 } 168} 169 170static void 171vga_bitblt(struct vt_device *vd, const uint8_t *src, 172 vt_axis_t top, vt_axis_t left, unsigned int width, unsigned int height, 173 term_color_t fg, term_color_t bg) 174{ 175 struct vga_softc *sc = vd->vd_softc; 176 u_long dst; 177 uint8_t shift; 178 179 dst = (VT_VGA_WIDTH * top + left) / 8; 180 shift = left % 8; 181 182 if (sc->vga_curcolor == fg) { 183 vga_bitblt_draw(vd, src, dst, shift, width, height, fg, 0); 184 vga_bitblt_draw(vd, src, dst, shift, width, height, bg, 1); 185 } else { 186 vga_bitblt_draw(vd, src, dst, shift, width, height, bg, 1); 187 vga_bitblt_draw(vd, src, dst, shift, width, height, fg, 0); 188 } 189} 190 191/* 192 * Binary searchable table for Unicode to CP437 conversion. 193 */ 194 195struct unicp437 { 196 uint16_t unicode_base; 197 uint8_t cp437_base; 198 uint8_t length; 199}; 200 201static const struct unicp437 cp437table[] = { 202 { 0x0020, 0x20, 0x5e }, { 0x00a0, 0x20, 0x00 }, 203 { 0x00a1, 0xad, 0x00 }, { 0x00a2, 0x9b, 0x00 }, 204 { 0x00a3, 0x9c, 0x00 }, { 0x00a5, 0x9d, 0x00 }, 205 { 0x00a7, 0x15, 0x00 }, { 0x00aa, 0xa6, 0x00 }, 206 { 0x00ab, 0xae, 0x00 }, { 0x00ac, 0xaa, 0x00 }, 207 { 0x00b0, 0xf8, 0x00 }, { 0x00b1, 0xf1, 0x00 }, 208 { 0x00b2, 0xfd, 0x00 }, { 0x00b5, 0xe6, 0x00 }, 209 { 0x00b6, 0x14, 0x00 }, { 0x00b7, 0xfa, 0x00 }, 210 { 0x00ba, 0xa7, 0x00 }, { 0x00bb, 0xaf, 0x00 }, 211 { 0x00bc, 0xac, 0x00 }, { 0x00bd, 0xab, 0x00 }, 212 { 0x00bf, 0xa8, 0x00 }, { 0x00c4, 0x8e, 0x01 }, 213 { 0x00c6, 0x92, 0x00 }, { 0x00c7, 0x80, 0x00 }, 214 { 0x00c9, 0x90, 0x00 }, { 0x00d1, 0xa5, 0x00 }, 215 { 0x00d6, 0x99, 0x00 }, { 0x00dc, 0x9a, 0x00 }, 216 { 0x00df, 0xe1, 0x00 }, { 0x00e0, 0x85, 0x00 }, 217 { 0x00e1, 0xa0, 0x00 }, { 0x00e2, 0x83, 0x00 }, 218 { 0x00e4, 0x84, 0x00 }, { 0x00e5, 0x86, 0x00 }, 219 { 0x00e6, 0x91, 0x00 }, { 0x00e7, 0x87, 0x00 }, 220 { 0x00e8, 0x8a, 0x00 }, { 0x00e9, 0x82, 0x00 }, 221 { 0x00ea, 0x88, 0x01 }, { 0x00ec, 0x8d, 0x00 }, 222 { 0x00ed, 0xa1, 0x00 }, { 0x00ee, 0x8c, 0x00 }, 223 { 0x00ef, 0x8b, 0x00 }, { 0x00f0, 0xeb, 0x00 }, 224 { 0x00f1, 0xa4, 0x00 }, { 0x00f2, 0x95, 0x00 }, 225 { 0x00f3, 0xa2, 0x00 }, { 0x00f4, 0x93, 0x00 }, 226 { 0x00f6, 0x94, 0x00 }, { 0x00f7, 0xf6, 0x00 }, 227 { 0x00f8, 0xed, 0x00 }, { 0x00f9, 0x97, 0x00 }, 228 { 0x00fa, 0xa3, 0x00 }, { 0x00fb, 0x96, 0x00 }, 229 { 0x00fc, 0x81, 0x00 }, { 0x00ff, 0x98, 0x00 }, 230 { 0x0192, 0x9f, 0x00 }, { 0x0393, 0xe2, 0x00 }, 231 { 0x0398, 0xe9, 0x00 }, { 0x03a3, 0xe4, 0x00 }, 232 { 0x03a6, 0xe8, 0x00 }, { 0x03a9, 0xea, 0x00 }, 233 { 0x03b1, 0xe0, 0x01 }, { 0x03b4, 0xeb, 0x00 }, 234 { 0x03b5, 0xee, 0x00 }, { 0x03bc, 0xe6, 0x00 }, 235 { 0x03c0, 0xe3, 0x00 }, { 0x03c3, 0xe5, 0x00 }, 236 { 0x03c4, 0xe7, 0x00 }, { 0x03c6, 0xed, 0x00 }, 237 { 0x03d5, 0xed, 0x00 }, { 0x2010, 0x2d, 0x00 }, 238 { 0x2014, 0x2d, 0x00 }, { 0x2018, 0x60, 0x00 }, 239 { 0x2019, 0x27, 0x00 }, { 0x201c, 0x22, 0x00 }, 240 { 0x201d, 0x22, 0x00 }, { 0x2022, 0x07, 0x00 }, 241 { 0x203c, 0x13, 0x00 }, { 0x207f, 0xfc, 0x00 }, 242 { 0x20a7, 0x9e, 0x00 }, { 0x20ac, 0xee, 0x00 }, 243 { 0x2126, 0xea, 0x00 }, { 0x2190, 0x1b, 0x00 }, 244 { 0x2191, 0x18, 0x00 }, { 0x2192, 0x1a, 0x00 }, 245 { 0x2193, 0x19, 0x00 }, { 0x2194, 0x1d, 0x00 }, 246 { 0x2195, 0x12, 0x00 }, { 0x21a8, 0x17, 0x00 }, 247 { 0x2202, 0xeb, 0x00 }, { 0x2208, 0xee, 0x00 }, 248 { 0x2211, 0xe4, 0x00 }, { 0x2212, 0x2d, 0x00 }, 249 { 0x2219, 0xf9, 0x00 }, { 0x221a, 0xfb, 0x00 }, 250 { 0x221e, 0xec, 0x00 }, { 0x221f, 0x1c, 0x00 }, 251 { 0x2229, 0xef, 0x00 }, { 0x2248, 0xf7, 0x00 }, 252 { 0x2261, 0xf0, 0x00 }, { 0x2264, 0xf3, 0x00 }, 253 { 0x2265, 0xf2, 0x00 }, { 0x2302, 0x7f, 0x00 }, 254 { 0x2310, 0xa9, 0x00 }, { 0x2320, 0xf4, 0x00 }, 255 { 0x2321, 0xf5, 0x00 }, { 0x2500, 0xc4, 0x00 }, 256 { 0x2502, 0xb3, 0x00 }, { 0x250c, 0xda, 0x00 }, 257 { 0x2510, 0xbf, 0x00 }, { 0x2514, 0xc0, 0x00 }, 258 { 0x2518, 0xd9, 0x00 }, { 0x251c, 0xc3, 0x00 }, 259 { 0x2524, 0xb4, 0x00 }, { 0x252c, 0xc2, 0x00 }, 260 { 0x2534, 0xc1, 0x00 }, { 0x253c, 0xc5, 0x00 }, 261 { 0x2550, 0xcd, 0x00 }, { 0x2551, 0xba, 0x00 }, 262 { 0x2552, 0xd5, 0x00 }, { 0x2553, 0xd6, 0x00 }, 263 { 0x2554, 0xc9, 0x00 }, { 0x2555, 0xb8, 0x00 }, 264 { 0x2556, 0xb7, 0x00 }, { 0x2557, 0xbb, 0x00 }, 265 { 0x2558, 0xd4, 0x00 }, { 0x2559, 0xd3, 0x00 }, 266 { 0x255a, 0xc8, 0x00 }, { 0x255b, 0xbe, 0x00 }, 267 { 0x255c, 0xbd, 0x00 }, { 0x255d, 0xbc, 0x00 }, 268 { 0x255e, 0xc6, 0x01 }, { 0x2560, 0xcc, 0x00 }, 269 { 0x2561, 0xb5, 0x00 }, { 0x2562, 0xb6, 0x00 }, 270 { 0x2563, 0xb9, 0x00 }, { 0x2564, 0xd1, 0x01 }, 271 { 0x2566, 0xcb, 0x00 }, { 0x2567, 0xcf, 0x00 }, 272 { 0x2568, 0xd0, 0x00 }, { 0x2569, 0xca, 0x00 }, 273 { 0x256a, 0xd8, 0x00 }, { 0x256b, 0xd7, 0x00 }, 274 { 0x256c, 0xce, 0x00 }, { 0x2580, 0xdf, 0x00 }, 275 { 0x2584, 0xdc, 0x00 }, { 0x2588, 0xdb, 0x00 }, 276 { 0x258c, 0xdd, 0x00 }, { 0x2590, 0xde, 0x00 }, 277 { 0x2591, 0xb0, 0x02 }, { 0x25a0, 0xfe, 0x00 }, 278 { 0x25ac, 0x16, 0x00 }, { 0x25b2, 0x1e, 0x00 }, 279 { 0x25ba, 0x10, 0x00 }, { 0x25bc, 0x1f, 0x00 }, 280 { 0x25c4, 0x11, 0x00 }, { 0x25cb, 0x09, 0x00 }, 281 { 0x25d8, 0x08, 0x00 }, { 0x25d9, 0x0a, 0x00 }, 282 { 0x263a, 0x01, 0x01 }, { 0x263c, 0x0f, 0x00 }, 283 { 0x2640, 0x0c, 0x00 }, { 0x2642, 0x0b, 0x00 }, 284 { 0x2660, 0x06, 0x00 }, { 0x2663, 0x05, 0x00 }, 285 { 0x2665, 0x03, 0x01 }, { 0x266a, 0x0d, 0x01 }, 286}; 287 288static uint8_t 289vga_get_cp437(term_char_t c) 290{ 291 int min, mid, max; 292 293 min = 0; 294 max = (sizeof(cp437table) / sizeof(struct unicp437)) - 1; 295 296 if (c < cp437table[0].unicode_base || 297 c > cp437table[max].unicode_base + cp437table[max].length) 298 return '?'; 299 300 while (max >= min) { 301 mid = (min + max) / 2; 302 if (c < cp437table[mid].unicode_base) 303 max = mid - 1; 304 else if (c > cp437table[mid].unicode_base + 305 cp437table[mid].length) 306 min = mid + 1; 307 else 308 return (c - cp437table[mid].unicode_base + 309 cp437table[mid].cp437_base); 310 } 311 312 return '?'; 313} 314 315static void 316vga_putchar(struct vt_device *vd, term_char_t c, 317 vt_axis_t top, vt_axis_t left, term_color_t fg, term_color_t bg) 318{ 319 struct vga_softc *sc = vd->vd_softc; 320 uint8_t ch, attr; 321 322 /* 323 * Convert character to CP437, which is the character set used 324 * by the VGA hardware by default. 325 */ 326 ch = vga_get_cp437(c); 327 328 /* 329 * Convert colors to VGA attributes. 330 */ 331 attr = bg << 4 | fg; 332 333 MEM_WRITE1(sc, 0x18000 + (top * 80 + left) * 2 + 0, ch); 334 MEM_WRITE1(sc, 0x18000 + (top * 80 + left) * 2 + 1, attr); 335} 336 337static void 338vga_initialize_graphics(struct vt_device *vd) 339{ 340 struct vga_softc *sc = vd->vd_softc; 341 342 /* Clock select. */ 343 REG_WRITE1(sc, VGA_GEN_MISC_OUTPUT_W, VGA_GEN_MO_VSP | VGA_GEN_MO_HSP | 344 VGA_GEN_MO_PB | VGA_GEN_MO_ER | VGA_GEN_MO_IOA); 345 /* Set sequencer clocking and memory mode. */ 346 REG_WRITE1(sc, VGA_SEQ_ADDRESS, VGA_SEQ_CLOCKING_MODE); 347 REG_WRITE1(sc, VGA_SEQ_DATA, VGA_SEQ_CM_89); 348 REG_WRITE1(sc, VGA_SEQ_ADDRESS, VGA_SEQ_MEMORY_MODE); 349 REG_WRITE1(sc, VGA_SEQ_DATA, VGA_SEQ_MM_OE | VGA_SEQ_MM_EM); 350 351 /* Set the graphics controller in graphics mode. */ 352 REG_WRITE1(sc, VGA_GC_ADDRESS, VGA_GC_MISCELLANEOUS); 353 REG_WRITE1(sc, VGA_GC_DATA, 0x04 + VGA_GC_MISC_GA); 354 /* Program the CRT controller. */ 355 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_HORIZ_TOTAL); 356 REG_WRITE1(sc, VGA_CRTC_DATA, 0x5f); /* 760 */ 357 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_HORIZ_DISP_END); 358 REG_WRITE1(sc, VGA_CRTC_DATA, 0x4f); /* 640 - 8 */ 359 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_START_HORIZ_BLANK); 360 REG_WRITE1(sc, VGA_CRTC_DATA, 0x50); /* 640 */ 361 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_END_HORIZ_BLANK); 362 REG_WRITE1(sc, VGA_CRTC_DATA, VGA_CRTC_EHB_CR + 2); 363 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_START_HORIZ_RETRACE); 364 REG_WRITE1(sc, VGA_CRTC_DATA, 0x54); /* 672 */ 365 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_END_HORIZ_RETRACE); 366 REG_WRITE1(sc, VGA_CRTC_DATA, VGA_CRTC_EHR_EHB + 0); 367 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_VERT_TOTAL); 368 REG_WRITE1(sc, VGA_CRTC_DATA, 0x0b); /* 523 */ 369 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_OVERFLOW); 370 REG_WRITE1(sc, VGA_CRTC_DATA, VGA_CRTC_OF_VT9 | VGA_CRTC_OF_LC8 | 371 VGA_CRTC_OF_VBS8 | VGA_CRTC_OF_VRS8 | VGA_CRTC_OF_VDE8); 372 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_MAX_SCAN_LINE); 373 REG_WRITE1(sc, VGA_CRTC_DATA, VGA_CRTC_MSL_LC9); 374 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_VERT_RETRACE_START); 375 REG_WRITE1(sc, VGA_CRTC_DATA, 0xea); /* 480 + 10 */ 376 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_VERT_RETRACE_END); 377 REG_WRITE1(sc, VGA_CRTC_DATA, 0x0c); 378 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_VERT_DISPLAY_END); 379 REG_WRITE1(sc, VGA_CRTC_DATA, 0xdf); /* 480 - 1*/ 380 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_OFFSET); 381 REG_WRITE1(sc, VGA_CRTC_DATA, 0x28); 382 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_START_VERT_BLANK); 383 REG_WRITE1(sc, VGA_CRTC_DATA, 0xe7); /* 480 + 7 */ 384 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_END_VERT_BLANK); 385 REG_WRITE1(sc, VGA_CRTC_DATA, 0x04); 386 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_MODE_CONTROL); 387 REG_WRITE1(sc, VGA_CRTC_DATA, VGA_CRTC_MC_WB | VGA_CRTC_MC_AW | 388 VGA_CRTC_MC_SRS | VGA_CRTC_MC_CMS); 389 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_LINE_COMPARE); 390 REG_WRITE1(sc, VGA_CRTC_DATA, 0xff); /* 480 + 31 */ 391 392 REG_WRITE1(sc, VGA_GEN_FEATURE_CTRL_W, 0); 393 394 REG_WRITE1(sc, VGA_SEQ_ADDRESS, VGA_SEQ_MAP_MASK); 395 REG_WRITE1(sc, VGA_SEQ_DATA, VGA_SEQ_MM_EM3 | VGA_SEQ_MM_EM2 | 396 VGA_SEQ_MM_EM1 | VGA_SEQ_MM_EM0); 397 REG_WRITE1(sc, VGA_SEQ_ADDRESS, VGA_SEQ_CHAR_MAP_SELECT); 398 REG_WRITE1(sc, VGA_SEQ_DATA, 0); 399 400 REG_WRITE1(sc, VGA_GC_ADDRESS, VGA_GC_SET_RESET); 401 REG_WRITE1(sc, VGA_GC_DATA, 0); 402 REG_WRITE1(sc, VGA_GC_ADDRESS, VGA_GC_ENABLE_SET_RESET); 403 REG_WRITE1(sc, VGA_GC_DATA, 0x0f); 404 REG_WRITE1(sc, VGA_GC_ADDRESS, VGA_GC_COLOR_COMPARE); 405 REG_WRITE1(sc, VGA_GC_DATA, 0); 406 REG_WRITE1(sc, VGA_GC_ADDRESS, VGA_GC_DATA_ROTATE); 407 REG_WRITE1(sc, VGA_GC_DATA, 0); 408 REG_WRITE1(sc, VGA_GC_ADDRESS, VGA_GC_READ_MAP_SELECT); 409 REG_WRITE1(sc, VGA_GC_DATA, 0); 410 REG_WRITE1(sc, VGA_GC_ADDRESS, VGA_GC_MODE); 411 REG_WRITE1(sc, VGA_GC_DATA, 0); 412 REG_WRITE1(sc, VGA_GC_ADDRESS, VGA_GC_COLOR_DONT_CARE); 413 REG_WRITE1(sc, VGA_GC_DATA, 0x0f); 414 REG_WRITE1(sc, VGA_GC_ADDRESS, VGA_GC_BIT_MASK); 415 REG_WRITE1(sc, VGA_GC_DATA, 0xff); 416} 417 418static void 419vga_initialize(struct vt_device *vd, int textmode) 420{ 421 struct vga_softc *sc = vd->vd_softc; 422 uint8_t x; 423 424 /* Make sure the VGA adapter is not in monochrome emulation mode. */ 425 x = REG_READ1(sc, VGA_GEN_MISC_OUTPUT_R); 426 REG_WRITE1(sc, VGA_GEN_MISC_OUTPUT_W, x | VGA_GEN_MO_IOA); 427 428 /* Unprotect CRTC registers 0-7. */ 429 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_VERT_RETRACE_END); 430 x = REG_READ1(sc, VGA_CRTC_DATA); 431 REG_WRITE1(sc, VGA_CRTC_DATA, x & ~VGA_CRTC_VRE_PR); 432 433 /* 434 * Wait for the vertical retrace. 435 * NOTE: this code reads the VGA_GEN_INPUT_STAT_1 register, which has 436 * the side-effect of clearing the internal flip-flip of the attribute 437 * controller's write register. This means that because this code is 438 * here, we know for sure that the first write to the attribute 439 * controller will be a write to the address register. Removing this 440 * code therefore also removes that guarantee and appropriate measures 441 * need to be taken. 442 */ 443 do { 444 x = REG_READ1(sc, VGA_GEN_INPUT_STAT_1); 445 x &= VGA_GEN_IS1_VR | VGA_GEN_IS1_DE; 446 } while (x != (VGA_GEN_IS1_VR | VGA_GEN_IS1_DE)); 447 448 /* Now, disable the sync. signals. */ 449 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_MODE_CONTROL); 450 x = REG_READ1(sc, VGA_CRTC_DATA); 451 REG_WRITE1(sc, VGA_CRTC_DATA, x & ~VGA_CRTC_MC_HR); 452 453 /* Asynchronous sequencer reset. */ 454 REG_WRITE1(sc, VGA_SEQ_ADDRESS, VGA_SEQ_RESET); 455 REG_WRITE1(sc, VGA_SEQ_DATA, VGA_SEQ_RST_SR); 456 457 if (!textmode) 458 vga_initialize_graphics(vd); 459 460 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_PRESET_ROW_SCAN); 461 REG_WRITE1(sc, VGA_CRTC_DATA, 0); 462 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_CURSOR_START); 463 REG_WRITE1(sc, VGA_CRTC_DATA, VGA_CRTC_CS_COO); 464 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_CURSOR_END); 465 REG_WRITE1(sc, VGA_CRTC_DATA, 0); 466 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_START_ADDR_HIGH); 467 REG_WRITE1(sc, VGA_CRTC_DATA, 0); 468 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_START_ADDR_LOW); 469 REG_WRITE1(sc, VGA_CRTC_DATA, 0); 470 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_CURSOR_LOC_HIGH); 471 REG_WRITE1(sc, VGA_CRTC_DATA, 0); 472 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_CURSOR_LOC_LOW); 473 REG_WRITE1(sc, VGA_CRTC_DATA, 0x59); 474 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_UNDERLINE_LOC); 475 REG_WRITE1(sc, VGA_CRTC_DATA, VGA_CRTC_UL_UL); 476 477 if (textmode) { 478 /* Set the attribute controller to blink disable. */ 479 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_MODE_CONTROL); 480 REG_WRITE1(sc, VGA_AC_WRITE, 0); 481 } else { 482 /* Set the attribute controller in graphics mode. */ 483 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_MODE_CONTROL); 484 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_MC_GA); 485 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_HORIZ_PIXEL_PANNING); 486 REG_WRITE1(sc, VGA_AC_WRITE, 0); 487 } 488 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PALETTE(0)); 489 REG_WRITE1(sc, VGA_AC_WRITE, 0); 490 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PALETTE(1)); 491 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PAL_R); 492 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PALETTE(2)); 493 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PAL_G); 494 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PALETTE(3)); 495 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PAL_SG | VGA_AC_PAL_R); 496 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PALETTE(4)); 497 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PAL_B); 498 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PALETTE(5)); 499 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PAL_R | VGA_AC_PAL_B); 500 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PALETTE(6)); 501 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PAL_G | VGA_AC_PAL_B); 502 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PALETTE(7)); 503 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PAL_R | VGA_AC_PAL_G | VGA_AC_PAL_B); 504 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PALETTE(8)); 505 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PAL_SR | VGA_AC_PAL_SG | 506 VGA_AC_PAL_SB); 507 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PALETTE(9)); 508 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PAL_SR | VGA_AC_PAL_SG | 509 VGA_AC_PAL_SB | VGA_AC_PAL_R); 510 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PALETTE(10)); 511 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PAL_SR | VGA_AC_PAL_SG | 512 VGA_AC_PAL_SB | VGA_AC_PAL_G); 513 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PALETTE(11)); 514 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PAL_SR | VGA_AC_PAL_SG | 515 VGA_AC_PAL_SB | VGA_AC_PAL_R | VGA_AC_PAL_G); 516 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PALETTE(12)); 517 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PAL_SR | VGA_AC_PAL_SG | 518 VGA_AC_PAL_SB | VGA_AC_PAL_B); 519 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PALETTE(13)); 520 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PAL_SR | VGA_AC_PAL_SG | 521 VGA_AC_PAL_SB | VGA_AC_PAL_R | VGA_AC_PAL_B); 522 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PALETTE(14)); 523 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PAL_SR | VGA_AC_PAL_SG | 524 VGA_AC_PAL_SB | VGA_AC_PAL_G | VGA_AC_PAL_B); 525 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PALETTE(15)); 526 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PAL_SR | VGA_AC_PAL_SG | 527 VGA_AC_PAL_SB | VGA_AC_PAL_R | VGA_AC_PAL_G | VGA_AC_PAL_B); 528 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_OVERSCAN_COLOR); 529 REG_WRITE1(sc, VGA_AC_WRITE, 0); 530 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_COLOR_PLANE_ENABLE); 531 REG_WRITE1(sc, VGA_AC_WRITE, 0x0f); 532 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_COLOR_SELECT); 533 REG_WRITE1(sc, VGA_AC_WRITE, 0); 534 535 if (!textmode) { 536 u_int ofs; 537 538 /* 539 * Done. Clear the frame buffer. All bit planes are 540 * enabled, so a single-paged loop should clear all 541 * planes. 542 */ 543 for (ofs = 0; ofs < VT_VGA_MEMSIZE; ofs++) { 544 MEM_READ1(sc, ofs); 545 MEM_WRITE1(sc, ofs, 0); 546 } 547 } 548 549 /* Re-enable the sequencer. */ 550 REG_WRITE1(sc, VGA_SEQ_ADDRESS, VGA_SEQ_RESET); 551 REG_WRITE1(sc, VGA_SEQ_DATA, VGA_SEQ_RST_SR | VGA_SEQ_RST_NAR); 552 /* Re-enable the sync signals. */ 553 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_MODE_CONTROL); 554 x = REG_READ1(sc, VGA_CRTC_DATA); 555 REG_WRITE1(sc, VGA_CRTC_DATA, x | VGA_CRTC_MC_HR); 556 557 if (!textmode) { 558 /* Switch to write mode 3, because we'll mainly do bitblt. */ 559 REG_WRITE1(sc, VGA_GC_ADDRESS, VGA_GC_MODE); 560 REG_WRITE1(sc, VGA_GC_DATA, 3); 561 REG_WRITE1(sc, VGA_GC_ADDRESS, VGA_GC_ENABLE_SET_RESET); 562 REG_WRITE1(sc, VGA_GC_DATA, 0x0f); 563 } 564} 565 566static int 567vga_init(struct vt_device *vd) 568{ 569 struct vga_softc *sc = vd->vd_softc; 570 int textmode = 0; 571 572#if defined(__amd64__) 573 sc->vga_fb_tag = AMD64_BUS_SPACE_MEM; 574 sc->vga_fb_handle = KERNBASE + VGA_MEM_BASE; 575 sc->vga_reg_tag = AMD64_BUS_SPACE_IO; 576 sc->vga_reg_handle = VGA_REG_BASE; 577#elif defined(__i386__) 578 sc->vga_fb_tag = I386_BUS_SPACE_MEM; 579 sc->vga_fb_handle = KERNBASE + VGA_MEM_BASE; 580 sc->vga_reg_tag = I386_BUS_SPACE_IO; 581 sc->vga_reg_handle = VGA_REG_BASE; 582#else 583# error "Architecture not yet supported!" 584#endif 585 586 TUNABLE_INT_FETCH("hw.vga.textmode", &textmode); 587 if (textmode) { 588 vd->vd_flags |= VDF_TEXTMODE; 589 vd->vd_width = 80; 590 vd->vd_height = 25; 591 } else { 592 vd->vd_width = VT_VGA_WIDTH; 593 vd->vd_height = VT_VGA_HEIGHT; 594 } 595 vga_initialize(vd, textmode); 596 597 return (CN_INTERNAL); 598} 599