if_vr.c revision 151773
1/*- 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/dev/vr/if_vr.c 151773 2005-10-27 21:18:37Z jhb $"); 35 36/* 37 * VIA Rhine fast ethernet PCI NIC driver 38 * 39 * Supports various network adapters based on the VIA Rhine 40 * and Rhine II PCI controllers, including the D-Link DFE530TX. 41 * Datasheets are available at http://www.via.com.tw. 42 * 43 * Written by Bill Paul <wpaul@ctr.columbia.edu> 44 * Electrical Engineering Department 45 * Columbia University, New York City 46 */ 47 48/* 49 * The VIA Rhine controllers are similar in some respects to the 50 * the DEC tulip chips, except less complicated. The controller 51 * uses an MII bus and an external physical layer interface. The 52 * receiver has a one entry perfect filter and a 64-bit hash table 53 * multicast filter. Transmit and receive descriptors are similar 54 * to the tulip. 55 * 56 * The Rhine has a serious flaw in its transmit DMA mechanism: 57 * transmit buffers must be longword aligned. Unfortunately, 58 * FreeBSD doesn't guarantee that mbufs will be filled in starting 59 * at longword boundaries, so we have to do a buffer copy before 60 * transmission. 61 */ 62 63#ifdef HAVE_KERNEL_OPTION_HEADERS 64#include "opt_device_polling.h" 65#endif 66 67#include <sys/param.h> 68#include <sys/systm.h> 69#include <sys/sockio.h> 70#include <sys/mbuf.h> 71#include <sys/malloc.h> 72#include <sys/kernel.h> 73#include <sys/module.h> 74#include <sys/socket.h> 75 76#include <net/if.h> 77#include <net/if_arp.h> 78#include <net/ethernet.h> 79#include <net/if_dl.h> 80#include <net/if_media.h> 81#include <net/if_types.h> 82 83#include <net/bpf.h> 84 85#include <vm/vm.h> /* for vtophys */ 86#include <vm/pmap.h> /* for vtophys */ 87#include <machine/bus.h> 88#include <machine/resource.h> 89#include <sys/bus.h> 90#include <sys/rman.h> 91 92#include <dev/mii/mii.h> 93#include <dev/mii/miivar.h> 94 95#include <dev/pci/pcireg.h> 96#include <dev/pci/pcivar.h> 97 98#define VR_USEIOSPACE 99 100#include <pci/if_vrreg.h> 101 102MODULE_DEPEND(vr, pci, 1, 1, 1); 103MODULE_DEPEND(vr, ether, 1, 1, 1); 104MODULE_DEPEND(vr, miibus, 1, 1, 1); 105 106/* "device miibus" required. See GENERIC if you get errors here. */ 107#include "miibus_if.h" 108 109#undef VR_USESWSHIFT 110 111/* 112 * Various supported device vendors/types and their names. 113 */ 114static struct vr_type vr_devs[] = { 115 { VIA_VENDORID, VIA_DEVICEID_RHINE, 116 "VIA VT3043 Rhine I 10/100BaseTX" }, 117 { VIA_VENDORID, VIA_DEVICEID_RHINE_II, 118 "VIA VT86C100A Rhine II 10/100BaseTX" }, 119 { VIA_VENDORID, VIA_DEVICEID_RHINE_II_2, 120 "VIA VT6102 Rhine II 10/100BaseTX" }, 121 { VIA_VENDORID, VIA_DEVICEID_RHINE_III, 122 "VIA VT6105 Rhine III 10/100BaseTX" }, 123 { VIA_VENDORID, VIA_DEVICEID_RHINE_III_M, 124 "VIA VT6105M Rhine III 10/100BaseTX" }, 125 { DELTA_VENDORID, DELTA_DEVICEID_RHINE_II, 126 "Delta Electronics Rhine II 10/100BaseTX" }, 127 { ADDTRON_VENDORID, ADDTRON_DEVICEID_RHINE_II, 128 "Addtron Technology Rhine II 10/100BaseTX" }, 129 { 0, 0, NULL } 130}; 131 132static int vr_probe(device_t); 133static int vr_attach(device_t); 134static int vr_detach(device_t); 135 136static int vr_newbuf(struct vr_softc *, struct vr_chain_onefrag *, 137 struct mbuf *); 138static int vr_encap(struct vr_softc *, struct vr_chain *, struct mbuf * ); 139 140static void vr_rxeof(struct vr_softc *); 141static void vr_rxeoc(struct vr_softc *); 142static void vr_txeof(struct vr_softc *); 143static void vr_tick(void *); 144static void vr_intr(void *); 145static void vr_start(struct ifnet *); 146static void vr_start_locked(struct ifnet *); 147static int vr_ioctl(struct ifnet *, u_long, caddr_t); 148static void vr_init(void *); 149static void vr_init_locked(struct vr_softc *); 150static void vr_stop(struct vr_softc *); 151static void vr_watchdog(struct ifnet *); 152static void vr_shutdown(device_t); 153static int vr_ifmedia_upd(struct ifnet *); 154static void vr_ifmedia_sts(struct ifnet *, struct ifmediareq *); 155 156#ifdef VR_USESWSHIFT 157static void vr_mii_sync(struct vr_softc *); 158static void vr_mii_send(struct vr_softc *, uint32_t, int); 159#endif 160static int vr_mii_readreg(struct vr_softc *, struct vr_mii_frame *); 161static int vr_mii_writereg(struct vr_softc *, struct vr_mii_frame *); 162static int vr_miibus_readreg(device_t, uint16_t, uint16_t); 163static int vr_miibus_writereg(device_t, uint16_t, uint16_t, uint16_t); 164static void vr_miibus_statchg(device_t); 165 166static void vr_setcfg(struct vr_softc *, int); 167static void vr_setmulti(struct vr_softc *); 168static void vr_reset(struct vr_softc *); 169static int vr_list_rx_init(struct vr_softc *); 170static int vr_list_tx_init(struct vr_softc *); 171 172#ifdef VR_USEIOSPACE 173#define VR_RES SYS_RES_IOPORT 174#define VR_RID VR_PCI_LOIO 175#else 176#define VR_RES SYS_RES_MEMORY 177#define VR_RID VR_PCI_LOMEM 178#endif 179 180static device_method_t vr_methods[] = { 181 /* Device interface */ 182 DEVMETHOD(device_probe, vr_probe), 183 DEVMETHOD(device_attach, vr_attach), 184 DEVMETHOD(device_detach, vr_detach), 185 DEVMETHOD(device_shutdown, vr_shutdown), 186 187 /* bus interface */ 188 DEVMETHOD(bus_print_child, bus_generic_print_child), 189 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 190 191 /* MII interface */ 192 DEVMETHOD(miibus_readreg, vr_miibus_readreg), 193 DEVMETHOD(miibus_writereg, vr_miibus_writereg), 194 DEVMETHOD(miibus_statchg, vr_miibus_statchg), 195 196 { 0, 0 } 197}; 198 199static driver_t vr_driver = { 200 "vr", 201 vr_methods, 202 sizeof(struct vr_softc) 203}; 204 205static devclass_t vr_devclass; 206 207DRIVER_MODULE(vr, pci, vr_driver, vr_devclass, 0, 0); 208DRIVER_MODULE(miibus, vr, miibus_driver, miibus_devclass, 0, 0); 209 210#define VR_SETBIT(sc, reg, x) \ 211 CSR_WRITE_1(sc, reg, \ 212 CSR_READ_1(sc, reg) | (x)) 213 214#define VR_CLRBIT(sc, reg, x) \ 215 CSR_WRITE_1(sc, reg, \ 216 CSR_READ_1(sc, reg) & ~(x)) 217 218#define VR_SETBIT16(sc, reg, x) \ 219 CSR_WRITE_2(sc, reg, \ 220 CSR_READ_2(sc, reg) | (x)) 221 222#define VR_CLRBIT16(sc, reg, x) \ 223 CSR_WRITE_2(sc, reg, \ 224 CSR_READ_2(sc, reg) & ~(x)) 225 226#define VR_SETBIT32(sc, reg, x) \ 227 CSR_WRITE_4(sc, reg, \ 228 CSR_READ_4(sc, reg) | (x)) 229 230#define VR_CLRBIT32(sc, reg, x) \ 231 CSR_WRITE_4(sc, reg, \ 232 CSR_READ_4(sc, reg) & ~(x)) 233 234#define SIO_SET(x) \ 235 CSR_WRITE_1(sc, VR_MIICMD, \ 236 CSR_READ_1(sc, VR_MIICMD) | (x)) 237 238#define SIO_CLR(x) \ 239 CSR_WRITE_1(sc, VR_MIICMD, \ 240 CSR_READ_1(sc, VR_MIICMD) & ~(x)) 241 242#ifdef VR_USESWSHIFT 243/* 244 * Sync the PHYs by setting data bit and strobing the clock 32 times. 245 */ 246static void 247vr_mii_sync(struct vr_softc *sc) 248{ 249 register int i; 250 251 SIO_SET(VR_MIICMD_DIR|VR_MIICMD_DATAIN); 252 253 for (i = 0; i < 32; i++) { 254 SIO_SET(VR_MIICMD_CLK); 255 DELAY(1); 256 SIO_CLR(VR_MIICMD_CLK); 257 DELAY(1); 258 } 259} 260 261/* 262 * Clock a series of bits through the MII. 263 */ 264static void 265vr_mii_send(struct vr_softc *sc, uint32_t bits, int cnt) 266{ 267 int i; 268 269 SIO_CLR(VR_MIICMD_CLK); 270 271 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 272 if (bits & i) { 273 SIO_SET(VR_MIICMD_DATAIN); 274 } else { 275 SIO_CLR(VR_MIICMD_DATAIN); 276 } 277 DELAY(1); 278 SIO_CLR(VR_MIICMD_CLK); 279 DELAY(1); 280 SIO_SET(VR_MIICMD_CLK); 281 } 282} 283#endif 284 285/* 286 * Read an PHY register through the MII. 287 */ 288static int 289vr_mii_readreg(struct vr_softc *sc, struct vr_mii_frame *frame) 290#ifdef VR_USESWSHIFT 291{ 292 int i, ack; 293 294 /* Set up frame for RX. */ 295 frame->mii_stdelim = VR_MII_STARTDELIM; 296 frame->mii_opcode = VR_MII_READOP; 297 frame->mii_turnaround = 0; 298 frame->mii_data = 0; 299 300 CSR_WRITE_1(sc, VR_MIICMD, 0); 301 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM); 302 303 /* Turn on data xmit. */ 304 SIO_SET(VR_MIICMD_DIR); 305 306 vr_mii_sync(sc); 307 308 /* Send command/address info. */ 309 vr_mii_send(sc, frame->mii_stdelim, 2); 310 vr_mii_send(sc, frame->mii_opcode, 2); 311 vr_mii_send(sc, frame->mii_phyaddr, 5); 312 vr_mii_send(sc, frame->mii_regaddr, 5); 313 314 /* Idle bit. */ 315 SIO_CLR((VR_MIICMD_CLK|VR_MIICMD_DATAIN)); 316 DELAY(1); 317 SIO_SET(VR_MIICMD_CLK); 318 DELAY(1); 319 320 /* Turn off xmit. */ 321 SIO_CLR(VR_MIICMD_DIR); 322 323 /* Check for ack */ 324 SIO_CLR(VR_MIICMD_CLK); 325 DELAY(1); 326 ack = CSR_READ_4(sc, VR_MIICMD) & VR_MIICMD_DATAOUT; 327 SIO_SET(VR_MIICMD_CLK); 328 DELAY(1); 329 330 /* 331 * Now try reading data bits. If the ack failed, we still 332 * need to clock through 16 cycles to keep the PHY(s) in sync. 333 */ 334 if (ack) { 335 for(i = 0; i < 16; i++) { 336 SIO_CLR(VR_MIICMD_CLK); 337 DELAY(1); 338 SIO_SET(VR_MIICMD_CLK); 339 DELAY(1); 340 } 341 goto fail; 342 } 343 344 for (i = 0x8000; i; i >>= 1) { 345 SIO_CLR(VR_MIICMD_CLK); 346 DELAY(1); 347 if (!ack) { 348 if (CSR_READ_4(sc, VR_MIICMD) & VR_MIICMD_DATAOUT) 349 frame->mii_data |= i; 350 DELAY(1); 351 } 352 SIO_SET(VR_MIICMD_CLK); 353 DELAY(1); 354 } 355 356fail: 357 SIO_CLR(VR_MIICMD_CLK); 358 DELAY(1); 359 SIO_SET(VR_MIICMD_CLK); 360 DELAY(1); 361 362 if (ack) 363 return (1); 364 return (0); 365} 366#else 367{ 368 int i; 369 370 /* Set the PHY address. */ 371 CSR_WRITE_1(sc, VR_PHYADDR, (CSR_READ_1(sc, VR_PHYADDR)& 0xe0)| 372 frame->mii_phyaddr); 373 374 /* Set the register address. */ 375 CSR_WRITE_1(sc, VR_MIIADDR, frame->mii_regaddr); 376 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_READ_ENB); 377 378 for (i = 0; i < 10000; i++) { 379 if ((CSR_READ_1(sc, VR_MIICMD) & VR_MIICMD_READ_ENB) == 0) 380 break; 381 DELAY(1); 382 } 383 frame->mii_data = CSR_READ_2(sc, VR_MIIDATA); 384 385 return (0); 386} 387#endif 388 389 390/* 391 * Write to a PHY register through the MII. 392 */ 393static int 394vr_mii_writereg(struct vr_softc *sc, struct vr_mii_frame *frame) 395#ifdef VR_USESWSHIFT 396{ 397 CSR_WRITE_1(sc, VR_MIICMD, 0); 398 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM); 399 400 /* Set up frame for TX. */ 401 frame->mii_stdelim = VR_MII_STARTDELIM; 402 frame->mii_opcode = VR_MII_WRITEOP; 403 frame->mii_turnaround = VR_MII_TURNAROUND; 404 405 /* Turn on data output. */ 406 SIO_SET(VR_MIICMD_DIR); 407 408 vr_mii_sync(sc); 409 410 vr_mii_send(sc, frame->mii_stdelim, 2); 411 vr_mii_send(sc, frame->mii_opcode, 2); 412 vr_mii_send(sc, frame->mii_phyaddr, 5); 413 vr_mii_send(sc, frame->mii_regaddr, 5); 414 vr_mii_send(sc, frame->mii_turnaround, 2); 415 vr_mii_send(sc, frame->mii_data, 16); 416 417 /* Idle bit. */ 418 SIO_SET(VR_MIICMD_CLK); 419 DELAY(1); 420 SIO_CLR(VR_MIICMD_CLK); 421 DELAY(1); 422 423 /* Turn off xmit. */ 424 SIO_CLR(VR_MIICMD_DIR); 425 426 return (0); 427} 428#else 429{ 430 int i; 431 432 /* Set the PHY address. */ 433 CSR_WRITE_1(sc, VR_PHYADDR, (CSR_READ_1(sc, VR_PHYADDR)& 0xe0)| 434 frame->mii_phyaddr); 435 436 /* Set the register address and data to write. */ 437 CSR_WRITE_1(sc, VR_MIIADDR, frame->mii_regaddr); 438 CSR_WRITE_2(sc, VR_MIIDATA, frame->mii_data); 439 440 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_WRITE_ENB); 441 442 for (i = 0; i < 10000; i++) { 443 if ((CSR_READ_1(sc, VR_MIICMD) & VR_MIICMD_WRITE_ENB) == 0) 444 break; 445 DELAY(1); 446 } 447 448 return (0); 449} 450#endif 451 452static int 453vr_miibus_readreg(device_t dev, uint16_t phy, uint16_t reg) 454{ 455 struct vr_mii_frame frame; 456 struct vr_softc *sc = device_get_softc(dev); 457 458 switch (sc->vr_revid) { 459 case REV_ID_VT6102_APOLLO: 460 if (phy != 1) { 461 frame.mii_data = 0; 462 goto out; 463 } 464 default: 465 break; 466 } 467 468 bzero((char *)&frame, sizeof(frame)); 469 frame.mii_phyaddr = phy; 470 frame.mii_regaddr = reg; 471 vr_mii_readreg(sc, &frame); 472 473out: 474 return (frame.mii_data); 475} 476 477static int 478vr_miibus_writereg(device_t dev, uint16_t phy, uint16_t reg, uint16_t data) 479{ 480 struct vr_mii_frame frame; 481 struct vr_softc *sc = device_get_softc(dev); 482 483 switch (sc->vr_revid) { 484 case REV_ID_VT6102_APOLLO: 485 if (phy != 1) 486 return (0); 487 default: 488 break; 489 } 490 491 bzero((char *)&frame, sizeof(frame)); 492 frame.mii_phyaddr = phy; 493 frame.mii_regaddr = reg; 494 frame.mii_data = data; 495 vr_mii_writereg(sc, &frame); 496 497 return (0); 498} 499 500static void 501vr_miibus_statchg(device_t dev) 502{ 503 struct mii_data *mii; 504 struct vr_softc *sc = device_get_softc(dev); 505 506 mii = device_get_softc(sc->vr_miibus); 507 vr_setcfg(sc, mii->mii_media_active); 508} 509 510/* 511 * Program the 64-bit multicast hash filter. 512 */ 513static void 514vr_setmulti(struct vr_softc *sc) 515{ 516 struct ifnet *ifp = sc->vr_ifp; 517 int h = 0; 518 uint32_t hashes[2] = { 0, 0 }; 519 struct ifmultiaddr *ifma; 520 uint8_t rxfilt; 521 int mcnt = 0; 522 523 VR_LOCK_ASSERT(sc); 524 525 rxfilt = CSR_READ_1(sc, VR_RXCFG); 526 527 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 528 rxfilt |= VR_RXCFG_RX_MULTI; 529 CSR_WRITE_1(sc, VR_RXCFG, rxfilt); 530 CSR_WRITE_4(sc, VR_MAR0, 0xFFFFFFFF); 531 CSR_WRITE_4(sc, VR_MAR1, 0xFFFFFFFF); 532 return; 533 } 534 535 /* First, zero out all the existing hash bits. */ 536 CSR_WRITE_4(sc, VR_MAR0, 0); 537 CSR_WRITE_4(sc, VR_MAR1, 0); 538 539 /* Now program new ones. */ 540 IF_ADDR_LOCK(ifp); 541 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 542 if (ifma->ifma_addr->sa_family != AF_LINK) 543 continue; 544 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 545 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 546 if (h < 32) 547 hashes[0] |= (1 << h); 548 else 549 hashes[1] |= (1 << (h - 32)); 550 mcnt++; 551 } 552 IF_ADDR_UNLOCK(ifp); 553 554 if (mcnt) 555 rxfilt |= VR_RXCFG_RX_MULTI; 556 else 557 rxfilt &= ~VR_RXCFG_RX_MULTI; 558 559 CSR_WRITE_4(sc, VR_MAR0, hashes[0]); 560 CSR_WRITE_4(sc, VR_MAR1, hashes[1]); 561 CSR_WRITE_1(sc, VR_RXCFG, rxfilt); 562} 563 564/* 565 * In order to fiddle with the 566 * 'full-duplex' and '100Mbps' bits in the netconfig register, we 567 * first have to put the transmit and/or receive logic in the idle state. 568 */ 569static void 570vr_setcfg(struct vr_softc *sc, int media) 571{ 572 int restart = 0; 573 574 VR_LOCK_ASSERT(sc); 575 576 if (CSR_READ_2(sc, VR_COMMAND) & (VR_CMD_TX_ON|VR_CMD_RX_ON)) { 577 restart = 1; 578 VR_CLRBIT16(sc, VR_COMMAND, (VR_CMD_TX_ON|VR_CMD_RX_ON)); 579 } 580 581 if ((media & IFM_GMASK) == IFM_FDX) 582 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX); 583 else 584 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX); 585 586 if (restart) 587 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_ON|VR_CMD_RX_ON); 588} 589 590static void 591vr_reset(struct vr_softc *sc) 592{ 593 register int i; 594 595 /*VR_LOCK_ASSERT(sc);*/ /* XXX: Called during attach w/o lock. */ 596 597 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RESET); 598 599 for (i = 0; i < VR_TIMEOUT; i++) { 600 DELAY(10); 601 if (!(CSR_READ_2(sc, VR_COMMAND) & VR_CMD_RESET)) 602 break; 603 } 604 if (i == VR_TIMEOUT) { 605 if (sc->vr_revid < REV_ID_VT3065_A) 606 if_printf(sc->vr_ifp, "reset never completed!\n"); 607 else { 608 /* Use newer force reset command */ 609 if_printf(sc->vr_ifp, "Using force reset command.\n"); 610 VR_SETBIT(sc, VR_MISC_CR1, VR_MISCCR1_FORSRST); 611 } 612 } 613 614 /* Wait a little while for the chip to get its brains in order. */ 615 DELAY(1000); 616} 617 618/* 619 * Probe for a VIA Rhine chip. Check the PCI vendor and device 620 * IDs against our list and return a device name if we find a match. 621 */ 622static int 623vr_probe(device_t dev) 624{ 625 struct vr_type *t = vr_devs; 626 627 while (t->vr_name != NULL) { 628 if ((pci_get_vendor(dev) == t->vr_vid) && 629 (pci_get_device(dev) == t->vr_did)) { 630 device_set_desc(dev, t->vr_name); 631 return (BUS_PROBE_DEFAULT); 632 } 633 t++; 634 } 635 636 return (ENXIO); 637} 638 639/* 640 * Attach the interface. Allocate softc structures, do ifmedia 641 * setup and ethernet/BPF attach. 642 */ 643static int 644vr_attach(dev) 645 device_t dev; 646{ 647 int i; 648 u_char eaddr[ETHER_ADDR_LEN]; 649 struct vr_softc *sc; 650 struct ifnet *ifp; 651 int unit, error = 0, rid; 652 653 sc = device_get_softc(dev); 654 unit = device_get_unit(dev); 655 656 mtx_init(&sc->vr_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 657 MTX_DEF); 658 /* 659 * Map control/status registers. 660 */ 661 pci_enable_busmaster(dev); 662 sc->vr_revid = pci_read_config(dev, VR_PCI_REVID, 4) & 0x000000FF; 663 664 rid = VR_RID; 665 sc->vr_res = bus_alloc_resource_any(dev, VR_RES, &rid, RF_ACTIVE); 666 667 if (sc->vr_res == NULL) { 668 device_printf(dev, "couldn't map ports/memory\n"); 669 error = ENXIO; 670 goto fail; 671 } 672 673 sc->vr_btag = rman_get_bustag(sc->vr_res); 674 sc->vr_bhandle = rman_get_bushandle(sc->vr_res); 675 676 /* Allocate interrupt */ 677 rid = 0; 678 sc->vr_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 679 RF_SHAREABLE | RF_ACTIVE); 680 681 if (sc->vr_irq == NULL) { 682 device_printf(dev, "couldn't map interrupt\n"); 683 error = ENXIO; 684 goto fail; 685 } 686 687 /* Allocate ifnet structure. */ 688 ifp = sc->vr_ifp = if_alloc(IFT_ETHER); 689 if (ifp == NULL) { 690 device_printf(dev, "can not if_alloc()\n"); 691 error = ENOSPC; 692 goto fail; 693 } 694 ifp->if_softc = sc; 695 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 696 ifp->if_mtu = ETHERMTU; 697 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 698 ifp->if_ioctl = vr_ioctl; 699 ifp->if_start = vr_start; 700 ifp->if_watchdog = vr_watchdog; 701 ifp->if_init = vr_init; 702 ifp->if_baudrate = 10000000; 703 IFQ_SET_MAXLEN(&ifp->if_snd, VR_TX_LIST_CNT - 1); 704 ifp->if_snd.ifq_maxlen = VR_TX_LIST_CNT - 1; 705 IFQ_SET_READY(&ifp->if_snd); 706 ifp->if_capenable = ifp->if_capabilities; 707#ifdef DEVICE_POLLING 708 ifp->if_capabilities |= IFCAP_POLLING; 709#endif 710 711 /* 712 * Windows may put the chip in suspend mode when it 713 * shuts down. Be sure to kick it in the head to wake it 714 * up again. 715 */ 716 VR_CLRBIT(sc, VR_STICKHW, (VR_STICKHW_DS0|VR_STICKHW_DS1)); 717 718 /* Reset the adapter. */ 719 vr_reset(sc); 720 721 /* 722 * Turn on bit2 (MIION) in PCI configuration register 0x53 during 723 * initialization and disable AUTOPOLL. 724 */ 725 pci_write_config(dev, VR_PCI_MODE, 726 pci_read_config(dev, VR_PCI_MODE, 4) | (VR_MODE3_MIION << 24), 4); 727 VR_CLRBIT(sc, VR_MIICMD, VR_MIICMD_AUTOPOLL); 728 729 /* 730 * Get station address. The way the Rhine chips work, 731 * you're not allowed to directly access the EEPROM once 732 * they've been programmed a special way. Consequently, 733 * we need to read the node address from the PAR0 and PAR1 734 * registers. 735 */ 736 VR_SETBIT(sc, VR_EECSR, VR_EECSR_LOAD); 737 DELAY(200); 738 for (i = 0; i < ETHER_ADDR_LEN; i++) 739 eaddr[i] = CSR_READ_1(sc, VR_PAR0 + i); 740 741 sc->vr_ldata = contigmalloc(sizeof(struct vr_list_data), M_DEVBUF, 742 M_NOWAIT | M_ZERO, 0, 0xffffffff, PAGE_SIZE, 0); 743 744 if (sc->vr_ldata == NULL) { 745 device_printf(dev, "no memory for list buffers!\n"); 746 error = ENXIO; 747 goto fail; 748 } 749 750 /* Do MII setup. */ 751 if (mii_phy_probe(dev, &sc->vr_miibus, 752 vr_ifmedia_upd, vr_ifmedia_sts)) { 753 device_printf(dev, "MII without any phy!\n"); 754 error = ENXIO; 755 goto fail; 756 } 757 758 callout_handle_init(&sc->vr_stat_ch); 759 760 /* Call MI attach routine. */ 761 ether_ifattach(ifp, eaddr); 762 763 sc->suspended = 0; 764 765 /* Hook interrupt last to avoid having to lock softc */ 766 error = bus_setup_intr(dev, sc->vr_irq, INTR_TYPE_NET | INTR_MPSAFE, 767 vr_intr, sc, &sc->vr_intrhand); 768 769 if (error) { 770 device_printf(dev, "couldn't set up irq\n"); 771 ether_ifdetach(ifp); 772 goto fail; 773 } 774 775fail: 776 if (error) 777 vr_detach(dev); 778 779 return (error); 780} 781 782/* 783 * Shutdown hardware and free up resources. This can be called any 784 * time after the mutex has been initialized. It is called in both 785 * the error case in attach and the normal detach case so it needs 786 * to be careful about only freeing resources that have actually been 787 * allocated. 788 */ 789static int 790vr_detach(device_t dev) 791{ 792 struct vr_softc *sc = device_get_softc(dev); 793 struct ifnet *ifp = sc->vr_ifp; 794 795 KASSERT(mtx_initialized(&sc->vr_mtx), ("vr mutex not initialized")); 796 797#ifdef DEVICE_POLLING 798 if (ifp->if_capenable & IFCAP_POLLING) 799 ether_poll_deregister(ifp); 800#endif 801 802 VR_LOCK(sc); 803 804 sc->suspended = 1; 805 806 /* These should only be active if attach succeeded */ 807 if (device_is_attached(dev)) { 808 vr_stop(sc); 809 VR_UNLOCK(sc); /* XXX: Avoid recursive acquire. */ 810 ether_ifdetach(ifp); 811 VR_LOCK(sc); 812 } 813 if (sc->vr_miibus) 814 device_delete_child(dev, sc->vr_miibus); 815 bus_generic_detach(dev); 816 817 if (sc->vr_intrhand) 818 bus_teardown_intr(dev, sc->vr_irq, sc->vr_intrhand); 819 if (sc->vr_irq) 820 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq); 821 if (sc->vr_res) 822 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res); 823 824 if (ifp) 825 if_free(ifp); 826 827 if (sc->vr_ldata) 828 contigfree(sc->vr_ldata, sizeof(struct vr_list_data), M_DEVBUF); 829 830 VR_UNLOCK(sc); 831 mtx_destroy(&sc->vr_mtx); 832 833 return (0); 834} 835 836/* 837 * Initialize the transmit descriptors. 838 */ 839static int 840vr_list_tx_init(struct vr_softc *sc) 841{ 842 struct vr_chain_data *cd; 843 struct vr_list_data *ld; 844 int i; 845 846 cd = &sc->vr_cdata; 847 ld = sc->vr_ldata; 848 for (i = 0; i < VR_TX_LIST_CNT; i++) { 849 cd->vr_tx_chain[i].vr_ptr = &ld->vr_tx_list[i]; 850 if (i == (VR_TX_LIST_CNT - 1)) 851 cd->vr_tx_chain[i].vr_nextdesc = 852 &cd->vr_tx_chain[0]; 853 else 854 cd->vr_tx_chain[i].vr_nextdesc = 855 &cd->vr_tx_chain[i + 1]; 856 } 857 cd->vr_tx_cons = cd->vr_tx_prod = &cd->vr_tx_chain[0]; 858 859 return (0); 860} 861 862 863/* 864 * Initialize the RX descriptors and allocate mbufs for them. Note that 865 * we arrange the descriptors in a closed ring, so that the last descriptor 866 * points back to the first. 867 */ 868static int 869vr_list_rx_init(struct vr_softc *sc) 870{ 871 struct vr_chain_data *cd; 872 struct vr_list_data *ld; 873 int i; 874 875 VR_LOCK_ASSERT(sc); 876 877 cd = &sc->vr_cdata; 878 ld = sc->vr_ldata; 879 880 for (i = 0; i < VR_RX_LIST_CNT; i++) { 881 cd->vr_rx_chain[i].vr_ptr = 882 (struct vr_desc *)&ld->vr_rx_list[i]; 883 if (vr_newbuf(sc, &cd->vr_rx_chain[i], NULL) == ENOBUFS) 884 return (ENOBUFS); 885 if (i == (VR_RX_LIST_CNT - 1)) { 886 cd->vr_rx_chain[i].vr_nextdesc = 887 &cd->vr_rx_chain[0]; 888 ld->vr_rx_list[i].vr_next = 889 vtophys(&ld->vr_rx_list[0]); 890 } else { 891 cd->vr_rx_chain[i].vr_nextdesc = 892 &cd->vr_rx_chain[i + 1]; 893 ld->vr_rx_list[i].vr_next = 894 vtophys(&ld->vr_rx_list[i + 1]); 895 } 896 } 897 898 cd->vr_rx_head = &cd->vr_rx_chain[0]; 899 900 return (0); 901} 902 903/* 904 * Initialize an RX descriptor and attach an MBUF cluster. 905 * Note: the length fields are only 11 bits wide, which means the 906 * largest size we can specify is 2047. This is important because 907 * MCLBYTES is 2048, so we have to subtract one otherwise we'll 908 * overflow the field and make a mess. 909 */ 910static int 911vr_newbuf(struct vr_softc *sc, struct vr_chain_onefrag *c, struct mbuf *m) 912{ 913 struct mbuf *m_new = NULL; 914 915 if (m == NULL) { 916 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 917 if (m_new == NULL) 918 return (ENOBUFS); 919 920 MCLGET(m_new, M_DONTWAIT); 921 if (!(m_new->m_flags & M_EXT)) { 922 m_freem(m_new); 923 return (ENOBUFS); 924 } 925 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 926 } else { 927 m_new = m; 928 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 929 m_new->m_data = m_new->m_ext.ext_buf; 930 } 931 932 m_adj(m_new, sizeof(uint64_t)); 933 934 c->vr_mbuf = m_new; 935 c->vr_ptr->vr_status = VR_RXSTAT; 936 c->vr_ptr->vr_data = vtophys(mtod(m_new, caddr_t)); 937 c->vr_ptr->vr_ctl = VR_RXCTL | VR_RXLEN; 938 939 return (0); 940} 941 942/* 943 * A frame has been uploaded: pass the resulting mbuf chain up to 944 * the higher level protocols. 945 */ 946static void 947vr_rxeof(struct vr_softc *sc) 948{ 949 struct mbuf *m, *m0; 950 struct ifnet *ifp; 951 struct vr_chain_onefrag *cur_rx; 952 int total_len = 0; 953 uint32_t rxstat; 954 955 VR_LOCK_ASSERT(sc); 956 ifp = sc->vr_ifp; 957 958 while (!((rxstat = sc->vr_cdata.vr_rx_head->vr_ptr->vr_status) & 959 VR_RXSTAT_OWN)) { 960#ifdef DEVICE_POLLING 961 if (ifp->if_capenable & IFCAP_POLLING) { 962 if (sc->rxcycles <= 0) 963 break; 964 sc->rxcycles--; 965 } 966#endif 967 m0 = NULL; 968 cur_rx = sc->vr_cdata.vr_rx_head; 969 sc->vr_cdata.vr_rx_head = cur_rx->vr_nextdesc; 970 m = cur_rx->vr_mbuf; 971 972 /* 973 * If an error occurs, update stats, clear the 974 * status word and leave the mbuf cluster in place: 975 * it should simply get re-used next time this descriptor 976 * comes up in the ring. 977 */ 978 if (rxstat & VR_RXSTAT_RXERR) { 979 ifp->if_ierrors++; 980 if_printf(ifp, "rx error (%02x):", rxstat & 0x000000ff); 981 if (rxstat & VR_RXSTAT_CRCERR) 982 printf(" crc error"); 983 if (rxstat & VR_RXSTAT_FRAMEALIGNERR) 984 printf(" frame alignment error\n"); 985 if (rxstat & VR_RXSTAT_FIFOOFLOW) 986 printf(" FIFO overflow"); 987 if (rxstat & VR_RXSTAT_GIANT) 988 printf(" received giant packet"); 989 if (rxstat & VR_RXSTAT_RUNT) 990 printf(" received runt packet"); 991 if (rxstat & VR_RXSTAT_BUSERR) 992 printf(" system bus error"); 993 if (rxstat & VR_RXSTAT_BUFFERR) 994 printf("rx buffer error"); 995 printf("\n"); 996 vr_newbuf(sc, cur_rx, m); 997 continue; 998 } 999 1000 /* No errors; receive the packet. */ 1001 total_len = VR_RXBYTES(cur_rx->vr_ptr->vr_status); 1002 1003 /* 1004 * XXX The VIA Rhine chip includes the CRC with every 1005 * received frame, and there's no way to turn this 1006 * behavior off (at least, I can't find anything in 1007 * the manual that explains how to do it) so we have 1008 * to trim off the CRC manually. 1009 */ 1010 total_len -= ETHER_CRC_LEN; 1011 1012 m0 = m_devget(mtod(m, char *), total_len, ETHER_ALIGN, ifp, 1013 NULL); 1014 vr_newbuf(sc, cur_rx, m); 1015 if (m0 == NULL) { 1016 ifp->if_ierrors++; 1017 continue; 1018 } 1019 m = m0; 1020 1021 ifp->if_ipackets++; 1022 VR_UNLOCK(sc); 1023 (*ifp->if_input)(ifp, m); 1024 VR_LOCK(sc); 1025 } 1026} 1027 1028static void 1029vr_rxeoc(struct vr_softc *sc) 1030{ 1031 struct ifnet *ifp = sc->vr_ifp; 1032 int i; 1033 1034 VR_LOCK_ASSERT(sc); 1035 1036 ifp->if_ierrors++; 1037 1038 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_RX_ON); 1039 DELAY(10000); 1040 1041 /* Wait for receiver to stop */ 1042 for (i = 0x400; 1043 i && (CSR_READ_2(sc, VR_COMMAND) & VR_CMD_RX_ON); 1044 i--) { 1045 ; 1046 } 1047 1048 if (!i) { 1049 if_printf(ifp, "rx shutdown error!\n"); 1050 sc->vr_flags |= VR_F_RESTART; 1051 return; 1052 } 1053 1054 vr_rxeof(sc); 1055 1056 CSR_WRITE_4(sc, VR_RXADDR, vtophys(sc->vr_cdata.vr_rx_head->vr_ptr)); 1057 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RX_ON); 1058 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RX_GO); 1059} 1060 1061/* 1062 * A frame was downloaded to the chip. It's safe for us to clean up 1063 * the list buffers. 1064 */ 1065static void 1066vr_txeof(struct vr_softc *sc) 1067{ 1068 struct vr_chain *cur_tx; 1069 struct ifnet *ifp = sc->vr_ifp; 1070 1071 VR_LOCK_ASSERT(sc); 1072 1073 /* 1074 * Go through our tx list and free mbufs for those 1075 * frames that have been transmitted. 1076 */ 1077 cur_tx = sc->vr_cdata.vr_tx_cons; 1078 while (cur_tx->vr_mbuf != NULL) { 1079 uint32_t txstat; 1080 int i; 1081 1082 txstat = cur_tx->vr_ptr->vr_status; 1083 1084 if ((txstat & VR_TXSTAT_ABRT) || 1085 (txstat & VR_TXSTAT_UDF)) { 1086 for (i = 0x400; 1087 i && (CSR_READ_2(sc, VR_COMMAND) & VR_CMD_TX_ON); 1088 i--) 1089 ; /* Wait for chip to shutdown */ 1090 if (!i) { 1091 if_printf(ifp, "tx shutdown timeout\n"); 1092 sc->vr_flags |= VR_F_RESTART; 1093 break; 1094 } 1095 VR_TXOWN(cur_tx) = VR_TXSTAT_OWN; 1096 CSR_WRITE_4(sc, VR_TXADDR, vtophys(cur_tx->vr_ptr)); 1097 break; 1098 } 1099 1100 if (txstat & VR_TXSTAT_OWN) 1101 break; 1102 1103 if (txstat & VR_TXSTAT_ERRSUM) { 1104 ifp->if_oerrors++; 1105 if (txstat & VR_TXSTAT_DEFER) 1106 ifp->if_collisions++; 1107 if (txstat & VR_TXSTAT_LATECOLL) 1108 ifp->if_collisions++; 1109 } 1110 1111 ifp->if_collisions +=(txstat & VR_TXSTAT_COLLCNT) >> 3; 1112 1113 ifp->if_opackets++; 1114 m_freem(cur_tx->vr_mbuf); 1115 cur_tx->vr_mbuf = NULL; 1116 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1117 1118 cur_tx = cur_tx->vr_nextdesc; 1119 } 1120 sc->vr_cdata.vr_tx_cons = cur_tx; 1121 if (cur_tx->vr_mbuf == NULL) 1122 ifp->if_timer = 0; 1123} 1124 1125static void 1126vr_tick(void *xsc) 1127{ 1128 struct vr_softc *sc = xsc; 1129 struct mii_data *mii; 1130 1131 VR_LOCK(sc); 1132 1133 if (sc->vr_flags & VR_F_RESTART) { 1134 if_printf(sc->vr_ifp, "restarting\n"); 1135 vr_stop(sc); 1136 vr_reset(sc); 1137 vr_init_locked(sc); 1138 sc->vr_flags &= ~VR_F_RESTART; 1139 } 1140 1141 mii = device_get_softc(sc->vr_miibus); 1142 mii_tick(mii); 1143 sc->vr_stat_ch = timeout(vr_tick, sc, hz); 1144 1145 VR_UNLOCK(sc); 1146} 1147 1148#ifdef DEVICE_POLLING 1149static poll_handler_t vr_poll; 1150static poll_handler_t vr_poll_locked; 1151 1152static void 1153vr_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1154{ 1155 struct vr_softc *sc = ifp->if_softc; 1156 1157 VR_LOCK(sc); 1158 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1159 vr_poll_locked(ifp, cmd, count); 1160 VR_UNLOCK(sc); 1161} 1162 1163static void 1164vr_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) 1165{ 1166 struct vr_softc *sc = ifp->if_softc; 1167 1168 VR_LOCK_ASSERT(sc); 1169 1170 sc->rxcycles = count; 1171 vr_rxeof(sc); 1172 vr_txeof(sc); 1173 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1174 vr_start_locked(ifp); 1175 1176 if (cmd == POLL_AND_CHECK_STATUS) { 1177 uint16_t status; 1178 1179 /* Also check status register. */ 1180 status = CSR_READ_2(sc, VR_ISR); 1181 if (status) 1182 CSR_WRITE_2(sc, VR_ISR, status); 1183 1184 if ((status & VR_INTRS) == 0) 1185 return; 1186 1187 if (status & VR_ISR_RX_DROPPED) { 1188 if_printf(ifp, "rx packet lost\n"); 1189 ifp->if_ierrors++; 1190 } 1191 1192 if ((status & VR_ISR_RX_ERR) || (status & VR_ISR_RX_NOBUF) || 1193 (status & VR_ISR_RX_NOBUF) || (status & VR_ISR_RX_OFLOW)) { 1194 if_printf(ifp, "receive error (%04x)", status); 1195 if (status & VR_ISR_RX_NOBUF) 1196 printf(" no buffers"); 1197 if (status & VR_ISR_RX_OFLOW) 1198 printf(" overflow"); 1199 if (status & VR_ISR_RX_DROPPED) 1200 printf(" packet lost"); 1201 printf("\n"); 1202 vr_rxeoc(sc); 1203 } 1204 1205 if ((status & VR_ISR_BUSERR) || 1206 (status & VR_ISR_TX_UNDERRUN)) { 1207 vr_reset(sc); 1208 vr_init_locked(sc); 1209 return; 1210 } 1211 1212 if ((status & VR_ISR_UDFI) || 1213 (status & VR_ISR_TX_ABRT2) || 1214 (status & VR_ISR_TX_ABRT)) { 1215 ifp->if_oerrors++; 1216 if (sc->vr_cdata.vr_tx_cons->vr_mbuf != NULL) { 1217 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_ON); 1218 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_GO); 1219 } 1220 } 1221 } 1222} 1223#endif /* DEVICE_POLLING */ 1224 1225static void 1226vr_intr(void *arg) 1227{ 1228 struct vr_softc *sc = arg; 1229 struct ifnet *ifp = sc->vr_ifp; 1230 uint16_t status; 1231 1232 VR_LOCK(sc); 1233 1234 if (sc->suspended) { 1235 /* 1236 * Forcibly disable interrupts. 1237 * XXX: Mobile VIA based platforms may need 1238 * interrupt re-enable on resume. 1239 */ 1240 CSR_WRITE_2(sc, VR_IMR, 0x0000); 1241 goto done_locked; 1242 } 1243 1244#ifdef DEVICE_POLLING 1245 if (ifp->if_capenable & IFCAP_POLLING) 1246 goto done_locked; 1247#endif 1248 1249 /* Suppress unwanted interrupts. */ 1250 if (!(ifp->if_flags & IFF_UP)) { 1251 vr_stop(sc); 1252 goto done_locked; 1253 } 1254 1255 /* Disable interrupts. */ 1256 CSR_WRITE_2(sc, VR_IMR, 0x0000); 1257 1258 for (;;) { 1259 status = CSR_READ_2(sc, VR_ISR); 1260 if (status) 1261 CSR_WRITE_2(sc, VR_ISR, status); 1262 1263 if ((status & VR_INTRS) == 0) 1264 break; 1265 1266 if (status & VR_ISR_RX_OK) 1267 vr_rxeof(sc); 1268 1269 if (status & VR_ISR_RX_DROPPED) { 1270 if_printf(ifp, "rx packet lost\n"); 1271 ifp->if_ierrors++; 1272 } 1273 1274 if ((status & VR_ISR_RX_ERR) || (status & VR_ISR_RX_NOBUF) || 1275 (status & VR_ISR_RX_NOBUF) || (status & VR_ISR_RX_OFLOW)) { 1276 if_printf(ifp, "receive error (%04x)", status); 1277 if (status & VR_ISR_RX_NOBUF) 1278 printf(" no buffers"); 1279 if (status & VR_ISR_RX_OFLOW) 1280 printf(" overflow"); 1281 if (status & VR_ISR_RX_DROPPED) 1282 printf(" packet lost"); 1283 printf("\n"); 1284 vr_rxeoc(sc); 1285 } 1286 1287 if ((status & VR_ISR_BUSERR) || (status & VR_ISR_TX_UNDERRUN)) { 1288 vr_reset(sc); 1289 vr_init_locked(sc); 1290 break; 1291 } 1292 1293 if ((status & VR_ISR_TX_OK) || (status & VR_ISR_TX_ABRT) || 1294 (status & VR_ISR_TX_ABRT2) || (status & VR_ISR_UDFI)) { 1295 vr_txeof(sc); 1296 if ((status & VR_ISR_UDFI) || 1297 (status & VR_ISR_TX_ABRT2) || 1298 (status & VR_ISR_TX_ABRT)) { 1299 ifp->if_oerrors++; 1300 if (sc->vr_cdata.vr_tx_cons->vr_mbuf != NULL) { 1301 VR_SETBIT16(sc, VR_COMMAND, 1302 VR_CMD_TX_ON); 1303 VR_SETBIT16(sc, VR_COMMAND, 1304 VR_CMD_TX_GO); 1305 } 1306 } 1307 } 1308 } 1309 1310 /* Re-enable interrupts. */ 1311 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 1312 1313 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1314 vr_start_locked(ifp); 1315 1316done_locked: 1317 VR_UNLOCK(sc); 1318} 1319 1320/* 1321 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1322 * pointers to the fragment pointers. 1323 */ 1324static int 1325vr_encap(struct vr_softc *sc, struct vr_chain *c, struct mbuf *m_head) 1326{ 1327 struct vr_desc *f = NULL; 1328 struct mbuf *m; 1329 1330 VR_LOCK_ASSERT(sc); 1331 /* 1332 * The VIA Rhine wants packet buffers to be longword 1333 * aligned, but very often our mbufs aren't. Rather than 1334 * waste time trying to decide when to copy and when not 1335 * to copy, just do it all the time. 1336 */ 1337 m = m_defrag(m_head, M_DONTWAIT); 1338 if (m == NULL) 1339 return (1); 1340 1341 /* 1342 * The Rhine chip doesn't auto-pad, so we have to make 1343 * sure to pad short frames out to the minimum frame length 1344 * ourselves. 1345 */ 1346 if (m->m_len < VR_MIN_FRAMELEN) { 1347 m->m_pkthdr.len += VR_MIN_FRAMELEN - m->m_len; 1348 m->m_len = m->m_pkthdr.len; 1349 } 1350 1351 c->vr_mbuf = m; 1352 f = c->vr_ptr; 1353 f->vr_data = vtophys(mtod(m, caddr_t)); 1354 f->vr_ctl = m->m_len; 1355 f->vr_ctl |= VR_TXCTL_TLINK|VR_TXCTL_FIRSTFRAG; 1356 f->vr_status = 0; 1357 f->vr_ctl |= VR_TXCTL_LASTFRAG|VR_TXCTL_FINT; 1358 f->vr_next = vtophys(c->vr_nextdesc->vr_ptr); 1359 1360 return (0); 1361} 1362 1363/* 1364 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1365 * to the mbuf data regions directly in the transmit lists. We also save a 1366 * copy of the pointers since the transmit list fragment pointers are 1367 * physical addresses. 1368 */ 1369 1370static void 1371vr_start(struct ifnet *ifp) 1372{ 1373 struct vr_softc *sc = ifp->if_softc; 1374 1375 VR_LOCK(sc); 1376 vr_start_locked(ifp); 1377 VR_UNLOCK(sc); 1378} 1379 1380static void 1381vr_start_locked(struct ifnet *ifp) 1382{ 1383 struct vr_softc *sc = ifp->if_softc; 1384 struct mbuf *m_head; 1385 struct vr_chain *cur_tx; 1386 1387 if (ifp->if_drv_flags & IFF_DRV_OACTIVE) 1388 return; 1389 1390 cur_tx = sc->vr_cdata.vr_tx_prod; 1391 while (cur_tx->vr_mbuf == NULL) { 1392 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1393 if (m_head == NULL) 1394 break; 1395 1396 /* Pack the data into the descriptor. */ 1397 if (vr_encap(sc, cur_tx, m_head)) { 1398 /* Rollback, send what we were able to encap. */ 1399 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1400 break; 1401 } 1402 1403 VR_TXOWN(cur_tx) = VR_TXSTAT_OWN; 1404 1405 /* 1406 * If there's a BPF listener, bounce a copy of this frame 1407 * to him. 1408 */ 1409 BPF_MTAP(ifp, cur_tx->vr_mbuf); 1410 1411 cur_tx = cur_tx->vr_nextdesc; 1412 } 1413 if (cur_tx != sc->vr_cdata.vr_tx_prod || cur_tx->vr_mbuf != NULL) { 1414 sc->vr_cdata.vr_tx_prod = cur_tx; 1415 1416 /* Tell the chip to start transmitting. */ 1417 VR_SETBIT16(sc, VR_COMMAND, /*VR_CMD_TX_ON|*/ VR_CMD_TX_GO); 1418 1419 /* Set a timeout in case the chip goes out to lunch. */ 1420 ifp->if_timer = 5; 1421 1422 if (cur_tx->vr_mbuf != NULL) 1423 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1424 } 1425} 1426 1427static void 1428vr_init(void *xsc) 1429{ 1430 struct vr_softc *sc = xsc; 1431 1432 VR_LOCK(sc); 1433 vr_init_locked(sc); 1434 VR_UNLOCK(sc); 1435} 1436 1437static void 1438vr_init_locked(struct vr_softc *sc) 1439{ 1440 struct ifnet *ifp = sc->vr_ifp; 1441 struct mii_data *mii; 1442 int i; 1443 1444 VR_LOCK_ASSERT(sc); 1445 1446 mii = device_get_softc(sc->vr_miibus); 1447 1448 /* Cancel pending I/O and free all RX/TX buffers. */ 1449 vr_stop(sc); 1450 vr_reset(sc); 1451 1452 /* Set our station address. */ 1453 for (i = 0; i < ETHER_ADDR_LEN; i++) 1454 CSR_WRITE_1(sc, VR_PAR0 + i, IFP2ENADDR(sc->vr_ifp)[i]); 1455 1456 /* Set DMA size. */ 1457 VR_CLRBIT(sc, VR_BCR0, VR_BCR0_DMA_LENGTH); 1458 VR_SETBIT(sc, VR_BCR0, VR_BCR0_DMA_STORENFWD); 1459 1460 /* 1461 * BCR0 and BCR1 can override the RXCFG and TXCFG registers, 1462 * so we must set both. 1463 */ 1464 VR_CLRBIT(sc, VR_BCR0, VR_BCR0_RX_THRESH); 1465 VR_SETBIT(sc, VR_BCR0, VR_BCR0_RXTHRESH128BYTES); 1466 1467 VR_CLRBIT(sc, VR_BCR1, VR_BCR1_TX_THRESH); 1468 VR_SETBIT(sc, VR_BCR1, VR_BCR1_TXTHRESHSTORENFWD); 1469 1470 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_THRESH); 1471 VR_SETBIT(sc, VR_RXCFG, VR_RXTHRESH_128BYTES); 1472 1473 VR_CLRBIT(sc, VR_TXCFG, VR_TXCFG_TX_THRESH); 1474 VR_SETBIT(sc, VR_TXCFG, VR_TXTHRESH_STORENFWD); 1475 1476 /* Init circular RX list. */ 1477 if (vr_list_rx_init(sc) == ENOBUFS) { 1478 if_printf(ifp, 1479 "initialization failed: no memory for rx buffers\n"); 1480 vr_stop(sc); 1481 return; 1482 } 1483 1484 /* Init tx descriptors. */ 1485 vr_list_tx_init(sc); 1486 1487 /* If we want promiscuous mode, set the allframes bit. */ 1488 if (ifp->if_flags & IFF_PROMISC) 1489 VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC); 1490 else 1491 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC); 1492 1493 /* Set capture broadcast bit to capture broadcast frames. */ 1494 if (ifp->if_flags & IFF_BROADCAST) 1495 VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD); 1496 else 1497 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD); 1498 1499 /* 1500 * Program the multicast filter, if necessary. 1501 */ 1502 vr_setmulti(sc); 1503 1504 /* 1505 * Load the address of the RX list. 1506 */ 1507 CSR_WRITE_4(sc, VR_RXADDR, vtophys(sc->vr_cdata.vr_rx_head->vr_ptr)); 1508 1509 /* Enable receiver and transmitter. */ 1510 CSR_WRITE_2(sc, VR_COMMAND, VR_CMD_TX_NOPOLL|VR_CMD_START| 1511 VR_CMD_TX_ON|VR_CMD_RX_ON| 1512 VR_CMD_RX_GO); 1513 1514 CSR_WRITE_4(sc, VR_TXADDR, vtophys(&sc->vr_ldata->vr_tx_list[0])); 1515 1516 CSR_WRITE_2(sc, VR_ISR, 0xFFFF); 1517#ifdef DEVICE_POLLING 1518 /* 1519 * Disable interrupts if we are polling. 1520 */ 1521 if (ifp->if_capenable & IFCAP_POLLING) 1522 CSR_WRITE_2(sc, VR_IMR, 0); 1523 else 1524#endif 1525 /* 1526 * Enable interrupts. 1527 */ 1528 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 1529 1530 mii_mediachg(mii); 1531 1532 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1533 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1534 1535 sc->vr_stat_ch = timeout(vr_tick, sc, hz); 1536} 1537 1538/* 1539 * Set media options. 1540 */ 1541static int 1542vr_ifmedia_upd(struct ifnet *ifp) 1543{ 1544 struct vr_softc *sc = ifp->if_softc; 1545 1546 if (ifp->if_flags & IFF_UP) 1547 vr_init(sc); 1548 1549 return (0); 1550} 1551 1552/* 1553 * Report current media status. 1554 */ 1555static void 1556vr_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1557{ 1558 struct vr_softc *sc = ifp->if_softc; 1559 struct mii_data *mii; 1560 1561 mii = device_get_softc(sc->vr_miibus); 1562 VR_LOCK(sc); 1563 mii_pollstat(mii); 1564 VR_UNLOCK(sc); 1565 ifmr->ifm_active = mii->mii_media_active; 1566 ifmr->ifm_status = mii->mii_media_status; 1567} 1568 1569static int 1570vr_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1571{ 1572 struct vr_softc *sc = ifp->if_softc; 1573 struct ifreq *ifr = (struct ifreq *) data; 1574 struct mii_data *mii; 1575 int error = 0; 1576 1577 switch (command) { 1578 case SIOCSIFFLAGS: 1579 VR_LOCK(sc); 1580 if (ifp->if_flags & IFF_UP) { 1581 vr_init_locked(sc); 1582 } else { 1583 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1584 vr_stop(sc); 1585 } 1586 VR_UNLOCK(sc); 1587 error = 0; 1588 break; 1589 case SIOCADDMULTI: 1590 case SIOCDELMULTI: 1591 VR_LOCK(sc); 1592 vr_setmulti(sc); 1593 VR_UNLOCK(sc); 1594 error = 0; 1595 break; 1596 case SIOCGIFMEDIA: 1597 case SIOCSIFMEDIA: 1598 mii = device_get_softc(sc->vr_miibus); 1599 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1600 break; 1601 case SIOCSIFCAP: 1602#ifdef DEVICE_POLLING 1603 if (ifr->ifr_reqcap & IFCAP_POLLING && 1604 !(ifp->if_capenable & IFCAP_POLLING)) { 1605 error = ether_poll_register(vr_poll, ifp); 1606 if (error) 1607 return(error); 1608 VR_LOCK(sc); 1609 /* Disable interrupts */ 1610 CSR_WRITE_2(sc, VR_IMR, 0x0000); 1611 ifp->if_capenable |= IFCAP_POLLING; 1612 VR_UNLOCK(sc); 1613 return (error); 1614 1615 } 1616 if (!(ifr->ifr_reqcap & IFCAP_POLLING) && 1617 ifp->if_capenable & IFCAP_POLLING) { 1618 error = ether_poll_deregister(ifp); 1619 /* Enable interrupts. */ 1620 VR_LOCK(sc); 1621 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 1622 ifp->if_capenable &= ~IFCAP_POLLING; 1623 VR_UNLOCK(sc); 1624 return (error); 1625 } 1626#endif /* DEVICE_POLLING */ 1627 break; 1628 default: 1629 error = ether_ioctl(ifp, command, data); 1630 break; 1631 } 1632 1633 return (error); 1634} 1635 1636static void 1637vr_watchdog(struct ifnet *ifp) 1638{ 1639 struct vr_softc *sc = ifp->if_softc; 1640 1641 VR_LOCK(sc); 1642 1643 ifp->if_oerrors++; 1644 if_printf(ifp, "watchdog timeout\n"); 1645 1646 vr_stop(sc); 1647 vr_reset(sc); 1648 vr_init_locked(sc); 1649 1650 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1651 vr_start_locked(ifp); 1652 1653 VR_UNLOCK(sc); 1654} 1655 1656/* 1657 * Stop the adapter and free any mbufs allocated to the 1658 * RX and TX lists. 1659 */ 1660static void 1661vr_stop(struct vr_softc *sc) 1662{ 1663 register int i; 1664 struct ifnet *ifp; 1665 1666 VR_LOCK_ASSERT(sc); 1667 1668 ifp = sc->vr_ifp; 1669 ifp->if_timer = 0; 1670 1671 untimeout(vr_tick, sc, sc->vr_stat_ch); 1672 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1673 1674 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_STOP); 1675 VR_CLRBIT16(sc, VR_COMMAND, (VR_CMD_RX_ON|VR_CMD_TX_ON)); 1676 CSR_WRITE_2(sc, VR_IMR, 0x0000); 1677 CSR_WRITE_4(sc, VR_TXADDR, 0x00000000); 1678 CSR_WRITE_4(sc, VR_RXADDR, 0x00000000); 1679 1680 /* 1681 * Free data in the RX lists. 1682 */ 1683 for (i = 0; i < VR_RX_LIST_CNT; i++) { 1684 if (sc->vr_cdata.vr_rx_chain[i].vr_mbuf != NULL) { 1685 m_freem(sc->vr_cdata.vr_rx_chain[i].vr_mbuf); 1686 sc->vr_cdata.vr_rx_chain[i].vr_mbuf = NULL; 1687 } 1688 } 1689 bzero((char *)&sc->vr_ldata->vr_rx_list, 1690 sizeof(sc->vr_ldata->vr_rx_list)); 1691 1692 /* 1693 * Free the TX list buffers. 1694 */ 1695 for (i = 0; i < VR_TX_LIST_CNT; i++) { 1696 if (sc->vr_cdata.vr_tx_chain[i].vr_mbuf != NULL) { 1697 m_freem(sc->vr_cdata.vr_tx_chain[i].vr_mbuf); 1698 sc->vr_cdata.vr_tx_chain[i].vr_mbuf = NULL; 1699 } 1700 } 1701 bzero((char *)&sc->vr_ldata->vr_tx_list, 1702 sizeof(sc->vr_ldata->vr_tx_list)); 1703} 1704 1705/* 1706 * Stop all chip I/O so that the kernel's probe routines don't 1707 * get confused by errant DMAs when rebooting. 1708 */ 1709static void 1710vr_shutdown(device_t dev) 1711{ 1712 1713 vr_detach(dev); 1714} 1715