if_vr.c revision 111119
1/* 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: head/sys/dev/vr/if_vr.c 111119 2003-02-19 05:47:46Z imp $ 33 */ 34 35/* 36 * VIA Rhine fast ethernet PCI NIC driver 37 * 38 * Supports various network adapters based on the VIA Rhine 39 * and Rhine II PCI controllers, including the D-Link DFE530TX. 40 * Datasheets are available at http://www.via.com.tw. 41 * 42 * Written by Bill Paul <wpaul@ctr.columbia.edu> 43 * Electrical Engineering Department 44 * Columbia University, New York City 45 */ 46 47/* 48 * The VIA Rhine controllers are similar in some respects to the 49 * the DEC tulip chips, except less complicated. The controller 50 * uses an MII bus and an external physical layer interface. The 51 * receiver has a one entry perfect filter and a 64-bit hash table 52 * multicast filter. Transmit and receive descriptors are similar 53 * to the tulip. 54 * 55 * The Rhine has a serious flaw in its transmit DMA mechanism: 56 * transmit buffers must be longword aligned. Unfortunately, 57 * FreeBSD doesn't guarantee that mbufs will be filled in starting 58 * at longword boundaries, so we have to do a buffer copy before 59 * transmission. 60 */ 61 62#include <sys/param.h> 63#include <sys/systm.h> 64#include <sys/sockio.h> 65#include <sys/mbuf.h> 66#include <sys/malloc.h> 67#include <sys/kernel.h> 68#include <sys/socket.h> 69 70#include <net/if.h> 71#include <net/if_arp.h> 72#include <net/ethernet.h> 73#include <net/if_dl.h> 74#include <net/if_media.h> 75 76#include <net/bpf.h> 77 78#include <vm/vm.h> /* for vtophys */ 79#include <vm/pmap.h> /* for vtophys */ 80#include <machine/bus_pio.h> 81#include <machine/bus_memio.h> 82#include <machine/bus.h> 83#include <machine/resource.h> 84#include <sys/bus.h> 85#include <sys/rman.h> 86 87#include <dev/mii/mii.h> 88#include <dev/mii/miivar.h> 89 90#include <pci/pcireg.h> 91#include <pci/pcivar.h> 92 93#define VR_USEIOSPACE 94 95#include <pci/if_vrreg.h> 96 97MODULE_DEPEND(vr, miibus, 1, 1, 1); 98 99/* "controller miibus0" required. See GENERIC if you get errors here. */ 100#include "miibus_if.h" 101 102#ifndef lint 103static const char rcsid[] = 104 "$FreeBSD: head/sys/dev/vr/if_vr.c 111119 2003-02-19 05:47:46Z imp $"; 105#endif 106 107#undef VR_USESWSHIFT 108 109/* 110 * Various supported device vendors/types and their names. 111 */ 112static struct vr_type vr_devs[] = { 113 { VIA_VENDORID, VIA_DEVICEID_RHINE, 114 "VIA VT3043 Rhine I 10/100BaseTX" }, 115 { VIA_VENDORID, VIA_DEVICEID_RHINE_II, 116 "VIA VT86C100A Rhine II 10/100BaseTX" }, 117 { VIA_VENDORID, VIA_DEVICEID_RHINE_II_2, 118 "VIA VT6102 Rhine II 10/100BaseTX" }, 119 { VIA_VENDORID, VIA_DEVICEID_RHINE_III, 120 "VIA VT6105 Rhine III 10/100BaseTX" }, 121 { VIA_VENDORID, VIA_DEVICEID_RHINE_III_M, 122 "VIA VT6105M Rhine III 10/100BaseTX" }, 123 { DELTA_VENDORID, DELTA_DEVICEID_RHINE_II, 124 "Delta Electronics Rhine II 10/100BaseTX" }, 125 { ADDTRON_VENDORID, ADDTRON_DEVICEID_RHINE_II, 126 "Addtron Technology Rhine II 10/100BaseTX" }, 127 { 0, 0, NULL } 128}; 129 130static int vr_probe (device_t); 131static int vr_attach (device_t); 132static int vr_detach (device_t); 133 134static int vr_newbuf (struct vr_softc *, 135 struct vr_chain_onefrag *, 136 struct mbuf *); 137static int vr_encap (struct vr_softc *, struct vr_chain *, 138 struct mbuf * ); 139 140static void vr_rxeof (struct vr_softc *); 141static void vr_rxeoc (struct vr_softc *); 142static void vr_txeof (struct vr_softc *); 143static void vr_txeoc (struct vr_softc *); 144static void vr_tick (void *); 145static void vr_intr (void *); 146static void vr_start (struct ifnet *); 147static int vr_ioctl (struct ifnet *, u_long, caddr_t); 148static void vr_init (void *); 149static void vr_stop (struct vr_softc *); 150static void vr_watchdog (struct ifnet *); 151static void vr_shutdown (device_t); 152static int vr_ifmedia_upd (struct ifnet *); 153static void vr_ifmedia_sts (struct ifnet *, struct ifmediareq *); 154 155#ifdef VR_USESWSHIFT 156static void vr_mii_sync (struct vr_softc *); 157static void vr_mii_send (struct vr_softc *, u_int32_t, int); 158#endif 159static int vr_mii_readreg (struct vr_softc *, struct vr_mii_frame *); 160static int vr_mii_writereg (struct vr_softc *, struct vr_mii_frame *); 161static int vr_miibus_readreg (device_t, int, int); 162static int vr_miibus_writereg (device_t, int, int, int); 163static void vr_miibus_statchg (device_t); 164 165static void vr_setcfg (struct vr_softc *, int); 166static u_int8_t vr_calchash (u_int8_t *); 167static void vr_setmulti (struct vr_softc *); 168static void vr_reset (struct vr_softc *); 169static int vr_list_rx_init (struct vr_softc *); 170static int vr_list_tx_init (struct vr_softc *); 171 172#ifdef VR_USEIOSPACE 173#define VR_RES SYS_RES_IOPORT 174#define VR_RID VR_PCI_LOIO 175#else 176#define VR_RES SYS_RES_MEMORY 177#define VR_RID VR_PCI_LOMEM 178#endif 179 180static device_method_t vr_methods[] = { 181 /* Device interface */ 182 DEVMETHOD(device_probe, vr_probe), 183 DEVMETHOD(device_attach, vr_attach), 184 DEVMETHOD(device_detach, vr_detach), 185 DEVMETHOD(device_shutdown, vr_shutdown), 186 187 /* bus interface */ 188 DEVMETHOD(bus_print_child, bus_generic_print_child), 189 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 190 191 /* MII interface */ 192 DEVMETHOD(miibus_readreg, vr_miibus_readreg), 193 DEVMETHOD(miibus_writereg, vr_miibus_writereg), 194 DEVMETHOD(miibus_statchg, vr_miibus_statchg), 195 196 { 0, 0 } 197}; 198 199static driver_t vr_driver = { 200 "vr", 201 vr_methods, 202 sizeof(struct vr_softc) 203}; 204 205static devclass_t vr_devclass; 206 207DRIVER_MODULE(if_vr, pci, vr_driver, vr_devclass, 0, 0); 208DRIVER_MODULE(miibus, vr, miibus_driver, miibus_devclass, 0, 0); 209 210#define VR_SETBIT(sc, reg, x) \ 211 CSR_WRITE_1(sc, reg, \ 212 CSR_READ_1(sc, reg) | (x)) 213 214#define VR_CLRBIT(sc, reg, x) \ 215 CSR_WRITE_1(sc, reg, \ 216 CSR_READ_1(sc, reg) & ~(x)) 217 218#define VR_SETBIT16(sc, reg, x) \ 219 CSR_WRITE_2(sc, reg, \ 220 CSR_READ_2(sc, reg) | (x)) 221 222#define VR_CLRBIT16(sc, reg, x) \ 223 CSR_WRITE_2(sc, reg, \ 224 CSR_READ_2(sc, reg) & ~(x)) 225 226#define VR_SETBIT32(sc, reg, x) \ 227 CSR_WRITE_4(sc, reg, \ 228 CSR_READ_4(sc, reg) | (x)) 229 230#define VR_CLRBIT32(sc, reg, x) \ 231 CSR_WRITE_4(sc, reg, \ 232 CSR_READ_4(sc, reg) & ~(x)) 233 234#define SIO_SET(x) \ 235 CSR_WRITE_1(sc, VR_MIICMD, \ 236 CSR_READ_1(sc, VR_MIICMD) | (x)) 237 238#define SIO_CLR(x) \ 239 CSR_WRITE_1(sc, VR_MIICMD, \ 240 CSR_READ_1(sc, VR_MIICMD) & ~(x)) 241 242#ifdef VR_USESWSHIFT 243/* 244 * Sync the PHYs by setting data bit and strobing the clock 32 times. 245 */ 246static void 247vr_mii_sync(sc) 248 struct vr_softc *sc; 249{ 250 register int i; 251 252 SIO_SET(VR_MIICMD_DIR|VR_MIICMD_DATAIN); 253 254 for (i = 0; i < 32; i++) { 255 SIO_SET(VR_MIICMD_CLK); 256 DELAY(1); 257 SIO_CLR(VR_MIICMD_CLK); 258 DELAY(1); 259 } 260 261 return; 262} 263 264/* 265 * Clock a series of bits through the MII. 266 */ 267static void 268vr_mii_send(sc, bits, cnt) 269 struct vr_softc *sc; 270 u_int32_t bits; 271 int cnt; 272{ 273 int i; 274 275 SIO_CLR(VR_MIICMD_CLK); 276 277 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 278 if (bits & i) { 279 SIO_SET(VR_MIICMD_DATAIN); 280 } else { 281 SIO_CLR(VR_MIICMD_DATAIN); 282 } 283 DELAY(1); 284 SIO_CLR(VR_MIICMD_CLK); 285 DELAY(1); 286 SIO_SET(VR_MIICMD_CLK); 287 } 288} 289#endif 290 291/* 292 * Read an PHY register through the MII. 293 */ 294static int 295vr_mii_readreg(sc, frame) 296 struct vr_softc *sc; 297 struct vr_mii_frame *frame; 298 299#ifdef VR_USESWSHIFT 300{ 301 int i, ack; 302 303 VR_LOCK(sc); 304 305 /* 306 * Set up frame for RX. 307 */ 308 frame->mii_stdelim = VR_MII_STARTDELIM; 309 frame->mii_opcode = VR_MII_READOP; 310 frame->mii_turnaround = 0; 311 frame->mii_data = 0; 312 313 CSR_WRITE_1(sc, VR_MIICMD, 0); 314 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM); 315 316 /* 317 * Turn on data xmit. 318 */ 319 SIO_SET(VR_MIICMD_DIR); 320 321 vr_mii_sync(sc); 322 323 /* 324 * Send command/address info. 325 */ 326 vr_mii_send(sc, frame->mii_stdelim, 2); 327 vr_mii_send(sc, frame->mii_opcode, 2); 328 vr_mii_send(sc, frame->mii_phyaddr, 5); 329 vr_mii_send(sc, frame->mii_regaddr, 5); 330 331 /* Idle bit */ 332 SIO_CLR((VR_MIICMD_CLK|VR_MIICMD_DATAIN)); 333 DELAY(1); 334 SIO_SET(VR_MIICMD_CLK); 335 DELAY(1); 336 337 /* Turn off xmit. */ 338 SIO_CLR(VR_MIICMD_DIR); 339 340 /* Check for ack */ 341 SIO_CLR(VR_MIICMD_CLK); 342 DELAY(1); 343 ack = CSR_READ_4(sc, VR_MIICMD) & VR_MIICMD_DATAOUT; 344 SIO_SET(VR_MIICMD_CLK); 345 DELAY(1); 346 347 /* 348 * Now try reading data bits. If the ack failed, we still 349 * need to clock through 16 cycles to keep the PHY(s) in sync. 350 */ 351 if (ack) { 352 for(i = 0; i < 16; i++) { 353 SIO_CLR(VR_MIICMD_CLK); 354 DELAY(1); 355 SIO_SET(VR_MIICMD_CLK); 356 DELAY(1); 357 } 358 goto fail; 359 } 360 361 for (i = 0x8000; i; i >>= 1) { 362 SIO_CLR(VR_MIICMD_CLK); 363 DELAY(1); 364 if (!ack) { 365 if (CSR_READ_4(sc, VR_MIICMD) & VR_MIICMD_DATAOUT) 366 frame->mii_data |= i; 367 DELAY(1); 368 } 369 SIO_SET(VR_MIICMD_CLK); 370 DELAY(1); 371 } 372 373fail: 374 375 SIO_CLR(VR_MIICMD_CLK); 376 DELAY(1); 377 SIO_SET(VR_MIICMD_CLK); 378 DELAY(1); 379 380 VR_UNLOCK(sc); 381 382 if (ack) 383 return(1); 384 return(0); 385} 386#else 387{ 388 int s, i; 389 390 s = splimp(); 391 392 /* Set the PHY-adress */ 393 CSR_WRITE_1(sc, VR_PHYADDR, (CSR_READ_1(sc, VR_PHYADDR)& 0xe0)| 394 frame->mii_phyaddr); 395 396 /* Set the register-adress */ 397 CSR_WRITE_1(sc, VR_MIIADDR, frame->mii_regaddr); 398 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_READ_ENB); 399 400 for (i = 0; i < 10000; i++) { 401 if ((CSR_READ_1(sc, VR_MIICMD) & VR_MIICMD_READ_ENB) == 0) 402 break; 403 DELAY(1); 404 } 405 406 frame->mii_data = CSR_READ_2(sc, VR_MIIDATA); 407 408 (void)splx(s); 409 410 return(0); 411} 412#endif 413 414 415/* 416 * Write to a PHY register through the MII. 417 */ 418static int 419vr_mii_writereg(sc, frame) 420 struct vr_softc *sc; 421 struct vr_mii_frame *frame; 422 423#ifdef VR_USESWSHIFT 424{ 425 VR_LOCK(sc); 426 427 CSR_WRITE_1(sc, VR_MIICMD, 0); 428 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM); 429 430 /* 431 * Set up frame for TX. 432 */ 433 434 frame->mii_stdelim = VR_MII_STARTDELIM; 435 frame->mii_opcode = VR_MII_WRITEOP; 436 frame->mii_turnaround = VR_MII_TURNAROUND; 437 438 /* 439 * Turn on data output. 440 */ 441 SIO_SET(VR_MIICMD_DIR); 442 443 vr_mii_sync(sc); 444 445 vr_mii_send(sc, frame->mii_stdelim, 2); 446 vr_mii_send(sc, frame->mii_opcode, 2); 447 vr_mii_send(sc, frame->mii_phyaddr, 5); 448 vr_mii_send(sc, frame->mii_regaddr, 5); 449 vr_mii_send(sc, frame->mii_turnaround, 2); 450 vr_mii_send(sc, frame->mii_data, 16); 451 452 /* Idle bit. */ 453 SIO_SET(VR_MIICMD_CLK); 454 DELAY(1); 455 SIO_CLR(VR_MIICMD_CLK); 456 DELAY(1); 457 458 /* 459 * Turn off xmit. 460 */ 461 SIO_CLR(VR_MIICMD_DIR); 462 463 VR_UNLOCK(sc); 464 465 return(0); 466} 467#else 468{ 469 int s, i; 470 471 s = splimp(); 472 473 /* Set the PHY-adress */ 474 CSR_WRITE_1(sc, VR_PHYADDR, (CSR_READ_1(sc, VR_PHYADDR)& 0xe0)| 475 frame->mii_phyaddr); 476 477 /* Set the register-adress and data to write */ 478 CSR_WRITE_1(sc, VR_MIIADDR, frame->mii_regaddr); 479 CSR_WRITE_2(sc, VR_MIIDATA, frame->mii_data); 480 481 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_WRITE_ENB); 482 483 for (i = 0; i < 10000; i++) { 484 if ((CSR_READ_1(sc, VR_MIICMD) & VR_MIICMD_WRITE_ENB) == 0) 485 break; 486 DELAY(1); 487 } 488 489 (void)splx(s); 490 491 return(0); 492} 493#endif 494 495static int 496vr_miibus_readreg(dev, phy, reg) 497 device_t dev; 498 int phy, reg; 499{ 500 struct vr_softc *sc; 501 struct vr_mii_frame frame; 502 503 sc = device_get_softc(dev); 504 505 switch (sc->vr_revid) { 506 case REV_ID_VT6102_APOLLO: 507 if (phy != 1) 508 return 0; 509 default: 510 break; 511 } 512 513 bzero((char *)&frame, sizeof(frame)); 514 515 frame.mii_phyaddr = phy; 516 frame.mii_regaddr = reg; 517 vr_mii_readreg(sc, &frame); 518 519 return(frame.mii_data); 520} 521 522static int 523vr_miibus_writereg(dev, phy, reg, data) 524 device_t dev; 525 u_int16_t phy, reg, data; 526{ 527 struct vr_softc *sc; 528 struct vr_mii_frame frame; 529 530 sc = device_get_softc(dev); 531 532 switch (sc->vr_revid) { 533 case REV_ID_VT6102_APOLLO: 534 if (phy != 1) 535 return 0; 536 default: 537 break; 538 } 539 540 bzero((char *)&frame, sizeof(frame)); 541 542 frame.mii_phyaddr = phy; 543 frame.mii_regaddr = reg; 544 frame.mii_data = data; 545 546 vr_mii_writereg(sc, &frame); 547 548 return(0); 549} 550 551static void 552vr_miibus_statchg(dev) 553 device_t dev; 554{ 555 struct vr_softc *sc; 556 struct mii_data *mii; 557 558 sc = device_get_softc(dev); 559 VR_LOCK(sc); 560 mii = device_get_softc(sc->vr_miibus); 561 vr_setcfg(sc, mii->mii_media_active); 562 VR_UNLOCK(sc); 563 564 return; 565} 566 567/* 568 * Calculate CRC of a multicast group address, return the lower 6 bits. 569 */ 570static u_int8_t vr_calchash(addr) 571 u_int8_t *addr; 572{ 573 u_int32_t crc, carry; 574 int i, j; 575 u_int8_t c; 576 577 /* Compute CRC for the address value. */ 578 crc = 0xFFFFFFFF; /* initial value */ 579 580 for (i = 0; i < 6; i++) { 581 c = *(addr + i); 582 for (j = 0; j < 8; j++) { 583 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 584 crc <<= 1; 585 c >>= 1; 586 if (carry) 587 crc = (crc ^ 0x04c11db6) | carry; 588 } 589 } 590 591 /* return the filter bit position */ 592 return((crc >> 26) & 0x0000003F); 593} 594 595/* 596 * Program the 64-bit multicast hash filter. 597 */ 598static void 599vr_setmulti(sc) 600 struct vr_softc *sc; 601{ 602 struct ifnet *ifp; 603 int h = 0; 604 u_int32_t hashes[2] = { 0, 0 }; 605 struct ifmultiaddr *ifma; 606 u_int8_t rxfilt; 607 int mcnt = 0; 608 609 ifp = &sc->arpcom.ac_if; 610 611 rxfilt = CSR_READ_1(sc, VR_RXCFG); 612 613 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 614 rxfilt |= VR_RXCFG_RX_MULTI; 615 CSR_WRITE_1(sc, VR_RXCFG, rxfilt); 616 CSR_WRITE_4(sc, VR_MAR0, 0xFFFFFFFF); 617 CSR_WRITE_4(sc, VR_MAR1, 0xFFFFFFFF); 618 return; 619 } 620 621 /* first, zot all the existing hash bits */ 622 CSR_WRITE_4(sc, VR_MAR0, 0); 623 CSR_WRITE_4(sc, VR_MAR1, 0); 624 625 /* now program new ones */ 626 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 627 if (ifma->ifma_addr->sa_family != AF_LINK) 628 continue; 629 h = vr_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 630 if (h < 32) 631 hashes[0] |= (1 << h); 632 else 633 hashes[1] |= (1 << (h - 32)); 634 mcnt++; 635 } 636 637 if (mcnt) 638 rxfilt |= VR_RXCFG_RX_MULTI; 639 else 640 rxfilt &= ~VR_RXCFG_RX_MULTI; 641 642 CSR_WRITE_4(sc, VR_MAR0, hashes[0]); 643 CSR_WRITE_4(sc, VR_MAR1, hashes[1]); 644 CSR_WRITE_1(sc, VR_RXCFG, rxfilt); 645 646 return; 647} 648 649/* 650 * In order to fiddle with the 651 * 'full-duplex' and '100Mbps' bits in the netconfig register, we 652 * first have to put the transmit and/or receive logic in the idle state. 653 */ 654static void 655vr_setcfg(sc, media) 656 struct vr_softc *sc; 657 int media; 658{ 659 int restart = 0; 660 661 if (CSR_READ_2(sc, VR_COMMAND) & (VR_CMD_TX_ON|VR_CMD_RX_ON)) { 662 restart = 1; 663 VR_CLRBIT16(sc, VR_COMMAND, (VR_CMD_TX_ON|VR_CMD_RX_ON)); 664 } 665 666 if ((media & IFM_GMASK) == IFM_FDX) 667 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX); 668 else 669 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX); 670 671 if (restart) 672 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_ON|VR_CMD_RX_ON); 673 674 return; 675} 676 677static void 678vr_reset(sc) 679 struct vr_softc *sc; 680{ 681 register int i; 682 683 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RESET); 684 685 for (i = 0; i < VR_TIMEOUT; i++) { 686 DELAY(10); 687 if (!(CSR_READ_2(sc, VR_COMMAND) & VR_CMD_RESET)) 688 break; 689 } 690 if (i == VR_TIMEOUT) { 691 if (sc->vr_revid < REV_ID_VT3065_A) 692 printf("vr%d: reset never completed!\n", sc->vr_unit); 693 else { 694 /* Use newer force reset command */ 695 printf("vr%d: Using force reset command.\n", sc->vr_unit); 696 VR_SETBIT(sc, VR_MISC_CR1, VR_MISCCR1_FORSRST); 697 } 698 } 699 700 /* Wait a little while for the chip to get its brains in order. */ 701 DELAY(1000); 702 703 return; 704} 705 706/* 707 * Probe for a VIA Rhine chip. Check the PCI vendor and device 708 * IDs against our list and return a device name if we find a match. 709 */ 710static int 711vr_probe(dev) 712 device_t dev; 713{ 714 struct vr_type *t; 715 716 t = vr_devs; 717 718 while(t->vr_name != NULL) { 719 if ((pci_get_vendor(dev) == t->vr_vid) && 720 (pci_get_device(dev) == t->vr_did)) { 721 device_set_desc(dev, t->vr_name); 722 return(0); 723 } 724 t++; 725 } 726 727 return(ENXIO); 728} 729 730/* 731 * Attach the interface. Allocate softc structures, do ifmedia 732 * setup and ethernet/BPF attach. 733 */ 734static int 735vr_attach(dev) 736 device_t dev; 737{ 738 int i; 739 u_char eaddr[ETHER_ADDR_LEN]; 740 u_int32_t command; 741 struct vr_softc *sc; 742 struct ifnet *ifp; 743 int unit, error = 0, rid; 744 745 sc = device_get_softc(dev); 746 unit = device_get_unit(dev); 747 bzero(sc, sizeof(struct vr_softc *)); 748 749 mtx_init(&sc->vr_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 750 MTX_DEF | MTX_RECURSE); 751 VR_LOCK(sc); 752 753 /* 754 * Handle power management nonsense. 755 */ 756 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 757 u_int32_t iobase, membase, irq; 758 759 /* Save important PCI config data. */ 760 iobase = pci_read_config(dev, VR_PCI_LOIO, 4); 761 membase = pci_read_config(dev, VR_PCI_LOMEM, 4); 762 irq = pci_read_config(dev, VR_PCI_INTLINE, 4); 763 764 /* Reset the power state. */ 765 printf("vr%d: chip is in D%d power mode " 766 "-- setting to D0\n", unit, 767 pci_get_powerstate(dev)); 768 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 769 770 /* Restore PCI config data. */ 771 pci_write_config(dev, VR_PCI_LOIO, iobase, 4); 772 pci_write_config(dev, VR_PCI_LOMEM, membase, 4); 773 pci_write_config(dev, VR_PCI_INTLINE, irq, 4); 774 } 775 776 /* 777 * Map control/status registers. 778 */ 779 pci_enable_busmaster(dev); 780 pci_enable_io(dev, SYS_RES_IOPORT); 781 pci_enable_io(dev, SYS_RES_MEMORY); 782 command = pci_read_config(dev, PCIR_COMMAND, 4); 783 sc->vr_revid = pci_read_config(dev, VR_PCI_REVID, 4) & 0x000000FF; 784 785#ifdef VR_USEIOSPACE 786 if (!(command & PCIM_CMD_PORTEN)) { 787 printf("vr%d: failed to enable I/O ports!\n", unit); 788 free(sc, M_DEVBUF); 789 goto fail; 790 } 791#else 792 if (!(command & PCIM_CMD_MEMEN)) { 793 printf("vr%d: failed to enable memory mapping!\n", unit); 794 goto fail; 795 } 796#endif 797 798 rid = VR_RID; 799 sc->vr_res = bus_alloc_resource(dev, VR_RES, &rid, 800 0, ~0, 1, RF_ACTIVE); 801 802 if (sc->vr_res == NULL) { 803 printf("vr%d: couldn't map ports/memory\n", unit); 804 error = ENXIO; 805 goto fail; 806 } 807 808 sc->vr_btag = rman_get_bustag(sc->vr_res); 809 sc->vr_bhandle = rman_get_bushandle(sc->vr_res); 810 811 /* Allocate interrupt */ 812 rid = 0; 813 sc->vr_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 814 RF_SHAREABLE | RF_ACTIVE); 815 816 if (sc->vr_irq == NULL) { 817 printf("vr%d: couldn't map interrupt\n", unit); 818 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res); 819 error = ENXIO; 820 goto fail; 821 } 822 823 error = bus_setup_intr(dev, sc->vr_irq, INTR_TYPE_NET, 824 vr_intr, sc, &sc->vr_intrhand); 825 826 if (error) { 827 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq); 828 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res); 829 printf("vr%d: couldn't set up irq\n", unit); 830 goto fail; 831 } 832 833 /* 834 * Windows may put the chip in suspend mode when it 835 * shuts down. Be sure to kick it in the head to wake it 836 * up again. 837 */ 838 VR_CLRBIT(sc, VR_STICKHW, (VR_STICKHW_DS0|VR_STICKHW_DS1)); 839 840 /* Reset the adapter. */ 841 vr_reset(sc); 842 843 /* 844 * Turn on bit2 (MIION) in PCI configuration register 0x53 during 845 * initialization and disable AUTOPOLL. 846 */ 847 pci_write_config(dev, VR_PCI_MODE, 848 pci_read_config(dev, VR_PCI_MODE, 4) | (VR_MODE3_MIION << 24), 4); 849 VR_CLRBIT(sc, VR_MIICMD, VR_MIICMD_AUTOPOLL); 850 851 /* 852 * Get station address. The way the Rhine chips work, 853 * you're not allowed to directly access the EEPROM once 854 * they've been programmed a special way. Consequently, 855 * we need to read the node address from the PAR0 and PAR1 856 * registers. 857 */ 858 VR_SETBIT(sc, VR_EECSR, VR_EECSR_LOAD); 859 DELAY(200); 860 for (i = 0; i < ETHER_ADDR_LEN; i++) 861 eaddr[i] = CSR_READ_1(sc, VR_PAR0 + i); 862 863 /* 864 * A Rhine chip was detected. Inform the world. 865 */ 866 printf("vr%d: Ethernet address: %6D\n", unit, eaddr, ":"); 867 868 sc->vr_unit = unit; 869 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 870 871 sc->vr_ldata = contigmalloc(sizeof(struct vr_list_data), M_DEVBUF, 872 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 873 874 if (sc->vr_ldata == NULL) { 875 printf("vr%d: no memory for list buffers!\n", unit); 876 bus_teardown_intr(dev, sc->vr_irq, sc->vr_intrhand); 877 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq); 878 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res); 879 error = ENXIO; 880 goto fail; 881 } 882 883 bzero(sc->vr_ldata, sizeof(struct vr_list_data)); 884 885 ifp = &sc->arpcom.ac_if; 886 ifp->if_softc = sc; 887 ifp->if_unit = unit; 888 ifp->if_name = "vr"; 889 ifp->if_mtu = ETHERMTU; 890 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 891 ifp->if_ioctl = vr_ioctl; 892 ifp->if_output = ether_output; 893 ifp->if_start = vr_start; 894 ifp->if_watchdog = vr_watchdog; 895 ifp->if_init = vr_init; 896 ifp->if_baudrate = 10000000; 897 ifp->if_snd.ifq_maxlen = VR_TX_LIST_CNT - 1; 898 899 /* 900 * Do MII setup. 901 */ 902 if (mii_phy_probe(dev, &sc->vr_miibus, 903 vr_ifmedia_upd, vr_ifmedia_sts)) { 904 printf("vr%d: MII without any phy!\n", sc->vr_unit); 905 bus_teardown_intr(dev, sc->vr_irq, sc->vr_intrhand); 906 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq); 907 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res); 908 contigfree(sc->vr_ldata, 909 sizeof(struct vr_list_data), M_DEVBUF); 910 error = ENXIO; 911 goto fail; 912 } 913 914 callout_handle_init(&sc->vr_stat_ch); 915 916 /* 917 * Call MI attach routine. 918 */ 919 ether_ifattach(ifp, eaddr); 920 VR_UNLOCK(sc); 921 return(0); 922 923fail: 924 VR_UNLOCK(sc); 925 mtx_destroy(&sc->vr_mtx); 926 927 return(error); 928} 929 930static int 931vr_detach(dev) 932 device_t dev; 933{ 934 struct vr_softc *sc; 935 struct ifnet *ifp; 936 937 sc = device_get_softc(dev); 938 VR_LOCK(sc); 939 ifp = &sc->arpcom.ac_if; 940 941 vr_stop(sc); 942 ether_ifdetach(ifp); 943 944 bus_generic_detach(dev); 945 device_delete_child(dev, sc->vr_miibus); 946 947 bus_teardown_intr(dev, sc->vr_irq, sc->vr_intrhand); 948 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq); 949 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res); 950 951 contigfree(sc->vr_ldata, sizeof(struct vr_list_data), M_DEVBUF); 952 953 VR_UNLOCK(sc); 954 mtx_destroy(&sc->vr_mtx); 955 956 return(0); 957} 958 959/* 960 * Initialize the transmit descriptors. 961 */ 962static int 963vr_list_tx_init(sc) 964 struct vr_softc *sc; 965{ 966 struct vr_chain_data *cd; 967 struct vr_list_data *ld; 968 int i; 969 970 cd = &sc->vr_cdata; 971 ld = sc->vr_ldata; 972 for (i = 0; i < VR_TX_LIST_CNT; i++) { 973 cd->vr_tx_chain[i].vr_ptr = &ld->vr_tx_list[i]; 974 if (i == (VR_TX_LIST_CNT - 1)) 975 cd->vr_tx_chain[i].vr_nextdesc = 976 &cd->vr_tx_chain[0]; 977 else 978 cd->vr_tx_chain[i].vr_nextdesc = 979 &cd->vr_tx_chain[i + 1]; 980 } 981 982 cd->vr_tx_free = &cd->vr_tx_chain[0]; 983 cd->vr_tx_tail = cd->vr_tx_head = NULL; 984 985 return(0); 986} 987 988 989/* 990 * Initialize the RX descriptors and allocate mbufs for them. Note that 991 * we arrange the descriptors in a closed ring, so that the last descriptor 992 * points back to the first. 993 */ 994static int 995vr_list_rx_init(sc) 996 struct vr_softc *sc; 997{ 998 struct vr_chain_data *cd; 999 struct vr_list_data *ld; 1000 int i; 1001 1002 cd = &sc->vr_cdata; 1003 ld = sc->vr_ldata; 1004 1005 for (i = 0; i < VR_RX_LIST_CNT; i++) { 1006 cd->vr_rx_chain[i].vr_ptr = 1007 (struct vr_desc *)&ld->vr_rx_list[i]; 1008 if (vr_newbuf(sc, &cd->vr_rx_chain[i], NULL) == ENOBUFS) 1009 return(ENOBUFS); 1010 if (i == (VR_RX_LIST_CNT - 1)) { 1011 cd->vr_rx_chain[i].vr_nextdesc = 1012 &cd->vr_rx_chain[0]; 1013 ld->vr_rx_list[i].vr_next = 1014 vtophys(&ld->vr_rx_list[0]); 1015 } else { 1016 cd->vr_rx_chain[i].vr_nextdesc = 1017 &cd->vr_rx_chain[i + 1]; 1018 ld->vr_rx_list[i].vr_next = 1019 vtophys(&ld->vr_rx_list[i + 1]); 1020 } 1021 } 1022 1023 cd->vr_rx_head = &cd->vr_rx_chain[0]; 1024 1025 return(0); 1026} 1027 1028/* 1029 * Initialize an RX descriptor and attach an MBUF cluster. 1030 * Note: the length fields are only 11 bits wide, which means the 1031 * largest size we can specify is 2047. This is important because 1032 * MCLBYTES is 2048, so we have to subtract one otherwise we'll 1033 * overflow the field and make a mess. 1034 */ 1035static int 1036vr_newbuf(sc, c, m) 1037 struct vr_softc *sc; 1038 struct vr_chain_onefrag *c; 1039 struct mbuf *m; 1040{ 1041 struct mbuf *m_new = NULL; 1042 1043 if (m == NULL) { 1044 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1045 if (m_new == NULL) 1046 return(ENOBUFS); 1047 1048 MCLGET(m_new, M_DONTWAIT); 1049 if (!(m_new->m_flags & M_EXT)) { 1050 m_freem(m_new); 1051 return(ENOBUFS); 1052 } 1053 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1054 } else { 1055 m_new = m; 1056 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1057 m_new->m_data = m_new->m_ext.ext_buf; 1058 } 1059 1060 m_adj(m_new, sizeof(u_int64_t)); 1061 1062 c->vr_mbuf = m_new; 1063 c->vr_ptr->vr_status = VR_RXSTAT; 1064 c->vr_ptr->vr_data = vtophys(mtod(m_new, caddr_t)); 1065 c->vr_ptr->vr_ctl = VR_RXCTL | VR_RXLEN; 1066 1067 return(0); 1068} 1069 1070/* 1071 * A frame has been uploaded: pass the resulting mbuf chain up to 1072 * the higher level protocols. 1073 */ 1074static void 1075vr_rxeof(sc) 1076 struct vr_softc *sc; 1077{ 1078 struct mbuf *m; 1079 struct ifnet *ifp; 1080 struct vr_chain_onefrag *cur_rx; 1081 int total_len = 0; 1082 u_int32_t rxstat; 1083 1084 ifp = &sc->arpcom.ac_if; 1085 1086 while(!((rxstat = sc->vr_cdata.vr_rx_head->vr_ptr->vr_status) & 1087 VR_RXSTAT_OWN)) { 1088 struct mbuf *m0 = NULL; 1089 1090 cur_rx = sc->vr_cdata.vr_rx_head; 1091 sc->vr_cdata.vr_rx_head = cur_rx->vr_nextdesc; 1092 m = cur_rx->vr_mbuf; 1093 1094 /* 1095 * If an error occurs, update stats, clear the 1096 * status word and leave the mbuf cluster in place: 1097 * it should simply get re-used next time this descriptor 1098 * comes up in the ring. 1099 */ 1100 if (rxstat & VR_RXSTAT_RXERR) { 1101 ifp->if_ierrors++; 1102 printf("vr%d: rx error (%02x):", 1103 sc->vr_unit, rxstat & 0x000000ff); 1104 if (rxstat & VR_RXSTAT_CRCERR) 1105 printf(" crc error"); 1106 if (rxstat & VR_RXSTAT_FRAMEALIGNERR) 1107 printf(" frame alignment error\n"); 1108 if (rxstat & VR_RXSTAT_FIFOOFLOW) 1109 printf(" FIFO overflow"); 1110 if (rxstat & VR_RXSTAT_GIANT) 1111 printf(" received giant packet"); 1112 if (rxstat & VR_RXSTAT_RUNT) 1113 printf(" received runt packet"); 1114 if (rxstat & VR_RXSTAT_BUSERR) 1115 printf(" system bus error"); 1116 if (rxstat & VR_RXSTAT_BUFFERR) 1117 printf("rx buffer error"); 1118 printf("\n"); 1119 vr_newbuf(sc, cur_rx, m); 1120 continue; 1121 } 1122 1123 /* No errors; receive the packet. */ 1124 total_len = VR_RXBYTES(cur_rx->vr_ptr->vr_status); 1125 1126 /* 1127 * XXX The VIA Rhine chip includes the CRC with every 1128 * received frame, and there's no way to turn this 1129 * behavior off (at least, I can't find anything in 1130 * the manual that explains how to do it) so we have 1131 * to trim off the CRC manually. 1132 */ 1133 total_len -= ETHER_CRC_LEN; 1134 1135 m0 = m_devget(mtod(m, char *), total_len, ETHER_ALIGN, ifp, 1136 NULL); 1137 vr_newbuf(sc, cur_rx, m); 1138 if (m0 == NULL) { 1139 ifp->if_ierrors++; 1140 continue; 1141 } 1142 m = m0; 1143 1144 ifp->if_ipackets++; 1145 (*ifp->if_input)(ifp, m); 1146 } 1147 1148 return; 1149} 1150 1151static void 1152vr_rxeoc(sc) 1153 struct vr_softc *sc; 1154{ 1155 struct ifnet *ifp; 1156 int i; 1157 1158 ifp = &sc->arpcom.ac_if; 1159 1160 ifp->if_ierrors++; 1161 1162 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_RX_ON); 1163 DELAY(10000); 1164 1165 for (i = 0x400; 1166 i && (CSR_READ_2(sc, VR_COMMAND) & VR_CMD_RX_ON); 1167 i--) 1168 ; /* Wait for receiver to stop */ 1169 1170 if (!i) { 1171 printf("vr%d: rx shutdown error!\n", sc->vr_unit); 1172 sc->vr_flags |= VR_F_RESTART; 1173 return; 1174 } 1175 1176 vr_rxeof(sc); 1177 1178 CSR_WRITE_4(sc, VR_RXADDR, vtophys(sc->vr_cdata.vr_rx_head->vr_ptr)); 1179 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RX_ON); 1180 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RX_GO); 1181 1182 return; 1183} 1184 1185/* 1186 * A frame was downloaded to the chip. It's safe for us to clean up 1187 * the list buffers. 1188 */ 1189 1190static void 1191vr_txeof(sc) 1192 struct vr_softc *sc; 1193{ 1194 struct vr_chain *cur_tx; 1195 struct ifnet *ifp; 1196 1197 ifp = &sc->arpcom.ac_if; 1198 1199 /* Reset the timeout timer; if_txeoc will clear it. */ 1200 ifp->if_timer = 5; 1201 1202 /* Sanity check. */ 1203 if (sc->vr_cdata.vr_tx_head == NULL) 1204 return; 1205 1206 /* 1207 * Go through our tx list and free mbufs for those 1208 * frames that have been transmitted. 1209 */ 1210 while(sc->vr_cdata.vr_tx_head->vr_mbuf != NULL) { 1211 u_int32_t txstat; 1212 int i; 1213 1214 cur_tx = sc->vr_cdata.vr_tx_head; 1215 txstat = cur_tx->vr_ptr->vr_status; 1216 1217 if ((txstat & VR_TXSTAT_ABRT) || 1218 (txstat & VR_TXSTAT_UDF)) { 1219 for (i = 0x400; 1220 i && (CSR_READ_2(sc, VR_COMMAND) & VR_CMD_TX_ON); 1221 i--) 1222 ; /* Wait for chip to shutdown */ 1223 if (!i) { 1224 printf("vr%d: tx shutdown timeout\n", sc->vr_unit); 1225 sc->vr_flags |= VR_F_RESTART; 1226 break; 1227 } 1228 VR_TXOWN(cur_tx) = VR_TXSTAT_OWN; 1229 CSR_WRITE_4(sc, VR_TXADDR, vtophys(cur_tx->vr_ptr)); 1230 break; 1231 } 1232 1233 if (txstat & VR_TXSTAT_OWN) 1234 break; 1235 1236 if (txstat & VR_TXSTAT_ERRSUM) { 1237 ifp->if_oerrors++; 1238 if (txstat & VR_TXSTAT_DEFER) 1239 ifp->if_collisions++; 1240 if (txstat & VR_TXSTAT_LATECOLL) 1241 ifp->if_collisions++; 1242 } 1243 1244 ifp->if_collisions +=(txstat & VR_TXSTAT_COLLCNT) >> 3; 1245 1246 ifp->if_opackets++; 1247 if (cur_tx->vr_mbuf != NULL) { 1248 m_freem(cur_tx->vr_mbuf); 1249 cur_tx->vr_mbuf = NULL; 1250 } 1251 1252 if (sc->vr_cdata.vr_tx_head == sc->vr_cdata.vr_tx_tail) { 1253 sc->vr_cdata.vr_tx_head = NULL; 1254 sc->vr_cdata.vr_tx_tail = NULL; 1255 break; 1256 } 1257 1258 sc->vr_cdata.vr_tx_head = cur_tx->vr_nextdesc; 1259 } 1260 1261 return; 1262} 1263 1264/* 1265 * TX 'end of channel' interrupt handler. 1266 */ 1267static void 1268vr_txeoc(sc) 1269 struct vr_softc *sc; 1270{ 1271 struct ifnet *ifp; 1272 1273 ifp = &sc->arpcom.ac_if; 1274 1275 if (sc->vr_cdata.vr_tx_head == NULL) { 1276 ifp->if_flags &= ~IFF_OACTIVE; 1277 sc->vr_cdata.vr_tx_tail = NULL; 1278 ifp->if_timer = 0; 1279 } 1280 1281 return; 1282} 1283 1284static void 1285vr_tick(xsc) 1286 void *xsc; 1287{ 1288 struct vr_softc *sc; 1289 struct mii_data *mii; 1290 1291 sc = xsc; 1292 VR_LOCK(sc); 1293 if (sc->vr_flags & VR_F_RESTART) { 1294 printf("vr%d: restarting\n", sc->vr_unit); 1295 vr_stop(sc); 1296 vr_reset(sc); 1297 vr_init(sc); 1298 sc->vr_flags &= ~VR_F_RESTART; 1299 } 1300 1301 mii = device_get_softc(sc->vr_miibus); 1302 mii_tick(mii); 1303 1304 sc->vr_stat_ch = timeout(vr_tick, sc, hz); 1305 1306 VR_UNLOCK(sc); 1307 1308 return; 1309} 1310 1311static void 1312vr_intr(arg) 1313 void *arg; 1314{ 1315 struct vr_softc *sc; 1316 struct ifnet *ifp; 1317 u_int16_t status; 1318 1319 sc = arg; 1320 VR_LOCK(sc); 1321 ifp = &sc->arpcom.ac_if; 1322 1323 /* Supress unwanted interrupts. */ 1324 if (!(ifp->if_flags & IFF_UP)) { 1325 vr_stop(sc); 1326 VR_UNLOCK(sc); 1327 return; 1328 } 1329 1330 /* Disable interrupts. */ 1331 CSR_WRITE_2(sc, VR_IMR, 0x0000); 1332 1333 for (;;) { 1334 1335 status = CSR_READ_2(sc, VR_ISR); 1336 if (status) 1337 CSR_WRITE_2(sc, VR_ISR, status); 1338 1339 if ((status & VR_INTRS) == 0) 1340 break; 1341 1342 if (status & VR_ISR_RX_OK) 1343 vr_rxeof(sc); 1344 1345 if (status & VR_ISR_RX_DROPPED) { 1346 printf("vr%d: rx packet lost\n", sc->vr_unit); 1347 ifp->if_ierrors++; 1348 } 1349 1350 if ((status & VR_ISR_RX_ERR) || (status & VR_ISR_RX_NOBUF) || 1351 (status & VR_ISR_RX_NOBUF) || (status & VR_ISR_RX_OFLOW)) { 1352 printf("vr%d: receive error (%04x)", 1353 sc->vr_unit, status); 1354 if (status & VR_ISR_RX_NOBUF) 1355 printf(" no buffers"); 1356 if (status & VR_ISR_RX_OFLOW) 1357 printf(" overflow"); 1358 if (status & VR_ISR_RX_DROPPED) 1359 printf(" packet lost"); 1360 printf("\n"); 1361 vr_rxeoc(sc); 1362 } 1363 1364 if ((status & VR_ISR_BUSERR) || (status & VR_ISR_TX_UNDERRUN)) { 1365 vr_reset(sc); 1366 vr_init(sc); 1367 break; 1368 } 1369 1370 if ((status & VR_ISR_TX_OK) || (status & VR_ISR_TX_ABRT) || 1371 (status & VR_ISR_TX_ABRT2) || (status & VR_ISR_UDFI)) { 1372 vr_txeof(sc); 1373 if ((status & VR_ISR_UDFI) || 1374 (status & VR_ISR_TX_ABRT2) || 1375 (status & VR_ISR_TX_ABRT)) { 1376 ifp->if_oerrors++; 1377 if (sc->vr_cdata.vr_tx_head != NULL) { 1378 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_ON); 1379 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_GO); 1380 } 1381 } else 1382 vr_txeoc(sc); 1383 } 1384 1385 } 1386 1387 /* Re-enable interrupts. */ 1388 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 1389 1390 if (ifp->if_snd.ifq_head != NULL) { 1391 vr_start(ifp); 1392 } 1393 1394 VR_UNLOCK(sc); 1395 1396 return; 1397} 1398 1399/* 1400 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1401 * pointers to the fragment pointers. 1402 */ 1403static int 1404vr_encap(sc, c, m_head) 1405 struct vr_softc *sc; 1406 struct vr_chain *c; 1407 struct mbuf *m_head; 1408{ 1409 int frag = 0; 1410 struct vr_desc *f = NULL; 1411 int total_len; 1412 struct mbuf *m; 1413 1414 m = m_head; 1415 total_len = 0; 1416 1417 /* 1418 * The VIA Rhine wants packet buffers to be longword 1419 * aligned, but very often our mbufs aren't. Rather than 1420 * waste time trying to decide when to copy and when not 1421 * to copy, just do it all the time. 1422 */ 1423 if (m != NULL) { 1424 struct mbuf *m_new = NULL; 1425 1426 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1427 if (m_new == NULL) { 1428 printf("vr%d: no memory for tx list\n", sc->vr_unit); 1429 return(1); 1430 } 1431 if (m_head->m_pkthdr.len > MHLEN) { 1432 MCLGET(m_new, M_DONTWAIT); 1433 if (!(m_new->m_flags & M_EXT)) { 1434 m_freem(m_new); 1435 printf("vr%d: no memory for tx list\n", 1436 sc->vr_unit); 1437 return(1); 1438 } 1439 } 1440 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1441 mtod(m_new, caddr_t)); 1442 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1443 m_freem(m_head); 1444 m_head = m_new; 1445 /* 1446 * The Rhine chip doesn't auto-pad, so we have to make 1447 * sure to pad short frames out to the minimum frame length 1448 * ourselves. 1449 */ 1450 if (m_head->m_len < VR_MIN_FRAMELEN) { 1451 m_new->m_pkthdr.len += VR_MIN_FRAMELEN - m_new->m_len; 1452 m_new->m_len = m_new->m_pkthdr.len; 1453 } 1454 f = c->vr_ptr; 1455 f->vr_data = vtophys(mtod(m_new, caddr_t)); 1456 f->vr_ctl = total_len = m_new->m_len; 1457 f->vr_ctl |= VR_TXCTL_TLINK|VR_TXCTL_FIRSTFRAG; 1458 f->vr_status = 0; 1459 frag = 1; 1460 } 1461 1462 c->vr_mbuf = m_head; 1463 c->vr_ptr->vr_ctl |= VR_TXCTL_LASTFRAG|VR_TXCTL_FINT; 1464 c->vr_ptr->vr_next = vtophys(c->vr_nextdesc->vr_ptr); 1465 1466 return(0); 1467} 1468 1469/* 1470 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1471 * to the mbuf data regions directly in the transmit lists. We also save a 1472 * copy of the pointers since the transmit list fragment pointers are 1473 * physical addresses. 1474 */ 1475 1476static void 1477vr_start(ifp) 1478 struct ifnet *ifp; 1479{ 1480 struct vr_softc *sc; 1481 struct mbuf *m_head = NULL; 1482 struct vr_chain *cur_tx = NULL, *start_tx; 1483 1484 sc = ifp->if_softc; 1485 1486 VR_LOCK(sc); 1487 if (ifp->if_flags & IFF_OACTIVE) { 1488 VR_UNLOCK(sc); 1489 return; 1490 } 1491 1492 /* 1493 * Check for an available queue slot. If there are none, 1494 * punt. 1495 */ 1496 if (sc->vr_cdata.vr_tx_free->vr_mbuf != NULL) { 1497 ifp->if_flags |= IFF_OACTIVE; 1498 return; 1499 } 1500 1501 start_tx = sc->vr_cdata.vr_tx_free; 1502 1503 while(sc->vr_cdata.vr_tx_free->vr_mbuf == NULL) { 1504 IF_DEQUEUE(&ifp->if_snd, m_head); 1505 if (m_head == NULL) 1506 break; 1507 1508 /* Pick a descriptor off the free list. */ 1509 cur_tx = sc->vr_cdata.vr_tx_free; 1510 sc->vr_cdata.vr_tx_free = cur_tx->vr_nextdesc; 1511 1512 /* Pack the data into the descriptor. */ 1513 if (vr_encap(sc, cur_tx, m_head)) { 1514 IF_PREPEND(&ifp->if_snd, m_head); 1515 ifp->if_flags |= IFF_OACTIVE; 1516 cur_tx = NULL; 1517 break; 1518 } 1519 1520 if (cur_tx != start_tx) 1521 VR_TXOWN(cur_tx) = VR_TXSTAT_OWN; 1522 1523 /* 1524 * If there's a BPF listener, bounce a copy of this frame 1525 * to him. 1526 */ 1527 BPF_MTAP(ifp, cur_tx->vr_mbuf); 1528 1529 VR_TXOWN(cur_tx) = VR_TXSTAT_OWN; 1530 VR_SETBIT16(sc, VR_COMMAND, /*VR_CMD_TX_ON|*/VR_CMD_TX_GO); 1531 } 1532 1533 /* 1534 * If there are no frames queued, bail. 1535 */ 1536 if (cur_tx == NULL) { 1537 VR_UNLOCK(sc); 1538 return; 1539 } 1540 1541 sc->vr_cdata.vr_tx_tail = cur_tx; 1542 1543 if (sc->vr_cdata.vr_tx_head == NULL) 1544 sc->vr_cdata.vr_tx_head = start_tx; 1545 1546 /* 1547 * Set a timeout in case the chip goes out to lunch. 1548 */ 1549 ifp->if_timer = 5; 1550 VR_UNLOCK(sc); 1551 1552 return; 1553} 1554 1555static void 1556vr_init(xsc) 1557 void *xsc; 1558{ 1559 struct vr_softc *sc = xsc; 1560 struct ifnet *ifp = &sc->arpcom.ac_if; 1561 struct mii_data *mii; 1562 int i; 1563 1564 VR_LOCK(sc); 1565 1566 mii = device_get_softc(sc->vr_miibus); 1567 1568 /* 1569 * Cancel pending I/O and free all RX/TX buffers. 1570 */ 1571 vr_stop(sc); 1572 vr_reset(sc); 1573 1574 /* 1575 * Set our station address. 1576 */ 1577 for (i = 0; i < ETHER_ADDR_LEN; i++) 1578 CSR_WRITE_1(sc, VR_PAR0 + i, sc->arpcom.ac_enaddr[i]); 1579 1580 /* Set DMA size */ 1581 VR_CLRBIT(sc, VR_BCR0, VR_BCR0_DMA_LENGTH); 1582 VR_SETBIT(sc, VR_BCR0, VR_BCR0_DMA_STORENFWD); 1583 1584 /* 1585 * BCR0 and BCR1 can override the RXCFG and TXCFG registers, 1586 * so we must set both. 1587 */ 1588 VR_CLRBIT(sc, VR_BCR0, VR_BCR0_RX_THRESH); 1589 VR_SETBIT(sc, VR_BCR0, VR_BCR0_RXTHRESH128BYTES); 1590 1591 VR_CLRBIT(sc, VR_BCR1, VR_BCR1_TX_THRESH); 1592 VR_SETBIT(sc, VR_BCR1, VR_BCR1_TXTHRESHSTORENFWD); 1593 1594 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_THRESH); 1595 VR_SETBIT(sc, VR_RXCFG, VR_RXTHRESH_128BYTES); 1596 1597 VR_CLRBIT(sc, VR_TXCFG, VR_TXCFG_TX_THRESH); 1598 VR_SETBIT(sc, VR_TXCFG, VR_TXTHRESH_STORENFWD); 1599 1600 /* Init circular RX list. */ 1601 if (vr_list_rx_init(sc) == ENOBUFS) { 1602 printf("vr%d: initialization failed: no " 1603 "memory for rx buffers\n", sc->vr_unit); 1604 vr_stop(sc); 1605 VR_UNLOCK(sc); 1606 return; 1607 } 1608 1609 /* 1610 * Init tx descriptors. 1611 */ 1612 vr_list_tx_init(sc); 1613 1614 /* If we want promiscuous mode, set the allframes bit. */ 1615 if (ifp->if_flags & IFF_PROMISC) 1616 VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC); 1617 else 1618 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC); 1619 1620 /* Set capture broadcast bit to capture broadcast frames. */ 1621 if (ifp->if_flags & IFF_BROADCAST) 1622 VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD); 1623 else 1624 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD); 1625 1626 /* 1627 * Program the multicast filter, if necessary. 1628 */ 1629 vr_setmulti(sc); 1630 1631 /* 1632 * Load the address of the RX list. 1633 */ 1634 CSR_WRITE_4(sc, VR_RXADDR, vtophys(sc->vr_cdata.vr_rx_head->vr_ptr)); 1635 1636 /* Enable receiver and transmitter. */ 1637 CSR_WRITE_2(sc, VR_COMMAND, VR_CMD_TX_NOPOLL|VR_CMD_START| 1638 VR_CMD_TX_ON|VR_CMD_RX_ON| 1639 VR_CMD_RX_GO); 1640 1641 CSR_WRITE_4(sc, VR_TXADDR, vtophys(&sc->vr_ldata->vr_tx_list[0])); 1642 1643 /* 1644 * Enable interrupts. 1645 */ 1646 CSR_WRITE_2(sc, VR_ISR, 0xFFFF); 1647 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 1648 1649 mii_mediachg(mii); 1650 1651 ifp->if_flags |= IFF_RUNNING; 1652 ifp->if_flags &= ~IFF_OACTIVE; 1653 1654 sc->vr_stat_ch = timeout(vr_tick, sc, hz); 1655 1656 VR_UNLOCK(sc); 1657 1658 return; 1659} 1660 1661/* 1662 * Set media options. 1663 */ 1664static int 1665vr_ifmedia_upd(ifp) 1666 struct ifnet *ifp; 1667{ 1668 struct vr_softc *sc; 1669 1670 sc = ifp->if_softc; 1671 1672 if (ifp->if_flags & IFF_UP) 1673 vr_init(sc); 1674 1675 return(0); 1676} 1677 1678/* 1679 * Report current media status. 1680 */ 1681static void 1682vr_ifmedia_sts(ifp, ifmr) 1683 struct ifnet *ifp; 1684 struct ifmediareq *ifmr; 1685{ 1686 struct vr_softc *sc; 1687 struct mii_data *mii; 1688 1689 sc = ifp->if_softc; 1690 mii = device_get_softc(sc->vr_miibus); 1691 mii_pollstat(mii); 1692 ifmr->ifm_active = mii->mii_media_active; 1693 ifmr->ifm_status = mii->mii_media_status; 1694 1695 return; 1696} 1697 1698static int 1699vr_ioctl(ifp, command, data) 1700 struct ifnet *ifp; 1701 u_long command; 1702 caddr_t data; 1703{ 1704 struct vr_softc *sc = ifp->if_softc; 1705 struct ifreq *ifr = (struct ifreq *) data; 1706 struct mii_data *mii; 1707 int error = 0; 1708 1709 VR_LOCK(sc); 1710 1711 switch(command) { 1712 case SIOCSIFFLAGS: 1713 if (ifp->if_flags & IFF_UP) { 1714 vr_init(sc); 1715 } else { 1716 if (ifp->if_flags & IFF_RUNNING) 1717 vr_stop(sc); 1718 } 1719 error = 0; 1720 break; 1721 case SIOCADDMULTI: 1722 case SIOCDELMULTI: 1723 vr_setmulti(sc); 1724 error = 0; 1725 break; 1726 case SIOCGIFMEDIA: 1727 case SIOCSIFMEDIA: 1728 mii = device_get_softc(sc->vr_miibus); 1729 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1730 break; 1731 default: 1732 error = ether_ioctl(ifp, command, data); 1733 break; 1734 } 1735 1736 VR_UNLOCK(sc); 1737 1738 return(error); 1739} 1740 1741static void 1742vr_watchdog(ifp) 1743 struct ifnet *ifp; 1744{ 1745 struct vr_softc *sc; 1746 1747 sc = ifp->if_softc; 1748 1749 VR_LOCK(sc); 1750 ifp->if_oerrors++; 1751 printf("vr%d: watchdog timeout\n", sc->vr_unit); 1752 1753 vr_stop(sc); 1754 vr_reset(sc); 1755 vr_init(sc); 1756 1757 if (ifp->if_snd.ifq_head != NULL) 1758 vr_start(ifp); 1759 1760 VR_UNLOCK(sc); 1761 1762 return; 1763} 1764 1765/* 1766 * Stop the adapter and free any mbufs allocated to the 1767 * RX and TX lists. 1768 */ 1769static void 1770vr_stop(sc) 1771 struct vr_softc *sc; 1772{ 1773 register int i; 1774 struct ifnet *ifp; 1775 1776 VR_LOCK(sc); 1777 1778 ifp = &sc->arpcom.ac_if; 1779 ifp->if_timer = 0; 1780 1781 untimeout(vr_tick, sc, sc->vr_stat_ch); 1782 1783 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_STOP); 1784 VR_CLRBIT16(sc, VR_COMMAND, (VR_CMD_RX_ON|VR_CMD_TX_ON)); 1785 CSR_WRITE_2(sc, VR_IMR, 0x0000); 1786 CSR_WRITE_4(sc, VR_TXADDR, 0x00000000); 1787 CSR_WRITE_4(sc, VR_RXADDR, 0x00000000); 1788 1789 /* 1790 * Free data in the RX lists. 1791 */ 1792 for (i = 0; i < VR_RX_LIST_CNT; i++) { 1793 if (sc->vr_cdata.vr_rx_chain[i].vr_mbuf != NULL) { 1794 m_freem(sc->vr_cdata.vr_rx_chain[i].vr_mbuf); 1795 sc->vr_cdata.vr_rx_chain[i].vr_mbuf = NULL; 1796 } 1797 } 1798 bzero((char *)&sc->vr_ldata->vr_rx_list, 1799 sizeof(sc->vr_ldata->vr_rx_list)); 1800 1801 /* 1802 * Free the TX list buffers. 1803 */ 1804 for (i = 0; i < VR_TX_LIST_CNT; i++) { 1805 if (sc->vr_cdata.vr_tx_chain[i].vr_mbuf != NULL) { 1806 m_freem(sc->vr_cdata.vr_tx_chain[i].vr_mbuf); 1807 sc->vr_cdata.vr_tx_chain[i].vr_mbuf = NULL; 1808 } 1809 } 1810 1811 bzero((char *)&sc->vr_ldata->vr_tx_list, 1812 sizeof(sc->vr_ldata->vr_tx_list)); 1813 1814 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1815 VR_UNLOCK(sc); 1816 1817 return; 1818} 1819 1820/* 1821 * Stop all chip I/O so that the kernel's probe routines don't 1822 * get confused by errant DMAs when rebooting. 1823 */ 1824static void 1825vr_shutdown(dev) 1826 device_t dev; 1827{ 1828 struct vr_softc *sc; 1829 1830 sc = device_get_softc(dev); 1831 1832 vr_stop(sc); 1833 1834 return; 1835} 1836