if_vr.c revision 105221
1254721Semaste/* 2254721Semaste * Copyright (c) 1997, 1998 3254721Semaste * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4254721Semaste * 5254721Semaste * Redistribution and use in source and binary forms, with or without 6254721Semaste * modification, are permitted provided that the following conditions 7254721Semaste * are met: 8254721Semaste * 1. Redistributions of source code must retain the above copyright 9254721Semaste * notice, this list of conditions and the following disclaimer. 10254721Semaste * 2. Redistributions in binary form must reproduce the above copyright 11254721Semaste * notice, this list of conditions and the following disclaimer in the 12254721Semaste * documentation and/or other materials provided with the distribution. 13254721Semaste * 3. All advertising materials mentioning features or use of this software 14254721Semaste * must display the following acknowledgement: 15254721Semaste * This product includes software developed by Bill Paul. 16254721Semaste * 4. Neither the name of the author nor the names of any co-contributors 17254721Semaste * may be used to endorse or promote products derived from this software 18254721Semaste * without specific prior written permission. 19254721Semaste * 20254721Semaste * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21254721Semaste * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22254721Semaste * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23254721Semaste * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24254721Semaste * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25254721Semaste * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26254721Semaste * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27254721Semaste * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28254721Semaste * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29254721Semaste * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30254721Semaste * THE POSSIBILITY OF SUCH DAMAGE. 31254721Semaste * 32254721Semaste * $FreeBSD: head/sys/dev/vr/if_vr.c 105221 2002-10-16 09:14:59Z phk $ 33254721Semaste */ 34254721Semaste 35254721Semaste/* 36254721Semaste * VIA Rhine fast ethernet PCI NIC driver 37254721Semaste * 38254721Semaste * Supports various network adapters based on the VIA Rhine 39254721Semaste * and Rhine II PCI controllers, including the D-Link DFE530TX. 40254721Semaste * Datasheets are available at http://www.via.com.tw. 41254721Semaste * 42254721Semaste * Written by Bill Paul <wpaul@ctr.columbia.edu> 43254721Semaste * Electrical Engineering Department 44254721Semaste * Columbia University, New York City 45254721Semaste */ 46254721Semaste 47254721Semaste/* 48254721Semaste * The VIA Rhine controllers are similar in some respects to the 49254721Semaste * the DEC tulip chips, except less complicated. The controller 50254721Semaste * uses an MII bus and an external physical layer interface. The 51254721Semaste * receiver has a one entry perfect filter and a 64-bit hash table 52254721Semaste * multicast filter. Transmit and receive descriptors are similar 53254721Semaste * to the tulip. 54254721Semaste * 55254721Semaste * The Rhine has a serious flaw in its transmit DMA mechanism: 56254721Semaste * transmit buffers must be longword aligned. Unfortunately, 57254721Semaste * FreeBSD doesn't guarantee that mbufs will be filled in starting 58254721Semaste * at longword boundaries, so we have to do a buffer copy before 59254721Semaste * transmission. 60254721Semaste */ 61254721Semaste 62254721Semaste#include <sys/param.h> 63254721Semaste#include <sys/systm.h> 64254721Semaste#include <sys/sockio.h> 65254721Semaste#include <sys/mbuf.h> 66254721Semaste#include <sys/malloc.h> 67254721Semaste#include <sys/kernel.h> 68254721Semaste#include <sys/socket.h> 69254721Semaste 70254721Semaste#include <net/if.h> 71254721Semaste#include <net/if_arp.h> 72254721Semaste#include <net/ethernet.h> 73254721Semaste#include <net/if_dl.h> 74254721Semaste#include <net/if_media.h> 75254721Semaste 76254721Semaste#include <net/bpf.h> 77254721Semaste 78254721Semaste#include <vm/vm.h> /* for vtophys */ 79254721Semaste#include <vm/pmap.h> /* for vtophys */ 80254721Semaste#include <machine/bus_pio.h> 81254721Semaste#include <machine/bus_memio.h> 82254721Semaste#include <machine/bus.h> 83254721Semaste#include <machine/resource.h> 84254721Semaste#include <sys/bus.h> 85254721Semaste#include <sys/rman.h> 86254721Semaste 87254721Semaste#include <dev/mii/mii.h> 88254721Semaste#include <dev/mii/miivar.h> 89254721Semaste 90254721Semaste#include <pci/pcireg.h> 91254721Semaste#include <pci/pcivar.h> 92254721Semaste 93254721Semaste#define VR_USEIOSPACE 94254721Semaste 95254721Semaste#include <pci/if_vrreg.h> 96254721Semaste 97254721SemasteMODULE_DEPEND(vr, miibus, 1, 1, 1); 98254721Semaste 99254721Semaste/* "controller miibus0" required. See GENERIC if you get errors here. */ 100254721Semaste#include "miibus_if.h" 101254721Semaste 102254721Semaste#ifndef lint 103254721Semastestatic const char rcsid[] = 104254721Semaste "$FreeBSD: head/sys/dev/vr/if_vr.c 105221 2002-10-16 09:14:59Z phk $"; 105254721Semaste#endif 106254721Semaste 107254721Semaste/* 108254721Semaste * Various supported device vendors/types and their names. 109254721Semaste */ 110254721Semastestatic struct vr_type vr_devs[] = { 111254721Semaste { VIA_VENDORID, VIA_DEVICEID_RHINE, 112254721Semaste "VIA VT3043 Rhine I 10/100BaseTX" }, 113254721Semaste { VIA_VENDORID, VIA_DEVICEID_RHINE_II, 114254721Semaste "VIA VT86C100A Rhine II 10/100BaseTX" }, 115254721Semaste { VIA_VENDORID, VIA_DEVICEID_RHINE_II_2, 116254721Semaste "VIA VT6102 Rhine II 10/100BaseTX" }, 117254721Semaste { DELTA_VENDORID, DELTA_DEVICEID_RHINE_II, 118254721Semaste "Delta Electronics Rhine II 10/100BaseTX" }, 119254721Semaste { ADDTRON_VENDORID, ADDTRON_DEVICEID_RHINE_II, 120254721Semaste "Addtron Technology Rhine II 10/100BaseTX" }, 121254721Semaste { 0, 0, NULL } 122254721Semaste}; 123254721Semaste 124254721Semastestatic int vr_probe (device_t); 125254721Semastestatic int vr_attach (device_t); 126254721Semastestatic int vr_detach (device_t); 127254721Semaste 128254721Semastestatic int vr_newbuf (struct vr_softc *, 129254721Semaste struct vr_chain_onefrag *, 130254721Semaste struct mbuf *); 131254721Semastestatic int vr_encap (struct vr_softc *, struct vr_chain *, 132254721Semaste struct mbuf * ); 133254721Semaste 134254721Semastestatic void vr_rxeof (struct vr_softc *); 135254721Semastestatic void vr_rxeoc (struct vr_softc *); 136254721Semastestatic void vr_txeof (struct vr_softc *); 137254721Semastestatic void vr_txeoc (struct vr_softc *); 138254721Semastestatic void vr_tick (void *); 139254721Semastestatic void vr_intr (void *); 140254721Semastestatic void vr_start (struct ifnet *); 141254721Semastestatic int vr_ioctl (struct ifnet *, u_long, caddr_t); 142254721Semastestatic void vr_init (void *); 143254721Semastestatic void vr_stop (struct vr_softc *); 144254721Semastestatic void vr_watchdog (struct ifnet *); 145254721Semastestatic void vr_shutdown (device_t); 146254721Semastestatic int vr_ifmedia_upd (struct ifnet *); 147254721Semastestatic void vr_ifmedia_sts (struct ifnet *, struct ifmediareq *); 148254721Semaste 149254721Semastestatic void vr_mii_sync (struct vr_softc *); 150254721Semastestatic void vr_mii_send (struct vr_softc *, u_int32_t, int); 151254721Semastestatic int vr_mii_readreg (struct vr_softc *, struct vr_mii_frame *); 152254721Semastestatic int vr_mii_writereg (struct vr_softc *, struct vr_mii_frame *); 153254721Semastestatic int vr_miibus_readreg (device_t, int, int); 154254721Semastestatic int vr_miibus_writereg (device_t, int, int, int); 155254721Semastestatic void vr_miibus_statchg (device_t); 156254721Semaste 157254721Semastestatic void vr_setcfg (struct vr_softc *, int); 158254721Semastestatic u_int8_t vr_calchash (u_int8_t *); 159254721Semastestatic void vr_setmulti (struct vr_softc *); 160254721Semastestatic void vr_reset (struct vr_softc *); 161254721Semastestatic int vr_list_rx_init (struct vr_softc *); 162254721Semastestatic int vr_list_tx_init (struct vr_softc *); 163254721Semaste 164254721Semaste#ifdef VR_USEIOSPACE 165254721Semaste#define VR_RES SYS_RES_IOPORT 166254721Semaste#define VR_RID VR_PCI_LOIO 167254721Semaste#else 168254721Semaste#define VR_RES SYS_RES_MEMORY 169254721Semaste#define VR_RID VR_PCI_LOMEM 170254721Semaste#endif 171254721Semaste 172254721Semastestatic device_method_t vr_methods[] = { 173254721Semaste /* Device interface */ 174254721Semaste DEVMETHOD(device_probe, vr_probe), 175254721Semaste DEVMETHOD(device_attach, vr_attach), 176254721Semaste DEVMETHOD(device_detach, vr_detach), 177254721Semaste DEVMETHOD(device_shutdown, vr_shutdown), 178254721Semaste 179254721Semaste /* bus interface */ 180254721Semaste DEVMETHOD(bus_print_child, bus_generic_print_child), 181254721Semaste DEVMETHOD(bus_driver_added, bus_generic_driver_added), 182254721Semaste 183254721Semaste /* MII interface */ 184254721Semaste DEVMETHOD(miibus_readreg, vr_miibus_readreg), 185254721Semaste DEVMETHOD(miibus_writereg, vr_miibus_writereg), 186254721Semaste DEVMETHOD(miibus_statchg, vr_miibus_statchg), 187254721Semaste 188254721Semaste { 0, 0 } 189254721Semaste}; 190254721Semaste 191254721Semastestatic driver_t vr_driver = { 192254721Semaste "vr", 193254721Semaste vr_methods, 194254721Semaste sizeof(struct vr_softc) 195254721Semaste}; 196254721Semaste 197254721Semastestatic devclass_t vr_devclass; 198254721Semaste 199254721SemasteDRIVER_MODULE(if_vr, pci, vr_driver, vr_devclass, 0, 0); 200254721SemasteDRIVER_MODULE(miibus, vr, miibus_driver, miibus_devclass, 0, 0); 201254721Semaste 202254721Semaste#define VR_SETBIT(sc, reg, x) \ 203254721Semaste CSR_WRITE_1(sc, reg, \ 204254721Semaste CSR_READ_1(sc, reg) | (x)) 205254721Semaste 206254721Semaste#define VR_CLRBIT(sc, reg, x) \ 207254721Semaste CSR_WRITE_1(sc, reg, \ 208254721Semaste CSR_READ_1(sc, reg) & ~(x)) 209254721Semaste 210254721Semaste#define VR_SETBIT16(sc, reg, x) \ 211254721Semaste CSR_WRITE_2(sc, reg, \ 212254721Semaste CSR_READ_2(sc, reg) | (x)) 213254721Semaste 214254721Semaste#define VR_CLRBIT16(sc, reg, x) \ 215254721Semaste CSR_WRITE_2(sc, reg, \ 216254721Semaste CSR_READ_2(sc, reg) & ~(x)) 217254721Semaste 218254721Semaste#define VR_SETBIT32(sc, reg, x) \ 219254721Semaste CSR_WRITE_4(sc, reg, \ 220254721Semaste CSR_READ_4(sc, reg) | (x)) 221254721Semaste 222254721Semaste#define VR_CLRBIT32(sc, reg, x) \ 223254721Semaste CSR_WRITE_4(sc, reg, \ 224254721Semaste CSR_READ_4(sc, reg) & ~(x)) 225254721Semaste 226254721Semaste#define SIO_SET(x) \ 227254721Semaste CSR_WRITE_1(sc, VR_MIICMD, \ 228254721Semaste CSR_READ_1(sc, VR_MIICMD) | (x)) 229254721Semaste 230254721Semaste#define SIO_CLR(x) \ 231254721Semaste CSR_WRITE_1(sc, VR_MIICMD, \ 232254721Semaste CSR_READ_1(sc, VR_MIICMD) & ~(x)) 233254721Semaste 234254721Semaste/* 235254721Semaste * Sync the PHYs by setting data bit and strobing the clock 32 times. 236254721Semaste */ 237254721Semastestatic void 238254721Semastevr_mii_sync(sc) 239254721Semaste struct vr_softc *sc; 240254721Semaste{ 241254721Semaste register int i; 242254721Semaste 243254721Semaste SIO_SET(VR_MIICMD_DIR|VR_MIICMD_DATAIN); 244254721Semaste 245254721Semaste for (i = 0; i < 32; i++) { 246254721Semaste SIO_SET(VR_MIICMD_CLK); 247254721Semaste DELAY(1); 248254721Semaste SIO_CLR(VR_MIICMD_CLK); 249254721Semaste DELAY(1); 250254721Semaste } 251254721Semaste 252254721Semaste return; 253254721Semaste} 254254721Semaste 255254721Semaste/* 256254721Semaste * Clock a series of bits through the MII. 257254721Semaste */ 258254721Semastestatic void 259254721Semastevr_mii_send(sc, bits, cnt) 260254721Semaste struct vr_softc *sc; 261254721Semaste u_int32_t bits; 262254721Semaste int cnt; 263254721Semaste{ 264254721Semaste int i; 265254721Semaste 266254721Semaste SIO_CLR(VR_MIICMD_CLK); 267254721Semaste 268254721Semaste for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 269254721Semaste if (bits & i) { 270254721Semaste SIO_SET(VR_MIICMD_DATAIN); 271254721Semaste } else { 272254721Semaste SIO_CLR(VR_MIICMD_DATAIN); 273254721Semaste } 274254721Semaste DELAY(1); 275254721Semaste SIO_CLR(VR_MIICMD_CLK); 276254721Semaste DELAY(1); 277254721Semaste SIO_SET(VR_MIICMD_CLK); 278254721Semaste } 279254721Semaste} 280254721Semaste 281254721Semaste/* 282254721Semaste * Read an PHY register through the MII. 283254721Semaste */ 284254721Semastestatic int 285254721Semastevr_mii_readreg(sc, frame) 286254721Semaste struct vr_softc *sc; 287254721Semaste struct vr_mii_frame *frame; 288254721Semaste 289254721Semaste{ 290254721Semaste int i, ack; 291254721Semaste 292254721Semaste VR_LOCK(sc); 293254721Semaste 294254721Semaste /* 295254721Semaste * Set up frame for RX. 296254721Semaste */ 297254721Semaste frame->mii_stdelim = VR_MII_STARTDELIM; 298254721Semaste frame->mii_opcode = VR_MII_READOP; 299254721Semaste frame->mii_turnaround = 0; 300254721Semaste frame->mii_data = 0; 301254721Semaste 302254721Semaste CSR_WRITE_1(sc, VR_MIICMD, 0); 303254721Semaste VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM); 304254721Semaste 305254721Semaste /* 306254721Semaste * Turn on data xmit. 307254721Semaste */ 308254721Semaste SIO_SET(VR_MIICMD_DIR); 309254721Semaste 310254721Semaste vr_mii_sync(sc); 311254721Semaste 312254721Semaste /* 313254721Semaste * Send command/address info. 314254721Semaste */ 315254721Semaste vr_mii_send(sc, frame->mii_stdelim, 2); 316254721Semaste vr_mii_send(sc, frame->mii_opcode, 2); 317254721Semaste vr_mii_send(sc, frame->mii_phyaddr, 5); 318254721Semaste vr_mii_send(sc, frame->mii_regaddr, 5); 319254721Semaste 320254721Semaste /* Idle bit */ 321254721Semaste SIO_CLR((VR_MIICMD_CLK|VR_MIICMD_DATAIN)); 322254721Semaste DELAY(1); 323254721Semaste SIO_SET(VR_MIICMD_CLK); 324254721Semaste DELAY(1); 325254721Semaste 326254721Semaste /* Turn off xmit. */ 327254721Semaste SIO_CLR(VR_MIICMD_DIR); 328254721Semaste 329254721Semaste /* Check for ack */ 330254721Semaste SIO_CLR(VR_MIICMD_CLK); 331254721Semaste DELAY(1); 332254721Semaste SIO_SET(VR_MIICMD_CLK); 333254721Semaste DELAY(1); 334254721Semaste ack = CSR_READ_4(sc, VR_MIICMD) & VR_MIICMD_DATAOUT; 335254721Semaste 336254721Semaste /* 337254721Semaste * Now try reading data bits. If the ack failed, we still 338254721Semaste * need to clock through 16 cycles to keep the PHY(s) in sync. 339254721Semaste */ 340254721Semaste if (ack) { 341254721Semaste for(i = 0; i < 16; i++) { 342254721Semaste SIO_CLR(VR_MIICMD_CLK); 343254721Semaste DELAY(1); 344254721Semaste SIO_SET(VR_MIICMD_CLK); 345254721Semaste DELAY(1); 346254721Semaste } 347254721Semaste goto fail; 348254721Semaste } 349254721Semaste 350254721Semaste for (i = 0x8000; i; i >>= 1) { 351254721Semaste SIO_CLR(VR_MIICMD_CLK); 352254721Semaste DELAY(1); 353254721Semaste if (!ack) { 354254721Semaste if (CSR_READ_4(sc, VR_MIICMD) & VR_MIICMD_DATAOUT) 355254721Semaste frame->mii_data |= i; 356254721Semaste DELAY(1); 357254721Semaste } 358254721Semaste SIO_SET(VR_MIICMD_CLK); 359254721Semaste DELAY(1); 360254721Semaste } 361254721Semaste 362254721Semastefail: 363254721Semaste 364254721Semaste SIO_CLR(VR_MIICMD_CLK); 365254721Semaste DELAY(1); 366254721Semaste SIO_SET(VR_MIICMD_CLK); 367254721Semaste DELAY(1); 368254721Semaste 369254721Semaste VR_UNLOCK(sc); 370254721Semaste 371254721Semaste if (ack) 372254721Semaste return(1); 373254721Semaste return(0); 374254721Semaste} 375254721Semaste 376254721Semaste/* 377254721Semaste * Write to a PHY register through the MII. 378254721Semaste */ 379254721Semastestatic int 380254721Semastevr_mii_writereg(sc, frame) 381254721Semaste struct vr_softc *sc; 382254721Semaste struct vr_mii_frame *frame; 383254721Semaste 384254721Semaste{ 385254721Semaste VR_LOCK(sc); 386254721Semaste 387254721Semaste CSR_WRITE_1(sc, VR_MIICMD, 0); 388254721Semaste VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM); 389254721Semaste 390254721Semaste /* 391254721Semaste * Set up frame for TX. 392254721Semaste */ 393254721Semaste 394254721Semaste frame->mii_stdelim = VR_MII_STARTDELIM; 395254721Semaste frame->mii_opcode = VR_MII_WRITEOP; 396254721Semaste frame->mii_turnaround = VR_MII_TURNAROUND; 397254721Semaste 398254721Semaste /* 399254721Semaste * Turn on data output. 400254721Semaste */ 401254721Semaste SIO_SET(VR_MIICMD_DIR); 402254721Semaste 403254721Semaste vr_mii_sync(sc); 404254721Semaste 405254721Semaste vr_mii_send(sc, frame->mii_stdelim, 2); 406254721Semaste vr_mii_send(sc, frame->mii_opcode, 2); 407254721Semaste vr_mii_send(sc, frame->mii_phyaddr, 5); 408254721Semaste vr_mii_send(sc, frame->mii_regaddr, 5); 409254721Semaste vr_mii_send(sc, frame->mii_turnaround, 2); 410254721Semaste vr_mii_send(sc, frame->mii_data, 16); 411254721Semaste 412254721Semaste /* Idle bit. */ 413254721Semaste SIO_SET(VR_MIICMD_CLK); 414254721Semaste DELAY(1); 415254721Semaste SIO_CLR(VR_MIICMD_CLK); 416254721Semaste DELAY(1); 417254721Semaste 418254721Semaste /* 419254721Semaste * Turn off xmit. 420254721Semaste */ 421254721Semaste SIO_CLR(VR_MIICMD_DIR); 422254721Semaste 423254721Semaste VR_UNLOCK(sc); 424254721Semaste 425254721Semaste return(0); 426254721Semaste} 427254721Semaste 428254721Semastestatic int 429254721Semastevr_miibus_readreg(dev, phy, reg) 430254721Semaste device_t dev; 431254721Semaste int phy, reg; 432254721Semaste{ 433254721Semaste struct vr_softc *sc; 434254721Semaste struct vr_mii_frame frame; 435254721Semaste 436254721Semaste sc = device_get_softc(dev); 437254721Semaste bzero((char *)&frame, sizeof(frame)); 438254721Semaste 439254721Semaste frame.mii_phyaddr = phy; 440254721Semaste frame.mii_regaddr = reg; 441254721Semaste vr_mii_readreg(sc, &frame); 442254721Semaste 443254721Semaste return(frame.mii_data); 444254721Semaste} 445254721Semaste 446254721Semastestatic int 447254721Semastevr_miibus_writereg(dev, phy, reg, data) 448254721Semaste device_t dev; 449254721Semaste u_int16_t phy, reg, data; 450254721Semaste{ 451254721Semaste struct vr_softc *sc; 452254721Semaste struct vr_mii_frame frame; 453254721Semaste 454254721Semaste sc = device_get_softc(dev); 455254721Semaste bzero((char *)&frame, sizeof(frame)); 456254721Semaste 457254721Semaste frame.mii_phyaddr = phy; 458254721Semaste frame.mii_regaddr = reg; 459254721Semaste frame.mii_data = data; 460254721Semaste 461254721Semaste vr_mii_writereg(sc, &frame); 462254721Semaste 463254721Semaste return(0); 464254721Semaste} 465254721Semaste 466254721Semastestatic void 467254721Semastevr_miibus_statchg(dev) 468254721Semaste device_t dev; 469254721Semaste{ 470254721Semaste struct vr_softc *sc; 471254721Semaste struct mii_data *mii; 472254721Semaste 473254721Semaste sc = device_get_softc(dev); 474254721Semaste VR_LOCK(sc); 475254721Semaste mii = device_get_softc(sc->vr_miibus); 476254721Semaste vr_setcfg(sc, mii->mii_media_active); 477254721Semaste VR_UNLOCK(sc); 478254721Semaste 479254721Semaste return; 480254721Semaste} 481254721Semaste 482254721Semaste/* 483254721Semaste * Calculate CRC of a multicast group address, return the lower 6 bits. 484254721Semaste */ 485254721Semastestatic u_int8_t vr_calchash(addr) 486254721Semaste u_int8_t *addr; 487254721Semaste{ 488254721Semaste u_int32_t crc, carry; 489254721Semaste int i, j; 490254721Semaste u_int8_t c; 491254721Semaste 492254721Semaste /* Compute CRC for the address value. */ 493254721Semaste crc = 0xFFFFFFFF; /* initial value */ 494254721Semaste 495254721Semaste for (i = 0; i < 6; i++) { 496254721Semaste c = *(addr + i); 497254721Semaste for (j = 0; j < 8; j++) { 498254721Semaste carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 499254721Semaste crc <<= 1; 500254721Semaste c >>= 1; 501254721Semaste if (carry) 502254721Semaste crc = (crc ^ 0x04c11db6) | carry; 503254721Semaste } 504254721Semaste } 505254721Semaste 506254721Semaste /* return the filter bit position */ 507254721Semaste return((crc >> 26) & 0x0000003F); 508254721Semaste} 509254721Semaste 510254721Semaste/* 511254721Semaste * Program the 64-bit multicast hash filter. 512254721Semaste */ 513254721Semastestatic void 514254721Semastevr_setmulti(sc) 515254721Semaste struct vr_softc *sc; 516254721Semaste{ 517254721Semaste struct ifnet *ifp; 518254721Semaste int h = 0; 519254721Semaste u_int32_t hashes[2] = { 0, 0 }; 520254721Semaste struct ifmultiaddr *ifma; 521254721Semaste u_int8_t rxfilt; 522254721Semaste int mcnt = 0; 523254721Semaste 524254721Semaste ifp = &sc->arpcom.ac_if; 525254721Semaste 526254721Semaste rxfilt = CSR_READ_1(sc, VR_RXCFG); 527254721Semaste 528254721Semaste if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 529254721Semaste rxfilt |= VR_RXCFG_RX_MULTI; 530254721Semaste CSR_WRITE_1(sc, VR_RXCFG, rxfilt); 531254721Semaste CSR_WRITE_4(sc, VR_MAR0, 0xFFFFFFFF); 532254721Semaste CSR_WRITE_4(sc, VR_MAR1, 0xFFFFFFFF); 533254721Semaste return; 534254721Semaste } 535254721Semaste 536254721Semaste /* first, zot all the existing hash bits */ 537254721Semaste CSR_WRITE_4(sc, VR_MAR0, 0); 538254721Semaste CSR_WRITE_4(sc, VR_MAR1, 0); 539254721Semaste 540254721Semaste /* now program new ones */ 541254721Semaste TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 542254721Semaste if (ifma->ifma_addr->sa_family != AF_LINK) 543254721Semaste continue; 544254721Semaste h = vr_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 545254721Semaste if (h < 32) 546254721Semaste hashes[0] |= (1 << h); 547254721Semaste else 548254721Semaste hashes[1] |= (1 << (h - 32)); 549254721Semaste mcnt++; 550254721Semaste } 551254721Semaste 552254721Semaste if (mcnt) 553254721Semaste rxfilt |= VR_RXCFG_RX_MULTI; 554254721Semaste else 555254721Semaste rxfilt &= ~VR_RXCFG_RX_MULTI; 556254721Semaste 557254721Semaste CSR_WRITE_4(sc, VR_MAR0, hashes[0]); 558254721Semaste CSR_WRITE_4(sc, VR_MAR1, hashes[1]); 559254721Semaste CSR_WRITE_1(sc, VR_RXCFG, rxfilt); 560254721Semaste 561254721Semaste return; 562254721Semaste} 563254721Semaste 564254721Semaste/* 565254721Semaste * In order to fiddle with the 566254721Semaste * 'full-duplex' and '100Mbps' bits in the netconfig register, we 567254721Semaste * first have to put the transmit and/or receive logic in the idle state. 568254721Semaste */ 569254721Semastestatic void 570254721Semastevr_setcfg(sc, media) 571254721Semaste struct vr_softc *sc; 572254721Semaste int media; 573254721Semaste{ 574254721Semaste int restart = 0; 575254721Semaste 576254721Semaste if (CSR_READ_2(sc, VR_COMMAND) & (VR_CMD_TX_ON|VR_CMD_RX_ON)) { 577254721Semaste restart = 1; 578254721Semaste VR_CLRBIT16(sc, VR_COMMAND, (VR_CMD_TX_ON|VR_CMD_RX_ON)); 579254721Semaste } 580254721Semaste 581254721Semaste if ((media & IFM_GMASK) == IFM_FDX) 582254721Semaste VR_SETBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX); 583254721Semaste else 584254721Semaste VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX); 585254721Semaste 586254721Semaste if (restart) 587254721Semaste VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_ON|VR_CMD_RX_ON); 588254721Semaste 589254721Semaste return; 590254721Semaste} 591254721Semaste 592254721Semastestatic void 593254721Semastevr_reset(sc) 594254721Semaste struct vr_softc *sc; 595254721Semaste{ 596254721Semaste register int i; 597254721Semaste 598254721Semaste VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RESET); 599254721Semaste 600254721Semaste for (i = 0; i < VR_TIMEOUT; i++) { 601254721Semaste DELAY(10); 602254721Semaste if (!(CSR_READ_2(sc, VR_COMMAND) & VR_CMD_RESET)) 603254721Semaste break; 604254721Semaste } 605254721Semaste if (i == VR_TIMEOUT) 606254721Semaste printf("vr%d: reset never completed!\n", sc->vr_unit); 607254721Semaste 608254721Semaste /* Wait a little while for the chip to get its brains in order. */ 609254721Semaste DELAY(1000); 610254721Semaste 611254721Semaste return; 612254721Semaste} 613254721Semaste 614254721Semaste/* 615254721Semaste * Probe for a VIA Rhine chip. Check the PCI vendor and device 616254721Semaste * IDs against our list and return a device name if we find a match. 617254721Semaste */ 618254721Semastestatic int 619254721Semastevr_probe(dev) 620254721Semaste device_t dev; 621254721Semaste{ 622254721Semaste struct vr_type *t; 623254721Semaste 624254721Semaste t = vr_devs; 625254721Semaste 626254721Semaste while(t->vr_name != NULL) { 627254721Semaste if ((pci_get_vendor(dev) == t->vr_vid) && 628254721Semaste (pci_get_device(dev) == t->vr_did)) { 629254721Semaste device_set_desc(dev, t->vr_name); 630254721Semaste return(0); 631254721Semaste } 632254721Semaste t++; 633254721Semaste } 634254721Semaste 635254721Semaste return(ENXIO); 636254721Semaste} 637254721Semaste 638254721Semaste/* 639254721Semaste * Attach the interface. Allocate softc structures, do ifmedia 640254721Semaste * setup and ethernet/BPF attach. 641254721Semaste */ 642254721Semastestatic int 643254721Semastevr_attach(dev) 644254721Semaste device_t dev; 645254721Semaste{ 646254721Semaste int i; 647254721Semaste u_char eaddr[ETHER_ADDR_LEN]; 648254721Semaste u_int32_t command; 649254721Semaste struct vr_softc *sc; 650254721Semaste struct ifnet *ifp; 651254721Semaste int unit, error = 0, rid; 652254721Semaste 653254721Semaste sc = device_get_softc(dev); 654254721Semaste unit = device_get_unit(dev); 655254721Semaste bzero(sc, sizeof(struct vr_softc *)); 656254721Semaste 657254721Semaste mtx_init(&sc->vr_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 658254721Semaste MTX_DEF | MTX_RECURSE); 659254721Semaste VR_LOCK(sc); 660254721Semaste 661254721Semaste /* 662254721Semaste * Handle power management nonsense. 663254721Semaste */ 664254721Semaste if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 665254721Semaste u_int32_t iobase, membase, irq; 666254721Semaste 667254721Semaste /* Save important PCI config data. */ 668254721Semaste iobase = pci_read_config(dev, VR_PCI_LOIO, 4); 669254721Semaste membase = pci_read_config(dev, VR_PCI_LOMEM, 4); 670254721Semaste irq = pci_read_config(dev, VR_PCI_INTLINE, 4); 671254721Semaste 672254721Semaste /* Reset the power state. */ 673254721Semaste printf("vr%d: chip is in D%d power mode " 674254721Semaste "-- setting to D0\n", unit, 675254721Semaste pci_get_powerstate(dev)); 676254721Semaste pci_set_powerstate(dev, PCI_POWERSTATE_D0); 677254721Semaste 678254721Semaste /* Restore PCI config data. */ 679254721Semaste pci_write_config(dev, VR_PCI_LOIO, iobase, 4); 680254721Semaste pci_write_config(dev, VR_PCI_LOMEM, membase, 4); 681254721Semaste pci_write_config(dev, VR_PCI_INTLINE, irq, 4); 682254721Semaste } 683254721Semaste 684254721Semaste /* 685254721Semaste * Map control/status registers. 686254721Semaste */ 687254721Semaste pci_enable_busmaster(dev); 688254721Semaste pci_enable_io(dev, SYS_RES_IOPORT); 689254721Semaste pci_enable_io(dev, SYS_RES_MEMORY); 690254721Semaste command = pci_read_config(dev, PCIR_COMMAND, 4); 691254721Semaste 692254721Semaste#ifdef VR_USEIOSPACE 693254721Semaste if (!(command & PCIM_CMD_PORTEN)) { 694254721Semaste printf("vr%d: failed to enable I/O ports!\n", unit); 695254721Semaste free(sc, M_DEVBUF); 696254721Semaste goto fail; 697254721Semaste } 698254721Semaste#else 699254721Semaste if (!(command & PCIM_CMD_MEMEN)) { 700254721Semaste printf("vr%d: failed to enable memory mapping!\n", unit); 701254721Semaste goto fail; 702254721Semaste } 703254721Semaste#endif 704254721Semaste 705254721Semaste rid = VR_RID; 706254721Semaste sc->vr_res = bus_alloc_resource(dev, VR_RES, &rid, 707254721Semaste 0, ~0, 1, RF_ACTIVE); 708254721Semaste 709254721Semaste if (sc->vr_res == NULL) { 710254721Semaste printf("vr%d: couldn't map ports/memory\n", unit); 711254721Semaste error = ENXIO; 712254721Semaste goto fail; 713254721Semaste } 714254721Semaste 715254721Semaste sc->vr_btag = rman_get_bustag(sc->vr_res); 716254721Semaste sc->vr_bhandle = rman_get_bushandle(sc->vr_res); 717254721Semaste 718254721Semaste /* Allocate interrupt */ 719254721Semaste rid = 0; 720254721Semaste sc->vr_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 721254721Semaste RF_SHAREABLE | RF_ACTIVE); 722254721Semaste 723254721Semaste if (sc->vr_irq == NULL) { 724254721Semaste printf("vr%d: couldn't map interrupt\n", unit); 725254721Semaste bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res); 726254721Semaste error = ENXIO; 727254721Semaste goto fail; 728254721Semaste } 729254721Semaste 730254721Semaste error = bus_setup_intr(dev, sc->vr_irq, INTR_TYPE_NET, 731254721Semaste vr_intr, sc, &sc->vr_intrhand); 732254721Semaste 733254721Semaste if (error) { 734254721Semaste bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq); 735254721Semaste bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res); 736254721Semaste printf("vr%d: couldn't set up irq\n", unit); 737254721Semaste goto fail; 738254721Semaste } 739254721Semaste 740254721Semaste /* 741254721Semaste * Windows may put the chip in suspend mode when it 742254721Semaste * shuts down. Be sure to kick it in the head to wake it 743254721Semaste * up again. 744254721Semaste */ 745254721Semaste VR_CLRBIT(sc, VR_STICKHW, (VR_STICKHW_DS0|VR_STICKHW_DS1)); 746254721Semaste 747254721Semaste /* Reset the adapter. */ 748254721Semaste vr_reset(sc); 749254721Semaste 750254721Semaste /* 751254721Semaste * Get station address. The way the Rhine chips work, 752254721Semaste * you're not allowed to directly access the EEPROM once 753254721Semaste * they've been programmed a special way. Consequently, 754254721Semaste * we need to read the node address from the PAR0 and PAR1 755254721Semaste * registers. 756254721Semaste */ 757254721Semaste VR_SETBIT(sc, VR_EECSR, VR_EECSR_LOAD); 758254721Semaste DELAY(200); 759254721Semaste for (i = 0; i < ETHER_ADDR_LEN; i++) 760254721Semaste eaddr[i] = CSR_READ_1(sc, VR_PAR0 + i); 761254721Semaste 762254721Semaste /* 763254721Semaste * A Rhine chip was detected. Inform the world. 764254721Semaste */ 765254721Semaste printf("vr%d: Ethernet address: %6D\n", unit, eaddr, ":"); 766254721Semaste 767254721Semaste sc->vr_unit = unit; 768254721Semaste bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 769254721Semaste 770254721Semaste sc->vr_ldata = contigmalloc(sizeof(struct vr_list_data), M_DEVBUF, 771254721Semaste M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 772254721Semaste 773254721Semaste if (sc->vr_ldata == NULL) { 774254721Semaste printf("vr%d: no memory for list buffers!\n", unit); 775254721Semaste bus_teardown_intr(dev, sc->vr_irq, sc->vr_intrhand); 776254721Semaste bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq); 777254721Semaste bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res); 778254721Semaste error = ENXIO; 779254721Semaste goto fail; 780254721Semaste } 781254721Semaste 782254721Semaste bzero(sc->vr_ldata, sizeof(struct vr_list_data)); 783254721Semaste 784254721Semaste ifp = &sc->arpcom.ac_if; 785254721Semaste ifp->if_softc = sc; 786254721Semaste ifp->if_unit = unit; 787254721Semaste ifp->if_name = "vr"; 788254721Semaste ifp->if_mtu = ETHERMTU; 789254721Semaste ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 790254721Semaste ifp->if_ioctl = vr_ioctl; 791254721Semaste ifp->if_output = ether_output; 792254721Semaste ifp->if_start = vr_start; 793254721Semaste ifp->if_watchdog = vr_watchdog; 794254721Semaste ifp->if_init = vr_init; 795254721Semaste ifp->if_baudrate = 10000000; 796254721Semaste ifp->if_snd.ifq_maxlen = VR_TX_LIST_CNT - 1; 797254721Semaste 798254721Semaste /* 799254721Semaste * Do MII setup. 800254721Semaste */ 801254721Semaste if (mii_phy_probe(dev, &sc->vr_miibus, 802254721Semaste vr_ifmedia_upd, vr_ifmedia_sts)) { 803254721Semaste printf("vr%d: MII without any phy!\n", sc->vr_unit); 804254721Semaste bus_teardown_intr(dev, sc->vr_irq, sc->vr_intrhand); 805254721Semaste bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq); 806254721Semaste bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res); 807254721Semaste contigfree(sc->vr_ldata, 808254721Semaste sizeof(struct vr_list_data), M_DEVBUF); 809254721Semaste error = ENXIO; 810254721Semaste goto fail; 811254721Semaste } 812254721Semaste 813254721Semaste callout_handle_init(&sc->vr_stat_ch); 814254721Semaste 815254721Semaste /* 816254721Semaste * Call MI attach routine. 817254721Semaste */ 818254721Semaste ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 819254721Semaste VR_UNLOCK(sc); 820254721Semaste return(0); 821254721Semaste 822254721Semastefail: 823254721Semaste VR_UNLOCK(sc); 824254721Semaste mtx_destroy(&sc->vr_mtx); 825254721Semaste 826254721Semaste return(error); 827254721Semaste} 828254721Semaste 829254721Semastestatic int 830254721Semastevr_detach(dev) 831254721Semaste device_t dev; 832254721Semaste{ 833254721Semaste struct vr_softc *sc; 834254721Semaste struct ifnet *ifp; 835254721Semaste 836254721Semaste sc = device_get_softc(dev); 837254721Semaste VR_LOCK(sc); 838254721Semaste ifp = &sc->arpcom.ac_if; 839254721Semaste 840254721Semaste vr_stop(sc); 841254721Semaste ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 842254721Semaste 843254721Semaste bus_generic_detach(dev); 844254721Semaste device_delete_child(dev, sc->vr_miibus); 845254721Semaste 846254721Semaste bus_teardown_intr(dev, sc->vr_irq, sc->vr_intrhand); 847254721Semaste bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq); 848254721Semaste bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res); 849254721Semaste 850254721Semaste contigfree(sc->vr_ldata, sizeof(struct vr_list_data), M_DEVBUF); 851254721Semaste 852254721Semaste VR_UNLOCK(sc); 853254721Semaste mtx_destroy(&sc->vr_mtx); 854254721Semaste 855254721Semaste return(0); 856254721Semaste} 857254721Semaste 858254721Semaste/* 859254721Semaste * Initialize the transmit descriptors. 860254721Semaste */ 861254721Semastestatic int 862254721Semastevr_list_tx_init(sc) 863254721Semaste struct vr_softc *sc; 864254721Semaste{ 865254721Semaste struct vr_chain_data *cd; 866254721Semaste struct vr_list_data *ld; 867254721Semaste int i; 868254721Semaste 869254721Semaste cd = &sc->vr_cdata; 870254721Semaste ld = sc->vr_ldata; 871254721Semaste for (i = 0; i < VR_TX_LIST_CNT; i++) { 872254721Semaste cd->vr_tx_chain[i].vr_ptr = &ld->vr_tx_list[i]; 873254721Semaste if (i == (VR_TX_LIST_CNT - 1)) 874254721Semaste cd->vr_tx_chain[i].vr_nextdesc = 875254721Semaste &cd->vr_tx_chain[0]; 876254721Semaste else 877254721Semaste cd->vr_tx_chain[i].vr_nextdesc = 878254721Semaste &cd->vr_tx_chain[i + 1]; 879254721Semaste } 880254721Semaste 881254721Semaste cd->vr_tx_free = &cd->vr_tx_chain[0]; 882254721Semaste cd->vr_tx_tail = cd->vr_tx_head = NULL; 883254721Semaste 884254721Semaste return(0); 885254721Semaste} 886254721Semaste 887254721Semaste 888254721Semaste/* 889254721Semaste * Initialize the RX descriptors and allocate mbufs for them. Note that 890254721Semaste * we arrange the descriptors in a closed ring, so that the last descriptor 891254721Semaste * points back to the first. 892254721Semaste */ 893254721Semastestatic int 894254721Semastevr_list_rx_init(sc) 895254721Semaste struct vr_softc *sc; 896254721Semaste{ 897254721Semaste struct vr_chain_data *cd; 898254721Semaste struct vr_list_data *ld; 899254721Semaste int i; 900254721Semaste 901254721Semaste cd = &sc->vr_cdata; 902254721Semaste ld = sc->vr_ldata; 903254721Semaste 904254721Semaste for (i = 0; i < VR_RX_LIST_CNT; i++) { 905254721Semaste cd->vr_rx_chain[i].vr_ptr = 906254721Semaste (struct vr_desc *)&ld->vr_rx_list[i]; 907254721Semaste if (vr_newbuf(sc, &cd->vr_rx_chain[i], NULL) == ENOBUFS) 908254721Semaste return(ENOBUFS); 909254721Semaste if (i == (VR_RX_LIST_CNT - 1)) { 910254721Semaste cd->vr_rx_chain[i].vr_nextdesc = 911254721Semaste &cd->vr_rx_chain[0]; 912254721Semaste ld->vr_rx_list[i].vr_next = 913254721Semaste vtophys(&ld->vr_rx_list[0]); 914254721Semaste } else { 915254721Semaste cd->vr_rx_chain[i].vr_nextdesc = 916254721Semaste &cd->vr_rx_chain[i + 1]; 917254721Semaste ld->vr_rx_list[i].vr_next = 918254721Semaste vtophys(&ld->vr_rx_list[i + 1]); 919254721Semaste } 920254721Semaste } 921254721Semaste 922254721Semaste cd->vr_rx_head = &cd->vr_rx_chain[0]; 923254721Semaste 924254721Semaste return(0); 925254721Semaste} 926254721Semaste 927254721Semaste/* 928254721Semaste * Initialize an RX descriptor and attach an MBUF cluster. 929254721Semaste * Note: the length fields are only 11 bits wide, which means the 930254721Semaste * largest size we can specify is 2047. This is important because 931254721Semaste * MCLBYTES is 2048, so we have to subtract one otherwise we'll 932254721Semaste * overflow the field and make a mess. 933254721Semaste */ 934254721Semastestatic int 935254721Semastevr_newbuf(sc, c, m) 936254721Semaste struct vr_softc *sc; 937254721Semaste struct vr_chain_onefrag *c; 938254721Semaste struct mbuf *m; 939254721Semaste{ 940254721Semaste struct mbuf *m_new = NULL; 941254721Semaste 942254721Semaste if (m == NULL) { 943254721Semaste MGETHDR(m_new, M_DONTWAIT, MT_DATA); 944254721Semaste if (m_new == NULL) 945254721Semaste return(ENOBUFS); 946254721Semaste 947254721Semaste MCLGET(m_new, M_DONTWAIT); 948254721Semaste if (!(m_new->m_flags & M_EXT)) { 949254721Semaste m_freem(m_new); 950254721Semaste return(ENOBUFS); 951254721Semaste } 952254721Semaste m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 953254721Semaste } else { 954254721Semaste m_new = m; 955254721Semaste m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 956254721Semaste m_new->m_data = m_new->m_ext.ext_buf; 957254721Semaste } 958254721Semaste 959254721Semaste m_adj(m_new, sizeof(u_int64_t)); 960254721Semaste 961254721Semaste c->vr_mbuf = m_new; 962254721Semaste c->vr_ptr->vr_status = VR_RXSTAT; 963254721Semaste c->vr_ptr->vr_data = vtophys(mtod(m_new, caddr_t)); 964254721Semaste c->vr_ptr->vr_ctl = VR_RXCTL | VR_RXLEN; 965254721Semaste 966254721Semaste return(0); 967254721Semaste} 968254721Semaste 969254721Semaste/* 970254721Semaste * A frame has been uploaded: pass the resulting mbuf chain up to 971254721Semaste * the higher level protocols. 972254721Semaste */ 973254721Semastestatic void 974254721Semastevr_rxeof(sc) 975254721Semaste struct vr_softc *sc; 976254721Semaste{ 977254721Semaste struct ether_header *eh; 978254721Semaste struct mbuf *m; 979254721Semaste struct ifnet *ifp; 980254721Semaste struct vr_chain_onefrag *cur_rx; 981254721Semaste int total_len = 0; 982254721Semaste u_int32_t rxstat; 983254721Semaste 984254721Semaste ifp = &sc->arpcom.ac_if; 985254721Semaste 986254721Semaste while(!((rxstat = sc->vr_cdata.vr_rx_head->vr_ptr->vr_status) & 987254721Semaste VR_RXSTAT_OWN)) { 988254721Semaste struct mbuf *m0 = NULL; 989254721Semaste 990254721Semaste cur_rx = sc->vr_cdata.vr_rx_head; 991254721Semaste sc->vr_cdata.vr_rx_head = cur_rx->vr_nextdesc; 992254721Semaste m = cur_rx->vr_mbuf; 993254721Semaste 994254721Semaste /* 995254721Semaste * If an error occurs, update stats, clear the 996254721Semaste * status word and leave the mbuf cluster in place: 997254721Semaste * it should simply get re-used next time this descriptor 998254721Semaste * comes up in the ring. 999254721Semaste */ 1000254721Semaste if (rxstat & VR_RXSTAT_RXERR) { 1001254721Semaste ifp->if_ierrors++; 1002254721Semaste printf("vr%d: rx error: ", sc->vr_unit); 1003254721Semaste switch(rxstat & 0x000000FF) { 1004254721Semaste case VR_RXSTAT_CRCERR: 1005254721Semaste printf("crc error\n"); 1006254721Semaste break; 1007254721Semaste case VR_RXSTAT_FRAMEALIGNERR: 1008254721Semaste printf("frame alignment error\n"); 1009254721Semaste break; 1010254721Semaste case VR_RXSTAT_FIFOOFLOW: 1011254721Semaste printf("FIFO overflow\n"); 1012254721Semaste break; 1013254721Semaste case VR_RXSTAT_GIANT: 1014254721Semaste printf("received giant packet\n"); 1015254721Semaste break; 1016254721Semaste case VR_RXSTAT_RUNT: 1017254721Semaste printf("received runt packet\n"); 1018254721Semaste break; 1019254721Semaste case VR_RXSTAT_BUSERR: 1020254721Semaste printf("system bus error\n"); 1021254721Semaste break; 1022254721Semaste case VR_RXSTAT_BUFFERR: 1023254721Semaste printf("rx buffer error\n"); 1024254721Semaste break; 1025254721Semaste default: 1026254721Semaste printf("unknown rx error\n"); 1027254721Semaste break; 1028254721Semaste } 1029254721Semaste vr_newbuf(sc, cur_rx, m); 1030254721Semaste continue; 1031254721Semaste } 1032254721Semaste 1033254721Semaste /* No errors; receive the packet. */ 1034254721Semaste total_len = VR_RXBYTES(cur_rx->vr_ptr->vr_status); 1035254721Semaste 1036254721Semaste /* 1037254721Semaste * XXX The VIA Rhine chip includes the CRC with every 1038254721Semaste * received frame, and there's no way to turn this 1039254721Semaste * behavior off (at least, I can't find anything in 1040254721Semaste * the manual that explains how to do it) so we have 1041254721Semaste * to trim off the CRC manually. 1042254721Semaste */ 1043254721Semaste total_len -= ETHER_CRC_LEN; 1044254721Semaste 1045254721Semaste m0 = m_devget(mtod(m, char *), total_len, ETHER_ALIGN, ifp, 1046254721Semaste NULL); 1047254721Semaste vr_newbuf(sc, cur_rx, m); 1048254721Semaste if (m0 == NULL) { 1049254721Semaste ifp->if_ierrors++; 1050254721Semaste continue; 1051254721Semaste } 1052254721Semaste m = m0; 1053254721Semaste 1054254721Semaste ifp->if_ipackets++; 1055254721Semaste eh = mtod(m, struct ether_header *); 1056254721Semaste 1057254721Semaste /* Remove header from mbuf and pass it on. */ 1058254721Semaste m_adj(m, sizeof(struct ether_header)); 1059254721Semaste ether_input(ifp, eh, m); 1060254721Semaste } 1061254721Semaste 1062254721Semaste return; 1063254721Semaste} 1064254721Semaste 1065254721Semastestatic void 1066254721Semastevr_rxeoc(sc) 1067254721Semaste struct vr_softc *sc; 1068254721Semaste{ 1069254721Semaste 1070254721Semaste vr_rxeof(sc); 1071254721Semaste VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_RX_ON); 1072254721Semaste CSR_WRITE_4(sc, VR_RXADDR, vtophys(sc->vr_cdata.vr_rx_head->vr_ptr)); 1073254721Semaste VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RX_ON); 1074254721Semaste VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RX_GO); 1075254721Semaste 1076254721Semaste return; 1077254721Semaste} 1078254721Semaste 1079254721Semaste/* 1080254721Semaste * A frame was downloaded to the chip. It's safe for us to clean up 1081254721Semaste * the list buffers. 1082254721Semaste */ 1083254721Semaste 1084254721Semastestatic void 1085254721Semastevr_txeof(sc) 1086254721Semaste struct vr_softc *sc; 1087254721Semaste{ 1088254721Semaste struct vr_chain *cur_tx; 1089254721Semaste struct ifnet *ifp; 1090254721Semaste 1091254721Semaste ifp = &sc->arpcom.ac_if; 1092254721Semaste 1093254721Semaste /* Reset the timeout timer; if_txeoc will clear it. */ 1094254721Semaste ifp->if_timer = 5; 1095254721Semaste 1096254721Semaste /* Sanity check. */ 1097254721Semaste if (sc->vr_cdata.vr_tx_head == NULL) 1098254721Semaste return; 1099254721Semaste 1100254721Semaste /* 1101254721Semaste * Go through our tx list and free mbufs for those 1102254721Semaste * frames that have been transmitted. 1103254721Semaste */ 1104254721Semaste while(sc->vr_cdata.vr_tx_head->vr_mbuf != NULL) { 1105254721Semaste u_int32_t txstat; 1106254721Semaste 1107254721Semaste cur_tx = sc->vr_cdata.vr_tx_head; 1108254721Semaste txstat = cur_tx->vr_ptr->vr_status; 1109254721Semaste 1110254721Semaste if ((txstat & VR_TXSTAT_ABRT) || 1111254721Semaste (txstat & VR_TXSTAT_UDF)) { 1112254721Semaste while (CSR_READ_2(sc, VR_COMMAND) & VR_CMD_TX_ON) 1113254721Semaste ; /* Wait for chip to shutdown */ 1114254721Semaste VR_TXOWN(cur_tx) = VR_TXSTAT_OWN; 1115254721Semaste CSR_WRITE_4(sc, VR_TXADDR, vtophys(cur_tx->vr_ptr)); 1116254721Semaste break; 1117254721Semaste } 1118254721Semaste 1119254721Semaste if (txstat & VR_TXSTAT_OWN) 1120254721Semaste break; 1121254721Semaste 1122254721Semaste if (txstat & VR_TXSTAT_ERRSUM) { 1123254721Semaste ifp->if_oerrors++; 1124254721Semaste if (txstat & VR_TXSTAT_DEFER) 1125254721Semaste ifp->if_collisions++; 1126254721Semaste if (txstat & VR_TXSTAT_LATECOLL) 1127254721Semaste ifp->if_collisions++; 1128254721Semaste } 1129254721Semaste 1130254721Semaste ifp->if_collisions +=(txstat & VR_TXSTAT_COLLCNT) >> 3; 1131254721Semaste 1132254721Semaste ifp->if_opackets++; 1133254721Semaste if (cur_tx->vr_mbuf != NULL) { 1134254721Semaste m_freem(cur_tx->vr_mbuf); 1135254721Semaste cur_tx->vr_mbuf = NULL; 1136254721Semaste } 1137254721Semaste 1138254721Semaste if (sc->vr_cdata.vr_tx_head == sc->vr_cdata.vr_tx_tail) { 1139254721Semaste sc->vr_cdata.vr_tx_head = NULL; 1140254721Semaste sc->vr_cdata.vr_tx_tail = NULL; 1141254721Semaste break; 1142254721Semaste } 1143254721Semaste 1144254721Semaste sc->vr_cdata.vr_tx_head = cur_tx->vr_nextdesc; 1145254721Semaste } 1146254721Semaste 1147254721Semaste return; 1148254721Semaste} 1149254721Semaste 1150254721Semaste/* 1151254721Semaste * TX 'end of channel' interrupt handler. 1152254721Semaste */ 1153254721Semastestatic void 1154254721Semastevr_txeoc(sc) 1155254721Semaste struct vr_softc *sc; 1156254721Semaste{ 1157254721Semaste struct ifnet *ifp; 1158254721Semaste 1159254721Semaste ifp = &sc->arpcom.ac_if; 1160254721Semaste 1161254721Semaste if (sc->vr_cdata.vr_tx_head == NULL) { 1162254721Semaste ifp->if_flags &= ~IFF_OACTIVE; 1163254721Semaste sc->vr_cdata.vr_tx_tail = NULL; 1164254721Semaste ifp->if_timer = 0; 1165254721Semaste } 1166254721Semaste 1167254721Semaste return; 1168254721Semaste} 1169254721Semaste 1170254721Semastestatic void 1171254721Semastevr_tick(xsc) 1172254721Semaste void *xsc; 1173254721Semaste{ 1174254721Semaste struct vr_softc *sc; 1175254721Semaste struct mii_data *mii; 1176254721Semaste 1177254721Semaste sc = xsc; 1178254721Semaste VR_LOCK(sc); 1179254721Semaste mii = device_get_softc(sc->vr_miibus); 1180254721Semaste mii_tick(mii); 1181254721Semaste 1182254721Semaste sc->vr_stat_ch = timeout(vr_tick, sc, hz); 1183254721Semaste 1184254721Semaste VR_UNLOCK(sc); 1185254721Semaste 1186254721Semaste return; 1187254721Semaste} 1188254721Semaste 1189254721Semastestatic void 1190254721Semastevr_intr(arg) 1191254721Semaste void *arg; 1192254721Semaste{ 1193254721Semaste struct vr_softc *sc; 1194254721Semaste struct ifnet *ifp; 1195254721Semaste u_int16_t status; 1196254721Semaste 1197254721Semaste sc = arg; 1198254721Semaste VR_LOCK(sc); 1199254721Semaste ifp = &sc->arpcom.ac_if; 1200254721Semaste 1201254721Semaste /* Supress unwanted interrupts. */ 1202254721Semaste if (!(ifp->if_flags & IFF_UP)) { 1203254721Semaste vr_stop(sc); 1204254721Semaste VR_UNLOCK(sc); 1205254721Semaste return; 1206254721Semaste } 1207254721Semaste 1208254721Semaste /* Disable interrupts. */ 1209254721Semaste CSR_WRITE_2(sc, VR_IMR, 0x0000); 1210254721Semaste 1211254721Semaste for (;;) { 1212 1213 status = CSR_READ_2(sc, VR_ISR); 1214 if (status) 1215 CSR_WRITE_2(sc, VR_ISR, status); 1216 1217 if ((status & VR_INTRS) == 0) 1218 break; 1219 1220 if (status & VR_ISR_RX_OK) 1221 vr_rxeof(sc); 1222 1223 if ((status & VR_ISR_RX_ERR) || (status & VR_ISR_RX_NOBUF) || 1224 (status & VR_ISR_RX_NOBUF) || (status & VR_ISR_RX_OFLOW) || 1225 (status & VR_ISR_RX_DROPPED)) { 1226 vr_rxeof(sc); 1227 vr_rxeoc(sc); 1228 } 1229 1230 if ((status & VR_ISR_BUSERR) || (status & VR_ISR_TX_UNDERRUN)) { 1231 vr_reset(sc); 1232 vr_init(sc); 1233 break; 1234 } 1235 1236 if ((status & VR_ISR_TX_OK) || (status & VR_ISR_TX_ABRT) || 1237 (status & VR_ISR_TX_ABRT2) || (status & VR_ISR_UDFI)) { 1238 vr_txeof(sc); 1239 if ((status & VR_ISR_UDFI) || 1240 (status & VR_ISR_TX_ABRT2) || 1241 (status & VR_ISR_TX_ABRT)) { 1242 ifp->if_oerrors++; 1243 if (sc->vr_cdata.vr_tx_head != NULL) { 1244 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_ON); 1245 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_GO); 1246 } 1247 } else 1248 vr_txeoc(sc); 1249 } 1250 1251 } 1252 1253 /* Re-enable interrupts. */ 1254 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 1255 1256 if (ifp->if_snd.ifq_head != NULL) { 1257 vr_start(ifp); 1258 } 1259 1260 VR_UNLOCK(sc); 1261 1262 return; 1263} 1264 1265/* 1266 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1267 * pointers to the fragment pointers. 1268 */ 1269static int 1270vr_encap(sc, c, m_head) 1271 struct vr_softc *sc; 1272 struct vr_chain *c; 1273 struct mbuf *m_head; 1274{ 1275 int frag = 0; 1276 struct vr_desc *f = NULL; 1277 int total_len; 1278 struct mbuf *m; 1279 1280 m = m_head; 1281 total_len = 0; 1282 1283 /* 1284 * The VIA Rhine wants packet buffers to be longword 1285 * aligned, but very often our mbufs aren't. Rather than 1286 * waste time trying to decide when to copy and when not 1287 * to copy, just do it all the time. 1288 */ 1289 if (m != NULL) { 1290 struct mbuf *m_new = NULL; 1291 1292 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1293 if (m_new == NULL) { 1294 printf("vr%d: no memory for tx list\n", sc->vr_unit); 1295 return(1); 1296 } 1297 if (m_head->m_pkthdr.len > MHLEN) { 1298 MCLGET(m_new, M_DONTWAIT); 1299 if (!(m_new->m_flags & M_EXT)) { 1300 m_freem(m_new); 1301 printf("vr%d: no memory for tx list\n", 1302 sc->vr_unit); 1303 return(1); 1304 } 1305 } 1306 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1307 mtod(m_new, caddr_t)); 1308 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1309 m_freem(m_head); 1310 m_head = m_new; 1311 /* 1312 * The Rhine chip doesn't auto-pad, so we have to make 1313 * sure to pad short frames out to the minimum frame length 1314 * ourselves. 1315 */ 1316 if (m_head->m_len < VR_MIN_FRAMELEN) { 1317 m_new->m_pkthdr.len += VR_MIN_FRAMELEN - m_new->m_len; 1318 m_new->m_len = m_new->m_pkthdr.len; 1319 } 1320 f = c->vr_ptr; 1321 f->vr_data = vtophys(mtod(m_new, caddr_t)); 1322 f->vr_ctl = total_len = m_new->m_len; 1323 f->vr_ctl |= VR_TXCTL_TLINK|VR_TXCTL_FIRSTFRAG; 1324 f->vr_status = 0; 1325 frag = 1; 1326 } 1327 1328 c->vr_mbuf = m_head; 1329 c->vr_ptr->vr_ctl |= VR_TXCTL_LASTFRAG|VR_TXCTL_FINT; 1330 c->vr_ptr->vr_next = vtophys(c->vr_nextdesc->vr_ptr); 1331 1332 return(0); 1333} 1334 1335/* 1336 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1337 * to the mbuf data regions directly in the transmit lists. We also save a 1338 * copy of the pointers since the transmit list fragment pointers are 1339 * physical addresses. 1340 */ 1341 1342static void 1343vr_start(ifp) 1344 struct ifnet *ifp; 1345{ 1346 struct vr_softc *sc; 1347 struct mbuf *m_head = NULL; 1348 struct vr_chain *cur_tx = NULL, *start_tx; 1349 1350 sc = ifp->if_softc; 1351 1352 VR_LOCK(sc); 1353 if (ifp->if_flags & IFF_OACTIVE) { 1354 VR_UNLOCK(sc); 1355 return; 1356 } 1357 1358 /* 1359 * Check for an available queue slot. If there are none, 1360 * punt. 1361 */ 1362 if (sc->vr_cdata.vr_tx_free->vr_mbuf != NULL) { 1363 ifp->if_flags |= IFF_OACTIVE; 1364 return; 1365 } 1366 1367 start_tx = sc->vr_cdata.vr_tx_free; 1368 1369 while(sc->vr_cdata.vr_tx_free->vr_mbuf == NULL) { 1370 IF_DEQUEUE(&ifp->if_snd, m_head); 1371 if (m_head == NULL) 1372 break; 1373 1374 /* Pick a descriptor off the free list. */ 1375 cur_tx = sc->vr_cdata.vr_tx_free; 1376 sc->vr_cdata.vr_tx_free = cur_tx->vr_nextdesc; 1377 1378 /* Pack the data into the descriptor. */ 1379 if (vr_encap(sc, cur_tx, m_head)) { 1380 IF_PREPEND(&ifp->if_snd, m_head); 1381 ifp->if_flags |= IFF_OACTIVE; 1382 cur_tx = NULL; 1383 break; 1384 } 1385 1386 if (cur_tx != start_tx) 1387 VR_TXOWN(cur_tx) = VR_TXSTAT_OWN; 1388 1389 /* 1390 * If there's a BPF listener, bounce a copy of this frame 1391 * to him. 1392 */ 1393 if (ifp->if_bpf) 1394 bpf_mtap(ifp, cur_tx->vr_mbuf); 1395 1396 VR_TXOWN(cur_tx) = VR_TXSTAT_OWN; 1397 VR_SETBIT16(sc, VR_COMMAND, /*VR_CMD_TX_ON|*/VR_CMD_TX_GO); 1398 } 1399 1400 /* 1401 * If there are no frames queued, bail. 1402 */ 1403 if (cur_tx == NULL) { 1404 VR_UNLOCK(sc); 1405 return; 1406 } 1407 1408 sc->vr_cdata.vr_tx_tail = cur_tx; 1409 1410 if (sc->vr_cdata.vr_tx_head == NULL) 1411 sc->vr_cdata.vr_tx_head = start_tx; 1412 1413 /* 1414 * Set a timeout in case the chip goes out to lunch. 1415 */ 1416 ifp->if_timer = 5; 1417 VR_UNLOCK(sc); 1418 1419 return; 1420} 1421 1422static void 1423vr_init(xsc) 1424 void *xsc; 1425{ 1426 struct vr_softc *sc = xsc; 1427 struct ifnet *ifp = &sc->arpcom.ac_if; 1428 struct mii_data *mii; 1429 int i; 1430 1431 VR_LOCK(sc); 1432 1433 mii = device_get_softc(sc->vr_miibus); 1434 1435 /* 1436 * Cancel pending I/O and free all RX/TX buffers. 1437 */ 1438 vr_stop(sc); 1439 vr_reset(sc); 1440 1441 /* 1442 * Set our station address. 1443 */ 1444 for (i = 0; i < ETHER_ADDR_LEN; i++) 1445 CSR_WRITE_1(sc, VR_PAR0 + i, sc->arpcom.ac_enaddr[i]); 1446 1447 /* Set DMA size */ 1448 VR_CLRBIT(sc, VR_BCR0, VR_BCR0_DMA_LENGTH); 1449 VR_SETBIT(sc, VR_BCR0, VR_BCR0_DMA_STORENFWD); 1450 1451 /* 1452 * BCR0 and BCR1 can override the RXCFG and TXCFG registers, 1453 * so we must set both. 1454 */ 1455 VR_CLRBIT(sc, VR_BCR0, VR_BCR0_RX_THRESH); 1456 VR_SETBIT(sc, VR_BCR0, VR_BCR0_RXTHRESHSTORENFWD); 1457 1458 VR_CLRBIT(sc, VR_BCR1, VR_BCR1_TX_THRESH); 1459 VR_SETBIT(sc, VR_BCR1, VR_BCR1_TXTHRESHSTORENFWD); 1460 1461 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_THRESH); 1462 VR_SETBIT(sc, VR_RXCFG, VR_RXTHRESH_STORENFWD); 1463 1464 VR_CLRBIT(sc, VR_TXCFG, VR_TXCFG_TX_THRESH); 1465 VR_SETBIT(sc, VR_TXCFG, VR_TXTHRESH_STORENFWD); 1466 1467 /* Init circular RX list. */ 1468 if (vr_list_rx_init(sc) == ENOBUFS) { 1469 printf("vr%d: initialization failed: no " 1470 "memory for rx buffers\n", sc->vr_unit); 1471 vr_stop(sc); 1472 VR_UNLOCK(sc); 1473 return; 1474 } 1475 1476 /* 1477 * Init tx descriptors. 1478 */ 1479 vr_list_tx_init(sc); 1480 1481 /* If we want promiscuous mode, set the allframes bit. */ 1482 if (ifp->if_flags & IFF_PROMISC) 1483 VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC); 1484 else 1485 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC); 1486 1487 /* Set capture broadcast bit to capture broadcast frames. */ 1488 if (ifp->if_flags & IFF_BROADCAST) 1489 VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD); 1490 else 1491 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD); 1492 1493 /* 1494 * Program the multicast filter, if necessary. 1495 */ 1496 vr_setmulti(sc); 1497 1498 /* 1499 * Load the address of the RX list. 1500 */ 1501 CSR_WRITE_4(sc, VR_RXADDR, vtophys(sc->vr_cdata.vr_rx_head->vr_ptr)); 1502 1503 /* Enable receiver and transmitter. */ 1504 CSR_WRITE_2(sc, VR_COMMAND, VR_CMD_TX_NOPOLL|VR_CMD_START| 1505 VR_CMD_TX_ON|VR_CMD_RX_ON| 1506 VR_CMD_RX_GO); 1507 1508 CSR_WRITE_4(sc, VR_TXADDR, vtophys(&sc->vr_ldata->vr_tx_list[0])); 1509 1510 /* 1511 * Enable interrupts. 1512 */ 1513 CSR_WRITE_2(sc, VR_ISR, 0xFFFF); 1514 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 1515 1516 mii_mediachg(mii); 1517 1518 ifp->if_flags |= IFF_RUNNING; 1519 ifp->if_flags &= ~IFF_OACTIVE; 1520 1521 sc->vr_stat_ch = timeout(vr_tick, sc, hz); 1522 1523 VR_UNLOCK(sc); 1524 1525 return; 1526} 1527 1528/* 1529 * Set media options. 1530 */ 1531static int 1532vr_ifmedia_upd(ifp) 1533 struct ifnet *ifp; 1534{ 1535 struct vr_softc *sc; 1536 1537 sc = ifp->if_softc; 1538 1539 if (ifp->if_flags & IFF_UP) 1540 vr_init(sc); 1541 1542 return(0); 1543} 1544 1545/* 1546 * Report current media status. 1547 */ 1548static void 1549vr_ifmedia_sts(ifp, ifmr) 1550 struct ifnet *ifp; 1551 struct ifmediareq *ifmr; 1552{ 1553 struct vr_softc *sc; 1554 struct mii_data *mii; 1555 1556 sc = ifp->if_softc; 1557 mii = device_get_softc(sc->vr_miibus); 1558 mii_pollstat(mii); 1559 ifmr->ifm_active = mii->mii_media_active; 1560 ifmr->ifm_status = mii->mii_media_status; 1561 1562 return; 1563} 1564 1565static int 1566vr_ioctl(ifp, command, data) 1567 struct ifnet *ifp; 1568 u_long command; 1569 caddr_t data; 1570{ 1571 struct vr_softc *sc = ifp->if_softc; 1572 struct ifreq *ifr = (struct ifreq *) data; 1573 struct mii_data *mii; 1574 int error = 0; 1575 1576 VR_LOCK(sc); 1577 1578 switch(command) { 1579 case SIOCSIFADDR: 1580 case SIOCGIFADDR: 1581 case SIOCSIFMTU: 1582 error = ether_ioctl(ifp, command, data); 1583 break; 1584 case SIOCSIFFLAGS: 1585 if (ifp->if_flags & IFF_UP) { 1586 vr_init(sc); 1587 } else { 1588 if (ifp->if_flags & IFF_RUNNING) 1589 vr_stop(sc); 1590 } 1591 error = 0; 1592 break; 1593 case SIOCADDMULTI: 1594 case SIOCDELMULTI: 1595 vr_setmulti(sc); 1596 error = 0; 1597 break; 1598 case SIOCGIFMEDIA: 1599 case SIOCSIFMEDIA: 1600 mii = device_get_softc(sc->vr_miibus); 1601 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1602 break; 1603 default: 1604 error = EINVAL; 1605 break; 1606 } 1607 1608 VR_UNLOCK(sc); 1609 1610 return(error); 1611} 1612 1613static void 1614vr_watchdog(ifp) 1615 struct ifnet *ifp; 1616{ 1617 struct vr_softc *sc; 1618 1619 sc = ifp->if_softc; 1620 1621 VR_LOCK(sc); 1622 ifp->if_oerrors++; 1623 printf("vr%d: watchdog timeout\n", sc->vr_unit); 1624 1625 vr_stop(sc); 1626 vr_reset(sc); 1627 vr_init(sc); 1628 1629 if (ifp->if_snd.ifq_head != NULL) 1630 vr_start(ifp); 1631 1632 VR_UNLOCK(sc); 1633 1634 return; 1635} 1636 1637/* 1638 * Stop the adapter and free any mbufs allocated to the 1639 * RX and TX lists. 1640 */ 1641static void 1642vr_stop(sc) 1643 struct vr_softc *sc; 1644{ 1645 register int i; 1646 struct ifnet *ifp; 1647 1648 VR_LOCK(sc); 1649 1650 ifp = &sc->arpcom.ac_if; 1651 ifp->if_timer = 0; 1652 1653 untimeout(vr_tick, sc, sc->vr_stat_ch); 1654 1655 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_STOP); 1656 VR_CLRBIT16(sc, VR_COMMAND, (VR_CMD_RX_ON|VR_CMD_TX_ON)); 1657 CSR_WRITE_2(sc, VR_IMR, 0x0000); 1658 CSR_WRITE_4(sc, VR_TXADDR, 0x00000000); 1659 CSR_WRITE_4(sc, VR_RXADDR, 0x00000000); 1660 1661 /* 1662 * Free data in the RX lists. 1663 */ 1664 for (i = 0; i < VR_RX_LIST_CNT; i++) { 1665 if (sc->vr_cdata.vr_rx_chain[i].vr_mbuf != NULL) { 1666 m_freem(sc->vr_cdata.vr_rx_chain[i].vr_mbuf); 1667 sc->vr_cdata.vr_rx_chain[i].vr_mbuf = NULL; 1668 } 1669 } 1670 bzero((char *)&sc->vr_ldata->vr_rx_list, 1671 sizeof(sc->vr_ldata->vr_rx_list)); 1672 1673 /* 1674 * Free the TX list buffers. 1675 */ 1676 for (i = 0; i < VR_TX_LIST_CNT; i++) { 1677 if (sc->vr_cdata.vr_tx_chain[i].vr_mbuf != NULL) { 1678 m_freem(sc->vr_cdata.vr_tx_chain[i].vr_mbuf); 1679 sc->vr_cdata.vr_tx_chain[i].vr_mbuf = NULL; 1680 } 1681 } 1682 1683 bzero((char *)&sc->vr_ldata->vr_tx_list, 1684 sizeof(sc->vr_ldata->vr_tx_list)); 1685 1686 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1687 VR_UNLOCK(sc); 1688 1689 return; 1690} 1691 1692/* 1693 * Stop all chip I/O so that the kernel's probe routines don't 1694 * get confused by errant DMAs when rebooting. 1695 */ 1696static void 1697vr_shutdown(dev) 1698 device_t dev; 1699{ 1700 struct vr_softc *sc; 1701 1702 sc = device_get_softc(dev); 1703 1704 vr_stop(sc); 1705 1706 return; 1707} 1708