if_ural.c revision 212122
1/* $FreeBSD: head/sys/dev/usb/wlan/if_ural.c 212122 2010-09-01 23:47:53Z thompsa $ */ 2 3/*- 4 * Copyright (c) 2005, 2006 5 * Damien Bergamini <damien.bergamini@free.fr> 6 * 7 * Copyright (c) 2006, 2008 8 * Hans Petter Selasky <hselasky@FreeBSD.org> 9 * 10 * Permission to use, copy, modify, and distribute this software for any 11 * purpose with or without fee is hereby granted, provided that the above 12 * copyright notice and this permission notice appear in all copies. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 15 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 16 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 17 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 18 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 19 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 20 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 21 */ 22 23#include <sys/cdefs.h> 24__FBSDID("$FreeBSD: head/sys/dev/usb/wlan/if_ural.c 212122 2010-09-01 23:47:53Z thompsa $"); 25 26/*- 27 * Ralink Technology RT2500USB chipset driver 28 * http://www.ralinktech.com/ 29 */ 30 31#include <sys/param.h> 32#include <sys/sockio.h> 33#include <sys/sysctl.h> 34#include <sys/lock.h> 35#include <sys/mutex.h> 36#include <sys/mbuf.h> 37#include <sys/kernel.h> 38#include <sys/socket.h> 39#include <sys/systm.h> 40#include <sys/malloc.h> 41#include <sys/module.h> 42#include <sys/bus.h> 43#include <sys/endian.h> 44#include <sys/kdb.h> 45 46#include <machine/bus.h> 47#include <machine/resource.h> 48#include <sys/rman.h> 49 50#include <net/bpf.h> 51#include <net/if.h> 52#include <net/if_arp.h> 53#include <net/ethernet.h> 54#include <net/if_dl.h> 55#include <net/if_media.h> 56#include <net/if_types.h> 57 58#ifdef INET 59#include <netinet/in.h> 60#include <netinet/in_systm.h> 61#include <netinet/in_var.h> 62#include <netinet/if_ether.h> 63#include <netinet/ip.h> 64#endif 65 66#include <net80211/ieee80211_var.h> 67#include <net80211/ieee80211_regdomain.h> 68#include <net80211/ieee80211_radiotap.h> 69#include <net80211/ieee80211_ratectl.h> 70 71#include <dev/usb/usb.h> 72#include <dev/usb/usbdi.h> 73#include "usbdevs.h" 74 75#define USB_DEBUG_VAR ural_debug 76#include <dev/usb/usb_debug.h> 77 78#include <dev/usb/wlan/if_uralreg.h> 79#include <dev/usb/wlan/if_uralvar.h> 80 81#ifdef USB_DEBUG 82static int ural_debug = 0; 83 84SYSCTL_NODE(_hw_usb, OID_AUTO, ural, CTLFLAG_RW, 0, "USB ural"); 85SYSCTL_INT(_hw_usb_ural, OID_AUTO, debug, CTLFLAG_RW, &ural_debug, 0, 86 "Debug level"); 87#endif 88 89#define URAL_RSSI(rssi) \ 90 ((rssi) > (RAL_NOISE_FLOOR + RAL_RSSI_CORR) ? \ 91 ((rssi) - (RAL_NOISE_FLOOR + RAL_RSSI_CORR)) : 0) 92 93/* various supported device vendors/products */ 94static const struct usb_device_id ural_devs[] = { 95#define URAL_DEV(v,p) { USB_VP(USB_VENDOR_##v, USB_PRODUCT_##v##_##p) } 96 URAL_DEV(ASUS, WL167G), 97 URAL_DEV(ASUS, RT2570), 98 URAL_DEV(BELKIN, F5D7050), 99 URAL_DEV(BELKIN, F5D7051), 100 URAL_DEV(CISCOLINKSYS, HU200TS), 101 URAL_DEV(CISCOLINKSYS, WUSB54G), 102 URAL_DEV(CISCOLINKSYS, WUSB54GP), 103 URAL_DEV(CONCEPTRONIC2, C54RU), 104 URAL_DEV(DLINK, DWLG122), 105 URAL_DEV(GIGABYTE, GN54G), 106 URAL_DEV(GIGABYTE, GNWBKG), 107 URAL_DEV(GUILLEMOT, HWGUSB254), 108 URAL_DEV(MELCO, KG54), 109 URAL_DEV(MELCO, KG54AI), 110 URAL_DEV(MELCO, KG54YB), 111 URAL_DEV(MELCO, NINWIFI), 112 URAL_DEV(MSI, RT2570), 113 URAL_DEV(MSI, RT2570_2), 114 URAL_DEV(MSI, RT2570_3), 115 URAL_DEV(NOVATECH, NV902), 116 URAL_DEV(RALINK, RT2570), 117 URAL_DEV(RALINK, RT2570_2), 118 URAL_DEV(RALINK, RT2570_3), 119 URAL_DEV(SIEMENS2, WL54G), 120 URAL_DEV(SMC, 2862WG), 121 URAL_DEV(SPHAIRON, UB801R), 122 URAL_DEV(SURECOM, RT2570), 123 URAL_DEV(VTECH, RT2570), 124 URAL_DEV(ZINWELL, RT2570), 125#undef URAL_DEV 126}; 127 128static usb_callback_t ural_bulk_read_callback; 129static usb_callback_t ural_bulk_write_callback; 130 131static usb_error_t ural_do_request(struct ural_softc *sc, 132 struct usb_device_request *req, void *data); 133static struct ieee80211vap *ural_vap_create(struct ieee80211com *, 134 const char name[IFNAMSIZ], int unit, int opmode, 135 int flags, const uint8_t bssid[IEEE80211_ADDR_LEN], 136 const uint8_t mac[IEEE80211_ADDR_LEN]); 137static void ural_vap_delete(struct ieee80211vap *); 138static void ural_tx_free(struct ural_tx_data *, int); 139static void ural_setup_tx_list(struct ural_softc *); 140static void ural_unsetup_tx_list(struct ural_softc *); 141static int ural_newstate(struct ieee80211vap *, 142 enum ieee80211_state, int); 143static void ural_setup_tx_desc(struct ural_softc *, 144 struct ural_tx_desc *, uint32_t, int, int); 145static int ural_tx_bcn(struct ural_softc *, struct mbuf *, 146 struct ieee80211_node *); 147static int ural_tx_mgt(struct ural_softc *, struct mbuf *, 148 struct ieee80211_node *); 149static int ural_tx_data(struct ural_softc *, struct mbuf *, 150 struct ieee80211_node *); 151static void ural_start(struct ifnet *); 152static int ural_ioctl(struct ifnet *, u_long, caddr_t); 153static void ural_set_testmode(struct ural_softc *); 154static void ural_eeprom_read(struct ural_softc *, uint16_t, void *, 155 int); 156static uint16_t ural_read(struct ural_softc *, uint16_t); 157static void ural_read_multi(struct ural_softc *, uint16_t, void *, 158 int); 159static void ural_write(struct ural_softc *, uint16_t, uint16_t); 160static void ural_write_multi(struct ural_softc *, uint16_t, void *, 161 int) __unused; 162static void ural_bbp_write(struct ural_softc *, uint8_t, uint8_t); 163static uint8_t ural_bbp_read(struct ural_softc *, uint8_t); 164static void ural_rf_write(struct ural_softc *, uint8_t, uint32_t); 165static void ural_scan_start(struct ieee80211com *); 166static void ural_scan_end(struct ieee80211com *); 167static void ural_set_channel(struct ieee80211com *); 168static void ural_set_chan(struct ural_softc *, 169 struct ieee80211_channel *); 170static void ural_disable_rf_tune(struct ural_softc *); 171static void ural_enable_tsf_sync(struct ural_softc *); 172static void ural_enable_tsf(struct ural_softc *); 173static void ural_update_slot(struct ifnet *); 174static void ural_set_txpreamble(struct ural_softc *); 175static void ural_set_basicrates(struct ural_softc *, 176 const struct ieee80211_channel *); 177static void ural_set_bssid(struct ural_softc *, const uint8_t *); 178static void ural_set_macaddr(struct ural_softc *, uint8_t *); 179static void ural_update_promisc(struct ifnet *); 180static void ural_setpromisc(struct ural_softc *); 181static const char *ural_get_rf(int); 182static void ural_read_eeprom(struct ural_softc *); 183static int ural_bbp_init(struct ural_softc *); 184static void ural_set_txantenna(struct ural_softc *, int); 185static void ural_set_rxantenna(struct ural_softc *, int); 186static void ural_init_locked(struct ural_softc *); 187static void ural_init(void *); 188static void ural_stop(struct ural_softc *); 189static int ural_raw_xmit(struct ieee80211_node *, struct mbuf *, 190 const struct ieee80211_bpf_params *); 191static void ural_ratectl_start(struct ural_softc *, 192 struct ieee80211_node *); 193static void ural_ratectl_timeout(void *); 194static void ural_ratectl_task(void *, int); 195static int ural_pause(struct ural_softc *sc, int timeout); 196 197/* 198 * Default values for MAC registers; values taken from the reference driver. 199 */ 200static const struct { 201 uint16_t reg; 202 uint16_t val; 203} ural_def_mac[] = { 204 { RAL_TXRX_CSR5, 0x8c8d }, 205 { RAL_TXRX_CSR6, 0x8b8a }, 206 { RAL_TXRX_CSR7, 0x8687 }, 207 { RAL_TXRX_CSR8, 0x0085 }, 208 { RAL_MAC_CSR13, 0x1111 }, 209 { RAL_MAC_CSR14, 0x1e11 }, 210 { RAL_TXRX_CSR21, 0xe78f }, 211 { RAL_MAC_CSR9, 0xff1d }, 212 { RAL_MAC_CSR11, 0x0002 }, 213 { RAL_MAC_CSR22, 0x0053 }, 214 { RAL_MAC_CSR15, 0x0000 }, 215 { RAL_MAC_CSR8, RAL_FRAME_SIZE }, 216 { RAL_TXRX_CSR19, 0x0000 }, 217 { RAL_TXRX_CSR18, 0x005a }, 218 { RAL_PHY_CSR2, 0x0000 }, 219 { RAL_TXRX_CSR0, 0x1ec0 }, 220 { RAL_PHY_CSR4, 0x000f } 221}; 222 223/* 224 * Default values for BBP registers; values taken from the reference driver. 225 */ 226static const struct { 227 uint8_t reg; 228 uint8_t val; 229} ural_def_bbp[] = { 230 { 3, 0x02 }, 231 { 4, 0x19 }, 232 { 14, 0x1c }, 233 { 15, 0x30 }, 234 { 16, 0xac }, 235 { 17, 0x48 }, 236 { 18, 0x18 }, 237 { 19, 0xff }, 238 { 20, 0x1e }, 239 { 21, 0x08 }, 240 { 22, 0x08 }, 241 { 23, 0x08 }, 242 { 24, 0x80 }, 243 { 25, 0x50 }, 244 { 26, 0x08 }, 245 { 27, 0x23 }, 246 { 30, 0x10 }, 247 { 31, 0x2b }, 248 { 32, 0xb9 }, 249 { 34, 0x12 }, 250 { 35, 0x50 }, 251 { 39, 0xc4 }, 252 { 40, 0x02 }, 253 { 41, 0x60 }, 254 { 53, 0x10 }, 255 { 54, 0x18 }, 256 { 56, 0x08 }, 257 { 57, 0x10 }, 258 { 58, 0x08 }, 259 { 61, 0x60 }, 260 { 62, 0x10 }, 261 { 75, 0xff } 262}; 263 264/* 265 * Default values for RF register R2 indexed by channel numbers. 266 */ 267static const uint32_t ural_rf2522_r2[] = { 268 0x307f6, 0x307fb, 0x30800, 0x30805, 0x3080a, 0x3080f, 0x30814, 269 0x30819, 0x3081e, 0x30823, 0x30828, 0x3082d, 0x30832, 0x3083e 270}; 271 272static const uint32_t ural_rf2523_r2[] = { 273 0x00327, 0x00328, 0x00329, 0x0032a, 0x0032b, 0x0032c, 0x0032d, 274 0x0032e, 0x0032f, 0x00340, 0x00341, 0x00342, 0x00343, 0x00346 275}; 276 277static const uint32_t ural_rf2524_r2[] = { 278 0x00327, 0x00328, 0x00329, 0x0032a, 0x0032b, 0x0032c, 0x0032d, 279 0x0032e, 0x0032f, 0x00340, 0x00341, 0x00342, 0x00343, 0x00346 280}; 281 282static const uint32_t ural_rf2525_r2[] = { 283 0x20327, 0x20328, 0x20329, 0x2032a, 0x2032b, 0x2032c, 0x2032d, 284 0x2032e, 0x2032f, 0x20340, 0x20341, 0x20342, 0x20343, 0x20346 285}; 286 287static const uint32_t ural_rf2525_hi_r2[] = { 288 0x2032f, 0x20340, 0x20341, 0x20342, 0x20343, 0x20344, 0x20345, 289 0x20346, 0x20347, 0x20348, 0x20349, 0x2034a, 0x2034b, 0x2034e 290}; 291 292static const uint32_t ural_rf2525e_r2[] = { 293 0x2044d, 0x2044e, 0x2044f, 0x20460, 0x20461, 0x20462, 0x20463, 294 0x20464, 0x20465, 0x20466, 0x20467, 0x20468, 0x20469, 0x2046b 295}; 296 297static const uint32_t ural_rf2526_hi_r2[] = { 298 0x0022a, 0x0022b, 0x0022b, 0x0022c, 0x0022c, 0x0022d, 0x0022d, 299 0x0022e, 0x0022e, 0x0022f, 0x0022d, 0x00240, 0x00240, 0x00241 300}; 301 302static const uint32_t ural_rf2526_r2[] = { 303 0x00226, 0x00227, 0x00227, 0x00228, 0x00228, 0x00229, 0x00229, 304 0x0022a, 0x0022a, 0x0022b, 0x0022b, 0x0022c, 0x0022c, 0x0022d 305}; 306 307/* 308 * For dual-band RF, RF registers R1 and R4 also depend on channel number; 309 * values taken from the reference driver. 310 */ 311static const struct { 312 uint8_t chan; 313 uint32_t r1; 314 uint32_t r2; 315 uint32_t r4; 316} ural_rf5222[] = { 317 { 1, 0x08808, 0x0044d, 0x00282 }, 318 { 2, 0x08808, 0x0044e, 0x00282 }, 319 { 3, 0x08808, 0x0044f, 0x00282 }, 320 { 4, 0x08808, 0x00460, 0x00282 }, 321 { 5, 0x08808, 0x00461, 0x00282 }, 322 { 6, 0x08808, 0x00462, 0x00282 }, 323 { 7, 0x08808, 0x00463, 0x00282 }, 324 { 8, 0x08808, 0x00464, 0x00282 }, 325 { 9, 0x08808, 0x00465, 0x00282 }, 326 { 10, 0x08808, 0x00466, 0x00282 }, 327 { 11, 0x08808, 0x00467, 0x00282 }, 328 { 12, 0x08808, 0x00468, 0x00282 }, 329 { 13, 0x08808, 0x00469, 0x00282 }, 330 { 14, 0x08808, 0x0046b, 0x00286 }, 331 332 { 36, 0x08804, 0x06225, 0x00287 }, 333 { 40, 0x08804, 0x06226, 0x00287 }, 334 { 44, 0x08804, 0x06227, 0x00287 }, 335 { 48, 0x08804, 0x06228, 0x00287 }, 336 { 52, 0x08804, 0x06229, 0x00287 }, 337 { 56, 0x08804, 0x0622a, 0x00287 }, 338 { 60, 0x08804, 0x0622b, 0x00287 }, 339 { 64, 0x08804, 0x0622c, 0x00287 }, 340 341 { 100, 0x08804, 0x02200, 0x00283 }, 342 { 104, 0x08804, 0x02201, 0x00283 }, 343 { 108, 0x08804, 0x02202, 0x00283 }, 344 { 112, 0x08804, 0x02203, 0x00283 }, 345 { 116, 0x08804, 0x02204, 0x00283 }, 346 { 120, 0x08804, 0x02205, 0x00283 }, 347 { 124, 0x08804, 0x02206, 0x00283 }, 348 { 128, 0x08804, 0x02207, 0x00283 }, 349 { 132, 0x08804, 0x02208, 0x00283 }, 350 { 136, 0x08804, 0x02209, 0x00283 }, 351 { 140, 0x08804, 0x0220a, 0x00283 }, 352 353 { 149, 0x08808, 0x02429, 0x00281 }, 354 { 153, 0x08808, 0x0242b, 0x00281 }, 355 { 157, 0x08808, 0x0242d, 0x00281 }, 356 { 161, 0x08808, 0x0242f, 0x00281 } 357}; 358 359static const struct usb_config ural_config[URAL_N_TRANSFER] = { 360 [URAL_BULK_WR] = { 361 .type = UE_BULK, 362 .endpoint = UE_ADDR_ANY, 363 .direction = UE_DIR_OUT, 364 .bufsize = (RAL_FRAME_SIZE + RAL_TX_DESC_SIZE + 4), 365 .flags = {.pipe_bof = 1,.force_short_xfer = 1,}, 366 .callback = ural_bulk_write_callback, 367 .timeout = 5000, /* ms */ 368 }, 369 [URAL_BULK_RD] = { 370 .type = UE_BULK, 371 .endpoint = UE_ADDR_ANY, 372 .direction = UE_DIR_IN, 373 .bufsize = (RAL_FRAME_SIZE + RAL_RX_DESC_SIZE), 374 .flags = {.pipe_bof = 1,.short_xfer_ok = 1,}, 375 .callback = ural_bulk_read_callback, 376 }, 377}; 378 379static device_probe_t ural_match; 380static device_attach_t ural_attach; 381static device_detach_t ural_detach; 382 383static device_method_t ural_methods[] = { 384 /* Device interface */ 385 DEVMETHOD(device_probe, ural_match), 386 DEVMETHOD(device_attach, ural_attach), 387 DEVMETHOD(device_detach, ural_detach), 388 389 { 0, 0 } 390}; 391 392static driver_t ural_driver = { 393 .name = "ural", 394 .methods = ural_methods, 395 .size = sizeof(struct ural_softc), 396}; 397 398static devclass_t ural_devclass; 399 400DRIVER_MODULE(ural, uhub, ural_driver, ural_devclass, NULL, 0); 401MODULE_DEPEND(ural, usb, 1, 1, 1); 402MODULE_DEPEND(ural, wlan, 1, 1, 1); 403MODULE_VERSION(ural, 1); 404 405static int 406ural_match(device_t self) 407{ 408 struct usb_attach_arg *uaa = device_get_ivars(self); 409 410 if (uaa->usb_mode != USB_MODE_HOST) 411 return (ENXIO); 412 if (uaa->info.bConfigIndex != 0) 413 return (ENXIO); 414 if (uaa->info.bIfaceIndex != RAL_IFACE_INDEX) 415 return (ENXIO); 416 417 return (usbd_lookup_id_by_uaa(ural_devs, sizeof(ural_devs), uaa)); 418} 419 420static int 421ural_attach(device_t self) 422{ 423 struct usb_attach_arg *uaa = device_get_ivars(self); 424 struct ural_softc *sc = device_get_softc(self); 425 struct ifnet *ifp; 426 struct ieee80211com *ic; 427 uint8_t iface_index, bands; 428 int error; 429 430 device_set_usb_desc(self); 431 sc->sc_udev = uaa->device; 432 sc->sc_dev = self; 433 434 mtx_init(&sc->sc_mtx, device_get_nameunit(self), 435 MTX_NETWORK_LOCK, MTX_DEF); 436 437 iface_index = RAL_IFACE_INDEX; 438 error = usbd_transfer_setup(uaa->device, 439 &iface_index, sc->sc_xfer, ural_config, 440 URAL_N_TRANSFER, sc, &sc->sc_mtx); 441 if (error) { 442 device_printf(self, "could not allocate USB transfers, " 443 "err=%s\n", usbd_errstr(error)); 444 goto detach; 445 } 446 447 RAL_LOCK(sc); 448 /* retrieve RT2570 rev. no */ 449 sc->asic_rev = ural_read(sc, RAL_MAC_CSR0); 450 451 /* retrieve MAC address and various other things from EEPROM */ 452 ural_read_eeprom(sc); 453 RAL_UNLOCK(sc); 454 455 device_printf(self, "MAC/BBP RT2570 (rev 0x%02x), RF %s\n", 456 sc->asic_rev, ural_get_rf(sc->rf_rev)); 457 458 ifp = sc->sc_ifp = if_alloc(IFT_IEEE80211); 459 if (ifp == NULL) { 460 device_printf(sc->sc_dev, "can not if_alloc()\n"); 461 goto detach; 462 } 463 ic = ifp->if_l2com; 464 465 ifp->if_softc = sc; 466 if_initname(ifp, "ural", device_get_unit(sc->sc_dev)); 467 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 468 ifp->if_init = ural_init; 469 ifp->if_ioctl = ural_ioctl; 470 ifp->if_start = ural_start; 471 IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen); 472 ifp->if_snd.ifq_drv_maxlen = ifqmaxlen; 473 IFQ_SET_READY(&ifp->if_snd); 474 475 ic->ic_ifp = ifp; 476 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 477 478 /* set device capabilities */ 479 ic->ic_caps = 480 IEEE80211_C_STA /* station mode supported */ 481 | IEEE80211_C_IBSS /* IBSS mode supported */ 482 | IEEE80211_C_MONITOR /* monitor mode supported */ 483 | IEEE80211_C_HOSTAP /* HostAp mode supported */ 484 | IEEE80211_C_TXPMGT /* tx power management */ 485 | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 486 | IEEE80211_C_SHSLOT /* short slot time supported */ 487 | IEEE80211_C_BGSCAN /* bg scanning supported */ 488 | IEEE80211_C_WPA /* 802.11i */ 489 | IEEE80211_C_RATECTL /* use ratectl */ 490 ; 491 492 bands = 0; 493 setbit(&bands, IEEE80211_MODE_11B); 494 setbit(&bands, IEEE80211_MODE_11G); 495 if (sc->rf_rev == RAL_RF_5222) 496 setbit(&bands, IEEE80211_MODE_11A); 497 ieee80211_init_channels(ic, NULL, &bands); 498 499 ieee80211_ifattach(ic, sc->sc_bssid); 500 ic->ic_update_promisc = ural_update_promisc; 501 ic->ic_raw_xmit = ural_raw_xmit; 502 ic->ic_scan_start = ural_scan_start; 503 ic->ic_scan_end = ural_scan_end; 504 ic->ic_set_channel = ural_set_channel; 505 506 ic->ic_vap_create = ural_vap_create; 507 ic->ic_vap_delete = ural_vap_delete; 508 509 ieee80211_radiotap_attach(ic, 510 &sc->sc_txtap.wt_ihdr, sizeof(sc->sc_txtap), 511 RAL_TX_RADIOTAP_PRESENT, 512 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap), 513 RAL_RX_RADIOTAP_PRESENT); 514 515 if (bootverbose) 516 ieee80211_announce(ic); 517 518 return (0); 519 520detach: 521 ural_detach(self); 522 return (ENXIO); /* failure */ 523} 524 525static int 526ural_detach(device_t self) 527{ 528 struct ural_softc *sc = device_get_softc(self); 529 struct ifnet *ifp = sc->sc_ifp; 530 struct ieee80211com *ic; 531 532 /* stop all USB transfers */ 533 usbd_transfer_unsetup(sc->sc_xfer, URAL_N_TRANSFER); 534 535 /* free TX list, if any */ 536 RAL_LOCK(sc); 537 ural_unsetup_tx_list(sc); 538 RAL_UNLOCK(sc); 539 540 if (ifp) { 541 ic = ifp->if_l2com; 542 ieee80211_ifdetach(ic); 543 if_free(ifp); 544 } 545 mtx_destroy(&sc->sc_mtx); 546 547 return (0); 548} 549 550static usb_error_t 551ural_do_request(struct ural_softc *sc, 552 struct usb_device_request *req, void *data) 553{ 554 usb_error_t err; 555 int ntries = 10; 556 557 while (ntries--) { 558 err = usbd_do_request_flags(sc->sc_udev, &sc->sc_mtx, 559 req, data, 0, NULL, 250 /* ms */); 560 if (err == 0) 561 break; 562 563 DPRINTFN(1, "Control request failed, %s (retrying)\n", 564 usbd_errstr(err)); 565 if (ural_pause(sc, hz / 100)) 566 break; 567 } 568 return (err); 569} 570 571static struct ieee80211vap * 572ural_vap_create(struct ieee80211com *ic, 573 const char name[IFNAMSIZ], int unit, int opmode, int flags, 574 const uint8_t bssid[IEEE80211_ADDR_LEN], 575 const uint8_t mac[IEEE80211_ADDR_LEN]) 576{ 577 struct ural_softc *sc = ic->ic_ifp->if_softc; 578 struct ural_vap *uvp; 579 struct ieee80211vap *vap; 580 581 if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */ 582 return NULL; 583 uvp = (struct ural_vap *) malloc(sizeof(struct ural_vap), 584 M_80211_VAP, M_NOWAIT | M_ZERO); 585 if (uvp == NULL) 586 return NULL; 587 vap = &uvp->vap; 588 /* enable s/w bmiss handling for sta mode */ 589 ieee80211_vap_setup(ic, vap, name, unit, opmode, 590 flags | IEEE80211_CLONE_NOBEACONS, bssid, mac); 591 592 /* override state transition machine */ 593 uvp->newstate = vap->iv_newstate; 594 vap->iv_newstate = ural_newstate; 595 596 usb_callout_init_mtx(&uvp->ratectl_ch, &sc->sc_mtx, 0); 597 TASK_INIT(&uvp->ratectl_task, 0, ural_ratectl_task, uvp); 598 ieee80211_ratectl_init(vap); 599 ieee80211_ratectl_setinterval(vap, 1000 /* 1 sec */); 600 601 /* complete setup */ 602 ieee80211_vap_attach(vap, ieee80211_media_change, ieee80211_media_status); 603 ic->ic_opmode = opmode; 604 return vap; 605} 606 607static void 608ural_vap_delete(struct ieee80211vap *vap) 609{ 610 struct ural_vap *uvp = URAL_VAP(vap); 611 struct ieee80211com *ic = vap->iv_ic; 612 613 usb_callout_drain(&uvp->ratectl_ch); 614 ieee80211_draintask(ic, &uvp->ratectl_task); 615 ieee80211_ratectl_deinit(vap); 616 ieee80211_vap_detach(vap); 617 free(uvp, M_80211_VAP); 618} 619 620static void 621ural_tx_free(struct ural_tx_data *data, int txerr) 622{ 623 struct ural_softc *sc = data->sc; 624 625 if (data->m != NULL) { 626 if (data->m->m_flags & M_TXCB) 627 ieee80211_process_callback(data->ni, data->m, 628 txerr ? ETIMEDOUT : 0); 629 m_freem(data->m); 630 data->m = NULL; 631 632 ieee80211_free_node(data->ni); 633 data->ni = NULL; 634 } 635 STAILQ_INSERT_TAIL(&sc->tx_free, data, next); 636 sc->tx_nfree++; 637} 638 639static void 640ural_setup_tx_list(struct ural_softc *sc) 641{ 642 struct ural_tx_data *data; 643 int i; 644 645 sc->tx_nfree = 0; 646 STAILQ_INIT(&sc->tx_q); 647 STAILQ_INIT(&sc->tx_free); 648 649 for (i = 0; i < RAL_TX_LIST_COUNT; i++) { 650 data = &sc->tx_data[i]; 651 652 data->sc = sc; 653 STAILQ_INSERT_TAIL(&sc->tx_free, data, next); 654 sc->tx_nfree++; 655 } 656} 657 658static void 659ural_unsetup_tx_list(struct ural_softc *sc) 660{ 661 struct ural_tx_data *data; 662 int i; 663 664 /* make sure any subsequent use of the queues will fail */ 665 sc->tx_nfree = 0; 666 STAILQ_INIT(&sc->tx_q); 667 STAILQ_INIT(&sc->tx_free); 668 669 /* free up all node references and mbufs */ 670 for (i = 0; i < RAL_TX_LIST_COUNT; i++) { 671 data = &sc->tx_data[i]; 672 673 if (data->m != NULL) { 674 m_freem(data->m); 675 data->m = NULL; 676 } 677 if (data->ni != NULL) { 678 ieee80211_free_node(data->ni); 679 data->ni = NULL; 680 } 681 } 682} 683 684static int 685ural_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 686{ 687 struct ural_vap *uvp = URAL_VAP(vap); 688 struct ieee80211com *ic = vap->iv_ic; 689 struct ural_softc *sc = ic->ic_ifp->if_softc; 690 const struct ieee80211_txparam *tp; 691 struct ieee80211_node *ni; 692 struct mbuf *m; 693 694 DPRINTF("%s -> %s\n", 695 ieee80211_state_name[vap->iv_state], 696 ieee80211_state_name[nstate]); 697 698 IEEE80211_UNLOCK(ic); 699 RAL_LOCK(sc); 700 usb_callout_stop(&uvp->ratectl_ch); 701 702 switch (nstate) { 703 case IEEE80211_S_INIT: 704 if (vap->iv_state == IEEE80211_S_RUN) { 705 /* abort TSF synchronization */ 706 ural_write(sc, RAL_TXRX_CSR19, 0); 707 708 /* force tx led to stop blinking */ 709 ural_write(sc, RAL_MAC_CSR20, 0); 710 } 711 break; 712 713 case IEEE80211_S_RUN: 714 ni = vap->iv_bss; 715 716 if (vap->iv_opmode != IEEE80211_M_MONITOR) { 717 ural_update_slot(ic->ic_ifp); 718 ural_set_txpreamble(sc); 719 ural_set_basicrates(sc, ic->ic_bsschan); 720 IEEE80211_ADDR_COPY(sc->sc_bssid, ni->ni_bssid); 721 ural_set_bssid(sc, sc->sc_bssid); 722 } 723 724 if (vap->iv_opmode == IEEE80211_M_HOSTAP || 725 vap->iv_opmode == IEEE80211_M_IBSS) { 726 m = ieee80211_beacon_alloc(ni, &uvp->bo); 727 if (m == NULL) { 728 device_printf(sc->sc_dev, 729 "could not allocate beacon\n"); 730 RAL_UNLOCK(sc); 731 IEEE80211_LOCK(ic); 732 return (-1); 733 } 734 ieee80211_ref_node(ni); 735 if (ural_tx_bcn(sc, m, ni) != 0) { 736 device_printf(sc->sc_dev, 737 "could not send beacon\n"); 738 RAL_UNLOCK(sc); 739 IEEE80211_LOCK(ic); 740 return (-1); 741 } 742 } 743 744 /* make tx led blink on tx (controlled by ASIC) */ 745 ural_write(sc, RAL_MAC_CSR20, 1); 746 747 if (vap->iv_opmode != IEEE80211_M_MONITOR) 748 ural_enable_tsf_sync(sc); 749 else 750 ural_enable_tsf(sc); 751 752 /* enable automatic rate adaptation */ 753 /* XXX should use ic_bsschan but not valid until after newstate call below */ 754 tp = &vap->iv_txparms[ieee80211_chan2mode(ic->ic_curchan)]; 755 if (tp->ucastrate == IEEE80211_FIXED_RATE_NONE) 756 ural_ratectl_start(sc, ni); 757 758 break; 759 760 default: 761 break; 762 } 763 RAL_UNLOCK(sc); 764 IEEE80211_LOCK(ic); 765 return (uvp->newstate(vap, nstate, arg)); 766} 767 768 769static void 770ural_bulk_write_callback(struct usb_xfer *xfer, usb_error_t error) 771{ 772 struct ural_softc *sc = usbd_xfer_softc(xfer); 773 struct ifnet *ifp = sc->sc_ifp; 774 struct ieee80211vap *vap; 775 struct ural_tx_data *data; 776 struct mbuf *m; 777 struct usb_page_cache *pc; 778 int len; 779 780 usbd_xfer_status(xfer, &len, NULL, NULL, NULL); 781 782 switch (USB_GET_STATE(xfer)) { 783 case USB_ST_TRANSFERRED: 784 DPRINTFN(11, "transfer complete, %d bytes\n", len); 785 786 /* free resources */ 787 data = usbd_xfer_get_priv(xfer); 788 ural_tx_free(data, 0); 789 usbd_xfer_set_priv(xfer, NULL); 790 791 ifp->if_opackets++; 792 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 793 794 /* FALLTHROUGH */ 795 case USB_ST_SETUP: 796tr_setup: 797 data = STAILQ_FIRST(&sc->tx_q); 798 if (data) { 799 STAILQ_REMOVE_HEAD(&sc->tx_q, next); 800 m = data->m; 801 802 if (m->m_pkthdr.len > (RAL_FRAME_SIZE + RAL_TX_DESC_SIZE)) { 803 DPRINTFN(0, "data overflow, %u bytes\n", 804 m->m_pkthdr.len); 805 m->m_pkthdr.len = (RAL_FRAME_SIZE + RAL_TX_DESC_SIZE); 806 } 807 pc = usbd_xfer_get_frame(xfer, 0); 808 usbd_copy_in(pc, 0, &data->desc, RAL_TX_DESC_SIZE); 809 usbd_m_copy_in(pc, RAL_TX_DESC_SIZE, m, 0, 810 m->m_pkthdr.len); 811 812 vap = data->ni->ni_vap; 813 if (ieee80211_radiotap_active_vap(vap)) { 814 struct ural_tx_radiotap_header *tap = &sc->sc_txtap; 815 816 tap->wt_flags = 0; 817 tap->wt_rate = data->rate; 818 tap->wt_antenna = sc->tx_ant; 819 820 ieee80211_radiotap_tx(vap, m); 821 } 822 823 /* xfer length needs to be a multiple of two! */ 824 len = (RAL_TX_DESC_SIZE + m->m_pkthdr.len + 1) & ~1; 825 if ((len % 64) == 0) 826 len += 2; 827 828 DPRINTFN(11, "sending frame len=%u xferlen=%u\n", 829 m->m_pkthdr.len, len); 830 831 usbd_xfer_set_frame_len(xfer, 0, len); 832 usbd_xfer_set_priv(xfer, data); 833 834 usbd_transfer_submit(xfer); 835 } 836 RAL_UNLOCK(sc); 837 ural_start(ifp); 838 RAL_LOCK(sc); 839 break; 840 841 default: /* Error */ 842 DPRINTFN(11, "transfer error, %s\n", 843 usbd_errstr(error)); 844 845 ifp->if_oerrors++; 846 data = usbd_xfer_get_priv(xfer); 847 if (data != NULL) { 848 ural_tx_free(data, error); 849 usbd_xfer_set_priv(xfer, NULL); 850 } 851 852 if (error == USB_ERR_STALLED) { 853 /* try to clear stall first */ 854 usbd_xfer_set_stall(xfer); 855 goto tr_setup; 856 } 857 if (error == USB_ERR_TIMEOUT) 858 device_printf(sc->sc_dev, "device timeout\n"); 859 break; 860 } 861} 862 863static void 864ural_bulk_read_callback(struct usb_xfer *xfer, usb_error_t error) 865{ 866 struct ural_softc *sc = usbd_xfer_softc(xfer); 867 struct ifnet *ifp = sc->sc_ifp; 868 struct ieee80211com *ic = ifp->if_l2com; 869 struct ieee80211_node *ni; 870 struct mbuf *m = NULL; 871 struct usb_page_cache *pc; 872 uint32_t flags; 873 int8_t rssi = 0, nf = 0; 874 int len; 875 876 usbd_xfer_status(xfer, &len, NULL, NULL, NULL); 877 878 switch (USB_GET_STATE(xfer)) { 879 case USB_ST_TRANSFERRED: 880 881 DPRINTFN(15, "rx done, actlen=%d\n", len); 882 883 if (len < RAL_RX_DESC_SIZE + IEEE80211_MIN_LEN) { 884 DPRINTF("%s: xfer too short %d\n", 885 device_get_nameunit(sc->sc_dev), len); 886 ifp->if_ierrors++; 887 goto tr_setup; 888 } 889 890 len -= RAL_RX_DESC_SIZE; 891 /* rx descriptor is located at the end */ 892 pc = usbd_xfer_get_frame(xfer, 0); 893 usbd_copy_out(pc, len, &sc->sc_rx_desc, RAL_RX_DESC_SIZE); 894 895 rssi = URAL_RSSI(sc->sc_rx_desc.rssi); 896 nf = RAL_NOISE_FLOOR; 897 flags = le32toh(sc->sc_rx_desc.flags); 898 if (flags & (RAL_RX_PHY_ERROR | RAL_RX_CRC_ERROR)) { 899 /* 900 * This should not happen since we did not 901 * request to receive those frames when we 902 * filled RAL_TXRX_CSR2: 903 */ 904 DPRINTFN(5, "PHY or CRC error\n"); 905 ifp->if_ierrors++; 906 goto tr_setup; 907 } 908 909 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 910 if (m == NULL) { 911 DPRINTF("could not allocate mbuf\n"); 912 ifp->if_ierrors++; 913 goto tr_setup; 914 } 915 usbd_copy_out(pc, 0, mtod(m, uint8_t *), len); 916 917 /* finalize mbuf */ 918 m->m_pkthdr.rcvif = ifp; 919 m->m_pkthdr.len = m->m_len = (flags >> 16) & 0xfff; 920 921 if (ieee80211_radiotap_active(ic)) { 922 struct ural_rx_radiotap_header *tap = &sc->sc_rxtap; 923 924 /* XXX set once */ 925 tap->wr_flags = 0; 926 tap->wr_rate = ieee80211_plcp2rate(sc->sc_rx_desc.rate, 927 (flags & RAL_RX_OFDM) ? 928 IEEE80211_T_OFDM : IEEE80211_T_CCK); 929 tap->wr_antenna = sc->rx_ant; 930 tap->wr_antsignal = nf + rssi; 931 tap->wr_antnoise = nf; 932 } 933 /* Strip trailing 802.11 MAC FCS. */ 934 m_adj(m, -IEEE80211_CRC_LEN); 935 936 /* FALLTHROUGH */ 937 case USB_ST_SETUP: 938tr_setup: 939 usbd_xfer_set_frame_len(xfer, 0, usbd_xfer_max_len(xfer)); 940 usbd_transfer_submit(xfer); 941 942 /* 943 * At the end of a USB callback it is always safe to unlock 944 * the private mutex of a device! That is why we do the 945 * "ieee80211_input" here, and not some lines up! 946 */ 947 RAL_UNLOCK(sc); 948 if (m) { 949 ni = ieee80211_find_rxnode(ic, 950 mtod(m, struct ieee80211_frame_min *)); 951 if (ni != NULL) { 952 (void) ieee80211_input(ni, m, rssi, nf); 953 ieee80211_free_node(ni); 954 } else 955 (void) ieee80211_input_all(ic, m, rssi, nf); 956 } 957 if ((ifp->if_drv_flags & IFF_DRV_OACTIVE) == 0 && 958 !IFQ_IS_EMPTY(&ifp->if_snd)) 959 ural_start(ifp); 960 RAL_LOCK(sc); 961 return; 962 963 default: /* Error */ 964 if (error != USB_ERR_CANCELLED) { 965 /* try to clear stall first */ 966 usbd_xfer_set_stall(xfer); 967 goto tr_setup; 968 } 969 return; 970 } 971} 972 973static uint8_t 974ural_plcp_signal(int rate) 975{ 976 switch (rate) { 977 /* OFDM rates (cf IEEE Std 802.11a-1999, pp. 14 Table 80) */ 978 case 12: return 0xb; 979 case 18: return 0xf; 980 case 24: return 0xa; 981 case 36: return 0xe; 982 case 48: return 0x9; 983 case 72: return 0xd; 984 case 96: return 0x8; 985 case 108: return 0xc; 986 987 /* CCK rates (NB: not IEEE std, device-specific) */ 988 case 2: return 0x0; 989 case 4: return 0x1; 990 case 11: return 0x2; 991 case 22: return 0x3; 992 } 993 return 0xff; /* XXX unsupported/unknown rate */ 994} 995 996static void 997ural_setup_tx_desc(struct ural_softc *sc, struct ural_tx_desc *desc, 998 uint32_t flags, int len, int rate) 999{ 1000 struct ifnet *ifp = sc->sc_ifp; 1001 struct ieee80211com *ic = ifp->if_l2com; 1002 uint16_t plcp_length; 1003 int remainder; 1004 1005 desc->flags = htole32(flags); 1006 desc->flags |= htole32(RAL_TX_NEWSEQ); 1007 desc->flags |= htole32(len << 16); 1008 1009 desc->wme = htole16(RAL_AIFSN(2) | RAL_LOGCWMIN(3) | RAL_LOGCWMAX(5)); 1010 desc->wme |= htole16(RAL_IVOFFSET(sizeof (struct ieee80211_frame))); 1011 1012 /* setup PLCP fields */ 1013 desc->plcp_signal = ural_plcp_signal(rate); 1014 desc->plcp_service = 4; 1015 1016 len += IEEE80211_CRC_LEN; 1017 if (ieee80211_rate2phytype(ic->ic_rt, rate) == IEEE80211_T_OFDM) { 1018 desc->flags |= htole32(RAL_TX_OFDM); 1019 1020 plcp_length = len & 0xfff; 1021 desc->plcp_length_hi = plcp_length >> 6; 1022 desc->plcp_length_lo = plcp_length & 0x3f; 1023 } else { 1024 plcp_length = (16 * len + rate - 1) / rate; 1025 if (rate == 22) { 1026 remainder = (16 * len) % 22; 1027 if (remainder != 0 && remainder < 7) 1028 desc->plcp_service |= RAL_PLCP_LENGEXT; 1029 } 1030 desc->plcp_length_hi = plcp_length >> 8; 1031 desc->plcp_length_lo = plcp_length & 0xff; 1032 1033 if (rate != 2 && (ic->ic_flags & IEEE80211_F_SHPREAMBLE)) 1034 desc->plcp_signal |= 0x08; 1035 } 1036 1037 desc->iv = 0; 1038 desc->eiv = 0; 1039} 1040 1041#define RAL_TX_TIMEOUT 5000 1042 1043static int 1044ural_tx_bcn(struct ural_softc *sc, struct mbuf *m0, struct ieee80211_node *ni) 1045{ 1046 struct ieee80211vap *vap = ni->ni_vap; 1047 struct ieee80211com *ic = ni->ni_ic; 1048 struct ifnet *ifp = sc->sc_ifp; 1049 const struct ieee80211_txparam *tp; 1050 struct ural_tx_data *data; 1051 1052 if (sc->tx_nfree == 0) { 1053 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1054 m_freem(m0); 1055 ieee80211_free_node(ni); 1056 return EIO; 1057 } 1058 data = STAILQ_FIRST(&sc->tx_free); 1059 STAILQ_REMOVE_HEAD(&sc->tx_free, next); 1060 sc->tx_nfree--; 1061 tp = &vap->iv_txparms[ieee80211_chan2mode(ic->ic_bsschan)]; 1062 1063 data->m = m0; 1064 data->ni = ni; 1065 data->rate = tp->mgmtrate; 1066 1067 ural_setup_tx_desc(sc, &data->desc, 1068 RAL_TX_IFS_NEWBACKOFF | RAL_TX_TIMESTAMP, m0->m_pkthdr.len, 1069 tp->mgmtrate); 1070 1071 DPRINTFN(10, "sending beacon frame len=%u rate=%u\n", 1072 m0->m_pkthdr.len, tp->mgmtrate); 1073 1074 STAILQ_INSERT_TAIL(&sc->tx_q, data, next); 1075 usbd_transfer_start(sc->sc_xfer[URAL_BULK_WR]); 1076 1077 return (0); 1078} 1079 1080static int 1081ural_tx_mgt(struct ural_softc *sc, struct mbuf *m0, struct ieee80211_node *ni) 1082{ 1083 struct ieee80211vap *vap = ni->ni_vap; 1084 struct ieee80211com *ic = ni->ni_ic; 1085 const struct ieee80211_txparam *tp; 1086 struct ural_tx_data *data; 1087 struct ieee80211_frame *wh; 1088 struct ieee80211_key *k; 1089 uint32_t flags; 1090 uint16_t dur; 1091 1092 RAL_LOCK_ASSERT(sc, MA_OWNED); 1093 1094 data = STAILQ_FIRST(&sc->tx_free); 1095 STAILQ_REMOVE_HEAD(&sc->tx_free, next); 1096 sc->tx_nfree--; 1097 1098 tp = &vap->iv_txparms[ieee80211_chan2mode(ic->ic_curchan)]; 1099 1100 wh = mtod(m0, struct ieee80211_frame *); 1101 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 1102 k = ieee80211_crypto_encap(ni, m0); 1103 if (k == NULL) { 1104 m_freem(m0); 1105 return ENOBUFS; 1106 } 1107 wh = mtod(m0, struct ieee80211_frame *); 1108 } 1109 1110 data->m = m0; 1111 data->ni = ni; 1112 data->rate = tp->mgmtrate; 1113 1114 flags = 0; 1115 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1116 flags |= RAL_TX_ACK; 1117 1118 dur = ieee80211_ack_duration(ic->ic_rt, tp->mgmtrate, 1119 ic->ic_flags & IEEE80211_F_SHPREAMBLE); 1120 *(uint16_t *)wh->i_dur = htole16(dur); 1121 1122 /* tell hardware to add timestamp for probe responses */ 1123 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) == 1124 IEEE80211_FC0_TYPE_MGT && 1125 (wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) == 1126 IEEE80211_FC0_SUBTYPE_PROBE_RESP) 1127 flags |= RAL_TX_TIMESTAMP; 1128 } 1129 1130 ural_setup_tx_desc(sc, &data->desc, flags, m0->m_pkthdr.len, tp->mgmtrate); 1131 1132 DPRINTFN(10, "sending mgt frame len=%u rate=%u\n", 1133 m0->m_pkthdr.len, tp->mgmtrate); 1134 1135 STAILQ_INSERT_TAIL(&sc->tx_q, data, next); 1136 usbd_transfer_start(sc->sc_xfer[URAL_BULK_WR]); 1137 1138 return 0; 1139} 1140 1141static int 1142ural_sendprot(struct ural_softc *sc, 1143 const struct mbuf *m, struct ieee80211_node *ni, int prot, int rate) 1144{ 1145 struct ieee80211com *ic = ni->ni_ic; 1146 const struct ieee80211_frame *wh; 1147 struct ural_tx_data *data; 1148 struct mbuf *mprot; 1149 int protrate, ackrate, pktlen, flags, isshort; 1150 uint16_t dur; 1151 1152 KASSERT(prot == IEEE80211_PROT_RTSCTS || prot == IEEE80211_PROT_CTSONLY, 1153 ("protection %d", prot)); 1154 1155 wh = mtod(m, const struct ieee80211_frame *); 1156 pktlen = m->m_pkthdr.len + IEEE80211_CRC_LEN; 1157 1158 protrate = ieee80211_ctl_rate(ic->ic_rt, rate); 1159 ackrate = ieee80211_ack_rate(ic->ic_rt, rate); 1160 1161 isshort = (ic->ic_flags & IEEE80211_F_SHPREAMBLE) != 0; 1162 dur = ieee80211_compute_duration(ic->ic_rt, pktlen, rate, isshort) 1163 + ieee80211_ack_duration(ic->ic_rt, rate, isshort); 1164 flags = RAL_TX_RETRY(7); 1165 if (prot == IEEE80211_PROT_RTSCTS) { 1166 /* NB: CTS is the same size as an ACK */ 1167 dur += ieee80211_ack_duration(ic->ic_rt, rate, isshort); 1168 flags |= RAL_TX_ACK; 1169 mprot = ieee80211_alloc_rts(ic, wh->i_addr1, wh->i_addr2, dur); 1170 } else { 1171 mprot = ieee80211_alloc_cts(ic, ni->ni_vap->iv_myaddr, dur); 1172 } 1173 if (mprot == NULL) { 1174 /* XXX stat + msg */ 1175 return ENOBUFS; 1176 } 1177 data = STAILQ_FIRST(&sc->tx_free); 1178 STAILQ_REMOVE_HEAD(&sc->tx_free, next); 1179 sc->tx_nfree--; 1180 1181 data->m = mprot; 1182 data->ni = ieee80211_ref_node(ni); 1183 data->rate = protrate; 1184 ural_setup_tx_desc(sc, &data->desc, flags, mprot->m_pkthdr.len, protrate); 1185 1186 STAILQ_INSERT_TAIL(&sc->tx_q, data, next); 1187 usbd_transfer_start(sc->sc_xfer[URAL_BULK_WR]); 1188 1189 return 0; 1190} 1191 1192static int 1193ural_tx_raw(struct ural_softc *sc, struct mbuf *m0, struct ieee80211_node *ni, 1194 const struct ieee80211_bpf_params *params) 1195{ 1196 struct ieee80211com *ic = ni->ni_ic; 1197 struct ural_tx_data *data; 1198 uint32_t flags; 1199 int error; 1200 int rate; 1201 1202 RAL_LOCK_ASSERT(sc, MA_OWNED); 1203 KASSERT(params != NULL, ("no raw xmit params")); 1204 1205 rate = params->ibp_rate0; 1206 if (!ieee80211_isratevalid(ic->ic_rt, rate)) { 1207 m_freem(m0); 1208 return EINVAL; 1209 } 1210 flags = 0; 1211 if ((params->ibp_flags & IEEE80211_BPF_NOACK) == 0) 1212 flags |= RAL_TX_ACK; 1213 if (params->ibp_flags & (IEEE80211_BPF_RTS|IEEE80211_BPF_CTS)) { 1214 error = ural_sendprot(sc, m0, ni, 1215 params->ibp_flags & IEEE80211_BPF_RTS ? 1216 IEEE80211_PROT_RTSCTS : IEEE80211_PROT_CTSONLY, 1217 rate); 1218 if (error || sc->tx_nfree == 0) { 1219 m_freem(m0); 1220 return ENOBUFS; 1221 } 1222 flags |= RAL_TX_IFS_SIFS; 1223 } 1224 1225 data = STAILQ_FIRST(&sc->tx_free); 1226 STAILQ_REMOVE_HEAD(&sc->tx_free, next); 1227 sc->tx_nfree--; 1228 1229 data->m = m0; 1230 data->ni = ni; 1231 data->rate = rate; 1232 1233 /* XXX need to setup descriptor ourself */ 1234 ural_setup_tx_desc(sc, &data->desc, flags, m0->m_pkthdr.len, rate); 1235 1236 DPRINTFN(10, "sending raw frame len=%u rate=%u\n", 1237 m0->m_pkthdr.len, rate); 1238 1239 STAILQ_INSERT_TAIL(&sc->tx_q, data, next); 1240 usbd_transfer_start(sc->sc_xfer[URAL_BULK_WR]); 1241 1242 return 0; 1243} 1244 1245static int 1246ural_tx_data(struct ural_softc *sc, struct mbuf *m0, struct ieee80211_node *ni) 1247{ 1248 struct ieee80211vap *vap = ni->ni_vap; 1249 struct ieee80211com *ic = ni->ni_ic; 1250 struct ural_tx_data *data; 1251 struct ieee80211_frame *wh; 1252 const struct ieee80211_txparam *tp; 1253 struct ieee80211_key *k; 1254 uint32_t flags = 0; 1255 uint16_t dur; 1256 int error, rate; 1257 1258 RAL_LOCK_ASSERT(sc, MA_OWNED); 1259 1260 wh = mtod(m0, struct ieee80211_frame *); 1261 1262 tp = &vap->iv_txparms[ieee80211_chan2mode(ni->ni_chan)]; 1263 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 1264 rate = tp->mcastrate; 1265 else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) 1266 rate = tp->ucastrate; 1267 else 1268 rate = ni->ni_txrate; 1269 1270 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 1271 k = ieee80211_crypto_encap(ni, m0); 1272 if (k == NULL) { 1273 m_freem(m0); 1274 return ENOBUFS; 1275 } 1276 /* packet header may have moved, reset our local pointer */ 1277 wh = mtod(m0, struct ieee80211_frame *); 1278 } 1279 1280 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1281 int prot = IEEE80211_PROT_NONE; 1282 if (m0->m_pkthdr.len + IEEE80211_CRC_LEN > vap->iv_rtsthreshold) 1283 prot = IEEE80211_PROT_RTSCTS; 1284 else if ((ic->ic_flags & IEEE80211_F_USEPROT) && 1285 ieee80211_rate2phytype(ic->ic_rt, rate) == IEEE80211_T_OFDM) 1286 prot = ic->ic_protmode; 1287 if (prot != IEEE80211_PROT_NONE) { 1288 error = ural_sendprot(sc, m0, ni, prot, rate); 1289 if (error || sc->tx_nfree == 0) { 1290 m_freem(m0); 1291 return ENOBUFS; 1292 } 1293 flags |= RAL_TX_IFS_SIFS; 1294 } 1295 } 1296 1297 data = STAILQ_FIRST(&sc->tx_free); 1298 STAILQ_REMOVE_HEAD(&sc->tx_free, next); 1299 sc->tx_nfree--; 1300 1301 data->m = m0; 1302 data->ni = ni; 1303 data->rate = rate; 1304 1305 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1306 flags |= RAL_TX_ACK; 1307 flags |= RAL_TX_RETRY(7); 1308 1309 dur = ieee80211_ack_duration(ic->ic_rt, rate, 1310 ic->ic_flags & IEEE80211_F_SHPREAMBLE); 1311 *(uint16_t *)wh->i_dur = htole16(dur); 1312 } 1313 1314 ural_setup_tx_desc(sc, &data->desc, flags, m0->m_pkthdr.len, rate); 1315 1316 DPRINTFN(10, "sending data frame len=%u rate=%u\n", 1317 m0->m_pkthdr.len, rate); 1318 1319 STAILQ_INSERT_TAIL(&sc->tx_q, data, next); 1320 usbd_transfer_start(sc->sc_xfer[URAL_BULK_WR]); 1321 1322 return 0; 1323} 1324 1325static void 1326ural_start(struct ifnet *ifp) 1327{ 1328 struct ural_softc *sc = ifp->if_softc; 1329 struct ieee80211_node *ni; 1330 struct mbuf *m; 1331 1332 RAL_LOCK(sc); 1333 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 1334 RAL_UNLOCK(sc); 1335 return; 1336 } 1337 for (;;) { 1338 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 1339 if (m == NULL) 1340 break; 1341 if (sc->tx_nfree < RAL_TX_MINFREE) { 1342 IFQ_DRV_PREPEND(&ifp->if_snd, m); 1343 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1344 break; 1345 } 1346 ni = (struct ieee80211_node *) m->m_pkthdr.rcvif; 1347 if (ural_tx_data(sc, m, ni) != 0) { 1348 ieee80211_free_node(ni); 1349 ifp->if_oerrors++; 1350 break; 1351 } 1352 } 1353 RAL_UNLOCK(sc); 1354} 1355 1356static int 1357ural_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1358{ 1359 struct ural_softc *sc = ifp->if_softc; 1360 struct ieee80211com *ic = ifp->if_l2com; 1361 struct ifreq *ifr = (struct ifreq *) data; 1362 int error = 0, startall = 0; 1363 1364 switch (cmd) { 1365 case SIOCSIFFLAGS: 1366 RAL_LOCK(sc); 1367 if (ifp->if_flags & IFF_UP) { 1368 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 1369 ural_init_locked(sc); 1370 startall = 1; 1371 } else 1372 ural_setpromisc(sc); 1373 } else { 1374 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1375 ural_stop(sc); 1376 } 1377 RAL_UNLOCK(sc); 1378 if (startall) 1379 ieee80211_start_all(ic); 1380 break; 1381 case SIOCGIFMEDIA: 1382 case SIOCSIFMEDIA: 1383 error = ifmedia_ioctl(ifp, ifr, &ic->ic_media, cmd); 1384 break; 1385 default: 1386 error = ether_ioctl(ifp, cmd, data); 1387 break; 1388 } 1389 return error; 1390} 1391 1392static void 1393ural_set_testmode(struct ural_softc *sc) 1394{ 1395 struct usb_device_request req; 1396 usb_error_t error; 1397 1398 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1399 req.bRequest = RAL_VENDOR_REQUEST; 1400 USETW(req.wValue, 4); 1401 USETW(req.wIndex, 1); 1402 USETW(req.wLength, 0); 1403 1404 error = ural_do_request(sc, &req, NULL); 1405 if (error != 0) { 1406 device_printf(sc->sc_dev, "could not set test mode: %s\n", 1407 usbd_errstr(error)); 1408 } 1409} 1410 1411static void 1412ural_eeprom_read(struct ural_softc *sc, uint16_t addr, void *buf, int len) 1413{ 1414 struct usb_device_request req; 1415 usb_error_t error; 1416 1417 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1418 req.bRequest = RAL_READ_EEPROM; 1419 USETW(req.wValue, 0); 1420 USETW(req.wIndex, addr); 1421 USETW(req.wLength, len); 1422 1423 error = ural_do_request(sc, &req, buf); 1424 if (error != 0) { 1425 device_printf(sc->sc_dev, "could not read EEPROM: %s\n", 1426 usbd_errstr(error)); 1427 } 1428} 1429 1430static uint16_t 1431ural_read(struct ural_softc *sc, uint16_t reg) 1432{ 1433 struct usb_device_request req; 1434 usb_error_t error; 1435 uint16_t val; 1436 1437 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1438 req.bRequest = RAL_READ_MAC; 1439 USETW(req.wValue, 0); 1440 USETW(req.wIndex, reg); 1441 USETW(req.wLength, sizeof (uint16_t)); 1442 1443 error = ural_do_request(sc, &req, &val); 1444 if (error != 0) { 1445 device_printf(sc->sc_dev, "could not read MAC register: %s\n", 1446 usbd_errstr(error)); 1447 return 0; 1448 } 1449 1450 return le16toh(val); 1451} 1452 1453static void 1454ural_read_multi(struct ural_softc *sc, uint16_t reg, void *buf, int len) 1455{ 1456 struct usb_device_request req; 1457 usb_error_t error; 1458 1459 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1460 req.bRequest = RAL_READ_MULTI_MAC; 1461 USETW(req.wValue, 0); 1462 USETW(req.wIndex, reg); 1463 USETW(req.wLength, len); 1464 1465 error = ural_do_request(sc, &req, buf); 1466 if (error != 0) { 1467 device_printf(sc->sc_dev, "could not read MAC register: %s\n", 1468 usbd_errstr(error)); 1469 } 1470} 1471 1472static void 1473ural_write(struct ural_softc *sc, uint16_t reg, uint16_t val) 1474{ 1475 struct usb_device_request req; 1476 usb_error_t error; 1477 1478 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1479 req.bRequest = RAL_WRITE_MAC; 1480 USETW(req.wValue, val); 1481 USETW(req.wIndex, reg); 1482 USETW(req.wLength, 0); 1483 1484 error = ural_do_request(sc, &req, NULL); 1485 if (error != 0) { 1486 device_printf(sc->sc_dev, "could not write MAC register: %s\n", 1487 usbd_errstr(error)); 1488 } 1489} 1490 1491static void 1492ural_write_multi(struct ural_softc *sc, uint16_t reg, void *buf, int len) 1493{ 1494 struct usb_device_request req; 1495 usb_error_t error; 1496 1497 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1498 req.bRequest = RAL_WRITE_MULTI_MAC; 1499 USETW(req.wValue, 0); 1500 USETW(req.wIndex, reg); 1501 USETW(req.wLength, len); 1502 1503 error = ural_do_request(sc, &req, buf); 1504 if (error != 0) { 1505 device_printf(sc->sc_dev, "could not write MAC register: %s\n", 1506 usbd_errstr(error)); 1507 } 1508} 1509 1510static void 1511ural_bbp_write(struct ural_softc *sc, uint8_t reg, uint8_t val) 1512{ 1513 uint16_t tmp; 1514 int ntries; 1515 1516 for (ntries = 0; ntries < 100; ntries++) { 1517 if (!(ural_read(sc, RAL_PHY_CSR8) & RAL_BBP_BUSY)) 1518 break; 1519 if (ural_pause(sc, hz / 100)) 1520 break; 1521 } 1522 if (ntries == 100) { 1523 device_printf(sc->sc_dev, "could not write to BBP\n"); 1524 return; 1525 } 1526 1527 tmp = reg << 8 | val; 1528 ural_write(sc, RAL_PHY_CSR7, tmp); 1529} 1530 1531static uint8_t 1532ural_bbp_read(struct ural_softc *sc, uint8_t reg) 1533{ 1534 uint16_t val; 1535 int ntries; 1536 1537 val = RAL_BBP_WRITE | reg << 8; 1538 ural_write(sc, RAL_PHY_CSR7, val); 1539 1540 for (ntries = 0; ntries < 100; ntries++) { 1541 if (!(ural_read(sc, RAL_PHY_CSR8) & RAL_BBP_BUSY)) 1542 break; 1543 if (ural_pause(sc, hz / 100)) 1544 break; 1545 } 1546 if (ntries == 100) { 1547 device_printf(sc->sc_dev, "could not read BBP\n"); 1548 return 0; 1549 } 1550 1551 return ural_read(sc, RAL_PHY_CSR7) & 0xff; 1552} 1553 1554static void 1555ural_rf_write(struct ural_softc *sc, uint8_t reg, uint32_t val) 1556{ 1557 uint32_t tmp; 1558 int ntries; 1559 1560 for (ntries = 0; ntries < 100; ntries++) { 1561 if (!(ural_read(sc, RAL_PHY_CSR10) & RAL_RF_LOBUSY)) 1562 break; 1563 if (ural_pause(sc, hz / 100)) 1564 break; 1565 } 1566 if (ntries == 100) { 1567 device_printf(sc->sc_dev, "could not write to RF\n"); 1568 return; 1569 } 1570 1571 tmp = RAL_RF_BUSY | RAL_RF_20BIT | (val & 0xfffff) << 2 | (reg & 0x3); 1572 ural_write(sc, RAL_PHY_CSR9, tmp & 0xffff); 1573 ural_write(sc, RAL_PHY_CSR10, tmp >> 16); 1574 1575 /* remember last written value in sc */ 1576 sc->rf_regs[reg] = val; 1577 1578 DPRINTFN(15, "RF R[%u] <- 0x%05x\n", reg & 0x3, val & 0xfffff); 1579} 1580 1581static void 1582ural_scan_start(struct ieee80211com *ic) 1583{ 1584 struct ifnet *ifp = ic->ic_ifp; 1585 struct ural_softc *sc = ifp->if_softc; 1586 1587 RAL_LOCK(sc); 1588 ural_write(sc, RAL_TXRX_CSR19, 0); 1589 ural_set_bssid(sc, ifp->if_broadcastaddr); 1590 RAL_UNLOCK(sc); 1591} 1592 1593static void 1594ural_scan_end(struct ieee80211com *ic) 1595{ 1596 struct ural_softc *sc = ic->ic_ifp->if_softc; 1597 1598 RAL_LOCK(sc); 1599 ural_enable_tsf_sync(sc); 1600 ural_set_bssid(sc, sc->sc_bssid); 1601 RAL_UNLOCK(sc); 1602 1603} 1604 1605static void 1606ural_set_channel(struct ieee80211com *ic) 1607{ 1608 struct ural_softc *sc = ic->ic_ifp->if_softc; 1609 1610 RAL_LOCK(sc); 1611 ural_set_chan(sc, ic->ic_curchan); 1612 RAL_UNLOCK(sc); 1613} 1614 1615static void 1616ural_set_chan(struct ural_softc *sc, struct ieee80211_channel *c) 1617{ 1618 struct ifnet *ifp = sc->sc_ifp; 1619 struct ieee80211com *ic = ifp->if_l2com; 1620 uint8_t power, tmp; 1621 int i, chan; 1622 1623 chan = ieee80211_chan2ieee(ic, c); 1624 if (chan == 0 || chan == IEEE80211_CHAN_ANY) 1625 return; 1626 1627 if (IEEE80211_IS_CHAN_2GHZ(c)) 1628 power = min(sc->txpow[chan - 1], 31); 1629 else 1630 power = 31; 1631 1632 /* adjust txpower using ifconfig settings */ 1633 power -= (100 - ic->ic_txpowlimit) / 8; 1634 1635 DPRINTFN(2, "setting channel to %u, txpower to %u\n", chan, power); 1636 1637 switch (sc->rf_rev) { 1638 case RAL_RF_2522: 1639 ural_rf_write(sc, RAL_RF1, 0x00814); 1640 ural_rf_write(sc, RAL_RF2, ural_rf2522_r2[chan - 1]); 1641 ural_rf_write(sc, RAL_RF3, power << 7 | 0x00040); 1642 break; 1643 1644 case RAL_RF_2523: 1645 ural_rf_write(sc, RAL_RF1, 0x08804); 1646 ural_rf_write(sc, RAL_RF2, ural_rf2523_r2[chan - 1]); 1647 ural_rf_write(sc, RAL_RF3, power << 7 | 0x38044); 1648 ural_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00280 : 0x00286); 1649 break; 1650 1651 case RAL_RF_2524: 1652 ural_rf_write(sc, RAL_RF1, 0x0c808); 1653 ural_rf_write(sc, RAL_RF2, ural_rf2524_r2[chan - 1]); 1654 ural_rf_write(sc, RAL_RF3, power << 7 | 0x00040); 1655 ural_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00280 : 0x00286); 1656 break; 1657 1658 case RAL_RF_2525: 1659 ural_rf_write(sc, RAL_RF1, 0x08808); 1660 ural_rf_write(sc, RAL_RF2, ural_rf2525_hi_r2[chan - 1]); 1661 ural_rf_write(sc, RAL_RF3, power << 7 | 0x18044); 1662 ural_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00280 : 0x00286); 1663 1664 ural_rf_write(sc, RAL_RF1, 0x08808); 1665 ural_rf_write(sc, RAL_RF2, ural_rf2525_r2[chan - 1]); 1666 ural_rf_write(sc, RAL_RF3, power << 7 | 0x18044); 1667 ural_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00280 : 0x00286); 1668 break; 1669 1670 case RAL_RF_2525E: 1671 ural_rf_write(sc, RAL_RF1, 0x08808); 1672 ural_rf_write(sc, RAL_RF2, ural_rf2525e_r2[chan - 1]); 1673 ural_rf_write(sc, RAL_RF3, power << 7 | 0x18044); 1674 ural_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00286 : 0x00282); 1675 break; 1676 1677 case RAL_RF_2526: 1678 ural_rf_write(sc, RAL_RF2, ural_rf2526_hi_r2[chan - 1]); 1679 ural_rf_write(sc, RAL_RF4, (chan & 1) ? 0x00386 : 0x00381); 1680 ural_rf_write(sc, RAL_RF1, 0x08804); 1681 1682 ural_rf_write(sc, RAL_RF2, ural_rf2526_r2[chan - 1]); 1683 ural_rf_write(sc, RAL_RF3, power << 7 | 0x18044); 1684 ural_rf_write(sc, RAL_RF4, (chan & 1) ? 0x00386 : 0x00381); 1685 break; 1686 1687 /* dual-band RF */ 1688 case RAL_RF_5222: 1689 for (i = 0; ural_rf5222[i].chan != chan; i++); 1690 1691 ural_rf_write(sc, RAL_RF1, ural_rf5222[i].r1); 1692 ural_rf_write(sc, RAL_RF2, ural_rf5222[i].r2); 1693 ural_rf_write(sc, RAL_RF3, power << 7 | 0x00040); 1694 ural_rf_write(sc, RAL_RF4, ural_rf5222[i].r4); 1695 break; 1696 } 1697 1698 if (ic->ic_opmode != IEEE80211_M_MONITOR && 1699 (ic->ic_flags & IEEE80211_F_SCAN) == 0) { 1700 /* set Japan filter bit for channel 14 */ 1701 tmp = ural_bbp_read(sc, 70); 1702 1703 tmp &= ~RAL_JAPAN_FILTER; 1704 if (chan == 14) 1705 tmp |= RAL_JAPAN_FILTER; 1706 1707 ural_bbp_write(sc, 70, tmp); 1708 1709 /* clear CRC errors */ 1710 ural_read(sc, RAL_STA_CSR0); 1711 1712 ural_pause(sc, hz / 100); 1713 ural_disable_rf_tune(sc); 1714 } 1715 1716 /* XXX doesn't belong here */ 1717 /* update basic rate set */ 1718 ural_set_basicrates(sc, c); 1719 1720 /* give the hardware some time to do the switchover */ 1721 ural_pause(sc, hz / 100); 1722} 1723 1724/* 1725 * Disable RF auto-tuning. 1726 */ 1727static void 1728ural_disable_rf_tune(struct ural_softc *sc) 1729{ 1730 uint32_t tmp; 1731 1732 if (sc->rf_rev != RAL_RF_2523) { 1733 tmp = sc->rf_regs[RAL_RF1] & ~RAL_RF1_AUTOTUNE; 1734 ural_rf_write(sc, RAL_RF1, tmp); 1735 } 1736 1737 tmp = sc->rf_regs[RAL_RF3] & ~RAL_RF3_AUTOTUNE; 1738 ural_rf_write(sc, RAL_RF3, tmp); 1739 1740 DPRINTFN(2, "disabling RF autotune\n"); 1741} 1742 1743/* 1744 * Refer to IEEE Std 802.11-1999 pp. 123 for more information on TSF 1745 * synchronization. 1746 */ 1747static void 1748ural_enable_tsf_sync(struct ural_softc *sc) 1749{ 1750 struct ifnet *ifp = sc->sc_ifp; 1751 struct ieee80211com *ic = ifp->if_l2com; 1752 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 1753 uint16_t logcwmin, preload, tmp; 1754 1755 /* first, disable TSF synchronization */ 1756 ural_write(sc, RAL_TXRX_CSR19, 0); 1757 1758 tmp = (16 * vap->iv_bss->ni_intval) << 4; 1759 ural_write(sc, RAL_TXRX_CSR18, tmp); 1760 1761 logcwmin = (ic->ic_opmode == IEEE80211_M_IBSS) ? 2 : 0; 1762 preload = (ic->ic_opmode == IEEE80211_M_IBSS) ? 320 : 6; 1763 tmp = logcwmin << 12 | preload; 1764 ural_write(sc, RAL_TXRX_CSR20, tmp); 1765 1766 /* finally, enable TSF synchronization */ 1767 tmp = RAL_ENABLE_TSF | RAL_ENABLE_TBCN; 1768 if (ic->ic_opmode == IEEE80211_M_STA) 1769 tmp |= RAL_ENABLE_TSF_SYNC(1); 1770 else 1771 tmp |= RAL_ENABLE_TSF_SYNC(2) | RAL_ENABLE_BEACON_GENERATOR; 1772 ural_write(sc, RAL_TXRX_CSR19, tmp); 1773 1774 DPRINTF("enabling TSF synchronization\n"); 1775} 1776 1777static void 1778ural_enable_tsf(struct ural_softc *sc) 1779{ 1780 /* first, disable TSF synchronization */ 1781 ural_write(sc, RAL_TXRX_CSR19, 0); 1782 ural_write(sc, RAL_TXRX_CSR19, RAL_ENABLE_TSF | RAL_ENABLE_TSF_SYNC(2)); 1783} 1784 1785#define RAL_RXTX_TURNAROUND 5 /* us */ 1786static void 1787ural_update_slot(struct ifnet *ifp) 1788{ 1789 struct ural_softc *sc = ifp->if_softc; 1790 struct ieee80211com *ic = ifp->if_l2com; 1791 uint16_t slottime, sifs, eifs; 1792 1793 slottime = (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; 1794 1795 /* 1796 * These settings may sound a bit inconsistent but this is what the 1797 * reference driver does. 1798 */ 1799 if (ic->ic_curmode == IEEE80211_MODE_11B) { 1800 sifs = 16 - RAL_RXTX_TURNAROUND; 1801 eifs = 364; 1802 } else { 1803 sifs = 10 - RAL_RXTX_TURNAROUND; 1804 eifs = 64; 1805 } 1806 1807 ural_write(sc, RAL_MAC_CSR10, slottime); 1808 ural_write(sc, RAL_MAC_CSR11, sifs); 1809 ural_write(sc, RAL_MAC_CSR12, eifs); 1810} 1811 1812static void 1813ural_set_txpreamble(struct ural_softc *sc) 1814{ 1815 struct ifnet *ifp = sc->sc_ifp; 1816 struct ieee80211com *ic = ifp->if_l2com; 1817 uint16_t tmp; 1818 1819 tmp = ural_read(sc, RAL_TXRX_CSR10); 1820 1821 tmp &= ~RAL_SHORT_PREAMBLE; 1822 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 1823 tmp |= RAL_SHORT_PREAMBLE; 1824 1825 ural_write(sc, RAL_TXRX_CSR10, tmp); 1826} 1827 1828static void 1829ural_set_basicrates(struct ural_softc *sc, const struct ieee80211_channel *c) 1830{ 1831 /* XXX wrong, take from rate set */ 1832 /* update basic rate set */ 1833 if (IEEE80211_IS_CHAN_5GHZ(c)) { 1834 /* 11a basic rates: 6, 12, 24Mbps */ 1835 ural_write(sc, RAL_TXRX_CSR11, 0x150); 1836 } else if (IEEE80211_IS_CHAN_ANYG(c)) { 1837 /* 11g basic rates: 1, 2, 5.5, 11, 6, 12, 24Mbps */ 1838 ural_write(sc, RAL_TXRX_CSR11, 0x15f); 1839 } else { 1840 /* 11b basic rates: 1, 2Mbps */ 1841 ural_write(sc, RAL_TXRX_CSR11, 0x3); 1842 } 1843} 1844 1845static void 1846ural_set_bssid(struct ural_softc *sc, const uint8_t *bssid) 1847{ 1848 uint16_t tmp; 1849 1850 tmp = bssid[0] | bssid[1] << 8; 1851 ural_write(sc, RAL_MAC_CSR5, tmp); 1852 1853 tmp = bssid[2] | bssid[3] << 8; 1854 ural_write(sc, RAL_MAC_CSR6, tmp); 1855 1856 tmp = bssid[4] | bssid[5] << 8; 1857 ural_write(sc, RAL_MAC_CSR7, tmp); 1858 1859 DPRINTF("setting BSSID to %6D\n", bssid, ":"); 1860} 1861 1862static void 1863ural_set_macaddr(struct ural_softc *sc, uint8_t *addr) 1864{ 1865 uint16_t tmp; 1866 1867 tmp = addr[0] | addr[1] << 8; 1868 ural_write(sc, RAL_MAC_CSR2, tmp); 1869 1870 tmp = addr[2] | addr[3] << 8; 1871 ural_write(sc, RAL_MAC_CSR3, tmp); 1872 1873 tmp = addr[4] | addr[5] << 8; 1874 ural_write(sc, RAL_MAC_CSR4, tmp); 1875 1876 DPRINTF("setting MAC address to %6D\n", addr, ":"); 1877} 1878 1879static void 1880ural_setpromisc(struct ural_softc *sc) 1881{ 1882 struct ifnet *ifp = sc->sc_ifp; 1883 uint32_t tmp; 1884 1885 tmp = ural_read(sc, RAL_TXRX_CSR2); 1886 1887 tmp &= ~RAL_DROP_NOT_TO_ME; 1888 if (!(ifp->if_flags & IFF_PROMISC)) 1889 tmp |= RAL_DROP_NOT_TO_ME; 1890 1891 ural_write(sc, RAL_TXRX_CSR2, tmp); 1892 1893 DPRINTF("%s promiscuous mode\n", (ifp->if_flags & IFF_PROMISC) ? 1894 "entering" : "leaving"); 1895} 1896 1897static void 1898ural_update_promisc(struct ifnet *ifp) 1899{ 1900 struct ural_softc *sc = ifp->if_softc; 1901 1902 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 1903 return; 1904 1905 RAL_LOCK(sc); 1906 ural_setpromisc(sc); 1907 RAL_UNLOCK(sc); 1908} 1909 1910static const char * 1911ural_get_rf(int rev) 1912{ 1913 switch (rev) { 1914 case RAL_RF_2522: return "RT2522"; 1915 case RAL_RF_2523: return "RT2523"; 1916 case RAL_RF_2524: return "RT2524"; 1917 case RAL_RF_2525: return "RT2525"; 1918 case RAL_RF_2525E: return "RT2525e"; 1919 case RAL_RF_2526: return "RT2526"; 1920 case RAL_RF_5222: return "RT5222"; 1921 default: return "unknown"; 1922 } 1923} 1924 1925static void 1926ural_read_eeprom(struct ural_softc *sc) 1927{ 1928 uint16_t val; 1929 1930 ural_eeprom_read(sc, RAL_EEPROM_CONFIG0, &val, 2); 1931 val = le16toh(val); 1932 sc->rf_rev = (val >> 11) & 0x7; 1933 sc->hw_radio = (val >> 10) & 0x1; 1934 sc->led_mode = (val >> 6) & 0x7; 1935 sc->rx_ant = (val >> 4) & 0x3; 1936 sc->tx_ant = (val >> 2) & 0x3; 1937 sc->nb_ant = val & 0x3; 1938 1939 /* read MAC address */ 1940 ural_eeprom_read(sc, RAL_EEPROM_ADDRESS, sc->sc_bssid, 6); 1941 1942 /* read default values for BBP registers */ 1943 ural_eeprom_read(sc, RAL_EEPROM_BBP_BASE, sc->bbp_prom, 2 * 16); 1944 1945 /* read Tx power for all b/g channels */ 1946 ural_eeprom_read(sc, RAL_EEPROM_TXPOWER, sc->txpow, 14); 1947} 1948 1949static int 1950ural_bbp_init(struct ural_softc *sc) 1951{ 1952#define N(a) (sizeof (a) / sizeof ((a)[0])) 1953 int i, ntries; 1954 1955 /* wait for BBP to be ready */ 1956 for (ntries = 0; ntries < 100; ntries++) { 1957 if (ural_bbp_read(sc, RAL_BBP_VERSION) != 0) 1958 break; 1959 if (ural_pause(sc, hz / 100)) 1960 break; 1961 } 1962 if (ntries == 100) { 1963 device_printf(sc->sc_dev, "timeout waiting for BBP\n"); 1964 return EIO; 1965 } 1966 1967 /* initialize BBP registers to default values */ 1968 for (i = 0; i < N(ural_def_bbp); i++) 1969 ural_bbp_write(sc, ural_def_bbp[i].reg, ural_def_bbp[i].val); 1970 1971#if 0 1972 /* initialize BBP registers to values stored in EEPROM */ 1973 for (i = 0; i < 16; i++) { 1974 if (sc->bbp_prom[i].reg == 0xff) 1975 continue; 1976 ural_bbp_write(sc, sc->bbp_prom[i].reg, sc->bbp_prom[i].val); 1977 } 1978#endif 1979 1980 return 0; 1981#undef N 1982} 1983 1984static void 1985ural_set_txantenna(struct ural_softc *sc, int antenna) 1986{ 1987 uint16_t tmp; 1988 uint8_t tx; 1989 1990 tx = ural_bbp_read(sc, RAL_BBP_TX) & ~RAL_BBP_ANTMASK; 1991 if (antenna == 1) 1992 tx |= RAL_BBP_ANTA; 1993 else if (antenna == 2) 1994 tx |= RAL_BBP_ANTB; 1995 else 1996 tx |= RAL_BBP_DIVERSITY; 1997 1998 /* need to force I/Q flip for RF 2525e, 2526 and 5222 */ 1999 if (sc->rf_rev == RAL_RF_2525E || sc->rf_rev == RAL_RF_2526 || 2000 sc->rf_rev == RAL_RF_5222) 2001 tx |= RAL_BBP_FLIPIQ; 2002 2003 ural_bbp_write(sc, RAL_BBP_TX, tx); 2004 2005 /* update values in PHY_CSR5 and PHY_CSR6 */ 2006 tmp = ural_read(sc, RAL_PHY_CSR5) & ~0x7; 2007 ural_write(sc, RAL_PHY_CSR5, tmp | (tx & 0x7)); 2008 2009 tmp = ural_read(sc, RAL_PHY_CSR6) & ~0x7; 2010 ural_write(sc, RAL_PHY_CSR6, tmp | (tx & 0x7)); 2011} 2012 2013static void 2014ural_set_rxantenna(struct ural_softc *sc, int antenna) 2015{ 2016 uint8_t rx; 2017 2018 rx = ural_bbp_read(sc, RAL_BBP_RX) & ~RAL_BBP_ANTMASK; 2019 if (antenna == 1) 2020 rx |= RAL_BBP_ANTA; 2021 else if (antenna == 2) 2022 rx |= RAL_BBP_ANTB; 2023 else 2024 rx |= RAL_BBP_DIVERSITY; 2025 2026 /* need to force no I/Q flip for RF 2525e and 2526 */ 2027 if (sc->rf_rev == RAL_RF_2525E || sc->rf_rev == RAL_RF_2526) 2028 rx &= ~RAL_BBP_FLIPIQ; 2029 2030 ural_bbp_write(sc, RAL_BBP_RX, rx); 2031} 2032 2033static void 2034ural_init_locked(struct ural_softc *sc) 2035{ 2036#define N(a) (sizeof (a) / sizeof ((a)[0])) 2037 struct ifnet *ifp = sc->sc_ifp; 2038 struct ieee80211com *ic = ifp->if_l2com; 2039 uint16_t tmp; 2040 int i, ntries; 2041 2042 RAL_LOCK_ASSERT(sc, MA_OWNED); 2043 2044 ural_set_testmode(sc); 2045 ural_write(sc, 0x308, 0x00f0); /* XXX magic */ 2046 2047 ural_stop(sc); 2048 2049 /* initialize MAC registers to default values */ 2050 for (i = 0; i < N(ural_def_mac); i++) 2051 ural_write(sc, ural_def_mac[i].reg, ural_def_mac[i].val); 2052 2053 /* wait for BBP and RF to wake up (this can take a long time!) */ 2054 for (ntries = 0; ntries < 100; ntries++) { 2055 tmp = ural_read(sc, RAL_MAC_CSR17); 2056 if ((tmp & (RAL_BBP_AWAKE | RAL_RF_AWAKE)) == 2057 (RAL_BBP_AWAKE | RAL_RF_AWAKE)) 2058 break; 2059 if (ural_pause(sc, hz / 100)) 2060 break; 2061 } 2062 if (ntries == 100) { 2063 device_printf(sc->sc_dev, 2064 "timeout waiting for BBP/RF to wakeup\n"); 2065 goto fail; 2066 } 2067 2068 /* we're ready! */ 2069 ural_write(sc, RAL_MAC_CSR1, RAL_HOST_READY); 2070 2071 /* set basic rate set (will be updated later) */ 2072 ural_write(sc, RAL_TXRX_CSR11, 0x15f); 2073 2074 if (ural_bbp_init(sc) != 0) 2075 goto fail; 2076 2077 ural_set_chan(sc, ic->ic_curchan); 2078 2079 /* clear statistic registers (STA_CSR0 to STA_CSR10) */ 2080 ural_read_multi(sc, RAL_STA_CSR0, sc->sta, sizeof sc->sta); 2081 2082 ural_set_txantenna(sc, sc->tx_ant); 2083 ural_set_rxantenna(sc, sc->rx_ant); 2084 2085 ural_set_macaddr(sc, IF_LLADDR(ifp)); 2086 2087 /* 2088 * Allocate Tx and Rx xfer queues. 2089 */ 2090 ural_setup_tx_list(sc); 2091 2092 /* kick Rx */ 2093 tmp = RAL_DROP_PHY | RAL_DROP_CRC; 2094 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 2095 tmp |= RAL_DROP_CTL | RAL_DROP_BAD_VERSION; 2096 if (ic->ic_opmode != IEEE80211_M_HOSTAP) 2097 tmp |= RAL_DROP_TODS; 2098 if (!(ifp->if_flags & IFF_PROMISC)) 2099 tmp |= RAL_DROP_NOT_TO_ME; 2100 } 2101 ural_write(sc, RAL_TXRX_CSR2, tmp); 2102 2103 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2104 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2105 usbd_xfer_set_stall(sc->sc_xfer[URAL_BULK_WR]); 2106 usbd_transfer_start(sc->sc_xfer[URAL_BULK_RD]); 2107 return; 2108 2109fail: ural_stop(sc); 2110#undef N 2111} 2112 2113static void 2114ural_init(void *priv) 2115{ 2116 struct ural_softc *sc = priv; 2117 struct ifnet *ifp = sc->sc_ifp; 2118 struct ieee80211com *ic = ifp->if_l2com; 2119 2120 RAL_LOCK(sc); 2121 ural_init_locked(sc); 2122 RAL_UNLOCK(sc); 2123 2124 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2125 ieee80211_start_all(ic); /* start all vap's */ 2126} 2127 2128static void 2129ural_stop(struct ural_softc *sc) 2130{ 2131 struct ifnet *ifp = sc->sc_ifp; 2132 2133 RAL_LOCK_ASSERT(sc, MA_OWNED); 2134 2135 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2136 2137 /* 2138 * Drain all the transfers, if not already drained: 2139 */ 2140 RAL_UNLOCK(sc); 2141 usbd_transfer_drain(sc->sc_xfer[URAL_BULK_WR]); 2142 usbd_transfer_drain(sc->sc_xfer[URAL_BULK_RD]); 2143 RAL_LOCK(sc); 2144 2145 ural_unsetup_tx_list(sc); 2146 2147 /* disable Rx */ 2148 ural_write(sc, RAL_TXRX_CSR2, RAL_DISABLE_RX); 2149 /* reset ASIC and BBP (but won't reset MAC registers!) */ 2150 ural_write(sc, RAL_MAC_CSR1, RAL_RESET_ASIC | RAL_RESET_BBP); 2151 /* wait a little */ 2152 ural_pause(sc, hz / 10); 2153 ural_write(sc, RAL_MAC_CSR1, 0); 2154 /* wait a little */ 2155 ural_pause(sc, hz / 10); 2156} 2157 2158static int 2159ural_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 2160 const struct ieee80211_bpf_params *params) 2161{ 2162 struct ieee80211com *ic = ni->ni_ic; 2163 struct ifnet *ifp = ic->ic_ifp; 2164 struct ural_softc *sc = ifp->if_softc; 2165 2166 RAL_LOCK(sc); 2167 /* prevent management frames from being sent if we're not ready */ 2168 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 2169 RAL_UNLOCK(sc); 2170 m_freem(m); 2171 ieee80211_free_node(ni); 2172 return ENETDOWN; 2173 } 2174 if (sc->tx_nfree < RAL_TX_MINFREE) { 2175 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2176 RAL_UNLOCK(sc); 2177 m_freem(m); 2178 ieee80211_free_node(ni); 2179 return EIO; 2180 } 2181 2182 ifp->if_opackets++; 2183 2184 if (params == NULL) { 2185 /* 2186 * Legacy path; interpret frame contents to decide 2187 * precisely how to send the frame. 2188 */ 2189 if (ural_tx_mgt(sc, m, ni) != 0) 2190 goto bad; 2191 } else { 2192 /* 2193 * Caller supplied explicit parameters to use in 2194 * sending the frame. 2195 */ 2196 if (ural_tx_raw(sc, m, ni, params) != 0) 2197 goto bad; 2198 } 2199 RAL_UNLOCK(sc); 2200 return 0; 2201bad: 2202 ifp->if_oerrors++; 2203 RAL_UNLOCK(sc); 2204 ieee80211_free_node(ni); 2205 return EIO; /* XXX */ 2206} 2207 2208static void 2209ural_ratectl_start(struct ural_softc *sc, struct ieee80211_node *ni) 2210{ 2211 struct ieee80211vap *vap = ni->ni_vap; 2212 struct ural_vap *uvp = URAL_VAP(vap); 2213 2214 /* clear statistic registers (STA_CSR0 to STA_CSR10) */ 2215 ural_read_multi(sc, RAL_STA_CSR0, sc->sta, sizeof sc->sta); 2216 2217 ieee80211_ratectl_node_init(ni); 2218 2219 usb_callout_reset(&uvp->ratectl_ch, hz, ural_ratectl_timeout, uvp); 2220} 2221 2222static void 2223ural_ratectl_timeout(void *arg) 2224{ 2225 struct ural_vap *uvp = arg; 2226 struct ieee80211vap *vap = &uvp->vap; 2227 struct ieee80211com *ic = vap->iv_ic; 2228 2229 ieee80211_runtask(ic, &uvp->ratectl_task); 2230} 2231 2232static void 2233ural_ratectl_task(void *arg, int pending) 2234{ 2235 struct ural_vap *uvp = arg; 2236 struct ieee80211vap *vap = &uvp->vap; 2237 struct ieee80211com *ic = vap->iv_ic; 2238 struct ifnet *ifp = ic->ic_ifp; 2239 struct ural_softc *sc = ifp->if_softc; 2240 struct ieee80211_node *ni = vap->iv_bss; 2241 int ok, fail; 2242 int sum, retrycnt; 2243 2244 RAL_LOCK(sc); 2245 /* read and clear statistic registers (STA_CSR0 to STA_CSR10) */ 2246 ural_read_multi(sc, RAL_STA_CSR0, sc->sta, sizeof(sc->sta)); 2247 2248 ok = sc->sta[7] + /* TX ok w/o retry */ 2249 sc->sta[8]; /* TX ok w/ retry */ 2250 fail = sc->sta[9]; /* TX retry-fail count */ 2251 sum = ok+fail; 2252 retrycnt = sc->sta[8] + fail; 2253 2254 ieee80211_ratectl_tx_update(vap, ni, &sum, &ok, &retrycnt); 2255 (void) ieee80211_ratectl_rate(ni, NULL, 0); 2256 2257 ifp->if_oerrors += fail; /* count TX retry-fail as Tx errors */ 2258 2259 usb_callout_reset(&uvp->ratectl_ch, hz, ural_ratectl_timeout, uvp); 2260 RAL_UNLOCK(sc); 2261} 2262 2263static int 2264ural_pause(struct ural_softc *sc, int timeout) 2265{ 2266 2267 usb_pause_mtx(&sc->sc_mtx, timeout); 2268 return (0); 2269} 2270