if_ural.c revision 190532
1280304Sjkim/* $FreeBSD: head/sys/dev/usb/wlan/if_ural.c 190532 2009-03-29 21:17:08Z sam $ */ 2238384Sjkim 3238384Sjkim/*- 4238384Sjkim * Copyright (c) 2005, 2006 5238384Sjkim * Damien Bergamini <damien.bergamini@free.fr> 6280304Sjkim * 7280304Sjkim * Copyright (c) 2006, 2008 8238384Sjkim * Hans Petter Selasky <hselasky@FreeBSD.org> 9238384Sjkim * 10238384Sjkim * Permission to use, copy, modify, and distribute this software for any 11238384Sjkim * purpose with or without fee is hereby granted, provided that the above 12238384Sjkim * copyright notice and this permission notice appear in all copies. 13238384Sjkim * 14238384Sjkim * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 15238384Sjkim * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 16238384Sjkim * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 17238384Sjkim * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 18238384Sjkim * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 19238384Sjkim * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 20238384Sjkim * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 21238384Sjkim */ 22238384Sjkim 23238384Sjkim#include <sys/cdefs.h> 24238384Sjkim__FBSDID("$FreeBSD: head/sys/dev/usb/wlan/if_ural.c 190532 2009-03-29 21:17:08Z sam $"); 25238384Sjkim 26238384Sjkim/*- 27238384Sjkim * Ralink Technology RT2500USB chipset driver 28238384Sjkim * http://www.ralinktech.com/ 29238384Sjkim */ 30238384Sjkim 31238384Sjkim#include "usbdevs.h" 32238384Sjkim#include <dev/usb/usb.h> 33238384Sjkim#include <dev/usb/usb_mfunc.h> 34238384Sjkim#include <dev/usb/usb_error.h> 35238384Sjkim 36238384Sjkim#define USB_DEBUG_VAR ural_debug 37238384Sjkim 38238384Sjkim#include <dev/usb/usb_core.h> 39238384Sjkim#include <dev/usb/usb_lookup.h> 40238384Sjkim#include <dev/usb/usb_process.h> 41238384Sjkim#include <dev/usb/usb_debug.h> 42238384Sjkim#include <dev/usb/usb_request.h> 43238384Sjkim#include <dev/usb/usb_busdma.h> 44238384Sjkim#include <dev/usb/usb_util.h> 45238384Sjkim 46238384Sjkim#include <dev/usb/wlan/usb_wlan.h> 47238384Sjkim#include <dev/usb/wlan/if_uralreg.h> 48238384Sjkim#include <dev/usb/wlan/if_uralvar.h> 49238384Sjkim 50238384Sjkim#if USB_DEBUG 51238384Sjkimstatic int ural_debug = 0; 52238384Sjkim 53238384SjkimSYSCTL_NODE(_hw_usb2, OID_AUTO, ural, CTLFLAG_RW, 0, "USB ural"); 54238384SjkimSYSCTL_INT(_hw_usb2_ural, OID_AUTO, debug, CTLFLAG_RW, &ural_debug, 0, 55238384Sjkim "Debug level"); 56238384Sjkim#endif 57238384Sjkim 58238384Sjkim#define URAL_RSSI(rssi) \ 59238384Sjkim ((rssi) > (RAL_NOISE_FLOOR + RAL_RSSI_CORR) ? \ 60238384Sjkim ((rssi) - (RAL_NOISE_FLOOR + RAL_RSSI_CORR)) : 0) 61238384Sjkim 62238384Sjkim/* various supported device vendors/products */ 63238384Sjkimstatic const struct usb2_device_id ural_devs[] = { 64238384Sjkim { USB_VP(USB_VENDOR_ASUS, USB_PRODUCT_ASUS_WL167G) }, 65238384Sjkim { USB_VP(USB_VENDOR_ASUS, USB_PRODUCT_RALINK_RT2570) }, 66238384Sjkim { USB_VP(USB_VENDOR_BELKIN, USB_PRODUCT_BELKIN_F5D7050) }, 67238384Sjkim { USB_VP(USB_VENDOR_BELKIN, USB_PRODUCT_BELKIN_F5D7051) }, 68238384Sjkim { USB_VP(USB_VENDOR_CISCOLINKSYS, USB_PRODUCT_CISCOLINKSYS_HU200TS) }, 69238384Sjkim { USB_VP(USB_VENDOR_CISCOLINKSYS, USB_PRODUCT_CISCOLINKSYS_WUSB54G) }, 70238384Sjkim { USB_VP(USB_VENDOR_CISCOLINKSYS, USB_PRODUCT_CISCOLINKSYS_WUSB54GP) }, 71238384Sjkim { USB_VP(USB_VENDOR_CONCEPTRONIC2, USB_PRODUCT_CONCEPTRONIC2_C54RU) }, 72238384Sjkim { USB_VP(USB_VENDOR_DLINK, USB_PRODUCT_DLINK_DWLG122) }, 73238384Sjkim { USB_VP(USB_VENDOR_GIGABYTE, USB_PRODUCT_GIGABYTE_GN54G) }, 74280304Sjkim { USB_VP(USB_VENDOR_GIGABYTE, USB_PRODUCT_GIGABYTE_GNWBKG) }, 75238384Sjkim { USB_VP(USB_VENDOR_GUILLEMOT, USB_PRODUCT_GUILLEMOT_HWGUSB254) }, 76238384Sjkim { USB_VP(USB_VENDOR_MELCO, USB_PRODUCT_MELCO_KG54) }, 77238384Sjkim { USB_VP(USB_VENDOR_MELCO, USB_PRODUCT_MELCO_KG54AI) }, 78238384Sjkim { USB_VP(USB_VENDOR_MELCO, USB_PRODUCT_MELCO_KG54YB) }, 79238384Sjkim { USB_VP(USB_VENDOR_MELCO, USB_PRODUCT_MELCO_NINWIFI) }, 80280304Sjkim { USB_VP(USB_VENDOR_MSI, USB_PRODUCT_MSI_RT2570) }, 81238384Sjkim { USB_VP(USB_VENDOR_MSI, USB_PRODUCT_MSI_RT2570_2) }, 82238384Sjkim { USB_VP(USB_VENDOR_MSI, USB_PRODUCT_MSI_RT2570_3) }, 83280304Sjkim { USB_VP(USB_VENDOR_NOVATECH, USB_PRODUCT_NOVATECH_NV902) }, 84280304Sjkim { USB_VP(USB_VENDOR_RALINK, USB_PRODUCT_RALINK_RT2570) }, 85238384Sjkim { USB_VP(USB_VENDOR_RALINK, USB_PRODUCT_RALINK_RT2570_2) }, 86280304Sjkim { USB_VP(USB_VENDOR_RALINK, USB_PRODUCT_RALINK_RT2570_3) }, 87280304Sjkim { USB_VP(USB_VENDOR_SIEMENS2, USB_PRODUCT_SIEMENS2_WL54G) }, 88280304Sjkim { USB_VP(USB_VENDOR_SMC, USB_PRODUCT_SMC_2862WG) }, 89238384Sjkim { USB_VP(USB_VENDOR_SPHAIRON, USB_PRODUCT_SPHAIRON_UB801R) }, 90280304Sjkim { USB_VP(USB_VENDOR_SURECOM, USB_PRODUCT_SURECOM_RT2570) }, 91280304Sjkim { USB_VP(USB_VENDOR_VTECH, USB_PRODUCT_VTECH_RT2570) }, 92280304Sjkim { USB_VP(USB_VENDOR_ZINWELL, USB_PRODUCT_ZINWELL_RT2570) }, 93238384Sjkim}; 94238384Sjkim 95280304Sjkimstatic usb2_callback_t ural_bulk_read_callback; 96280304Sjkimstatic usb2_callback_t ural_bulk_write_callback; 97280304Sjkim 98280304Sjkimstatic usb2_proc_callback_t ural_command_wrapper; 99280304Sjkimstatic usb2_proc_callback_t ural_attach_post; 100280304Sjkimstatic usb2_proc_callback_t ural_task; 101280304Sjkimstatic usb2_proc_callback_t ural_scantask; 102280304Sjkimstatic usb2_proc_callback_t ural_promisctask; 103280304Sjkimstatic usb2_proc_callback_t ural_amrr_task; 104280304Sjkimstatic usb2_proc_callback_t ural_init_task; 105238384Sjkimstatic usb2_proc_callback_t ural_stop_task; 106280304Sjkimstatic usb2_proc_callback_t ural_flush_task; 107280304Sjkim 108280304Sjkimstatic usb2_error_t ural_do_request(struct ural_softc *sc, 109238384Sjkim struct usb2_device_request *req, void *data); 110280304Sjkimstatic struct ieee80211vap *ural_vap_create(struct ieee80211com *, 111280304Sjkim const char name[IFNAMSIZ], int unit, int opmode, 112280304Sjkim int flags, const uint8_t bssid[IEEE80211_ADDR_LEN], 113280304Sjkim const uint8_t mac[IEEE80211_ADDR_LEN]); 114238384Sjkimstatic void ural_vap_delete(struct ieee80211vap *); 115280304Sjkimstatic void ural_tx_free(struct ural_tx_data *, int); 116238384Sjkimstatic void ural_setup_tx_list(struct ural_softc *); 117238384Sjkimstatic void ural_unsetup_tx_list(struct ural_softc *); 118280304Sjkimstatic int ural_newstate(struct ieee80211vap *, 119280304Sjkim enum ieee80211_state, int); 120280304Sjkimstatic void ural_setup_tx_desc(struct ural_softc *, 121280304Sjkim struct ural_tx_desc *, uint32_t, int, int); 122280304Sjkimstatic int ural_tx_bcn(struct ural_softc *, struct mbuf *, 123280304Sjkim struct ieee80211_node *); 124280304Sjkimstatic int ural_tx_mgt(struct ural_softc *, struct mbuf *, 125280304Sjkim struct ieee80211_node *); 126238384Sjkimstatic int ural_tx_data(struct ural_softc *, struct mbuf *, 127238384Sjkim struct ieee80211_node *); 128280304Sjkimstatic void ural_start(struct ifnet *); 129238384Sjkimstatic int ural_ioctl(struct ifnet *, u_long, caddr_t); 130280304Sjkimstatic void ural_set_testmode(struct ural_softc *); 131280304Sjkimstatic void ural_eeprom_read(struct ural_softc *, uint16_t, void *, 132280304Sjkim int); 133280304Sjkimstatic uint16_t ural_read(struct ural_softc *, uint16_t); 134280304Sjkimstatic void ural_read_multi(struct ural_softc *, uint16_t, void *, 135280304Sjkim int); 136280304Sjkimstatic void ural_write(struct ural_softc *, uint16_t, uint16_t); 137280304Sjkimstatic void ural_write_multi(struct ural_softc *, uint16_t, void *, 138280304Sjkim int) __unused; 139280304Sjkimstatic void ural_bbp_write(struct ural_softc *, uint8_t, uint8_t); 140280304Sjkimstatic uint8_t ural_bbp_read(struct ural_softc *, uint8_t); 141280304Sjkimstatic void ural_rf_write(struct ural_softc *, uint8_t, uint32_t); 142280304Sjkimstatic struct ieee80211_node *ural_node_alloc(struct ieee80211vap *, 143280304Sjkim const uint8_t mac[IEEE80211_ADDR_LEN]); 144280304Sjkimstatic void ural_newassoc(struct ieee80211_node *, int); 145280304Sjkimstatic void ural_scan_start(struct ieee80211com *); 146238384Sjkimstatic void ural_scan_end(struct ieee80211com *); 147238384Sjkimstatic void ural_set_channel(struct ieee80211com *); 148238384Sjkimstatic void ural_set_chan(struct ural_softc *, 149238384Sjkim struct ieee80211_channel *); 150238384Sjkimstatic void ural_disable_rf_tune(struct ural_softc *); 151238384Sjkimstatic void ural_enable_tsf_sync(struct ural_softc *); 152238384Sjkimstatic void ural_update_slot(struct ifnet *); 153238384Sjkimstatic void ural_set_txpreamble(struct ural_softc *); 154238384Sjkimstatic void ural_set_basicrates(struct ural_softc *, 155280304Sjkim const struct ieee80211_channel *); 156280304Sjkimstatic void ural_set_bssid(struct ural_softc *, const uint8_t *); 157280304Sjkimstatic void ural_set_macaddr(struct ural_softc *, uint8_t *); 158280304Sjkimstatic void ural_update_promisc(struct ifnet *); 159238384Sjkimstatic const char *ural_get_rf(int); 160238384Sjkimstatic void ural_read_eeprom(struct ural_softc *); 161238384Sjkimstatic int ural_bbp_init(struct ural_softc *); 162238384Sjkimstatic void ural_set_txantenna(struct ural_softc *, int); 163238384Sjkimstatic void ural_set_rxantenna(struct ural_softc *, int); 164238384Sjkimstatic void ural_init(void *); 165280304Sjkimstatic int ural_raw_xmit(struct ieee80211_node *, struct mbuf *, 166280304Sjkim const struct ieee80211_bpf_params *); 167280304Sjkimstatic void ural_amrr_start(struct ural_softc *, 168238384Sjkim struct ieee80211_node *); 169280304Sjkimstatic void ural_amrr_timeout(void *); 170238384Sjkimstatic int ural_pause(struct ural_softc *sc, int timeout); 171238384Sjkimstatic void ural_queue_command(struct ural_softc *, 172238384Sjkim usb2_proc_callback_t *, struct usb2_proc_msg *, 173238384Sjkim struct usb2_proc_msg *); 174280304Sjkim 175238384Sjkim/* 176280304Sjkim * Default values for MAC registers; values taken from the reference driver. 177280304Sjkim */ 178238384Sjkimstatic const struct { 179280304Sjkim uint16_t reg; 180280304Sjkim uint16_t val; 181280304Sjkim} ural_def_mac[] = { 182280304Sjkim { RAL_TXRX_CSR5, 0x8c8d }, 183238384Sjkim { RAL_TXRX_CSR6, 0x8b8a }, 184280304Sjkim { RAL_TXRX_CSR7, 0x8687 }, 185280304Sjkim { RAL_TXRX_CSR8, 0x0085 }, 186280304Sjkim { RAL_MAC_CSR13, 0x1111 }, 187280304Sjkim { RAL_MAC_CSR14, 0x1e11 }, 188280304Sjkim { RAL_TXRX_CSR21, 0xe78f }, 189238384Sjkim { RAL_MAC_CSR9, 0xff1d }, 190280304Sjkim { RAL_MAC_CSR11, 0x0002 }, 191280304Sjkim { RAL_MAC_CSR22, 0x0053 }, 192280304Sjkim { RAL_MAC_CSR15, 0x0000 }, 193280304Sjkim { RAL_MAC_CSR8, RAL_FRAME_SIZE }, 194280304Sjkim { RAL_TXRX_CSR19, 0x0000 }, 195280304Sjkim { RAL_TXRX_CSR18, 0x005a }, 196280304Sjkim { RAL_PHY_CSR2, 0x0000 }, 197280304Sjkim { RAL_TXRX_CSR0, 0x1ec0 }, 198280304Sjkim { RAL_PHY_CSR4, 0x000f } 199280304Sjkim}; 200238384Sjkim 201280304Sjkim/* 202280304Sjkim * Default values for BBP registers; values taken from the reference driver. 203238384Sjkim */ 204238384Sjkimstatic const struct { 205280304Sjkim uint8_t reg; 206238384Sjkim uint8_t val; 207238384Sjkim} ural_def_bbp[] = { 208280304Sjkim { 3, 0x02 }, 209238384Sjkim { 4, 0x19 }, 210280304Sjkim { 14, 0x1c }, 211238384Sjkim { 15, 0x30 }, 212280304Sjkim { 16, 0xac }, 213280304Sjkim { 17, 0x48 }, 214280304Sjkim { 18, 0x18 }, 215238384Sjkim { 19, 0xff }, 216280304Sjkim { 20, 0x1e }, 217280304Sjkim { 21, 0x08 }, 218280304Sjkim { 22, 0x08 }, 219280304Sjkim { 23, 0x08 }, 220238384Sjkim { 24, 0x80 }, 221280304Sjkim { 25, 0x50 }, 222238384Sjkim { 26, 0x08 }, 223238384Sjkim { 27, 0x23 }, 224280304Sjkim { 30, 0x10 }, 225238384Sjkim { 31, 0x2b }, 226238384Sjkim { 32, 0xb9 }, 227280304Sjkim { 34, 0x12 }, 228238384Sjkim { 35, 0x50 }, 229280304Sjkim { 39, 0xc4 }, 230238384Sjkim { 40, 0x02 }, 231238384Sjkim { 41, 0x60 }, 232280304Sjkim { 53, 0x10 }, 233280304Sjkim { 54, 0x18 }, 234280304Sjkim { 56, 0x08 }, 235238384Sjkim { 57, 0x10 }, 236280304Sjkim { 58, 0x08 }, 237280304Sjkim { 61, 0x60 }, 238238384Sjkim { 62, 0x10 }, 239280304Sjkim { 75, 0xff } 240280304Sjkim}; 241280304Sjkim 242238384Sjkim/* 243280304Sjkim * Default values for RF register R2 indexed by channel numbers. 244280304Sjkim */ 245280304Sjkimstatic const uint32_t ural_rf2522_r2[] = { 246238384Sjkim 0x307f6, 0x307fb, 0x30800, 0x30805, 0x3080a, 0x3080f, 0x30814, 247280304Sjkim 0x30819, 0x3081e, 0x30823, 0x30828, 0x3082d, 0x30832, 0x3083e 248238384Sjkim}; 249238384Sjkim 250238384Sjkimstatic const uint32_t ural_rf2523_r2[] = { 251280304Sjkim 0x00327, 0x00328, 0x00329, 0x0032a, 0x0032b, 0x0032c, 0x0032d, 252280304Sjkim 0x0032e, 0x0032f, 0x00340, 0x00341, 0x00342, 0x00343, 0x00346 253238384Sjkim}; 254280304Sjkim 255238384Sjkimstatic const uint32_t ural_rf2524_r2[] = { 256280304Sjkim 0x00327, 0x00328, 0x00329, 0x0032a, 0x0032b, 0x0032c, 0x0032d, 257280304Sjkim 0x0032e, 0x0032f, 0x00340, 0x00341, 0x00342, 0x00343, 0x00346 258280304Sjkim}; 259280304Sjkim 260280304Sjkimstatic const uint32_t ural_rf2525_r2[] = { 261280304Sjkim 0x20327, 0x20328, 0x20329, 0x2032a, 0x2032b, 0x2032c, 0x2032d, 262280304Sjkim 0x2032e, 0x2032f, 0x20340, 0x20341, 0x20342, 0x20343, 0x20346 263280304Sjkim}; 264280304Sjkim 265280304Sjkimstatic const uint32_t ural_rf2525_hi_r2[] = { 266280304Sjkim 0x2032f, 0x20340, 0x20341, 0x20342, 0x20343, 0x20344, 0x20345, 267280304Sjkim 0x20346, 0x20347, 0x20348, 0x20349, 0x2034a, 0x2034b, 0x2034e 268280304Sjkim}; 269280304Sjkim 270280304Sjkimstatic const uint32_t ural_rf2525e_r2[] = { 271280304Sjkim 0x2044d, 0x2044e, 0x2044f, 0x20460, 0x20461, 0x20462, 0x20463, 272280304Sjkim 0x20464, 0x20465, 0x20466, 0x20467, 0x20468, 0x20469, 0x2046b 273280304Sjkim}; 274280304Sjkim 275280304Sjkimstatic const uint32_t ural_rf2526_hi_r2[] = { 276280304Sjkim 0x0022a, 0x0022b, 0x0022b, 0x0022c, 0x0022c, 0x0022d, 0x0022d, 277280304Sjkim 0x0022e, 0x0022e, 0x0022f, 0x0022d, 0x00240, 0x00240, 0x00241 278280304Sjkim}; 279280304Sjkim 280280304Sjkimstatic const uint32_t ural_rf2526_r2[] = { 281280304Sjkim 0x00226, 0x00227, 0x00227, 0x00228, 0x00228, 0x00229, 0x00229, 282280304Sjkim 0x0022a, 0x0022a, 0x0022b, 0x0022b, 0x0022c, 0x0022c, 0x0022d 283280304Sjkim}; 284238384Sjkim 285238384Sjkim/* 286238384Sjkim * For dual-band RF, RF registers R1 and R4 also depend on channel number; 287238384Sjkim * values taken from the reference driver. 288238384Sjkim */ 289238384Sjkimstatic const struct { 290238384Sjkim uint8_t chan; 291238384Sjkim uint32_t r1; 292238384Sjkim uint32_t r2; 293280304Sjkim uint32_t r4; 294238384Sjkim} ural_rf5222[] = { 295280304Sjkim { 1, 0x08808, 0x0044d, 0x00282 }, 296238384Sjkim { 2, 0x08808, 0x0044e, 0x00282 }, 297238384Sjkim { 3, 0x08808, 0x0044f, 0x00282 }, 298238384Sjkim { 4, 0x08808, 0x00460, 0x00282 }, 299238384Sjkim { 5, 0x08808, 0x00461, 0x00282 }, 300238384Sjkim { 6, 0x08808, 0x00462, 0x00282 }, 301238384Sjkim { 7, 0x08808, 0x00463, 0x00282 }, 302238384Sjkim { 8, 0x08808, 0x00464, 0x00282 }, 303238384Sjkim { 9, 0x08808, 0x00465, 0x00282 }, 304238384Sjkim { 10, 0x08808, 0x00466, 0x00282 }, 305280304Sjkim { 11, 0x08808, 0x00467, 0x00282 }, 306238384Sjkim { 12, 0x08808, 0x00468, 0x00282 }, 307238384Sjkim { 13, 0x08808, 0x00469, 0x00282 }, 308238384Sjkim { 14, 0x08808, 0x0046b, 0x00286 }, 309238384Sjkim 310238384Sjkim { 36, 0x08804, 0x06225, 0x00287 }, 311238384Sjkim { 40, 0x08804, 0x06226, 0x00287 }, 312238384Sjkim { 44, 0x08804, 0x06227, 0x00287 }, 313280304Sjkim { 48, 0x08804, 0x06228, 0x00287 }, 314280304Sjkim { 52, 0x08804, 0x06229, 0x00287 }, 315280304Sjkim { 56, 0x08804, 0x0622a, 0x00287 }, 316280304Sjkim { 60, 0x08804, 0x0622b, 0x00287 }, 317238384Sjkim { 64, 0x08804, 0x0622c, 0x00287 }, 318280304Sjkim 319238384Sjkim { 100, 0x08804, 0x02200, 0x00283 }, 320280304Sjkim { 104, 0x08804, 0x02201, 0x00283 }, 321280304Sjkim { 108, 0x08804, 0x02202, 0x00283 }, 322280304Sjkim { 112, 0x08804, 0x02203, 0x00283 }, 323280304Sjkim { 116, 0x08804, 0x02204, 0x00283 }, 324280304Sjkim { 120, 0x08804, 0x02205, 0x00283 }, 325280304Sjkim { 124, 0x08804, 0x02206, 0x00283 }, 326280304Sjkim { 128, 0x08804, 0x02207, 0x00283 }, 327280304Sjkim { 132, 0x08804, 0x02208, 0x00283 }, 328280304Sjkim { 136, 0x08804, 0x02209, 0x00283 }, 329280304Sjkim { 140, 0x08804, 0x0220a, 0x00283 }, 330280304Sjkim 331280304Sjkim { 149, 0x08808, 0x02429, 0x00281 }, 332280304Sjkim { 153, 0x08808, 0x0242b, 0x00281 }, 333280304Sjkim { 157, 0x08808, 0x0242d, 0x00281 }, 334280304Sjkim { 161, 0x08808, 0x0242f, 0x00281 } 335280304Sjkim}; 336280304Sjkim 337280304Sjkimstatic const struct usb2_config ural_config[URAL_N_TRANSFER] = { 338238384Sjkim [URAL_BULK_WR] = { 339238384Sjkim .type = UE_BULK, 340280304Sjkim .endpoint = UE_ADDR_ANY, 341280304Sjkim .direction = UE_DIR_OUT, 342280304Sjkim .mh.bufsize = (RAL_FRAME_SIZE + RAL_TX_DESC_SIZE + 4), 343280304Sjkim .mh.flags = {.pipe_bof = 1,.force_short_xfer = 1,}, 344238384Sjkim .mh.callback = ural_bulk_write_callback, 345280304Sjkim .mh.timeout = 5000, /* ms */ 346280304Sjkim }, 347238384Sjkim [URAL_BULK_RD] = { 348280304Sjkim .type = UE_BULK, 349280304Sjkim .endpoint = UE_ADDR_ANY, 350280304Sjkim .direction = UE_DIR_IN, 351238384Sjkim .mh.bufsize = (RAL_FRAME_SIZE + RAL_RX_DESC_SIZE), 352280304Sjkim .mh.flags = {.pipe_bof = 1,.short_xfer_ok = 1,}, 353280304Sjkim .mh.callback = ural_bulk_read_callback, 354280304Sjkim }, 355280304Sjkim}; 356280304Sjkim 357280304Sjkimstatic device_probe_t ural_match; 358280304Sjkimstatic device_attach_t ural_attach; 359280304Sjkimstatic device_detach_t ural_detach; 360280304Sjkim 361280304Sjkimstatic device_method_t ural_methods[] = { 362280304Sjkim /* Device interface */ 363238384Sjkim DEVMETHOD(device_probe, ural_match), 364280304Sjkim DEVMETHOD(device_attach, ural_attach), 365280304Sjkim DEVMETHOD(device_detach, ural_detach), 366280304Sjkim 367280304Sjkim { 0, 0 } 368280304Sjkim}; 369238384Sjkim 370280304Sjkimstatic driver_t ural_driver = { 371280304Sjkim .name = "ural", 372280304Sjkim .methods = ural_methods, 373280304Sjkim .size = sizeof(struct ural_softc), 374238384Sjkim}; 375280304Sjkim 376280304Sjkimstatic devclass_t ural_devclass; 377280304Sjkim 378238384SjkimDRIVER_MODULE(ural, uhub, ural_driver, ural_devclass, NULL, 0); 379280304SjkimMODULE_DEPEND(ural, usb, 1, 1, 1); 380238384SjkimMODULE_DEPEND(ural, wlan, 1, 1, 1); 381238384SjkimMODULE_DEPEND(ural, wlan_amrr, 1, 1, 1); 382280304Sjkim 383280304Sjkimstatic int 384238384Sjkimural_match(device_t self) 385280304Sjkim{ 386238384Sjkim struct usb2_attach_arg *uaa = device_get_ivars(self); 387280304Sjkim 388280304Sjkim if (uaa->usb2_mode != USB_MODE_HOST) 389238384Sjkim return (ENXIO); 390280304Sjkim if (uaa->info.bConfigIndex != 0) 391280304Sjkim return (ENXIO); 392280304Sjkim if (uaa->info.bIfaceIndex != RAL_IFACE_INDEX) 393280304Sjkim return (ENXIO); 394238384Sjkim 395280304Sjkim return (usb2_lookup_id_by_uaa(ural_devs, sizeof(ural_devs), uaa)); 396280304Sjkim} 397238384Sjkim 398280304Sjkimstatic int 399280304Sjkimural_attach(device_t self) 400280304Sjkim{ 401280304Sjkim struct usb2_attach_arg *uaa = device_get_ivars(self); 402280304Sjkim struct ural_softc *sc = device_get_softc(self); 403238384Sjkim int error; 404280304Sjkim uint8_t iface_index; 405238384Sjkim 406238384Sjkim device_set_usb2_desc(self); 407280304Sjkim sc->sc_udev = uaa->device; 408238384Sjkim sc->sc_dev = self; 409238384Sjkim 410238384Sjkim mtx_init(&sc->sc_mtx, device_get_nameunit(self), 411238384Sjkim MTX_NETWORK_LOCK, MTX_DEF); 412238384Sjkim 413238384Sjkim cv_init(&sc->sc_cmd_cv, "wtxdone"); 414238384Sjkim 415238384Sjkim iface_index = RAL_IFACE_INDEX; 416238384Sjkim error = usb2_transfer_setup(uaa->device, 417280304Sjkim &iface_index, sc->sc_xfer, ural_config, 418238384Sjkim URAL_N_TRANSFER, sc, &sc->sc_mtx); 419280304Sjkim if (error) { 420280304Sjkim device_printf(self, "could not allocate USB transfers, " 421280304Sjkim "err=%s\n", usb2_errstr(error)); 422280304Sjkim goto detach; 423280304Sjkim } 424280304Sjkim error = usb2_proc_create(&sc->sc_tq, &sc->sc_mtx, 425280304Sjkim device_get_nameunit(self), USB_PRI_MED); 426280304Sjkim if (error) { 427280304Sjkim device_printf(self, "could not setup config thread!\n"); 428280304Sjkim goto detach; 429238384Sjkim } 430238384Sjkim 431238384Sjkim /* fork rest of the attach code */ 432280304Sjkim RAL_LOCK(sc); 433280304Sjkim ural_queue_command(sc, ural_attach_post, 434280304Sjkim &sc->sc_synctask[0].hdr, 435238384Sjkim &sc->sc_synctask[1].hdr); 436280304Sjkim RAL_UNLOCK(sc); 437280304Sjkim return (0); 438280304Sjkim 439280304Sjkimdetach: 440280304Sjkim ural_detach(self); 441280304Sjkim return (ENXIO); /* failure */ 442280304Sjkim} 443280304Sjkim 444280304Sjkimstatic void 445280304Sjkimural_attach_post(struct usb2_proc_msg *pm) 446280304Sjkim{ 447280304Sjkim struct ural_task *task = (struct ural_task *)pm; 448280304Sjkim struct ural_softc *sc = task->sc; 449280304Sjkim struct ifnet *ifp; 450238384Sjkim struct ieee80211com *ic; 451238384Sjkim uint8_t bands; 452238384Sjkim 453280304Sjkim /* retrieve RT2570 rev. no */ 454280304Sjkim sc->asic_rev = ural_read(sc, RAL_MAC_CSR0); 455280304Sjkim 456280304Sjkim /* retrieve MAC address and various other things from EEPROM */ 457280304Sjkim ural_read_eeprom(sc); 458280304Sjkim 459280304Sjkim /* XXX Async attach race */ 460280304Sjkim if (usb2_proc_is_gone(&sc->sc_tq)) 461280304Sjkim return; 462238384Sjkim 463280304Sjkim RAL_UNLOCK(sc); 464238384Sjkim 465280304Sjkim device_printf(sc->sc_dev, "MAC/BBP RT2570 (rev 0x%02x), RF %s\n", 466238384Sjkim sc->asic_rev, ural_get_rf(sc->rf_rev)); 467280304Sjkim 468280304Sjkim ifp = sc->sc_ifp = if_alloc(IFT_IEEE80211); 469280304Sjkim if (ifp == NULL) { 470280304Sjkim device_printf(sc->sc_dev, "can not if_alloc()\n"); 471238384Sjkim RAL_LOCK(sc); 472280304Sjkim return; 473238384Sjkim } 474238384Sjkim ic = ifp->if_l2com; 475280304Sjkim 476280304Sjkim ifp->if_softc = sc; 477280304Sjkim if_initname(ifp, "ural", device_get_unit(sc->sc_dev)); 478280304Sjkim ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 479280304Sjkim ifp->if_init = ural_init; 480280304Sjkim ifp->if_ioctl = ural_ioctl; 481280304Sjkim ifp->if_start = ural_start; 482280304Sjkim IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN); 483280304Sjkim ifp->if_snd.ifq_drv_maxlen = IFQ_MAXLEN; 484280304Sjkim IFQ_SET_READY(&ifp->if_snd); 485280304Sjkim 486280304Sjkim ic->ic_ifp = ifp; 487238384Sjkim ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 488280304Sjkim 489280304Sjkim /* set device capabilities */ 490238384Sjkim ic->ic_caps = 491280304Sjkim IEEE80211_C_STA /* station mode supported */ 492280304Sjkim | IEEE80211_C_IBSS /* IBSS mode supported */ 493280304Sjkim | IEEE80211_C_MONITOR /* monitor mode supported */ 494280304Sjkim | IEEE80211_C_HOSTAP /* HostAp mode supported */ 495238384Sjkim | IEEE80211_C_TXPMGT /* tx power management */ 496280304Sjkim | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 497238384Sjkim | IEEE80211_C_SHSLOT /* short slot time supported */ 498238384Sjkim | IEEE80211_C_BGSCAN /* bg scanning supported */ 499280304Sjkim | IEEE80211_C_WPA /* 802.11i */ 500238384Sjkim ; 501238384Sjkim 502238384Sjkim bands = 0; 503238384Sjkim setbit(&bands, IEEE80211_MODE_11B); 504238384Sjkim setbit(&bands, IEEE80211_MODE_11G); 505238384Sjkim if (sc->rf_rev == RAL_RF_5222) 506238384Sjkim setbit(&bands, IEEE80211_MODE_11A); 507280304Sjkim ieee80211_init_channels(ic, NULL, &bands); 508280304Sjkim 509280304Sjkim ieee80211_ifattach(ic, sc->sc_bssid); 510280304Sjkim ic->ic_update_promisc = ural_update_promisc; 511238384Sjkim ic->ic_newassoc = ural_newassoc; 512280304Sjkim ic->ic_raw_xmit = ural_raw_xmit; 513280304Sjkim ic->ic_node_alloc = ural_node_alloc; 514280304Sjkim ic->ic_scan_start = ural_scan_start; 515238384Sjkim ic->ic_scan_end = ural_scan_end; 516280304Sjkim ic->ic_set_channel = ural_set_channel; 517280304Sjkim 518280304Sjkim ic->ic_vap_create = ural_vap_create; 519280304Sjkim ic->ic_vap_delete = ural_vap_delete; 520280304Sjkim 521280304Sjkim bpfattach(ifp, DLT_IEEE802_11_RADIO, 522280304Sjkim sizeof (struct ieee80211_frame) + sizeof(sc->sc_txtap)); 523280304Sjkim 524280304Sjkim sc->sc_rxtap_len = sizeof sc->sc_rxtap; 525280304Sjkim sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 526238384Sjkim sc->sc_rxtap.wr_ihdr.it_present = htole32(RAL_RX_RADIOTAP_PRESENT); 527238384Sjkim 528238384Sjkim sc->sc_txtap_len = sizeof sc->sc_txtap; 529238384Sjkim sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 530238384Sjkim sc->sc_txtap.wt_ihdr.it_present = htole32(RAL_TX_RADIOTAP_PRESENT); 531238384Sjkim 532238384Sjkim if (bootverbose) 533280304Sjkim ieee80211_announce(ic); 534280304Sjkim 535280304Sjkim RAL_LOCK(sc); 536280304Sjkim} 537238384Sjkim 538238384Sjkimstatic int 539280304Sjkimural_detach(device_t self) 540280304Sjkim{ 541280304Sjkim struct ural_softc *sc = device_get_softc(self); 542280304Sjkim struct ifnet *ifp = sc->sc_ifp; 543280304Sjkim struct ieee80211com *ic; 544238384Sjkim 545280304Sjkim /* wait for any post attach or other command to complete */ 546280304Sjkim usb2_proc_drain(&sc->sc_tq); 547280304Sjkim 548280304Sjkim /* stop all USB transfers */ 549280304Sjkim usb2_transfer_unsetup(sc->sc_xfer, URAL_N_TRANSFER); 550280304Sjkim usb2_proc_free(&sc->sc_tq); 551280304Sjkim 552280304Sjkim /* free TX list, if any */ 553280304Sjkim RAL_LOCK(sc); 554280304Sjkim ural_unsetup_tx_list(sc); 555280304Sjkim RAL_UNLOCK(sc); 556280304Sjkim 557280304Sjkim if (ifp) { 558238384Sjkim ic = ifp->if_l2com; 559238384Sjkim bpfdetach(ifp); 560238384Sjkim ieee80211_ifdetach(ic); 561238384Sjkim if_free(ifp); 562280304Sjkim } 563280304Sjkim cv_destroy(&sc->sc_cmd_cv); 564280304Sjkim mtx_destroy(&sc->sc_mtx); 565280304Sjkim 566280304Sjkim return (0); 567280304Sjkim} 568280304Sjkim 569280304Sjkimstatic usb2_error_t 570280304Sjkimural_do_request(struct ural_softc *sc, 571280304Sjkim struct usb2_device_request *req, void *data) 572280304Sjkim{ 573280304Sjkim usb2_error_t err; 574280304Sjkim int ntries = 10; 575280304Sjkim 576280304Sjkim while (ntries--) { 577280304Sjkim err = usb2_do_request_proc(sc->sc_udev, &sc->sc_tq, 578280304Sjkim req, data, 0, NULL, 250 /* ms */); 579280304Sjkim if (err == 0) 580280304Sjkim break; 581280304Sjkim 582280304Sjkim DPRINTFN(1, "Control request failed, %s (retrying)\n", 583280304Sjkim usb2_errstr(err)); 584280304Sjkim if (ural_pause(sc, hz / 100)) 585280304Sjkim break; 586280304Sjkim } 587280304Sjkim return (err); 588280304Sjkim} 589280304Sjkim 590280304Sjkimstatic struct ieee80211vap * 591280304Sjkimural_vap_create(struct ieee80211com *ic, 592280304Sjkim const char name[IFNAMSIZ], int unit, int opmode, int flags, 593280304Sjkim const uint8_t bssid[IEEE80211_ADDR_LEN], 594280304Sjkim const uint8_t mac[IEEE80211_ADDR_LEN]) 595280304Sjkim{ 596280304Sjkim struct ural_softc *sc = ic->ic_ifp->if_softc; 597280304Sjkim struct ural_vap *uvp; 598280304Sjkim struct ieee80211vap *vap; 599280304Sjkim 600280304Sjkim if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */ 601280304Sjkim return NULL; 602280304Sjkim uvp = (struct ural_vap *) malloc(sizeof(struct ural_vap), 603280304Sjkim M_80211_VAP, M_NOWAIT | M_ZERO); 604280304Sjkim if (uvp == NULL) 605280304Sjkim return NULL; 606280304Sjkim vap = &uvp->vap; 607280304Sjkim /* enable s/w bmiss handling for sta mode */ 608238384Sjkim ieee80211_vap_setup(ic, vap, name, unit, opmode, 609238384Sjkim flags | IEEE80211_CLONE_NOBEACONS, bssid, mac); 610280304Sjkim 611280304Sjkim /* override state transition machine */ 612280304Sjkim uvp->newstate = vap->iv_newstate; 613280304Sjkim vap->iv_newstate = ural_newstate; 614280304Sjkim 615280304Sjkim uvp->sc = sc; 616280304Sjkim usb2_callout_init_mtx(&uvp->amrr_ch, &sc->sc_mtx, 0); 617280304Sjkim ieee80211_amrr_init(&uvp->amrr, vap, 618280304Sjkim IEEE80211_AMRR_MIN_SUCCESS_THRESHOLD, 619280304Sjkim IEEE80211_AMRR_MAX_SUCCESS_THRESHOLD, 620280304Sjkim 1000 /* 1 sec */); 621280304Sjkim 622280304Sjkim /* complete setup */ 623280304Sjkim ieee80211_vap_attach(vap, ieee80211_media_change, ieee80211_media_status); 624238384Sjkim ic->ic_opmode = opmode; 625238384Sjkim return vap; 626280304Sjkim} 627280304Sjkim 628280304Sjkimstatic void 629238384Sjkimural_flush_task(struct usb2_proc_msg *pm) 630280304Sjkim{ 631280304Sjkim /* nothing to do */ 632238384Sjkim} 633280304Sjkim 634280304Sjkimstatic void 635280304Sjkimural_vap_delete(struct ieee80211vap *vap) 636280304Sjkim{ 637280304Sjkim struct ural_vap *uvp = URAL_VAP(vap); 638280304Sjkim struct ural_softc *sc = uvp->sc; 639280304Sjkim 640280304Sjkim RAL_LOCK(sc); 641280304Sjkim /* wait for any pending tasks to complete */ 642280304Sjkim ural_queue_command(sc, ural_flush_task, 643280304Sjkim &sc->sc_synctask[0].hdr, 644280304Sjkim &sc->sc_synctask[1].hdr); 645280304Sjkim RAL_UNLOCK(sc); 646280304Sjkim 647280304Sjkim usb2_callout_drain(&uvp->amrr_ch); 648280304Sjkim ieee80211_amrr_cleanup(&uvp->amrr); 649280304Sjkim ieee80211_vap_detach(vap); 650280304Sjkim free(uvp, M_80211_VAP); 651280304Sjkim} 652280304Sjkim 653280304Sjkimstatic void 654280304Sjkimural_tx_free(struct ural_tx_data *data, int txerr) 655280304Sjkim{ 656280304Sjkim struct ural_softc *sc = data->sc; 657280304Sjkim 658280304Sjkim if (data->m != NULL) { 659238384Sjkim if (data->m->m_flags & M_TXCB) 660280304Sjkim ieee80211_process_callback(data->ni, data->m, 661280304Sjkim txerr ? ETIMEDOUT : 0); 662280304Sjkim m_freem(data->m); 663280304Sjkim data->m = NULL; 664238384Sjkim 665280304Sjkim ieee80211_free_node(data->ni); 666280304Sjkim data->ni = NULL; 667280304Sjkim } 668280304Sjkim STAILQ_INSERT_TAIL(&sc->tx_free, data, next); 669280304Sjkim sc->tx_nfree++; 670238384Sjkim} 671280304Sjkim 672280304Sjkimstatic void 673238384Sjkimural_setup_tx_list(struct ural_softc *sc) 674238384Sjkim{ 675238384Sjkim struct ural_tx_data *data; 676280304Sjkim int i; 677238384Sjkim 678280304Sjkim sc->tx_nfree = 0; 679238384Sjkim STAILQ_INIT(&sc->tx_q); 680280304Sjkim STAILQ_INIT(&sc->tx_free); 681280304Sjkim 682280304Sjkim for (i = 0; i < RAL_TX_LIST_COUNT; i++) { 683280304Sjkim data = &sc->tx_data[i]; 684238384Sjkim 685280304Sjkim data->sc = sc; 686280304Sjkim STAILQ_INSERT_TAIL(&sc->tx_free, data, next); 687280304Sjkim sc->tx_nfree++; 688280304Sjkim } 689238384Sjkim} 690280304Sjkim 691280304Sjkimstatic void 692280304Sjkimural_unsetup_tx_list(struct ural_softc *sc) 693280304Sjkim{ 694280304Sjkim struct ural_tx_data *data; 695280304Sjkim int i; 696280304Sjkim 697280304Sjkim /* make sure any subsequent use of the queues will fail */ 698280304Sjkim sc->tx_nfree = 0; 699280304Sjkim STAILQ_INIT(&sc->tx_q); 700280304Sjkim STAILQ_INIT(&sc->tx_free); 701280304Sjkim 702280304Sjkim /* free up all node references and mbufs */ 703280304Sjkim for (i = 0; i < RAL_TX_LIST_COUNT; i++) { 704280304Sjkim data = &sc->tx_data[i]; 705280304Sjkim 706280304Sjkim if (data->m != NULL) { 707280304Sjkim m_freem(data->m); 708280304Sjkim data->m = NULL; 709238384Sjkim } 710238384Sjkim if (data->ni != NULL) { 711280304Sjkim ieee80211_free_node(data->ni); 712280304Sjkim data->ni = NULL; 713280304Sjkim } 714280304Sjkim } 715238384Sjkim} 716280304Sjkim 717280304Sjkimstatic void 718280304Sjkimural_task(struct usb2_proc_msg *pm) 719280304Sjkim{ 720238384Sjkim struct ural_task *task = (struct ural_task *)pm; 721280304Sjkim struct ural_softc *sc = task->sc; 722280304Sjkim struct ifnet *ifp = sc->sc_ifp; 723280304Sjkim struct ieee80211com *ic = ifp->if_l2com; 724280304Sjkim struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 725238384Sjkim struct ural_vap *uvp = URAL_VAP(vap); 726238384Sjkim const struct ieee80211_txparam *tp; 727280304Sjkim enum ieee80211_state ostate; 728280304Sjkim struct ieee80211_node *ni; 729238384Sjkim struct mbuf *m; 730280304Sjkim 731280304Sjkim ostate = vap->iv_state; 732280304Sjkim 733280304Sjkim switch (sc->sc_state) { 734280304Sjkim case IEEE80211_S_INIT: 735238384Sjkim if (ostate == IEEE80211_S_RUN) { 736280304Sjkim /* abort TSF synchronization */ 737280304Sjkim ural_write(sc, RAL_TXRX_CSR19, 0); 738280304Sjkim 739280304Sjkim /* force tx led to stop blinking */ 740280304Sjkim ural_write(sc, RAL_MAC_CSR20, 0); 741280304Sjkim } 742280304Sjkim break; 743280304Sjkim 744280304Sjkim case IEEE80211_S_RUN: 745280304Sjkim ni = vap->iv_bss; 746280304Sjkim 747280304Sjkim if (vap->iv_opmode != IEEE80211_M_MONITOR) { 748280304Sjkim ural_update_slot(ic->ic_ifp); 749280304Sjkim ural_set_txpreamble(sc); 750238384Sjkim ural_set_basicrates(sc, ic->ic_bsschan); 751280304Sjkim IEEE80211_ADDR_COPY(sc->sc_bssid, ni->ni_bssid); 752280304Sjkim ural_set_bssid(sc, sc->sc_bssid); 753280304Sjkim } 754280304Sjkim 755280304Sjkim if (vap->iv_opmode == IEEE80211_M_HOSTAP || 756280304Sjkim vap->iv_opmode == IEEE80211_M_IBSS) { 757280304Sjkim m = ieee80211_beacon_alloc(ni, &uvp->bo); 758280304Sjkim if (m == NULL) { 759280304Sjkim device_printf(sc->sc_dev, 760280304Sjkim "could not allocate beacon\n"); 761280304Sjkim return; 762280304Sjkim } 763238384Sjkim 764280304Sjkim if (ural_tx_bcn(sc, m, ni) != 0) { 765280304Sjkim device_printf(sc->sc_dev, 766280304Sjkim "could not send beacon\n"); 767280304Sjkim return; 768280304Sjkim } 769280304Sjkim } 770280304Sjkim 771280304Sjkim /* make tx led blink on tx (controlled by ASIC) */ 772280304Sjkim ural_write(sc, RAL_MAC_CSR20, 1); 773280304Sjkim 774280304Sjkim if (vap->iv_opmode != IEEE80211_M_MONITOR) 775280304Sjkim ural_enable_tsf_sync(sc); 776238384Sjkim 777280304Sjkim /* enable automatic rate adaptation */ 778280304Sjkim tp = &vap->iv_txparms[ieee80211_chan2mode(ic->ic_bsschan)]; 779280304Sjkim if (tp->ucastrate == IEEE80211_FIXED_RATE_NONE) 780280304Sjkim ural_amrr_start(sc, ni); 781280304Sjkim 782238384Sjkim break; 783280304Sjkim 784238384Sjkim default: 785238384Sjkim break; 786238384Sjkim } 787238384Sjkim 788280304Sjkim RAL_UNLOCK(sc); 789280304Sjkim IEEE80211_LOCK(ic); 790238384Sjkim uvp->newstate(vap, sc->sc_state, sc->sc_arg); 791280304Sjkim if (vap->iv_newstate_cb != NULL) 792280304Sjkim vap->iv_newstate_cb(vap, sc->sc_state, sc->sc_arg); 793238384Sjkim IEEE80211_UNLOCK(ic); 794280304Sjkim RAL_LOCK(sc); 795280304Sjkim} 796238384Sjkim 797280304Sjkimstatic void 798280304Sjkimural_scantask(struct usb2_proc_msg *pm) 799238384Sjkim{ 800280304Sjkim struct ural_task *task = (struct ural_task *)pm; 801280304Sjkim struct ural_softc *sc = task->sc; 802280304Sjkim struct ifnet *ifp = sc->sc_ifp; 803280304Sjkim struct ieee80211com *ic = ifp->if_l2com; 804280304Sjkim 805280304Sjkim RAL_LOCK_ASSERT(sc, MA_OWNED); 806280304Sjkim 807238384Sjkim switch (sc->sc_scan_action) { 808280304Sjkim case URAL_SCAN_START: 809280304Sjkim /* abort TSF synchronization */ 810280304Sjkim DPRINTF("starting scan\n"); 811280304Sjkim ural_write(sc, RAL_TXRX_CSR19, 0); 812280304Sjkim ural_set_bssid(sc, ifp->if_broadcastaddr); 813280304Sjkim break; 814280304Sjkim 815280304Sjkim case URAL_SET_CHANNEL: 816238384Sjkim ural_set_chan(sc, ic->ic_curchan); 817280304Sjkim break; 818280304Sjkim 819280304Sjkim default: /* URAL_SCAN_END */ 820280304Sjkim DPRINTF("stopping scan\n"); 821280304Sjkim ural_enable_tsf_sync(sc); 822280304Sjkim ural_set_bssid(sc, sc->sc_bssid); 823280304Sjkim break; 824280304Sjkim } 825280304Sjkim} 826280304Sjkim 827280304Sjkimstatic int 828280304Sjkimural_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 829280304Sjkim{ 830280304Sjkim struct ural_vap *uvp = URAL_VAP(vap); 831280304Sjkim struct ieee80211com *ic = vap->iv_ic; 832280304Sjkim struct ural_softc *sc = ic->ic_ifp->if_softc; 833280304Sjkim 834280304Sjkim DPRINTF("%s -> %s\n", 835280304Sjkim ieee80211_state_name[vap->iv_state], 836280304Sjkim ieee80211_state_name[nstate]); 837280304Sjkim 838280304Sjkim RAL_LOCK(sc); 839280304Sjkim usb2_callout_stop(&uvp->amrr_ch); 840238384Sjkim 841280304Sjkim /* do it in a process context */ 842280304Sjkim sc->sc_state = nstate; 843280304Sjkim sc->sc_arg = arg; 844280304Sjkim RAL_UNLOCK(sc); 845238384Sjkim 846280304Sjkim if (nstate == IEEE80211_S_INIT) { 847280304Sjkim uvp->newstate(vap, nstate, arg); 848280304Sjkim return 0; 849280304Sjkim } else { 850280304Sjkim RAL_LOCK(sc); 851280304Sjkim ural_queue_command(sc, ural_task, &sc->sc_task[0].hdr, 852238384Sjkim &sc->sc_task[1].hdr); 853280304Sjkim RAL_UNLOCK(sc); 854238384Sjkim return EINPROGRESS; 855238384Sjkim } 856280304Sjkim} 857238384Sjkim 858238384Sjkim 859238384Sjkimstatic void 860238384Sjkimural_bulk_write_callback(struct usb2_xfer *xfer) 861238384Sjkim{ 862238384Sjkim struct ural_softc *sc = xfer->priv_sc; 863238384Sjkim struct ifnet *ifp = sc->sc_ifp; 864280304Sjkim struct ieee80211com *ic = ifp->if_l2com; 865238384Sjkim struct ieee80211_channel *c = ic->ic_curchan; 866280304Sjkim struct ural_tx_data *data; 867280304Sjkim struct mbuf *m; 868238384Sjkim unsigned int len; 869280304Sjkim 870280304Sjkim /* wakeup waiting command, if any */ 871238384Sjkim if (sc->sc_last_task != NULL) 872280304Sjkim cv_signal(&sc->sc_cmd_cv); 873280304Sjkim 874280304Sjkim switch (USB_GET_STATE(xfer)) { 875280304Sjkim case USB_ST_TRANSFERRED: 876238384Sjkim DPRINTFN(11, "transfer complete, %d bytes\n", xfer->actlen); 877280304Sjkim 878280304Sjkim /* free resources */ 879280304Sjkim data = xfer->priv_fifo; 880280304Sjkim ural_tx_free(data, 0); 881280304Sjkim xfer->priv_fifo = NULL; 882280304Sjkim 883238384Sjkim ifp->if_opackets++; 884280304Sjkim ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 885280304Sjkim 886280304Sjkim /* FALLTHROUGH */ 887280304Sjkim case USB_ST_SETUP: 888280304Sjkimtr_setup: 889280304Sjkim /* wait for command to complete, if any */ 890238384Sjkim if (sc->sc_last_task != NULL) 891280304Sjkim break; 892280304Sjkim 893280304Sjkim data = STAILQ_FIRST(&sc->tx_q); 894280304Sjkim if (data) { 895280304Sjkim STAILQ_REMOVE_HEAD(&sc->tx_q, next); 896238384Sjkim m = data->m; 897280304Sjkim 898280304Sjkim if (m->m_pkthdr.len > (RAL_FRAME_SIZE + RAL_TX_DESC_SIZE)) { 899280304Sjkim DPRINTFN(0, "data overflow, %u bytes\n", 900238384Sjkim m->m_pkthdr.len); 901280304Sjkim m->m_pkthdr.len = (RAL_FRAME_SIZE + RAL_TX_DESC_SIZE); 902238384Sjkim } 903280304Sjkim usb2_copy_in(xfer->frbuffers, 0, &data->desc, 904238384Sjkim RAL_TX_DESC_SIZE); 905238384Sjkim usb2_m_copy_in(xfer->frbuffers, RAL_TX_DESC_SIZE, m, 0, 906280304Sjkim m->m_pkthdr.len); 907280304Sjkim 908280304Sjkim if (bpf_peers_present(ifp->if_bpf)) { 909280304Sjkim struct ural_tx_radiotap_header *tap = &sc->sc_txtap; 910280304Sjkim 911280304Sjkim tap->wt_flags = 0; 912238384Sjkim tap->wt_rate = data->rate; 913280304Sjkim tap->wt_chan_freq = htole16(c->ic_freq); 914280304Sjkim tap->wt_chan_flags = htole16(c->ic_flags); 915280304Sjkim tap->wt_antenna = sc->tx_ant; 916280304Sjkim 917238384Sjkim bpf_mtap2(ifp->if_bpf, tap, sc->sc_txtap_len, m); 918238384Sjkim } 919280304Sjkim 920238384Sjkim /* xfer length needs to be a multiple of two! */ 921280304Sjkim len = (RAL_TX_DESC_SIZE + m->m_pkthdr.len + 1) & ~1; 922280304Sjkim if ((len % 64) == 0) 923280304Sjkim len += 2; 924280304Sjkim 925280304Sjkim DPRINTFN(11, "sending frame len=%u xferlen=%u\n", 926280304Sjkim m->m_pkthdr.len, len); 927238384Sjkim 928280304Sjkim xfer->frlengths[0] = len; 929280304Sjkim xfer->priv_fifo = data; 930280304Sjkim 931280304Sjkim usb2_start_hardware(xfer); 932280304Sjkim } 933238384Sjkim break; 934280304Sjkim 935280304Sjkim default: /* Error */ 936280304Sjkim DPRINTFN(11, "transfer error, %s\n", 937280304Sjkim usb2_errstr(xfer->error)); 938238384Sjkim 939280304Sjkim ifp->if_oerrors++; 940280304Sjkim data = xfer->priv_fifo; 941280304Sjkim if (data != NULL) { 942280304Sjkim ural_tx_free(data, xfer->error); 943280304Sjkim xfer->priv_fifo = NULL; 944280304Sjkim } 945280304Sjkim 946280304Sjkim if (xfer->error == USB_ERR_STALLED) { 947280304Sjkim /* try to clear stall first */ 948280304Sjkim xfer->flags.stall_pipe = 1; 949238384Sjkim goto tr_setup; 950280304Sjkim } 951280304Sjkim if (xfer->error == USB_ERR_TIMEOUT) 952280304Sjkim device_printf(sc->sc_dev, "device timeout\n"); 953280304Sjkim break; 954280304Sjkim } 955238384Sjkim} 956280304Sjkim 957280304Sjkimstatic void 958280304Sjkimural_bulk_read_callback(struct usb2_xfer *xfer) 959280304Sjkim{ 960238384Sjkim struct ural_softc *sc = xfer->priv_sc; 961280304Sjkim struct ifnet *ifp = sc->sc_ifp; 962280304Sjkim struct ieee80211com *ic = ifp->if_l2com; 963280304Sjkim struct ieee80211_node *ni; 964280304Sjkim struct mbuf *m = NULL; 965238384Sjkim uint32_t flags; 966280304Sjkim uint8_t rssi = 0; 967280304Sjkim unsigned int len; 968280304Sjkim 969280304Sjkim switch (USB_GET_STATE(xfer)) { 970280304Sjkim case USB_ST_TRANSFERRED: 971280304Sjkim 972280304Sjkim DPRINTFN(15, "rx done, actlen=%d\n", xfer->actlen); 973280304Sjkim 974280304Sjkim len = xfer->actlen; 975280304Sjkim if (len < RAL_RX_DESC_SIZE + IEEE80211_MIN_LEN) { 976280304Sjkim DPRINTF("%s: xfer too short %d\n", 977238384Sjkim device_get_nameunit(sc->sc_dev), len); 978280304Sjkim ifp->if_ierrors++; 979280304Sjkim goto tr_setup; 980280304Sjkim } 981280304Sjkim 982280304Sjkim len -= RAL_RX_DESC_SIZE; 983280304Sjkim /* rx descriptor is located at the end */ 984280304Sjkim usb2_copy_out(xfer->frbuffers, len, &sc->sc_rx_desc, 985280304Sjkim RAL_RX_DESC_SIZE); 986280304Sjkim 987280304Sjkim rssi = URAL_RSSI(sc->sc_rx_desc.rssi); 988280304Sjkim flags = le32toh(sc->sc_rx_desc.flags); 989280304Sjkim if (flags & (RAL_RX_PHY_ERROR | RAL_RX_CRC_ERROR)) { 990280304Sjkim /* 991280304Sjkim * This should not happen since we did not 992238384Sjkim * request to receive those frames when we 993280304Sjkim * filled RAL_TXRX_CSR2: 994280304Sjkim */ 995238384Sjkim DPRINTFN(5, "PHY or CRC error\n"); 996280304Sjkim ifp->if_ierrors++; 997280304Sjkim goto tr_setup; 998280304Sjkim } 999280304Sjkim 1000280304Sjkim m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1001280304Sjkim if (m == NULL) { 1002238384Sjkim DPRINTF("could not allocate mbuf\n"); 1003280304Sjkim ifp->if_ierrors++; 1004280304Sjkim goto tr_setup; 1005238384Sjkim } 1006280304Sjkim usb2_copy_out(xfer->frbuffers, 0, mtod(m, uint8_t *), len); 1007280304Sjkim 1008280304Sjkim /* finalize mbuf */ 1009280304Sjkim m->m_pkthdr.rcvif = ifp; 1010280304Sjkim m->m_pkthdr.len = m->m_len = (flags >> 16) & 0xfff; 1011238384Sjkim 1012280304Sjkim if (bpf_peers_present(ifp->if_bpf)) { 1013280304Sjkim struct ural_rx_radiotap_header *tap = &sc->sc_rxtap; 1014280304Sjkim 1015280304Sjkim tap->wr_flags = IEEE80211_RADIOTAP_F_FCS; 1016280304Sjkim tap->wr_rate = ieee80211_plcp2rate(sc->sc_rx_desc.rate, 1017280304Sjkim (flags & RAL_RX_OFDM) ? 1018280304Sjkim IEEE80211_T_OFDM : IEEE80211_T_CCK); 1019238384Sjkim tap->wr_chan_freq = htole16(ic->ic_curchan->ic_freq); 1020280304Sjkim tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags); 1021280304Sjkim tap->wr_antenna = sc->rx_ant; 1022238384Sjkim tap->wr_antsignal = rssi; 1023280304Sjkim 1024280304Sjkim bpf_mtap2(ifp->if_bpf, tap, sc->sc_rxtap_len, m); 1025280304Sjkim } 1026280304Sjkim /* Strip trailing 802.11 MAC FCS. */ 1027280304Sjkim m_adj(m, -IEEE80211_CRC_LEN); 1028280304Sjkim 1029280304Sjkim /* FALLTHROUGH */ 1030280304Sjkim case USB_ST_SETUP: 1031238384Sjkimtr_setup: 1032280304Sjkim xfer->frlengths[0] = xfer->max_data_length; 1033238384Sjkim usb2_start_hardware(xfer); 1034280304Sjkim 1035280304Sjkim /* 1036280304Sjkim * At the end of a USB callback it is always safe to unlock 1037280304Sjkim * the private mutex of a device! That is why we do the 1038238384Sjkim * "ieee80211_input" here, and not some lines up! 1039280304Sjkim */ 1040280304Sjkim if (m) { 1041280304Sjkim RAL_UNLOCK(sc); 1042280304Sjkim ni = ieee80211_find_rxnode(ic, 1043238384Sjkim mtod(m, struct ieee80211_frame_min *)); 1044280304Sjkim if (ni != NULL) { 1045280304Sjkim (void) ieee80211_input(ni, m, rssi, 1046280304Sjkim RAL_NOISE_FLOOR, 0); 1047280304Sjkim ieee80211_free_node(ni); 1048280304Sjkim } else 1049280304Sjkim (void) ieee80211_input_all(ic, m, rssi, 1050280304Sjkim RAL_NOISE_FLOOR, 0); 1051280304Sjkim RAL_LOCK(sc); 1052280304Sjkim } 1053280304Sjkim return; 1054280304Sjkim 1055280304Sjkim default: /* Error */ 1056280304Sjkim if (xfer->error != USB_ERR_CANCELLED) { 1057238384Sjkim /* try to clear stall first */ 1058280304Sjkim xfer->flags.stall_pipe = 1; 1059238384Sjkim goto tr_setup; 1060280304Sjkim } 1061280304Sjkim return; 1062280304Sjkim } 1063280304Sjkim} 1064238384Sjkim 1065280304Sjkimstatic uint8_t 1066280304Sjkimural_plcp_signal(int rate) 1067280304Sjkim{ 1068238384Sjkim switch (rate) { 1069280304Sjkim /* OFDM rates (cf IEEE Std 802.11a-1999, pp. 14 Table 80) */ 1070280304Sjkim case 12: return 0xb; 1071280304Sjkim case 18: return 0xf; 1072280304Sjkim case 24: return 0xa; 1073280304Sjkim case 36: return 0xe; 1074280304Sjkim case 48: return 0x9; 1075280304Sjkim case 72: return 0xd; 1076280304Sjkim case 96: return 0x8; 1077280304Sjkim case 108: return 0xc; 1078280304Sjkim 1079280304Sjkim /* CCK rates (NB: not IEEE std, device-specific) */ 1080280304Sjkim case 2: return 0x0; 1081280304Sjkim case 4: return 0x1; 1082280304Sjkim case 11: return 0x2; 1083280304Sjkim case 22: return 0x3; 1084280304Sjkim } 1085280304Sjkim return 0xff; /* XXX unsupported/unknown rate */ 1086238384Sjkim} 1087280304Sjkim 1088238384Sjkimstatic void 1089280304Sjkimural_setup_tx_desc(struct ural_softc *sc, struct ural_tx_desc *desc, 1090280304Sjkim uint32_t flags, int len, int rate) 1091280304Sjkim{ 1092280304Sjkim struct ifnet *ifp = sc->sc_ifp; 1093238384Sjkim struct ieee80211com *ic = ifp->if_l2com; 1094280304Sjkim uint16_t plcp_length; 1095280304Sjkim int remainder; 1096238384Sjkim 1097280304Sjkim desc->flags = htole32(flags); 1098280304Sjkim desc->flags |= htole32(RAL_TX_NEWSEQ); 1099280304Sjkim desc->flags |= htole32(len << 16); 1100238384Sjkim 1101280304Sjkim desc->wme = htole16(RAL_AIFSN(2) | RAL_LOGCWMIN(3) | RAL_LOGCWMAX(5)); 1102280304Sjkim desc->wme |= htole16(RAL_IVOFFSET(sizeof (struct ieee80211_frame))); 1103280304Sjkim 1104280304Sjkim /* setup PLCP fields */ 1105280304Sjkim desc->plcp_signal = ural_plcp_signal(rate); 1106280304Sjkim desc->plcp_service = 4; 1107280304Sjkim 1108280304Sjkim len += IEEE80211_CRC_LEN; 1109280304Sjkim if (ieee80211_rate2phytype(ic->ic_rt, rate) == IEEE80211_T_OFDM) { 1110280304Sjkim desc->flags |= htole32(RAL_TX_OFDM); 1111280304Sjkim 1112280304Sjkim plcp_length = len & 0xfff; 1113280304Sjkim desc->plcp_length_hi = plcp_length >> 6; 1114280304Sjkim desc->plcp_length_lo = plcp_length & 0x3f; 1115280304Sjkim } else { 1116280304Sjkim plcp_length = (16 * len + rate - 1) / rate; 1117280304Sjkim if (rate == 22) { 1118280304Sjkim remainder = (16 * len) % 22; 1119280304Sjkim if (remainder != 0 && remainder < 7) 1120280304Sjkim desc->plcp_service |= RAL_PLCP_LENGEXT; 1121280304Sjkim } 1122280304Sjkim desc->plcp_length_hi = plcp_length >> 8; 1123280304Sjkim desc->plcp_length_lo = plcp_length & 0xff; 1124280304Sjkim 1125280304Sjkim if (rate != 2 && (ic->ic_flags & IEEE80211_F_SHPREAMBLE)) 1126280304Sjkim desc->plcp_signal |= 0x08; 1127238384Sjkim } 1128280304Sjkim 1129280304Sjkim desc->iv = 0; 1130238384Sjkim desc->eiv = 0; 1131280304Sjkim} 1132280304Sjkim 1133280304Sjkim#define RAL_TX_TIMEOUT 5000 1134280304Sjkim 1135280304Sjkimstatic int 1136280304Sjkimural_tx_bcn(struct ural_softc *sc, struct mbuf *m0, struct ieee80211_node *ni) 1137280304Sjkim{ 1138280304Sjkim struct ieee80211vap *vap = ni->ni_vap; 1139280304Sjkim struct ieee80211com *ic = ni->ni_ic; 1140280304Sjkim struct ifnet *ifp = sc->sc_ifp; 1141238384Sjkim const struct ieee80211_txparam *tp; 1142280304Sjkim struct ural_tx_data *data; 1143238384Sjkim 1144280304Sjkim if (sc->tx_nfree == 0) { 1145280304Sjkim ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1146280304Sjkim m_freem(m0); 1147280304Sjkim ieee80211_free_node(ni); 1148238384Sjkim return EIO; 1149280304Sjkim } 1150280304Sjkim data = STAILQ_FIRST(&sc->tx_free); 1151280304Sjkim STAILQ_REMOVE_HEAD(&sc->tx_free, next); 1152238384Sjkim sc->tx_nfree--; 1153280304Sjkim tp = &vap->iv_txparms[ieee80211_chan2mode(ic->ic_bsschan)]; 1154280304Sjkim 1155238384Sjkim data->m = m0; 1156280304Sjkim data->ni = ni; 1157280304Sjkim data->rate = tp->mgmtrate; 1158280304Sjkim 1159280304Sjkim ural_setup_tx_desc(sc, &data->desc, 1160280304Sjkim RAL_TX_IFS_NEWBACKOFF | RAL_TX_TIMESTAMP, m0->m_pkthdr.len, 1161280304Sjkim tp->mgmtrate); 1162280304Sjkim 1163280304Sjkim DPRINTFN(10, "sending beacon frame len=%u rate=%u\n", 1164280304Sjkim m0->m_pkthdr.len, tp->mgmtrate); 1165238384Sjkim 1166280304Sjkim STAILQ_INSERT_TAIL(&sc->tx_q, data, next); 1167280304Sjkim usb2_transfer_start(sc->sc_xfer[URAL_BULK_WR]); 1168238384Sjkim 1169280304Sjkim return (0); 1170280304Sjkim} 1171280304Sjkim 1172238384Sjkimstatic int 1173280304Sjkimural_tx_mgt(struct ural_softc *sc, struct mbuf *m0, struct ieee80211_node *ni) 1174280304Sjkim{ 1175280304Sjkim struct ieee80211vap *vap = ni->ni_vap; 1176280304Sjkim struct ieee80211com *ic = ni->ni_ic; 1177280304Sjkim const struct ieee80211_txparam *tp; 1178280304Sjkim struct ural_tx_data *data; 1179280304Sjkim struct ieee80211_frame *wh; 1180238384Sjkim struct ieee80211_key *k; 1181280304Sjkim uint32_t flags; 1182238384Sjkim uint16_t dur; 1183280304Sjkim 1184238384Sjkim RAL_LOCK_ASSERT(sc, MA_OWNED); 1185238384Sjkim 1186280304Sjkim data = STAILQ_FIRST(&sc->tx_free); 1187238384Sjkim STAILQ_REMOVE_HEAD(&sc->tx_free, next); 1188238384Sjkim sc->tx_nfree--; 1189238384Sjkim 1190238384Sjkim tp = &vap->iv_txparms[ieee80211_chan2mode(ic->ic_curchan)]; 1191238384Sjkim 1192238384Sjkim wh = mtod(m0, struct ieee80211_frame *); 1193238384Sjkim if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 1194238384Sjkim k = ieee80211_crypto_encap(ni, m0); 1195280304Sjkim if (k == NULL) { 1196280304Sjkim m_freem(m0); 1197280304Sjkim return ENOBUFS; 1198280304Sjkim } 1199280304Sjkim wh = mtod(m0, struct ieee80211_frame *); 1200238384Sjkim } 1201280304Sjkim 1202238384Sjkim data->m = m0; 1203280304Sjkim data->ni = ni; 1204280304Sjkim data->rate = tp->mgmtrate; 1205280304Sjkim 1206280304Sjkim flags = 0; 1207280304Sjkim if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1208280304Sjkim flags |= RAL_TX_ACK; 1209280304Sjkim 1210280304Sjkim dur = ieee80211_ack_duration(ic->ic_rt, tp->mgmtrate, 1211280304Sjkim ic->ic_flags & IEEE80211_F_SHPREAMBLE); 1212280304Sjkim *(uint16_t *)wh->i_dur = htole16(dur); 1213280304Sjkim 1214280304Sjkim /* tell hardware to add timestamp for probe responses */ 1215280304Sjkim if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) == 1216280304Sjkim IEEE80211_FC0_TYPE_MGT && 1217280304Sjkim (wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) == 1218280304Sjkim IEEE80211_FC0_SUBTYPE_PROBE_RESP) 1219280304Sjkim flags |= RAL_TX_TIMESTAMP; 1220280304Sjkim } 1221280304Sjkim 1222280304Sjkim ural_setup_tx_desc(sc, &data->desc, flags, m0->m_pkthdr.len, tp->mgmtrate); 1223280304Sjkim 1224280304Sjkim DPRINTFN(10, "sending mgt frame len=%u rate=%u\n", 1225280304Sjkim m0->m_pkthdr.len, tp->mgmtrate); 1226280304Sjkim 1227280304Sjkim STAILQ_INSERT_TAIL(&sc->tx_q, data, next); 1228280304Sjkim usb2_transfer_start(sc->sc_xfer[URAL_BULK_WR]); 1229280304Sjkim 1230280304Sjkim return 0; 1231280304Sjkim} 1232238384Sjkim 1233280304Sjkimstatic int 1234238384Sjkimural_sendprot(struct ural_softc *sc, 1235238384Sjkim const struct mbuf *m, struct ieee80211_node *ni, int prot, int rate) 1236238384Sjkim{ 1237280304Sjkim struct ieee80211com *ic = ni->ni_ic; 1238238384Sjkim const struct ieee80211_frame *wh; 1239280304Sjkim struct ural_tx_data *data; 1240238384Sjkim struct mbuf *mprot; 1241238384Sjkim int protrate, ackrate, pktlen, flags, isshort; 1242238384Sjkim uint16_t dur; 1243238384Sjkim 1244280304Sjkim KASSERT(prot == IEEE80211_PROT_RTSCTS || prot == IEEE80211_PROT_CTSONLY, 1245280304Sjkim ("protection %d", prot)); 1246280304Sjkim 1247280304Sjkim wh = mtod(m, const struct ieee80211_frame *); 1248280304Sjkim pktlen = m->m_pkthdr.len + IEEE80211_CRC_LEN; 1249280304Sjkim 1250238384Sjkim protrate = ieee80211_ctl_rate(ic->ic_rt, rate); 1251238384Sjkim ackrate = ieee80211_ack_rate(ic->ic_rt, rate); 1252280304Sjkim 1253280304Sjkim isshort = (ic->ic_flags & IEEE80211_F_SHPREAMBLE) != 0; 1254238384Sjkim dur = ieee80211_compute_duration(ic->ic_rt, pktlen, rate, isshort); 1255280304Sjkim + ieee80211_ack_duration(ic->ic_rt, rate, isshort); 1256238384Sjkim flags = RAL_TX_RETRY(7); 1257280304Sjkim if (prot == IEEE80211_PROT_RTSCTS) { 1258280304Sjkim /* NB: CTS is the same size as an ACK */ 1259280304Sjkim dur += ieee80211_ack_duration(ic->ic_rt, rate, isshort); 1260280304Sjkim flags |= RAL_TX_ACK; 1261280304Sjkim mprot = ieee80211_alloc_rts(ic, wh->i_addr1, wh->i_addr2, dur); 1262238384Sjkim } else { 1263280304Sjkim mprot = ieee80211_alloc_cts(ic, ni->ni_vap->iv_myaddr, dur); 1264280304Sjkim } 1265280304Sjkim if (mprot == NULL) { 1266280304Sjkim /* XXX stat + msg */ 1267 return ENOBUFS; 1268 } 1269 data = STAILQ_FIRST(&sc->tx_free); 1270 STAILQ_REMOVE_HEAD(&sc->tx_free, next); 1271 sc->tx_nfree--; 1272 1273 data->m = mprot; 1274 data->ni = ieee80211_ref_node(ni); 1275 data->rate = protrate; 1276 ural_setup_tx_desc(sc, &data->desc, flags, mprot->m_pkthdr.len, protrate); 1277 1278 STAILQ_INSERT_TAIL(&sc->tx_q, data, next); 1279 usb2_transfer_start(sc->sc_xfer[URAL_BULK_WR]); 1280 1281 return 0; 1282} 1283 1284static int 1285ural_tx_raw(struct ural_softc *sc, struct mbuf *m0, struct ieee80211_node *ni, 1286 const struct ieee80211_bpf_params *params) 1287{ 1288 struct ural_tx_data *data; 1289 uint32_t flags; 1290 int error; 1291 int rate; 1292 1293 RAL_LOCK_ASSERT(sc, MA_OWNED); 1294 KASSERT(params != NULL, ("no raw xmit params")); 1295 1296 rate = params->ibp_rate0 & IEEE80211_RATE_VAL; 1297 /* XXX validate */ 1298 if (rate == 0) { 1299 m_freem(m0); 1300 return EINVAL; 1301 } 1302 flags = 0; 1303 if ((params->ibp_flags & IEEE80211_BPF_NOACK) == 0) 1304 flags |= RAL_TX_ACK; 1305 if (params->ibp_flags & (IEEE80211_BPF_RTS|IEEE80211_BPF_CTS)) { 1306 error = ural_sendprot(sc, m0, ni, 1307 params->ibp_flags & IEEE80211_BPF_RTS ? 1308 IEEE80211_PROT_RTSCTS : IEEE80211_PROT_CTSONLY, 1309 rate); 1310 if (error || sc->tx_nfree == 0) { 1311 m_freem(m0); 1312 return ENOBUFS; 1313 } 1314 flags |= RAL_TX_IFS_SIFS; 1315 } 1316 1317 data = STAILQ_FIRST(&sc->tx_free); 1318 STAILQ_REMOVE_HEAD(&sc->tx_free, next); 1319 sc->tx_nfree--; 1320 1321 data->m = m0; 1322 data->ni = ni; 1323 data->rate = rate; 1324 1325 /* XXX need to setup descriptor ourself */ 1326 ural_setup_tx_desc(sc, &data->desc, flags, m0->m_pkthdr.len, rate); 1327 1328 DPRINTFN(10, "sending raw frame len=%u rate=%u\n", 1329 m0->m_pkthdr.len, rate); 1330 1331 STAILQ_INSERT_TAIL(&sc->tx_q, data, next); 1332 usb2_transfer_start(sc->sc_xfer[URAL_BULK_WR]); 1333 1334 return 0; 1335} 1336 1337static int 1338ural_tx_data(struct ural_softc *sc, struct mbuf *m0, struct ieee80211_node *ni) 1339{ 1340 struct ieee80211vap *vap = ni->ni_vap; 1341 struct ieee80211com *ic = ni->ni_ic; 1342 struct ural_tx_data *data; 1343 struct ieee80211_frame *wh; 1344 const struct ieee80211_txparam *tp; 1345 struct ieee80211_key *k; 1346 uint32_t flags = 0; 1347 uint16_t dur; 1348 int error, rate; 1349 1350 RAL_LOCK_ASSERT(sc, MA_OWNED); 1351 1352 wh = mtod(m0, struct ieee80211_frame *); 1353 1354 tp = &vap->iv_txparms[ieee80211_chan2mode(ni->ni_chan)]; 1355 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 1356 rate = tp->mcastrate; 1357 else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) 1358 rate = tp->ucastrate; 1359 else 1360 rate = ni->ni_txrate; 1361 1362 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 1363 k = ieee80211_crypto_encap(ni, m0); 1364 if (k == NULL) { 1365 m_freem(m0); 1366 return ENOBUFS; 1367 } 1368 /* packet header may have moved, reset our local pointer */ 1369 wh = mtod(m0, struct ieee80211_frame *); 1370 } 1371 1372 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1373 int prot = IEEE80211_PROT_NONE; 1374 if (m0->m_pkthdr.len + IEEE80211_CRC_LEN > vap->iv_rtsthreshold) 1375 prot = IEEE80211_PROT_RTSCTS; 1376 else if ((ic->ic_flags & IEEE80211_F_USEPROT) && 1377 ieee80211_rate2phytype(ic->ic_rt, rate) == IEEE80211_T_OFDM) 1378 prot = ic->ic_protmode; 1379 if (prot != IEEE80211_PROT_NONE) { 1380 error = ural_sendprot(sc, m0, ni, prot, rate); 1381 if (error || sc->tx_nfree == 0) { 1382 m_freem(m0); 1383 return ENOBUFS; 1384 } 1385 flags |= RAL_TX_IFS_SIFS; 1386 } 1387 } 1388 1389 data = STAILQ_FIRST(&sc->tx_free); 1390 STAILQ_REMOVE_HEAD(&sc->tx_free, next); 1391 sc->tx_nfree--; 1392 1393 data->m = m0; 1394 data->ni = ni; 1395 data->rate = rate; 1396 1397 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1398 flags |= RAL_TX_ACK; 1399 flags |= RAL_TX_RETRY(7); 1400 1401 dur = ieee80211_ack_duration(ic->ic_rt, rate, 1402 ic->ic_flags & IEEE80211_F_SHPREAMBLE); 1403 *(uint16_t *)wh->i_dur = htole16(dur); 1404 } 1405 1406 ural_setup_tx_desc(sc, &data->desc, flags, m0->m_pkthdr.len, rate); 1407 1408 DPRINTFN(10, "sending data frame len=%u rate=%u\n", 1409 m0->m_pkthdr.len, rate); 1410 1411 STAILQ_INSERT_TAIL(&sc->tx_q, data, next); 1412 usb2_transfer_start(sc->sc_xfer[URAL_BULK_WR]); 1413 1414 return 0; 1415} 1416 1417static void 1418ural_start(struct ifnet *ifp) 1419{ 1420 struct ural_softc *sc = ifp->if_softc; 1421 struct ieee80211_node *ni; 1422 struct mbuf *m; 1423 1424 RAL_LOCK(sc); 1425 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 1426 RAL_UNLOCK(sc); 1427 return; 1428 } 1429 for (;;) { 1430 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 1431 if (m == NULL) 1432 break; 1433 if (sc->tx_nfree < RAL_TX_MINFREE) { 1434 IFQ_DRV_PREPEND(&ifp->if_snd, m); 1435 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1436 break; 1437 } 1438 ni = (struct ieee80211_node *) m->m_pkthdr.rcvif; 1439 m = ieee80211_encap(ni, m); 1440 if (m == NULL) { 1441 ieee80211_free_node(ni); 1442 ifp->if_oerrors++; 1443 continue; 1444 } 1445 if (ural_tx_data(sc, m, ni) != 0) { 1446 ieee80211_free_node(ni); 1447 ifp->if_oerrors++; 1448 break; 1449 } 1450 } 1451 RAL_UNLOCK(sc); 1452} 1453 1454static int 1455ural_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1456{ 1457 struct ural_softc *sc = ifp->if_softc; 1458 struct ieee80211com *ic = ifp->if_l2com; 1459 struct ifreq *ifr = (struct ifreq *) data; 1460 int error = 0, startall = 0; 1461 1462 switch (cmd) { 1463 case SIOCSIFFLAGS: 1464 RAL_LOCK(sc); 1465 if (ifp->if_flags & IFF_UP) { 1466 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 1467 ural_queue_command(sc, ural_init_task, 1468 &sc->sc_synctask[0].hdr, 1469 &sc->sc_synctask[1].hdr); 1470 startall = 1; 1471 } else 1472 ural_queue_command(sc, ural_promisctask, 1473 &sc->sc_promisctask[0].hdr, 1474 &sc->sc_promisctask[1].hdr); 1475 } else { 1476 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1477 ural_queue_command(sc, ural_stop_task, 1478 &sc->sc_synctask[0].hdr, 1479 &sc->sc_synctask[1].hdr); 1480 } 1481 } 1482 RAL_UNLOCK(sc); 1483 if (startall) 1484 ieee80211_start_all(ic); 1485 break; 1486 case SIOCGIFMEDIA: 1487 case SIOCSIFMEDIA: 1488 error = ifmedia_ioctl(ifp, ifr, &ic->ic_media, cmd); 1489 break; 1490 default: 1491 error = ether_ioctl(ifp, cmd, data); 1492 break; 1493 } 1494 return error; 1495} 1496 1497static void 1498ural_set_testmode(struct ural_softc *sc) 1499{ 1500 struct usb2_device_request req; 1501 usb2_error_t error; 1502 1503 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1504 req.bRequest = RAL_VENDOR_REQUEST; 1505 USETW(req.wValue, 4); 1506 USETW(req.wIndex, 1); 1507 USETW(req.wLength, 0); 1508 1509 error = ural_do_request(sc, &req, NULL); 1510 if (error != 0) { 1511 device_printf(sc->sc_dev, "could not set test mode: %s\n", 1512 usb2_errstr(error)); 1513 } 1514} 1515 1516static void 1517ural_eeprom_read(struct ural_softc *sc, uint16_t addr, void *buf, int len) 1518{ 1519 struct usb2_device_request req; 1520 usb2_error_t error; 1521 1522 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1523 req.bRequest = RAL_READ_EEPROM; 1524 USETW(req.wValue, 0); 1525 USETW(req.wIndex, addr); 1526 USETW(req.wLength, len); 1527 1528 error = ural_do_request(sc, &req, buf); 1529 if (error != 0) { 1530 device_printf(sc->sc_dev, "could not read EEPROM: %s\n", 1531 usb2_errstr(error)); 1532 } 1533} 1534 1535static uint16_t 1536ural_read(struct ural_softc *sc, uint16_t reg) 1537{ 1538 struct usb2_device_request req; 1539 usb2_error_t error; 1540 uint16_t val; 1541 1542 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1543 req.bRequest = RAL_READ_MAC; 1544 USETW(req.wValue, 0); 1545 USETW(req.wIndex, reg); 1546 USETW(req.wLength, sizeof (uint16_t)); 1547 1548 error = ural_do_request(sc, &req, &val); 1549 if (error != 0) { 1550 device_printf(sc->sc_dev, "could not read MAC register: %s\n", 1551 usb2_errstr(error)); 1552 return 0; 1553 } 1554 1555 return le16toh(val); 1556} 1557 1558static void 1559ural_read_multi(struct ural_softc *sc, uint16_t reg, void *buf, int len) 1560{ 1561 struct usb2_device_request req; 1562 usb2_error_t error; 1563 1564 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1565 req.bRequest = RAL_READ_MULTI_MAC; 1566 USETW(req.wValue, 0); 1567 USETW(req.wIndex, reg); 1568 USETW(req.wLength, len); 1569 1570 error = ural_do_request(sc, &req, buf); 1571 if (error != 0) { 1572 device_printf(sc->sc_dev, "could not read MAC register: %s\n", 1573 usb2_errstr(error)); 1574 } 1575} 1576 1577static void 1578ural_write(struct ural_softc *sc, uint16_t reg, uint16_t val) 1579{ 1580 struct usb2_device_request req; 1581 usb2_error_t error; 1582 1583 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1584 req.bRequest = RAL_WRITE_MAC; 1585 USETW(req.wValue, val); 1586 USETW(req.wIndex, reg); 1587 USETW(req.wLength, 0); 1588 1589 error = ural_do_request(sc, &req, NULL); 1590 if (error != 0) { 1591 device_printf(sc->sc_dev, "could not write MAC register: %s\n", 1592 usb2_errstr(error)); 1593 } 1594} 1595 1596static void 1597ural_write_multi(struct ural_softc *sc, uint16_t reg, void *buf, int len) 1598{ 1599 struct usb2_device_request req; 1600 usb2_error_t error; 1601 1602 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1603 req.bRequest = RAL_WRITE_MULTI_MAC; 1604 USETW(req.wValue, 0); 1605 USETW(req.wIndex, reg); 1606 USETW(req.wLength, len); 1607 1608 error = ural_do_request(sc, &req, buf); 1609 if (error != 0) { 1610 device_printf(sc->sc_dev, "could not write MAC register: %s\n", 1611 usb2_errstr(error)); 1612 } 1613} 1614 1615static void 1616ural_bbp_write(struct ural_softc *sc, uint8_t reg, uint8_t val) 1617{ 1618 uint16_t tmp; 1619 int ntries; 1620 1621 for (ntries = 0; ntries < 100; ntries++) { 1622 if (!(ural_read(sc, RAL_PHY_CSR8) & RAL_BBP_BUSY)) 1623 break; 1624 if (ural_pause(sc, hz / 100)) 1625 break; 1626 } 1627 if (ntries == 100) { 1628 device_printf(sc->sc_dev, "could not write to BBP\n"); 1629 return; 1630 } 1631 1632 tmp = reg << 8 | val; 1633 ural_write(sc, RAL_PHY_CSR7, tmp); 1634} 1635 1636static uint8_t 1637ural_bbp_read(struct ural_softc *sc, uint8_t reg) 1638{ 1639 uint16_t val; 1640 int ntries; 1641 1642 val = RAL_BBP_WRITE | reg << 8; 1643 ural_write(sc, RAL_PHY_CSR7, val); 1644 1645 for (ntries = 0; ntries < 100; ntries++) { 1646 if (!(ural_read(sc, RAL_PHY_CSR8) & RAL_BBP_BUSY)) 1647 break; 1648 if (ural_pause(sc, hz / 100)) 1649 break; 1650 } 1651 if (ntries == 100) { 1652 device_printf(sc->sc_dev, "could not read BBP\n"); 1653 return 0; 1654 } 1655 1656 return ural_read(sc, RAL_PHY_CSR7) & 0xff; 1657} 1658 1659static void 1660ural_rf_write(struct ural_softc *sc, uint8_t reg, uint32_t val) 1661{ 1662 uint32_t tmp; 1663 int ntries; 1664 1665 for (ntries = 0; ntries < 100; ntries++) { 1666 if (!(ural_read(sc, RAL_PHY_CSR10) & RAL_RF_LOBUSY)) 1667 break; 1668 if (ural_pause(sc, hz / 100)) 1669 break; 1670 } 1671 if (ntries == 100) { 1672 device_printf(sc->sc_dev, "could not write to RF\n"); 1673 return; 1674 } 1675 1676 tmp = RAL_RF_BUSY | RAL_RF_20BIT | (val & 0xfffff) << 2 | (reg & 0x3); 1677 ural_write(sc, RAL_PHY_CSR9, tmp & 0xffff); 1678 ural_write(sc, RAL_PHY_CSR10, tmp >> 16); 1679 1680 /* remember last written value in sc */ 1681 sc->rf_regs[reg] = val; 1682 1683 DPRINTFN(15, "RF R[%u] <- 0x%05x\n", reg & 0x3, val & 0xfffff); 1684} 1685 1686/* ARGUSED */ 1687static struct ieee80211_node * 1688ural_node_alloc(struct ieee80211vap *vap __unused, 1689 const uint8_t mac[IEEE80211_ADDR_LEN] __unused) 1690{ 1691 struct ural_node *un; 1692 1693 un = malloc(sizeof(struct ural_node), M_80211_NODE, M_NOWAIT | M_ZERO); 1694 return un != NULL ? &un->ni : NULL; 1695} 1696 1697static void 1698ural_newassoc(struct ieee80211_node *ni, int isnew) 1699{ 1700 struct ieee80211vap *vap = ni->ni_vap; 1701 1702 ieee80211_amrr_node_init(&URAL_VAP(vap)->amrr, &URAL_NODE(ni)->amn, ni); 1703} 1704 1705static void 1706ural_scan_start(struct ieee80211com *ic) 1707{ 1708 struct ural_softc *sc = ic->ic_ifp->if_softc; 1709 1710 RAL_LOCK(sc); 1711 /* do it in a process context */ 1712 sc->sc_scan_action = URAL_SCAN_START; 1713 ural_queue_command(sc, ural_scantask, 1714 &sc->sc_scantask[0].hdr, &sc->sc_scantask[1].hdr); 1715 RAL_UNLOCK(sc); 1716 1717} 1718 1719static void 1720ural_scan_end(struct ieee80211com *ic) 1721{ 1722 struct ural_softc *sc = ic->ic_ifp->if_softc; 1723 1724 RAL_LOCK(sc); 1725 /* do it in a process context */ 1726 sc->sc_scan_action = URAL_SCAN_END; 1727 ural_queue_command(sc, ural_scantask, 1728 &sc->sc_scantask[0].hdr, &sc->sc_scantask[1].hdr); 1729 RAL_UNLOCK(sc); 1730 1731} 1732 1733static void 1734ural_set_channel(struct ieee80211com *ic) 1735{ 1736 struct ural_softc *sc = ic->ic_ifp->if_softc; 1737 1738 RAL_LOCK(sc); 1739 /* do it in a process context */ 1740 sc->sc_scan_action = URAL_SET_CHANNEL; 1741 ural_queue_command(sc, ural_scantask, 1742 &sc->sc_scantask[0].hdr, &sc->sc_scantask[1].hdr); 1743 RAL_UNLOCK(sc); 1744} 1745 1746static void 1747ural_set_chan(struct ural_softc *sc, struct ieee80211_channel *c) 1748{ 1749 struct ifnet *ifp = sc->sc_ifp; 1750 struct ieee80211com *ic = ifp->if_l2com; 1751 uint8_t power, tmp; 1752 int i, chan; 1753 1754 chan = ieee80211_chan2ieee(ic, c); 1755 if (chan == 0 || chan == IEEE80211_CHAN_ANY) 1756 return; 1757 1758 if (IEEE80211_IS_CHAN_2GHZ(c)) 1759 power = min(sc->txpow[chan - 1], 31); 1760 else 1761 power = 31; 1762 1763 /* adjust txpower using ifconfig settings */ 1764 power -= (100 - ic->ic_txpowlimit) / 8; 1765 1766 DPRINTFN(2, "setting channel to %u, txpower to %u\n", chan, power); 1767 1768 switch (sc->rf_rev) { 1769 case RAL_RF_2522: 1770 ural_rf_write(sc, RAL_RF1, 0x00814); 1771 ural_rf_write(sc, RAL_RF2, ural_rf2522_r2[chan - 1]); 1772 ural_rf_write(sc, RAL_RF3, power << 7 | 0x00040); 1773 break; 1774 1775 case RAL_RF_2523: 1776 ural_rf_write(sc, RAL_RF1, 0x08804); 1777 ural_rf_write(sc, RAL_RF2, ural_rf2523_r2[chan - 1]); 1778 ural_rf_write(sc, RAL_RF3, power << 7 | 0x38044); 1779 ural_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00280 : 0x00286); 1780 break; 1781 1782 case RAL_RF_2524: 1783 ural_rf_write(sc, RAL_RF1, 0x0c808); 1784 ural_rf_write(sc, RAL_RF2, ural_rf2524_r2[chan - 1]); 1785 ural_rf_write(sc, RAL_RF3, power << 7 | 0x00040); 1786 ural_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00280 : 0x00286); 1787 break; 1788 1789 case RAL_RF_2525: 1790 ural_rf_write(sc, RAL_RF1, 0x08808); 1791 ural_rf_write(sc, RAL_RF2, ural_rf2525_hi_r2[chan - 1]); 1792 ural_rf_write(sc, RAL_RF3, power << 7 | 0x18044); 1793 ural_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00280 : 0x00286); 1794 1795 ural_rf_write(sc, RAL_RF1, 0x08808); 1796 ural_rf_write(sc, RAL_RF2, ural_rf2525_r2[chan - 1]); 1797 ural_rf_write(sc, RAL_RF3, power << 7 | 0x18044); 1798 ural_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00280 : 0x00286); 1799 break; 1800 1801 case RAL_RF_2525E: 1802 ural_rf_write(sc, RAL_RF1, 0x08808); 1803 ural_rf_write(sc, RAL_RF2, ural_rf2525e_r2[chan - 1]); 1804 ural_rf_write(sc, RAL_RF3, power << 7 | 0x18044); 1805 ural_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00286 : 0x00282); 1806 break; 1807 1808 case RAL_RF_2526: 1809 ural_rf_write(sc, RAL_RF2, ural_rf2526_hi_r2[chan - 1]); 1810 ural_rf_write(sc, RAL_RF4, (chan & 1) ? 0x00386 : 0x00381); 1811 ural_rf_write(sc, RAL_RF1, 0x08804); 1812 1813 ural_rf_write(sc, RAL_RF2, ural_rf2526_r2[chan - 1]); 1814 ural_rf_write(sc, RAL_RF3, power << 7 | 0x18044); 1815 ural_rf_write(sc, RAL_RF4, (chan & 1) ? 0x00386 : 0x00381); 1816 break; 1817 1818 /* dual-band RF */ 1819 case RAL_RF_5222: 1820 for (i = 0; ural_rf5222[i].chan != chan; i++); 1821 1822 ural_rf_write(sc, RAL_RF1, ural_rf5222[i].r1); 1823 ural_rf_write(sc, RAL_RF2, ural_rf5222[i].r2); 1824 ural_rf_write(sc, RAL_RF3, power << 7 | 0x00040); 1825 ural_rf_write(sc, RAL_RF4, ural_rf5222[i].r4); 1826 break; 1827 } 1828 1829 if (ic->ic_opmode != IEEE80211_M_MONITOR && 1830 (ic->ic_flags & IEEE80211_F_SCAN) == 0) { 1831 /* set Japan filter bit for channel 14 */ 1832 tmp = ural_bbp_read(sc, 70); 1833 1834 tmp &= ~RAL_JAPAN_FILTER; 1835 if (chan == 14) 1836 tmp |= RAL_JAPAN_FILTER; 1837 1838 ural_bbp_write(sc, 70, tmp); 1839 1840 /* clear CRC errors */ 1841 ural_read(sc, RAL_STA_CSR0); 1842 1843 ural_pause(sc, hz / 100); 1844 ural_disable_rf_tune(sc); 1845 } 1846 1847 /* XXX doesn't belong here */ 1848 /* update basic rate set */ 1849 ural_set_basicrates(sc, c); 1850 1851 /* give the hardware some time to do the switchover */ 1852 ural_pause(sc, hz / 100); 1853} 1854 1855/* 1856 * Disable RF auto-tuning. 1857 */ 1858static void 1859ural_disable_rf_tune(struct ural_softc *sc) 1860{ 1861 uint32_t tmp; 1862 1863 if (sc->rf_rev != RAL_RF_2523) { 1864 tmp = sc->rf_regs[RAL_RF1] & ~RAL_RF1_AUTOTUNE; 1865 ural_rf_write(sc, RAL_RF1, tmp); 1866 } 1867 1868 tmp = sc->rf_regs[RAL_RF3] & ~RAL_RF3_AUTOTUNE; 1869 ural_rf_write(sc, RAL_RF3, tmp); 1870 1871 DPRINTFN(2, "disabling RF autotune\n"); 1872} 1873 1874/* 1875 * Refer to IEEE Std 802.11-1999 pp. 123 for more information on TSF 1876 * synchronization. 1877 */ 1878static void 1879ural_enable_tsf_sync(struct ural_softc *sc) 1880{ 1881 struct ifnet *ifp = sc->sc_ifp; 1882 struct ieee80211com *ic = ifp->if_l2com; 1883 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 1884 uint16_t logcwmin, preload, tmp; 1885 1886 /* first, disable TSF synchronization */ 1887 ural_write(sc, RAL_TXRX_CSR19, 0); 1888 1889 tmp = (16 * vap->iv_bss->ni_intval) << 4; 1890 ural_write(sc, RAL_TXRX_CSR18, tmp); 1891 1892 logcwmin = (ic->ic_opmode == IEEE80211_M_IBSS) ? 2 : 0; 1893 preload = (ic->ic_opmode == IEEE80211_M_IBSS) ? 320 : 6; 1894 tmp = logcwmin << 12 | preload; 1895 ural_write(sc, RAL_TXRX_CSR20, tmp); 1896 1897 /* finally, enable TSF synchronization */ 1898 tmp = RAL_ENABLE_TSF | RAL_ENABLE_TBCN; 1899 if (ic->ic_opmode == IEEE80211_M_STA) 1900 tmp |= RAL_ENABLE_TSF_SYNC(1); 1901 else 1902 tmp |= RAL_ENABLE_TSF_SYNC(2) | RAL_ENABLE_BEACON_GENERATOR; 1903 ural_write(sc, RAL_TXRX_CSR19, tmp); 1904 1905 DPRINTF("enabling TSF synchronization\n"); 1906} 1907 1908#define RAL_RXTX_TURNAROUND 5 /* us */ 1909static void 1910ural_update_slot(struct ifnet *ifp) 1911{ 1912 struct ural_softc *sc = ifp->if_softc; 1913 struct ieee80211com *ic = ifp->if_l2com; 1914 uint16_t slottime, sifs, eifs; 1915 1916 slottime = (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; 1917 1918 /* 1919 * These settings may sound a bit inconsistent but this is what the 1920 * reference driver does. 1921 */ 1922 if (ic->ic_curmode == IEEE80211_MODE_11B) { 1923 sifs = 16 - RAL_RXTX_TURNAROUND; 1924 eifs = 364; 1925 } else { 1926 sifs = 10 - RAL_RXTX_TURNAROUND; 1927 eifs = 64; 1928 } 1929 1930 ural_write(sc, RAL_MAC_CSR10, slottime); 1931 ural_write(sc, RAL_MAC_CSR11, sifs); 1932 ural_write(sc, RAL_MAC_CSR12, eifs); 1933} 1934 1935static void 1936ural_set_txpreamble(struct ural_softc *sc) 1937{ 1938 struct ifnet *ifp = sc->sc_ifp; 1939 struct ieee80211com *ic = ifp->if_l2com; 1940 uint16_t tmp; 1941 1942 tmp = ural_read(sc, RAL_TXRX_CSR10); 1943 1944 tmp &= ~RAL_SHORT_PREAMBLE; 1945 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 1946 tmp |= RAL_SHORT_PREAMBLE; 1947 1948 ural_write(sc, RAL_TXRX_CSR10, tmp); 1949} 1950 1951static void 1952ural_set_basicrates(struct ural_softc *sc, const struct ieee80211_channel *c) 1953{ 1954 /* XXX wrong, take from rate set */ 1955 /* update basic rate set */ 1956 if (IEEE80211_IS_CHAN_5GHZ(c)) { 1957 /* 11a basic rates: 6, 12, 24Mbps */ 1958 ural_write(sc, RAL_TXRX_CSR11, 0x150); 1959 } else if (IEEE80211_IS_CHAN_ANYG(c)) { 1960 /* 11g basic rates: 1, 2, 5.5, 11, 6, 12, 24Mbps */ 1961 ural_write(sc, RAL_TXRX_CSR11, 0x15f); 1962 } else { 1963 /* 11b basic rates: 1, 2Mbps */ 1964 ural_write(sc, RAL_TXRX_CSR11, 0x3); 1965 } 1966} 1967 1968static void 1969ural_set_bssid(struct ural_softc *sc, const uint8_t *bssid) 1970{ 1971 uint16_t tmp; 1972 1973 tmp = bssid[0] | bssid[1] << 8; 1974 ural_write(sc, RAL_MAC_CSR5, tmp); 1975 1976 tmp = bssid[2] | bssid[3] << 8; 1977 ural_write(sc, RAL_MAC_CSR6, tmp); 1978 1979 tmp = bssid[4] | bssid[5] << 8; 1980 ural_write(sc, RAL_MAC_CSR7, tmp); 1981 1982 DPRINTF("setting BSSID to %6D\n", bssid, ":"); 1983} 1984 1985static void 1986ural_set_macaddr(struct ural_softc *sc, uint8_t *addr) 1987{ 1988 uint16_t tmp; 1989 1990 tmp = addr[0] | addr[1] << 8; 1991 ural_write(sc, RAL_MAC_CSR2, tmp); 1992 1993 tmp = addr[2] | addr[3] << 8; 1994 ural_write(sc, RAL_MAC_CSR3, tmp); 1995 1996 tmp = addr[4] | addr[5] << 8; 1997 ural_write(sc, RAL_MAC_CSR4, tmp); 1998 1999 DPRINTF("setting MAC address to %6D\n", addr, ":"); 2000} 2001 2002static void 2003ural_promisctask(struct usb2_proc_msg *pm) 2004{ 2005 struct ural_task *task = (struct ural_task *)pm; 2006 struct ural_softc *sc = task->sc; 2007 struct ifnet *ifp = sc->sc_ifp; 2008 uint32_t tmp; 2009 2010 tmp = ural_read(sc, RAL_TXRX_CSR2); 2011 2012 tmp &= ~RAL_DROP_NOT_TO_ME; 2013 if (!(ifp->if_flags & IFF_PROMISC)) 2014 tmp |= RAL_DROP_NOT_TO_ME; 2015 2016 ural_write(sc, RAL_TXRX_CSR2, tmp); 2017 2018 DPRINTF("%s promiscuous mode\n", (ifp->if_flags & IFF_PROMISC) ? 2019 "entering" : "leaving"); 2020} 2021 2022static void 2023ural_update_promisc(struct ifnet *ifp) 2024{ 2025 struct ural_softc *sc = ifp->if_softc; 2026 2027 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 2028 return; 2029 2030 RAL_LOCK(sc); 2031 ural_queue_command(sc, ural_promisctask, 2032 &sc->sc_promisctask[0].hdr, 2033 &sc->sc_promisctask[1].hdr); 2034 RAL_UNLOCK(sc); 2035} 2036 2037static const char * 2038ural_get_rf(int rev) 2039{ 2040 switch (rev) { 2041 case RAL_RF_2522: return "RT2522"; 2042 case RAL_RF_2523: return "RT2523"; 2043 case RAL_RF_2524: return "RT2524"; 2044 case RAL_RF_2525: return "RT2525"; 2045 case RAL_RF_2525E: return "RT2525e"; 2046 case RAL_RF_2526: return "RT2526"; 2047 case RAL_RF_5222: return "RT5222"; 2048 default: return "unknown"; 2049 } 2050} 2051 2052static void 2053ural_read_eeprom(struct ural_softc *sc) 2054{ 2055 uint16_t val; 2056 2057 ural_eeprom_read(sc, RAL_EEPROM_CONFIG0, &val, 2); 2058 val = le16toh(val); 2059 sc->rf_rev = (val >> 11) & 0x7; 2060 sc->hw_radio = (val >> 10) & 0x1; 2061 sc->led_mode = (val >> 6) & 0x7; 2062 sc->rx_ant = (val >> 4) & 0x3; 2063 sc->tx_ant = (val >> 2) & 0x3; 2064 sc->nb_ant = val & 0x3; 2065 2066 /* read MAC address */ 2067 ural_eeprom_read(sc, RAL_EEPROM_ADDRESS, sc->sc_bssid, 6); 2068 2069 /* read default values for BBP registers */ 2070 ural_eeprom_read(sc, RAL_EEPROM_BBP_BASE, sc->bbp_prom, 2 * 16); 2071 2072 /* read Tx power for all b/g channels */ 2073 ural_eeprom_read(sc, RAL_EEPROM_TXPOWER, sc->txpow, 14); 2074} 2075 2076static int 2077ural_bbp_init(struct ural_softc *sc) 2078{ 2079#define N(a) (sizeof (a) / sizeof ((a)[0])) 2080 int i, ntries; 2081 2082 /* wait for BBP to be ready */ 2083 for (ntries = 0; ntries < 100; ntries++) { 2084 if (ural_bbp_read(sc, RAL_BBP_VERSION) != 0) 2085 break; 2086 if (ural_pause(sc, hz / 100)) 2087 break; 2088 } 2089 if (ntries == 100) { 2090 device_printf(sc->sc_dev, "timeout waiting for BBP\n"); 2091 return EIO; 2092 } 2093 2094 /* initialize BBP registers to default values */ 2095 for (i = 0; i < N(ural_def_bbp); i++) 2096 ural_bbp_write(sc, ural_def_bbp[i].reg, ural_def_bbp[i].val); 2097 2098#if 0 2099 /* initialize BBP registers to values stored in EEPROM */ 2100 for (i = 0; i < 16; i++) { 2101 if (sc->bbp_prom[i].reg == 0xff) 2102 continue; 2103 ural_bbp_write(sc, sc->bbp_prom[i].reg, sc->bbp_prom[i].val); 2104 } 2105#endif 2106 2107 return 0; 2108#undef N 2109} 2110 2111static void 2112ural_set_txantenna(struct ural_softc *sc, int antenna) 2113{ 2114 uint16_t tmp; 2115 uint8_t tx; 2116 2117 tx = ural_bbp_read(sc, RAL_BBP_TX) & ~RAL_BBP_ANTMASK; 2118 if (antenna == 1) 2119 tx |= RAL_BBP_ANTA; 2120 else if (antenna == 2) 2121 tx |= RAL_BBP_ANTB; 2122 else 2123 tx |= RAL_BBP_DIVERSITY; 2124 2125 /* need to force I/Q flip for RF 2525e, 2526 and 5222 */ 2126 if (sc->rf_rev == RAL_RF_2525E || sc->rf_rev == RAL_RF_2526 || 2127 sc->rf_rev == RAL_RF_5222) 2128 tx |= RAL_BBP_FLIPIQ; 2129 2130 ural_bbp_write(sc, RAL_BBP_TX, tx); 2131 2132 /* update values in PHY_CSR5 and PHY_CSR6 */ 2133 tmp = ural_read(sc, RAL_PHY_CSR5) & ~0x7; 2134 ural_write(sc, RAL_PHY_CSR5, tmp | (tx & 0x7)); 2135 2136 tmp = ural_read(sc, RAL_PHY_CSR6) & ~0x7; 2137 ural_write(sc, RAL_PHY_CSR6, tmp | (tx & 0x7)); 2138} 2139 2140static void 2141ural_set_rxantenna(struct ural_softc *sc, int antenna) 2142{ 2143 uint8_t rx; 2144 2145 rx = ural_bbp_read(sc, RAL_BBP_RX) & ~RAL_BBP_ANTMASK; 2146 if (antenna == 1) 2147 rx |= RAL_BBP_ANTA; 2148 else if (antenna == 2) 2149 rx |= RAL_BBP_ANTB; 2150 else 2151 rx |= RAL_BBP_DIVERSITY; 2152 2153 /* need to force no I/Q flip for RF 2525e and 2526 */ 2154 if (sc->rf_rev == RAL_RF_2525E || sc->rf_rev == RAL_RF_2526) 2155 rx &= ~RAL_BBP_FLIPIQ; 2156 2157 ural_bbp_write(sc, RAL_BBP_RX, rx); 2158} 2159 2160static void 2161ural_init_task(struct usb2_proc_msg *pm) 2162{ 2163#define N(a) (sizeof (a) / sizeof ((a)[0])) 2164 struct ural_task *task = (struct ural_task *)pm; 2165 struct ural_softc *sc = task->sc; 2166 struct ifnet *ifp = sc->sc_ifp; 2167 struct ieee80211com *ic = ifp->if_l2com; 2168 uint16_t tmp; 2169 int i, ntries; 2170 2171 RAL_LOCK_ASSERT(sc, MA_OWNED); 2172 2173 ural_set_testmode(sc); 2174 ural_write(sc, 0x308, 0x00f0); /* XXX magic */ 2175 2176 ural_stop_task(pm); 2177 2178 /* initialize MAC registers to default values */ 2179 for (i = 0; i < N(ural_def_mac); i++) 2180 ural_write(sc, ural_def_mac[i].reg, ural_def_mac[i].val); 2181 2182 /* wait for BBP and RF to wake up (this can take a long time!) */ 2183 for (ntries = 0; ntries < 100; ntries++) { 2184 tmp = ural_read(sc, RAL_MAC_CSR17); 2185 if ((tmp & (RAL_BBP_AWAKE | RAL_RF_AWAKE)) == 2186 (RAL_BBP_AWAKE | RAL_RF_AWAKE)) 2187 break; 2188 if (ural_pause(sc, hz / 100)) 2189 break; 2190 } 2191 if (ntries == 100) { 2192 device_printf(sc->sc_dev, 2193 "timeout waiting for BBP/RF to wakeup\n"); 2194 goto fail; 2195 } 2196 2197 /* we're ready! */ 2198 ural_write(sc, RAL_MAC_CSR1, RAL_HOST_READY); 2199 2200 /* set basic rate set (will be updated later) */ 2201 ural_write(sc, RAL_TXRX_CSR11, 0x15f); 2202 2203 if (ural_bbp_init(sc) != 0) 2204 goto fail; 2205 2206 ural_set_chan(sc, ic->ic_curchan); 2207 2208 /* clear statistic registers (STA_CSR0 to STA_CSR10) */ 2209 ural_read_multi(sc, RAL_STA_CSR0, sc->sta, sizeof sc->sta); 2210 2211 ural_set_txantenna(sc, sc->tx_ant); 2212 ural_set_rxantenna(sc, sc->rx_ant); 2213 2214 ural_set_macaddr(sc, IF_LLADDR(ifp)); 2215 2216 /* 2217 * Allocate Tx and Rx xfer queues. 2218 */ 2219 ural_setup_tx_list(sc); 2220 2221 /* kick Rx */ 2222 tmp = RAL_DROP_PHY | RAL_DROP_CRC; 2223 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 2224 tmp |= RAL_DROP_CTL | RAL_DROP_BAD_VERSION; 2225 if (ic->ic_opmode != IEEE80211_M_HOSTAP) 2226 tmp |= RAL_DROP_TODS; 2227 if (!(ifp->if_flags & IFF_PROMISC)) 2228 tmp |= RAL_DROP_NOT_TO_ME; 2229 } 2230 ural_write(sc, RAL_TXRX_CSR2, tmp); 2231 2232 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2233 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2234 usb2_transfer_set_stall(sc->sc_xfer[URAL_BULK_WR]); 2235 usb2_transfer_start(sc->sc_xfer[URAL_BULK_RD]); 2236 return; 2237 2238fail: ural_stop_task(pm); 2239#undef N 2240} 2241 2242static void 2243ural_init(void *priv) 2244{ 2245 struct ural_softc *sc = priv; 2246 struct ifnet *ifp = sc->sc_ifp; 2247 struct ieee80211com *ic = ifp->if_l2com; 2248 2249 RAL_LOCK(sc); 2250 ural_queue_command(sc, ural_init_task, 2251 &sc->sc_synctask[0].hdr, 2252 &sc->sc_synctask[1].hdr); 2253 RAL_UNLOCK(sc); 2254 2255 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2256 ieee80211_start_all(ic); /* start all vap's */ 2257} 2258 2259static void 2260ural_stop_task(struct usb2_proc_msg *pm) 2261{ 2262 struct ural_task *task = (struct ural_task *)pm; 2263 struct ural_softc *sc = task->sc; 2264 struct ifnet *ifp = sc->sc_ifp; 2265 2266 RAL_LOCK_ASSERT(sc, MA_OWNED); 2267 2268 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2269 2270 /* 2271 * Drain all the transfers, if not already drained: 2272 */ 2273 RAL_UNLOCK(sc); 2274 usb2_transfer_drain(sc->sc_xfer[URAL_BULK_WR]); 2275 usb2_transfer_drain(sc->sc_xfer[URAL_BULK_RD]); 2276 RAL_LOCK(sc); 2277 2278 ural_unsetup_tx_list(sc); 2279 2280 /* disable Rx */ 2281 ural_write(sc, RAL_TXRX_CSR2, RAL_DISABLE_RX); 2282 /* reset ASIC and BBP (but won't reset MAC registers!) */ 2283 ural_write(sc, RAL_MAC_CSR1, RAL_RESET_ASIC | RAL_RESET_BBP); 2284 /* wait a little */ 2285 ural_pause(sc, hz / 10); 2286 ural_write(sc, RAL_MAC_CSR1, 0); 2287 /* wait a little */ 2288 ural_pause(sc, hz / 10); 2289} 2290 2291static int 2292ural_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 2293 const struct ieee80211_bpf_params *params) 2294{ 2295 struct ieee80211com *ic = ni->ni_ic; 2296 struct ifnet *ifp = ic->ic_ifp; 2297 struct ural_softc *sc = ifp->if_softc; 2298 2299 RAL_LOCK(sc); 2300 /* prevent management frames from being sent if we're not ready */ 2301 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 2302 RAL_UNLOCK(sc); 2303 m_freem(m); 2304 ieee80211_free_node(ni); 2305 return ENETDOWN; 2306 } 2307 if (sc->tx_nfree < RAL_TX_MINFREE) { 2308 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2309 RAL_UNLOCK(sc); 2310 m_freem(m); 2311 ieee80211_free_node(ni); 2312 return EIO; 2313 } 2314 2315 ifp->if_opackets++; 2316 2317 if (params == NULL) { 2318 /* 2319 * Legacy path; interpret frame contents to decide 2320 * precisely how to send the frame. 2321 */ 2322 if (ural_tx_mgt(sc, m, ni) != 0) 2323 goto bad; 2324 } else { 2325 /* 2326 * Caller supplied explicit parameters to use in 2327 * sending the frame. 2328 */ 2329 if (ural_tx_raw(sc, m, ni, params) != 0) 2330 goto bad; 2331 } 2332 RAL_UNLOCK(sc); 2333 return 0; 2334bad: 2335 ifp->if_oerrors++; 2336 RAL_UNLOCK(sc); 2337 ieee80211_free_node(ni); 2338 return EIO; /* XXX */ 2339} 2340 2341static void 2342ural_amrr_start(struct ural_softc *sc, struct ieee80211_node *ni) 2343{ 2344 struct ieee80211vap *vap = ni->ni_vap; 2345 struct ural_vap *uvp = URAL_VAP(vap); 2346 2347 /* clear statistic registers (STA_CSR0 to STA_CSR10) */ 2348 ural_read_multi(sc, RAL_STA_CSR0, sc->sta, sizeof sc->sta); 2349 2350 ieee80211_amrr_node_init(&uvp->amrr, &URAL_NODE(ni)->amn, ni); 2351 2352 usb2_callout_reset(&uvp->amrr_ch, hz, ural_amrr_timeout, uvp); 2353} 2354 2355static void 2356ural_amrr_timeout(void *arg) 2357{ 2358 struct ural_vap *uvp = arg; 2359 struct ural_softc *sc = uvp->sc; 2360 2361 ural_queue_command(sc, ural_amrr_task, 2362 &uvp->amrr_task[0].hdr, &uvp->amrr_task[1].hdr); 2363} 2364 2365static void 2366ural_amrr_task(struct usb2_proc_msg *pm) 2367{ 2368 struct ural_task *task = (struct ural_task *)pm; 2369 struct ural_softc *sc = task->sc; 2370 struct ifnet *ifp = sc->sc_ifp; 2371 struct ieee80211com *ic = ifp->if_l2com; 2372 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 2373 struct ural_vap *uvp = URAL_VAP(vap); 2374 struct ieee80211_node *ni = vap->iv_bss; 2375 int ok, fail; 2376 2377 /* read and clear statistic registers (STA_CSR0 to STA_CSR10) */ 2378 ural_read_multi(sc, RAL_STA_CSR0, sc->sta, sizeof(sc->sta)); 2379 2380 ok = sc->sta[7] + /* TX ok w/o retry */ 2381 sc->sta[8]; /* TX ok w/ retry */ 2382 fail = sc->sta[9]; /* TX retry-fail count */ 2383 2384 ieee80211_amrr_tx_update(&URAL_NODE(ni)->amn, 2385 ok+fail, ok, sc->sta[8] + fail); 2386 (void) ieee80211_amrr_choose(ni, &URAL_NODE(ni)->amn); 2387 2388 ifp->if_oerrors += fail; /* count TX retry-fail as Tx errors */ 2389 2390 usb2_callout_reset(&uvp->amrr_ch, hz, ural_amrr_timeout, uvp); 2391} 2392 2393static int 2394ural_pause(struct ural_softc *sc, int timeout) 2395{ 2396 if (usb2_proc_is_gone(&sc->sc_tq)) 2397 return (1); 2398 2399 usb2_pause_mtx(&sc->sc_mtx, timeout); 2400 return (0); 2401} 2402 2403static void 2404ural_command_wrapper(struct usb2_proc_msg *pm) 2405{ 2406 struct ural_task *task = (struct ural_task *)pm; 2407 struct ural_softc *sc = task->sc; 2408 struct ifnet *ifp; 2409 2410 /* wait for pending transfer, if any */ 2411 while (usb2_transfer_pending(sc->sc_xfer[URAL_BULK_WR])) 2412 cv_wait(&sc->sc_cmd_cv, &sc->sc_mtx); 2413 2414 /* make sure any hardware FIFOs are emptied */ 2415 ural_pause(sc, hz / 1000); 2416 2417 /* execute task */ 2418 task->func(pm); 2419 2420 /* check if this is the last task executed */ 2421 if (sc->sc_last_task == task) { 2422 sc->sc_last_task = NULL; 2423 ifp = sc->sc_ifp; 2424 /* re-start TX, if any */ 2425 if ((ifp != NULL) && (ifp->if_drv_flags & IFF_DRV_RUNNING)) 2426 usb2_transfer_start(sc->sc_xfer[URAL_BULK_WR]); 2427 } 2428} 2429 2430static void 2431ural_queue_command(struct ural_softc *sc, usb2_proc_callback_t *fn, 2432 struct usb2_proc_msg *t0, struct usb2_proc_msg *t1) 2433{ 2434 struct ural_task *task; 2435 2436 RAL_LOCK_ASSERT(sc, MA_OWNED); 2437 2438 /* 2439 * NOTE: The task cannot get executed before we drop the 2440 * "sc_mtx" mutex. It is safe to update fields in the message 2441 * structure after that the message got queued. 2442 */ 2443 task = (struct ural_task *) 2444 usb2_proc_msignal(&sc->sc_tq, t0, t1); 2445 2446 /* Setup callback and softc pointers */ 2447 task->hdr.pm_callback = ural_command_wrapper; 2448 task->func = fn; 2449 task->sc = sc; 2450 2451 /* Make sure that any TX operation will stop */ 2452 sc->sc_last_task = task; 2453 2454 /* 2455 * Init, stop and flush must be synchronous! 2456 */ 2457 if ((fn == ural_init_task) || (fn == ural_stop_task) || 2458 (fn == ural_stop_task)) 2459 usb2_proc_mwait(&sc->sc_tq, t0, t1); 2460} 2461