uss820dci.c revision 192448
1132332Smarcel/* $FreeBSD: head/sys/dev/usb/controller/uss820dci.c 192448 2009-05-20 17:03:12Z thompsa $ */
2132332Smarcel/*-
3132332Smarcel * Copyright (c) 2008 Hans Petter Selasky <hselasky@FreeBSD.org>
4132332Smarcel * All rights reserved.
5132332Smarcel *
6132332Smarcel * Redistribution and use in source and binary forms, with or without
7132332Smarcel * modification, are permitted provided that the following conditions
8132332Smarcel * are met:
9132332Smarcel * 1. Redistributions of source code must retain the above copyright
10132332Smarcel *    notice, this list of conditions and the following disclaimer.
11132332Smarcel * 2. Redistributions in binary form must reproduce the above copyright
12132332Smarcel *    notice, this list of conditions and the following disclaimer in the
13132332Smarcel *    documentation and/or other materials provided with the distribution.
14132332Smarcel *
15132332Smarcel * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16132332Smarcel * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17132332Smarcel * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18132332Smarcel * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19132332Smarcel * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20132332Smarcel * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21132332Smarcel * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22132332Smarcel * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23132332Smarcel * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24132332Smarcel * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25132332Smarcel * SUCH DAMAGE.
26132332Smarcel */
27132332Smarcel
28132332Smarcel/*
29132332Smarcel * This file contains the driver for the USS820 series USB Device
30132332Smarcel * Controller
31132332Smarcel *
32132332Smarcel * NOTE: The datasheet does not document everything.
33132332Smarcel */
34132332Smarcel
35132332Smarcel#include <dev/usb/usb.h>
36177490Sdavidxu#include <dev/usb/usb_mfunc.h>
37132332Smarcel#include <dev/usb/usb_revision.h>
38132332Smarcel#include <dev/usb/usb_error.h>
39132332Smarcel
40132332Smarcel#define	USB_DEBUG_VAR uss820dcidebug
41132332Smarcel
42177526Sjeff#include <dev/usb/usb_core.h>
43132332Smarcel#include <dev/usb/usb_debug.h>
44132332Smarcel#include <dev/usb/usb_busdma.h>
45132332Smarcel#include <dev/usb/usb_process.h>
46132332Smarcel#include <dev/usb/usb_transfer.h>
47132332Smarcel#include <dev/usb/usb_device.h>
48132332Smarcel#include <dev/usb/usb_hub.h>
49132332Smarcel#include <dev/usb/usb_util.h>
50132332Smarcel
51132332Smarcel#include <dev/usb/usb_controller.h>
52132332Smarcel#include <dev/usb/usb_bus.h>
53132332Smarcel#include <dev/usb/controller/uss820dci.h>
54132332Smarcel
55132332Smarcel#define	USS820_DCI_BUS2SC(bus) \
56132332Smarcel   ((struct uss820dci_softc *)(((uint8_t *)(bus)) - \
57132332Smarcel    ((uint8_t *)&(((struct uss820dci_softc *)0)->sc_bus))))
58132332Smarcel
59132332Smarcel#define	USS820_DCI_PC2SC(pc) \
60132332Smarcel   USS820_DCI_BUS2SC(USB_DMATAG_TO_XROOT((pc)->tag_parent)->bus)
61132332Smarcel
62132332Smarcel#if USB_DEBUG
63132332Smarcelstatic int uss820dcidebug = 0;
64132332Smarcel
65132332SmarcelSYSCTL_NODE(_hw_usb2, OID_AUTO, uss820dci, CTLFLAG_RW, 0, "USB uss820dci");
66132332SmarcelSYSCTL_INT(_hw_usb2_uss820dci, OID_AUTO, debug, CTLFLAG_RW,
67132332Smarcel    &uss820dcidebug, 0, "uss820dci debug level");
68132332Smarcel#endif
69132332Smarcel
70132332Smarcel#define	USS820_DCI_INTR_ENDPT 1
71132332Smarcel
72132332Smarcel/* prototypes */
73181059Smarcel
74132332Smarcelstruct usb2_bus_methods uss820dci_bus_methods;
75132332Smarcelstruct usb2_pipe_methods uss820dci_device_bulk_methods;
76132332Smarcelstruct usb2_pipe_methods uss820dci_device_ctrl_methods;
77132332Smarcelstruct usb2_pipe_methods uss820dci_device_intr_methods;
78132332Smarcelstruct usb2_pipe_methods uss820dci_device_isoc_fs_methods;
79132332Smarcel
80132332Smarcelstatic uss820dci_cmd_t uss820dci_setup_rx;
81132332Smarcelstatic uss820dci_cmd_t uss820dci_data_rx;
82132332Smarcelstatic uss820dci_cmd_t uss820dci_data_tx;
83132332Smarcelstatic uss820dci_cmd_t uss820dci_data_tx_sync;
84132332Smarcelstatic void	uss820dci_device_done(struct usb2_xfer *, usb2_error_t);
85132332Smarcelstatic void	uss820dci_do_poll(struct usb2_bus *);
86132332Smarcelstatic void	uss820dci_standard_done(struct usb2_xfer *);
87132332Smarcelstatic void	uss820dci_intr_set(struct usb2_xfer *, uint8_t);
88132332Smarcelstatic void	uss820dci_update_shared_1(struct uss820dci_softc *, uint8_t,
89132332Smarcel		    uint8_t, uint8_t);
90132332Smarcelstatic void	uss820dci_root_intr(struct uss820dci_softc *);
91132332Smarcel
92132332Smarcel/*
93132332Smarcel * Here is a list of what the USS820D chip can support. The main
94132332Smarcel * limitation is that the sum of the buffer sizes must be less than
95132332Smarcel * 1120 bytes.
96132332Smarcel */
97132332Smarcelstatic const struct usb2_hw_ep_profile
98132332Smarcel	uss820dci_ep_profile[] = {
99132332Smarcel
100132332Smarcel	[0] = {
101132332Smarcel		.max_in_frame_size = 32,
102132332Smarcel		.max_out_frame_size = 32,
103132332Smarcel		.is_simplex = 0,
104132332Smarcel		.support_control = 1,
105132332Smarcel	},
106132332Smarcel	[1] = {
107132332Smarcel		.max_in_frame_size = 64,
108132332Smarcel		.max_out_frame_size = 64,
109132332Smarcel		.is_simplex = 0,
110132332Smarcel		.support_multi_buffer = 1,
111132332Smarcel		.support_bulk = 1,
112132332Smarcel		.support_interrupt = 1,
113132332Smarcel		.support_in = 1,
114132332Smarcel		.support_out = 1,
115132332Smarcel	},
116132332Smarcel	[2] = {
117132332Smarcel		.max_in_frame_size = 8,
118132332Smarcel		.max_out_frame_size = 8,
119132332Smarcel		.is_simplex = 0,
120132332Smarcel		.support_multi_buffer = 1,
121132332Smarcel		.support_bulk = 1,
122132332Smarcel		.support_interrupt = 1,
123132332Smarcel		.support_in = 1,
124132332Smarcel		.support_out = 1,
125132332Smarcel	},
126132332Smarcel	[3] = {
127132332Smarcel		.max_in_frame_size = 256,
128132332Smarcel		.max_out_frame_size = 256,
129132332Smarcel		.is_simplex = 0,
130132332Smarcel		.support_multi_buffer = 1,
131132332Smarcel		.support_isochronous = 1,
132133802Sdavidxu		.support_in = 1,
133133802Sdavidxu		.support_out = 1,
134133802Sdavidxu	},
135133802Sdavidxu};
136133802Sdavidxu
137133802Sdavidxustatic void
138133802Sdavidxuuss820dci_update_shared_1(struct uss820dci_softc *sc, uint8_t reg,
139133802Sdavidxu    uint8_t keep_mask, uint8_t set_mask)
140133802Sdavidxu{
141133802Sdavidxu	uint8_t temp;
142133802Sdavidxu
143133802Sdavidxu	USS820_WRITE_1(sc, USS820_PEND, 1);
144133802Sdavidxu	temp = USS820_READ_1(sc, reg);
145133802Sdavidxu	temp &= (keep_mask);
146132332Smarcel	temp |= (set_mask);
147133802Sdavidxu	USS820_WRITE_1(sc, reg, temp);
148132332Smarcel	USS820_WRITE_1(sc, USS820_PEND, 0);
149132332Smarcel}
150132332Smarcel
151132332Smarcelstatic void
152132332Smarceluss820dci_get_hw_ep_profile(struct usb2_device *udev,
153132332Smarcel    const struct usb2_hw_ep_profile **ppf, uint8_t ep_addr)
154132332Smarcel{
155132332Smarcel	if (ep_addr == 0) {
156132332Smarcel		*ppf = uss820dci_ep_profile + 0;
157132332Smarcel	} else if (ep_addr < 5) {
158132332Smarcel		*ppf = uss820dci_ep_profile + 1;
159132332Smarcel	} else if (ep_addr < 7) {
160132332Smarcel		*ppf = uss820dci_ep_profile + 2;
161132332Smarcel	} else if (ep_addr == 7) {
162132332Smarcel		*ppf = uss820dci_ep_profile + 3;
163132332Smarcel	} else {
164132332Smarcel		*ppf = NULL;
165132332Smarcel	}
166132332Smarcel}
167133802Sdavidxu
168133802Sdavidxustatic void
169133802Sdavidxuuss820dci_pull_up(struct uss820dci_softc *sc)
170133802Sdavidxu{
171133802Sdavidxu	uint8_t temp;
172133802Sdavidxu
173133802Sdavidxu	/* pullup D+, if possible */
174133802Sdavidxu
175133802Sdavidxu	if (!sc->sc_flags.d_pulled_up &&
176133802Sdavidxu	    sc->sc_flags.port_powered) {
177133802Sdavidxu		sc->sc_flags.d_pulled_up = 1;
178133802Sdavidxu
179133802Sdavidxu		DPRINTF("\n");
180133802Sdavidxu
181133802Sdavidxu		temp = USS820_READ_1(sc, USS820_MCSR);
182133802Sdavidxu		temp |= USS820_MCSR_DPEN;
183133802Sdavidxu		USS820_WRITE_1(sc, USS820_MCSR, temp);
184158680Sdavidxu	}
185158680Sdavidxu}
186132332Smarcel
187132332Smarcelstatic void
188132332Smarceluss820dci_pull_down(struct uss820dci_softc *sc)
189132332Smarcel{
190132332Smarcel	uint8_t temp;
191132332Smarcel
192132332Smarcel	/* pulldown D+, if possible */
193132332Smarcel
194132332Smarcel	if (sc->sc_flags.d_pulled_up) {
195132332Smarcel		sc->sc_flags.d_pulled_up = 0;
196132332Smarcel
197132332Smarcel		DPRINTF("\n");
198132332Smarcel
199132332Smarcel		temp = USS820_READ_1(sc, USS820_MCSR);
200132332Smarcel		temp &= ~USS820_MCSR_DPEN;
201132332Smarcel		USS820_WRITE_1(sc, USS820_MCSR, temp);
202132332Smarcel	}
203132332Smarcel}
204132332Smarcel
205132332Smarcelstatic void
206132332Smarceluss820dci_wakeup_peer(struct uss820dci_softc *sc)
207132332Smarcel{
208132332Smarcel	if (!(sc->sc_flags.status_suspend)) {
209132332Smarcel		return;
210132332Smarcel	}
211132332Smarcel	DPRINTFN(0, "not supported\n");
212132332Smarcel}
213132332Smarcel
214132332Smarcelstatic void
215132332Smarceluss820dci_set_address(struct uss820dci_softc *sc, uint8_t addr)
216132332Smarcel{
217132332Smarcel	DPRINTFN(5, "addr=%d\n", addr);
218132332Smarcel
219132332Smarcel	USS820_WRITE_1(sc, USS820_FADDR, addr);
220132332Smarcel}
221132332Smarcel
222132332Smarcelstatic uint8_t
223132332Smarceluss820dci_setup_rx(struct uss820dci_td *td)
224132332Smarcel{
225132332Smarcel	struct uss820dci_softc *sc;
226132332Smarcel	struct usb2_device_request req;
227132332Smarcel	uint16_t count;
228132332Smarcel	uint8_t rx_stat;
229132332Smarcel	uint8_t temp;
230132332Smarcel
231183021Smarcel	/* select the correct endpoint */
232183021Smarcel	bus_space_write_1(td->io_tag, td->io_hdl,
233132332Smarcel	    USS820_EPINDEX, td->ep_index);
234183021Smarcel
235132332Smarcel	/* read out FIFO status */
236132332Smarcel	rx_stat = bus_space_read_1(td->io_tag, td->io_hdl,
237132332Smarcel	    USS820_RXSTAT);
238132332Smarcel
239132332Smarcel	/* get pointer to softc */
240132332Smarcel	sc = USS820_DCI_PC2SC(td->pc);
241183021Smarcel
242183021Smarcel	DPRINTFN(5, "rx_stat=0x%02x rem=%u\n", rx_stat, td->remainder);
243132332Smarcel
244183021Smarcel	if (!(rx_stat & USS820_RXSTAT_RXSETUP)) {
245183021Smarcel		goto not_complete;
246183021Smarcel	}
247132332Smarcel	/* clear did stall */
248183021Smarcel	td->did_stall = 0;
249132332Smarcel
250132332Smarcel	/* clear stall and all I/O */
251132332Smarcel	uss820dci_update_shared_1(sc, USS820_EPCON,
252132332Smarcel	    0xFF ^ (USS820_EPCON_TXSTL |
253132332Smarcel	    USS820_EPCON_RXSTL |
254132332Smarcel	    USS820_EPCON_RXIE |
255132332Smarcel	    USS820_EPCON_TXOE), 0);
256132332Smarcel
257132332Smarcel	/* clear end overwrite flag */
258183021Smarcel	uss820dci_update_shared_1(sc, USS820_RXSTAT,
259132332Smarcel	    0xFF ^ USS820_RXSTAT_EDOVW, 0);
260183021Smarcel
261132332Smarcel	/* get the packet byte count */
262132332Smarcel	count = bus_space_read_1(td->io_tag, td->io_hdl,
263155411Sdavidxu	    USS820_RXCNTL);
264155411Sdavidxu	count |= (bus_space_read_1(td->io_tag, td->io_hdl,
265132332Smarcel	    USS820_RXCNTH) << 8);
266132332Smarcel	count &= 0x3FF;
267132332Smarcel
268132332Smarcel	/* verify data length */
269132332Smarcel	if (count != td->remainder) {
270132332Smarcel		DPRINTFN(0, "Invalid SETUP packet "
271183021Smarcel		    "length, %d bytes\n", count);
272183021Smarcel		goto setup_not_complete;
273132332Smarcel	}
274183021Smarcel	if (count != sizeof(req)) {
275132332Smarcel		DPRINTFN(0, "Unsupported SETUP packet "
276183021Smarcel		    "length, %d bytes\n", count);
277132332Smarcel		goto setup_not_complete;
278183021Smarcel	}
279132332Smarcel	/* receive data */
280132332Smarcel	bus_space_read_multi_1(td->io_tag, td->io_hdl,
281132332Smarcel	    USS820_RXDAT, (void *)&req, sizeof(req));
282132332Smarcel
283132332Smarcel	/* read out FIFO status */
284132332Smarcel	rx_stat = bus_space_read_1(td->io_tag, td->io_hdl,
285132332Smarcel	    USS820_RXSTAT);
286132332Smarcel
287132332Smarcel	if (rx_stat & (USS820_RXSTAT_EDOVW |
288132332Smarcel	    USS820_RXSTAT_STOVW)) {
289144663Sdavidxu		DPRINTF("new SETUP packet received\n");
290132332Smarcel		return (1);		/* not complete */
291132332Smarcel	}
292132332Smarcel	/* clear receive setup bit */
293132332Smarcel	uss820dci_update_shared_1(sc, USS820_RXSTAT,
294132332Smarcel	    0xFF ^ (USS820_RXSTAT_RXSETUP |
295132332Smarcel	    USS820_RXSTAT_EDOVW |
296183021Smarcel	    USS820_RXSTAT_STOVW), 0);
297183021Smarcel
298132332Smarcel	/* set RXFFRC bit */
299183021Smarcel	temp = bus_space_read_1(td->io_tag, td->io_hdl,
300132332Smarcel	    USS820_RXCON);
301132332Smarcel	temp |= USS820_RXCON_RXFFRC;
302183021Smarcel	bus_space_write_1(td->io_tag, td->io_hdl,
303132332Smarcel	    USS820_RXCON, temp);
304183021Smarcel
305132332Smarcel	/* copy data into real buffer */
306183021Smarcel	usb2_copy_in(td->pc, 0, &req, sizeof(req));
307132332Smarcel
308183021Smarcel	td->offset = sizeof(req);
309183021Smarcel	td->remainder = 0;
310183021Smarcel
311132332Smarcel	/* sneak peek the set address */
312183021Smarcel	if ((req.bmRequestType == UT_WRITE_DEVICE) &&
313183021Smarcel	    (req.bRequest == UR_SET_ADDRESS)) {
314132332Smarcel		sc->sc_dv_addr = req.wValue[0] & 0x7F;
315132332Smarcel	} else {
316132332Smarcel		sc->sc_dv_addr = 0xFF;
317132332Smarcel	}
318132332Smarcel	return (0);			/* complete */
319144663Sdavidxu
320132332Smarcelsetup_not_complete:
321132332Smarcel
322132332Smarcel	/* set RXFFRC bit */
323132332Smarcel	temp = bus_space_read_1(td->io_tag, td->io_hdl,
324183021Smarcel	    USS820_RXCON);
325132332Smarcel	temp |= USS820_RXCON_RXFFRC;
326183021Smarcel	bus_space_write_1(td->io_tag, td->io_hdl,
327132332Smarcel	    USS820_RXCON, temp);
328132332Smarcel
329132332Smarcel	/* FALLTHROUGH */
330132332Smarcel
331132332Smarcelnot_complete:
332132332Smarcel	/* abort any ongoing transfer */
333181341Smarcel	if (!td->did_stall) {
334181341Smarcel		DPRINTFN(5, "stalling\n");
335181341Smarcel		/* set stall */
336132332Smarcel		uss820dci_update_shared_1(sc, USS820_EPCON, 0xFF,
337132332Smarcel		    (USS820_EPCON_TXSTL | USS820_EPCON_RXSTL));
338132332Smarcel
339132332Smarcel		td->did_stall = 1;
340183021Smarcel	}
341132332Smarcel
342132332Smarcel	/* clear end overwrite flag, if any */
343132332Smarcel	if (rx_stat & USS820_RXSTAT_RXSETUP) {
344132332Smarcel		uss820dci_update_shared_1(sc, USS820_RXSTAT,
345132332Smarcel		    0xFF ^ (USS820_RXSTAT_EDOVW |
346132332Smarcel		    USS820_RXSTAT_STOVW |
347132332Smarcel		    USS820_RXSTAT_RXSETUP), 0);
348132332Smarcel	}
349132332Smarcel	return (1);			/* not complete */
350132332Smarcel
351183021Smarcel}
352183021Smarcel
353183021Smarcelstatic uint8_t
354132332Smarceluss820dci_data_rx(struct uss820dci_td *td)
355132332Smarcel{
356132332Smarcel	struct usb2_page_search buf_res;
357144663Sdavidxu	uint16_t count;
358132332Smarcel	uint8_t rx_flag;
359132332Smarcel	uint8_t rx_stat;
360132332Smarcel	uint8_t rx_cntl;
361132332Smarcel	uint8_t to;
362132332Smarcel	uint8_t got_short;
363132332Smarcel
364183021Smarcel	to = 2;				/* don't loop forever! */
365183021Smarcel	got_short = 0;
366183021Smarcel
367132332Smarcel	/* select the correct endpoint */
368132332Smarcel	bus_space_write_1(td->io_tag, td->io_hdl, USS820_EPINDEX, td->ep_index);
369132332Smarcel
370132332Smarcel	/* check if any of the FIFO banks have data */
371132332Smarcelrepeat:
372132332Smarcel	/* read out FIFO flag */
373132332Smarcel	rx_flag = bus_space_read_1(td->io_tag, td->io_hdl,
374181341Smarcel	    USS820_RXFLG);
375133802Sdavidxu	/* read out FIFO status */
376133802Sdavidxu	rx_stat = bus_space_read_1(td->io_tag, td->io_hdl,
377132332Smarcel	    USS820_RXSTAT);
378132332Smarcel
379132332Smarcel	DPRINTFN(5, "rx_stat=0x%02x rx_flag=0x%02x rem=%u\n",
380133802Sdavidxu	    rx_stat, rx_flag, td->remainder);
381133802Sdavidxu
382133802Sdavidxu	if (rx_stat & (USS820_RXSTAT_RXSETUP |
383132332Smarcel	    USS820_RXSTAT_RXSOVW |
384133802Sdavidxu	    USS820_RXSTAT_EDOVW)) {
385133805Sdavidxu		if (td->remainder == 0) {
386133805Sdavidxu			/*
387132332Smarcel			 * We are actually complete and have
388133805Sdavidxu			 * received the next SETUP
389133802Sdavidxu			 */
390181341Smarcel			DPRINTFN(5, "faking complete\n");
391181341Smarcel			return (0);	/* complete */
392181341Smarcel		}
393181341Smarcel		/*
394133802Sdavidxu	         * USB Host Aborted the transfer.
395133802Sdavidxu	         */
396133802Sdavidxu		td->error = 1;
397133802Sdavidxu		return (0);		/* complete */
398132332Smarcel	}
399133802Sdavidxu	/* check for errors */
400132332Smarcel	if (rx_flag & (USS820_RXFLG_RXOVF |
401132332Smarcel	    USS820_RXFLG_RXURF)) {
402133802Sdavidxu		DPRINTFN(5, "overflow or underflow\n");
403132332Smarcel		/* should not happen */
404132332Smarcel		td->error = 1;
405132332Smarcel		return (0);		/* complete */
406132332Smarcel	}
407181341Smarcel	/* check status */
408181341Smarcel	if (!(rx_flag & (USS820_RXFLG_RXFIF0 |
409132332Smarcel	    USS820_RXFLG_RXFIF1))) {
410132332Smarcel
411144922Sdavidxu		/* read out EPCON register */
412132332Smarcel		/* enable RX input */
413132332Smarcel		if (!td->did_stall) {
414132332Smarcel			uss820dci_update_shared_1(USS820_DCI_PC2SC(td->pc),
415181341Smarcel			    USS820_EPCON, 0xFF, USS820_EPCON_RXIE);
416181341Smarcel			td->did_stall = 1;
417132332Smarcel		}
418132332Smarcel		return (1);		/* not complete */
419144922Sdavidxu	}
420132332Smarcel	/* get the packet byte count */
421132332Smarcel	count = bus_space_read_1(td->io_tag, td->io_hdl,
422132332Smarcel	    USS820_RXCNTL);
423181341Smarcel
424181341Smarcel	count |= (bus_space_read_1(td->io_tag, td->io_hdl,
425132332Smarcel	    USS820_RXCNTH) << 8);
426132332Smarcel	count &= 0x3FF;
427144922Sdavidxu
428132332Smarcel	DPRINTFN(5, "count=0x%04x\n", count);
429132332Smarcel
430132332Smarcel	/* verify the packet byte count */
431181341Smarcel	if (count != td->max_packet_size) {
432181341Smarcel		if (count < td->max_packet_size) {
433132332Smarcel			/* we have a short packet */
434132332Smarcel			td->short_pkt = 1;
435132332Smarcel			got_short = 1;
436132332Smarcel		} else {
437132332Smarcel			/* invalid USB packet */
438132332Smarcel			td->error = 1;
439132951Sdavidxu			return (0);	/* we are complete */
440132951Sdavidxu		}
441181341Smarcel	}
442132951Sdavidxu	/* verify the packet byte count */
443132951Sdavidxu	if (count > td->remainder) {
444132951Sdavidxu		/* invalid USB packet */
445133342Sdavidxu		td->error = 1;
446132951Sdavidxu		return (0);		/* we are complete */
447132951Sdavidxu	}
448132951Sdavidxu	while (count > 0) {
449132951Sdavidxu		usb2_get_page(td->pc, td->offset, &buf_res);
450132951Sdavidxu
451132951Sdavidxu		/* get correct length */
452132951Sdavidxu		if (buf_res.length > count) {
453132951Sdavidxu			buf_res.length = count;
454132951Sdavidxu		}
455132951Sdavidxu		/* receive data */
456132951Sdavidxu		bus_space_read_multi_1(td->io_tag, td->io_hdl,
457132951Sdavidxu		    USS820_RXDAT, buf_res.buffer, buf_res.length);
458132951Sdavidxu
459132951Sdavidxu		/* update counters */
460132951Sdavidxu		count -= buf_res.length;
461132951Sdavidxu		td->offset += buf_res.length;
462133802Sdavidxu		td->remainder -= buf_res.length;
463132951Sdavidxu	}
464132951Sdavidxu
465132951Sdavidxu	/* set RXFFRC bit */
466132951Sdavidxu	rx_cntl = bus_space_read_1(td->io_tag, td->io_hdl,
467133802Sdavidxu	    USS820_RXCON);
468133802Sdavidxu	rx_cntl |= USS820_RXCON_RXFFRC;
469132951Sdavidxu	bus_space_write_1(td->io_tag, td->io_hdl,
470132951Sdavidxu	    USS820_RXCON, rx_cntl);
471133802Sdavidxu
472132951Sdavidxu	/* check if we are complete */
473132951Sdavidxu	if ((td->remainder == 0) || got_short) {
474132951Sdavidxu		if (td->short_pkt) {
475132951Sdavidxu			/* we are complete */
476133342Sdavidxu			return (0);
477133342Sdavidxu		}
478133342Sdavidxu		/* else need to receive a zero length packet */
479133802Sdavidxu	}
480133342Sdavidxu	if (--to) {
481133342Sdavidxu		goto repeat;
482133342Sdavidxu	}
483133342Sdavidxu	return (1);			/* not complete */
484133342Sdavidxu}
485133342Sdavidxu
486133802Sdavidxustatic uint8_t
487133342Sdavidxuuss820dci_data_tx(struct uss820dci_td *td)
488133342Sdavidxu{
489133342Sdavidxu	struct usb2_page_search buf_res;
490133802Sdavidxu	uint16_t count;
491133802Sdavidxu	uint16_t count_copy;
492133342Sdavidxu	uint8_t rx_stat;
493133342Sdavidxu	uint8_t tx_flag;
494133342Sdavidxu	uint8_t to;
495133342Sdavidxu
496133802Sdavidxu	/* select the correct endpoint */
497133342Sdavidxu	bus_space_write_1(td->io_tag, td->io_hdl,
498133342Sdavidxu	    USS820_EPINDEX, td->ep_index);
499133342Sdavidxu
500133342Sdavidxu	to = 2;				/* don't loop forever! */
501133342Sdavidxu
502133342Sdavidxurepeat:
503133342Sdavidxu	/* read out TX FIFO flags */
504133342Sdavidxu	tx_flag = bus_space_read_1(td->io_tag, td->io_hdl,
505133342Sdavidxu	    USS820_TXFLG);
506132951Sdavidxu
507133342Sdavidxu	/* read out RX FIFO status last */
508132951Sdavidxu	rx_stat = bus_space_read_1(td->io_tag, td->io_hdl,
509132951Sdavidxu	    USS820_RXSTAT);
510133342Sdavidxu
511133342Sdavidxu	DPRINTFN(5, "rx_stat=0x%02x tx_flag=0x%02x rem=%u\n",
512133342Sdavidxu	    rx_stat, tx_flag, td->remainder);
513133342Sdavidxu
514155413Sdavidxu	if (rx_stat & (USS820_RXSTAT_RXSETUP |
515133342Sdavidxu	    USS820_RXSTAT_RXSOVW |
516133342Sdavidxu	    USS820_RXSTAT_EDOVW)) {
517133342Sdavidxu		/*
518133342Sdavidxu	         * The current transfer was aborted
519133342Sdavidxu	         * by the USB Host
520133342Sdavidxu	         */
521133342Sdavidxu		td->error = 1;
522133342Sdavidxu		return (0);		/* complete */
523133342Sdavidxu	}
524133342Sdavidxu	if (tx_flag & (USS820_TXFLG_TXOVF |
525132951Sdavidxu	    USS820_TXFLG_TXURF)) {
526132951Sdavidxu		td->error = 1;
527132951Sdavidxu		return (0);		/* complete */
528132951Sdavidxu	}
529132951Sdavidxu	if (tx_flag & USS820_TXFLG_TXFIF0) {
530132951Sdavidxu		if (tx_flag & USS820_TXFLG_TXFIF1) {
531132951Sdavidxu			return (1);	/* not complete */
532132951Sdavidxu		}
533132951Sdavidxu	}
534133047Sdavidxu	if ((!td->support_multi_buffer) &&
535132951Sdavidxu	    (tx_flag & (USS820_TXFLG_TXFIF0 |
536133047Sdavidxu	    USS820_TXFLG_TXFIF1))) {
537132951Sdavidxu		return (1);		/* not complete */
538132951Sdavidxu	}
539132951Sdavidxu	count = td->max_packet_size;
540132951Sdavidxu	if (td->remainder < count) {
541132951Sdavidxu		/* we have a short packet */
542132951Sdavidxu		td->short_pkt = 1;
543132951Sdavidxu		count = td->remainder;
544132332Smarcel	}
545132332Smarcel	count_copy = count;
546132332Smarcel	while (count > 0) {
547132951Sdavidxu
548132951Sdavidxu		usb2_get_page(td->pc, td->offset, &buf_res);
549132332Smarcel
550132332Smarcel		/* get correct length */
551132332Smarcel		if (buf_res.length > count) {
552132332Smarcel			buf_res.length = count;
553132332Smarcel		}
554132332Smarcel		/* transmit data */
555132951Sdavidxu		bus_space_write_multi_1(td->io_tag, td->io_hdl,
556132951Sdavidxu		    USS820_TXDAT, buf_res.buffer, buf_res.length);
557132332Smarcel
558132332Smarcel		/* update counters */
559132332Smarcel		count -= buf_res.length;
560132332Smarcel		td->offset += buf_res.length;
561132332Smarcel		td->remainder -= buf_res.length;
562132332Smarcel	}
563132332Smarcel
564132332Smarcel	/* post-write high packet byte count first */
565132332Smarcel	bus_space_write_1(td->io_tag, td->io_hdl,
566132332Smarcel	    USS820_TXCNTH, count_copy >> 8);
567132332Smarcel
568132332Smarcel	/* post-write low packet byte count last */
569132951Sdavidxu	bus_space_write_1(td->io_tag, td->io_hdl,
570132332Smarcel	    USS820_TXCNTL, count_copy);
571132332Smarcel
572132332Smarcel	/*
573209689Skib	 * Enable TX output, which must happen after that we have written
574132332Smarcel	 * data into the FIFO. This is undocumented.
575132332Smarcel	 */
576158680Sdavidxu	if (!td->did_stall) {
577133802Sdavidxu		uss820dci_update_shared_1(USS820_DCI_PC2SC(td->pc),
578133802Sdavidxu		    USS820_EPCON, 0xFF, USS820_EPCON_TXOE);
579158680Sdavidxu		td->did_stall = 1;
580133802Sdavidxu	}
581132332Smarcel	/* check remainder */
582158680Sdavidxu	if (td->remainder == 0) {
583132332Smarcel		if (td->short_pkt) {
584132332Smarcel			return (0);	/* complete */
585132332Smarcel		}
586155387Sdavidxu		/* else we need to transmit a short packet */
587132332Smarcel	}
588132332Smarcel	if (--to) {
589132332Smarcel		goto repeat;
590132332Smarcel	}
591132332Smarcel	return (1);			/* not complete */
592132332Smarcel}
593132332Smarcel
594132332Smarcelstatic uint8_t
595132332Smarceluss820dci_data_tx_sync(struct uss820dci_td *td)
596132332Smarcel{
597132332Smarcel	struct uss820dci_softc *sc;
598132332Smarcel	uint8_t rx_stat;
599132332Smarcel	uint8_t tx_flag;
600158680Sdavidxu
601158680Sdavidxu	/* select the correct endpoint */
602158680Sdavidxu	bus_space_write_1(td->io_tag, td->io_hdl,
603158680Sdavidxu	    USS820_EPINDEX, td->ep_index);
604158680Sdavidxu
605158680Sdavidxu	/* read out TX FIFO flag */
606133802Sdavidxu	tx_flag = bus_space_read_1(td->io_tag, td->io_hdl,
607133802Sdavidxu	    USS820_TXFLG);
608132332Smarcel
609132332Smarcel	/* read out RX FIFO status last */
610133802Sdavidxu	rx_stat = bus_space_read_1(td->io_tag, td->io_hdl,
611133802Sdavidxu	    USS820_RXSTAT);
612132332Smarcel
613133802Sdavidxu	DPRINTFN(5, "rx_stat=0x%02x rem=%u\n", rx_stat, td->remainder);
614133802Sdavidxu
615132332Smarcel	if (rx_stat & (USS820_RXSTAT_RXSETUP |
616132332Smarcel	    USS820_RXSTAT_RXSOVW |
617132332Smarcel	    USS820_RXSTAT_EDOVW)) {
618132951Sdavidxu		DPRINTFN(5, "faking complete\n");
619133802Sdavidxu		/* Race condition */
620133802Sdavidxu		return (0);		/* complete */
621132951Sdavidxu	}
622132951Sdavidxu	DPRINTFN(5, "tx_flag=0x%02x rem=%u\n",
623132951Sdavidxu	    tx_flag, td->remainder);
624158680Sdavidxu
625158680Sdavidxu	if (tx_flag & (USS820_TXFLG_TXOVF |
626158680Sdavidxu	    USS820_TXFLG_TXURF)) {
627158680Sdavidxu		td->error = 1;
628132332Smarcel		return (0);		/* complete */
629132332Smarcel	}
630158680Sdavidxu	if (tx_flag & (USS820_TXFLG_TXFIF0 |
631158680Sdavidxu	    USS820_TXFLG_TXFIF1)) {
632158680Sdavidxu		return (1);		/* not complete */
633158680Sdavidxu	}
634158680Sdavidxu	sc = USS820_DCI_PC2SC(td->pc);
635158680Sdavidxu	if (sc->sc_dv_addr != 0xFF) {
636158680Sdavidxu		/* write function address */
637158680Sdavidxu		uss820dci_set_address(sc, sc->sc_dv_addr);
638158680Sdavidxu	}
639158680Sdavidxu	return (0);			/* complete */
640158680Sdavidxu}
641158680Sdavidxu
642158680Sdavidxustatic uint8_t
643158680Sdavidxuuss820dci_xfer_do_fifo(struct usb2_xfer *xfer)
644158680Sdavidxu{
645158680Sdavidxu	struct uss820dci_td *td;
646158680Sdavidxu
647158680Sdavidxu	DPRINTFN(9, "\n");
648158680Sdavidxu
649158680Sdavidxu	td = xfer->td_transfer_cache;
650158680Sdavidxu	while (1) {
651133802Sdavidxu		if ((td->func) (td)) {
652132332Smarcel			/* operation in progress */
653133802Sdavidxu			break;
654133802Sdavidxu		}
655133802Sdavidxu		if (((void *)td) == xfer->td_transfer_last) {
656132332Smarcel			goto done;
657133047Sdavidxu		}
658132332Smarcel		if (td->error) {
659132332Smarcel			goto done;
660132332Smarcel		} else if (td->remainder > 0) {
661132332Smarcel			/*
662209689Skib			 * We had a short transfer. If there is no alternate
663209689Skib			 * next, stop processing !
664209689Skib			 */
665209689Skib			if (!td->alt_next) {
666209689Skib				goto done;
667209689Skib			}
668209689Skib		}
669209689Skib		/*
670209689Skib		 * Fetch the next transfer descriptor.
671209689Skib		 */
672146818Sdfr		td = td->obj_next;
673132332Smarcel		xfer->td_transfer_cache = td;
674146818Sdfr	}
675146818Sdfr	return (1);			/* not complete */
676146818Sdfr
677146818Sdfrdone:
678146818Sdfr	/* compute all actual lengths */
679146818Sdfr
680146818Sdfr	uss820dci_standard_done(xfer);
681146818Sdfr
682146818Sdfr	return (0);			/* complete */
683146818Sdfr}
684146818Sdfr
685146818Sdfrstatic void
686146818Sdfruss820dci_interrupt_poll(struct uss820dci_softc *sc)
687146818Sdfr{
688146818Sdfr	struct usb2_xfer *xfer;
689146818Sdfr
690146818Sdfrrepeat:
691146818Sdfr	TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
692146818Sdfr		if (!uss820dci_xfer_do_fifo(xfer)) {
693146818Sdfr			/* queue has been modified */
694146818Sdfr			goto repeat;
695146818Sdfr		}
696146818Sdfr	}
697146818Sdfr}
698146818Sdfr
699146818Sdfrstatic void
700146818Sdfruss820dci_wait_suspend(struct uss820dci_softc *sc, uint8_t on)
701146818Sdfr{
702146818Sdfr	uint8_t scr;
703146818Sdfr	uint8_t scratch;
704146818Sdfr
705146818Sdfr	scr = USS820_READ_1(sc, USS820_SCR);
706146818Sdfr	scratch = USS820_READ_1(sc, USS820_SCRATCH);
707146818Sdfr
708146818Sdfr	if (on) {
709146818Sdfr		scr |= USS820_SCR_IE_SUSP;
710146818Sdfr		scratch &= ~USS820_SCRATCH_IE_RESUME;
711146818Sdfr	} else {
712146818Sdfr		scr &= ~USS820_SCR_IE_SUSP;
713146818Sdfr		scratch |= USS820_SCRATCH_IE_RESUME;
714146818Sdfr	}
715146818Sdfr
716146818Sdfr	USS820_WRITE_1(sc, USS820_SCR, scr);
717146818Sdfr	USS820_WRITE_1(sc, USS820_SCRATCH, scratch);
718132332Smarcel}
719132332Smarcel
720132332Smarcelvoid
721132332Smarceluss820dci_interrupt(struct uss820dci_softc *sc)
722132332Smarcel{
723132332Smarcel	uint8_t ssr;
724132332Smarcel	uint8_t event;
725132332Smarcel
726132332Smarcel	USB_BUS_LOCK(&sc->sc_bus);
727132332Smarcel
728132332Smarcel	ssr = USS820_READ_1(sc, USS820_SSR);
729132332Smarcel
730132332Smarcel	ssr &= (USS820_SSR_SUSPEND |
731132332Smarcel	    USS820_SSR_RESUME |
732132332Smarcel	    USS820_SSR_RESET);
733132332Smarcel
734132332Smarcel	/* acknowledge all interrupts */
735132332Smarcel
736132332Smarcel	uss820dci_update_shared_1(sc, USS820_SSR, 0, 0);
737133802Sdavidxu
738132951Sdavidxu	/* check for any bus state change interrupts */
739132332Smarcel
740132332Smarcel	if (ssr) {
741133802Sdavidxu
742132332Smarcel		event = 0;
743132332Smarcel
744132332Smarcel		if (ssr & USS820_SSR_RESET) {
745132332Smarcel			sc->sc_flags.status_bus_reset = 1;
746132332Smarcel			sc->sc_flags.status_suspend = 0;
747132332Smarcel			sc->sc_flags.change_suspend = 0;
748132332Smarcel			sc->sc_flags.change_connect = 1;
749132332Smarcel
750132332Smarcel			/* disable resume interrupt */
751132332Smarcel			uss820dci_wait_suspend(sc, 1);
752132332Smarcel
753132332Smarcel			event = 1;
754132332Smarcel		}
755132332Smarcel		/*
756132332Smarcel	         * If "RESUME" and "SUSPEND" is set at the same time
757132332Smarcel	         * we interpret that like "RESUME". Resume is set when
758132332Smarcel	         * there is at least 3 milliseconds of inactivity on
759132332Smarcel	         * the USB BUS.
760132332Smarcel	         */
761132332Smarcel		if (ssr & USS820_SSR_RESUME) {
762132332Smarcel			if (sc->sc_flags.status_suspend) {
763132332Smarcel				sc->sc_flags.status_suspend = 0;
764132332Smarcel				sc->sc_flags.change_suspend = 1;
765132332Smarcel				/* disable resume interrupt */
766132332Smarcel				uss820dci_wait_suspend(sc, 1);
767132332Smarcel				event = 1;
768132332Smarcel			}
769132332Smarcel		} else if (ssr & USS820_SSR_SUSPEND) {
770132332Smarcel			if (!sc->sc_flags.status_suspend) {
771132332Smarcel				sc->sc_flags.status_suspend = 1;
772132332Smarcel				sc->sc_flags.change_suspend = 1;
773132332Smarcel				/* enable resume interrupt */
774132332Smarcel				uss820dci_wait_suspend(sc, 0);
775132332Smarcel				event = 1;
776132332Smarcel			}
777132332Smarcel		}
778132332Smarcel		if (event) {
779133802Sdavidxu
780132332Smarcel			DPRINTF("real bus interrupt 0x%02x\n", ssr);
781132332Smarcel
782132332Smarcel			/* complete root HUB interrupt endpoint */
783133802Sdavidxu			uss820dci_root_intr(sc);
784132332Smarcel		}
785132332Smarcel	}
786132332Smarcel	/* acknowledge all SBI interrupts */
787132332Smarcel	uss820dci_update_shared_1(sc, USS820_SBI, 0, 0);
788132332Smarcel
789132332Smarcel	/* acknowledge all SBI1 interrupts */
790132332Smarcel	uss820dci_update_shared_1(sc, USS820_SBI1, 0, 0);
791132332Smarcel
792132332Smarcel	/* poll all active transfers */
793132332Smarcel	uss820dci_interrupt_poll(sc);
794132332Smarcel
795132332Smarcel	USB_BUS_UNLOCK(&sc->sc_bus);
796132332Smarcel}
797132332Smarcel
798132332Smarcelstatic void
799146818Sdfruss820dci_setup_standard_chain_sub(struct uss820_std_temp *temp)
800132332Smarcel{
801146818Sdfr	struct uss820dci_td *td;
802146818Sdfr
803146818Sdfr	/* get current Transfer Descriptor */
804146818Sdfr	td = temp->td_next;
805146818Sdfr	temp->td = td;
806146818Sdfr
807146818Sdfr	/* prepare for next TD */
808146818Sdfr	temp->td_next = td->obj_next;
809146818Sdfr
810146818Sdfr	/* fill out the Transfer Descriptor */
811146818Sdfr	td->func = temp->func;
812146818Sdfr	td->pc = temp->pc;
813146818Sdfr	td->offset = temp->offset;
814146818Sdfr	td->remainder = temp->len;
815146818Sdfr	td->error = 0;
816146818Sdfr	td->did_stall = 0;
817146818Sdfr	td->short_pkt = temp->short_pkt;
818146818Sdfr	td->alt_next = temp->setup_alt_next;
819146818Sdfr}
820146818Sdfr
821146818Sdfrstatic void
822146818Sdfruss820dci_setup_standard_chain(struct usb2_xfer *xfer)
823146818Sdfr{
824146818Sdfr	struct uss820_std_temp temp;
825146818Sdfr	struct uss820dci_softc *sc;
826146818Sdfr	struct uss820dci_td *td;
827146818Sdfr	uint32_t x;
828146818Sdfr	uint8_t ep_no;
829146818Sdfr
830146818Sdfr	DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n",
831146818Sdfr	    xfer->address, UE_GET_ADDR(xfer->endpoint),
832146818Sdfr	    xfer->sumlen, usb2_get_speed(xfer->xroot->udev));
833146818Sdfr
834146818Sdfr	temp.max_frame_size = xfer->max_frame_size;
835146818Sdfr
836146818Sdfr	td = xfer->td_start[0];
837146818Sdfr	xfer->td_transfer_first = td;
838146818Sdfr	xfer->td_transfer_cache = td;
839146818Sdfr
840146818Sdfr	/* setup temp */
841146818Sdfr
842146818Sdfr	temp.td = NULL;
843146818Sdfr	temp.td_next = xfer->td_start[0];
844146818Sdfr	temp.offset = 0;
845146818Sdfr	temp.setup_alt_next = xfer->flags_int.short_frames_ok;
846146818Sdfr
847146818Sdfr	sc = USS820_DCI_BUS2SC(xfer->xroot->bus);
848146818Sdfr	ep_no = (xfer->endpoint & UE_ADDR);
849146818Sdfr
850146818Sdfr	/* check if we should prepend a setup message */
851132332Smarcel
852132332Smarcel	if (xfer->flags_int.control_xfr) {
853132332Smarcel		if (xfer->flags_int.control_hdr) {
854132332Smarcel
855132332Smarcel			temp.func = &uss820dci_setup_rx;
856132332Smarcel			temp.len = xfer->frlengths[0];
857132332Smarcel			temp.pc = xfer->frbuffers + 0;
858132332Smarcel			temp.short_pkt = temp.len ? 1 : 0;
859132332Smarcel			/* check for last frame */
860132332Smarcel			if (xfer->nframes == 1) {
861132332Smarcel				/* no STATUS stage yet, SETUP is last */
862132332Smarcel				if (xfer->flags_int.control_act)
863132332Smarcel					temp.setup_alt_next = 0;
864132332Smarcel			}
865132332Smarcel
866132332Smarcel			uss820dci_setup_standard_chain_sub(&temp);
867132332Smarcel		}
868132332Smarcel		x = 1;
869132332Smarcel	} else {
870132332Smarcel		x = 0;
871133802Sdavidxu	}
872132332Smarcel
873132332Smarcel	if (x != xfer->nframes) {
874132332Smarcel		if (xfer->endpoint & UE_DIR_IN) {
875133802Sdavidxu			temp.func = &uss820dci_data_tx;
876132332Smarcel		} else {
877132332Smarcel			temp.func = &uss820dci_data_rx;
878132332Smarcel		}
879132332Smarcel
880132332Smarcel		/* setup "pc" pointer */
881132332Smarcel		temp.pc = xfer->frbuffers + x;
882132332Smarcel	}
883132332Smarcel	while (x != xfer->nframes) {
884132332Smarcel
885132332Smarcel		/* DATA0 / DATA1 message */
886132332Smarcel
887132332Smarcel		temp.len = xfer->frlengths[x];
888132332Smarcel
889132332Smarcel		x++;
890132332Smarcel
891132332Smarcel		if (x == xfer->nframes) {
892132332Smarcel			if (xfer->flags_int.control_xfr) {
893132332Smarcel				if (xfer->flags_int.control_act) {
894132332Smarcel					temp.setup_alt_next = 0;
895132332Smarcel				}
896132332Smarcel			} else {
897132332Smarcel				temp.setup_alt_next = 0;
898132332Smarcel			}
899132332Smarcel		}
900132332Smarcel		if (temp.len == 0) {
901132332Smarcel
902132332Smarcel			/* make sure that we send an USB packet */
903132332Smarcel
904132332Smarcel			temp.short_pkt = 0;
905132332Smarcel
906132332Smarcel		} else {
907132332Smarcel
908132332Smarcel			/* regular data transfer */
909132332Smarcel
910132332Smarcel			temp.short_pkt = (xfer->flags.force_short_xfer) ? 0 : 1;
911132332Smarcel		}
912132332Smarcel
913132332Smarcel		uss820dci_setup_standard_chain_sub(&temp);
914132332Smarcel
915132332Smarcel		if (xfer->flags_int.isochronous_xfr) {
916132332Smarcel			temp.offset += temp.len;
917132332Smarcel		} else {
918133802Sdavidxu			/* get next Page Cache pointer */
919132332Smarcel			temp.pc = xfer->frbuffers + x;
920132332Smarcel		}
921132332Smarcel	}
922133802Sdavidxu
923132332Smarcel	/* check for control transfer */
924132332Smarcel	if (xfer->flags_int.control_xfr) {
925132332Smarcel		uint8_t need_sync;
926132332Smarcel
927132332Smarcel		/* always setup a valid "pc" pointer for status and sync */
928132332Smarcel		temp.pc = xfer->frbuffers + 0;
929132332Smarcel		temp.len = 0;
930132332Smarcel		temp.short_pkt = 0;
931132332Smarcel		temp.setup_alt_next = 0;
932132332Smarcel
933132332Smarcel		/* check if we should append a status stage */
934132332Smarcel		if (!xfer->flags_int.control_act) {
935132332Smarcel
936132332Smarcel			/*
937132332Smarcel			 * Send a DATA1 message and invert the current
938132332Smarcel			 * endpoint direction.
939132332Smarcel			 */
940132332Smarcel			if (xfer->endpoint & UE_DIR_IN) {
941132332Smarcel				temp.func = &uss820dci_data_rx;
942132332Smarcel				need_sync = 0;
943132332Smarcel			} else {
944132332Smarcel				temp.func = &uss820dci_data_tx;
945181341Smarcel				need_sync = 1;
946132332Smarcel			}
947132332Smarcel			temp.len = 0;
948144922Sdavidxu			temp.short_pkt = 0;
949132332Smarcel
950132332Smarcel			uss820dci_setup_standard_chain_sub(&temp);
951132332Smarcel			if (need_sync) {
952181341Smarcel				/* we need a SYNC point after TX */
953181341Smarcel				temp.func = &uss820dci_data_tx_sync;
954132332Smarcel				uss820dci_setup_standard_chain_sub(&temp);
955132332Smarcel			}
956144922Sdavidxu		}
957132332Smarcel	}
958132332Smarcel	/* must have at least one frame! */
959132332Smarcel	td = temp.td;
960181341Smarcel	xfer->td_transfer_last = td;
961181341Smarcel}
962132332Smarcel
963132332Smarcelstatic void
964144922Sdavidxuuss820dci_timeout(void *arg)
965132332Smarcel{
966132332Smarcel	struct usb2_xfer *xfer = arg;
967132332Smarcel
968181341Smarcel	DPRINTF("xfer=%p\n", xfer);
969181341Smarcel
970132332Smarcel	USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED);
971132332Smarcel
972132332Smarcel	/* transfer is transferred */
973132332Smarcel	uss820dci_device_done(xfer, USB_ERR_TIMEOUT);
974132332Smarcel}
975132332Smarcel
976132332Smarcelstatic void
977132332Smarceluss820dci_intr_set(struct usb2_xfer *xfer, uint8_t set)
978132332Smarcel{
979132332Smarcel	struct uss820dci_softc *sc = USS820_DCI_BUS2SC(xfer->xroot->bus);
980132332Smarcel	uint8_t ep_no = (xfer->endpoint & UE_ADDR);
981132332Smarcel	uint8_t ep_reg;
982132951Sdavidxu	uint8_t temp;
983132332Smarcel
984132332Smarcel	DPRINTFN(15, "endpoint 0x%02x\n", xfer->endpoint);
985132332Smarcel
986132332Smarcel	if (ep_no > 3) {
987132332Smarcel		ep_reg = USS820_SBIE1;
988132332Smarcel	} else {
989132332Smarcel		ep_reg = USS820_SBIE;
990132332Smarcel	}
991132332Smarcel
992132332Smarcel	ep_no &= 3;
993132332Smarcel	ep_no = 1 << (2 * ep_no);
994132332Smarcel
995132332Smarcel	if (xfer->flags_int.control_xfr) {
996133802Sdavidxu		if (xfer->flags_int.control_hdr) {
997132332Smarcel			ep_no <<= 1;	/* RX interrupt only */
998132332Smarcel		} else {
999132332Smarcel			ep_no |= (ep_no << 1);	/* RX and TX interrupt */
1000132332Smarcel		}
1001132332Smarcel	} else {
1002133802Sdavidxu		if (!(xfer->endpoint & UE_DIR_IN)) {
1003133802Sdavidxu			ep_no <<= 1;
1004133802Sdavidxu		}
1005133802Sdavidxu	}
1006132951Sdavidxu	temp = USS820_READ_1(sc, ep_reg);
1007132951Sdavidxu	if (set) {
1008132951Sdavidxu		temp |= ep_no;
1009132951Sdavidxu	} else {
1010132951Sdavidxu		temp &= ~ep_no;
1011132951Sdavidxu	}
1012133802Sdavidxu	USS820_WRITE_1(sc, ep_reg, temp);
1013133802Sdavidxu}
1014133802Sdavidxu
1015133802Sdavidxustatic void
1016132332Smarceluss820dci_start_standard_chain(struct usb2_xfer *xfer)
1017132332Smarcel{
1018132332Smarcel	DPRINTFN(9, "\n");
1019133802Sdavidxu
1020133802Sdavidxu	/* poll one time */
1021133802Sdavidxu	if (uss820dci_xfer_do_fifo(xfer)) {
1022133802Sdavidxu
1023132332Smarcel		/*
1024132332Smarcel		 * Only enable the endpoint interrupt when we are
1025132332Smarcel		 * actually waiting for data, hence we are dealing
1026132951Sdavidxu		 * with level triggered interrupts !
1027132332Smarcel		 */
1028133802Sdavidxu		uss820dci_intr_set(xfer, 1);
1029132332Smarcel
1030132332Smarcel		/* put transfer on interrupt queue */
1031132332Smarcel		usb2_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer);
1032132332Smarcel
1033132332Smarcel		/* start timeout, if any */
1034132332Smarcel		if (xfer->timeout != 0) {
1035132332Smarcel			usb2_transfer_timeout_ms(xfer,
1036132332Smarcel			    &uss820dci_timeout, xfer->timeout);
1037132332Smarcel		}
1038132332Smarcel	}
1039132332Smarcel}
1040132332Smarcel
1041132332Smarcelstatic void
1042132332Smarceluss820dci_root_intr(struct uss820dci_softc *sc)
1043132332Smarcel{
1044132332Smarcel	DPRINTFN(9, "\n");
1045132332Smarcel
1046132332Smarcel	USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
1047132332Smarcel
1048132332Smarcel	/* set port bit */
1049132332Smarcel	sc->sc_hub_idata[0] = 0x02;	/* we only have one port */
1050132332Smarcel
1051132332Smarcel	uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata,
1052132332Smarcel	    sizeof(sc->sc_hub_idata));
1053132332Smarcel}
1054132332Smarcel
1055132332Smarcelstatic usb2_error_t
1056132332Smarceluss820dci_standard_done_sub(struct usb2_xfer *xfer)
1057132332Smarcel{
1058132332Smarcel	struct uss820dci_td *td;
1059132332Smarcel	uint32_t len;
1060132332Smarcel	uint8_t error;
1061132332Smarcel
1062132332Smarcel	DPRINTFN(9, "\n");
1063132332Smarcel
1064132332Smarcel	td = xfer->td_transfer_cache;
1065132332Smarcel
1066132332Smarcel	do {
1067132332Smarcel		len = td->remainder;
1068132332Smarcel
1069132332Smarcel		if (xfer->aframes != xfer->nframes) {
1070181059Smarcel			/*
1071180982Smarcel		         * Verify the length and subtract
1072180982Smarcel		         * the remainder from "frlengths[]":
1073133342Sdavidxu		         */
1074133342Sdavidxu			if (len > xfer->frlengths[xfer->aframes]) {
1075180982Smarcel				td->error = 1;
1076133342Sdavidxu			} else {
1077133342Sdavidxu				xfer->frlengths[xfer->aframes] -= len;
1078133342Sdavidxu			}
1079180982Smarcel		}
1080133342Sdavidxu		/* Check for transfer error */
1081133342Sdavidxu		if (td->error) {
1082133342Sdavidxu			/* the transfer is finished */
1083133802Sdavidxu			error = 1;
1084133342Sdavidxu			td = NULL;
1085133342Sdavidxu			break;
1086133342Sdavidxu		}
1087133342Sdavidxu		/* Check for short transfer */
1088133342Sdavidxu		if (len > 0) {
1089133342Sdavidxu			if (xfer->flags_int.short_frames_ok) {
1090133802Sdavidxu				/* follow alt next */
1091133342Sdavidxu				if (td->alt_next) {
1092133342Sdavidxu					td = td->obj_next;
1093133342Sdavidxu				} else {
1094133342Sdavidxu					td = NULL;
1095133342Sdavidxu				}
1096133802Sdavidxu			} else {
1097133342Sdavidxu				/* the transfer is finished */
1098133342Sdavidxu				td = NULL;
1099133342Sdavidxu			}
1100133342Sdavidxu			error = 0;
1101180982Smarcel			break;
1102180982Smarcel		}
1103133342Sdavidxu		td = td->obj_next;
1104133342Sdavidxu
1105133342Sdavidxu		/* this USB frame is complete */
1106133342Sdavidxu		error = 0;
1107133342Sdavidxu		break;
1108133342Sdavidxu
1109133342Sdavidxu	} while (0);
1110241720Sed
1111132332Smarcel	/* update transfer cache */
1112132332Smarcel
1113132332Smarcel	xfer->td_transfer_cache = td;
1114132332Smarcel
1115132332Smarcel	return (error ?
1116132332Smarcel	    USB_ERR_STALLED : USB_ERR_NORMAL_COMPLETION);
1117132332Smarcel}
1118132332Smarcel
1119132332Smarcelstatic void
1120132332Smarceluss820dci_standard_done(struct usb2_xfer *xfer)
1121132332Smarcel{
1122132332Smarcel	usb2_error_t err = 0;
1123132332Smarcel
1124132332Smarcel	DPRINTFN(13, "xfer=%p pipe=%p transfer done\n",
1125132332Smarcel	    xfer, xfer->pipe);
1126132332Smarcel
1127209689Skib	/* reset scanner */
1128132332Smarcel
1129132332Smarcel	xfer->td_transfer_cache = xfer->td_transfer_first;
1130132332Smarcel
1131132332Smarcel	if (xfer->flags_int.control_xfr) {
1132132332Smarcel
1133132332Smarcel		if (xfer->flags_int.control_hdr) {
1134132332Smarcel
1135133342Sdavidxu			err = uss820dci_standard_done_sub(xfer);
1136132332Smarcel		}
1137132332Smarcel		xfer->aframes = 1;
1138132332Smarcel
1139146818Sdfr		if (xfer->td_transfer_cache == NULL) {
1140146818Sdfr			goto done;
1141146818Sdfr		}
1142146818Sdfr	}
1143132332Smarcel	while (xfer->aframes != xfer->nframes) {
1144177490Sdavidxu
1145177490Sdavidxu		err = uss820dci_standard_done_sub(xfer);
1146		xfer->aframes++;
1147
1148		if (xfer->td_transfer_cache == NULL) {
1149			goto done;
1150		}
1151	}
1152
1153	if (xfer->flags_int.control_xfr &&
1154	    !xfer->flags_int.control_act) {
1155
1156		err = uss820dci_standard_done_sub(xfer);
1157	}
1158done:
1159	uss820dci_device_done(xfer, err);
1160}
1161
1162/*------------------------------------------------------------------------*
1163 *	uss820dci_device_done
1164 *
1165 * NOTE: this function can be called more than one time on the
1166 * same USB transfer!
1167 *------------------------------------------------------------------------*/
1168static void
1169uss820dci_device_done(struct usb2_xfer *xfer, usb2_error_t error)
1170{
1171	USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED);
1172
1173	DPRINTFN(2, "xfer=%p, pipe=%p, error=%d\n",
1174	    xfer, xfer->pipe, error);
1175
1176	if (xfer->flags_int.usb2_mode == USB_MODE_DEVICE) {
1177		uss820dci_intr_set(xfer, 0);
1178	}
1179	/* dequeue transfer and start next transfer */
1180	usb2_transfer_done(xfer, error);
1181}
1182
1183static void
1184uss820dci_set_stall(struct usb2_device *udev, struct usb2_xfer *xfer,
1185    struct usb2_pipe *pipe)
1186{
1187	struct uss820dci_softc *sc;
1188	uint8_t ep_no;
1189	uint8_t ep_type;
1190	uint8_t ep_dir;
1191	uint8_t temp;
1192
1193	USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED);
1194
1195	DPRINTFN(5, "pipe=%p\n", pipe);
1196
1197	if (xfer) {
1198		/* cancel any ongoing transfers */
1199		uss820dci_device_done(xfer, USB_ERR_STALLED);
1200	}
1201	/* set FORCESTALL */
1202	sc = USS820_DCI_BUS2SC(udev->bus);
1203	ep_no = (pipe->edesc->bEndpointAddress & UE_ADDR);
1204	ep_dir = (pipe->edesc->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT));
1205	ep_type = (pipe->edesc->bmAttributes & UE_XFERTYPE);
1206
1207	if (ep_type == UE_CONTROL) {
1208		/* should not happen */
1209		return;
1210	}
1211	USS820_WRITE_1(sc, USS820_EPINDEX, ep_no);
1212
1213	if (ep_dir == UE_DIR_IN) {
1214		temp = USS820_EPCON_TXSTL;
1215	} else {
1216		temp = USS820_EPCON_RXSTL;
1217	}
1218	uss820dci_update_shared_1(sc, USS820_EPCON, 0xFF, temp);
1219}
1220
1221static void
1222uss820dci_clear_stall_sub(struct uss820dci_softc *sc,
1223    uint8_t ep_no, uint8_t ep_type, uint8_t ep_dir)
1224{
1225	uint8_t temp;
1226
1227	if (ep_type == UE_CONTROL) {
1228		/* clearing stall is not needed */
1229		return;
1230	}
1231	/* select endpoint index */
1232	USS820_WRITE_1(sc, USS820_EPINDEX, ep_no);
1233
1234	/* clear stall and disable I/O transfers */
1235	if (ep_dir == UE_DIR_IN) {
1236		temp = 0xFF ^ (USS820_EPCON_TXOE |
1237		    USS820_EPCON_TXSTL);
1238	} else {
1239		temp = 0xFF ^ (USS820_EPCON_RXIE |
1240		    USS820_EPCON_RXSTL);
1241	}
1242	uss820dci_update_shared_1(sc, USS820_EPCON, temp, 0);
1243
1244	if (ep_dir == UE_DIR_IN) {
1245		/* reset data toggle */
1246		USS820_WRITE_1(sc, USS820_TXSTAT,
1247		    USS820_TXSTAT_TXSOVW);
1248
1249		/* reset FIFO */
1250		temp = USS820_READ_1(sc, USS820_TXCON);
1251		temp |= USS820_TXCON_TXCLR;
1252		USS820_WRITE_1(sc, USS820_TXCON, temp);
1253		temp &= ~USS820_TXCON_TXCLR;
1254		USS820_WRITE_1(sc, USS820_TXCON, temp);
1255	} else {
1256
1257		/* reset data toggle */
1258		uss820dci_update_shared_1(sc, USS820_RXSTAT,
1259		    0, USS820_RXSTAT_RXSOVW);
1260
1261		/* reset FIFO */
1262		temp = USS820_READ_1(sc, USS820_RXCON);
1263		temp |= USS820_RXCON_RXCLR;
1264		temp &= ~USS820_RXCON_RXFFRC;
1265		USS820_WRITE_1(sc, USS820_RXCON, temp);
1266		temp &= ~USS820_RXCON_RXCLR;
1267		USS820_WRITE_1(sc, USS820_RXCON, temp);
1268	}
1269}
1270
1271static void
1272uss820dci_clear_stall(struct usb2_device *udev, struct usb2_pipe *pipe)
1273{
1274	struct uss820dci_softc *sc;
1275	struct usb2_endpoint_descriptor *ed;
1276
1277	USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED);
1278
1279	DPRINTFN(5, "pipe=%p\n", pipe);
1280
1281	/* check mode */
1282	if (udev->flags.usb2_mode != USB_MODE_DEVICE) {
1283		/* not supported */
1284		return;
1285	}
1286	/* get softc */
1287	sc = USS820_DCI_BUS2SC(udev->bus);
1288
1289	/* get endpoint descriptor */
1290	ed = pipe->edesc;
1291
1292	/* reset endpoint */
1293	uss820dci_clear_stall_sub(sc,
1294	    (ed->bEndpointAddress & UE_ADDR),
1295	    (ed->bmAttributes & UE_XFERTYPE),
1296	    (ed->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT)));
1297}
1298
1299usb2_error_t
1300uss820dci_init(struct uss820dci_softc *sc)
1301{
1302	const struct usb2_hw_ep_profile *pf;
1303	uint8_t n;
1304	uint8_t temp;
1305
1306	DPRINTF("start\n");
1307
1308	/* set up the bus structure */
1309	sc->sc_bus.usbrev = USB_REV_1_1;
1310	sc->sc_bus.methods = &uss820dci_bus_methods;
1311
1312	USB_BUS_LOCK(&sc->sc_bus);
1313
1314	/* we always have VBUS */
1315	sc->sc_flags.status_vbus = 1;
1316
1317	/* reset the chip */
1318	USS820_WRITE_1(sc, USS820_SCR, USS820_SCR_SRESET);
1319	DELAY(100);
1320	USS820_WRITE_1(sc, USS820_SCR, 0);
1321
1322	/* wait for reset to complete */
1323	for (n = 0;; n++) {
1324
1325		temp = USS820_READ_1(sc, USS820_MCSR);
1326
1327		if (temp & USS820_MCSR_INIT) {
1328			break;
1329		}
1330		if (n == 100) {
1331			USB_BUS_UNLOCK(&sc->sc_bus);
1332			return (USB_ERR_INVAL);
1333		}
1334		/* wait a little for things to stabilise */
1335		DELAY(100);
1336	}
1337
1338	/* do a pulldown */
1339	uss820dci_pull_down(sc);
1340
1341	/* wait 10ms for pulldown to stabilise */
1342	usb2_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100);
1343
1344	/* check hardware revision */
1345	temp = USS820_READ_1(sc, USS820_REV);
1346
1347	if (temp < 0x13) {
1348		USB_BUS_UNLOCK(&sc->sc_bus);
1349		return (USB_ERR_INVAL);
1350	}
1351	/* enable interrupts */
1352	USS820_WRITE_1(sc, USS820_SCR,
1353	    USS820_SCR_T_IRQ |
1354	    USS820_SCR_IE_RESET |
1355	/* USS820_SCR_RWUPE | */
1356	    USS820_SCR_IE_SUSP |
1357	    USS820_SCR_IRQPOL);
1358
1359	/* enable interrupts */
1360	USS820_WRITE_1(sc, USS820_SCRATCH,
1361	    USS820_SCRATCH_IE_RESUME);
1362
1363	/* enable features */
1364	USS820_WRITE_1(sc, USS820_MCSR,
1365	    USS820_MCSR_BDFEAT |
1366	    USS820_MCSR_FEAT);
1367
1368	sc->sc_flags.mcsr_feat = 1;
1369
1370	/* disable interrupts */
1371	USS820_WRITE_1(sc, USS820_SBIE, 0);
1372
1373	/* disable interrupts */
1374	USS820_WRITE_1(sc, USS820_SBIE1, 0);
1375
1376	/* disable all endpoints */
1377	for (n = 0; n != USS820_EP_MAX; n++) {
1378
1379		/* select endpoint */
1380		USS820_WRITE_1(sc, USS820_EPINDEX, n);
1381
1382		/* disable endpoint */
1383		uss820dci_update_shared_1(sc, USS820_EPCON, 0, 0);
1384	}
1385
1386	/*
1387	 * Initialise default values for some registers that cannot be
1388	 * changed during operation!
1389	 */
1390	for (n = 0; n != USS820_EP_MAX; n++) {
1391
1392		uss820dci_get_hw_ep_profile(NULL, &pf, n);
1393
1394		/* the maximum frame sizes should be the same */
1395		if (pf->max_in_frame_size != pf->max_out_frame_size) {
1396			DPRINTF("Max frame size mismatch %u != %u\n",
1397			    pf->max_in_frame_size, pf->max_out_frame_size);
1398		}
1399		if (pf->support_isochronous) {
1400			if (pf->max_in_frame_size <= 64) {
1401				temp = (USS820_TXCON_FFSZ_16_64 |
1402				    USS820_TXCON_TXISO |
1403				    USS820_TXCON_ATM);
1404			} else if (pf->max_in_frame_size <= 256) {
1405				temp = (USS820_TXCON_FFSZ_64_256 |
1406				    USS820_TXCON_TXISO |
1407				    USS820_TXCON_ATM);
1408			} else if (pf->max_in_frame_size <= 512) {
1409				temp = (USS820_TXCON_FFSZ_8_512 |
1410				    USS820_TXCON_TXISO |
1411				    USS820_TXCON_ATM);
1412			} else {	/* 1024 bytes */
1413				temp = (USS820_TXCON_FFSZ_32_1024 |
1414				    USS820_TXCON_TXISO |
1415				    USS820_TXCON_ATM);
1416			}
1417		} else {
1418			if ((pf->max_in_frame_size <= 8) &&
1419			    (sc->sc_flags.mcsr_feat)) {
1420				temp = (USS820_TXCON_FFSZ_8_512 |
1421				    USS820_TXCON_ATM);
1422			} else if (pf->max_in_frame_size <= 16) {
1423				temp = (USS820_TXCON_FFSZ_16_64 |
1424				    USS820_TXCON_ATM);
1425			} else if ((pf->max_in_frame_size <= 32) &&
1426			    (sc->sc_flags.mcsr_feat)) {
1427				temp = (USS820_TXCON_FFSZ_32_1024 |
1428				    USS820_TXCON_ATM);
1429			} else {	/* 64 bytes */
1430				temp = (USS820_TXCON_FFSZ_64_256 |
1431				    USS820_TXCON_ATM);
1432			}
1433		}
1434
1435		/* need to configure the chip early */
1436
1437		USS820_WRITE_1(sc, USS820_EPINDEX, n);
1438		USS820_WRITE_1(sc, USS820_TXCON, temp);
1439		USS820_WRITE_1(sc, USS820_RXCON, temp);
1440
1441		if (pf->support_control) {
1442			temp = USS820_EPCON_CTLEP |
1443			    USS820_EPCON_RXSPM |
1444			    USS820_EPCON_RXIE |
1445			    USS820_EPCON_RXEPEN |
1446			    USS820_EPCON_TXOE |
1447			    USS820_EPCON_TXEPEN;
1448		} else {
1449			temp = USS820_EPCON_RXEPEN | USS820_EPCON_TXEPEN;
1450		}
1451
1452		uss820dci_update_shared_1(sc, USS820_EPCON, 0xFF, temp);
1453	}
1454
1455	USB_BUS_UNLOCK(&sc->sc_bus);
1456
1457	/* catch any lost interrupts */
1458
1459	uss820dci_do_poll(&sc->sc_bus);
1460
1461	return (0);			/* success */
1462}
1463
1464void
1465uss820dci_uninit(struct uss820dci_softc *sc)
1466{
1467	uint8_t temp;
1468
1469	USB_BUS_LOCK(&sc->sc_bus);
1470
1471	/* disable all interrupts */
1472	temp = USS820_READ_1(sc, USS820_SCR);
1473	temp &= ~USS820_SCR_T_IRQ;
1474	USS820_WRITE_1(sc, USS820_SCR, temp);
1475
1476	sc->sc_flags.port_powered = 0;
1477	sc->sc_flags.status_vbus = 0;
1478	sc->sc_flags.status_bus_reset = 0;
1479	sc->sc_flags.status_suspend = 0;
1480	sc->sc_flags.change_suspend = 0;
1481	sc->sc_flags.change_connect = 1;
1482
1483	uss820dci_pull_down(sc);
1484	USB_BUS_UNLOCK(&sc->sc_bus);
1485}
1486
1487void
1488uss820dci_suspend(struct uss820dci_softc *sc)
1489{
1490	return;
1491}
1492
1493void
1494uss820dci_resume(struct uss820dci_softc *sc)
1495{
1496	return;
1497}
1498
1499static void
1500uss820dci_do_poll(struct usb2_bus *bus)
1501{
1502	struct uss820dci_softc *sc = USS820_DCI_BUS2SC(bus);
1503
1504	USB_BUS_LOCK(&sc->sc_bus);
1505	uss820dci_interrupt_poll(sc);
1506	USB_BUS_UNLOCK(&sc->sc_bus);
1507}
1508
1509/*------------------------------------------------------------------------*
1510 * at91dci bulk support
1511 *------------------------------------------------------------------------*/
1512static void
1513uss820dci_device_bulk_open(struct usb2_xfer *xfer)
1514{
1515	return;
1516}
1517
1518static void
1519uss820dci_device_bulk_close(struct usb2_xfer *xfer)
1520{
1521	uss820dci_device_done(xfer, USB_ERR_CANCELLED);
1522}
1523
1524static void
1525uss820dci_device_bulk_enter(struct usb2_xfer *xfer)
1526{
1527	return;
1528}
1529
1530static void
1531uss820dci_device_bulk_start(struct usb2_xfer *xfer)
1532{
1533	/* setup TDs */
1534	uss820dci_setup_standard_chain(xfer);
1535	uss820dci_start_standard_chain(xfer);
1536}
1537
1538struct usb2_pipe_methods uss820dci_device_bulk_methods =
1539{
1540	.open = uss820dci_device_bulk_open,
1541	.close = uss820dci_device_bulk_close,
1542	.enter = uss820dci_device_bulk_enter,
1543	.start = uss820dci_device_bulk_start,
1544};
1545
1546/*------------------------------------------------------------------------*
1547 * at91dci control support
1548 *------------------------------------------------------------------------*/
1549static void
1550uss820dci_device_ctrl_open(struct usb2_xfer *xfer)
1551{
1552	return;
1553}
1554
1555static void
1556uss820dci_device_ctrl_close(struct usb2_xfer *xfer)
1557{
1558	uss820dci_device_done(xfer, USB_ERR_CANCELLED);
1559}
1560
1561static void
1562uss820dci_device_ctrl_enter(struct usb2_xfer *xfer)
1563{
1564	return;
1565}
1566
1567static void
1568uss820dci_device_ctrl_start(struct usb2_xfer *xfer)
1569{
1570	/* setup TDs */
1571	uss820dci_setup_standard_chain(xfer);
1572	uss820dci_start_standard_chain(xfer);
1573}
1574
1575struct usb2_pipe_methods uss820dci_device_ctrl_methods =
1576{
1577	.open = uss820dci_device_ctrl_open,
1578	.close = uss820dci_device_ctrl_close,
1579	.enter = uss820dci_device_ctrl_enter,
1580	.start = uss820dci_device_ctrl_start,
1581};
1582
1583/*------------------------------------------------------------------------*
1584 * at91dci interrupt support
1585 *------------------------------------------------------------------------*/
1586static void
1587uss820dci_device_intr_open(struct usb2_xfer *xfer)
1588{
1589	return;
1590}
1591
1592static void
1593uss820dci_device_intr_close(struct usb2_xfer *xfer)
1594{
1595	uss820dci_device_done(xfer, USB_ERR_CANCELLED);
1596}
1597
1598static void
1599uss820dci_device_intr_enter(struct usb2_xfer *xfer)
1600{
1601	return;
1602}
1603
1604static void
1605uss820dci_device_intr_start(struct usb2_xfer *xfer)
1606{
1607	/* setup TDs */
1608	uss820dci_setup_standard_chain(xfer);
1609	uss820dci_start_standard_chain(xfer);
1610}
1611
1612struct usb2_pipe_methods uss820dci_device_intr_methods =
1613{
1614	.open = uss820dci_device_intr_open,
1615	.close = uss820dci_device_intr_close,
1616	.enter = uss820dci_device_intr_enter,
1617	.start = uss820dci_device_intr_start,
1618};
1619
1620/*------------------------------------------------------------------------*
1621 * at91dci full speed isochronous support
1622 *------------------------------------------------------------------------*/
1623static void
1624uss820dci_device_isoc_fs_open(struct usb2_xfer *xfer)
1625{
1626	return;
1627}
1628
1629static void
1630uss820dci_device_isoc_fs_close(struct usb2_xfer *xfer)
1631{
1632	uss820dci_device_done(xfer, USB_ERR_CANCELLED);
1633}
1634
1635static void
1636uss820dci_device_isoc_fs_enter(struct usb2_xfer *xfer)
1637{
1638	struct uss820dci_softc *sc = USS820_DCI_BUS2SC(xfer->xroot->bus);
1639	uint32_t temp;
1640	uint32_t nframes;
1641
1642	DPRINTFN(6, "xfer=%p next=%d nframes=%d\n",
1643	    xfer, xfer->pipe->isoc_next, xfer->nframes);
1644
1645	/* get the current frame index - we don't need the high bits */
1646
1647	nframes = USS820_READ_1(sc, USS820_SOFL);
1648
1649	/*
1650	 * check if the frame index is within the window where the
1651	 * frames will be inserted
1652	 */
1653	temp = (nframes - xfer->pipe->isoc_next) & USS820_SOFL_MASK;
1654
1655	if ((xfer->pipe->is_synced == 0) ||
1656	    (temp < xfer->nframes)) {
1657		/*
1658		 * If there is data underflow or the pipe queue is
1659		 * empty we schedule the transfer a few frames ahead
1660		 * of the current frame position. Else two isochronous
1661		 * transfers might overlap.
1662		 */
1663		xfer->pipe->isoc_next = (nframes + 3) & USS820_SOFL_MASK;
1664		xfer->pipe->is_synced = 1;
1665		DPRINTFN(3, "start next=%d\n", xfer->pipe->isoc_next);
1666	}
1667	/*
1668	 * compute how many milliseconds the insertion is ahead of the
1669	 * current frame position:
1670	 */
1671	temp = (xfer->pipe->isoc_next - nframes) & USS820_SOFL_MASK;
1672
1673	/*
1674	 * pre-compute when the isochronous transfer will be finished:
1675	 */
1676	xfer->isoc_time_complete =
1677	    usb2_isoc_time_expand(&sc->sc_bus, nframes) + temp +
1678	    xfer->nframes;
1679
1680	/* compute frame number for next insertion */
1681	xfer->pipe->isoc_next += xfer->nframes;
1682
1683	/* setup TDs */
1684	uss820dci_setup_standard_chain(xfer);
1685}
1686
1687static void
1688uss820dci_device_isoc_fs_start(struct usb2_xfer *xfer)
1689{
1690	/* start TD chain */
1691	uss820dci_start_standard_chain(xfer);
1692}
1693
1694struct usb2_pipe_methods uss820dci_device_isoc_fs_methods =
1695{
1696	.open = uss820dci_device_isoc_fs_open,
1697	.close = uss820dci_device_isoc_fs_close,
1698	.enter = uss820dci_device_isoc_fs_enter,
1699	.start = uss820dci_device_isoc_fs_start,
1700};
1701
1702/*------------------------------------------------------------------------*
1703 * at91dci root control support
1704 *------------------------------------------------------------------------*
1705 * Simulate a hardware HUB by handling all the necessary requests.
1706 *------------------------------------------------------------------------*/
1707
1708static const struct usb2_device_descriptor uss820dci_devd = {
1709	.bLength = sizeof(struct usb2_device_descriptor),
1710	.bDescriptorType = UDESC_DEVICE,
1711	.bcdUSB = {0x00, 0x02},
1712	.bDeviceClass = UDCLASS_HUB,
1713	.bDeviceSubClass = UDSUBCLASS_HUB,
1714	.bDeviceProtocol = UDPROTO_HSHUBSTT,
1715	.bMaxPacketSize = 64,
1716	.bcdDevice = {0x00, 0x01},
1717	.iManufacturer = 1,
1718	.iProduct = 2,
1719	.bNumConfigurations = 1,
1720};
1721
1722static const struct usb2_device_qualifier uss820dci_odevd = {
1723	.bLength = sizeof(struct usb2_device_qualifier),
1724	.bDescriptorType = UDESC_DEVICE_QUALIFIER,
1725	.bcdUSB = {0x00, 0x02},
1726	.bDeviceClass = UDCLASS_HUB,
1727	.bDeviceSubClass = UDSUBCLASS_HUB,
1728	.bDeviceProtocol = UDPROTO_FSHUB,
1729	.bMaxPacketSize0 = 0,
1730	.bNumConfigurations = 0,
1731};
1732
1733static const struct uss820dci_config_desc uss820dci_confd = {
1734	.confd = {
1735		.bLength = sizeof(struct usb2_config_descriptor),
1736		.bDescriptorType = UDESC_CONFIG,
1737		.wTotalLength[0] = sizeof(uss820dci_confd),
1738		.bNumInterface = 1,
1739		.bConfigurationValue = 1,
1740		.iConfiguration = 0,
1741		.bmAttributes = UC_SELF_POWERED,
1742		.bMaxPower = 0,
1743	},
1744	.ifcd = {
1745		.bLength = sizeof(struct usb2_interface_descriptor),
1746		.bDescriptorType = UDESC_INTERFACE,
1747		.bNumEndpoints = 1,
1748		.bInterfaceClass = UICLASS_HUB,
1749		.bInterfaceSubClass = UISUBCLASS_HUB,
1750		.bInterfaceProtocol = UIPROTO_HSHUBSTT,
1751	},
1752
1753	.endpd = {
1754		.bLength = sizeof(struct usb2_endpoint_descriptor),
1755		.bDescriptorType = UDESC_ENDPOINT,
1756		.bEndpointAddress = (UE_DIR_IN | USS820_DCI_INTR_ENDPT),
1757		.bmAttributes = UE_INTERRUPT,
1758		.wMaxPacketSize[0] = 8,
1759		.bInterval = 255,
1760	},
1761};
1762
1763static const struct usb2_hub_descriptor_min uss820dci_hubd = {
1764	.bDescLength = sizeof(uss820dci_hubd),
1765	.bDescriptorType = UDESC_HUB,
1766	.bNbrPorts = 1,
1767	.wHubCharacteristics[0] =
1768	(UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL) & 0xFF,
1769	.wHubCharacteristics[1] =
1770	(UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL) >> 8,
1771	.bPwrOn2PwrGood = 50,
1772	.bHubContrCurrent = 0,
1773	.DeviceRemovable = {0},		/* port is removable */
1774};
1775
1776#define	STRING_LANG \
1777  0x09, 0x04,				/* American English */
1778
1779#define	STRING_VENDOR \
1780  'A', 0, 'G', 0, 'E', 0, 'R', 0, 'E', 0
1781
1782#define	STRING_PRODUCT \
1783  'D', 0, 'C', 0, 'I', 0, ' ', 0, 'R', 0, \
1784  'o', 0, 'o', 0, 't', 0, ' ', 0, 'H', 0, \
1785  'U', 0, 'B', 0,
1786
1787USB_MAKE_STRING_DESC(STRING_LANG, uss820dci_langtab);
1788USB_MAKE_STRING_DESC(STRING_VENDOR, uss820dci_vendor);
1789USB_MAKE_STRING_DESC(STRING_PRODUCT, uss820dci_product);
1790
1791static usb2_error_t
1792uss820dci_roothub_exec(struct usb2_device *udev,
1793    struct usb2_device_request *req, const void **pptr, uint16_t *plength)
1794{
1795	struct uss820dci_softc *sc = USS820_DCI_BUS2SC(udev->bus);
1796	const void *ptr;
1797	uint16_t len;
1798	uint16_t value;
1799	uint16_t index;
1800	usb2_error_t err;
1801
1802	USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
1803
1804	/* buffer reset */
1805	ptr = (const void *)&sc->sc_hub_temp;
1806	len = 0;
1807	err = 0;
1808
1809	value = UGETW(req->wValue);
1810	index = UGETW(req->wIndex);
1811
1812	/* demultiplex the control request */
1813
1814	switch (req->bmRequestType) {
1815	case UT_READ_DEVICE:
1816		switch (req->bRequest) {
1817		case UR_GET_DESCRIPTOR:
1818			goto tr_handle_get_descriptor;
1819		case UR_GET_CONFIG:
1820			goto tr_handle_get_config;
1821		case UR_GET_STATUS:
1822			goto tr_handle_get_status;
1823		default:
1824			goto tr_stalled;
1825		}
1826		break;
1827
1828	case UT_WRITE_DEVICE:
1829		switch (req->bRequest) {
1830		case UR_SET_ADDRESS:
1831			goto tr_handle_set_address;
1832		case UR_SET_CONFIG:
1833			goto tr_handle_set_config;
1834		case UR_CLEAR_FEATURE:
1835			goto tr_valid;	/* nop */
1836		case UR_SET_DESCRIPTOR:
1837			goto tr_valid;	/* nop */
1838		case UR_SET_FEATURE:
1839		default:
1840			goto tr_stalled;
1841		}
1842		break;
1843
1844	case UT_WRITE_ENDPOINT:
1845		switch (req->bRequest) {
1846		case UR_CLEAR_FEATURE:
1847			switch (UGETW(req->wValue)) {
1848			case UF_ENDPOINT_HALT:
1849				goto tr_handle_clear_halt;
1850			case UF_DEVICE_REMOTE_WAKEUP:
1851				goto tr_handle_clear_wakeup;
1852			default:
1853				goto tr_stalled;
1854			}
1855			break;
1856		case UR_SET_FEATURE:
1857			switch (UGETW(req->wValue)) {
1858			case UF_ENDPOINT_HALT:
1859				goto tr_handle_set_halt;
1860			case UF_DEVICE_REMOTE_WAKEUP:
1861				goto tr_handle_set_wakeup;
1862			default:
1863				goto tr_stalled;
1864			}
1865			break;
1866		case UR_SYNCH_FRAME:
1867			goto tr_valid;	/* nop */
1868		default:
1869			goto tr_stalled;
1870		}
1871		break;
1872
1873	case UT_READ_ENDPOINT:
1874		switch (req->bRequest) {
1875		case UR_GET_STATUS:
1876			goto tr_handle_get_ep_status;
1877		default:
1878			goto tr_stalled;
1879		}
1880		break;
1881
1882	case UT_WRITE_INTERFACE:
1883		switch (req->bRequest) {
1884		case UR_SET_INTERFACE:
1885			goto tr_handle_set_interface;
1886		case UR_CLEAR_FEATURE:
1887			goto tr_valid;	/* nop */
1888		case UR_SET_FEATURE:
1889		default:
1890			goto tr_stalled;
1891		}
1892		break;
1893
1894	case UT_READ_INTERFACE:
1895		switch (req->bRequest) {
1896		case UR_GET_INTERFACE:
1897			goto tr_handle_get_interface;
1898		case UR_GET_STATUS:
1899			goto tr_handle_get_iface_status;
1900		default:
1901			goto tr_stalled;
1902		}
1903		break;
1904
1905	case UT_WRITE_CLASS_INTERFACE:
1906	case UT_WRITE_VENDOR_INTERFACE:
1907		/* XXX forward */
1908		break;
1909
1910	case UT_READ_CLASS_INTERFACE:
1911	case UT_READ_VENDOR_INTERFACE:
1912		/* XXX forward */
1913		break;
1914
1915	case UT_WRITE_CLASS_DEVICE:
1916		switch (req->bRequest) {
1917		case UR_CLEAR_FEATURE:
1918			goto tr_valid;
1919		case UR_SET_DESCRIPTOR:
1920		case UR_SET_FEATURE:
1921			break;
1922		default:
1923			goto tr_stalled;
1924		}
1925		break;
1926
1927	case UT_WRITE_CLASS_OTHER:
1928		switch (req->bRequest) {
1929		case UR_CLEAR_FEATURE:
1930			goto tr_handle_clear_port_feature;
1931		case UR_SET_FEATURE:
1932			goto tr_handle_set_port_feature;
1933		case UR_CLEAR_TT_BUFFER:
1934		case UR_RESET_TT:
1935		case UR_STOP_TT:
1936			goto tr_valid;
1937
1938		default:
1939			goto tr_stalled;
1940		}
1941		break;
1942
1943	case UT_READ_CLASS_OTHER:
1944		switch (req->bRequest) {
1945		case UR_GET_TT_STATE:
1946			goto tr_handle_get_tt_state;
1947		case UR_GET_STATUS:
1948			goto tr_handle_get_port_status;
1949		default:
1950			goto tr_stalled;
1951		}
1952		break;
1953
1954	case UT_READ_CLASS_DEVICE:
1955		switch (req->bRequest) {
1956		case UR_GET_DESCRIPTOR:
1957			goto tr_handle_get_class_descriptor;
1958		case UR_GET_STATUS:
1959			goto tr_handle_get_class_status;
1960
1961		default:
1962			goto tr_stalled;
1963		}
1964		break;
1965	default:
1966		goto tr_stalled;
1967	}
1968	goto tr_valid;
1969
1970tr_handle_get_descriptor:
1971	switch (value >> 8) {
1972	case UDESC_DEVICE:
1973		if (value & 0xff) {
1974			goto tr_stalled;
1975		}
1976		len = sizeof(uss820dci_devd);
1977		ptr = (const void *)&uss820dci_devd;
1978		goto tr_valid;
1979	case UDESC_CONFIG:
1980		if (value & 0xff) {
1981			goto tr_stalled;
1982		}
1983		len = sizeof(uss820dci_confd);
1984		ptr = (const void *)&uss820dci_confd;
1985		goto tr_valid;
1986	case UDESC_STRING:
1987		switch (value & 0xff) {
1988		case 0:		/* Language table */
1989			len = sizeof(uss820dci_langtab);
1990			ptr = (const void *)&uss820dci_langtab;
1991			goto tr_valid;
1992
1993		case 1:		/* Vendor */
1994			len = sizeof(uss820dci_vendor);
1995			ptr = (const void *)&uss820dci_vendor;
1996			goto tr_valid;
1997
1998		case 2:		/* Product */
1999			len = sizeof(uss820dci_product);
2000			ptr = (const void *)&uss820dci_product;
2001			goto tr_valid;
2002		default:
2003			break;
2004		}
2005		break;
2006	default:
2007		goto tr_stalled;
2008	}
2009	goto tr_stalled;
2010
2011tr_handle_get_config:
2012	len = 1;
2013	sc->sc_hub_temp.wValue[0] = sc->sc_conf;
2014	goto tr_valid;
2015
2016tr_handle_get_status:
2017	len = 2;
2018	USETW(sc->sc_hub_temp.wValue, UDS_SELF_POWERED);
2019	goto tr_valid;
2020
2021tr_handle_set_address:
2022	if (value & 0xFF00) {
2023		goto tr_stalled;
2024	}
2025	sc->sc_rt_addr = value;
2026	goto tr_valid;
2027
2028tr_handle_set_config:
2029	if (value >= 2) {
2030		goto tr_stalled;
2031	}
2032	sc->sc_conf = value;
2033	goto tr_valid;
2034
2035tr_handle_get_interface:
2036	len = 1;
2037	sc->sc_hub_temp.wValue[0] = 0;
2038	goto tr_valid;
2039
2040tr_handle_get_tt_state:
2041tr_handle_get_class_status:
2042tr_handle_get_iface_status:
2043tr_handle_get_ep_status:
2044	len = 2;
2045	USETW(sc->sc_hub_temp.wValue, 0);
2046	goto tr_valid;
2047
2048tr_handle_set_halt:
2049tr_handle_set_interface:
2050tr_handle_set_wakeup:
2051tr_handle_clear_wakeup:
2052tr_handle_clear_halt:
2053	goto tr_valid;
2054
2055tr_handle_clear_port_feature:
2056	if (index != 1) {
2057		goto tr_stalled;
2058	}
2059	DPRINTFN(9, "UR_CLEAR_PORT_FEATURE on port %d\n", index);
2060
2061	switch (value) {
2062	case UHF_PORT_SUSPEND:
2063		uss820dci_wakeup_peer(sc);
2064		break;
2065
2066	case UHF_PORT_ENABLE:
2067		sc->sc_flags.port_enabled = 0;
2068		break;
2069
2070	case UHF_PORT_TEST:
2071	case UHF_PORT_INDICATOR:
2072	case UHF_C_PORT_ENABLE:
2073	case UHF_C_PORT_OVER_CURRENT:
2074	case UHF_C_PORT_RESET:
2075		/* nops */
2076		break;
2077	case UHF_PORT_POWER:
2078		sc->sc_flags.port_powered = 0;
2079		uss820dci_pull_down(sc);
2080		break;
2081	case UHF_C_PORT_CONNECTION:
2082		sc->sc_flags.change_connect = 0;
2083		break;
2084	case UHF_C_PORT_SUSPEND:
2085		sc->sc_flags.change_suspend = 0;
2086		break;
2087	default:
2088		err = USB_ERR_IOERROR;
2089		goto done;
2090	}
2091	goto tr_valid;
2092
2093tr_handle_set_port_feature:
2094	if (index != 1) {
2095		goto tr_stalled;
2096	}
2097	DPRINTFN(9, "UR_SET_PORT_FEATURE\n");
2098
2099	switch (value) {
2100	case UHF_PORT_ENABLE:
2101		sc->sc_flags.port_enabled = 1;
2102		break;
2103	case UHF_PORT_SUSPEND:
2104	case UHF_PORT_RESET:
2105	case UHF_PORT_TEST:
2106	case UHF_PORT_INDICATOR:
2107		/* nops */
2108		break;
2109	case UHF_PORT_POWER:
2110		sc->sc_flags.port_powered = 1;
2111		break;
2112	default:
2113		err = USB_ERR_IOERROR;
2114		goto done;
2115	}
2116	goto tr_valid;
2117
2118tr_handle_get_port_status:
2119
2120	DPRINTFN(9, "UR_GET_PORT_STATUS\n");
2121
2122	if (index != 1) {
2123		goto tr_stalled;
2124	}
2125	if (sc->sc_flags.status_vbus) {
2126		uss820dci_pull_up(sc);
2127	} else {
2128		uss820dci_pull_down(sc);
2129	}
2130
2131	/* Select FULL-speed and Device Side Mode */
2132
2133	value = UPS_PORT_MODE_DEVICE;
2134
2135	if (sc->sc_flags.port_powered) {
2136		value |= UPS_PORT_POWER;
2137	}
2138	if (sc->sc_flags.port_enabled) {
2139		value |= UPS_PORT_ENABLED;
2140	}
2141	if (sc->sc_flags.status_vbus &&
2142	    sc->sc_flags.status_bus_reset) {
2143		value |= UPS_CURRENT_CONNECT_STATUS;
2144	}
2145	if (sc->sc_flags.status_suspend) {
2146		value |= UPS_SUSPEND;
2147	}
2148	USETW(sc->sc_hub_temp.ps.wPortStatus, value);
2149
2150	value = 0;
2151
2152	if (sc->sc_flags.change_connect) {
2153		value |= UPS_C_CONNECT_STATUS;
2154	}
2155	if (sc->sc_flags.change_suspend) {
2156		value |= UPS_C_SUSPEND;
2157	}
2158	USETW(sc->sc_hub_temp.ps.wPortChange, value);
2159	len = sizeof(sc->sc_hub_temp.ps);
2160	goto tr_valid;
2161
2162tr_handle_get_class_descriptor:
2163	if (value & 0xFF) {
2164		goto tr_stalled;
2165	}
2166	ptr = (const void *)&uss820dci_hubd;
2167	len = sizeof(uss820dci_hubd);
2168	goto tr_valid;
2169
2170tr_stalled:
2171	err = USB_ERR_STALLED;
2172tr_valid:
2173done:
2174	*plength = len;
2175	*pptr = ptr;
2176	return (err);
2177}
2178
2179static void
2180uss820dci_xfer_setup(struct usb2_setup_params *parm)
2181{
2182	const struct usb2_hw_ep_profile *pf;
2183	struct uss820dci_softc *sc;
2184	struct usb2_xfer *xfer;
2185	void *last_obj;
2186	uint32_t ntd;
2187	uint32_t n;
2188	uint8_t ep_no;
2189
2190	sc = USS820_DCI_BUS2SC(parm->udev->bus);
2191	xfer = parm->curr_xfer;
2192
2193	/*
2194	 * NOTE: This driver does not use any of the parameters that
2195	 * are computed from the following values. Just set some
2196	 * reasonable dummies:
2197	 */
2198	parm->hc_max_packet_size = 0x500;
2199	parm->hc_max_packet_count = 1;
2200	parm->hc_max_frame_size = 0x500;
2201
2202	usb2_transfer_setup_sub(parm);
2203
2204	/*
2205	 * compute maximum number of TDs
2206	 */
2207	if (parm->methods == &uss820dci_device_ctrl_methods) {
2208
2209		ntd = xfer->nframes + 1 /* STATUS */ + 1 /* SYNC */ ;
2210
2211	} else if (parm->methods == &uss820dci_device_bulk_methods) {
2212
2213		ntd = xfer->nframes + 1 /* SYNC */ ;
2214
2215	} else if (parm->methods == &uss820dci_device_intr_methods) {
2216
2217		ntd = xfer->nframes + 1 /* SYNC */ ;
2218
2219	} else if (parm->methods == &uss820dci_device_isoc_fs_methods) {
2220
2221		ntd = xfer->nframes + 1 /* SYNC */ ;
2222
2223	} else {
2224
2225		ntd = 0;
2226	}
2227
2228	/*
2229	 * check if "usb2_transfer_setup_sub" set an error
2230	 */
2231	if (parm->err) {
2232		return;
2233	}
2234	/*
2235	 * allocate transfer descriptors
2236	 */
2237	last_obj = NULL;
2238
2239	/*
2240	 * get profile stuff
2241	 */
2242	if (ntd) {
2243
2244		ep_no = xfer->endpoint & UE_ADDR;
2245		uss820dci_get_hw_ep_profile(parm->udev, &pf, ep_no);
2246
2247		if (pf == NULL) {
2248			/* should not happen */
2249			parm->err = USB_ERR_INVAL;
2250			return;
2251		}
2252	} else {
2253		ep_no = 0;
2254		pf = NULL;
2255	}
2256
2257	/* align data */
2258	parm->size[0] += ((-parm->size[0]) & (USB_HOST_ALIGN - 1));
2259
2260	for (n = 0; n != ntd; n++) {
2261
2262		struct uss820dci_td *td;
2263
2264		if (parm->buf) {
2265
2266			td = USB_ADD_BYTES(parm->buf, parm->size[0]);
2267
2268			/* init TD */
2269			td->io_tag = sc->sc_io_tag;
2270			td->io_hdl = sc->sc_io_hdl;
2271			td->max_packet_size = xfer->max_packet_size;
2272			td->ep_index = ep_no;
2273			if (pf->support_multi_buffer &&
2274			    (parm->methods != &uss820dci_device_ctrl_methods)) {
2275				td->support_multi_buffer = 1;
2276			}
2277			td->obj_next = last_obj;
2278
2279			last_obj = td;
2280		}
2281		parm->size[0] += sizeof(*td);
2282	}
2283
2284	xfer->td_start[0] = last_obj;
2285}
2286
2287static void
2288uss820dci_xfer_unsetup(struct usb2_xfer *xfer)
2289{
2290	return;
2291}
2292
2293static void
2294uss820dci_pipe_init(struct usb2_device *udev, struct usb2_endpoint_descriptor *edesc,
2295    struct usb2_pipe *pipe)
2296{
2297	struct uss820dci_softc *sc = USS820_DCI_BUS2SC(udev->bus);
2298
2299	DPRINTFN(2, "pipe=%p, addr=%d, endpt=%d, mode=%d (%d)\n",
2300	    pipe, udev->address,
2301	    edesc->bEndpointAddress, udev->flags.usb2_mode,
2302	    sc->sc_rt_addr);
2303
2304	if (udev->device_index != sc->sc_rt_addr) {
2305
2306		if (udev->flags.usb2_mode != USB_MODE_DEVICE) {
2307			/* not supported */
2308			return;
2309		}
2310		if (udev->speed != USB_SPEED_FULL) {
2311			/* not supported */
2312			return;
2313		}
2314		switch (edesc->bmAttributes & UE_XFERTYPE) {
2315		case UE_CONTROL:
2316			pipe->methods = &uss820dci_device_ctrl_methods;
2317			break;
2318		case UE_INTERRUPT:
2319			pipe->methods = &uss820dci_device_intr_methods;
2320			break;
2321		case UE_ISOCHRONOUS:
2322			pipe->methods = &uss820dci_device_isoc_fs_methods;
2323			break;
2324		case UE_BULK:
2325			pipe->methods = &uss820dci_device_bulk_methods;
2326			break;
2327		default:
2328			/* do nothing */
2329			break;
2330		}
2331	}
2332}
2333
2334struct usb2_bus_methods uss820dci_bus_methods =
2335{
2336	.pipe_init = &uss820dci_pipe_init,
2337	.xfer_setup = &uss820dci_xfer_setup,
2338	.xfer_unsetup = &uss820dci_xfer_unsetup,
2339	.get_hw_ep_profile = &uss820dci_get_hw_ep_profile,
2340	.set_stall = &uss820dci_set_stall,
2341	.clear_stall = &uss820dci_clear_stall,
2342	.roothub_exec = &uss820dci_roothub_exec,
2343};
2344