1/*- 2 * Copyright (c) 2008 Hans Petter Selasky. All rights reserved. 3 * Copyright (c) 1998 The NetBSD Foundation, Inc. All rights reserved. 4 * Copyright (c) 1998 Lennart Augustsson. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28#include <sys/cdefs.h> 29__FBSDID("$FreeBSD$"); 30 31/* 32 * USB Universal Host Controller driver. 33 * Handles e.g. PIIX3 and PIIX4. 34 * 35 * UHCI spec: http://developer.intel.com/design/USB/UHCI11D.htm 36 * USB spec: http://www.usb.org/developers/docs/usbspec.zip 37 * PIIXn spec: ftp://download.intel.com/design/intarch/datashts/29055002.pdf 38 * ftp://download.intel.com/design/intarch/datashts/29056201.pdf 39 */ 40 41#include <sys/stdint.h> 42#include <sys/stddef.h> 43#include <sys/param.h> 44#include <sys/queue.h> 45#include <sys/types.h> 46#include <sys/systm.h> 47#include <sys/kernel.h> 48#include <sys/bus.h> 49#include <sys/module.h> 50#include <sys/lock.h> 51#include <sys/mutex.h> 52#include <sys/condvar.h> 53#include <sys/sysctl.h> 54#include <sys/sx.h> 55#include <sys/unistd.h> 56#include <sys/callout.h> 57#include <sys/malloc.h> 58#include <sys/priv.h> 59 60#include <dev/usb/usb.h> 61#include <dev/usb/usbdi.h> 62 63#define USB_DEBUG_VAR uhcidebug 64 65#include <dev/usb/usb_core.h> 66#include <dev/usb/usb_debug.h> 67#include <dev/usb/usb_busdma.h> 68#include <dev/usb/usb_process.h> 69#include <dev/usb/usb_transfer.h> 70#include <dev/usb/usb_device.h> 71#include <dev/usb/usb_hub.h> 72#include <dev/usb/usb_util.h> 73 74#include <dev/usb/usb_controller.h> 75#include <dev/usb/usb_bus.h> 76#include <dev/usb/controller/uhci.h> 77#include <dev/usb/controller/uhcireg.h> 78 79#define alt_next next 80#define UHCI_BUS2SC(bus) \ 81 ((uhci_softc_t *)(((uint8_t *)(bus)) - \ 82 ((uint8_t *)&(((uhci_softc_t *)0)->sc_bus)))) 83 84#ifdef USB_DEBUG 85static int uhcidebug = 0; 86static int uhcinoloop = 0; 87 88static SYSCTL_NODE(_hw_usb, OID_AUTO, uhci, CTLFLAG_RW, 0, "USB uhci"); 89SYSCTL_INT(_hw_usb_uhci, OID_AUTO, debug, CTLFLAG_RW | CTLFLAG_TUN, 90 &uhcidebug, 0, "uhci debug level"); 91TUNABLE_INT("hw.usb.uhci.debug", &uhcidebug); 92SYSCTL_INT(_hw_usb_uhci, OID_AUTO, loop, CTLFLAG_RW | CTLFLAG_TUN, 93 &uhcinoloop, 0, "uhci noloop"); 94TUNABLE_INT("hw.usb.uhci.loop", &uhcinoloop); 95 96static void uhci_dumpregs(uhci_softc_t *sc); 97static void uhci_dump_tds(uhci_td_t *td); 98 99#endif 100 101#define UBARR(sc) bus_space_barrier((sc)->sc_io_tag, (sc)->sc_io_hdl, 0, (sc)->sc_io_size, \ 102 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 103#define UWRITE1(sc, r, x) \ 104 do { UBARR(sc); bus_space_write_1((sc)->sc_io_tag, (sc)->sc_io_hdl, (r), (x)); \ 105 } while (/*CONSTCOND*/0) 106#define UWRITE2(sc, r, x) \ 107 do { UBARR(sc); bus_space_write_2((sc)->sc_io_tag, (sc)->sc_io_hdl, (r), (x)); \ 108 } while (/*CONSTCOND*/0) 109#define UWRITE4(sc, r, x) \ 110 do { UBARR(sc); bus_space_write_4((sc)->sc_io_tag, (sc)->sc_io_hdl, (r), (x)); \ 111 } while (/*CONSTCOND*/0) 112#define UREAD1(sc, r) (UBARR(sc), bus_space_read_1((sc)->sc_io_tag, (sc)->sc_io_hdl, (r))) 113#define UREAD2(sc, r) (UBARR(sc), bus_space_read_2((sc)->sc_io_tag, (sc)->sc_io_hdl, (r))) 114#define UREAD4(sc, r) (UBARR(sc), bus_space_read_4((sc)->sc_io_tag, (sc)->sc_io_hdl, (r))) 115 116#define UHCICMD(sc, cmd) UWRITE2(sc, UHCI_CMD, cmd) 117#define UHCISTS(sc) UREAD2(sc, UHCI_STS) 118 119#define UHCI_RESET_TIMEOUT 100 /* ms, reset timeout */ 120 121#define UHCI_INTR_ENDPT 1 122 123struct uhci_mem_layout { 124 125 struct usb_page_search buf_res; 126 struct usb_page_search fix_res; 127 128 struct usb_page_cache *buf_pc; 129 struct usb_page_cache *fix_pc; 130 131 uint32_t buf_offset; 132 133 uint16_t max_frame_size; 134}; 135 136struct uhci_std_temp { 137 138 struct uhci_mem_layout ml; 139 uhci_td_t *td; 140 uhci_td_t *td_next; 141 uint32_t average; 142 uint32_t td_status; 143 uint32_t td_token; 144 uint32_t len; 145 uint16_t max_frame_size; 146 uint8_t shortpkt; 147 uint8_t setup_alt_next; 148 uint8_t last_frame; 149}; 150 151extern struct usb_bus_methods uhci_bus_methods; 152extern struct usb_pipe_methods uhci_device_bulk_methods; 153extern struct usb_pipe_methods uhci_device_ctrl_methods; 154extern struct usb_pipe_methods uhci_device_intr_methods; 155extern struct usb_pipe_methods uhci_device_isoc_methods; 156 157static uint8_t uhci_restart(uhci_softc_t *sc); 158static void uhci_do_poll(struct usb_bus *); 159static void uhci_device_done(struct usb_xfer *, usb_error_t); 160static void uhci_transfer_intr_enqueue(struct usb_xfer *); 161static void uhci_timeout(void *); 162static uint8_t uhci_check_transfer(struct usb_xfer *); 163static void uhci_root_intr(uhci_softc_t *sc); 164 165void 166uhci_iterate_hw_softc(struct usb_bus *bus, usb_bus_mem_sub_cb_t *cb) 167{ 168 struct uhci_softc *sc = UHCI_BUS2SC(bus); 169 uint32_t i; 170 171 cb(bus, &sc->sc_hw.pframes_pc, &sc->sc_hw.pframes_pg, 172 sizeof(uint32_t) * UHCI_FRAMELIST_COUNT, UHCI_FRAMELIST_ALIGN); 173 174 cb(bus, &sc->sc_hw.ls_ctl_start_pc, &sc->sc_hw.ls_ctl_start_pg, 175 sizeof(uhci_qh_t), UHCI_QH_ALIGN); 176 177 cb(bus, &sc->sc_hw.fs_ctl_start_pc, &sc->sc_hw.fs_ctl_start_pg, 178 sizeof(uhci_qh_t), UHCI_QH_ALIGN); 179 180 cb(bus, &sc->sc_hw.bulk_start_pc, &sc->sc_hw.bulk_start_pg, 181 sizeof(uhci_qh_t), UHCI_QH_ALIGN); 182 183 cb(bus, &sc->sc_hw.last_qh_pc, &sc->sc_hw.last_qh_pg, 184 sizeof(uhci_qh_t), UHCI_QH_ALIGN); 185 186 cb(bus, &sc->sc_hw.last_td_pc, &sc->sc_hw.last_td_pg, 187 sizeof(uhci_td_t), UHCI_TD_ALIGN); 188 189 for (i = 0; i != UHCI_VFRAMELIST_COUNT; i++) { 190 cb(bus, sc->sc_hw.isoc_start_pc + i, 191 sc->sc_hw.isoc_start_pg + i, 192 sizeof(uhci_td_t), UHCI_TD_ALIGN); 193 } 194 195 for (i = 0; i != UHCI_IFRAMELIST_COUNT; i++) { 196 cb(bus, sc->sc_hw.intr_start_pc + i, 197 sc->sc_hw.intr_start_pg + i, 198 sizeof(uhci_qh_t), UHCI_QH_ALIGN); 199 } 200} 201 202static void 203uhci_mem_layout_init(struct uhci_mem_layout *ml, struct usb_xfer *xfer) 204{ 205 ml->buf_pc = xfer->frbuffers + 0; 206 ml->fix_pc = xfer->buf_fixup; 207 208 ml->buf_offset = 0; 209 210 ml->max_frame_size = xfer->max_frame_size; 211} 212 213static void 214uhci_mem_layout_fixup(struct uhci_mem_layout *ml, struct uhci_td *td) 215{ 216 usbd_get_page(ml->buf_pc, ml->buf_offset, &ml->buf_res); 217 218 if (ml->buf_res.length < td->len) { 219 220 /* need to do a fixup */ 221 222 usbd_get_page(ml->fix_pc, 0, &ml->fix_res); 223 224 td->td_buffer = htole32(ml->fix_res.physaddr); 225 226 /* 227 * The UHCI driver cannot handle 228 * page crossings, so a fixup is 229 * needed: 230 * 231 * +----+----+ - - - 232 * | YYY|Y | 233 * +----+----+ - - - 234 * \ \ 235 * \ \ 236 * +----+ 237 * |YYYY| (fixup) 238 * +----+ 239 */ 240 241 if ((td->td_token & htole32(UHCI_TD_PID)) == 242 htole32(UHCI_TD_PID_IN)) { 243 td->fix_pc = ml->fix_pc; 244 usb_pc_cpu_invalidate(ml->fix_pc); 245 246 } else { 247 td->fix_pc = NULL; 248 249 /* copy data to fixup location */ 250 251 usbd_copy_out(ml->buf_pc, ml->buf_offset, 252 ml->fix_res.buffer, td->len); 253 254 usb_pc_cpu_flush(ml->fix_pc); 255 } 256 257 /* prepare next fixup */ 258 259 ml->fix_pc++; 260 261 } else { 262 263 td->td_buffer = htole32(ml->buf_res.physaddr); 264 td->fix_pc = NULL; 265 } 266 267 /* prepare next data location */ 268 269 ml->buf_offset += td->len; 270} 271 272/* 273 * Return values: 274 * 0: Success 275 * Else: Failure 276 */ 277static uint8_t 278uhci_restart(uhci_softc_t *sc) 279{ 280 struct usb_page_search buf_res; 281 282 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 283 284 if (UREAD2(sc, UHCI_CMD) & UHCI_CMD_RS) { 285 DPRINTFN(2, "Already started\n"); 286 return (0); 287 } 288 289 DPRINTFN(2, "Restarting\n"); 290 291 usbd_get_page(&sc->sc_hw.pframes_pc, 0, &buf_res); 292 293 /* Reload fresh base address */ 294 UWRITE4(sc, UHCI_FLBASEADDR, buf_res.physaddr); 295 296 /* 297 * Assume 64 byte packets at frame end and start HC controller: 298 */ 299 UHCICMD(sc, (UHCI_CMD_MAXP | UHCI_CMD_RS)); 300 301 /* wait 10 milliseconds */ 302 303 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100); 304 305 /* check that controller has started */ 306 307 if (UREAD2(sc, UHCI_STS) & UHCI_STS_HCH) { 308 DPRINTFN(2, "Failed\n"); 309 return (1); 310 } 311 return (0); 312} 313 314void 315uhci_reset(uhci_softc_t *sc) 316{ 317 uint16_t n; 318 319 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 320 321 DPRINTF("resetting the HC\n"); 322 323 /* disable interrupts */ 324 325 UWRITE2(sc, UHCI_INTR, 0); 326 327 /* global reset */ 328 329 UHCICMD(sc, UHCI_CMD_GRESET); 330 331 /* wait */ 332 333 usb_pause_mtx(&sc->sc_bus.bus_mtx, 334 USB_MS_TO_TICKS(USB_BUS_RESET_DELAY)); 335 336 /* terminate all transfers */ 337 338 UHCICMD(sc, UHCI_CMD_HCRESET); 339 340 /* the reset bit goes low when the controller is done */ 341 342 n = UHCI_RESET_TIMEOUT; 343 while (n--) { 344 /* wait one millisecond */ 345 346 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 1000); 347 348 if (!(UREAD2(sc, UHCI_CMD) & UHCI_CMD_HCRESET)) { 349 goto done_1; 350 } 351 } 352 353 device_printf(sc->sc_bus.bdev, 354 "controller did not reset\n"); 355 356done_1: 357 358 n = 10; 359 while (n--) { 360 /* wait one millisecond */ 361 362 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 1000); 363 364 /* check if HC is stopped */ 365 if (UREAD2(sc, UHCI_STS) & UHCI_STS_HCH) { 366 goto done_2; 367 } 368 } 369 370 device_printf(sc->sc_bus.bdev, 371 "controller did not stop\n"); 372 373done_2: 374 375 /* reset frame number */ 376 UWRITE2(sc, UHCI_FRNUM, 0); 377 /* set default SOF value */ 378 UWRITE1(sc, UHCI_SOF, 0x40); 379 380 USB_BUS_UNLOCK(&sc->sc_bus); 381 382 /* stop root interrupt */ 383 usb_callout_drain(&sc->sc_root_intr); 384 385 USB_BUS_LOCK(&sc->sc_bus); 386} 387 388static void 389uhci_start(uhci_softc_t *sc) 390{ 391 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 392 393 DPRINTFN(2, "enabling\n"); 394 395 /* enable interrupts */ 396 397 UWRITE2(sc, UHCI_INTR, 398 (UHCI_INTR_TOCRCIE | 399 UHCI_INTR_RIE | 400 UHCI_INTR_IOCE | 401 UHCI_INTR_SPIE)); 402 403 if (uhci_restart(sc)) { 404 device_printf(sc->sc_bus.bdev, 405 "cannot start HC controller\n"); 406 } 407 408 /* start root interrupt */ 409 uhci_root_intr(sc); 410} 411 412static struct uhci_qh * 413uhci_init_qh(struct usb_page_cache *pc) 414{ 415 struct usb_page_search buf_res; 416 struct uhci_qh *qh; 417 418 usbd_get_page(pc, 0, &buf_res); 419 420 qh = buf_res.buffer; 421 422 qh->qh_self = 423 htole32(buf_res.physaddr) | 424 htole32(UHCI_PTR_QH); 425 426 qh->page_cache = pc; 427 428 return (qh); 429} 430 431static struct uhci_td * 432uhci_init_td(struct usb_page_cache *pc) 433{ 434 struct usb_page_search buf_res; 435 struct uhci_td *td; 436 437 usbd_get_page(pc, 0, &buf_res); 438 439 td = buf_res.buffer; 440 441 td->td_self = 442 htole32(buf_res.physaddr) | 443 htole32(UHCI_PTR_TD); 444 445 td->page_cache = pc; 446 447 return (td); 448} 449 450usb_error_t 451uhci_init(uhci_softc_t *sc) 452{ 453 uint16_t bit; 454 uint16_t x; 455 uint16_t y; 456 457 DPRINTF("start\n"); 458 459 usb_callout_init_mtx(&sc->sc_root_intr, &sc->sc_bus.bus_mtx, 0); 460 461#ifdef USB_DEBUG 462 if (uhcidebug > 2) { 463 uhci_dumpregs(sc); 464 } 465#endif 466 /* 467 * Setup QH's 468 */ 469 sc->sc_ls_ctl_p_last = 470 uhci_init_qh(&sc->sc_hw.ls_ctl_start_pc); 471 472 sc->sc_fs_ctl_p_last = 473 uhci_init_qh(&sc->sc_hw.fs_ctl_start_pc); 474 475 sc->sc_bulk_p_last = 476 uhci_init_qh(&sc->sc_hw.bulk_start_pc); 477#if 0 478 sc->sc_reclaim_qh_p = 479 sc->sc_fs_ctl_p_last; 480#else 481 /* setup reclaim looping point */ 482 sc->sc_reclaim_qh_p = 483 sc->sc_bulk_p_last; 484#endif 485 486 sc->sc_last_qh_p = 487 uhci_init_qh(&sc->sc_hw.last_qh_pc); 488 489 sc->sc_last_td_p = 490 uhci_init_td(&sc->sc_hw.last_td_pc); 491 492 for (x = 0; x != UHCI_VFRAMELIST_COUNT; x++) { 493 sc->sc_isoc_p_last[x] = 494 uhci_init_td(sc->sc_hw.isoc_start_pc + x); 495 } 496 497 for (x = 0; x != UHCI_IFRAMELIST_COUNT; x++) { 498 sc->sc_intr_p_last[x] = 499 uhci_init_qh(sc->sc_hw.intr_start_pc + x); 500 } 501 502 /* 503 * the QHs are arranged to give poll intervals that are 504 * powers of 2 times 1ms 505 */ 506 bit = UHCI_IFRAMELIST_COUNT / 2; 507 while (bit) { 508 x = bit; 509 while (x & bit) { 510 uhci_qh_t *qh_x; 511 uhci_qh_t *qh_y; 512 513 y = (x ^ bit) | (bit / 2); 514 515 /* 516 * the next QH has half the poll interval 517 */ 518 qh_x = sc->sc_intr_p_last[x]; 519 qh_y = sc->sc_intr_p_last[y]; 520 521 qh_x->h_next = NULL; 522 qh_x->qh_h_next = qh_y->qh_self; 523 qh_x->e_next = NULL; 524 qh_x->qh_e_next = htole32(UHCI_PTR_T); 525 x++; 526 } 527 bit >>= 1; 528 } 529 530 if (1) { 531 uhci_qh_t *qh_ls; 532 uhci_qh_t *qh_intr; 533 534 qh_ls = sc->sc_ls_ctl_p_last; 535 qh_intr = sc->sc_intr_p_last[0]; 536 537 /* start QH for interrupt traffic */ 538 qh_intr->h_next = qh_ls; 539 qh_intr->qh_h_next = qh_ls->qh_self; 540 qh_intr->e_next = 0; 541 qh_intr->qh_e_next = htole32(UHCI_PTR_T); 542 } 543 for (x = 0; x != UHCI_VFRAMELIST_COUNT; x++) { 544 545 uhci_td_t *td_x; 546 uhci_qh_t *qh_intr; 547 548 td_x = sc->sc_isoc_p_last[x]; 549 qh_intr = sc->sc_intr_p_last[x | (UHCI_IFRAMELIST_COUNT / 2)]; 550 551 /* start TD for isochronous traffic */ 552 td_x->next = NULL; 553 td_x->td_next = qh_intr->qh_self; 554 td_x->td_status = htole32(UHCI_TD_IOS); 555 td_x->td_token = htole32(0); 556 td_x->td_buffer = htole32(0); 557 } 558 559 if (1) { 560 uhci_qh_t *qh_ls; 561 uhci_qh_t *qh_fs; 562 563 qh_ls = sc->sc_ls_ctl_p_last; 564 qh_fs = sc->sc_fs_ctl_p_last; 565 566 /* start QH where low speed control traffic will be queued */ 567 qh_ls->h_next = qh_fs; 568 qh_ls->qh_h_next = qh_fs->qh_self; 569 qh_ls->e_next = 0; 570 qh_ls->qh_e_next = htole32(UHCI_PTR_T); 571 } 572 if (1) { 573 uhci_qh_t *qh_ctl; 574 uhci_qh_t *qh_blk; 575 uhci_qh_t *qh_lst; 576 uhci_td_t *td_lst; 577 578 qh_ctl = sc->sc_fs_ctl_p_last; 579 qh_blk = sc->sc_bulk_p_last; 580 581 /* start QH where full speed control traffic will be queued */ 582 qh_ctl->h_next = qh_blk; 583 qh_ctl->qh_h_next = qh_blk->qh_self; 584 qh_ctl->e_next = 0; 585 qh_ctl->qh_e_next = htole32(UHCI_PTR_T); 586 587 qh_lst = sc->sc_last_qh_p; 588 589 /* start QH where bulk traffic will be queued */ 590 qh_blk->h_next = qh_lst; 591 qh_blk->qh_h_next = qh_lst->qh_self; 592 qh_blk->e_next = 0; 593 qh_blk->qh_e_next = htole32(UHCI_PTR_T); 594 595 td_lst = sc->sc_last_td_p; 596 597 /* end QH which is used for looping the QHs */ 598 qh_lst->h_next = 0; 599 qh_lst->qh_h_next = htole32(UHCI_PTR_T); /* end of QH chain */ 600 qh_lst->e_next = td_lst; 601 qh_lst->qh_e_next = td_lst->td_self; 602 603 /* 604 * end TD which hangs from the last QH, to avoid a bug in the PIIX 605 * that makes it run berserk otherwise 606 */ 607 td_lst->next = 0; 608 td_lst->td_next = htole32(UHCI_PTR_T); 609 td_lst->td_status = htole32(0); /* inactive */ 610 td_lst->td_token = htole32(0); 611 td_lst->td_buffer = htole32(0); 612 } 613 if (1) { 614 struct usb_page_search buf_res; 615 uint32_t *pframes; 616 617 usbd_get_page(&sc->sc_hw.pframes_pc, 0, &buf_res); 618 619 pframes = buf_res.buffer; 620 621 622 /* 623 * Setup UHCI framelist 624 * 625 * Execution order: 626 * 627 * pframes -> full speed isochronous -> interrupt QH's -> low 628 * speed control -> full speed control -> bulk transfers 629 * 630 */ 631 632 for (x = 0; x != UHCI_FRAMELIST_COUNT; x++) { 633 pframes[x] = 634 sc->sc_isoc_p_last[x % UHCI_VFRAMELIST_COUNT]->td_self; 635 } 636 } 637 /* flush all cache into memory */ 638 639 usb_bus_mem_flush_all(&sc->sc_bus, &uhci_iterate_hw_softc); 640 641 /* set up the bus struct */ 642 sc->sc_bus.methods = &uhci_bus_methods; 643 644 USB_BUS_LOCK(&sc->sc_bus); 645 /* reset the controller */ 646 uhci_reset(sc); 647 648 /* start the controller */ 649 uhci_start(sc); 650 USB_BUS_UNLOCK(&sc->sc_bus); 651 652 /* catch lost interrupts */ 653 uhci_do_poll(&sc->sc_bus); 654 655 return (0); 656} 657 658static void 659uhci_suspend(uhci_softc_t *sc) 660{ 661#ifdef USB_DEBUG 662 if (uhcidebug > 2) { 663 uhci_dumpregs(sc); 664 } 665#endif 666 667 USB_BUS_LOCK(&sc->sc_bus); 668 669 /* stop the controller */ 670 671 uhci_reset(sc); 672 673 /* enter global suspend */ 674 675 UHCICMD(sc, UHCI_CMD_EGSM); 676 677 USB_BUS_UNLOCK(&sc->sc_bus); 678} 679 680static void 681uhci_resume(uhci_softc_t *sc) 682{ 683 USB_BUS_LOCK(&sc->sc_bus); 684 685 /* reset the controller */ 686 687 uhci_reset(sc); 688 689 /* force global resume */ 690 691 UHCICMD(sc, UHCI_CMD_FGR); 692 693 /* and start traffic again */ 694 695 uhci_start(sc); 696 697 USB_BUS_UNLOCK(&sc->sc_bus); 698 699#ifdef USB_DEBUG 700 if (uhcidebug > 2) 701 uhci_dumpregs(sc); 702#endif 703 704 /* catch lost interrupts */ 705 uhci_do_poll(&sc->sc_bus); 706} 707 708#ifdef USB_DEBUG 709static void 710uhci_dumpregs(uhci_softc_t *sc) 711{ 712 DPRINTFN(0, "%s regs: cmd=%04x, sts=%04x, intr=%04x, frnum=%04x, " 713 "flbase=%08x, sof=%04x, portsc1=%04x, portsc2=%04x\n", 714 device_get_nameunit(sc->sc_bus.bdev), 715 UREAD2(sc, UHCI_CMD), 716 UREAD2(sc, UHCI_STS), 717 UREAD2(sc, UHCI_INTR), 718 UREAD2(sc, UHCI_FRNUM), 719 UREAD4(sc, UHCI_FLBASEADDR), 720 UREAD1(sc, UHCI_SOF), 721 UREAD2(sc, UHCI_PORTSC1), 722 UREAD2(sc, UHCI_PORTSC2)); 723} 724 725static uint8_t 726uhci_dump_td(uhci_td_t *p) 727{ 728 uint32_t td_next; 729 uint32_t td_status; 730 uint32_t td_token; 731 uint8_t temp; 732 733 usb_pc_cpu_invalidate(p->page_cache); 734 735 td_next = le32toh(p->td_next); 736 td_status = le32toh(p->td_status); 737 td_token = le32toh(p->td_token); 738 739 /* 740 * Check whether the link pointer in this TD marks the link pointer 741 * as end of queue: 742 */ 743 temp = ((td_next & UHCI_PTR_T) || (td_next == 0)); 744 745 printf("TD(%p) at 0x%08x = link=0x%08x status=0x%08x " 746 "token=0x%08x buffer=0x%08x\n", 747 p, 748 le32toh(p->td_self), 749 td_next, 750 td_status, 751 td_token, 752 le32toh(p->td_buffer)); 753 754 printf("TD(%p) td_next=%s%s%s td_status=%s%s%s%s%s%s%s%s%s%s%s, errcnt=%d, actlen=%d pid=%02x," 755 "addr=%d,endpt=%d,D=%d,maxlen=%d\n", 756 p, 757 (td_next & 1) ? "-T" : "", 758 (td_next & 2) ? "-Q" : "", 759 (td_next & 4) ? "-VF" : "", 760 (td_status & UHCI_TD_BITSTUFF) ? "-BITSTUFF" : "", 761 (td_status & UHCI_TD_CRCTO) ? "-CRCTO" : "", 762 (td_status & UHCI_TD_NAK) ? "-NAK" : "", 763 (td_status & UHCI_TD_BABBLE) ? "-BABBLE" : "", 764 (td_status & UHCI_TD_DBUFFER) ? "-DBUFFER" : "", 765 (td_status & UHCI_TD_STALLED) ? "-STALLED" : "", 766 (td_status & UHCI_TD_ACTIVE) ? "-ACTIVE" : "", 767 (td_status & UHCI_TD_IOC) ? "-IOC" : "", 768 (td_status & UHCI_TD_IOS) ? "-IOS" : "", 769 (td_status & UHCI_TD_LS) ? "-LS" : "", 770 (td_status & UHCI_TD_SPD) ? "-SPD" : "", 771 UHCI_TD_GET_ERRCNT(td_status), 772 UHCI_TD_GET_ACTLEN(td_status), 773 UHCI_TD_GET_PID(td_token), 774 UHCI_TD_GET_DEVADDR(td_token), 775 UHCI_TD_GET_ENDPT(td_token), 776 UHCI_TD_GET_DT(td_token), 777 UHCI_TD_GET_MAXLEN(td_token)); 778 779 return (temp); 780} 781 782static uint8_t 783uhci_dump_qh(uhci_qh_t *sqh) 784{ 785 uint8_t temp; 786 uint32_t qh_h_next; 787 uint32_t qh_e_next; 788 789 usb_pc_cpu_invalidate(sqh->page_cache); 790 791 qh_h_next = le32toh(sqh->qh_h_next); 792 qh_e_next = le32toh(sqh->qh_e_next); 793 794 DPRINTFN(0, "QH(%p) at 0x%08x: h_next=0x%08x e_next=0x%08x\n", sqh, 795 le32toh(sqh->qh_self), qh_h_next, qh_e_next); 796 797 temp = ((((sqh->h_next != NULL) && !(qh_h_next & UHCI_PTR_T)) ? 1 : 0) | 798 (((sqh->e_next != NULL) && !(qh_e_next & UHCI_PTR_T)) ? 2 : 0)); 799 800 return (temp); 801} 802 803static void 804uhci_dump_all(uhci_softc_t *sc) 805{ 806 uhci_dumpregs(sc); 807 uhci_dump_qh(sc->sc_ls_ctl_p_last); 808 uhci_dump_qh(sc->sc_fs_ctl_p_last); 809 uhci_dump_qh(sc->sc_bulk_p_last); 810 uhci_dump_qh(sc->sc_last_qh_p); 811} 812 813static void 814uhci_dump_tds(uhci_td_t *td) 815{ 816 for (; 817 td != NULL; 818 td = td->obj_next) { 819 if (uhci_dump_td(td)) { 820 break; 821 } 822 } 823} 824 825#endif 826 827/* 828 * Let the last QH loop back to the full speed control transfer QH. 829 * This is what intel calls "bandwidth reclamation" and improves 830 * USB performance a lot for some devices. 831 * If we are already looping, just count it. 832 */ 833static void 834uhci_add_loop(uhci_softc_t *sc) 835{ 836 struct uhci_qh *qh_lst; 837 struct uhci_qh *qh_rec; 838 839#ifdef USB_DEBUG 840 if (uhcinoloop) { 841 return; 842 } 843#endif 844 if (++(sc->sc_loops) == 1) { 845 DPRINTFN(6, "add\n"); 846 847 qh_lst = sc->sc_last_qh_p; 848 qh_rec = sc->sc_reclaim_qh_p; 849 850 /* NOTE: we don't loop back the soft pointer */ 851 852 qh_lst->qh_h_next = qh_rec->qh_self; 853 usb_pc_cpu_flush(qh_lst->page_cache); 854 } 855} 856 857static void 858uhci_rem_loop(uhci_softc_t *sc) 859{ 860 struct uhci_qh *qh_lst; 861 862#ifdef USB_DEBUG 863 if (uhcinoloop) { 864 return; 865 } 866#endif 867 if (--(sc->sc_loops) == 0) { 868 DPRINTFN(6, "remove\n"); 869 870 qh_lst = sc->sc_last_qh_p; 871 qh_lst->qh_h_next = htole32(UHCI_PTR_T); 872 usb_pc_cpu_flush(qh_lst->page_cache); 873 } 874} 875 876static void 877uhci_transfer_intr_enqueue(struct usb_xfer *xfer) 878{ 879 /* check for early completion */ 880 if (uhci_check_transfer(xfer)) { 881 return; 882 } 883 /* put transfer on interrupt queue */ 884 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 885 886 /* start timeout, if any */ 887 if (xfer->timeout != 0) { 888 usbd_transfer_timeout_ms(xfer, &uhci_timeout, xfer->timeout); 889 } 890} 891 892#define UHCI_APPEND_TD(std,last) (last) = _uhci_append_td(std,last) 893static uhci_td_t * 894_uhci_append_td(uhci_td_t *std, uhci_td_t *last) 895{ 896 DPRINTFN(11, "%p to %p\n", std, last); 897 898 /* (sc->sc_bus.mtx) must be locked */ 899 900 std->next = last->next; 901 std->td_next = last->td_next; 902 903 std->prev = last; 904 905 usb_pc_cpu_flush(std->page_cache); 906 907 /* 908 * the last->next->prev is never followed: std->next->prev = std; 909 */ 910 last->next = std; 911 last->td_next = std->td_self; 912 913 usb_pc_cpu_flush(last->page_cache); 914 915 return (std); 916} 917 918#define UHCI_APPEND_QH(sqh,last) (last) = _uhci_append_qh(sqh,last) 919static uhci_qh_t * 920_uhci_append_qh(uhci_qh_t *sqh, uhci_qh_t *last) 921{ 922 DPRINTFN(11, "%p to %p\n", sqh, last); 923 924 if (sqh->h_prev != NULL) { 925 /* should not happen */ 926 DPRINTFN(0, "QH already linked!\n"); 927 return (last); 928 } 929 /* (sc->sc_bus.mtx) must be locked */ 930 931 sqh->h_next = last->h_next; 932 sqh->qh_h_next = last->qh_h_next; 933 934 sqh->h_prev = last; 935 936 usb_pc_cpu_flush(sqh->page_cache); 937 938 /* 939 * The "last->h_next->h_prev" is never followed: 940 * 941 * "sqh->h_next->h_prev" = sqh; 942 */ 943 944 last->h_next = sqh; 945 last->qh_h_next = sqh->qh_self; 946 947 usb_pc_cpu_flush(last->page_cache); 948 949 return (sqh); 950} 951 952/**/ 953 954#define UHCI_REMOVE_TD(std,last) (last) = _uhci_remove_td(std,last) 955static uhci_td_t * 956_uhci_remove_td(uhci_td_t *std, uhci_td_t *last) 957{ 958 DPRINTFN(11, "%p from %p\n", std, last); 959 960 /* (sc->sc_bus.mtx) must be locked */ 961 962 std->prev->next = std->next; 963 std->prev->td_next = std->td_next; 964 965 usb_pc_cpu_flush(std->prev->page_cache); 966 967 if (std->next) { 968 std->next->prev = std->prev; 969 usb_pc_cpu_flush(std->next->page_cache); 970 } 971 return ((last == std) ? std->prev : last); 972} 973 974#define UHCI_REMOVE_QH(sqh,last) (last) = _uhci_remove_qh(sqh,last) 975static uhci_qh_t * 976_uhci_remove_qh(uhci_qh_t *sqh, uhci_qh_t *last) 977{ 978 DPRINTFN(11, "%p from %p\n", sqh, last); 979 980 /* (sc->sc_bus.mtx) must be locked */ 981 982 /* only remove if not removed from a queue */ 983 if (sqh->h_prev) { 984 985 sqh->h_prev->h_next = sqh->h_next; 986 sqh->h_prev->qh_h_next = sqh->qh_h_next; 987 988 usb_pc_cpu_flush(sqh->h_prev->page_cache); 989 990 if (sqh->h_next) { 991 sqh->h_next->h_prev = sqh->h_prev; 992 usb_pc_cpu_flush(sqh->h_next->page_cache); 993 } 994 last = ((last == sqh) ? sqh->h_prev : last); 995 996 sqh->h_prev = 0; 997 998 usb_pc_cpu_flush(sqh->page_cache); 999 } 1000 return (last); 1001} 1002 1003static void 1004uhci_isoc_done(uhci_softc_t *sc, struct usb_xfer *xfer) 1005{ 1006 struct usb_page_search res; 1007 uint32_t nframes = xfer->nframes; 1008 uint32_t status; 1009 uint32_t offset = 0; 1010 uint32_t *plen = xfer->frlengths; 1011 uint16_t len = 0; 1012 uhci_td_t *td = xfer->td_transfer_first; 1013 uhci_td_t **pp_last = &sc->sc_isoc_p_last[xfer->qh_pos]; 1014 1015 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 1016 xfer, xfer->endpoint); 1017 1018 /* sync any DMA memory before doing fixups */ 1019 1020 usb_bdma_post_sync(xfer); 1021 1022 while (nframes--) { 1023 if (td == NULL) { 1024 panic("%s:%d: out of TD's\n", 1025 __FUNCTION__, __LINE__); 1026 } 1027 if (pp_last >= &sc->sc_isoc_p_last[UHCI_VFRAMELIST_COUNT]) { 1028 pp_last = &sc->sc_isoc_p_last[0]; 1029 } 1030#ifdef USB_DEBUG 1031 if (uhcidebug > 5) { 1032 DPRINTF("isoc TD\n"); 1033 uhci_dump_td(td); 1034 } 1035#endif 1036 usb_pc_cpu_invalidate(td->page_cache); 1037 status = le32toh(td->td_status); 1038 1039 len = UHCI_TD_GET_ACTLEN(status); 1040 1041 if (len > *plen) { 1042 len = *plen; 1043 } 1044 if (td->fix_pc) { 1045 1046 usbd_get_page(td->fix_pc, 0, &res); 1047 1048 /* copy data from fixup location to real location */ 1049 1050 usb_pc_cpu_invalidate(td->fix_pc); 1051 1052 usbd_copy_in(xfer->frbuffers, offset, 1053 res.buffer, len); 1054 } 1055 offset += *plen; 1056 1057 *plen = len; 1058 1059 /* remove TD from schedule */ 1060 UHCI_REMOVE_TD(td, *pp_last); 1061 1062 pp_last++; 1063 plen++; 1064 td = td->obj_next; 1065 } 1066 1067 xfer->aframes = xfer->nframes; 1068} 1069 1070static usb_error_t 1071uhci_non_isoc_done_sub(struct usb_xfer *xfer) 1072{ 1073 struct usb_page_search res; 1074 uhci_td_t *td; 1075 uhci_td_t *td_alt_next; 1076 uint32_t status; 1077 uint32_t token; 1078 uint16_t len; 1079 1080 td = xfer->td_transfer_cache; 1081 td_alt_next = td->alt_next; 1082 1083 if (xfer->aframes != xfer->nframes) { 1084 usbd_xfer_set_frame_len(xfer, xfer->aframes, 0); 1085 } 1086 while (1) { 1087 1088 usb_pc_cpu_invalidate(td->page_cache); 1089 status = le32toh(td->td_status); 1090 token = le32toh(td->td_token); 1091 1092 /* 1093 * Verify the status and add 1094 * up the actual length: 1095 */ 1096 1097 len = UHCI_TD_GET_ACTLEN(status); 1098 if (len > td->len) { 1099 /* should not happen */ 1100 DPRINTF("Invalid status length, " 1101 "0x%04x/0x%04x bytes\n", len, td->len); 1102 status |= UHCI_TD_STALLED; 1103 1104 } else if ((xfer->aframes != xfer->nframes) && (len > 0)) { 1105 1106 if (td->fix_pc) { 1107 1108 usbd_get_page(td->fix_pc, 0, &res); 1109 1110 /* 1111 * copy data from fixup location to real 1112 * location 1113 */ 1114 1115 usb_pc_cpu_invalidate(td->fix_pc); 1116 1117 usbd_copy_in(xfer->frbuffers + xfer->aframes, 1118 xfer->frlengths[xfer->aframes], res.buffer, len); 1119 } 1120 /* update actual length */ 1121 1122 xfer->frlengths[xfer->aframes] += len; 1123 } 1124 /* Check for last transfer */ 1125 if (((void *)td) == xfer->td_transfer_last) { 1126 td = NULL; 1127 break; 1128 } 1129 if (status & UHCI_TD_STALLED) { 1130 /* the transfer is finished */ 1131 td = NULL; 1132 break; 1133 } 1134 /* Check for short transfer */ 1135 if (len != td->len) { 1136 if (xfer->flags_int.short_frames_ok) { 1137 /* follow alt next */ 1138 td = td->alt_next; 1139 } else { 1140 /* the transfer is finished */ 1141 td = NULL; 1142 } 1143 break; 1144 } 1145 td = td->obj_next; 1146 1147 if (td->alt_next != td_alt_next) { 1148 /* this USB frame is complete */ 1149 break; 1150 } 1151 } 1152 1153 /* update transfer cache */ 1154 1155 xfer->td_transfer_cache = td; 1156 1157 /* update data toggle */ 1158 1159 xfer->endpoint->toggle_next = (token & UHCI_TD_SET_DT(1)) ? 0 : 1; 1160 1161#ifdef USB_DEBUG 1162 if (status & UHCI_TD_ERROR) { 1163 DPRINTFN(11, "error, addr=%d, endpt=0x%02x, frame=0x%02x " 1164 "status=%s%s%s%s%s%s%s%s%s%s%s\n", 1165 xfer->address, xfer->endpointno, xfer->aframes, 1166 (status & UHCI_TD_BITSTUFF) ? "[BITSTUFF]" : "", 1167 (status & UHCI_TD_CRCTO) ? "[CRCTO]" : "", 1168 (status & UHCI_TD_NAK) ? "[NAK]" : "", 1169 (status & UHCI_TD_BABBLE) ? "[BABBLE]" : "", 1170 (status & UHCI_TD_DBUFFER) ? "[DBUFFER]" : "", 1171 (status & UHCI_TD_STALLED) ? "[STALLED]" : "", 1172 (status & UHCI_TD_ACTIVE) ? "[ACTIVE]" : "[NOT_ACTIVE]", 1173 (status & UHCI_TD_IOC) ? "[IOC]" : "", 1174 (status & UHCI_TD_IOS) ? "[IOS]" : "", 1175 (status & UHCI_TD_LS) ? "[LS]" : "", 1176 (status & UHCI_TD_SPD) ? "[SPD]" : ""); 1177 } 1178#endif 1179 if (status & UHCI_TD_STALLED) { 1180 /* try to separate I/O errors from STALL */ 1181 if (UHCI_TD_GET_ERRCNT(status) == 0) 1182 return (USB_ERR_IOERROR); 1183 return (USB_ERR_STALLED); 1184 } 1185 return (USB_ERR_NORMAL_COMPLETION); 1186} 1187 1188static void 1189uhci_non_isoc_done(struct usb_xfer *xfer) 1190{ 1191 usb_error_t err = 0; 1192 1193 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 1194 xfer, xfer->endpoint); 1195 1196#ifdef USB_DEBUG 1197 if (uhcidebug > 10) { 1198 uhci_dump_tds(xfer->td_transfer_first); 1199 } 1200#endif 1201 1202 /* sync any DMA memory before doing fixups */ 1203 1204 usb_bdma_post_sync(xfer); 1205 1206 /* reset scanner */ 1207 1208 xfer->td_transfer_cache = xfer->td_transfer_first; 1209 1210 if (xfer->flags_int.control_xfr) { 1211 if (xfer->flags_int.control_hdr) { 1212 1213 err = uhci_non_isoc_done_sub(xfer); 1214 } 1215 xfer->aframes = 1; 1216 1217 if (xfer->td_transfer_cache == NULL) { 1218 goto done; 1219 } 1220 } 1221 while (xfer->aframes != xfer->nframes) { 1222 1223 err = uhci_non_isoc_done_sub(xfer); 1224 xfer->aframes++; 1225 1226 if (xfer->td_transfer_cache == NULL) { 1227 goto done; 1228 } 1229 } 1230 1231 if (xfer->flags_int.control_xfr && 1232 !xfer->flags_int.control_act) { 1233 1234 err = uhci_non_isoc_done_sub(xfer); 1235 } 1236done: 1237 uhci_device_done(xfer, err); 1238} 1239 1240/*------------------------------------------------------------------------* 1241 * uhci_check_transfer_sub 1242 * 1243 * The main purpose of this function is to update the data-toggle 1244 * in case it is wrong. 1245 *------------------------------------------------------------------------*/ 1246static void 1247uhci_check_transfer_sub(struct usb_xfer *xfer) 1248{ 1249 uhci_qh_t *qh; 1250 uhci_td_t *td; 1251 uhci_td_t *td_alt_next; 1252 1253 uint32_t td_token; 1254 uint32_t td_self; 1255 1256 td = xfer->td_transfer_cache; 1257 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1258 1259 td_token = td->obj_next->td_token; 1260 td = td->alt_next; 1261 xfer->td_transfer_cache = td; 1262 td_self = td->td_self; 1263 td_alt_next = td->alt_next; 1264 1265 if (xfer->flags_int.control_xfr) 1266 goto skip; /* don't touch the DT value! */ 1267 1268 if (!((td->td_token ^ td_token) & htole32(UHCI_TD_SET_DT(1)))) 1269 goto skip; /* data toggle has correct value */ 1270 1271 /* 1272 * The data toggle is wrong and we need to toggle it ! 1273 */ 1274 while (1) { 1275 1276 td->td_token ^= htole32(UHCI_TD_SET_DT(1)); 1277 usb_pc_cpu_flush(td->page_cache); 1278 1279 if (td == xfer->td_transfer_last) { 1280 /* last transfer */ 1281 break; 1282 } 1283 td = td->obj_next; 1284 1285 if (td->alt_next != td_alt_next) { 1286 /* next frame */ 1287 break; 1288 } 1289 } 1290skip: 1291 1292 /* update the QH */ 1293 qh->qh_e_next = td_self; 1294 usb_pc_cpu_flush(qh->page_cache); 1295 1296 DPRINTFN(13, "xfer=%p following alt next\n", xfer); 1297} 1298 1299/*------------------------------------------------------------------------* 1300 * uhci_check_transfer 1301 * 1302 * Return values: 1303 * 0: USB transfer is not finished 1304 * Else: USB transfer is finished 1305 *------------------------------------------------------------------------*/ 1306static uint8_t 1307uhci_check_transfer(struct usb_xfer *xfer) 1308{ 1309 uint32_t status; 1310 uint32_t token; 1311 uhci_td_t *td; 1312 1313 DPRINTFN(16, "xfer=%p checking transfer\n", xfer); 1314 1315 if (xfer->endpoint->methods == &uhci_device_isoc_methods) { 1316 /* isochronous transfer */ 1317 1318 td = xfer->td_transfer_last; 1319 1320 usb_pc_cpu_invalidate(td->page_cache); 1321 status = le32toh(td->td_status); 1322 1323 /* check also if the first is complete */ 1324 1325 td = xfer->td_transfer_first; 1326 1327 usb_pc_cpu_invalidate(td->page_cache); 1328 status |= le32toh(td->td_status); 1329 1330 if (!(status & UHCI_TD_ACTIVE)) { 1331 uhci_device_done(xfer, USB_ERR_NORMAL_COMPLETION); 1332 goto transferred; 1333 } 1334 } else { 1335 /* non-isochronous transfer */ 1336 1337 /* 1338 * check whether there is an error somewhere 1339 * in the middle, or whether there was a short 1340 * packet (SPD and not ACTIVE) 1341 */ 1342 td = xfer->td_transfer_cache; 1343 1344 while (1) { 1345 usb_pc_cpu_invalidate(td->page_cache); 1346 status = le32toh(td->td_status); 1347 token = le32toh(td->td_token); 1348 1349 /* 1350 * if there is an active TD the transfer isn't done 1351 */ 1352 if (status & UHCI_TD_ACTIVE) { 1353 /* update cache */ 1354 xfer->td_transfer_cache = td; 1355 goto done; 1356 } 1357 /* 1358 * last transfer descriptor makes the transfer done 1359 */ 1360 if (((void *)td) == xfer->td_transfer_last) { 1361 break; 1362 } 1363 /* 1364 * any kind of error makes the transfer done 1365 */ 1366 if (status & UHCI_TD_STALLED) { 1367 break; 1368 } 1369 /* 1370 * check if we reached the last packet 1371 * or if there is a short packet: 1372 */ 1373 if ((td->td_next == htole32(UHCI_PTR_T)) || 1374 (UHCI_TD_GET_ACTLEN(status) < td->len)) { 1375 1376 if (xfer->flags_int.short_frames_ok) { 1377 /* follow alt next */ 1378 if (td->alt_next) { 1379 /* update cache */ 1380 xfer->td_transfer_cache = td; 1381 uhci_check_transfer_sub(xfer); 1382 goto done; 1383 } 1384 } 1385 /* transfer is done */ 1386 break; 1387 } 1388 td = td->obj_next; 1389 } 1390 uhci_non_isoc_done(xfer); 1391 goto transferred; 1392 } 1393 1394done: 1395 DPRINTFN(13, "xfer=%p is still active\n", xfer); 1396 return (0); 1397 1398transferred: 1399 return (1); 1400} 1401 1402static void 1403uhci_interrupt_poll(uhci_softc_t *sc) 1404{ 1405 struct usb_xfer *xfer; 1406 1407repeat: 1408 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 1409 /* 1410 * check if transfer is transferred 1411 */ 1412 if (uhci_check_transfer(xfer)) { 1413 /* queue has been modified */ 1414 goto repeat; 1415 } 1416 } 1417} 1418 1419/*------------------------------------------------------------------------* 1420 * uhci_interrupt - UHCI interrupt handler 1421 * 1422 * NOTE: Do not access "sc->sc_bus.bdev" inside the interrupt handler, 1423 * hence the interrupt handler will be setup before "sc->sc_bus.bdev" 1424 * is present ! 1425 *------------------------------------------------------------------------*/ 1426void 1427uhci_interrupt(uhci_softc_t *sc) 1428{ 1429 uint32_t status; 1430 1431 USB_BUS_LOCK(&sc->sc_bus); 1432 1433 DPRINTFN(16, "real interrupt\n"); 1434 1435#ifdef USB_DEBUG 1436 if (uhcidebug > 15) { 1437 uhci_dumpregs(sc); 1438 } 1439#endif 1440 status = UREAD2(sc, UHCI_STS) & UHCI_STS_ALLINTRS; 1441 if (status == 0) { 1442 /* the interrupt was not for us */ 1443 goto done; 1444 } 1445 if (status & (UHCI_STS_RD | UHCI_STS_HSE | 1446 UHCI_STS_HCPE | UHCI_STS_HCH)) { 1447 1448 if (status & UHCI_STS_RD) { 1449#ifdef USB_DEBUG 1450 printf("%s: resume detect\n", 1451 __FUNCTION__); 1452#endif 1453 } 1454 if (status & UHCI_STS_HSE) { 1455 printf("%s: host system error\n", 1456 __FUNCTION__); 1457 } 1458 if (status & UHCI_STS_HCPE) { 1459 printf("%s: host controller process error\n", 1460 __FUNCTION__); 1461 } 1462 if (status & UHCI_STS_HCH) { 1463 /* no acknowledge needed */ 1464 DPRINTF("%s: host controller halted\n", 1465 __FUNCTION__); 1466#ifdef USB_DEBUG 1467 if (uhcidebug > 0) { 1468 uhci_dump_all(sc); 1469 } 1470#endif 1471 } 1472 } 1473 /* get acknowledge bits */ 1474 status &= (UHCI_STS_USBINT | 1475 UHCI_STS_USBEI | 1476 UHCI_STS_RD | 1477 UHCI_STS_HSE | 1478 UHCI_STS_HCPE); 1479 1480 if (status == 0) { 1481 /* nothing to acknowledge */ 1482 goto done; 1483 } 1484 /* acknowledge interrupts */ 1485 UWRITE2(sc, UHCI_STS, status); 1486 1487 /* poll all the USB transfers */ 1488 uhci_interrupt_poll(sc); 1489 1490done: 1491 USB_BUS_UNLOCK(&sc->sc_bus); 1492} 1493 1494/* 1495 * called when a request does not complete 1496 */ 1497static void 1498uhci_timeout(void *arg) 1499{ 1500 struct usb_xfer *xfer = arg; 1501 1502 DPRINTF("xfer=%p\n", xfer); 1503 1504 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 1505 1506 /* transfer is transferred */ 1507 uhci_device_done(xfer, USB_ERR_TIMEOUT); 1508} 1509 1510static void 1511uhci_do_poll(struct usb_bus *bus) 1512{ 1513 struct uhci_softc *sc = UHCI_BUS2SC(bus); 1514 1515 USB_BUS_LOCK(&sc->sc_bus); 1516 uhci_interrupt_poll(sc); 1517 USB_BUS_UNLOCK(&sc->sc_bus); 1518} 1519 1520static void 1521uhci_setup_standard_chain_sub(struct uhci_std_temp *temp) 1522{ 1523 uhci_td_t *td; 1524 uhci_td_t *td_next; 1525 uhci_td_t *td_alt_next; 1526 uint32_t average; 1527 uint32_t len_old; 1528 uint8_t shortpkt_old; 1529 uint8_t precompute; 1530 1531 td_alt_next = NULL; 1532 shortpkt_old = temp->shortpkt; 1533 len_old = temp->len; 1534 precompute = 1; 1535 1536 /* software is used to detect short incoming transfers */ 1537 1538 if ((temp->td_token & htole32(UHCI_TD_PID)) == htole32(UHCI_TD_PID_IN)) { 1539 temp->td_status |= htole32(UHCI_TD_SPD); 1540 } else { 1541 temp->td_status &= ~htole32(UHCI_TD_SPD); 1542 } 1543 1544 temp->ml.buf_offset = 0; 1545 1546restart: 1547 1548 temp->td_token &= ~htole32(UHCI_TD_SET_MAXLEN(0)); 1549 temp->td_token |= htole32(UHCI_TD_SET_MAXLEN(temp->average)); 1550 1551 td = temp->td; 1552 td_next = temp->td_next; 1553 1554 while (1) { 1555 1556 if (temp->len == 0) { 1557 1558 if (temp->shortpkt) { 1559 break; 1560 } 1561 /* send a Zero Length Packet, ZLP, last */ 1562 1563 temp->shortpkt = 1; 1564 temp->td_token |= htole32(UHCI_TD_SET_MAXLEN(0)); 1565 average = 0; 1566 1567 } else { 1568 1569 average = temp->average; 1570 1571 if (temp->len < average) { 1572 temp->shortpkt = 1; 1573 temp->td_token &= ~htole32(UHCI_TD_SET_MAXLEN(0)); 1574 temp->td_token |= htole32(UHCI_TD_SET_MAXLEN(temp->len)); 1575 average = temp->len; 1576 } 1577 } 1578 1579 if (td_next == NULL) { 1580 panic("%s: out of UHCI transfer descriptors!", __FUNCTION__); 1581 } 1582 /* get next TD */ 1583 1584 td = td_next; 1585 td_next = td->obj_next; 1586 1587 /* check if we are pre-computing */ 1588 1589 if (precompute) { 1590 1591 /* update remaining length */ 1592 1593 temp->len -= average; 1594 1595 continue; 1596 } 1597 /* fill out current TD */ 1598 1599 td->td_status = temp->td_status; 1600 td->td_token = temp->td_token; 1601 1602 /* update data toggle */ 1603 1604 temp->td_token ^= htole32(UHCI_TD_SET_DT(1)); 1605 1606 if (average == 0) { 1607 1608 td->len = 0; 1609 td->td_buffer = 0; 1610 td->fix_pc = NULL; 1611 1612 } else { 1613 1614 /* update remaining length */ 1615 1616 temp->len -= average; 1617 1618 td->len = average; 1619 1620 /* fill out buffer pointer and do fixup, if any */ 1621 1622 uhci_mem_layout_fixup(&temp->ml, td); 1623 } 1624 1625 td->alt_next = td_alt_next; 1626 1627 if ((td_next == td_alt_next) && temp->setup_alt_next) { 1628 /* we need to receive these frames one by one ! */ 1629 td->td_status |= htole32(UHCI_TD_IOC); 1630 td->td_next = htole32(UHCI_PTR_T); 1631 } else { 1632 if (td_next) { 1633 /* link the current TD with the next one */ 1634 td->td_next = td_next->td_self; 1635 } 1636 } 1637 1638 usb_pc_cpu_flush(td->page_cache); 1639 } 1640 1641 if (precompute) { 1642 precompute = 0; 1643 1644 /* setup alt next pointer, if any */ 1645 if (temp->last_frame) { 1646 td_alt_next = NULL; 1647 } else { 1648 /* we use this field internally */ 1649 td_alt_next = td_next; 1650 } 1651 1652 /* restore */ 1653 temp->shortpkt = shortpkt_old; 1654 temp->len = len_old; 1655 goto restart; 1656 } 1657 temp->td = td; 1658 temp->td_next = td_next; 1659} 1660 1661static uhci_td_t * 1662uhci_setup_standard_chain(struct usb_xfer *xfer) 1663{ 1664 struct uhci_std_temp temp; 1665 uhci_td_t *td; 1666 uint32_t x; 1667 1668 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n", 1669 xfer->address, UE_GET_ADDR(xfer->endpointno), 1670 xfer->sumlen, usbd_get_speed(xfer->xroot->udev)); 1671 1672 temp.average = xfer->max_frame_size; 1673 temp.max_frame_size = xfer->max_frame_size; 1674 1675 /* toggle the DMA set we are using */ 1676 xfer->flags_int.curr_dma_set ^= 1; 1677 1678 /* get next DMA set */ 1679 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 1680 xfer->td_transfer_first = td; 1681 xfer->td_transfer_cache = td; 1682 1683 temp.td = NULL; 1684 temp.td_next = td; 1685 temp.last_frame = 0; 1686 temp.setup_alt_next = xfer->flags_int.short_frames_ok; 1687 1688 uhci_mem_layout_init(&temp.ml, xfer); 1689 1690 temp.td_status = 1691 htole32(UHCI_TD_ZERO_ACTLEN(UHCI_TD_SET_ERRCNT(3) | 1692 UHCI_TD_ACTIVE)); 1693 1694 if (xfer->xroot->udev->speed == USB_SPEED_LOW) { 1695 temp.td_status |= htole32(UHCI_TD_LS); 1696 } 1697 temp.td_token = 1698 htole32(UHCI_TD_SET_ENDPT(xfer->endpointno) | 1699 UHCI_TD_SET_DEVADDR(xfer->address)); 1700 1701 if (xfer->endpoint->toggle_next) { 1702 /* DATA1 is next */ 1703 temp.td_token |= htole32(UHCI_TD_SET_DT(1)); 1704 } 1705 /* check if we should prepend a setup message */ 1706 1707 if (xfer->flags_int.control_xfr) { 1708 1709 if (xfer->flags_int.control_hdr) { 1710 1711 temp.td_token &= htole32(UHCI_TD_SET_DEVADDR(0x7F) | 1712 UHCI_TD_SET_ENDPT(0xF)); 1713 temp.td_token |= htole32(UHCI_TD_PID_SETUP | 1714 UHCI_TD_SET_DT(0)); 1715 1716 temp.len = xfer->frlengths[0]; 1717 temp.ml.buf_pc = xfer->frbuffers + 0; 1718 temp.shortpkt = temp.len ? 1 : 0; 1719 /* check for last frame */ 1720 if (xfer->nframes == 1) { 1721 /* no STATUS stage yet, SETUP is last */ 1722 if (xfer->flags_int.control_act) { 1723 temp.last_frame = 1; 1724 temp.setup_alt_next = 0; 1725 } 1726 } 1727 uhci_setup_standard_chain_sub(&temp); 1728 } 1729 x = 1; 1730 } else { 1731 x = 0; 1732 } 1733 1734 while (x != xfer->nframes) { 1735 1736 /* DATA0 / DATA1 message */ 1737 1738 temp.len = xfer->frlengths[x]; 1739 temp.ml.buf_pc = xfer->frbuffers + x; 1740 1741 x++; 1742 1743 if (x == xfer->nframes) { 1744 if (xfer->flags_int.control_xfr) { 1745 /* no STATUS stage yet, DATA is last */ 1746 if (xfer->flags_int.control_act) { 1747 temp.last_frame = 1; 1748 temp.setup_alt_next = 0; 1749 } 1750 } else { 1751 temp.last_frame = 1; 1752 temp.setup_alt_next = 0; 1753 } 1754 } 1755 /* 1756 * Keep previous data toggle, 1757 * device address and endpoint number: 1758 */ 1759 1760 temp.td_token &= htole32(UHCI_TD_SET_DEVADDR(0x7F) | 1761 UHCI_TD_SET_ENDPT(0xF) | 1762 UHCI_TD_SET_DT(1)); 1763 1764 if (temp.len == 0) { 1765 1766 /* make sure that we send an USB packet */ 1767 1768 temp.shortpkt = 0; 1769 1770 } else { 1771 1772 /* regular data transfer */ 1773 1774 temp.shortpkt = (xfer->flags.force_short_xfer) ? 0 : 1; 1775 } 1776 1777 /* set endpoint direction */ 1778 1779 temp.td_token |= 1780 (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) ? 1781 htole32(UHCI_TD_PID_IN) : 1782 htole32(UHCI_TD_PID_OUT); 1783 1784 uhci_setup_standard_chain_sub(&temp); 1785 } 1786 1787 /* check if we should append a status stage */ 1788 1789 if (xfer->flags_int.control_xfr && 1790 !xfer->flags_int.control_act) { 1791 1792 /* 1793 * send a DATA1 message and reverse the current endpoint 1794 * direction 1795 */ 1796 1797 temp.td_token &= htole32(UHCI_TD_SET_DEVADDR(0x7F) | 1798 UHCI_TD_SET_ENDPT(0xF) | 1799 UHCI_TD_SET_DT(1)); 1800 temp.td_token |= 1801 (UE_GET_DIR(xfer->endpointno) == UE_DIR_OUT) ? 1802 htole32(UHCI_TD_PID_IN | UHCI_TD_SET_DT(1)) : 1803 htole32(UHCI_TD_PID_OUT | UHCI_TD_SET_DT(1)); 1804 1805 temp.len = 0; 1806 temp.ml.buf_pc = NULL; 1807 temp.shortpkt = 0; 1808 temp.last_frame = 1; 1809 temp.setup_alt_next = 0; 1810 1811 uhci_setup_standard_chain_sub(&temp); 1812 } 1813 td = temp.td; 1814 1815 /* Ensure that last TD is terminating: */ 1816 td->td_next = htole32(UHCI_PTR_T); 1817 1818 /* set interrupt bit */ 1819 1820 td->td_status |= htole32(UHCI_TD_IOC); 1821 1822 usb_pc_cpu_flush(td->page_cache); 1823 1824 /* must have at least one frame! */ 1825 1826 xfer->td_transfer_last = td; 1827 1828#ifdef USB_DEBUG 1829 if (uhcidebug > 8) { 1830 DPRINTF("nexttog=%d; data before transfer:\n", 1831 xfer->endpoint->toggle_next); 1832 uhci_dump_tds(xfer->td_transfer_first); 1833 } 1834#endif 1835 return (xfer->td_transfer_first); 1836} 1837 1838/* NOTE: "done" can be run two times in a row, 1839 * from close and from interrupt 1840 */ 1841 1842static void 1843uhci_device_done(struct usb_xfer *xfer, usb_error_t error) 1844{ 1845 struct usb_pipe_methods *methods = xfer->endpoint->methods; 1846 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus); 1847 uhci_qh_t *qh; 1848 1849 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1850 1851 DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n", 1852 xfer, xfer->endpoint, error); 1853 1854 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1855 if (qh) { 1856 usb_pc_cpu_invalidate(qh->page_cache); 1857 } 1858 if (xfer->flags_int.bandwidth_reclaimed) { 1859 xfer->flags_int.bandwidth_reclaimed = 0; 1860 uhci_rem_loop(sc); 1861 } 1862 if (methods == &uhci_device_bulk_methods) { 1863 UHCI_REMOVE_QH(qh, sc->sc_bulk_p_last); 1864 } 1865 if (methods == &uhci_device_ctrl_methods) { 1866 if (xfer->xroot->udev->speed == USB_SPEED_LOW) { 1867 UHCI_REMOVE_QH(qh, sc->sc_ls_ctl_p_last); 1868 } else { 1869 UHCI_REMOVE_QH(qh, sc->sc_fs_ctl_p_last); 1870 } 1871 } 1872 if (methods == &uhci_device_intr_methods) { 1873 UHCI_REMOVE_QH(qh, sc->sc_intr_p_last[xfer->qh_pos]); 1874 } 1875 /* 1876 * Only finish isochronous transfers once 1877 * which will update "xfer->frlengths". 1878 */ 1879 if (xfer->td_transfer_first && 1880 xfer->td_transfer_last) { 1881 if (methods == &uhci_device_isoc_methods) { 1882 uhci_isoc_done(sc, xfer); 1883 } 1884 xfer->td_transfer_first = NULL; 1885 xfer->td_transfer_last = NULL; 1886 } 1887 /* dequeue transfer and start next transfer */ 1888 usbd_transfer_done(xfer, error); 1889} 1890 1891/*------------------------------------------------------------------------* 1892 * uhci bulk support 1893 *------------------------------------------------------------------------*/ 1894static void 1895uhci_device_bulk_open(struct usb_xfer *xfer) 1896{ 1897 return; 1898} 1899 1900static void 1901uhci_device_bulk_close(struct usb_xfer *xfer) 1902{ 1903 uhci_device_done(xfer, USB_ERR_CANCELLED); 1904} 1905 1906static void 1907uhci_device_bulk_enter(struct usb_xfer *xfer) 1908{ 1909 return; 1910} 1911 1912static void 1913uhci_device_bulk_start(struct usb_xfer *xfer) 1914{ 1915 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus); 1916 uhci_td_t *td; 1917 uhci_qh_t *qh; 1918 1919 /* setup TD's */ 1920 td = uhci_setup_standard_chain(xfer); 1921 1922 /* setup QH */ 1923 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1924 1925 qh->e_next = td; 1926 qh->qh_e_next = td->td_self; 1927 1928 if (xfer->xroot->udev->flags.self_suspended == 0) { 1929 UHCI_APPEND_QH(qh, sc->sc_bulk_p_last); 1930 uhci_add_loop(sc); 1931 xfer->flags_int.bandwidth_reclaimed = 1; 1932 } else { 1933 usb_pc_cpu_flush(qh->page_cache); 1934 } 1935 1936 /* put transfer on interrupt queue */ 1937 uhci_transfer_intr_enqueue(xfer); 1938} 1939 1940struct usb_pipe_methods uhci_device_bulk_methods = 1941{ 1942 .open = uhci_device_bulk_open, 1943 .close = uhci_device_bulk_close, 1944 .enter = uhci_device_bulk_enter, 1945 .start = uhci_device_bulk_start, 1946}; 1947 1948/*------------------------------------------------------------------------* 1949 * uhci control support 1950 *------------------------------------------------------------------------*/ 1951static void 1952uhci_device_ctrl_open(struct usb_xfer *xfer) 1953{ 1954 return; 1955} 1956 1957static void 1958uhci_device_ctrl_close(struct usb_xfer *xfer) 1959{ 1960 uhci_device_done(xfer, USB_ERR_CANCELLED); 1961} 1962 1963static void 1964uhci_device_ctrl_enter(struct usb_xfer *xfer) 1965{ 1966 return; 1967} 1968 1969static void 1970uhci_device_ctrl_start(struct usb_xfer *xfer) 1971{ 1972 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus); 1973 uhci_qh_t *qh; 1974 uhci_td_t *td; 1975 1976 /* setup TD's */ 1977 td = uhci_setup_standard_chain(xfer); 1978 1979 /* setup QH */ 1980 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1981 1982 qh->e_next = td; 1983 qh->qh_e_next = td->td_self; 1984 1985 /* 1986 * NOTE: some devices choke on bandwidth- reclamation for control 1987 * transfers 1988 */ 1989 if (xfer->xroot->udev->flags.self_suspended == 0) { 1990 if (xfer->xroot->udev->speed == USB_SPEED_LOW) { 1991 UHCI_APPEND_QH(qh, sc->sc_ls_ctl_p_last); 1992 } else { 1993 UHCI_APPEND_QH(qh, sc->sc_fs_ctl_p_last); 1994 } 1995 } else { 1996 usb_pc_cpu_flush(qh->page_cache); 1997 } 1998 /* put transfer on interrupt queue */ 1999 uhci_transfer_intr_enqueue(xfer); 2000} 2001 2002struct usb_pipe_methods uhci_device_ctrl_methods = 2003{ 2004 .open = uhci_device_ctrl_open, 2005 .close = uhci_device_ctrl_close, 2006 .enter = uhci_device_ctrl_enter, 2007 .start = uhci_device_ctrl_start, 2008}; 2009 2010/*------------------------------------------------------------------------* 2011 * uhci interrupt support 2012 *------------------------------------------------------------------------*/ 2013static void 2014uhci_device_intr_open(struct usb_xfer *xfer) 2015{ 2016 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus); 2017 uint16_t best; 2018 uint16_t bit; 2019 uint16_t x; 2020 2021 best = 0; 2022 bit = UHCI_IFRAMELIST_COUNT / 2; 2023 while (bit) { 2024 if (xfer->interval >= bit) { 2025 x = bit; 2026 best = bit; 2027 while (x & bit) { 2028 if (sc->sc_intr_stat[x] < 2029 sc->sc_intr_stat[best]) { 2030 best = x; 2031 } 2032 x++; 2033 } 2034 break; 2035 } 2036 bit >>= 1; 2037 } 2038 2039 sc->sc_intr_stat[best]++; 2040 xfer->qh_pos = best; 2041 2042 DPRINTFN(3, "best=%d interval=%d\n", 2043 best, xfer->interval); 2044} 2045 2046static void 2047uhci_device_intr_close(struct usb_xfer *xfer) 2048{ 2049 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus); 2050 2051 sc->sc_intr_stat[xfer->qh_pos]--; 2052 2053 uhci_device_done(xfer, USB_ERR_CANCELLED); 2054} 2055 2056static void 2057uhci_device_intr_enter(struct usb_xfer *xfer) 2058{ 2059 return; 2060} 2061 2062static void 2063uhci_device_intr_start(struct usb_xfer *xfer) 2064{ 2065 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus); 2066 uhci_qh_t *qh; 2067 uhci_td_t *td; 2068 2069 /* setup TD's */ 2070 td = uhci_setup_standard_chain(xfer); 2071 2072 /* setup QH */ 2073 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 2074 2075 qh->e_next = td; 2076 qh->qh_e_next = td->td_self; 2077 2078 if (xfer->xroot->udev->flags.self_suspended == 0) { 2079 /* enter QHs into the controller data structures */ 2080 UHCI_APPEND_QH(qh, sc->sc_intr_p_last[xfer->qh_pos]); 2081 } else { 2082 usb_pc_cpu_flush(qh->page_cache); 2083 } 2084 2085 /* put transfer on interrupt queue */ 2086 uhci_transfer_intr_enqueue(xfer); 2087} 2088 2089struct usb_pipe_methods uhci_device_intr_methods = 2090{ 2091 .open = uhci_device_intr_open, 2092 .close = uhci_device_intr_close, 2093 .enter = uhci_device_intr_enter, 2094 .start = uhci_device_intr_start, 2095}; 2096 2097/*------------------------------------------------------------------------* 2098 * uhci isochronous support 2099 *------------------------------------------------------------------------*/ 2100static void 2101uhci_device_isoc_open(struct usb_xfer *xfer) 2102{ 2103 uhci_td_t *td; 2104 uint32_t td_token; 2105 uint8_t ds; 2106 2107 td_token = 2108 (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) ? 2109 UHCI_TD_IN(0, xfer->endpointno, xfer->address, 0) : 2110 UHCI_TD_OUT(0, xfer->endpointno, xfer->address, 0); 2111 2112 td_token = htole32(td_token); 2113 2114 /* initialize all TD's */ 2115 2116 for (ds = 0; ds != 2; ds++) { 2117 2118 for (td = xfer->td_start[ds]; td; td = td->obj_next) { 2119 2120 /* mark TD as inactive */ 2121 td->td_status = htole32(UHCI_TD_IOS); 2122 td->td_token = td_token; 2123 2124 usb_pc_cpu_flush(td->page_cache); 2125 } 2126 } 2127} 2128 2129static void 2130uhci_device_isoc_close(struct usb_xfer *xfer) 2131{ 2132 uhci_device_done(xfer, USB_ERR_CANCELLED); 2133} 2134 2135static void 2136uhci_device_isoc_enter(struct usb_xfer *xfer) 2137{ 2138 struct uhci_mem_layout ml; 2139 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus); 2140 uint32_t nframes; 2141 uint32_t temp; 2142 uint32_t *plen; 2143 2144#ifdef USB_DEBUG 2145 uint8_t once = 1; 2146 2147#endif 2148 uhci_td_t *td; 2149 uhci_td_t *td_last = NULL; 2150 uhci_td_t **pp_last; 2151 2152 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n", 2153 xfer, xfer->endpoint->isoc_next, xfer->nframes); 2154 2155 nframes = UREAD2(sc, UHCI_FRNUM); 2156 2157 temp = (nframes - xfer->endpoint->isoc_next) & 2158 (UHCI_VFRAMELIST_COUNT - 1); 2159 2160 if ((xfer->endpoint->is_synced == 0) || 2161 (temp < xfer->nframes)) { 2162 /* 2163 * If there is data underflow or the pipe queue is empty we 2164 * schedule the transfer a few frames ahead of the current 2165 * frame position. Else two isochronous transfers might 2166 * overlap. 2167 */ 2168 xfer->endpoint->isoc_next = (nframes + 3) & (UHCI_VFRAMELIST_COUNT - 1); 2169 xfer->endpoint->is_synced = 1; 2170 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next); 2171 } 2172 /* 2173 * compute how many milliseconds the insertion is ahead of the 2174 * current frame position: 2175 */ 2176 temp = (xfer->endpoint->isoc_next - nframes) & 2177 (UHCI_VFRAMELIST_COUNT - 1); 2178 2179 /* 2180 * pre-compute when the isochronous transfer will be finished: 2181 */ 2182 xfer->isoc_time_complete = 2183 usb_isoc_time_expand(&sc->sc_bus, nframes) + temp + 2184 xfer->nframes; 2185 2186 /* get the real number of frames */ 2187 2188 nframes = xfer->nframes; 2189 2190 uhci_mem_layout_init(&ml, xfer); 2191 2192 plen = xfer->frlengths; 2193 2194 /* toggle the DMA set we are using */ 2195 xfer->flags_int.curr_dma_set ^= 1; 2196 2197 /* get next DMA set */ 2198 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 2199 xfer->td_transfer_first = td; 2200 2201 pp_last = &sc->sc_isoc_p_last[xfer->endpoint->isoc_next]; 2202 2203 /* store starting position */ 2204 2205 xfer->qh_pos = xfer->endpoint->isoc_next; 2206 2207 while (nframes--) { 2208 if (td == NULL) { 2209 panic("%s:%d: out of TD's\n", 2210 __FUNCTION__, __LINE__); 2211 } 2212 if (pp_last >= &sc->sc_isoc_p_last[UHCI_VFRAMELIST_COUNT]) { 2213 pp_last = &sc->sc_isoc_p_last[0]; 2214 } 2215 if (*plen > xfer->max_frame_size) { 2216#ifdef USB_DEBUG 2217 if (once) { 2218 once = 0; 2219 printf("%s: frame length(%d) exceeds %d " 2220 "bytes (frame truncated)\n", 2221 __FUNCTION__, *plen, 2222 xfer->max_frame_size); 2223 } 2224#endif 2225 *plen = xfer->max_frame_size; 2226 } 2227 /* reuse td_token from last transfer */ 2228 2229 td->td_token &= htole32(~UHCI_TD_MAXLEN_MASK); 2230 td->td_token |= htole32(UHCI_TD_SET_MAXLEN(*plen)); 2231 2232 td->len = *plen; 2233 2234 if (td->len == 0) { 2235 /* 2236 * Do not call "uhci_mem_layout_fixup()" when the 2237 * length is zero! 2238 */ 2239 td->td_buffer = 0; 2240 td->fix_pc = NULL; 2241 2242 } else { 2243 2244 /* fill out buffer pointer and do fixup, if any */ 2245 2246 uhci_mem_layout_fixup(&ml, td); 2247 2248 } 2249 2250 /* update status */ 2251 if (nframes == 0) { 2252 td->td_status = htole32 2253 (UHCI_TD_ZERO_ACTLEN 2254 (UHCI_TD_SET_ERRCNT(0) | 2255 UHCI_TD_ACTIVE | 2256 UHCI_TD_IOS | 2257 UHCI_TD_IOC)); 2258 } else { 2259 td->td_status = htole32 2260 (UHCI_TD_ZERO_ACTLEN 2261 (UHCI_TD_SET_ERRCNT(0) | 2262 UHCI_TD_ACTIVE | 2263 UHCI_TD_IOS)); 2264 } 2265 2266 usb_pc_cpu_flush(td->page_cache); 2267 2268#ifdef USB_DEBUG 2269 if (uhcidebug > 5) { 2270 DPRINTF("TD %d\n", nframes); 2271 uhci_dump_td(td); 2272 } 2273#endif 2274 /* insert TD into schedule */ 2275 UHCI_APPEND_TD(td, *pp_last); 2276 pp_last++; 2277 2278 plen++; 2279 td_last = td; 2280 td = td->obj_next; 2281 } 2282 2283 xfer->td_transfer_last = td_last; 2284 2285 /* update isoc_next */ 2286 xfer->endpoint->isoc_next = (pp_last - &sc->sc_isoc_p_last[0]) & 2287 (UHCI_VFRAMELIST_COUNT - 1); 2288} 2289 2290static void 2291uhci_device_isoc_start(struct usb_xfer *xfer) 2292{ 2293 /* put transfer on interrupt queue */ 2294 uhci_transfer_intr_enqueue(xfer); 2295} 2296 2297struct usb_pipe_methods uhci_device_isoc_methods = 2298{ 2299 .open = uhci_device_isoc_open, 2300 .close = uhci_device_isoc_close, 2301 .enter = uhci_device_isoc_enter, 2302 .start = uhci_device_isoc_start, 2303}; 2304 2305/*------------------------------------------------------------------------* 2306 * uhci root control support 2307 *------------------------------------------------------------------------* 2308 * Simulate a hardware hub by handling all the necessary requests. 2309 *------------------------------------------------------------------------*/ 2310 2311static const 2312struct usb_device_descriptor uhci_devd = 2313{ 2314 sizeof(struct usb_device_descriptor), 2315 UDESC_DEVICE, /* type */ 2316 {0x00, 0x01}, /* USB version */ 2317 UDCLASS_HUB, /* class */ 2318 UDSUBCLASS_HUB, /* subclass */ 2319 UDPROTO_FSHUB, /* protocol */ 2320 64, /* max packet */ 2321 {0}, {0}, {0x00, 0x01}, /* device id */ 2322 1, 2, 0, /* string indicies */ 2323 1 /* # of configurations */ 2324}; 2325 2326static const struct uhci_config_desc uhci_confd = { 2327 .confd = { 2328 .bLength = sizeof(struct usb_config_descriptor), 2329 .bDescriptorType = UDESC_CONFIG, 2330 .wTotalLength[0] = sizeof(uhci_confd), 2331 .bNumInterface = 1, 2332 .bConfigurationValue = 1, 2333 .iConfiguration = 0, 2334 .bmAttributes = UC_SELF_POWERED, 2335 .bMaxPower = 0 /* max power */ 2336 }, 2337 .ifcd = { 2338 .bLength = sizeof(struct usb_interface_descriptor), 2339 .bDescriptorType = UDESC_INTERFACE, 2340 .bNumEndpoints = 1, 2341 .bInterfaceClass = UICLASS_HUB, 2342 .bInterfaceSubClass = UISUBCLASS_HUB, 2343 .bInterfaceProtocol = UIPROTO_FSHUB, 2344 }, 2345 .endpd = { 2346 .bLength = sizeof(struct usb_endpoint_descriptor), 2347 .bDescriptorType = UDESC_ENDPOINT, 2348 .bEndpointAddress = UE_DIR_IN | UHCI_INTR_ENDPT, 2349 .bmAttributes = UE_INTERRUPT, 2350 .wMaxPacketSize[0] = 8, /* max packet (63 ports) */ 2351 .bInterval = 255, 2352 }, 2353}; 2354 2355static const 2356struct usb_hub_descriptor_min uhci_hubd_piix = 2357{ 2358 .bDescLength = sizeof(uhci_hubd_piix), 2359 .bDescriptorType = UDESC_HUB, 2360 .bNbrPorts = 2, 2361 .wHubCharacteristics = {UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL, 0}, 2362 .bPwrOn2PwrGood = 50, 2363}; 2364 2365/* 2366 * The USB hub protocol requires that SET_FEATURE(PORT_RESET) also 2367 * enables the port, and also states that SET_FEATURE(PORT_ENABLE) 2368 * should not be used by the USB subsystem. As we cannot issue a 2369 * SET_FEATURE(PORT_ENABLE) externally, we must ensure that the port 2370 * will be enabled as part of the reset. 2371 * 2372 * On the VT83C572, the port cannot be successfully enabled until the 2373 * outstanding "port enable change" and "connection status change" 2374 * events have been reset. 2375 */ 2376static usb_error_t 2377uhci_portreset(uhci_softc_t *sc, uint16_t index) 2378{ 2379 uint16_t port; 2380 uint16_t x; 2381 uint8_t lim; 2382 2383 if (index == 1) 2384 port = UHCI_PORTSC1; 2385 else if (index == 2) 2386 port = UHCI_PORTSC2; 2387 else 2388 return (USB_ERR_IOERROR); 2389 2390 /* 2391 * Before we do anything, turn on SOF messages on the USB 2392 * BUS. Some USB devices do not cope without them! 2393 */ 2394 uhci_restart(sc); 2395 2396 x = URWMASK(UREAD2(sc, port)); 2397 UWRITE2(sc, port, x | UHCI_PORTSC_PR); 2398 2399 usb_pause_mtx(&sc->sc_bus.bus_mtx, 2400 USB_MS_TO_TICKS(usb_port_root_reset_delay)); 2401 2402 DPRINTFN(4, "uhci port %d reset, status0 = 0x%04x\n", 2403 index, UREAD2(sc, port)); 2404 2405 x = URWMASK(UREAD2(sc, port)); 2406 UWRITE2(sc, port, x & ~UHCI_PORTSC_PR); 2407 2408 2409 mtx_unlock(&sc->sc_bus.bus_mtx); 2410 2411 /* 2412 * This delay needs to be exactly 100us, else some USB devices 2413 * fail to attach! 2414 */ 2415 DELAY(100); 2416 2417 mtx_lock(&sc->sc_bus.bus_mtx); 2418 2419 DPRINTFN(4, "uhci port %d reset, status1 = 0x%04x\n", 2420 index, UREAD2(sc, port)); 2421 2422 x = URWMASK(UREAD2(sc, port)); 2423 UWRITE2(sc, port, x | UHCI_PORTSC_PE); 2424 2425 for (lim = 0; lim < 12; lim++) { 2426 2427 usb_pause_mtx(&sc->sc_bus.bus_mtx, 2428 USB_MS_TO_TICKS(usb_port_reset_delay)); 2429 2430 x = UREAD2(sc, port); 2431 2432 DPRINTFN(4, "uhci port %d iteration %u, status = 0x%04x\n", 2433 index, lim, x); 2434 2435 if (!(x & UHCI_PORTSC_CCS)) { 2436 /* 2437 * No device is connected (or was disconnected 2438 * during reset). Consider the port reset. 2439 * The delay must be long enough to ensure on 2440 * the initial iteration that the device 2441 * connection will have been registered. 50ms 2442 * appears to be sufficient, but 20ms is not. 2443 */ 2444 DPRINTFN(4, "uhci port %d loop %u, device detached\n", 2445 index, lim); 2446 goto done; 2447 } 2448 if (x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC)) { 2449 /* 2450 * Port enabled changed and/or connection 2451 * status changed were set. Reset either or 2452 * both raised flags (by writing a 1 to that 2453 * bit), and wait again for state to settle. 2454 */ 2455 UWRITE2(sc, port, URWMASK(x) | 2456 (x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC))); 2457 continue; 2458 } 2459 if (x & UHCI_PORTSC_PE) { 2460 /* port is enabled */ 2461 goto done; 2462 } 2463 UWRITE2(sc, port, URWMASK(x) | UHCI_PORTSC_PE); 2464 } 2465 2466 DPRINTFN(2, "uhci port %d reset timed out\n", index); 2467 return (USB_ERR_TIMEOUT); 2468 2469done: 2470 DPRINTFN(4, "uhci port %d reset, status2 = 0x%04x\n", 2471 index, UREAD2(sc, port)); 2472 2473 sc->sc_isreset = 1; 2474 return (USB_ERR_NORMAL_COMPLETION); 2475} 2476 2477static usb_error_t 2478uhci_roothub_exec(struct usb_device *udev, 2479 struct usb_device_request *req, const void **pptr, uint16_t *plength) 2480{ 2481 uhci_softc_t *sc = UHCI_BUS2SC(udev->bus); 2482 const void *ptr; 2483 const char *str_ptr; 2484 uint16_t x; 2485 uint16_t port; 2486 uint16_t value; 2487 uint16_t index; 2488 uint16_t status; 2489 uint16_t change; 2490 uint16_t len; 2491 usb_error_t err; 2492 2493 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2494 2495 /* buffer reset */ 2496 ptr = (const void *)&sc->sc_hub_desc.temp; 2497 len = 0; 2498 err = 0; 2499 2500 value = UGETW(req->wValue); 2501 index = UGETW(req->wIndex); 2502 2503 DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x " 2504 "wValue=0x%04x wIndex=0x%04x\n", 2505 req->bmRequestType, req->bRequest, 2506 UGETW(req->wLength), value, index); 2507 2508#define C(x,y) ((x) | ((y) << 8)) 2509 switch (C(req->bRequest, req->bmRequestType)) { 2510 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 2511 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 2512 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 2513 /* 2514 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 2515 * for the integrated root hub. 2516 */ 2517 break; 2518 case C(UR_GET_CONFIG, UT_READ_DEVICE): 2519 len = 1; 2520 sc->sc_hub_desc.temp[0] = sc->sc_conf; 2521 break; 2522 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2523 switch (value >> 8) { 2524 case UDESC_DEVICE: 2525 if ((value & 0xff) != 0) { 2526 err = USB_ERR_IOERROR; 2527 goto done; 2528 } 2529 len = sizeof(uhci_devd); 2530 ptr = (const void *)&uhci_devd; 2531 break; 2532 2533 case UDESC_CONFIG: 2534 if ((value & 0xff) != 0) { 2535 err = USB_ERR_IOERROR; 2536 goto done; 2537 } 2538 len = sizeof(uhci_confd); 2539 ptr = (const void *)&uhci_confd; 2540 break; 2541 2542 case UDESC_STRING: 2543 switch (value & 0xff) { 2544 case 0: /* Language table */ 2545 str_ptr = "\001"; 2546 break; 2547 2548 case 1: /* Vendor */ 2549 str_ptr = sc->sc_vendor; 2550 break; 2551 2552 case 2: /* Product */ 2553 str_ptr = "UHCI root HUB"; 2554 break; 2555 2556 default: 2557 str_ptr = ""; 2558 break; 2559 } 2560 2561 len = usb_make_str_desc 2562 (sc->sc_hub_desc.temp, 2563 sizeof(sc->sc_hub_desc.temp), 2564 str_ptr); 2565 break; 2566 2567 default: 2568 err = USB_ERR_IOERROR; 2569 goto done; 2570 } 2571 break; 2572 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 2573 len = 1; 2574 sc->sc_hub_desc.temp[0] = 0; 2575 break; 2576 case C(UR_GET_STATUS, UT_READ_DEVICE): 2577 len = 2; 2578 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED); 2579 break; 2580 case C(UR_GET_STATUS, UT_READ_INTERFACE): 2581 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 2582 len = 2; 2583 USETW(sc->sc_hub_desc.stat.wStatus, 0); 2584 break; 2585 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 2586 if (value >= UHCI_MAX_DEVICES) { 2587 err = USB_ERR_IOERROR; 2588 goto done; 2589 } 2590 sc->sc_addr = value; 2591 break; 2592 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 2593 if ((value != 0) && (value != 1)) { 2594 err = USB_ERR_IOERROR; 2595 goto done; 2596 } 2597 sc->sc_conf = value; 2598 break; 2599 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 2600 break; 2601 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 2602 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 2603 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 2604 err = USB_ERR_IOERROR; 2605 goto done; 2606 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 2607 break; 2608 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 2609 break; 2610 /* Hub requests */ 2611 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2612 break; 2613 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2614 DPRINTFN(4, "UR_CLEAR_PORT_FEATURE " 2615 "port=%d feature=%d\n", 2616 index, value); 2617 if (index == 1) 2618 port = UHCI_PORTSC1; 2619 else if (index == 2) 2620 port = UHCI_PORTSC2; 2621 else { 2622 err = USB_ERR_IOERROR; 2623 goto done; 2624 } 2625 switch (value) { 2626 case UHF_PORT_ENABLE: 2627 x = URWMASK(UREAD2(sc, port)); 2628 UWRITE2(sc, port, x & ~UHCI_PORTSC_PE); 2629 break; 2630 case UHF_PORT_SUSPEND: 2631 x = URWMASK(UREAD2(sc, port)); 2632 UWRITE2(sc, port, x & ~(UHCI_PORTSC_SUSP)); 2633 break; 2634 case UHF_PORT_RESET: 2635 x = URWMASK(UREAD2(sc, port)); 2636 UWRITE2(sc, port, x & ~UHCI_PORTSC_PR); 2637 break; 2638 case UHF_C_PORT_CONNECTION: 2639 x = URWMASK(UREAD2(sc, port)); 2640 UWRITE2(sc, port, x | UHCI_PORTSC_CSC); 2641 break; 2642 case UHF_C_PORT_ENABLE: 2643 x = URWMASK(UREAD2(sc, port)); 2644 UWRITE2(sc, port, x | UHCI_PORTSC_POEDC); 2645 break; 2646 case UHF_C_PORT_OVER_CURRENT: 2647 x = URWMASK(UREAD2(sc, port)); 2648 UWRITE2(sc, port, x | UHCI_PORTSC_OCIC); 2649 break; 2650 case UHF_C_PORT_RESET: 2651 sc->sc_isreset = 0; 2652 err = USB_ERR_NORMAL_COMPLETION; 2653 goto done; 2654 case UHF_C_PORT_SUSPEND: 2655 sc->sc_isresumed &= ~(1 << index); 2656 break; 2657 case UHF_PORT_CONNECTION: 2658 case UHF_PORT_OVER_CURRENT: 2659 case UHF_PORT_POWER: 2660 case UHF_PORT_LOW_SPEED: 2661 default: 2662 err = USB_ERR_IOERROR; 2663 goto done; 2664 } 2665 break; 2666 case C(UR_GET_BUS_STATE, UT_READ_CLASS_OTHER): 2667 if (index == 1) 2668 port = UHCI_PORTSC1; 2669 else if (index == 2) 2670 port = UHCI_PORTSC2; 2671 else { 2672 err = USB_ERR_IOERROR; 2673 goto done; 2674 } 2675 len = 1; 2676 sc->sc_hub_desc.temp[0] = 2677 ((UREAD2(sc, port) & UHCI_PORTSC_LS) >> 2678 UHCI_PORTSC_LS_SHIFT); 2679 break; 2680 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2681 if ((value & 0xff) != 0) { 2682 err = USB_ERR_IOERROR; 2683 goto done; 2684 } 2685 len = sizeof(uhci_hubd_piix); 2686 ptr = (const void *)&uhci_hubd_piix; 2687 break; 2688 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2689 len = 16; 2690 memset(sc->sc_hub_desc.temp, 0, 16); 2691 break; 2692 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2693 if (index == 1) 2694 port = UHCI_PORTSC1; 2695 else if (index == 2) 2696 port = UHCI_PORTSC2; 2697 else { 2698 err = USB_ERR_IOERROR; 2699 goto done; 2700 } 2701 x = UREAD2(sc, port); 2702 status = change = 0; 2703 if (x & UHCI_PORTSC_CCS) 2704 status |= UPS_CURRENT_CONNECT_STATUS; 2705 if (x & UHCI_PORTSC_CSC) 2706 change |= UPS_C_CONNECT_STATUS; 2707 if (x & UHCI_PORTSC_PE) 2708 status |= UPS_PORT_ENABLED; 2709 if (x & UHCI_PORTSC_POEDC) 2710 change |= UPS_C_PORT_ENABLED; 2711 if (x & UHCI_PORTSC_OCI) 2712 status |= UPS_OVERCURRENT_INDICATOR; 2713 if (x & UHCI_PORTSC_OCIC) 2714 change |= UPS_C_OVERCURRENT_INDICATOR; 2715 if (x & UHCI_PORTSC_LSDA) 2716 status |= UPS_LOW_SPEED; 2717 if ((x & UHCI_PORTSC_PE) && (x & UHCI_PORTSC_RD)) { 2718 /* need to do a write back */ 2719 UWRITE2(sc, port, URWMASK(x)); 2720 2721 /* wait 20ms for resume sequence to complete */ 2722 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50); 2723 2724 /* clear suspend and resume detect */ 2725 UWRITE2(sc, port, URWMASK(x) & ~(UHCI_PORTSC_RD | 2726 UHCI_PORTSC_SUSP)); 2727 2728 /* wait a little bit */ 2729 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 500); 2730 2731 sc->sc_isresumed |= (1 << index); 2732 2733 } else if (x & UHCI_PORTSC_SUSP) { 2734 status |= UPS_SUSPEND; 2735 } 2736 status |= UPS_PORT_POWER; 2737 if (sc->sc_isresumed & (1 << index)) 2738 change |= UPS_C_SUSPEND; 2739 if (sc->sc_isreset) 2740 change |= UPS_C_PORT_RESET; 2741 USETW(sc->sc_hub_desc.ps.wPortStatus, status); 2742 USETW(sc->sc_hub_desc.ps.wPortChange, change); 2743 len = sizeof(sc->sc_hub_desc.ps); 2744 break; 2745 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2746 err = USB_ERR_IOERROR; 2747 goto done; 2748 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2749 break; 2750 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2751 if (index == 1) 2752 port = UHCI_PORTSC1; 2753 else if (index == 2) 2754 port = UHCI_PORTSC2; 2755 else { 2756 err = USB_ERR_IOERROR; 2757 goto done; 2758 } 2759 switch (value) { 2760 case UHF_PORT_ENABLE: 2761 x = URWMASK(UREAD2(sc, port)); 2762 UWRITE2(sc, port, x | UHCI_PORTSC_PE); 2763 break; 2764 case UHF_PORT_SUSPEND: 2765 x = URWMASK(UREAD2(sc, port)); 2766 UWRITE2(sc, port, x | UHCI_PORTSC_SUSP); 2767 break; 2768 case UHF_PORT_RESET: 2769 err = uhci_portreset(sc, index); 2770 goto done; 2771 case UHF_PORT_POWER: 2772 /* pretend we turned on power */ 2773 err = USB_ERR_NORMAL_COMPLETION; 2774 goto done; 2775 case UHF_C_PORT_CONNECTION: 2776 case UHF_C_PORT_ENABLE: 2777 case UHF_C_PORT_OVER_CURRENT: 2778 case UHF_PORT_CONNECTION: 2779 case UHF_PORT_OVER_CURRENT: 2780 case UHF_PORT_LOW_SPEED: 2781 case UHF_C_PORT_SUSPEND: 2782 case UHF_C_PORT_RESET: 2783 default: 2784 err = USB_ERR_IOERROR; 2785 goto done; 2786 } 2787 break; 2788 default: 2789 err = USB_ERR_IOERROR; 2790 goto done; 2791 } 2792done: 2793 *plength = len; 2794 *pptr = ptr; 2795 return (err); 2796} 2797 2798/* 2799 * This routine is executed periodically and simulates interrupts from 2800 * the root controller interrupt pipe for port status change: 2801 */ 2802static void 2803uhci_root_intr(uhci_softc_t *sc) 2804{ 2805 DPRINTFN(21, "\n"); 2806 2807 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2808 2809 sc->sc_hub_idata[0] = 0; 2810 2811 if (UREAD2(sc, UHCI_PORTSC1) & (UHCI_PORTSC_CSC | 2812 UHCI_PORTSC_OCIC | UHCI_PORTSC_RD)) { 2813 sc->sc_hub_idata[0] |= 1 << 1; 2814 } 2815 if (UREAD2(sc, UHCI_PORTSC2) & (UHCI_PORTSC_CSC | 2816 UHCI_PORTSC_OCIC | UHCI_PORTSC_RD)) { 2817 sc->sc_hub_idata[0] |= 1 << 2; 2818 } 2819 2820 /* restart timer */ 2821 usb_callout_reset(&sc->sc_root_intr, hz, 2822 (void *)&uhci_root_intr, sc); 2823 2824 if (sc->sc_hub_idata[0] != 0) { 2825 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, 2826 sizeof(sc->sc_hub_idata)); 2827 } 2828} 2829 2830static void 2831uhci_xfer_setup(struct usb_setup_params *parm) 2832{ 2833 struct usb_page_search page_info; 2834 struct usb_page_cache *pc; 2835 uhci_softc_t *sc; 2836 struct usb_xfer *xfer; 2837 void *last_obj; 2838 uint32_t ntd; 2839 uint32_t nqh; 2840 uint32_t nfixup; 2841 uint32_t n; 2842 uint16_t align; 2843 2844 sc = UHCI_BUS2SC(parm->udev->bus); 2845 xfer = parm->curr_xfer; 2846 2847 parm->hc_max_packet_size = 0x500; 2848 parm->hc_max_packet_count = 1; 2849 parm->hc_max_frame_size = 0x500; 2850 2851 /* 2852 * compute ntd and nqh 2853 */ 2854 if (parm->methods == &uhci_device_ctrl_methods) { 2855 xfer->flags_int.bdma_enable = 1; 2856 xfer->flags_int.bdma_no_post_sync = 1; 2857 2858 usbd_transfer_setup_sub(parm); 2859 2860 /* see EHCI HC driver for proof of "ntd" formula */ 2861 2862 nqh = 1; 2863 ntd = ((2 * xfer->nframes) + 1 /* STATUS */ 2864 + (xfer->max_data_length / xfer->max_frame_size)); 2865 2866 } else if (parm->methods == &uhci_device_bulk_methods) { 2867 xfer->flags_int.bdma_enable = 1; 2868 xfer->flags_int.bdma_no_post_sync = 1; 2869 2870 usbd_transfer_setup_sub(parm); 2871 2872 nqh = 1; 2873 ntd = ((2 * xfer->nframes) 2874 + (xfer->max_data_length / xfer->max_frame_size)); 2875 2876 } else if (parm->methods == &uhci_device_intr_methods) { 2877 xfer->flags_int.bdma_enable = 1; 2878 xfer->flags_int.bdma_no_post_sync = 1; 2879 2880 usbd_transfer_setup_sub(parm); 2881 2882 nqh = 1; 2883 ntd = ((2 * xfer->nframes) 2884 + (xfer->max_data_length / xfer->max_frame_size)); 2885 2886 } else if (parm->methods == &uhci_device_isoc_methods) { 2887 xfer->flags_int.bdma_enable = 1; 2888 xfer->flags_int.bdma_no_post_sync = 1; 2889 2890 usbd_transfer_setup_sub(parm); 2891 2892 nqh = 0; 2893 ntd = xfer->nframes; 2894 2895 } else { 2896 2897 usbd_transfer_setup_sub(parm); 2898 2899 nqh = 0; 2900 ntd = 0; 2901 } 2902 2903 if (parm->err) { 2904 return; 2905 } 2906 /* 2907 * NOTE: the UHCI controller requires that 2908 * every packet must be contiguous on 2909 * the same USB memory page ! 2910 */ 2911 nfixup = (parm->bufsize / USB_PAGE_SIZE) + 1; 2912 2913 /* 2914 * Compute a suitable power of two alignment 2915 * for our "max_frame_size" fixup buffer(s): 2916 */ 2917 align = xfer->max_frame_size; 2918 n = 0; 2919 while (align) { 2920 align >>= 1; 2921 n++; 2922 } 2923 2924 /* check for power of two */ 2925 if (!(xfer->max_frame_size & 2926 (xfer->max_frame_size - 1))) { 2927 n--; 2928 } 2929 /* 2930 * We don't allow alignments of 2931 * less than 8 bytes: 2932 * 2933 * NOTE: Allocating using an aligment 2934 * of 1 byte has special meaning! 2935 */ 2936 if (n < 3) { 2937 n = 3; 2938 } 2939 align = (1 << n); 2940 2941 if (usbd_transfer_setup_sub_malloc( 2942 parm, &pc, xfer->max_frame_size, 2943 align, nfixup)) { 2944 parm->err = USB_ERR_NOMEM; 2945 return; 2946 } 2947 xfer->buf_fixup = pc; 2948 2949alloc_dma_set: 2950 2951 if (parm->err) { 2952 return; 2953 } 2954 last_obj = NULL; 2955 2956 if (usbd_transfer_setup_sub_malloc( 2957 parm, &pc, sizeof(uhci_td_t), 2958 UHCI_TD_ALIGN, ntd)) { 2959 parm->err = USB_ERR_NOMEM; 2960 return; 2961 } 2962 if (parm->buf) { 2963 for (n = 0; n != ntd; n++) { 2964 uhci_td_t *td; 2965 2966 usbd_get_page(pc + n, 0, &page_info); 2967 2968 td = page_info.buffer; 2969 2970 /* init TD */ 2971 if ((parm->methods == &uhci_device_bulk_methods) || 2972 (parm->methods == &uhci_device_ctrl_methods) || 2973 (parm->methods == &uhci_device_intr_methods)) { 2974 /* set depth first bit */ 2975 td->td_self = htole32(page_info.physaddr | 2976 UHCI_PTR_TD | UHCI_PTR_VF); 2977 } else { 2978 td->td_self = htole32(page_info.physaddr | 2979 UHCI_PTR_TD); 2980 } 2981 2982 td->obj_next = last_obj; 2983 td->page_cache = pc + n; 2984 2985 last_obj = td; 2986 2987 usb_pc_cpu_flush(pc + n); 2988 } 2989 } 2990 xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj; 2991 2992 last_obj = NULL; 2993 2994 if (usbd_transfer_setup_sub_malloc( 2995 parm, &pc, sizeof(uhci_qh_t), 2996 UHCI_QH_ALIGN, nqh)) { 2997 parm->err = USB_ERR_NOMEM; 2998 return; 2999 } 3000 if (parm->buf) { 3001 for (n = 0; n != nqh; n++) { 3002 uhci_qh_t *qh; 3003 3004 usbd_get_page(pc + n, 0, &page_info); 3005 3006 qh = page_info.buffer; 3007 3008 /* init QH */ 3009 qh->qh_self = htole32(page_info.physaddr | UHCI_PTR_QH); 3010 qh->obj_next = last_obj; 3011 qh->page_cache = pc + n; 3012 3013 last_obj = qh; 3014 3015 usb_pc_cpu_flush(pc + n); 3016 } 3017 } 3018 xfer->qh_start[xfer->flags_int.curr_dma_set] = last_obj; 3019 3020 if (!xfer->flags_int.curr_dma_set) { 3021 xfer->flags_int.curr_dma_set = 1; 3022 goto alloc_dma_set; 3023 } 3024} 3025 3026static void 3027uhci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc, 3028 struct usb_endpoint *ep) 3029{ 3030 uhci_softc_t *sc = UHCI_BUS2SC(udev->bus); 3031 3032 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d (%d)\n", 3033 ep, udev->address, 3034 edesc->bEndpointAddress, udev->flags.usb_mode, 3035 sc->sc_addr); 3036 3037 if (udev->device_index != sc->sc_addr) { 3038 switch (edesc->bmAttributes & UE_XFERTYPE) { 3039 case UE_CONTROL: 3040 ep->methods = &uhci_device_ctrl_methods; 3041 break; 3042 case UE_INTERRUPT: 3043 ep->methods = &uhci_device_intr_methods; 3044 break; 3045 case UE_ISOCHRONOUS: 3046 if (udev->speed == USB_SPEED_FULL) { 3047 ep->methods = &uhci_device_isoc_methods; 3048 } 3049 break; 3050 case UE_BULK: 3051 ep->methods = &uhci_device_bulk_methods; 3052 break; 3053 default: 3054 /* do nothing */ 3055 break; 3056 } 3057 } 3058} 3059 3060static void 3061uhci_xfer_unsetup(struct usb_xfer *xfer) 3062{ 3063 return; 3064} 3065 3066static void 3067uhci_get_dma_delay(struct usb_device *udev, uint32_t *pus) 3068{ 3069 /* 3070 * Wait until hardware has finished any possible use of the 3071 * transfer descriptor(s) and QH 3072 */ 3073 *pus = (1125); /* microseconds */ 3074} 3075 3076static void 3077uhci_device_resume(struct usb_device *udev) 3078{ 3079 struct uhci_softc *sc = UHCI_BUS2SC(udev->bus); 3080 struct usb_xfer *xfer; 3081 struct usb_pipe_methods *methods; 3082 uhci_qh_t *qh; 3083 3084 DPRINTF("\n"); 3085 3086 USB_BUS_LOCK(udev->bus); 3087 3088 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3089 3090 if (xfer->xroot->udev == udev) { 3091 3092 methods = xfer->endpoint->methods; 3093 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 3094 3095 if (methods == &uhci_device_bulk_methods) { 3096 UHCI_APPEND_QH(qh, sc->sc_bulk_p_last); 3097 uhci_add_loop(sc); 3098 xfer->flags_int.bandwidth_reclaimed = 1; 3099 } 3100 if (methods == &uhci_device_ctrl_methods) { 3101 if (xfer->xroot->udev->speed == USB_SPEED_LOW) { 3102 UHCI_APPEND_QH(qh, sc->sc_ls_ctl_p_last); 3103 } else { 3104 UHCI_APPEND_QH(qh, sc->sc_fs_ctl_p_last); 3105 } 3106 } 3107 if (methods == &uhci_device_intr_methods) { 3108 UHCI_APPEND_QH(qh, sc->sc_intr_p_last[xfer->qh_pos]); 3109 } 3110 } 3111 } 3112 3113 USB_BUS_UNLOCK(udev->bus); 3114 3115 return; 3116} 3117 3118static void 3119uhci_device_suspend(struct usb_device *udev) 3120{ 3121 struct uhci_softc *sc = UHCI_BUS2SC(udev->bus); 3122 struct usb_xfer *xfer; 3123 struct usb_pipe_methods *methods; 3124 uhci_qh_t *qh; 3125 3126 DPRINTF("\n"); 3127 3128 USB_BUS_LOCK(udev->bus); 3129 3130 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3131 3132 if (xfer->xroot->udev == udev) { 3133 3134 methods = xfer->endpoint->methods; 3135 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 3136 3137 if (xfer->flags_int.bandwidth_reclaimed) { 3138 xfer->flags_int.bandwidth_reclaimed = 0; 3139 uhci_rem_loop(sc); 3140 } 3141 if (methods == &uhci_device_bulk_methods) { 3142 UHCI_REMOVE_QH(qh, sc->sc_bulk_p_last); 3143 } 3144 if (methods == &uhci_device_ctrl_methods) { 3145 if (xfer->xroot->udev->speed == USB_SPEED_LOW) { 3146 UHCI_REMOVE_QH(qh, sc->sc_ls_ctl_p_last); 3147 } else { 3148 UHCI_REMOVE_QH(qh, sc->sc_fs_ctl_p_last); 3149 } 3150 } 3151 if (methods == &uhci_device_intr_methods) { 3152 UHCI_REMOVE_QH(qh, sc->sc_intr_p_last[xfer->qh_pos]); 3153 } 3154 } 3155 } 3156 3157 USB_BUS_UNLOCK(udev->bus); 3158 3159 return; 3160} 3161 3162static void 3163uhci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state) 3164{ 3165 struct uhci_softc *sc = UHCI_BUS2SC(bus); 3166 3167 switch (state) { 3168 case USB_HW_POWER_SUSPEND: 3169 case USB_HW_POWER_SHUTDOWN: 3170 uhci_suspend(sc); 3171 break; 3172 case USB_HW_POWER_RESUME: 3173 uhci_resume(sc); 3174 break; 3175 default: 3176 break; 3177 } 3178} 3179 3180static void 3181uhci_set_hw_power(struct usb_bus *bus) 3182{ 3183 struct uhci_softc *sc = UHCI_BUS2SC(bus); 3184 uint32_t flags; 3185 3186 DPRINTF("\n"); 3187 3188 USB_BUS_LOCK(bus); 3189 3190 flags = bus->hw_power_state; 3191 3192 /* 3193 * WARNING: Some FULL speed USB devices require periodic SOF 3194 * messages! If any USB devices are connected through the 3195 * UHCI, power save will be disabled! 3196 */ 3197 if (flags & (USB_HW_POWER_CONTROL | 3198 USB_HW_POWER_NON_ROOT_HUB | 3199 USB_HW_POWER_BULK | 3200 USB_HW_POWER_INTERRUPT | 3201 USB_HW_POWER_ISOC)) { 3202 DPRINTF("Some USB transfer is " 3203 "active on unit %u.\n", 3204 device_get_unit(sc->sc_bus.bdev)); 3205 uhci_restart(sc); 3206 } else { 3207 DPRINTF("Power save on unit %u.\n", 3208 device_get_unit(sc->sc_bus.bdev)); 3209 UHCICMD(sc, UHCI_CMD_MAXP); 3210 } 3211 3212 USB_BUS_UNLOCK(bus); 3213 3214 return; 3215} 3216 3217 3218struct usb_bus_methods uhci_bus_methods = 3219{ 3220 .endpoint_init = uhci_ep_init, 3221 .xfer_setup = uhci_xfer_setup, 3222 .xfer_unsetup = uhci_xfer_unsetup, 3223 .get_dma_delay = uhci_get_dma_delay, 3224 .device_resume = uhci_device_resume, 3225 .device_suspend = uhci_device_suspend, 3226 .set_hw_power = uhci_set_hw_power, 3227 .set_hw_power_sleep = uhci_set_hw_power_sleep, 3228 .roothub_exec = uhci_roothub_exec, 3229 .xfer_poll = uhci_do_poll, 3230}; 3231