1198151Sthompsa/* $FreeBSD$ */ 2198151Sthompsa/*- 3198151Sthompsa * Copyright (c) 1998 The NetBSD Foundation, Inc. 4198151Sthompsa * All rights reserved. 5198151Sthompsa * 6198151Sthompsa * This code is derived from software contributed to The NetBSD Foundation 7198151Sthompsa * by Lennart Augustsson (lennart@augustsson.net) at 8198151Sthompsa * Carlstedt Research & Technology. 9198151Sthompsa * 10198151Sthompsa * Redistribution and use in source and binary forms, with or without 11198151Sthompsa * modification, are permitted provided that the following conditions 12198151Sthompsa * are met: 13198151Sthompsa * 1. Redistributions of source code must retain the above copyright 14198151Sthompsa * notice, this list of conditions and the following disclaimer. 15198151Sthompsa * 2. Redistributions in binary form must reproduce the above copyright 16198151Sthompsa * notice, this list of conditions and the following disclaimer in the 17198151Sthompsa * documentation and/or other materials provided with the distribution. 18198151Sthompsa * 19198151Sthompsa * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20198151Sthompsa * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21198151Sthompsa * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22198151Sthompsa * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23198151Sthompsa * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24198151Sthompsa * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25198151Sthompsa * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26198151Sthompsa * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27198151Sthompsa * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28198151Sthompsa * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29198151Sthompsa * POSSIBILITY OF SUCH DAMAGE. 30198151Sthompsa */ 31198151Sthompsa 32198151Sthompsa#ifndef _OHCIREG_H_ 33198151Sthompsa#define _OHCIREG_H_ 34198151Sthompsa 35198151Sthompsa/* PCI config registers */ 36198151Sthompsa#define PCI_CBMEM 0x10 /* configuration base memory */ 37198151Sthompsa#define PCI_INTERFACE_OHCI 0x10 38198151Sthompsa 39198151Sthompsa/* OHCI registers */ 40198151Sthompsa#define OHCI_REVISION 0x00 /* OHCI revision */ 41198151Sthompsa#define OHCI_REV_LO(rev) ((rev) & 0xf) 42198151Sthompsa#define OHCI_REV_HI(rev) (((rev)>>4) & 0xf) 43198151Sthompsa#define OHCI_REV_LEGACY(rev) ((rev) & 0x100) 44198151Sthompsa#define OHCI_CONTROL 0x04 45198151Sthompsa#define OHCI_CBSR_MASK 0x00000003 /* Control/Bulk Service Ratio */ 46198151Sthompsa#define OHCI_RATIO_1_1 0x00000000 47198151Sthompsa#define OHCI_RATIO_1_2 0x00000001 48198151Sthompsa#define OHCI_RATIO_1_3 0x00000002 49198151Sthompsa#define OHCI_RATIO_1_4 0x00000003 50198151Sthompsa#define OHCI_PLE 0x00000004 /* Periodic List Enable */ 51198151Sthompsa#define OHCI_IE 0x00000008 /* Isochronous Enable */ 52198151Sthompsa#define OHCI_CLE 0x00000010 /* Control List Enable */ 53198151Sthompsa#define OHCI_BLE 0x00000020 /* Bulk List Enable */ 54198151Sthompsa#define OHCI_HCFS_MASK 0x000000c0 /* HostControllerFunctionalStat 55198151Sthompsa * e */ 56198151Sthompsa#define OHCI_HCFS_RESET 0x00000000 57198151Sthompsa#define OHCI_HCFS_RESUME 0x00000040 58198151Sthompsa#define OHCI_HCFS_OPERATIONAL 0x00000080 59198151Sthompsa#define OHCI_HCFS_SUSPEND 0x000000c0 60198151Sthompsa#define OHCI_IR 0x00000100 /* Interrupt Routing */ 61198151Sthompsa#define OHCI_RWC 0x00000200 /* Remote Wakeup Connected */ 62198151Sthompsa#define OHCI_RWE 0x00000400 /* Remote Wakeup Enabled */ 63198151Sthompsa#define OHCI_COMMAND_STATUS 0x08 64198151Sthompsa#define OHCI_HCR 0x00000001 /* Host Controller Reset */ 65198151Sthompsa#define OHCI_CLF 0x00000002 /* Control List Filled */ 66198151Sthompsa#define OHCI_BLF 0x00000004 /* Bulk List Filled */ 67198151Sthompsa#define OHCI_OCR 0x00000008 /* Ownership Change Request */ 68198151Sthompsa#define OHCI_SOC_MASK 0x00030000 /* Scheduling Overrun Count */ 69198151Sthompsa#define OHCI_INTERRUPT_STATUS 0x0c 70198151Sthompsa#define OHCI_SO 0x00000001 /* Scheduling Overrun */ 71198151Sthompsa#define OHCI_WDH 0x00000002 /* Writeback Done Head */ 72198151Sthompsa#define OHCI_SF 0x00000004 /* Start of Frame */ 73198151Sthompsa#define OHCI_RD 0x00000008 /* Resume Detected */ 74198151Sthompsa#define OHCI_UE 0x00000010 /* Unrecoverable Error */ 75198151Sthompsa#define OHCI_FNO 0x00000020 /* Frame Number Overflow */ 76198151Sthompsa#define OHCI_RHSC 0x00000040 /* Root Hub Status Change */ 77198151Sthompsa#define OHCI_OC 0x40000000 /* Ownership Change */ 78198151Sthompsa#define OHCI_MIE 0x80000000 /* Master Interrupt Enable */ 79198151Sthompsa#define OHCI_INTERRUPT_ENABLE 0x10 80198151Sthompsa#define OHCI_INTERRUPT_DISABLE 0x14 81198151Sthompsa#define OHCI_HCCA 0x18 82198151Sthompsa#define OHCI_PERIOD_CURRENT_ED 0x1c 83198151Sthompsa#define OHCI_CONTROL_HEAD_ED 0x20 84198151Sthompsa#define OHCI_CONTROL_CURRENT_ED 0x24 85198151Sthompsa#define OHCI_BULK_HEAD_ED 0x28 86198151Sthompsa#define OHCI_BULK_CURRENT_ED 0x2c 87198151Sthompsa#define OHCI_DONE_HEAD 0x30 88198151Sthompsa#define OHCI_FM_INTERVAL 0x34 89198151Sthompsa#define OHCI_GET_IVAL(s) ((s) & 0x3fff) 90198151Sthompsa#define OHCI_GET_FSMPS(s) (((s) >> 16) & 0x7fff) 91198151Sthompsa#define OHCI_FIT 0x80000000 92198151Sthompsa#define OHCI_FM_REMAINING 0x38 93198151Sthompsa#define OHCI_FM_NUMBER 0x3c 94198151Sthompsa#define OHCI_PERIODIC_START 0x40 95198151Sthompsa#define OHCI_LS_THRESHOLD 0x44 96198151Sthompsa#define OHCI_RH_DESCRIPTOR_A 0x48 97198151Sthompsa#define OHCI_GET_NDP(s) ((s) & 0xff) 98198151Sthompsa#define OHCI_PSM 0x0100 /* Power Switching Mode */ 99198151Sthompsa#define OHCI_NPS 0x0200 /* No Power Switching */ 100198151Sthompsa#define OHCI_DT 0x0400 /* Device Type */ 101198151Sthompsa#define OHCI_OCPM 0x0800 /* Overcurrent Protection Mode */ 102198151Sthompsa#define OHCI_NOCP 0x1000 /* No Overcurrent Protection */ 103198151Sthompsa#define OHCI_GET_POTPGT(s) ((s) >> 24) 104198151Sthompsa#define OHCI_RH_DESCRIPTOR_B 0x4c 105198151Sthompsa#define OHCI_RH_STATUS 0x50 106198151Sthompsa#define OHCI_LPS 0x00000001 /* Local Power Status */ 107198151Sthompsa#define OHCI_OCI 0x00000002 /* OverCurrent Indicator */ 108198151Sthompsa#define OHCI_DRWE 0x00008000 /* Device Remote Wakeup Enable */ 109198151Sthompsa#define OHCI_LPSC 0x00010000 /* Local Power Status Change */ 110198151Sthompsa#define OHCI_CCIC 0x00020000 /* OverCurrent Indicator 111198151Sthompsa * Change */ 112198151Sthompsa#define OHCI_CRWE 0x80000000 /* Clear Remote Wakeup Enable */ 113198151Sthompsa#define OHCI_RH_PORT_STATUS(n) (0x50 + ((n)*4)) /* 1 based indexing */ 114198151Sthompsa 115198151Sthompsa#define OHCI_LES (OHCI_PLE | OHCI_IE | OHCI_CLE | OHCI_BLE) 116198151Sthompsa#define OHCI_ALL_INTRS (OHCI_SO | OHCI_WDH | OHCI_SF | \ 117198151Sthompsa OHCI_RD | OHCI_UE | OHCI_FNO | \ 118198151Sthompsa OHCI_RHSC | OHCI_OC) 119198151Sthompsa#define OHCI_NORMAL_INTRS (OHCI_WDH | OHCI_RD | OHCI_UE | OHCI_RHSC) 120198151Sthompsa 121198151Sthompsa#define OHCI_FSMPS(i) (((i-210)*6/7) << 16) 122198151Sthompsa#define OHCI_PERIODIC(i) ((i)*9/10) 123198151Sthompsa 124198151Sthompsa#endif /* _OHCIREG_H_ */ 125