musb_otg.c revision 257041
1/* $FreeBSD: stable/9/sys/dev/usb/controller/musb_otg.c 257041 2013-10-24 06:22:43Z hselasky $ */ 2/*- 3 * Copyright (c) 2008 Hans Petter Selasky. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27/* 28 * Thanks to Mentor Graphics for providing a reference driver for this USB chip 29 * at their homepage. 30 */ 31 32/* 33 * This file contains the driver for the Mentor Graphics Inventra USB 34 * 2.0 High Speed Dual-Role controller. 35 * 36 * NOTE: The current implementation only supports Device Side Mode! 37 */ 38 39#include <sys/stdint.h> 40#include <sys/stddef.h> 41#include <sys/param.h> 42#include <sys/queue.h> 43#include <sys/types.h> 44#include <sys/systm.h> 45#include <sys/kernel.h> 46#include <sys/bus.h> 47#include <sys/module.h> 48#include <sys/lock.h> 49#include <sys/mutex.h> 50#include <sys/condvar.h> 51#include <sys/sysctl.h> 52#include <sys/sx.h> 53#include <sys/unistd.h> 54#include <sys/callout.h> 55#include <sys/malloc.h> 56#include <sys/priv.h> 57 58#include <dev/usb/usb.h> 59#include <dev/usb/usbdi.h> 60 61#define USB_DEBUG_VAR musbotgdebug 62 63#include <dev/usb/usb_core.h> 64#include <dev/usb/usb_debug.h> 65#include <dev/usb/usb_busdma.h> 66#include <dev/usb/usb_process.h> 67#include <dev/usb/usb_transfer.h> 68#include <dev/usb/usb_device.h> 69#include <dev/usb/usb_hub.h> 70#include <dev/usb/usb_util.h> 71 72#include <dev/usb/usb_controller.h> 73#include <dev/usb/usb_bus.h> 74#include <dev/usb/controller/musb_otg.h> 75 76#define MUSBOTG_INTR_ENDPT 1 77 78#define MUSBOTG_BUS2SC(bus) \ 79 ((struct musbotg_softc *)(((uint8_t *)(bus)) - \ 80 USB_P2U(&(((struct musbotg_softc *)0)->sc_bus)))) 81 82#define MUSBOTG_PC2SC(pc) \ 83 MUSBOTG_BUS2SC(USB_DMATAG_TO_XROOT((pc)->tag_parent)->bus) 84 85#ifdef USB_DEBUG 86static int musbotgdebug = 0; 87 88static SYSCTL_NODE(_hw_usb, OID_AUTO, musbotg, CTLFLAG_RW, 0, "USB musbotg"); 89SYSCTL_INT(_hw_usb_musbotg, OID_AUTO, debug, CTLFLAG_RW, 90 &musbotgdebug, 0, "Debug level"); 91#endif 92 93#define MAX_NAK_TO 16 94 95/* prototypes */ 96 97struct usb_bus_methods musbotg_bus_methods; 98struct usb_pipe_methods musbotg_device_bulk_methods; 99struct usb_pipe_methods musbotg_device_ctrl_methods; 100struct usb_pipe_methods musbotg_device_intr_methods; 101struct usb_pipe_methods musbotg_device_isoc_methods; 102 103/* Control transfers: Device mode */ 104static musbotg_cmd_t musbotg_dev_ctrl_setup_rx; 105static musbotg_cmd_t musbotg_dev_ctrl_data_rx; 106static musbotg_cmd_t musbotg_dev_ctrl_data_tx; 107static musbotg_cmd_t musbotg_dev_ctrl_status; 108 109/* Control transfers: Host mode */ 110static musbotg_cmd_t musbotg_host_ctrl_setup_tx; 111static musbotg_cmd_t musbotg_host_ctrl_data_rx; 112static musbotg_cmd_t musbotg_host_ctrl_data_tx; 113static musbotg_cmd_t musbotg_host_ctrl_status_rx; 114static musbotg_cmd_t musbotg_host_ctrl_status_tx; 115 116/* Bulk, Interrupt, Isochronous: Device mode */ 117static musbotg_cmd_t musbotg_dev_data_rx; 118static musbotg_cmd_t musbotg_dev_data_tx; 119 120/* Bulk, Interrupt, Isochronous: Host mode */ 121static musbotg_cmd_t musbotg_host_data_rx; 122static musbotg_cmd_t musbotg_host_data_tx; 123 124static void musbotg_device_done(struct usb_xfer *, usb_error_t); 125static void musbotg_do_poll(struct usb_bus *); 126static void musbotg_standard_done(struct usb_xfer *); 127static void musbotg_interrupt_poll(struct musbotg_softc *); 128static void musbotg_root_intr(struct musbotg_softc *); 129static int musbotg_channel_alloc(struct musbotg_softc *, struct musbotg_td *td); 130static void musbotg_channel_free(struct musbotg_softc *, struct musbotg_td *td); 131static void musbotg_ep_int_set(struct musbotg_softc *sc, int channel, int on); 132 133/* 134 * Here is a configuration that the chip supports. 135 */ 136static const struct usb_hw_ep_profile musbotg_ep_profile[1] = { 137 138 [0] = { 139 .max_in_frame_size = 64,/* fixed */ 140 .max_out_frame_size = 64, /* fixed */ 141 .is_simplex = 1, 142 .support_control = 1, 143 } 144}; 145 146static int 147musbotg_channel_alloc(struct musbotg_softc *sc, struct musbotg_td *td) 148{ 149 int ch; 150 int ep; 151 152 ep = td->ep_no; 153 154 /* In device mode each EP got its own channel */ 155 if (sc->sc_mode == MUSB2_DEVICE_MODE) { 156 musbotg_ep_int_set(sc, ep, 1); 157 return (ep); 158 } 159 160 /* 161 * All control transactions go through EP0 162 */ 163 if (ep == 0) { 164 if (sc->sc_channel_mask & (1 << 0)) 165 return (-1); 166 sc->sc_channel_mask |= (1 << 0); 167 musbotg_ep_int_set(sc, ep, 1); 168 return (0); 169 } 170 171 for (ch = 1; ch < MUSB2_EP_MAX; ch++) { 172 if (!(sc->sc_channel_mask & (1 << ch))) { 173 sc->sc_channel_mask |= (1 << ch); 174 musbotg_ep_int_set(sc, ch, 1); 175 return (ch); 176 } 177 } 178 179 DPRINTFN(-1, "No available channels. Mask: %04x\n", sc->sc_channel_mask); 180 181 return (-1); 182} 183 184static void 185musbotg_channel_free(struct musbotg_softc *sc, struct musbotg_td *td) 186{ 187 188 DPRINTFN(1, "ep_no=%d\n", td->channel); 189 190 if (sc->sc_mode == MUSB2_DEVICE_MODE) 191 return; 192 193 if (td == NULL) 194 return; 195 if (td->channel == -1) 196 return; 197 198 musbotg_ep_int_set(sc, td->channel, 0); 199 sc->sc_channel_mask &= ~(1 << td->channel); 200 201 td->channel = -1; 202} 203 204static void 205musbotg_get_hw_ep_profile(struct usb_device *udev, 206 const struct usb_hw_ep_profile **ppf, uint8_t ep_addr) 207{ 208 struct musbotg_softc *sc; 209 210 sc = MUSBOTG_BUS2SC(udev->bus); 211 212 if (ep_addr == 0) { 213 /* control endpoint */ 214 *ppf = musbotg_ep_profile; 215 } else if (ep_addr <= sc->sc_ep_max) { 216 /* other endpoints */ 217 *ppf = sc->sc_hw_ep_profile + ep_addr; 218 } else { 219 *ppf = NULL; 220 } 221} 222 223static void 224musbotg_clocks_on(struct musbotg_softc *sc) 225{ 226 if (sc->sc_flags.clocks_off && 227 sc->sc_flags.port_powered) { 228 229 DPRINTFN(4, "\n"); 230 231 if (sc->sc_clocks_on) { 232 (sc->sc_clocks_on) (sc->sc_clocks_arg); 233 } 234 sc->sc_flags.clocks_off = 0; 235 236 /* XXX enable Transceiver */ 237 } 238} 239 240static void 241musbotg_clocks_off(struct musbotg_softc *sc) 242{ 243 if (!sc->sc_flags.clocks_off) { 244 245 DPRINTFN(4, "\n"); 246 247 /* XXX disable Transceiver */ 248 249 if (sc->sc_clocks_off) { 250 (sc->sc_clocks_off) (sc->sc_clocks_arg); 251 } 252 sc->sc_flags.clocks_off = 1; 253 } 254} 255 256static void 257musbotg_pull_common(struct musbotg_softc *sc, uint8_t on) 258{ 259 uint8_t temp; 260 261 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER); 262 if (on) 263 temp |= MUSB2_MASK_SOFTC; 264 else 265 temp &= ~MUSB2_MASK_SOFTC; 266 267 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp); 268} 269 270static void 271musbotg_pull_up(struct musbotg_softc *sc) 272{ 273 /* pullup D+, if possible */ 274 275 if (!sc->sc_flags.d_pulled_up && 276 sc->sc_flags.port_powered) { 277 sc->sc_flags.d_pulled_up = 1; 278 musbotg_pull_common(sc, 1); 279 } 280} 281 282static void 283musbotg_pull_down(struct musbotg_softc *sc) 284{ 285 /* pulldown D+, if possible */ 286 287 if (sc->sc_flags.d_pulled_up) { 288 sc->sc_flags.d_pulled_up = 0; 289 musbotg_pull_common(sc, 0); 290 } 291} 292 293static void 294musbotg_suspend_host(struct musbotg_softc *sc) 295{ 296 uint8_t temp; 297 298 if (sc->sc_flags.status_suspend) { 299 return; 300 } 301 302 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER); 303 temp |= MUSB2_MASK_SUSPMODE; 304 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp); 305 sc->sc_flags.status_suspend = 1; 306} 307 308static void 309musbotg_wakeup_host(struct musbotg_softc *sc) 310{ 311 uint8_t temp; 312 313 if (!(sc->sc_flags.status_suspend)) { 314 return; 315 } 316 317 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER); 318 temp &= ~MUSB2_MASK_SUSPMODE; 319 temp |= MUSB2_MASK_RESUME; 320 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp); 321 322 /* wait 20 milliseconds */ 323 /* Wait for reset to complete. */ 324 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50); 325 326 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER); 327 temp &= ~MUSB2_MASK_RESUME; 328 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp); 329 330 sc->sc_flags.status_suspend = 0; 331} 332 333static void 334musbotg_wakeup_peer(struct musbotg_softc *sc) 335{ 336 uint8_t temp; 337 338 if (!(sc->sc_flags.status_suspend)) { 339 return; 340 } 341 342 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER); 343 temp |= MUSB2_MASK_RESUME; 344 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp); 345 346 /* wait 8 milliseconds */ 347 /* Wait for reset to complete. */ 348 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 125); 349 350 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER); 351 temp &= ~MUSB2_MASK_RESUME; 352 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp); 353} 354 355static void 356musbotg_set_address(struct musbotg_softc *sc, uint8_t addr) 357{ 358 DPRINTFN(4, "addr=%d\n", addr); 359 addr &= 0x7F; 360 MUSB2_WRITE_1(sc, MUSB2_REG_FADDR, addr); 361} 362 363static uint8_t 364musbotg_dev_ctrl_setup_rx(struct musbotg_td *td) 365{ 366 struct musbotg_softc *sc; 367 struct usb_device_request req; 368 uint16_t count; 369 uint8_t csr; 370 371 /* get pointer to softc */ 372 sc = MUSBOTG_PC2SC(td->pc); 373 374 if (td->channel == -1) 375 td->channel = musbotg_channel_alloc(sc, td); 376 377 /* EP0 is busy, wait */ 378 if (td->channel == -1) 379 return (1); 380 381 DPRINTFN(1, "ep_no=%d\n", td->channel); 382 383 /* select endpoint 0 */ 384 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); 385 386 /* read out FIFO status */ 387 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 388 389 DPRINTFN(4, "csr=0x%02x\n", csr); 390 391 /* 392 * NOTE: If DATAEND is set we should not call the 393 * callback, hence the status stage is not complete. 394 */ 395 if (csr & MUSB2_MASK_CSR0L_DATAEND) { 396 /* do not stall at this point */ 397 td->did_stall = 1; 398 /* wait for interrupt */ 399 DPRINTFN(0, "CSR0 DATAEND\n"); 400 goto not_complete; 401 } 402 403 if (csr & MUSB2_MASK_CSR0L_SENTSTALL) { 404 /* clear SENTSTALL */ 405 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0); 406 /* get latest status */ 407 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 408 /* update EP0 state */ 409 sc->sc_ep0_busy = 0; 410 } 411 if (csr & MUSB2_MASK_CSR0L_SETUPEND) { 412 /* clear SETUPEND */ 413 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 414 MUSB2_MASK_CSR0L_SETUPEND_CLR); 415 /* get latest status */ 416 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 417 /* update EP0 state */ 418 sc->sc_ep0_busy = 0; 419 } 420 if (sc->sc_ep0_busy) { 421 DPRINTFN(0, "EP0 BUSY\n"); 422 goto not_complete; 423 } 424 if (!(csr & MUSB2_MASK_CSR0L_RXPKTRDY)) { 425 goto not_complete; 426 } 427 /* clear did stall flag */ 428 td->did_stall = 0; 429 /* get the packet byte count */ 430 count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT); 431 432 /* verify data length */ 433 if (count != td->remainder) { 434 DPRINTFN(0, "Invalid SETUP packet " 435 "length, %d bytes\n", count); 436 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 437 MUSB2_MASK_CSR0L_RXPKTRDY_CLR); 438 goto not_complete; 439 } 440 if (count != sizeof(req)) { 441 DPRINTFN(0, "Unsupported SETUP packet " 442 "length, %d bytes\n", count); 443 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 444 MUSB2_MASK_CSR0L_RXPKTRDY_CLR); 445 goto not_complete; 446 } 447 /* receive data */ 448 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 449 MUSB2_REG_EPFIFO(0), (void *)&req, sizeof(req)); 450 451 /* copy data into real buffer */ 452 usbd_copy_in(td->pc, 0, &req, sizeof(req)); 453 454 td->offset = sizeof(req); 455 td->remainder = 0; 456 457 /* set pending command */ 458 sc->sc_ep0_cmd = MUSB2_MASK_CSR0L_RXPKTRDY_CLR; 459 460 /* we need set stall or dataend after this */ 461 sc->sc_ep0_busy = 1; 462 463 /* sneak peek the set address */ 464 if ((req.bmRequestType == UT_WRITE_DEVICE) && 465 (req.bRequest == UR_SET_ADDRESS)) { 466 sc->sc_dv_addr = req.wValue[0] & 0x7F; 467 } else { 468 sc->sc_dv_addr = 0xFF; 469 } 470 471 musbotg_channel_free(sc, td); 472 return (0); /* complete */ 473 474not_complete: 475 /* abort any ongoing transfer */ 476 if (!td->did_stall) { 477 DPRINTFN(4, "stalling\n"); 478 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 479 MUSB2_MASK_CSR0L_SENDSTALL); 480 td->did_stall = 1; 481 } 482 return (1); /* not complete */ 483} 484 485static uint8_t 486musbotg_host_ctrl_setup_tx(struct musbotg_td *td) 487{ 488 struct musbotg_softc *sc; 489 struct usb_device_request req; 490 uint8_t csr, csrh; 491 492 /* get pointer to softc */ 493 sc = MUSBOTG_PC2SC(td->pc); 494 495 if (td->channel == -1) 496 td->channel = musbotg_channel_alloc(sc, td); 497 498 /* EP0 is busy, wait */ 499 if (td->channel == -1) 500 return (1); 501 502 DPRINTFN(1, "ep_no=%d\n", td->channel); 503 504 /* select endpoint 0 */ 505 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); 506 507 /* read out FIFO status */ 508 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 509 DPRINTFN(4, "csr=0x%02x\n", csr); 510 511 /* Not ready yet yet */ 512 if (csr & MUSB2_MASK_CSR0L_TXPKTRDY) 513 return (1); 514 515 /* Failed */ 516 if (csr & (MUSB2_MASK_CSR0L_RXSTALL | 517 MUSB2_MASK_CSR0L_ERROR)) 518 { 519 /* Clear status bit */ 520 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0); 521 DPRINTFN(1, "error bit set, csr=0x%02x\n", csr); 522 td->error = 1; 523 } 524 525 if (csr & MUSB2_MASK_CSR0L_NAKTIMO) { 526 DPRINTFN(1, "NAK timeout\n"); 527 528 if (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY) { 529 csrh = MUSB2_READ_1(sc, MUSB2_REG_TXCSRH); 530 csrh |= MUSB2_MASK_CSR0H_FFLUSH; 531 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, csrh); 532 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 533 if (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY) { 534 csrh = MUSB2_READ_1(sc, MUSB2_REG_TXCSRH); 535 csrh |= MUSB2_MASK_CSR0H_FFLUSH; 536 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, csrh); 537 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 538 } 539 } 540 541 csr &= ~MUSB2_MASK_CSR0L_NAKTIMO; 542 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr); 543 544 td->error = 1; 545 } 546 547 if (td->error) { 548 musbotg_channel_free(sc, td); 549 return (0); 550 } 551 552 /* Fifo is not empty and there is no NAK timeout */ 553 if (csr & MUSB2_MASK_CSR0L_TXPKTRDY) 554 return (1); 555 556 /* check if we are complete */ 557 if (td->remainder == 0) { 558 /* we are complete */ 559 musbotg_channel_free(sc, td); 560 return (0); 561 } 562 563 /* copy data into real buffer */ 564 usbd_copy_out(td->pc, 0, &req, sizeof(req)); 565 566 /* send data */ 567 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 568 MUSB2_REG_EPFIFO(0), (void *)&req, sizeof(req)); 569 570 /* update offset and remainder */ 571 td->offset += sizeof(req); 572 td->remainder -= sizeof(req); 573 574 575 MUSB2_WRITE_1(sc, MUSB2_REG_TXNAKLIMIT, MAX_NAK_TO); 576 MUSB2_WRITE_1(sc, MUSB2_REG_TXFADDR(0), td->dev_addr); 577 MUSB2_WRITE_1(sc, MUSB2_REG_TXHADDR(0), td->haddr); 578 MUSB2_WRITE_1(sc, MUSB2_REG_TXHUBPORT(0), td->hport); 579 MUSB2_WRITE_1(sc, MUSB2_REG_TXTI, td->transfer_type); 580 581 /* write command */ 582 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 583 MUSB2_MASK_CSR0L_TXPKTRDY | 584 MUSB2_MASK_CSR0L_SETUPPKT); 585 586 /* Just to be consistent, not used above */ 587 td->transaction_started = 1; 588 589 return (1); /* in progress */ 590} 591 592/* Control endpoint only data handling functions (RX/TX/SYNC) */ 593 594static uint8_t 595musbotg_dev_ctrl_data_rx(struct musbotg_td *td) 596{ 597 struct usb_page_search buf_res; 598 struct musbotg_softc *sc; 599 uint16_t count; 600 uint8_t csr; 601 uint8_t got_short; 602 603 /* get pointer to softc */ 604 sc = MUSBOTG_PC2SC(td->pc); 605 606 /* select endpoint 0 */ 607 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); 608 609 /* check if a command is pending */ 610 if (sc->sc_ep0_cmd) { 611 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, sc->sc_ep0_cmd); 612 sc->sc_ep0_cmd = 0; 613 } 614 /* read out FIFO status */ 615 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 616 617 DPRINTFN(4, "csr=0x%02x\n", csr); 618 619 got_short = 0; 620 621 if (csr & (MUSB2_MASK_CSR0L_SETUPEND | 622 MUSB2_MASK_CSR0L_SENTSTALL)) { 623 if (td->remainder == 0) { 624 /* 625 * We are actually complete and have 626 * received the next SETUP 627 */ 628 DPRINTFN(4, "faking complete\n"); 629 return (0); /* complete */ 630 } 631 /* 632 * USB Host Aborted the transfer. 633 */ 634 td->error = 1; 635 return (0); /* complete */ 636 } 637 if (!(csr & MUSB2_MASK_CSR0L_RXPKTRDY)) { 638 return (1); /* not complete */ 639 } 640 /* get the packet byte count */ 641 count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT); 642 643 /* verify the packet byte count */ 644 if (count != td->max_frame_size) { 645 if (count < td->max_frame_size) { 646 /* we have a short packet */ 647 td->short_pkt = 1; 648 got_short = 1; 649 } else { 650 /* invalid USB packet */ 651 td->error = 1; 652 return (0); /* we are complete */ 653 } 654 } 655 /* verify the packet byte count */ 656 if (count > td->remainder) { 657 /* invalid USB packet */ 658 td->error = 1; 659 return (0); /* we are complete */ 660 } 661 while (count > 0) { 662 uint32_t temp; 663 664 usbd_get_page(td->pc, td->offset, &buf_res); 665 666 /* get correct length */ 667 if (buf_res.length > count) { 668 buf_res.length = count; 669 } 670 /* check for unaligned memory address */ 671 if (USB_P2U(buf_res.buffer) & 3) { 672 673 temp = count & ~3; 674 675 if (temp) { 676 /* receive data 4 bytes at a time */ 677 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 678 MUSB2_REG_EPFIFO(0), sc->sc_bounce_buf, 679 temp / 4); 680 } 681 temp = count & 3; 682 if (temp) { 683 /* receive data 1 byte at a time */ 684 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 685 MUSB2_REG_EPFIFO(0), 686 (void *)(&sc->sc_bounce_buf[count / 4]), temp); 687 } 688 usbd_copy_in(td->pc, td->offset, 689 sc->sc_bounce_buf, count); 690 691 /* update offset and remainder */ 692 td->offset += count; 693 td->remainder -= count; 694 break; 695 } 696 /* check if we can optimise */ 697 if (buf_res.length >= 4) { 698 699 /* receive data 4 bytes at a time */ 700 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 701 MUSB2_REG_EPFIFO(0), buf_res.buffer, 702 buf_res.length / 4); 703 704 temp = buf_res.length & ~3; 705 706 /* update counters */ 707 count -= temp; 708 td->offset += temp; 709 td->remainder -= temp; 710 continue; 711 } 712 /* receive data */ 713 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 714 MUSB2_REG_EPFIFO(0), buf_res.buffer, buf_res.length); 715 716 /* update counters */ 717 count -= buf_res.length; 718 td->offset += buf_res.length; 719 td->remainder -= buf_res.length; 720 } 721 722 /* check if we are complete */ 723 if ((td->remainder == 0) || got_short) { 724 if (td->short_pkt) { 725 /* we are complete */ 726 sc->sc_ep0_cmd = MUSB2_MASK_CSR0L_RXPKTRDY_CLR; 727 return (0); 728 } 729 /* else need to receive a zero length packet */ 730 } 731 /* write command - need more data */ 732 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 733 MUSB2_MASK_CSR0L_RXPKTRDY_CLR); 734 return (1); /* not complete */ 735} 736 737static uint8_t 738musbotg_dev_ctrl_data_tx(struct musbotg_td *td) 739{ 740 struct usb_page_search buf_res; 741 struct musbotg_softc *sc; 742 uint16_t count; 743 uint8_t csr; 744 745 /* get pointer to softc */ 746 sc = MUSBOTG_PC2SC(td->pc); 747 748 /* select endpoint 0 */ 749 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); 750 751 /* check if a command is pending */ 752 if (sc->sc_ep0_cmd) { 753 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, sc->sc_ep0_cmd); 754 sc->sc_ep0_cmd = 0; 755 } 756 /* read out FIFO status */ 757 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 758 759 DPRINTFN(4, "csr=0x%02x\n", csr); 760 761 if (csr & (MUSB2_MASK_CSR0L_SETUPEND | 762 MUSB2_MASK_CSR0L_SENTSTALL)) { 763 /* 764 * The current transfer was aborted 765 * by the USB Host 766 */ 767 td->error = 1; 768 return (0); /* complete */ 769 } 770 if (csr & MUSB2_MASK_CSR0L_TXPKTRDY) { 771 return (1); /* not complete */ 772 } 773 count = td->max_frame_size; 774 if (td->remainder < count) { 775 /* we have a short packet */ 776 td->short_pkt = 1; 777 count = td->remainder; 778 } 779 while (count > 0) { 780 uint32_t temp; 781 782 usbd_get_page(td->pc, td->offset, &buf_res); 783 784 /* get correct length */ 785 if (buf_res.length > count) { 786 buf_res.length = count; 787 } 788 /* check for unaligned memory address */ 789 if (USB_P2U(buf_res.buffer) & 3) { 790 791 usbd_copy_out(td->pc, td->offset, 792 sc->sc_bounce_buf, count); 793 794 temp = count & ~3; 795 796 if (temp) { 797 /* transmit data 4 bytes at a time */ 798 bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 799 MUSB2_REG_EPFIFO(0), sc->sc_bounce_buf, 800 temp / 4); 801 } 802 temp = count & 3; 803 if (temp) { 804 /* receive data 1 byte at a time */ 805 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 806 MUSB2_REG_EPFIFO(0), 807 ((void *)&sc->sc_bounce_buf[count / 4]), temp); 808 } 809 /* update offset and remainder */ 810 td->offset += count; 811 td->remainder -= count; 812 break; 813 } 814 /* check if we can optimise */ 815 if (buf_res.length >= 4) { 816 817 /* transmit data 4 bytes at a time */ 818 bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 819 MUSB2_REG_EPFIFO(0), buf_res.buffer, 820 buf_res.length / 4); 821 822 temp = buf_res.length & ~3; 823 824 /* update counters */ 825 count -= temp; 826 td->offset += temp; 827 td->remainder -= temp; 828 continue; 829 } 830 /* transmit data */ 831 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 832 MUSB2_REG_EPFIFO(0), buf_res.buffer, buf_res.length); 833 834 /* update counters */ 835 count -= buf_res.length; 836 td->offset += buf_res.length; 837 td->remainder -= buf_res.length; 838 } 839 840 /* check remainder */ 841 if (td->remainder == 0) { 842 if (td->short_pkt) { 843 sc->sc_ep0_cmd = MUSB2_MASK_CSR0L_TXPKTRDY; 844 return (0); /* complete */ 845 } 846 /* else we need to transmit a short packet */ 847 } 848 /* write command */ 849 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 850 MUSB2_MASK_CSR0L_TXPKTRDY); 851 852 return (1); /* not complete */ 853} 854 855static uint8_t 856musbotg_host_ctrl_data_rx(struct musbotg_td *td) 857{ 858 struct usb_page_search buf_res; 859 struct musbotg_softc *sc; 860 uint16_t count; 861 uint8_t csr; 862 uint8_t got_short; 863 864 /* get pointer to softc */ 865 sc = MUSBOTG_PC2SC(td->pc); 866 867 if (td->channel == -1) 868 td->channel = musbotg_channel_alloc(sc, td); 869 870 /* EP0 is busy, wait */ 871 if (td->channel == -1) 872 return (1); 873 874 DPRINTFN(1, "ep_no=%d\n", td->channel); 875 876 /* select endpoint 0 */ 877 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); 878 879 /* read out FIFO status */ 880 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 881 882 DPRINTFN(4, "csr=0x%02x\n", csr); 883 884 got_short = 0; 885 if (!td->transaction_started) { 886 td->transaction_started = 1; 887 888 MUSB2_WRITE_1(sc, MUSB2_REG_RXNAKLIMIT, MAX_NAK_TO); 889 890 MUSB2_WRITE_1(sc, MUSB2_REG_RXFADDR(0), 891 td->dev_addr); 892 MUSB2_WRITE_1(sc, MUSB2_REG_RXHADDR(0), td->haddr); 893 MUSB2_WRITE_1(sc, MUSB2_REG_RXHUBPORT(0), td->hport); 894 MUSB2_WRITE_1(sc, MUSB2_REG_RXTI, td->transfer_type); 895 896 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 897 MUSB2_MASK_CSR0L_REQPKT); 898 899 return (1); 900 } 901 902 if (csr & MUSB2_MASK_CSR0L_NAKTIMO) { 903 csr &= ~MUSB2_MASK_CSR0L_REQPKT; 904 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr); 905 906 csr &= ~MUSB2_MASK_CSR0L_NAKTIMO; 907 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr); 908 909 td->error = 1; 910 } 911 912 /* Failed */ 913 if (csr & (MUSB2_MASK_CSR0L_RXSTALL | 914 MUSB2_MASK_CSR0L_ERROR)) 915 { 916 /* Clear status bit */ 917 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0); 918 DPRINTFN(1, "error bit set, csr=0x%02x\n", csr); 919 td->error = 1; 920 } 921 922 if (td->error) { 923 musbotg_channel_free(sc, td); 924 return (0); /* we are complete */ 925 } 926 927 if (!(csr & MUSB2_MASK_CSR0L_RXPKTRDY)) 928 return (1); /* not yet */ 929 930 /* get the packet byte count */ 931 count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT); 932 933 /* verify the packet byte count */ 934 if (count != td->max_frame_size) { 935 if (count < td->max_frame_size) { 936 /* we have a short packet */ 937 td->short_pkt = 1; 938 got_short = 1; 939 } else { 940 /* invalid USB packet */ 941 td->error = 1; 942 musbotg_channel_free(sc, td); 943 return (0); /* we are complete */ 944 } 945 } 946 /* verify the packet byte count */ 947 if (count > td->remainder) { 948 /* invalid USB packet */ 949 td->error = 1; 950 musbotg_channel_free(sc, td); 951 return (0); /* we are complete */ 952 } 953 while (count > 0) { 954 uint32_t temp; 955 956 usbd_get_page(td->pc, td->offset, &buf_res); 957 958 /* get correct length */ 959 if (buf_res.length > count) { 960 buf_res.length = count; 961 } 962 /* check for unaligned memory address */ 963 if (USB_P2U(buf_res.buffer) & 3) { 964 965 temp = count & ~3; 966 967 if (temp) { 968 /* receive data 4 bytes at a time */ 969 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 970 MUSB2_REG_EPFIFO(0), sc->sc_bounce_buf, 971 temp / 4); 972 } 973 temp = count & 3; 974 if (temp) { 975 /* receive data 1 byte at a time */ 976 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 977 MUSB2_REG_EPFIFO(0), 978 (void *)(&sc->sc_bounce_buf[count / 4]), temp); 979 } 980 usbd_copy_in(td->pc, td->offset, 981 sc->sc_bounce_buf, count); 982 983 /* update offset and remainder */ 984 td->offset += count; 985 td->remainder -= count; 986 break; 987 } 988 /* check if we can optimise */ 989 if (buf_res.length >= 4) { 990 991 /* receive data 4 bytes at a time */ 992 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 993 MUSB2_REG_EPFIFO(0), buf_res.buffer, 994 buf_res.length / 4); 995 996 temp = buf_res.length & ~3; 997 998 /* update counters */ 999 count -= temp; 1000 td->offset += temp; 1001 td->remainder -= temp; 1002 continue; 1003 } 1004 /* receive data */ 1005 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 1006 MUSB2_REG_EPFIFO(0), buf_res.buffer, buf_res.length); 1007 1008 /* update counters */ 1009 count -= buf_res.length; 1010 td->offset += buf_res.length; 1011 td->remainder -= buf_res.length; 1012 } 1013 1014 csr &= ~MUSB2_MASK_CSR0L_RXPKTRDY; 1015 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr); 1016 1017 /* check if we are complete */ 1018 if ((td->remainder == 0) || got_short) { 1019 if (td->short_pkt) { 1020 /* we are complete */ 1021 1022 musbotg_channel_free(sc, td); 1023 return (0); 1024 } 1025 /* else need to receive a zero length packet */ 1026 } 1027 1028 td->transaction_started = 1; 1029 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 1030 MUSB2_MASK_CSR0L_REQPKT); 1031 1032 return (1); /* not complete */ 1033} 1034 1035static uint8_t 1036musbotg_host_ctrl_data_tx(struct musbotg_td *td) 1037{ 1038 struct usb_page_search buf_res; 1039 struct musbotg_softc *sc; 1040 uint16_t count; 1041 uint8_t csr, csrh; 1042 1043 /* get pointer to softc */ 1044 sc = MUSBOTG_PC2SC(td->pc); 1045 1046 if (td->channel == -1) 1047 td->channel = musbotg_channel_alloc(sc, td); 1048 1049 /* No free EPs */ 1050 if (td->channel == -1) 1051 return (1); 1052 1053 DPRINTFN(1, "ep_no=%d\n", td->channel); 1054 1055 /* select endpoint */ 1056 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); 1057 1058 /* read out FIFO status */ 1059 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 1060 DPRINTFN(4, "csr=0x%02x\n", csr); 1061 1062 if (csr & (MUSB2_MASK_CSR0L_RXSTALL | 1063 MUSB2_MASK_CSR0L_ERROR)) { 1064 /* clear status bits */ 1065 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0); 1066 td->error = 1; 1067 } 1068 1069 if (csr & MUSB2_MASK_CSR0L_NAKTIMO ) { 1070 1071 if (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY) { 1072 csrh = MUSB2_READ_1(sc, MUSB2_REG_TXCSRH); 1073 csrh |= MUSB2_MASK_CSR0H_FFLUSH; 1074 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, csrh); 1075 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 1076 if (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY) { 1077 csrh = MUSB2_READ_1(sc, MUSB2_REG_TXCSRH); 1078 csrh |= MUSB2_MASK_CSR0H_FFLUSH; 1079 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, csrh); 1080 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 1081 } 1082 } 1083 1084 csr &= ~MUSB2_MASK_CSR0L_NAKTIMO; 1085 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr); 1086 1087 td->error = 1; 1088 } 1089 1090 1091 if (td->error) { 1092 musbotg_channel_free(sc, td); 1093 return (0); /* complete */ 1094 } 1095 1096 /* 1097 * Wait while FIFO is empty. 1098 * Do not flush it because it will cause transactions 1099 * with size more then packet size. It might upset 1100 * some devices 1101 */ 1102 if (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY) 1103 return (1); 1104 1105 /* Packet still being processed */ 1106 if (csr & MUSB2_MASK_CSR0L_TXPKTRDY) 1107 return (1); 1108 1109 if (td->transaction_started) { 1110 /* check remainder */ 1111 if (td->remainder == 0) { 1112 if (td->short_pkt) { 1113 musbotg_channel_free(sc, td); 1114 return (0); /* complete */ 1115 } 1116 /* else we need to transmit a short packet */ 1117 } 1118 1119 /* We're not complete - more transactions required */ 1120 td->transaction_started = 0; 1121 } 1122 1123 /* check for short packet */ 1124 count = td->max_frame_size; 1125 if (td->remainder < count) { 1126 /* we have a short packet */ 1127 td->short_pkt = 1; 1128 count = td->remainder; 1129 } 1130 1131 while (count > 0) { 1132 uint32_t temp; 1133 1134 usbd_get_page(td->pc, td->offset, &buf_res); 1135 1136 /* get correct length */ 1137 if (buf_res.length > count) { 1138 buf_res.length = count; 1139 } 1140 /* check for unaligned memory address */ 1141 if (USB_P2U(buf_res.buffer) & 3) { 1142 1143 usbd_copy_out(td->pc, td->offset, 1144 sc->sc_bounce_buf, count); 1145 1146 temp = count & ~3; 1147 1148 if (temp) { 1149 /* transmit data 4 bytes at a time */ 1150 bus_space_write_multi_4(sc->sc_io_tag, 1151 sc->sc_io_hdl, MUSB2_REG_EPFIFO(0), 1152 sc->sc_bounce_buf, temp / 4); 1153 } 1154 temp = count & 3; 1155 if (temp) { 1156 /* receive data 1 byte at a time */ 1157 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 1158 MUSB2_REG_EPFIFO(0), 1159 ((void *)&sc->sc_bounce_buf[count / 4]), temp); 1160 } 1161 /* update offset and remainder */ 1162 td->offset += count; 1163 td->remainder -= count; 1164 break; 1165 } 1166 /* check if we can optimise */ 1167 if (buf_res.length >= 4) { 1168 1169 /* transmit data 4 bytes at a time */ 1170 bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 1171 MUSB2_REG_EPFIFO(0), buf_res.buffer, 1172 buf_res.length / 4); 1173 1174 temp = buf_res.length & ~3; 1175 1176 /* update counters */ 1177 count -= temp; 1178 td->offset += temp; 1179 td->remainder -= temp; 1180 continue; 1181 } 1182 /* transmit data */ 1183 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 1184 MUSB2_REG_EPFIFO(0), buf_res.buffer, 1185 buf_res.length); 1186 1187 /* update counters */ 1188 count -= buf_res.length; 1189 td->offset += buf_res.length; 1190 td->remainder -= buf_res.length; 1191 } 1192 1193 /* Function address */ 1194 MUSB2_WRITE_1(sc, MUSB2_REG_TXFADDR(0), td->dev_addr); 1195 MUSB2_WRITE_1(sc, MUSB2_REG_TXHADDR(0), td->haddr); 1196 MUSB2_WRITE_1(sc, MUSB2_REG_TXHUBPORT(0), td->hport); 1197 MUSB2_WRITE_1(sc, MUSB2_REG_TXTI, td->transfer_type); 1198 1199 /* TX NAK timeout */ 1200 MUSB2_WRITE_1(sc, MUSB2_REG_TXNAKLIMIT, MAX_NAK_TO); 1201 1202 /* write command */ 1203 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 1204 MUSB2_MASK_CSR0L_TXPKTRDY); 1205 1206 td->transaction_started = 1; 1207 1208 return (1); /* not complete */ 1209} 1210 1211static uint8_t 1212musbotg_dev_ctrl_status(struct musbotg_td *td) 1213{ 1214 struct musbotg_softc *sc; 1215 uint8_t csr; 1216 1217 /* get pointer to softc */ 1218 sc = MUSBOTG_PC2SC(td->pc); 1219 1220 /* select endpoint 0 */ 1221 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); 1222 1223 if (sc->sc_ep0_busy) { 1224 sc->sc_ep0_busy = 0; 1225 sc->sc_ep0_cmd |= MUSB2_MASK_CSR0L_DATAEND; 1226 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, sc->sc_ep0_cmd); 1227 sc->sc_ep0_cmd = 0; 1228 } 1229 /* read out FIFO status */ 1230 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 1231 1232 DPRINTFN(4, "csr=0x%02x\n", csr); 1233 1234 if (csr & MUSB2_MASK_CSR0L_DATAEND) { 1235 /* wait for interrupt */ 1236 return (1); /* not complete */ 1237 } 1238 if (sc->sc_dv_addr != 0xFF) { 1239 /* write function address */ 1240 musbotg_set_address(sc, sc->sc_dv_addr); 1241 } 1242 1243 musbotg_channel_free(sc, td); 1244 return (0); /* complete */ 1245} 1246 1247static uint8_t 1248musbotg_host_ctrl_status_rx(struct musbotg_td *td) 1249{ 1250 struct musbotg_softc *sc; 1251 uint8_t csr, csrh; 1252 1253 /* get pointer to softc */ 1254 sc = MUSBOTG_PC2SC(td->pc); 1255 1256 if (td->channel == -1) 1257 td->channel = musbotg_channel_alloc(sc, td); 1258 1259 /* EP0 is busy, wait */ 1260 if (td->channel == -1) 1261 return (1); 1262 1263 DPRINTFN(1, "ep_no=%d\n", td->channel); 1264 1265 /* select endpoint 0 */ 1266 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); 1267 1268 if (!td->transaction_started) { 1269 MUSB2_WRITE_1(sc, MUSB2_REG_RXFADDR(0), 1270 td->dev_addr); 1271 1272 MUSB2_WRITE_1(sc, MUSB2_REG_RXHADDR(0), td->haddr); 1273 MUSB2_WRITE_1(sc, MUSB2_REG_RXHUBPORT(0), td->hport); 1274 MUSB2_WRITE_1(sc, MUSB2_REG_RXTI, td->transfer_type); 1275 1276 /* RX NAK timeout */ 1277 MUSB2_WRITE_1(sc, MUSB2_REG_RXNAKLIMIT, MAX_NAK_TO); 1278 1279 td->transaction_started = 1; 1280 1281 /* Disable PING */ 1282 csrh = MUSB2_READ_1(sc, MUSB2_REG_RXCSRH); 1283 csrh |= MUSB2_MASK_CSR0H_PING_DIS; 1284 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH, csrh); 1285 1286 /* write command */ 1287 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 1288 MUSB2_MASK_CSR0L_STATUSPKT | 1289 MUSB2_MASK_CSR0L_REQPKT); 1290 1291 return (1); /* Just started */ 1292 1293 } 1294 1295 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 1296 1297 DPRINTFN(4, "IN STATUS csr=0x%02x\n", csr); 1298 1299 if (csr & MUSB2_MASK_CSR0L_RXPKTRDY) { 1300 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 1301 MUSB2_MASK_CSR0L_RXPKTRDY_CLR); 1302 musbotg_channel_free(sc, td); 1303 return (0); /* complete */ 1304 } 1305 1306 if (csr & MUSB2_MASK_CSR0L_NAKTIMO) { 1307 csr &= ~ (MUSB2_MASK_CSR0L_STATUSPKT | 1308 MUSB2_MASK_CSR0L_REQPKT); 1309 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr); 1310 1311 csr &= ~MUSB2_MASK_CSR0L_NAKTIMO; 1312 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr); 1313 td->error = 1; 1314 } 1315 1316 /* Failed */ 1317 if (csr & (MUSB2_MASK_CSR0L_RXSTALL | 1318 MUSB2_MASK_CSR0L_ERROR)) 1319 { 1320 /* Clear status bit */ 1321 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0); 1322 DPRINTFN(1, "error bit set, csr=0x%02x\n", csr); 1323 td->error = 1; 1324 } 1325 1326 if (td->error) { 1327 musbotg_channel_free(sc, td); 1328 return (0); 1329 } 1330 1331 return (1); /* Not ready yet */ 1332} 1333 1334static uint8_t 1335musbotg_host_ctrl_status_tx(struct musbotg_td *td) 1336{ 1337 struct musbotg_softc *sc; 1338 uint8_t csr; 1339 1340 /* get pointer to softc */ 1341 sc = MUSBOTG_PC2SC(td->pc); 1342 1343 if (td->channel == -1) 1344 td->channel = musbotg_channel_alloc(sc, td); 1345 1346 /* EP0 is busy, wait */ 1347 if (td->channel == -1) 1348 return (1); 1349 1350 DPRINTFN(1, "ep_no=%d/%d [%d@%d.%d/%02x]\n", td->channel, td->transaction_started, 1351 td->dev_addr,td->haddr,td->hport, td->transfer_type); 1352 1353 /* select endpoint 0 */ 1354 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); 1355 1356 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 1357 DPRINTFN(4, "csr=0x%02x\n", csr); 1358 1359 /* Not yet */ 1360 if (csr & MUSB2_MASK_CSR0L_TXPKTRDY) 1361 return (1); 1362 1363 /* Failed */ 1364 if (csr & (MUSB2_MASK_CSR0L_RXSTALL | 1365 MUSB2_MASK_CSR0L_ERROR)) 1366 { 1367 /* Clear status bit */ 1368 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0); 1369 DPRINTFN(1, "error bit set, csr=0x%02x\n", csr); 1370 td->error = 1; 1371 musbotg_channel_free(sc, td); 1372 return (0); /* complete */ 1373 } 1374 1375 if (td->transaction_started) { 1376 musbotg_channel_free(sc, td); 1377 return (0); /* complete */ 1378 } 1379 1380 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH, MUSB2_MASK_CSR0H_PING_DIS); 1381 1382 MUSB2_WRITE_1(sc, MUSB2_REG_TXFADDR(0), td->dev_addr); 1383 MUSB2_WRITE_1(sc, MUSB2_REG_TXHADDR(0), td->haddr); 1384 MUSB2_WRITE_1(sc, MUSB2_REG_TXHUBPORT(0), td->hport); 1385 MUSB2_WRITE_1(sc, MUSB2_REG_TXTI, td->transfer_type); 1386 1387 /* TX NAK timeout */ 1388 MUSB2_WRITE_1(sc, MUSB2_REG_TXNAKLIMIT, MAX_NAK_TO); 1389 1390 td->transaction_started = 1; 1391 1392 /* write command */ 1393 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 1394 MUSB2_MASK_CSR0L_STATUSPKT | 1395 MUSB2_MASK_CSR0L_TXPKTRDY); 1396 1397 return (1); /* wait for interrupt */ 1398} 1399 1400static uint8_t 1401musbotg_dev_data_rx(struct musbotg_td *td) 1402{ 1403 struct usb_page_search buf_res; 1404 struct musbotg_softc *sc; 1405 uint16_t count; 1406 uint8_t csr; 1407 uint8_t to; 1408 uint8_t got_short; 1409 1410 to = 8; /* don't loop forever! */ 1411 got_short = 0; 1412 1413 /* get pointer to softc */ 1414 sc = MUSBOTG_PC2SC(td->pc); 1415 1416 if (td->channel == -1) 1417 td->channel = musbotg_channel_alloc(sc, td); 1418 1419 /* EP0 is busy, wait */ 1420 if (td->channel == -1) 1421 return (1); 1422 1423 /* select endpoint */ 1424 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, td->channel); 1425 1426repeat: 1427 /* read out FIFO status */ 1428 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL); 1429 1430 DPRINTFN(4, "csr=0x%02x\n", csr); 1431 1432 /* clear overrun */ 1433 if (csr & MUSB2_MASK_CSRL_RXOVERRUN) { 1434 /* make sure we don't clear "RXPKTRDY" */ 1435 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 1436 MUSB2_MASK_CSRL_RXPKTRDY); 1437 } 1438 1439 /* check status */ 1440 if (!(csr & MUSB2_MASK_CSRL_RXPKTRDY)) 1441 return (1); /* not complete */ 1442 1443 /* get the packet byte count */ 1444 count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT); 1445 1446 DPRINTFN(4, "count=0x%04x\n", count); 1447 1448 /* 1449 * Check for short or invalid packet: 1450 */ 1451 if (count != td->max_frame_size) { 1452 if (count < td->max_frame_size) { 1453 /* we have a short packet */ 1454 td->short_pkt = 1; 1455 got_short = 1; 1456 } else { 1457 /* invalid USB packet */ 1458 td->error = 1; 1459 musbotg_channel_free(sc, td); 1460 return (0); /* we are complete */ 1461 } 1462 } 1463 /* verify the packet byte count */ 1464 if (count > td->remainder) { 1465 /* invalid USB packet */ 1466 td->error = 1; 1467 musbotg_channel_free(sc, td); 1468 return (0); /* we are complete */ 1469 } 1470 while (count > 0) { 1471 uint32_t temp; 1472 1473 usbd_get_page(td->pc, td->offset, &buf_res); 1474 1475 /* get correct length */ 1476 if (buf_res.length > count) { 1477 buf_res.length = count; 1478 } 1479 /* check for unaligned memory address */ 1480 if (USB_P2U(buf_res.buffer) & 3) { 1481 1482 temp = count & ~3; 1483 1484 if (temp) { 1485 /* receive data 4 bytes at a time */ 1486 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 1487 MUSB2_REG_EPFIFO(td->channel), sc->sc_bounce_buf, 1488 temp / 4); 1489 } 1490 temp = count & 3; 1491 if (temp) { 1492 /* receive data 1 byte at a time */ 1493 bus_space_read_multi_1(sc->sc_io_tag, 1494 sc->sc_io_hdl, MUSB2_REG_EPFIFO(td->channel), 1495 ((void *)&sc->sc_bounce_buf[count / 4]), temp); 1496 } 1497 usbd_copy_in(td->pc, td->offset, 1498 sc->sc_bounce_buf, count); 1499 1500 /* update offset and remainder */ 1501 td->offset += count; 1502 td->remainder -= count; 1503 break; 1504 } 1505 /* check if we can optimise */ 1506 if (buf_res.length >= 4) { 1507 1508 /* receive data 4 bytes at a time */ 1509 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 1510 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer, 1511 buf_res.length / 4); 1512 1513 temp = buf_res.length & ~3; 1514 1515 /* update counters */ 1516 count -= temp; 1517 td->offset += temp; 1518 td->remainder -= temp; 1519 continue; 1520 } 1521 /* receive data */ 1522 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 1523 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer, 1524 buf_res.length); 1525 1526 /* update counters */ 1527 count -= buf_res.length; 1528 td->offset += buf_res.length; 1529 td->remainder -= buf_res.length; 1530 } 1531 1532 /* clear status bits */ 1533 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 0); 1534 1535 /* check if we are complete */ 1536 if ((td->remainder == 0) || got_short) { 1537 if (td->short_pkt) { 1538 /* we are complete */ 1539 musbotg_channel_free(sc, td); 1540 return (0); 1541 } 1542 /* else need to receive a zero length packet */ 1543 } 1544 if (--to) { 1545 goto repeat; 1546 } 1547 return (1); /* not complete */ 1548} 1549 1550static uint8_t 1551musbotg_dev_data_tx(struct musbotg_td *td) 1552{ 1553 struct usb_page_search buf_res; 1554 struct musbotg_softc *sc; 1555 uint16_t count; 1556 uint8_t csr; 1557 uint8_t to; 1558 1559 to = 8; /* don't loop forever! */ 1560 1561 /* get pointer to softc */ 1562 sc = MUSBOTG_PC2SC(td->pc); 1563 1564 if (td->channel == -1) 1565 td->channel = musbotg_channel_alloc(sc, td); 1566 1567 /* EP0 is busy, wait */ 1568 if (td->channel == -1) 1569 return (1); 1570 1571 /* select endpoint */ 1572 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, td->channel); 1573 1574repeat: 1575 1576 /* read out FIFO status */ 1577 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 1578 1579 DPRINTFN(4, "csr=0x%02x\n", csr); 1580 1581 if (csr & (MUSB2_MASK_CSRL_TXINCOMP | 1582 MUSB2_MASK_CSRL_TXUNDERRUN)) { 1583 /* clear status bits */ 1584 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0); 1585 } 1586 if (csr & MUSB2_MASK_CSRL_TXPKTRDY) { 1587 return (1); /* not complete */ 1588 } 1589 /* check for short packet */ 1590 count = td->max_frame_size; 1591 if (td->remainder < count) { 1592 /* we have a short packet */ 1593 td->short_pkt = 1; 1594 count = td->remainder; 1595 } 1596 while (count > 0) { 1597 uint32_t temp; 1598 1599 usbd_get_page(td->pc, td->offset, &buf_res); 1600 1601 /* get correct length */ 1602 if (buf_res.length > count) { 1603 buf_res.length = count; 1604 } 1605 /* check for unaligned memory address */ 1606 if (USB_P2U(buf_res.buffer) & 3) { 1607 1608 usbd_copy_out(td->pc, td->offset, 1609 sc->sc_bounce_buf, count); 1610 1611 temp = count & ~3; 1612 1613 if (temp) { 1614 /* transmit data 4 bytes at a time */ 1615 bus_space_write_multi_4(sc->sc_io_tag, 1616 sc->sc_io_hdl, MUSB2_REG_EPFIFO(td->channel), 1617 sc->sc_bounce_buf, temp / 4); 1618 } 1619 temp = count & 3; 1620 if (temp) { 1621 /* receive data 1 byte at a time */ 1622 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 1623 MUSB2_REG_EPFIFO(td->channel), 1624 ((void *)&sc->sc_bounce_buf[count / 4]), temp); 1625 } 1626 /* update offset and remainder */ 1627 td->offset += count; 1628 td->remainder -= count; 1629 break; 1630 } 1631 /* check if we can optimise */ 1632 if (buf_res.length >= 4) { 1633 1634 /* transmit data 4 bytes at a time */ 1635 bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 1636 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer, 1637 buf_res.length / 4); 1638 1639 temp = buf_res.length & ~3; 1640 1641 /* update counters */ 1642 count -= temp; 1643 td->offset += temp; 1644 td->remainder -= temp; 1645 continue; 1646 } 1647 /* transmit data */ 1648 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 1649 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer, 1650 buf_res.length); 1651 1652 /* update counters */ 1653 count -= buf_res.length; 1654 td->offset += buf_res.length; 1655 td->remainder -= buf_res.length; 1656 } 1657 1658 /* Max packet size */ 1659 MUSB2_WRITE_2(sc, MUSB2_REG_TXMAXP, td->reg_max_packet); 1660 1661 /* write command */ 1662 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 1663 MUSB2_MASK_CSRL_TXPKTRDY); 1664 1665 /* check remainder */ 1666 if (td->remainder == 0) { 1667 if (td->short_pkt) { 1668 musbotg_channel_free(sc, td); 1669 return (0); /* complete */ 1670 } 1671 /* else we need to transmit a short packet */ 1672 } 1673 if (--to) { 1674 goto repeat; 1675 } 1676 return (1); /* not complete */ 1677} 1678 1679static uint8_t 1680musbotg_host_data_rx(struct musbotg_td *td) 1681{ 1682 struct usb_page_search buf_res; 1683 struct musbotg_softc *sc; 1684 uint16_t count; 1685 uint8_t csr, csrh; 1686 uint8_t to; 1687 uint8_t got_short; 1688 1689 /* get pointer to softc */ 1690 sc = MUSBOTG_PC2SC(td->pc); 1691 1692 if (td->channel == -1) 1693 td->channel = musbotg_channel_alloc(sc, td); 1694 1695 /* No free EPs */ 1696 if (td->channel == -1) 1697 return (1); 1698 1699 DPRINTFN(1, "ep_no=%d\n", td->channel); 1700 1701 to = 8; /* don't loop forever! */ 1702 got_short = 0; 1703 1704 /* select endpoint */ 1705 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, td->channel); 1706 1707repeat: 1708 /* read out FIFO status */ 1709 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL); 1710 DPRINTFN(4, "csr=0x%02x\n", csr); 1711 1712 if (!td->transaction_started) { 1713 /* Function address */ 1714 MUSB2_WRITE_1(sc, MUSB2_REG_RXFADDR(td->channel), 1715 td->dev_addr); 1716 1717 /* SPLIT transaction */ 1718 MUSB2_WRITE_1(sc, MUSB2_REG_RXHADDR(td->channel), 1719 td->haddr); 1720 MUSB2_WRITE_1(sc, MUSB2_REG_RXHUBPORT(td->channel), 1721 td->hport); 1722 1723 /* RX NAK timeout */ 1724 if (td->transfer_type & MUSB2_MASK_TI_PROTO_ISOC) 1725 MUSB2_WRITE_1(sc, MUSB2_REG_RXNAKLIMIT, 0); 1726 else 1727 MUSB2_WRITE_1(sc, MUSB2_REG_RXNAKLIMIT, MAX_NAK_TO); 1728 1729 /* Protocol, speed, device endpoint */ 1730 MUSB2_WRITE_1(sc, MUSB2_REG_RXTI, td->transfer_type); 1731 1732 /* Max packet size */ 1733 MUSB2_WRITE_2(sc, MUSB2_REG_RXMAXP, td->reg_max_packet); 1734 1735 /* Data Toggle */ 1736 csrh = MUSB2_READ_1(sc, MUSB2_REG_RXCSRH); 1737 DPRINTFN(4, "csrh=0x%02x\n", csrh); 1738 1739 csrh |= MUSB2_MASK_CSRH_RXDT_WREN; 1740 if (td->toggle) 1741 csrh |= MUSB2_MASK_CSRH_RXDT_VAL; 1742 else 1743 csrh &= ~MUSB2_MASK_CSRH_RXDT_VAL; 1744 1745 /* Set data toggle */ 1746 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH, csrh); 1747 1748 /* write command */ 1749 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 1750 MUSB2_MASK_CSRL_RXREQPKT); 1751 1752 td->transaction_started = 1; 1753 return (1); 1754 } 1755 1756 /* clear NAK timeout */ 1757 if (csr & MUSB2_MASK_CSRL_RXNAKTO) { 1758 DPRINTFN(4, "NAK Timeout\n"); 1759 if (csr & MUSB2_MASK_CSRL_RXREQPKT) { 1760 csr &= ~MUSB2_MASK_CSRL_RXREQPKT; 1761 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, csr); 1762 1763 csr &= ~MUSB2_MASK_CSRL_RXNAKTO; 1764 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, csr); 1765 } 1766 1767 td->error = 1; 1768 } 1769 1770 if (csr & MUSB2_MASK_CSRL_RXERROR) { 1771 DPRINTFN(4, "RXERROR\n"); 1772 td->error = 1; 1773 } 1774 1775 if (csr & MUSB2_MASK_CSRL_RXSTALL) { 1776 DPRINTFN(4, "RXSTALL\n"); 1777 td->error = 1; 1778 } 1779 1780 if (td->error) { 1781 musbotg_channel_free(sc, td); 1782 return (0); /* we are complete */ 1783 } 1784 1785 if (!(csr & MUSB2_MASK_CSRL_RXPKTRDY)) { 1786 /* No data available yet */ 1787 return (1); 1788 } 1789 1790 td->toggle ^= 1; 1791 /* get the packet byte count */ 1792 count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT); 1793 DPRINTFN(4, "count=0x%04x\n", count); 1794 1795 /* 1796 * Check for short or invalid packet: 1797 */ 1798 if (count != td->max_frame_size) { 1799 if (count < td->max_frame_size) { 1800 /* we have a short packet */ 1801 td->short_pkt = 1; 1802 got_short = 1; 1803 } else { 1804 /* invalid USB packet */ 1805 td->error = 1; 1806 musbotg_channel_free(sc, td); 1807 return (0); /* we are complete */ 1808 } 1809 } 1810 1811 /* verify the packet byte count */ 1812 if (count > td->remainder) { 1813 /* invalid USB packet */ 1814 td->error = 1; 1815 musbotg_channel_free(sc, td); 1816 return (0); /* we are complete */ 1817 } 1818 1819 while (count > 0) { 1820 uint32_t temp; 1821 1822 usbd_get_page(td->pc, td->offset, &buf_res); 1823 1824 /* get correct length */ 1825 if (buf_res.length > count) { 1826 buf_res.length = count; 1827 } 1828 /* check for unaligned memory address */ 1829 if (USB_P2U(buf_res.buffer) & 3) { 1830 1831 temp = count & ~3; 1832 1833 if (temp) { 1834 /* receive data 4 bytes at a time */ 1835 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 1836 MUSB2_REG_EPFIFO(td->channel), sc->sc_bounce_buf, 1837 temp / 4); 1838 } 1839 temp = count & 3; 1840 if (temp) { 1841 /* receive data 1 byte at a time */ 1842 bus_space_read_multi_1(sc->sc_io_tag, 1843 sc->sc_io_hdl, MUSB2_REG_EPFIFO(td->channel), 1844 ((void *)&sc->sc_bounce_buf[count / 4]), temp); 1845 } 1846 usbd_copy_in(td->pc, td->offset, 1847 sc->sc_bounce_buf, count); 1848 1849 /* update offset and remainder */ 1850 td->offset += count; 1851 td->remainder -= count; 1852 break; 1853 } 1854 /* check if we can optimise */ 1855 if (buf_res.length >= 4) { 1856 1857 /* receive data 4 bytes at a time */ 1858 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 1859 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer, 1860 buf_res.length / 4); 1861 1862 temp = buf_res.length & ~3; 1863 1864 /* update counters */ 1865 count -= temp; 1866 td->offset += temp; 1867 td->remainder -= temp; 1868 continue; 1869 } 1870 /* receive data */ 1871 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 1872 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer, 1873 buf_res.length); 1874 1875 /* update counters */ 1876 count -= buf_res.length; 1877 td->offset += buf_res.length; 1878 td->remainder -= buf_res.length; 1879 } 1880 1881 /* clear status bits */ 1882 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 0); 1883 1884 /* check if we are complete */ 1885 if ((td->remainder == 0) || got_short) { 1886 if (td->short_pkt) { 1887 /* we are complete */ 1888 musbotg_channel_free(sc, td); 1889 return (0); 1890 } 1891 /* else need to receive a zero length packet */ 1892 } 1893 1894 /* Reset transaction state and restart */ 1895 td->transaction_started = 0; 1896 1897 if (--to) 1898 goto repeat; 1899 1900 return (1); /* not complete */ 1901} 1902 1903static uint8_t 1904musbotg_host_data_tx(struct musbotg_td *td) 1905{ 1906 struct usb_page_search buf_res; 1907 struct musbotg_softc *sc; 1908 uint16_t count; 1909 uint8_t csr, csrh; 1910 1911 /* get pointer to softc */ 1912 sc = MUSBOTG_PC2SC(td->pc); 1913 1914 if (td->channel == -1) 1915 td->channel = musbotg_channel_alloc(sc, td); 1916 1917 /* No free EPs */ 1918 if (td->channel == -1) 1919 return (1); 1920 1921 DPRINTFN(1, "ep_no=%d\n", td->channel); 1922 1923 /* select endpoint */ 1924 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, td->channel); 1925 1926 /* read out FIFO status */ 1927 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 1928 DPRINTFN(4, "csr=0x%02x\n", csr); 1929 1930 if (csr & (MUSB2_MASK_CSRL_TXSTALLED | 1931 MUSB2_MASK_CSRL_TXERROR)) { 1932 /* clear status bits */ 1933 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0); 1934 td->error = 1; 1935 musbotg_channel_free(sc, td); 1936 return (0); /* complete */ 1937 } 1938 1939 if (csr & MUSB2_MASK_CSRL_TXNAKTO) { 1940 /* 1941 * Flush TX FIFO before clearing NAK TO 1942 */ 1943 if (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) { 1944 csr |= MUSB2_MASK_CSRL_TXFFLUSH; 1945 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr); 1946 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 1947 if (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) { 1948 csr |= MUSB2_MASK_CSRL_TXFFLUSH; 1949 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr); 1950 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 1951 } 1952 } 1953 1954 csr &= ~MUSB2_MASK_CSRL_TXNAKTO; 1955 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr); 1956 1957 td->error = 1; 1958 musbotg_channel_free(sc, td); 1959 return (0); /* complete */ 1960 } 1961 1962 /* 1963 * Wait while FIFO is empty. 1964 * Do not flush it because it will cause transactions 1965 * with size more then packet size. It might upset 1966 * some devices 1967 */ 1968 if (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) 1969 return (1); 1970 1971 /* Packet still being processed */ 1972 if (csr & MUSB2_MASK_CSRL_TXPKTRDY) 1973 return (1); 1974 1975 if (td->transaction_started) { 1976 /* check remainder */ 1977 if (td->remainder == 0) { 1978 if (td->short_pkt) { 1979 musbotg_channel_free(sc, td); 1980 return (0); /* complete */ 1981 } 1982 /* else we need to transmit a short packet */ 1983 } 1984 1985 /* We're not complete - more transactions required */ 1986 td->transaction_started = 0; 1987 } 1988 1989 /* check for short packet */ 1990 count = td->max_frame_size; 1991 if (td->remainder < count) { 1992 /* we have a short packet */ 1993 td->short_pkt = 1; 1994 count = td->remainder; 1995 } 1996 1997 while (count > 0) { 1998 uint32_t temp; 1999 2000 usbd_get_page(td->pc, td->offset, &buf_res); 2001 2002 /* get correct length */ 2003 if (buf_res.length > count) { 2004 buf_res.length = count; 2005 } 2006 /* check for unaligned memory address */ 2007 if (USB_P2U(buf_res.buffer) & 3) { 2008 2009 usbd_copy_out(td->pc, td->offset, 2010 sc->sc_bounce_buf, count); 2011 2012 temp = count & ~3; 2013 2014 if (temp) { 2015 /* transmit data 4 bytes at a time */ 2016 bus_space_write_multi_4(sc->sc_io_tag, 2017 sc->sc_io_hdl, MUSB2_REG_EPFIFO(td->channel), 2018 sc->sc_bounce_buf, temp / 4); 2019 } 2020 temp = count & 3; 2021 if (temp) { 2022 /* receive data 1 byte at a time */ 2023 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 2024 MUSB2_REG_EPFIFO(td->channel), 2025 ((void *)&sc->sc_bounce_buf[count / 4]), temp); 2026 } 2027 /* update offset and remainder */ 2028 td->offset += count; 2029 td->remainder -= count; 2030 break; 2031 } 2032 /* check if we can optimise */ 2033 if (buf_res.length >= 4) { 2034 2035 /* transmit data 4 bytes at a time */ 2036 bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 2037 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer, 2038 buf_res.length / 4); 2039 2040 temp = buf_res.length & ~3; 2041 2042 /* update counters */ 2043 count -= temp; 2044 td->offset += temp; 2045 td->remainder -= temp; 2046 continue; 2047 } 2048 /* transmit data */ 2049 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 2050 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer, 2051 buf_res.length); 2052 2053 /* update counters */ 2054 count -= buf_res.length; 2055 td->offset += buf_res.length; 2056 td->remainder -= buf_res.length; 2057 } 2058 2059 /* Function address */ 2060 MUSB2_WRITE_1(sc, MUSB2_REG_TXFADDR(td->channel), 2061 td->dev_addr); 2062 2063 /* SPLIT transaction */ 2064 MUSB2_WRITE_1(sc, MUSB2_REG_TXHADDR(td->channel), 2065 td->haddr); 2066 MUSB2_WRITE_1(sc, MUSB2_REG_TXHUBPORT(td->channel), 2067 td->hport); 2068 2069 /* TX NAK timeout */ 2070 if (td->transfer_type & MUSB2_MASK_TI_PROTO_ISOC) 2071 MUSB2_WRITE_1(sc, MUSB2_REG_TXNAKLIMIT, 0); 2072 else 2073 MUSB2_WRITE_1(sc, MUSB2_REG_TXNAKLIMIT, MAX_NAK_TO); 2074 2075 /* Protocol, speed, device endpoint */ 2076 MUSB2_WRITE_1(sc, MUSB2_REG_TXTI, td->transfer_type); 2077 2078 /* Max packet size */ 2079 MUSB2_WRITE_2(sc, MUSB2_REG_TXMAXP, td->reg_max_packet); 2080 2081 if (!td->transaction_started) { 2082 csrh = MUSB2_READ_1(sc, MUSB2_REG_TXCSRH); 2083 DPRINTFN(4, "csrh=0x%02x\n", csrh); 2084 2085 csrh |= MUSB2_MASK_CSRH_TXDT_WREN; 2086 if (td->toggle) 2087 csrh |= MUSB2_MASK_CSRH_TXDT_VAL; 2088 else 2089 csrh &= ~MUSB2_MASK_CSRH_TXDT_VAL; 2090 2091 /* Set data toggle */ 2092 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, csrh); 2093 } 2094 2095 /* write command */ 2096 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 2097 MUSB2_MASK_CSRL_TXPKTRDY); 2098 2099 /* Update Data Toggle */ 2100 td->toggle ^= 1; 2101 td->transaction_started = 1; 2102 2103 return (1); /* not complete */ 2104} 2105 2106static uint8_t 2107musbotg_xfer_do_fifo(struct usb_xfer *xfer) 2108{ 2109 struct musbotg_softc *sc; 2110 struct musbotg_td *td; 2111 2112 DPRINTFN(8, "\n"); 2113 sc = MUSBOTG_BUS2SC(xfer->xroot->bus); 2114 2115 td = xfer->td_transfer_cache; 2116 while (1) { 2117 2118 if ((td->func) (td)) { 2119 /* operation in progress */ 2120 break; 2121 } 2122 2123 if (((void *)td) == xfer->td_transfer_last) { 2124 goto done; 2125 } 2126 if (td->error) { 2127 goto done; 2128 } else if (td->remainder > 0) { 2129 /* 2130 * We had a short transfer. If there is no alternate 2131 * next, stop processing ! 2132 */ 2133 if (!td->alt_next) { 2134 goto done; 2135 } 2136 } 2137 /* 2138 * Fetch the next transfer descriptor and transfer 2139 * some flags to the next transfer descriptor 2140 */ 2141 td = td->obj_next; 2142 xfer->td_transfer_cache = td; 2143 } 2144 2145 return (1); /* not complete */ 2146done: 2147 /* compute all actual lengths */ 2148 musbotg_standard_done(xfer); 2149 2150 return (0); /* complete */ 2151} 2152 2153static void 2154musbotg_interrupt_poll(struct musbotg_softc *sc) 2155{ 2156 struct usb_xfer *xfer; 2157 2158repeat: 2159 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 2160 if (!musbotg_xfer_do_fifo(xfer)) { 2161 /* queue has been modified */ 2162 goto repeat; 2163 } 2164 } 2165} 2166 2167void 2168musbotg_vbus_interrupt(struct musbotg_softc *sc, uint8_t is_on) 2169{ 2170 DPRINTFN(4, "vbus = %u\n", is_on); 2171 2172 USB_BUS_LOCK(&sc->sc_bus); 2173 if (is_on) { 2174 if (!sc->sc_flags.status_vbus) { 2175 sc->sc_flags.status_vbus = 1; 2176 2177 /* complete root HUB interrupt endpoint */ 2178 musbotg_root_intr(sc); 2179 } 2180 } else { 2181 if (sc->sc_flags.status_vbus) { 2182 sc->sc_flags.status_vbus = 0; 2183 sc->sc_flags.status_bus_reset = 0; 2184 sc->sc_flags.status_suspend = 0; 2185 sc->sc_flags.change_suspend = 0; 2186 sc->sc_flags.change_connect = 1; 2187 2188 /* complete root HUB interrupt endpoint */ 2189 musbotg_root_intr(sc); 2190 } 2191 } 2192 2193 USB_BUS_UNLOCK(&sc->sc_bus); 2194} 2195 2196void 2197musbotg_connect_interrupt(struct musbotg_softc *sc) 2198{ 2199 USB_BUS_LOCK(&sc->sc_bus); 2200 sc->sc_flags.change_connect = 1; 2201 2202 /* complete root HUB interrupt endpoint */ 2203 musbotg_root_intr(sc); 2204 USB_BUS_UNLOCK(&sc->sc_bus); 2205} 2206 2207void 2208musbotg_interrupt(struct musbotg_softc *sc, 2209 uint16_t rxstat, uint16_t txstat, uint8_t stat) 2210{ 2211 uint16_t rx_status; 2212 uint16_t tx_status; 2213 uint8_t usb_status; 2214 uint8_t temp; 2215 uint8_t to = 2; 2216 2217 USB_BUS_LOCK(&sc->sc_bus); 2218 2219repeat: 2220 2221 /* read all interrupt registers */ 2222 usb_status = MUSB2_READ_1(sc, MUSB2_REG_INTUSB); 2223 2224 /* read all FIFO interrupts */ 2225 rx_status = MUSB2_READ_2(sc, MUSB2_REG_INTRX); 2226 tx_status = MUSB2_READ_2(sc, MUSB2_REG_INTTX); 2227 rx_status |= rxstat; 2228 tx_status |= txstat; 2229 usb_status |= stat; 2230 2231 /* Clear platform flags after first time */ 2232 rxstat = 0; 2233 txstat = 0; 2234 stat = 0; 2235 2236 /* check for any bus state change interrupts */ 2237 2238 if (usb_status & (MUSB2_MASK_IRESET | 2239 MUSB2_MASK_IRESUME | MUSB2_MASK_ISUSP | 2240 MUSB2_MASK_ICONN | MUSB2_MASK_IDISC)) { 2241 2242 DPRINTFN(4, "real bus interrupt 0x%08x\n", usb_status); 2243 2244 if (usb_status & MUSB2_MASK_IRESET) { 2245 2246 /* set correct state */ 2247 sc->sc_flags.status_bus_reset = 1; 2248 sc->sc_flags.status_suspend = 0; 2249 sc->sc_flags.change_suspend = 0; 2250 sc->sc_flags.change_connect = 1; 2251 2252 /* determine line speed */ 2253 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER); 2254 if (temp & MUSB2_MASK_HSMODE) 2255 sc->sc_flags.status_high_speed = 1; 2256 else 2257 sc->sc_flags.status_high_speed = 0; 2258 2259 /* 2260 * After reset all interrupts are on and we need to 2261 * turn them off! 2262 */ 2263 temp = MUSB2_MASK_IRESET; 2264 /* disable resume interrupt */ 2265 temp &= ~MUSB2_MASK_IRESUME; 2266 /* enable suspend interrupt */ 2267 temp |= MUSB2_MASK_ISUSP; 2268 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, temp); 2269 /* disable TX and RX interrupts */ 2270 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, 0); 2271 MUSB2_WRITE_2(sc, MUSB2_REG_INTRXE, 0); 2272 } 2273 /* 2274 * If RXRSM and RXSUSP is set at the same time we interpret 2275 * that like RESUME. Resume is set when there is at least 3 2276 * milliseconds of inactivity on the USB BUS. 2277 */ 2278 if (usb_status & MUSB2_MASK_IRESUME) { 2279 if (sc->sc_flags.status_suspend) { 2280 sc->sc_flags.status_suspend = 0; 2281 sc->sc_flags.change_suspend = 1; 2282 2283 temp = MUSB2_READ_1(sc, MUSB2_REG_INTUSBE); 2284 /* disable resume interrupt */ 2285 temp &= ~MUSB2_MASK_IRESUME; 2286 /* enable suspend interrupt */ 2287 temp |= MUSB2_MASK_ISUSP; 2288 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, temp); 2289 } 2290 } else if (usb_status & MUSB2_MASK_ISUSP) { 2291 if (!sc->sc_flags.status_suspend) { 2292 sc->sc_flags.status_suspend = 1; 2293 sc->sc_flags.change_suspend = 1; 2294 2295 temp = MUSB2_READ_1(sc, MUSB2_REG_INTUSBE); 2296 /* disable suspend interrupt */ 2297 temp &= ~MUSB2_MASK_ISUSP; 2298 /* enable resume interrupt */ 2299 temp |= MUSB2_MASK_IRESUME; 2300 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, temp); 2301 } 2302 } 2303 if (usb_status & 2304 (MUSB2_MASK_ICONN | MUSB2_MASK_IDISC)) 2305 sc->sc_flags.change_connect = 1; 2306 2307 /* 2308 * Host Mode: There is no IRESET so assume bus is 2309 * always in reset state once device is connected. 2310 */ 2311 if (sc->sc_mode == MUSB2_HOST_MODE) { 2312 if (usb_status & MUSB2_MASK_ICONN) 2313 sc->sc_flags.status_bus_reset = 1; 2314 if (usb_status & MUSB2_MASK_IDISC) 2315 sc->sc_flags.status_bus_reset = 0; 2316 } 2317 2318 /* complete root HUB interrupt endpoint */ 2319 musbotg_root_intr(sc); 2320 } 2321 /* check for any endpoint interrupts */ 2322 2323 if (rx_status || tx_status) { 2324 DPRINTFN(4, "real endpoint interrupt " 2325 "rx=0x%04x, tx=0x%04x\n", rx_status, tx_status); 2326 } 2327 /* poll one time regardless of FIFO status */ 2328 2329 musbotg_interrupt_poll(sc); 2330 2331 if (--to) 2332 goto repeat; 2333 2334 USB_BUS_UNLOCK(&sc->sc_bus); 2335} 2336 2337static void 2338musbotg_setup_standard_chain_sub(struct musbotg_std_temp *temp) 2339{ 2340 struct musbotg_td *td; 2341 2342 /* get current Transfer Descriptor */ 2343 td = temp->td_next; 2344 temp->td = td; 2345 2346 /* prepare for next TD */ 2347 temp->td_next = td->obj_next; 2348 2349 /* fill out the Transfer Descriptor */ 2350 td->func = temp->func; 2351 td->pc = temp->pc; 2352 td->offset = temp->offset; 2353 td->remainder = temp->len; 2354 td->error = 0; 2355 td->transaction_started = 0; 2356 td->did_stall = temp->did_stall; 2357 td->short_pkt = temp->short_pkt; 2358 td->alt_next = temp->setup_alt_next; 2359 td->channel = temp->channel; 2360 td->dev_addr = temp->dev_addr; 2361 td->haddr = temp->haddr; 2362 td->hport = temp->hport; 2363 td->transfer_type = temp->transfer_type; 2364} 2365 2366static void 2367musbotg_setup_standard_chain(struct usb_xfer *xfer) 2368{ 2369 struct musbotg_std_temp temp; 2370 struct musbotg_softc *sc; 2371 struct musbotg_td *td; 2372 uint32_t x; 2373 uint8_t ep_no; 2374 uint8_t xfer_type; 2375 enum usb_dev_speed speed; 2376 int tx; 2377 int dev_addr; 2378 2379 DPRINTFN(8, "addr=%d endpt=%d sumlen=%d speed=%d\n", 2380 xfer->address, UE_GET_ADDR(xfer->endpointno), 2381 xfer->sumlen, usbd_get_speed(xfer->xroot->udev)); 2382 2383 sc = MUSBOTG_BUS2SC(xfer->xroot->bus); 2384 ep_no = (xfer->endpointno & UE_ADDR); 2385 2386 temp.max_frame_size = xfer->max_frame_size; 2387 2388 td = xfer->td_start[0]; 2389 xfer->td_transfer_first = td; 2390 xfer->td_transfer_cache = td; 2391 2392 /* setup temp */ 2393 dev_addr = xfer->address; 2394 2395 xfer_type = xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE; 2396 2397 temp.pc = NULL; 2398 temp.td = NULL; 2399 temp.td_next = xfer->td_start[0]; 2400 temp.offset = 0; 2401 temp.setup_alt_next = xfer->flags_int.short_frames_ok; 2402 temp.did_stall = !xfer->flags_int.control_stall; 2403 temp.channel = -1; 2404 temp.dev_addr = dev_addr; 2405 temp.haddr = xfer->xroot->udev->hs_hub_addr; 2406 temp.hport = xfer->xroot->udev->hs_port_no; 2407 2408 if (xfer->flags_int.usb_mode == USB_MODE_HOST) { 2409 speed = usbd_get_speed(xfer->xroot->udev); 2410 2411 switch (speed) { 2412 case USB_SPEED_LOW: 2413 temp.transfer_type = MUSB2_MASK_TI_SPEED_LO; 2414 break; 2415 case USB_SPEED_FULL: 2416 temp.transfer_type = MUSB2_MASK_TI_SPEED_FS; 2417 break; 2418 case USB_SPEED_HIGH: 2419 temp.transfer_type = MUSB2_MASK_TI_SPEED_HS; 2420 break; 2421 default: 2422 temp.transfer_type = 0; 2423 DPRINTFN(-1, "Invalid USB speed: %d\n", speed); 2424 break; 2425 } 2426 2427 switch (xfer_type) { 2428 case UE_CONTROL: 2429 temp.transfer_type |= MUSB2_MASK_TI_PROTO_CTRL; 2430 break; 2431 case UE_ISOCHRONOUS: 2432 temp.transfer_type |= MUSB2_MASK_TI_PROTO_ISOC; 2433 break; 2434 case UE_BULK: 2435 temp.transfer_type |= MUSB2_MASK_TI_PROTO_BULK; 2436 break; 2437 case UE_INTERRUPT: 2438 temp.transfer_type |= MUSB2_MASK_TI_PROTO_INTR; 2439 break; 2440 default: 2441 DPRINTFN(-1, "Invalid USB transfer type: %d\n", 2442 xfer_type); 2443 break; 2444 } 2445 2446 temp.transfer_type |= ep_no; 2447 td->toggle = xfer->endpoint->toggle_next; 2448 } 2449 2450 /* check if we should prepend a setup message */ 2451 2452 if (xfer->flags_int.control_xfr) { 2453 if (xfer->flags_int.control_hdr) { 2454 2455 if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) 2456 temp.func = &musbotg_dev_ctrl_setup_rx; 2457 else 2458 temp.func = &musbotg_host_ctrl_setup_tx; 2459 2460 temp.len = xfer->frlengths[0]; 2461 temp.pc = xfer->frbuffers + 0; 2462 temp.short_pkt = temp.len ? 1 : 0; 2463 2464 musbotg_setup_standard_chain_sub(&temp); 2465 } 2466 x = 1; 2467 } else { 2468 x = 0; 2469 } 2470 2471 tx = 0; 2472 2473 if (x != xfer->nframes) { 2474 if (xfer->endpointno & UE_DIR_IN) 2475 tx = 1; 2476 2477 if (xfer->flags_int.usb_mode == USB_MODE_HOST) { 2478 tx = !tx; 2479 2480 if (tx) { 2481 if (xfer->flags_int.control_xfr) 2482 temp.func = &musbotg_host_ctrl_data_tx; 2483 else 2484 temp.func = &musbotg_host_data_tx; 2485 } else { 2486 if (xfer->flags_int.control_xfr) 2487 temp.func = &musbotg_host_ctrl_data_rx; 2488 else 2489 temp.func = &musbotg_host_data_rx; 2490 } 2491 2492 } else { 2493 if (tx) { 2494 if (xfer->flags_int.control_xfr) 2495 temp.func = &musbotg_dev_ctrl_data_tx; 2496 else 2497 temp.func = &musbotg_dev_data_tx; 2498 } else { 2499 if (xfer->flags_int.control_xfr) 2500 temp.func = &musbotg_dev_ctrl_data_rx; 2501 else 2502 temp.func = &musbotg_dev_data_rx; 2503 } 2504 } 2505 2506 /* setup "pc" pointer */ 2507 temp.pc = xfer->frbuffers + x; 2508 } 2509 while (x != xfer->nframes) { 2510 2511 /* DATA0 / DATA1 message */ 2512 2513 temp.len = xfer->frlengths[x]; 2514 2515 x++; 2516 2517 if (x == xfer->nframes) { 2518 if (xfer->flags_int.control_xfr) { 2519 if (xfer->flags_int.control_act) { 2520 temp.setup_alt_next = 0; 2521 } 2522 } else { 2523 temp.setup_alt_next = 0; 2524 } 2525 } 2526 if (temp.len == 0) { 2527 2528 /* make sure that we send an USB packet */ 2529 2530 temp.short_pkt = 0; 2531 2532 } else { 2533 2534 if (xfer->flags_int.isochronous_xfr) { 2535 /* isochronous data transfer */ 2536 /* don't force short */ 2537 temp.short_pkt = 1; 2538 } else { 2539 /* regular data transfer */ 2540 temp.short_pkt = (xfer->flags.force_short_xfer ? 0 : 1); 2541 } 2542 } 2543 2544 musbotg_setup_standard_chain_sub(&temp); 2545 2546 if (xfer->flags_int.isochronous_xfr) { 2547 temp.offset += temp.len; 2548 } else { 2549 /* get next Page Cache pointer */ 2550 temp.pc = xfer->frbuffers + x; 2551 } 2552 } 2553 2554 /* check for control transfer */ 2555 if (xfer->flags_int.control_xfr) { 2556 2557 /* always setup a valid "pc" pointer for status and sync */ 2558 temp.pc = xfer->frbuffers + 0; 2559 temp.len = 0; 2560 temp.short_pkt = 0; 2561 temp.setup_alt_next = 0; 2562 2563 /* check if we should append a status stage */ 2564 if (!xfer->flags_int.control_act) { 2565 /* 2566 * Send a DATA1 message and invert the current 2567 * endpoint direction. 2568 */ 2569 if (sc->sc_mode == MUSB2_DEVICE_MODE) 2570 temp.func = &musbotg_dev_ctrl_status; 2571 else { 2572 if (xfer->endpointno & UE_DIR_IN) 2573 temp.func = musbotg_host_ctrl_status_tx; 2574 else 2575 temp.func = musbotg_host_ctrl_status_rx; 2576 } 2577 musbotg_setup_standard_chain_sub(&temp); 2578 } 2579 } 2580 /* must have at least one frame! */ 2581 td = temp.td; 2582 xfer->td_transfer_last = td; 2583} 2584 2585static void 2586musbotg_timeout(void *arg) 2587{ 2588 struct usb_xfer *xfer = arg; 2589 2590 DPRINTFN(1, "xfer=%p\n", xfer); 2591 2592 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 2593 2594 /* transfer is transferred */ 2595 musbotg_device_done(xfer, USB_ERR_TIMEOUT); 2596} 2597 2598static void 2599musbotg_ep_int_set(struct musbotg_softc *sc, int channel, int on) 2600{ 2601 uint16_t temp; 2602 2603 /* 2604 * Only enable the endpoint interrupt when we are 2605 * actually waiting for data, hence we are dealing 2606 * with level triggered interrupts ! 2607 */ 2608 DPRINTFN(1, "ep_no=%d, on=%d\n", channel, on); 2609 2610 if (channel == -1) 2611 return; 2612 2613 if (channel == 0) { 2614 temp = MUSB2_READ_2(sc, MUSB2_REG_INTTXE); 2615 if (on) 2616 temp |= MUSB2_MASK_EPINT(0); 2617 else 2618 temp &= ~MUSB2_MASK_EPINT(0); 2619 2620 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, temp); 2621 } else { 2622 temp = MUSB2_READ_2(sc, MUSB2_REG_INTRXE); 2623 if (on) 2624 temp |= MUSB2_MASK_EPINT(channel); 2625 else 2626 temp &= ~MUSB2_MASK_EPINT(channel); 2627 MUSB2_WRITE_2(sc, MUSB2_REG_INTRXE, temp); 2628 2629 temp = MUSB2_READ_2(sc, MUSB2_REG_INTTXE); 2630 if (on) 2631 temp |= MUSB2_MASK_EPINT(channel); 2632 else 2633 temp &= ~MUSB2_MASK_EPINT(channel); 2634 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, temp); 2635 } 2636 2637 if (sc->sc_ep_int_set) 2638 sc->sc_ep_int_set(sc, channel, on); 2639} 2640 2641static void 2642musbotg_start_standard_chain(struct usb_xfer *xfer) 2643{ 2644 DPRINTFN(8, "\n"); 2645 2646 /* poll one time */ 2647 if (musbotg_xfer_do_fifo(xfer)) { 2648 2649 DPRINTFN(14, "enabled interrupts on endpoint\n"); 2650 2651 /* put transfer on interrupt queue */ 2652 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 2653 2654 /* start timeout, if any */ 2655 if (xfer->timeout != 0) { 2656 usbd_transfer_timeout_ms(xfer, 2657 &musbotg_timeout, xfer->timeout); 2658 } 2659 } 2660} 2661 2662static void 2663musbotg_root_intr(struct musbotg_softc *sc) 2664{ 2665 DPRINTFN(8, "\n"); 2666 2667 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2668 2669 /* set port bit */ 2670 sc->sc_hub_idata[0] = 0x02; /* we only have one port */ 2671 2672 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, 2673 sizeof(sc->sc_hub_idata)); 2674} 2675 2676static usb_error_t 2677musbotg_standard_done_sub(struct usb_xfer *xfer) 2678{ 2679 struct musbotg_td *td; 2680 uint32_t len; 2681 uint8_t error; 2682 2683 DPRINTFN(8, "\n"); 2684 2685 td = xfer->td_transfer_cache; 2686 2687 do { 2688 len = td->remainder; 2689 2690 xfer->endpoint->toggle_next = td->toggle; 2691 2692 if (xfer->aframes != xfer->nframes) { 2693 /* 2694 * Verify the length and subtract 2695 * the remainder from "frlengths[]": 2696 */ 2697 if (len > xfer->frlengths[xfer->aframes]) { 2698 td->error = 1; 2699 } else { 2700 xfer->frlengths[xfer->aframes] -= len; 2701 } 2702 } 2703 /* Check for transfer error */ 2704 if (td->error) { 2705 /* the transfer is finished */ 2706 error = 1; 2707 td = NULL; 2708 break; 2709 } 2710 /* Check for short transfer */ 2711 if (len > 0) { 2712 if (xfer->flags_int.short_frames_ok) { 2713 /* follow alt next */ 2714 if (td->alt_next) { 2715 td = td->obj_next; 2716 } else { 2717 td = NULL; 2718 } 2719 } else { 2720 /* the transfer is finished */ 2721 td = NULL; 2722 } 2723 error = 0; 2724 break; 2725 } 2726 td = td->obj_next; 2727 2728 /* this USB frame is complete */ 2729 error = 0; 2730 break; 2731 2732 } while (0); 2733 2734 /* update transfer cache */ 2735 2736 xfer->td_transfer_cache = td; 2737 2738 return (error ? 2739 USB_ERR_STALLED : USB_ERR_NORMAL_COMPLETION); 2740} 2741 2742static void 2743musbotg_standard_done(struct usb_xfer *xfer) 2744{ 2745 usb_error_t err = 0; 2746 2747 DPRINTFN(12, "xfer=%p endpoint=%p transfer done\n", 2748 xfer, xfer->endpoint); 2749 2750 /* reset scanner */ 2751 2752 xfer->td_transfer_cache = xfer->td_transfer_first; 2753 2754 if (xfer->flags_int.control_xfr) { 2755 2756 if (xfer->flags_int.control_hdr) { 2757 2758 err = musbotg_standard_done_sub(xfer); 2759 } 2760 xfer->aframes = 1; 2761 2762 if (xfer->td_transfer_cache == NULL) { 2763 goto done; 2764 } 2765 } 2766 while (xfer->aframes != xfer->nframes) { 2767 2768 err = musbotg_standard_done_sub(xfer); 2769 xfer->aframes++; 2770 2771 if (xfer->td_transfer_cache == NULL) { 2772 goto done; 2773 } 2774 } 2775 2776 if (xfer->flags_int.control_xfr && 2777 !xfer->flags_int.control_act) { 2778 2779 err = musbotg_standard_done_sub(xfer); 2780 } 2781done: 2782 musbotg_device_done(xfer, err); 2783} 2784 2785/*------------------------------------------------------------------------* 2786 * musbotg_device_done 2787 * 2788 * NOTE: this function can be called more than one time on the 2789 * same USB transfer! 2790 *------------------------------------------------------------------------*/ 2791static void 2792musbotg_device_done(struct usb_xfer *xfer, usb_error_t error) 2793{ 2794 struct musbotg_td *td; 2795 struct musbotg_softc *sc; 2796 2797 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 2798 2799 DPRINTFN(1, "xfer=%p, endpoint=%p, error=%d\n", 2800 xfer, xfer->endpoint, error); 2801 2802 DPRINTFN(14, "disabled interrupts on endpoint\n"); 2803 2804 sc = MUSBOTG_BUS2SC(xfer->xroot->bus); 2805 td = xfer->td_transfer_cache; 2806 2807 if (td && (td->channel != -1)) 2808 musbotg_channel_free(sc, td); 2809 2810 /* dequeue transfer and start next transfer */ 2811 usbd_transfer_done(xfer, error); 2812} 2813 2814static void 2815musbotg_set_stall(struct usb_device *udev, struct usb_xfer *xfer, 2816 struct usb_endpoint *ep, uint8_t *did_stall) 2817{ 2818 struct musbotg_softc *sc; 2819 uint8_t ep_no; 2820 2821 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 2822 2823 DPRINTFN(4, "endpoint=%p\n", ep); 2824 2825 if (xfer) { 2826 /* cancel any ongoing transfers */ 2827 musbotg_device_done(xfer, USB_ERR_STALLED); 2828 } 2829 /* set FORCESTALL */ 2830 sc = MUSBOTG_BUS2SC(udev->bus); 2831 2832 ep_no = (ep->edesc->bEndpointAddress & UE_ADDR); 2833 2834 /* select endpoint */ 2835 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, ep_no); 2836 2837 if (ep->edesc->bEndpointAddress & UE_DIR_IN) { 2838 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 2839 MUSB2_MASK_CSRL_TXSENDSTALL); 2840 } else { 2841 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 2842 MUSB2_MASK_CSRL_RXSENDSTALL); 2843 } 2844} 2845 2846static void 2847musbotg_clear_stall_sub(struct musbotg_softc *sc, uint16_t wMaxPacket, 2848 uint8_t ep_no, uint8_t ep_type, uint8_t ep_dir) 2849{ 2850 uint16_t mps; 2851 uint16_t temp; 2852 uint8_t csr; 2853 2854 if (ep_type == UE_CONTROL) { 2855 /* clearing stall is not needed */ 2856 return; 2857 } 2858 /* select endpoint */ 2859 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, ep_no); 2860 2861 /* compute max frame size */ 2862 mps = wMaxPacket & 0x7FF; 2863 switch ((wMaxPacket >> 11) & 3) { 2864 case 1: 2865 mps *= 2; 2866 break; 2867 case 2: 2868 mps *= 3; 2869 break; 2870 default: 2871 break; 2872 } 2873 2874 if (ep_dir == UE_DIR_IN) { 2875 2876 temp = 0; 2877 2878 /* Configure endpoint */ 2879 switch (ep_type) { 2880 case UE_INTERRUPT: 2881 MUSB2_WRITE_2(sc, MUSB2_REG_TXMAXP, wMaxPacket); 2882 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, 2883 MUSB2_MASK_CSRH_TXMODE | temp); 2884 break; 2885 case UE_ISOCHRONOUS: 2886 MUSB2_WRITE_2(sc, MUSB2_REG_TXMAXP, wMaxPacket); 2887 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, 2888 MUSB2_MASK_CSRH_TXMODE | 2889 MUSB2_MASK_CSRH_TXISO | temp); 2890 break; 2891 case UE_BULK: 2892 MUSB2_WRITE_2(sc, MUSB2_REG_TXMAXP, wMaxPacket); 2893 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, 2894 MUSB2_MASK_CSRH_TXMODE | temp); 2895 break; 2896 default: 2897 break; 2898 } 2899 2900 /* Need to flush twice in case of double bufring */ 2901 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 2902 if (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) { 2903 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 2904 MUSB2_MASK_CSRL_TXFFLUSH); 2905 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 2906 if (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) { 2907 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 2908 MUSB2_MASK_CSRL_TXFFLUSH); 2909 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 2910 } 2911 } 2912 /* reset data toggle */ 2913 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 2914 MUSB2_MASK_CSRL_TXDT_CLR); 2915 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0); 2916 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 2917 2918 /* set double/single buffering */ 2919 temp = MUSB2_READ_2(sc, MUSB2_REG_TXDBDIS); 2920 if (mps <= (sc->sc_hw_ep_profile[ep_no]. 2921 max_in_frame_size / 2)) { 2922 /* double buffer */ 2923 temp &= ~(1 << ep_no); 2924 } else { 2925 /* single buffer */ 2926 temp |= (1 << ep_no); 2927 } 2928 MUSB2_WRITE_2(sc, MUSB2_REG_TXDBDIS, temp); 2929 2930 /* clear sent stall */ 2931 if (csr & MUSB2_MASK_CSRL_TXSENTSTALL) { 2932 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0); 2933 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 2934 } 2935 } else { 2936 2937 temp = 0; 2938 2939 /* Configure endpoint */ 2940 switch (ep_type) { 2941 case UE_INTERRUPT: 2942 MUSB2_WRITE_2(sc, MUSB2_REG_RXMAXP, wMaxPacket); 2943 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH, 2944 MUSB2_MASK_CSRH_RXNYET | temp); 2945 break; 2946 case UE_ISOCHRONOUS: 2947 MUSB2_WRITE_2(sc, MUSB2_REG_RXMAXP, wMaxPacket); 2948 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH, 2949 MUSB2_MASK_CSRH_RXNYET | 2950 MUSB2_MASK_CSRH_RXISO | temp); 2951 break; 2952 case UE_BULK: 2953 MUSB2_WRITE_2(sc, MUSB2_REG_RXMAXP, wMaxPacket); 2954 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH, temp); 2955 break; 2956 default: 2957 break; 2958 } 2959 2960 /* Need to flush twice in case of double bufring */ 2961 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL); 2962 if (csr & MUSB2_MASK_CSRL_RXPKTRDY) { 2963 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 2964 MUSB2_MASK_CSRL_RXFFLUSH); 2965 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL); 2966 if (csr & MUSB2_MASK_CSRL_RXPKTRDY) { 2967 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 2968 MUSB2_MASK_CSRL_RXFFLUSH); 2969 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL); 2970 } 2971 } 2972 /* reset data toggle */ 2973 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 2974 MUSB2_MASK_CSRL_RXDT_CLR); 2975 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 0); 2976 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL); 2977 2978 /* set double/single buffering */ 2979 temp = MUSB2_READ_2(sc, MUSB2_REG_RXDBDIS); 2980 if (mps <= (sc->sc_hw_ep_profile[ep_no]. 2981 max_out_frame_size / 2)) { 2982 /* double buffer */ 2983 temp &= ~(1 << ep_no); 2984 } else { 2985 /* single buffer */ 2986 temp |= (1 << ep_no); 2987 } 2988 MUSB2_WRITE_2(sc, MUSB2_REG_RXDBDIS, temp); 2989 2990 /* clear sent stall */ 2991 if (csr & MUSB2_MASK_CSRL_RXSENTSTALL) { 2992 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 0); 2993 } 2994 } 2995} 2996 2997static void 2998musbotg_clear_stall(struct usb_device *udev, struct usb_endpoint *ep) 2999{ 3000 struct musbotg_softc *sc; 3001 struct usb_endpoint_descriptor *ed; 3002 3003 DPRINTFN(4, "endpoint=%p\n", ep); 3004 3005 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 3006 3007 /* check mode */ 3008 if (udev->flags.usb_mode != USB_MODE_DEVICE) { 3009 /* not supported */ 3010 return; 3011 } 3012 /* get softc */ 3013 sc = MUSBOTG_BUS2SC(udev->bus); 3014 3015 /* get endpoint descriptor */ 3016 ed = ep->edesc; 3017 3018 /* reset endpoint */ 3019 musbotg_clear_stall_sub(sc, 3020 UGETW(ed->wMaxPacketSize), 3021 (ed->bEndpointAddress & UE_ADDR), 3022 (ed->bmAttributes & UE_XFERTYPE), 3023 (ed->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT))); 3024} 3025 3026usb_error_t 3027musbotg_init(struct musbotg_softc *sc) 3028{ 3029 struct usb_hw_ep_profile *pf; 3030 uint16_t offset; 3031 uint8_t nrx; 3032 uint8_t ntx; 3033 uint8_t temp; 3034 uint8_t fsize; 3035 uint8_t frx; 3036 uint8_t ftx; 3037 uint8_t dynfifo; 3038 3039 DPRINTFN(1, "start\n"); 3040 3041 /* set up the bus structure */ 3042 sc->sc_bus.usbrev = USB_REV_2_0; 3043 sc->sc_bus.methods = &musbotg_bus_methods; 3044 3045 USB_BUS_LOCK(&sc->sc_bus); 3046 3047 /* turn on clocks */ 3048 3049 if (sc->sc_clocks_on) { 3050 (sc->sc_clocks_on) (sc->sc_clocks_arg); 3051 } 3052 3053 /* wait a little for things to stabilise */ 3054 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 1000); 3055 3056 /* disable all interrupts */ 3057 3058 temp = MUSB2_READ_1(sc, MUSB2_REG_DEVCTL); 3059 DPRINTF("pre-DEVCTL=0x%02x\n", temp); 3060 3061 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, 0); 3062 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, 0); 3063 MUSB2_WRITE_2(sc, MUSB2_REG_INTRXE, 0); 3064 3065 /* disable pullup */ 3066 3067 musbotg_pull_common(sc, 0); 3068 3069 /* wait a little bit (10ms) */ 3070 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100); 3071 3072 3073 /* disable double packet buffering */ 3074 MUSB2_WRITE_2(sc, MUSB2_REG_RXDBDIS, 0xFFFF); 3075 MUSB2_WRITE_2(sc, MUSB2_REG_TXDBDIS, 0xFFFF); 3076 3077 /* enable HighSpeed and ISO Update flags */ 3078 3079 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, 3080 MUSB2_MASK_HSENAB | MUSB2_MASK_ISOUPD); 3081 3082 if (sc->sc_mode == MUSB2_DEVICE_MODE) { 3083 /* clear Session bit, if set */ 3084 temp = MUSB2_READ_1(sc, MUSB2_REG_DEVCTL); 3085 temp &= ~MUSB2_MASK_SESS; 3086 MUSB2_WRITE_1(sc, MUSB2_REG_DEVCTL, temp); 3087 } else { 3088 /* Enter session for Host mode */ 3089 temp = MUSB2_READ_1(sc, MUSB2_REG_DEVCTL); 3090 temp |= MUSB2_MASK_SESS; 3091 MUSB2_WRITE_1(sc, MUSB2_REG_DEVCTL, temp); 3092 } 3093 3094 /* wait a little for things to stabilise */ 3095 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 10); 3096 3097 DPRINTF("DEVCTL=0x%02x\n", temp); 3098 3099 /* disable testmode */ 3100 3101 MUSB2_WRITE_1(sc, MUSB2_REG_TESTMODE, 0); 3102 3103 /* set default value */ 3104 3105 MUSB2_WRITE_1(sc, MUSB2_REG_MISC, 0); 3106 3107 /* select endpoint index 0 */ 3108 3109 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); 3110 3111 /* read out number of endpoints */ 3112 3113 nrx = 3114 (MUSB2_READ_1(sc, MUSB2_REG_EPINFO) / 16); 3115 3116 ntx = 3117 (MUSB2_READ_1(sc, MUSB2_REG_EPINFO) % 16); 3118 3119 /* these numbers exclude the control endpoint */ 3120 3121 DPRINTFN(2, "RX/TX endpoints: %u/%u\n", nrx, ntx); 3122 3123 sc->sc_ep_max = (nrx > ntx) ? nrx : ntx; 3124 if (sc->sc_ep_max == 0) { 3125 DPRINTFN(2, "ERROR: Looks like the clocks are off!\n"); 3126 } 3127 /* read out configuration data */ 3128 3129 sc->sc_conf_data = MUSB2_READ_1(sc, MUSB2_REG_CONFDATA); 3130 3131 DPRINTFN(2, "Config Data: 0x%02x\n", 3132 sc->sc_conf_data); 3133 3134 dynfifo = (sc->sc_conf_data & MUSB2_MASK_CD_DYNFIFOSZ) ? 1 : 0; 3135 3136 if (dynfifo) { 3137 device_printf(sc->sc_bus.bdev, "Dynamic FIFO sizing detected, " 3138 "assuming 16Kbytes of FIFO RAM\n"); 3139 } 3140 3141 DPRINTFN(2, "HW version: 0x%04x\n", 3142 MUSB2_READ_1(sc, MUSB2_REG_HWVERS)); 3143 3144 /* initialise endpoint profiles */ 3145 3146 offset = 0; 3147 3148 for (temp = 1; temp <= sc->sc_ep_max; temp++) { 3149 pf = sc->sc_hw_ep_profile + temp; 3150 3151 /* select endpoint */ 3152 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, temp); 3153 3154 fsize = MUSB2_READ_1(sc, MUSB2_REG_FSIZE); 3155 frx = (fsize & MUSB2_MASK_RX_FSIZE) / 16; 3156 ftx = (fsize & MUSB2_MASK_TX_FSIZE); 3157 3158 DPRINTF("Endpoint %u FIFO size: IN=%u, OUT=%u, DYN=%d\n", 3159 temp, ftx, frx, dynfifo); 3160 3161 if (dynfifo) { 3162 if (frx && (temp <= nrx)) { 3163 if (temp == 1) { 3164 frx = 12; /* 4K */ 3165 MUSB2_WRITE_1(sc, MUSB2_REG_RXFIFOSZ, 3166 MUSB2_VAL_FIFOSZ_4096 | 3167 MUSB2_MASK_FIFODB); 3168 } else if (temp < 8) { 3169 frx = 10; /* 1K */ 3170 MUSB2_WRITE_1(sc, MUSB2_REG_RXFIFOSZ, 3171 MUSB2_VAL_FIFOSZ_512 | 3172 MUSB2_MASK_FIFODB); 3173 } else { 3174 frx = 7; /* 128 bytes */ 3175 MUSB2_WRITE_1(sc, MUSB2_REG_RXFIFOSZ, 3176 MUSB2_VAL_FIFOSZ_128); 3177 } 3178 3179 MUSB2_WRITE_2(sc, MUSB2_REG_RXFIFOADD, 3180 offset >> 3); 3181 3182 offset += (1 << frx); 3183 } 3184 if (ftx && (temp <= ntx)) { 3185 if (temp == 1) { 3186 ftx = 12; /* 4K */ 3187 MUSB2_WRITE_1(sc, MUSB2_REG_TXFIFOSZ, 3188 MUSB2_VAL_FIFOSZ_4096 | 3189 MUSB2_MASK_FIFODB); 3190 } else if (temp < 8) { 3191 ftx = 10; /* 1K */ 3192 MUSB2_WRITE_1(sc, MUSB2_REG_TXFIFOSZ, 3193 MUSB2_VAL_FIFOSZ_512 | 3194 MUSB2_MASK_FIFODB); 3195 } else { 3196 ftx = 7; /* 128 bytes */ 3197 MUSB2_WRITE_1(sc, MUSB2_REG_TXFIFOSZ, 3198 MUSB2_VAL_FIFOSZ_128); 3199 } 3200 3201 MUSB2_WRITE_2(sc, MUSB2_REG_TXFIFOADD, 3202 offset >> 3); 3203 3204 offset += (1 << ftx); 3205 } 3206 } 3207 3208 if (frx && ftx && (temp <= nrx) && (temp <= ntx)) { 3209 pf->max_in_frame_size = 1 << ftx; 3210 pf->max_out_frame_size = 1 << frx; 3211 pf->is_simplex = 0; /* duplex */ 3212 pf->support_multi_buffer = 1; 3213 pf->support_bulk = 1; 3214 pf->support_interrupt = 1; 3215 pf->support_isochronous = 1; 3216 pf->support_in = 1; 3217 pf->support_out = 1; 3218 } else if (frx && (temp <= nrx)) { 3219 pf->max_out_frame_size = 1 << frx; 3220 pf->is_simplex = 1; /* simplex */ 3221 pf->support_multi_buffer = 1; 3222 pf->support_bulk = 1; 3223 pf->support_interrupt = 1; 3224 pf->support_isochronous = 1; 3225 pf->support_out = 1; 3226 } else if (ftx && (temp <= ntx)) { 3227 pf->max_in_frame_size = 1 << ftx; 3228 pf->is_simplex = 1; /* simplex */ 3229 pf->support_multi_buffer = 1; 3230 pf->support_bulk = 1; 3231 pf->support_interrupt = 1; 3232 pf->support_isochronous = 1; 3233 pf->support_in = 1; 3234 } 3235 } 3236 3237 DPRINTFN(2, "Dynamic FIFO size = %d bytes\n", offset); 3238 3239 /* turn on default interrupts */ 3240 3241 if (sc->sc_mode == MUSB2_HOST_MODE) 3242 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, 0xff); 3243 else 3244 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, 3245 MUSB2_MASK_IRESET); 3246 3247 musbotg_clocks_off(sc); 3248 3249 USB_BUS_UNLOCK(&sc->sc_bus); 3250 3251 /* catch any lost interrupts */ 3252 3253 musbotg_do_poll(&sc->sc_bus); 3254 3255 return (0); /* success */ 3256} 3257 3258void 3259musbotg_uninit(struct musbotg_softc *sc) 3260{ 3261 USB_BUS_LOCK(&sc->sc_bus); 3262 3263 /* disable all interrupts */ 3264 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, 0); 3265 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, 0); 3266 MUSB2_WRITE_2(sc, MUSB2_REG_INTRXE, 0); 3267 3268 sc->sc_flags.port_powered = 0; 3269 sc->sc_flags.status_vbus = 0; 3270 sc->sc_flags.status_bus_reset = 0; 3271 sc->sc_flags.status_suspend = 0; 3272 sc->sc_flags.change_suspend = 0; 3273 sc->sc_flags.change_connect = 1; 3274 3275 musbotg_pull_down(sc); 3276 musbotg_clocks_off(sc); 3277 USB_BUS_UNLOCK(&sc->sc_bus); 3278} 3279 3280static void 3281musbotg_suspend(struct musbotg_softc *sc) 3282{ 3283 /* TODO */ 3284} 3285 3286static void 3287musbotg_resume(struct musbotg_softc *sc) 3288{ 3289 /* TODO */ 3290} 3291 3292static void 3293musbotg_do_poll(struct usb_bus *bus) 3294{ 3295 struct musbotg_softc *sc = MUSBOTG_BUS2SC(bus); 3296 3297 USB_BUS_LOCK(&sc->sc_bus); 3298 musbotg_interrupt_poll(sc); 3299 USB_BUS_UNLOCK(&sc->sc_bus); 3300} 3301 3302/*------------------------------------------------------------------------* 3303 * musbotg bulk support 3304 *------------------------------------------------------------------------*/ 3305static void 3306musbotg_device_bulk_open(struct usb_xfer *xfer) 3307{ 3308 return; 3309} 3310 3311static void 3312musbotg_device_bulk_close(struct usb_xfer *xfer) 3313{ 3314 musbotg_device_done(xfer, USB_ERR_CANCELLED); 3315} 3316 3317static void 3318musbotg_device_bulk_enter(struct usb_xfer *xfer) 3319{ 3320 return; 3321} 3322 3323static void 3324musbotg_device_bulk_start(struct usb_xfer *xfer) 3325{ 3326 /* setup TDs */ 3327 musbotg_setup_standard_chain(xfer); 3328 musbotg_start_standard_chain(xfer); 3329} 3330 3331struct usb_pipe_methods musbotg_device_bulk_methods = 3332{ 3333 .open = musbotg_device_bulk_open, 3334 .close = musbotg_device_bulk_close, 3335 .enter = musbotg_device_bulk_enter, 3336 .start = musbotg_device_bulk_start, 3337}; 3338 3339/*------------------------------------------------------------------------* 3340 * musbotg control support 3341 *------------------------------------------------------------------------*/ 3342static void 3343musbotg_device_ctrl_open(struct usb_xfer *xfer) 3344{ 3345 return; 3346} 3347 3348static void 3349musbotg_device_ctrl_close(struct usb_xfer *xfer) 3350{ 3351 musbotg_device_done(xfer, USB_ERR_CANCELLED); 3352} 3353 3354static void 3355musbotg_device_ctrl_enter(struct usb_xfer *xfer) 3356{ 3357 return; 3358} 3359 3360static void 3361musbotg_device_ctrl_start(struct usb_xfer *xfer) 3362{ 3363 /* setup TDs */ 3364 musbotg_setup_standard_chain(xfer); 3365 musbotg_start_standard_chain(xfer); 3366} 3367 3368struct usb_pipe_methods musbotg_device_ctrl_methods = 3369{ 3370 .open = musbotg_device_ctrl_open, 3371 .close = musbotg_device_ctrl_close, 3372 .enter = musbotg_device_ctrl_enter, 3373 .start = musbotg_device_ctrl_start, 3374}; 3375 3376/*------------------------------------------------------------------------* 3377 * musbotg interrupt support 3378 *------------------------------------------------------------------------*/ 3379static void 3380musbotg_device_intr_open(struct usb_xfer *xfer) 3381{ 3382 return; 3383} 3384 3385static void 3386musbotg_device_intr_close(struct usb_xfer *xfer) 3387{ 3388 musbotg_device_done(xfer, USB_ERR_CANCELLED); 3389} 3390 3391static void 3392musbotg_device_intr_enter(struct usb_xfer *xfer) 3393{ 3394 return; 3395} 3396 3397static void 3398musbotg_device_intr_start(struct usb_xfer *xfer) 3399{ 3400 /* setup TDs */ 3401 musbotg_setup_standard_chain(xfer); 3402 musbotg_start_standard_chain(xfer); 3403} 3404 3405struct usb_pipe_methods musbotg_device_intr_methods = 3406{ 3407 .open = musbotg_device_intr_open, 3408 .close = musbotg_device_intr_close, 3409 .enter = musbotg_device_intr_enter, 3410 .start = musbotg_device_intr_start, 3411}; 3412 3413/*------------------------------------------------------------------------* 3414 * musbotg full speed isochronous support 3415 *------------------------------------------------------------------------*/ 3416static void 3417musbotg_device_isoc_open(struct usb_xfer *xfer) 3418{ 3419 return; 3420} 3421 3422static void 3423musbotg_device_isoc_close(struct usb_xfer *xfer) 3424{ 3425 musbotg_device_done(xfer, USB_ERR_CANCELLED); 3426} 3427 3428static void 3429musbotg_device_isoc_enter(struct usb_xfer *xfer) 3430{ 3431 struct musbotg_softc *sc = MUSBOTG_BUS2SC(xfer->xroot->bus); 3432 uint32_t temp; 3433 uint32_t nframes; 3434 uint32_t fs_frames; 3435 3436 DPRINTFN(5, "xfer=%p next=%d nframes=%d\n", 3437 xfer, xfer->endpoint->isoc_next, xfer->nframes); 3438 3439 /* get the current frame index */ 3440 3441 nframes = MUSB2_READ_2(sc, MUSB2_REG_FRAME); 3442 3443 /* 3444 * check if the frame index is within the window where the frames 3445 * will be inserted 3446 */ 3447 temp = (nframes - xfer->endpoint->isoc_next) & MUSB2_MASK_FRAME; 3448 3449 if (usbd_get_speed(xfer->xroot->udev) == USB_SPEED_HIGH) { 3450 fs_frames = (xfer->nframes + 7) / 8; 3451 } else { 3452 fs_frames = xfer->nframes; 3453 } 3454 3455 if ((xfer->endpoint->is_synced == 0) || 3456 (temp < fs_frames)) { 3457 /* 3458 * If there is data underflow or the pipe queue is 3459 * empty we schedule the transfer a few frames ahead 3460 * of the current frame position. Else two isochronous 3461 * transfers might overlap. 3462 */ 3463 xfer->endpoint->isoc_next = (nframes + 3) & MUSB2_MASK_FRAME; 3464 xfer->endpoint->is_synced = 1; 3465 DPRINTFN(2, "start next=%d\n", xfer->endpoint->isoc_next); 3466 } 3467 /* 3468 * compute how many milliseconds the insertion is ahead of the 3469 * current frame position: 3470 */ 3471 temp = (xfer->endpoint->isoc_next - nframes) & MUSB2_MASK_FRAME; 3472 3473 /* 3474 * pre-compute when the isochronous transfer will be finished: 3475 */ 3476 xfer->isoc_time_complete = 3477 usb_isoc_time_expand(&sc->sc_bus, nframes) + temp + 3478 fs_frames; 3479 3480 /* compute frame number for next insertion */ 3481 xfer->endpoint->isoc_next += fs_frames; 3482 3483 /* setup TDs */ 3484 musbotg_setup_standard_chain(xfer); 3485} 3486 3487static void 3488musbotg_device_isoc_start(struct usb_xfer *xfer) 3489{ 3490 /* start TD chain */ 3491 musbotg_start_standard_chain(xfer); 3492} 3493 3494struct usb_pipe_methods musbotg_device_isoc_methods = 3495{ 3496 .open = musbotg_device_isoc_open, 3497 .close = musbotg_device_isoc_close, 3498 .enter = musbotg_device_isoc_enter, 3499 .start = musbotg_device_isoc_start, 3500}; 3501 3502/*------------------------------------------------------------------------* 3503 * musbotg root control support 3504 *------------------------------------------------------------------------* 3505 * Simulate a hardware HUB by handling all the necessary requests. 3506 *------------------------------------------------------------------------*/ 3507 3508static const struct usb_device_descriptor musbotg_devd = { 3509 .bLength = sizeof(struct usb_device_descriptor), 3510 .bDescriptorType = UDESC_DEVICE, 3511 .bcdUSB = {0x00, 0x02}, 3512 .bDeviceClass = UDCLASS_HUB, 3513 .bDeviceSubClass = UDSUBCLASS_HUB, 3514 .bDeviceProtocol = UDPROTO_HSHUBSTT, 3515 .bMaxPacketSize = 64, 3516 .bcdDevice = {0x00, 0x01}, 3517 .iManufacturer = 1, 3518 .iProduct = 2, 3519 .bNumConfigurations = 1, 3520}; 3521 3522static const struct usb_device_qualifier musbotg_odevd = { 3523 .bLength = sizeof(struct usb_device_qualifier), 3524 .bDescriptorType = UDESC_DEVICE_QUALIFIER, 3525 .bcdUSB = {0x00, 0x02}, 3526 .bDeviceClass = UDCLASS_HUB, 3527 .bDeviceSubClass = UDSUBCLASS_HUB, 3528 .bDeviceProtocol = UDPROTO_FSHUB, 3529 .bMaxPacketSize0 = 0, 3530 .bNumConfigurations = 0, 3531}; 3532 3533static const struct musbotg_config_desc musbotg_confd = { 3534 .confd = { 3535 .bLength = sizeof(struct usb_config_descriptor), 3536 .bDescriptorType = UDESC_CONFIG, 3537 .wTotalLength[0] = sizeof(musbotg_confd), 3538 .bNumInterface = 1, 3539 .bConfigurationValue = 1, 3540 .iConfiguration = 0, 3541 .bmAttributes = UC_SELF_POWERED, 3542 .bMaxPower = 0, 3543 }, 3544 .ifcd = { 3545 .bLength = sizeof(struct usb_interface_descriptor), 3546 .bDescriptorType = UDESC_INTERFACE, 3547 .bNumEndpoints = 1, 3548 .bInterfaceClass = UICLASS_HUB, 3549 .bInterfaceSubClass = UISUBCLASS_HUB, 3550 .bInterfaceProtocol = 0, 3551 }, 3552 .endpd = { 3553 .bLength = sizeof(struct usb_endpoint_descriptor), 3554 .bDescriptorType = UDESC_ENDPOINT, 3555 .bEndpointAddress = (UE_DIR_IN | MUSBOTG_INTR_ENDPT), 3556 .bmAttributes = UE_INTERRUPT, 3557 .wMaxPacketSize[0] = 8, 3558 .bInterval = 255, 3559 }, 3560}; 3561 3562#define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) } 3563 3564static const struct usb_hub_descriptor_min musbotg_hubd = { 3565 .bDescLength = sizeof(musbotg_hubd), 3566 .bDescriptorType = UDESC_HUB, 3567 .bNbrPorts = 1, 3568 HSETW(.wHubCharacteristics, (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL)), 3569 .bPwrOn2PwrGood = 50, 3570 .bHubContrCurrent = 0, 3571 .DeviceRemovable = {0}, /* port is removable */ 3572}; 3573 3574#define STRING_LANG \ 3575 0x09, 0x04, /* American English */ 3576 3577#define STRING_VENDOR \ 3578 'M', 0, 'e', 0, 'n', 0, 't', 0, 'o', 0, 'r', 0, ' ', 0, \ 3579 'G', 0, 'r', 0, 'a', 0, 'p', 0, 'h', 0, 'i', 0, 'c', 0, 's', 0 3580 3581#define STRING_PRODUCT \ 3582 'O', 0, 'T', 0, 'G', 0, ' ', 0, 'R', 0, \ 3583 'o', 0, 'o', 0, 't', 0, ' ', 0, 'H', 0, \ 3584 'U', 0, 'B', 0, 3585 3586USB_MAKE_STRING_DESC(STRING_LANG, musbotg_langtab); 3587USB_MAKE_STRING_DESC(STRING_VENDOR, musbotg_vendor); 3588USB_MAKE_STRING_DESC(STRING_PRODUCT, musbotg_product); 3589 3590static usb_error_t 3591musbotg_roothub_exec(struct usb_device *udev, 3592 struct usb_device_request *req, const void **pptr, uint16_t *plength) 3593{ 3594 struct musbotg_softc *sc = MUSBOTG_BUS2SC(udev->bus); 3595 const void *ptr; 3596 uint16_t len; 3597 uint16_t value; 3598 uint16_t index; 3599 uint8_t reg; 3600 usb_error_t err; 3601 3602 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 3603 3604 /* buffer reset */ 3605 ptr = (const void *)&sc->sc_hub_temp; 3606 len = 0; 3607 err = 0; 3608 3609 value = UGETW(req->wValue); 3610 index = UGETW(req->wIndex); 3611 3612 /* demultiplex the control request */ 3613 3614 switch (req->bmRequestType) { 3615 case UT_READ_DEVICE: 3616 switch (req->bRequest) { 3617 case UR_GET_DESCRIPTOR: 3618 goto tr_handle_get_descriptor; 3619 case UR_GET_CONFIG: 3620 goto tr_handle_get_config; 3621 case UR_GET_STATUS: 3622 goto tr_handle_get_status; 3623 default: 3624 goto tr_stalled; 3625 } 3626 break; 3627 3628 case UT_WRITE_DEVICE: 3629 switch (req->bRequest) { 3630 case UR_SET_ADDRESS: 3631 goto tr_handle_set_address; 3632 case UR_SET_CONFIG: 3633 goto tr_handle_set_config; 3634 case UR_CLEAR_FEATURE: 3635 goto tr_valid; /* nop */ 3636 case UR_SET_DESCRIPTOR: 3637 goto tr_valid; /* nop */ 3638 case UR_SET_FEATURE: 3639 default: 3640 goto tr_stalled; 3641 } 3642 break; 3643 3644 case UT_WRITE_ENDPOINT: 3645 switch (req->bRequest) { 3646 case UR_CLEAR_FEATURE: 3647 switch (UGETW(req->wValue)) { 3648 case UF_ENDPOINT_HALT: 3649 goto tr_handle_clear_halt; 3650 case UF_DEVICE_REMOTE_WAKEUP: 3651 goto tr_handle_clear_wakeup; 3652 default: 3653 goto tr_stalled; 3654 } 3655 break; 3656 case UR_SET_FEATURE: 3657 switch (UGETW(req->wValue)) { 3658 case UF_ENDPOINT_HALT: 3659 goto tr_handle_set_halt; 3660 case UF_DEVICE_REMOTE_WAKEUP: 3661 goto tr_handle_set_wakeup; 3662 default: 3663 goto tr_stalled; 3664 } 3665 break; 3666 case UR_SYNCH_FRAME: 3667 goto tr_valid; /* nop */ 3668 default: 3669 goto tr_stalled; 3670 } 3671 break; 3672 3673 case UT_READ_ENDPOINT: 3674 switch (req->bRequest) { 3675 case UR_GET_STATUS: 3676 goto tr_handle_get_ep_status; 3677 default: 3678 goto tr_stalled; 3679 } 3680 break; 3681 3682 case UT_WRITE_INTERFACE: 3683 switch (req->bRequest) { 3684 case UR_SET_INTERFACE: 3685 goto tr_handle_set_interface; 3686 case UR_CLEAR_FEATURE: 3687 goto tr_valid; /* nop */ 3688 case UR_SET_FEATURE: 3689 default: 3690 goto tr_stalled; 3691 } 3692 break; 3693 3694 case UT_READ_INTERFACE: 3695 switch (req->bRequest) { 3696 case UR_GET_INTERFACE: 3697 goto tr_handle_get_interface; 3698 case UR_GET_STATUS: 3699 goto tr_handle_get_iface_status; 3700 default: 3701 goto tr_stalled; 3702 } 3703 break; 3704 3705 case UT_WRITE_CLASS_INTERFACE: 3706 case UT_WRITE_VENDOR_INTERFACE: 3707 /* XXX forward */ 3708 break; 3709 3710 case UT_READ_CLASS_INTERFACE: 3711 case UT_READ_VENDOR_INTERFACE: 3712 /* XXX forward */ 3713 break; 3714 3715 case UT_WRITE_CLASS_DEVICE: 3716 switch (req->bRequest) { 3717 case UR_CLEAR_FEATURE: 3718 goto tr_valid; 3719 case UR_SET_DESCRIPTOR: 3720 case UR_SET_FEATURE: 3721 break; 3722 default: 3723 goto tr_stalled; 3724 } 3725 break; 3726 3727 case UT_WRITE_CLASS_OTHER: 3728 switch (req->bRequest) { 3729 case UR_CLEAR_FEATURE: 3730 goto tr_handle_clear_port_feature; 3731 case UR_SET_FEATURE: 3732 goto tr_handle_set_port_feature; 3733 case UR_CLEAR_TT_BUFFER: 3734 case UR_RESET_TT: 3735 case UR_STOP_TT: 3736 goto tr_valid; 3737 3738 default: 3739 goto tr_stalled; 3740 } 3741 break; 3742 3743 case UT_READ_CLASS_OTHER: 3744 switch (req->bRequest) { 3745 case UR_GET_TT_STATE: 3746 goto tr_handle_get_tt_state; 3747 case UR_GET_STATUS: 3748 goto tr_handle_get_port_status; 3749 default: 3750 goto tr_stalled; 3751 } 3752 break; 3753 3754 case UT_READ_CLASS_DEVICE: 3755 switch (req->bRequest) { 3756 case UR_GET_DESCRIPTOR: 3757 goto tr_handle_get_class_descriptor; 3758 case UR_GET_STATUS: 3759 goto tr_handle_get_class_status; 3760 3761 default: 3762 goto tr_stalled; 3763 } 3764 break; 3765 default: 3766 goto tr_stalled; 3767 } 3768 goto tr_valid; 3769 3770tr_handle_get_descriptor: 3771 switch (value >> 8) { 3772 case UDESC_DEVICE: 3773 if (value & 0xff) { 3774 goto tr_stalled; 3775 } 3776 len = sizeof(musbotg_devd); 3777 ptr = (const void *)&musbotg_devd; 3778 goto tr_valid; 3779 case UDESC_CONFIG: 3780 if (value & 0xff) { 3781 goto tr_stalled; 3782 } 3783 len = sizeof(musbotg_confd); 3784 ptr = (const void *)&musbotg_confd; 3785 goto tr_valid; 3786 case UDESC_STRING: 3787 switch (value & 0xff) { 3788 case 0: /* Language table */ 3789 len = sizeof(musbotg_langtab); 3790 ptr = (const void *)&musbotg_langtab; 3791 goto tr_valid; 3792 3793 case 1: /* Vendor */ 3794 len = sizeof(musbotg_vendor); 3795 ptr = (const void *)&musbotg_vendor; 3796 goto tr_valid; 3797 3798 case 2: /* Product */ 3799 len = sizeof(musbotg_product); 3800 ptr = (const void *)&musbotg_product; 3801 goto tr_valid; 3802 default: 3803 break; 3804 } 3805 break; 3806 default: 3807 goto tr_stalled; 3808 } 3809 goto tr_stalled; 3810 3811tr_handle_get_config: 3812 len = 1; 3813 sc->sc_hub_temp.wValue[0] = sc->sc_conf; 3814 goto tr_valid; 3815 3816tr_handle_get_status: 3817 len = 2; 3818 USETW(sc->sc_hub_temp.wValue, UDS_SELF_POWERED); 3819 goto tr_valid; 3820 3821tr_handle_set_address: 3822 if (value & 0xFF00) { 3823 goto tr_stalled; 3824 } 3825 sc->sc_rt_addr = value; 3826 goto tr_valid; 3827 3828tr_handle_set_config: 3829 if (value >= 2) { 3830 goto tr_stalled; 3831 } 3832 sc->sc_conf = value; 3833 goto tr_valid; 3834 3835tr_handle_get_interface: 3836 len = 1; 3837 sc->sc_hub_temp.wValue[0] = 0; 3838 goto tr_valid; 3839 3840tr_handle_get_tt_state: 3841tr_handle_get_class_status: 3842tr_handle_get_iface_status: 3843tr_handle_get_ep_status: 3844 len = 2; 3845 USETW(sc->sc_hub_temp.wValue, 0); 3846 goto tr_valid; 3847 3848tr_handle_set_halt: 3849tr_handle_set_interface: 3850tr_handle_set_wakeup: 3851tr_handle_clear_wakeup: 3852tr_handle_clear_halt: 3853 goto tr_valid; 3854 3855tr_handle_clear_port_feature: 3856 if (index != 1) { 3857 goto tr_stalled; 3858 } 3859 DPRINTFN(8, "UR_CLEAR_PORT_FEATURE on port %d\n", index); 3860 3861 switch (value) { 3862 case UHF_PORT_SUSPEND: 3863 if (sc->sc_mode == MUSB2_HOST_MODE) 3864 musbotg_wakeup_host(sc); 3865 else 3866 musbotg_wakeup_peer(sc); 3867 break; 3868 3869 case UHF_PORT_ENABLE: 3870 sc->sc_flags.port_enabled = 0; 3871 break; 3872 3873 case UHF_C_PORT_ENABLE: 3874 sc->sc_flags.change_enabled = 0; 3875 break; 3876 3877 case UHF_C_PORT_OVER_CURRENT: 3878 sc->sc_flags.change_over_current = 0; 3879 break; 3880 3881 case UHF_C_PORT_RESET: 3882 sc->sc_flags.change_reset = 0; 3883 break; 3884 3885 case UHF_PORT_TEST: 3886 case UHF_PORT_INDICATOR: 3887 /* nops */ 3888 break; 3889 3890 case UHF_PORT_POWER: 3891 sc->sc_flags.port_powered = 0; 3892 musbotg_pull_down(sc); 3893 musbotg_clocks_off(sc); 3894 break; 3895 case UHF_C_PORT_CONNECTION: 3896 sc->sc_flags.change_connect = 0; 3897 break; 3898 case UHF_C_PORT_SUSPEND: 3899 sc->sc_flags.change_suspend = 0; 3900 break; 3901 default: 3902 err = USB_ERR_IOERROR; 3903 goto done; 3904 } 3905 goto tr_valid; 3906 3907tr_handle_set_port_feature: 3908 if (index != 1) { 3909 goto tr_stalled; 3910 } 3911 DPRINTFN(8, "UR_SET_PORT_FEATURE\n"); 3912 3913 switch (value) { 3914 case UHF_PORT_ENABLE: 3915 sc->sc_flags.port_enabled = 1; 3916 break; 3917 case UHF_PORT_SUSPEND: 3918 if (sc->sc_mode == MUSB2_HOST_MODE) 3919 musbotg_suspend_host(sc); 3920 break; 3921 3922 case UHF_PORT_RESET: 3923 if (sc->sc_mode == MUSB2_HOST_MODE) { 3924 reg = MUSB2_READ_1(sc, MUSB2_REG_POWER); 3925 reg |= MUSB2_MASK_RESET; 3926 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, reg); 3927 3928 /* Wait for 20 msec */ 3929 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 5); 3930 3931 reg = MUSB2_READ_1(sc, MUSB2_REG_POWER); 3932 reg &= ~MUSB2_MASK_RESET; 3933 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, reg); 3934 3935 /* determine line speed */ 3936 reg = MUSB2_READ_1(sc, MUSB2_REG_POWER); 3937 if (reg & MUSB2_MASK_HSMODE) 3938 sc->sc_flags.status_high_speed = 1; 3939 else 3940 sc->sc_flags.status_high_speed = 0; 3941 3942 sc->sc_flags.change_reset = 1; 3943 } else 3944 err = USB_ERR_IOERROR; 3945 break; 3946 3947 case UHF_PORT_TEST: 3948 case UHF_PORT_INDICATOR: 3949 /* nops */ 3950 break; 3951 case UHF_PORT_POWER: 3952 sc->sc_flags.port_powered = 1; 3953 break; 3954 default: 3955 err = USB_ERR_IOERROR; 3956 goto done; 3957 } 3958 goto tr_valid; 3959 3960tr_handle_get_port_status: 3961 3962 DPRINTFN(8, "UR_GET_PORT_STATUS\n"); 3963 3964 if (index != 1) { 3965 goto tr_stalled; 3966 } 3967 if (sc->sc_flags.status_vbus) { 3968 musbotg_clocks_on(sc); 3969 musbotg_pull_up(sc); 3970 } else { 3971 musbotg_pull_down(sc); 3972 musbotg_clocks_off(sc); 3973 } 3974 3975 /* Select Device Side Mode */ 3976 if (sc->sc_mode == MUSB2_DEVICE_MODE) 3977 value = UPS_PORT_MODE_DEVICE; 3978 else 3979 value = 0; 3980 3981 if (sc->sc_flags.status_high_speed) { 3982 value |= UPS_HIGH_SPEED; 3983 } 3984 if (sc->sc_flags.port_powered) { 3985 value |= UPS_PORT_POWER; 3986 } 3987 if (sc->sc_flags.port_enabled) { 3988 value |= UPS_PORT_ENABLED; 3989 } 3990 3991 if (sc->sc_flags.port_over_current) 3992 value |= UPS_OVERCURRENT_INDICATOR; 3993 3994 if (sc->sc_flags.status_vbus && 3995 sc->sc_flags.status_bus_reset) { 3996 value |= UPS_CURRENT_CONNECT_STATUS; 3997 } 3998 if (sc->sc_flags.status_suspend) { 3999 value |= UPS_SUSPEND; 4000 } 4001 USETW(sc->sc_hub_temp.ps.wPortStatus, value); 4002 4003 value = 0; 4004 4005 if (sc->sc_flags.change_connect) { 4006 value |= UPS_C_CONNECT_STATUS; 4007 4008 if (sc->sc_mode == MUSB2_DEVICE_MODE) { 4009 if (sc->sc_flags.status_vbus && 4010 sc->sc_flags.status_bus_reset) { 4011 /* reset EP0 state */ 4012 sc->sc_ep0_busy = 0; 4013 sc->sc_ep0_cmd = 0; 4014 } 4015 } 4016 } 4017 if (sc->sc_flags.change_suspend) 4018 value |= UPS_C_SUSPEND; 4019 if (sc->sc_flags.change_reset) 4020 value |= UPS_C_PORT_RESET; 4021 if (sc->sc_flags.change_over_current) 4022 value |= UPS_C_OVERCURRENT_INDICATOR; 4023 4024 USETW(sc->sc_hub_temp.ps.wPortChange, value); 4025 len = sizeof(sc->sc_hub_temp.ps); 4026 goto tr_valid; 4027 4028tr_handle_get_class_descriptor: 4029 if (value & 0xFF) { 4030 goto tr_stalled; 4031 } 4032 ptr = (const void *)&musbotg_hubd; 4033 len = sizeof(musbotg_hubd); 4034 goto tr_valid; 4035 4036tr_stalled: 4037 err = USB_ERR_STALLED; 4038tr_valid: 4039done: 4040 *plength = len; 4041 *pptr = ptr; 4042 return (err); 4043} 4044 4045static void 4046musbotg_xfer_setup(struct usb_setup_params *parm) 4047{ 4048 struct musbotg_softc *sc; 4049 struct usb_xfer *xfer; 4050 void *last_obj; 4051 uint32_t ntd; 4052 uint32_t n; 4053 uint8_t ep_no; 4054 4055 sc = MUSBOTG_BUS2SC(parm->udev->bus); 4056 xfer = parm->curr_xfer; 4057 4058 /* 4059 * NOTE: This driver does not use any of the parameters that 4060 * are computed from the following values. Just set some 4061 * reasonable dummies: 4062 */ 4063 parm->hc_max_packet_size = 0x400; 4064 parm->hc_max_frame_size = 0xc00; 4065 4066 if ((parm->methods == &musbotg_device_isoc_methods) || 4067 (parm->methods == &musbotg_device_intr_methods)) 4068 parm->hc_max_packet_count = 3; 4069 else 4070 parm->hc_max_packet_count = 1; 4071 4072 usbd_transfer_setup_sub(parm); 4073 4074 /* 4075 * compute maximum number of TDs 4076 */ 4077 if (parm->methods == &musbotg_device_ctrl_methods) { 4078 4079 ntd = xfer->nframes + 1 /* STATUS */ + 1 /* SYNC */ ; 4080 4081 } else if (parm->methods == &musbotg_device_bulk_methods) { 4082 4083 ntd = xfer->nframes + 1 /* SYNC */ ; 4084 4085 } else if (parm->methods == &musbotg_device_intr_methods) { 4086 4087 ntd = xfer->nframes + 1 /* SYNC */ ; 4088 4089 } else if (parm->methods == &musbotg_device_isoc_methods) { 4090 4091 ntd = xfer->nframes + 1 /* SYNC */ ; 4092 4093 } else { 4094 4095 ntd = 0; 4096 } 4097 4098 /* 4099 * check if "usbd_transfer_setup_sub" set an error 4100 */ 4101 if (parm->err) { 4102 return; 4103 } 4104 /* 4105 * allocate transfer descriptors 4106 */ 4107 last_obj = NULL; 4108 4109 ep_no = xfer->endpointno & UE_ADDR; 4110 4111 /* 4112 * Check for a valid endpoint profile in USB device mode: 4113 */ 4114 if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) { 4115 const struct usb_hw_ep_profile *pf; 4116 4117 musbotg_get_hw_ep_profile(parm->udev, &pf, ep_no); 4118 4119 if (pf == NULL) { 4120 /* should not happen */ 4121 parm->err = USB_ERR_INVAL; 4122 return; 4123 } 4124 } 4125 4126 /* align data */ 4127 parm->size[0] += ((-parm->size[0]) & (USB_HOST_ALIGN - 1)); 4128 4129 for (n = 0; n != ntd; n++) { 4130 4131 struct musbotg_td *td; 4132 4133 if (parm->buf) { 4134 4135 td = USB_ADD_BYTES(parm->buf, parm->size[0]); 4136 4137 /* init TD */ 4138 td->max_frame_size = xfer->max_frame_size; 4139 td->reg_max_packet = xfer->max_packet_size | 4140 ((xfer->max_packet_count - 1) << 11); 4141 td->ep_no = ep_no; 4142 td->obj_next = last_obj; 4143 4144 last_obj = td; 4145 } 4146 parm->size[0] += sizeof(*td); 4147 } 4148 4149 xfer->td_start[0] = last_obj; 4150} 4151 4152static void 4153musbotg_xfer_unsetup(struct usb_xfer *xfer) 4154{ 4155 return; 4156} 4157 4158static void 4159musbotg_get_dma_delay(struct usb_device *udev, uint32_t *pus) 4160{ 4161 struct musbotg_softc *sc = MUSBOTG_BUS2SC(udev->bus); 4162 4163 if (sc->sc_mode == MUSB2_HOST_MODE) 4164 *pus = 2000; /* microseconds */ 4165 else 4166 *pus = 0; 4167} 4168 4169static void 4170musbotg_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc, 4171 struct usb_endpoint *ep) 4172{ 4173 struct musbotg_softc *sc = MUSBOTG_BUS2SC(udev->bus); 4174 4175 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d (%d)\n", 4176 ep, udev->address, 4177 edesc->bEndpointAddress, udev->flags.usb_mode, 4178 sc->sc_rt_addr); 4179 4180 if (udev->device_index != sc->sc_rt_addr) { 4181 switch (edesc->bmAttributes & UE_XFERTYPE) { 4182 case UE_CONTROL: 4183 ep->methods = &musbotg_device_ctrl_methods; 4184 break; 4185 case UE_INTERRUPT: 4186 ep->methods = &musbotg_device_intr_methods; 4187 break; 4188 case UE_ISOCHRONOUS: 4189 ep->methods = &musbotg_device_isoc_methods; 4190 break; 4191 case UE_BULK: 4192 ep->methods = &musbotg_device_bulk_methods; 4193 break; 4194 default: 4195 /* do nothing */ 4196 break; 4197 } 4198 } 4199} 4200 4201static void 4202musbotg_set_hw_power_sleep(struct usb_bus *bus, uint32_t state) 4203{ 4204 struct musbotg_softc *sc = MUSBOTG_BUS2SC(bus); 4205 4206 switch (state) { 4207 case USB_HW_POWER_SUSPEND: 4208 musbotg_suspend(sc); 4209 break; 4210 case USB_HW_POWER_SHUTDOWN: 4211 musbotg_uninit(sc); 4212 break; 4213 case USB_HW_POWER_RESUME: 4214 musbotg_resume(sc); 4215 break; 4216 default: 4217 break; 4218 } 4219} 4220 4221struct usb_bus_methods musbotg_bus_methods = 4222{ 4223 .endpoint_init = &musbotg_ep_init, 4224 .get_dma_delay = &musbotg_get_dma_delay, 4225 .xfer_setup = &musbotg_xfer_setup, 4226 .xfer_unsetup = &musbotg_xfer_unsetup, 4227 .get_hw_ep_profile = &musbotg_get_hw_ep_profile, 4228 .set_stall = &musbotg_set_stall, 4229 .clear_stall = &musbotg_clear_stall, 4230 .roothub_exec = &musbotg_roothub_exec, 4231 .xfer_poll = &musbotg_do_poll, 4232 .set_hw_power_sleep = &musbotg_set_hw_power_sleep, 4233}; 4234