musb_otg.c revision 257040
1/* $FreeBSD: stable/9/sys/dev/usb/controller/musb_otg.c 257040 2013-10-24 06:06:17Z hselasky $ */ 2/*- 3 * Copyright (c) 2008 Hans Petter Selasky. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27/* 28 * Thanks to Mentor Graphics for providing a reference driver for this USB chip 29 * at their homepage. 30 */ 31 32/* 33 * This file contains the driver for the Mentor Graphics Inventra USB 34 * 2.0 High Speed Dual-Role controller. 35 * 36 * NOTE: The current implementation only supports Device Side Mode! 37 */ 38 39#include <sys/stdint.h> 40#include <sys/stddef.h> 41#include <sys/param.h> 42#include <sys/queue.h> 43#include <sys/types.h> 44#include <sys/systm.h> 45#include <sys/kernel.h> 46#include <sys/bus.h> 47#include <sys/module.h> 48#include <sys/lock.h> 49#include <sys/mutex.h> 50#include <sys/condvar.h> 51#include <sys/sysctl.h> 52#include <sys/sx.h> 53#include <sys/unistd.h> 54#include <sys/callout.h> 55#include <sys/malloc.h> 56#include <sys/priv.h> 57 58#include <dev/usb/usb.h> 59#include <dev/usb/usbdi.h> 60 61#define USB_DEBUG_VAR musbotgdebug 62 63#include <dev/usb/usb_core.h> 64#include <dev/usb/usb_debug.h> 65#include <dev/usb/usb_busdma.h> 66#include <dev/usb/usb_process.h> 67#include <dev/usb/usb_transfer.h> 68#include <dev/usb/usb_device.h> 69#include <dev/usb/usb_hub.h> 70#include <dev/usb/usb_util.h> 71 72#include <dev/usb/usb_controller.h> 73#include <dev/usb/usb_bus.h> 74#include <dev/usb/controller/musb_otg.h> 75 76#define MUSBOTG_INTR_ENDPT 1 77 78#define MUSBOTG_BUS2SC(bus) \ 79 ((struct musbotg_softc *)(((uint8_t *)(bus)) - \ 80 USB_P2U(&(((struct musbotg_softc *)0)->sc_bus)))) 81 82#define MUSBOTG_PC2SC(pc) \ 83 MUSBOTG_BUS2SC(USB_DMATAG_TO_XROOT((pc)->tag_parent)->bus) 84 85#ifdef USB_DEBUG 86static int musbotgdebug = 0; 87 88static SYSCTL_NODE(_hw_usb, OID_AUTO, musbotg, CTLFLAG_RW, 0, "USB musbotg"); 89SYSCTL_INT(_hw_usb_musbotg, OID_AUTO, debug, CTLFLAG_RW, 90 &musbotgdebug, 0, "Debug level"); 91#endif 92 93/* prototypes */ 94 95struct usb_bus_methods musbotg_bus_methods; 96struct usb_pipe_methods musbotg_device_bulk_methods; 97struct usb_pipe_methods musbotg_device_ctrl_methods; 98struct usb_pipe_methods musbotg_device_intr_methods; 99struct usb_pipe_methods musbotg_device_isoc_methods; 100 101static musbotg_cmd_t musbotg_setup_rx; 102static musbotg_cmd_t musbotg_setup_data_rx; 103static musbotg_cmd_t musbotg_setup_data_tx; 104static musbotg_cmd_t musbotg_setup_status; 105static musbotg_cmd_t musbotg_data_rx; 106static musbotg_cmd_t musbotg_data_tx; 107static void musbotg_device_done(struct usb_xfer *, usb_error_t); 108static void musbotg_do_poll(struct usb_bus *); 109static void musbotg_standard_done(struct usb_xfer *); 110static void musbotg_interrupt_poll(struct musbotg_softc *); 111static void musbotg_root_intr(struct musbotg_softc *); 112 113/* 114 * Here is a configuration that the chip supports. 115 */ 116static const struct usb_hw_ep_profile musbotg_ep_profile[1] = { 117 118 [0] = { 119 .max_in_frame_size = 64,/* fixed */ 120 .max_out_frame_size = 64, /* fixed */ 121 .is_simplex = 1, 122 .support_control = 1, 123 } 124}; 125 126static void 127musbotg_get_hw_ep_profile(struct usb_device *udev, 128 const struct usb_hw_ep_profile **ppf, uint8_t ep_addr) 129{ 130 struct musbotg_softc *sc; 131 132 sc = MUSBOTG_BUS2SC(udev->bus); 133 134 if (ep_addr == 0) { 135 /* control endpoint */ 136 *ppf = musbotg_ep_profile; 137 } else if (ep_addr <= sc->sc_ep_max) { 138 /* other endpoints */ 139 *ppf = sc->sc_hw_ep_profile + ep_addr; 140 } else { 141 *ppf = NULL; 142 } 143} 144 145static void 146musbotg_clocks_on(struct musbotg_softc *sc) 147{ 148 if (sc->sc_flags.clocks_off && 149 sc->sc_flags.port_powered) { 150 151 DPRINTFN(4, "\n"); 152 153 if (sc->sc_clocks_on) { 154 (sc->sc_clocks_on) (sc->sc_clocks_arg); 155 } 156 sc->sc_flags.clocks_off = 0; 157 158 /* XXX enable Transceiver */ 159 } 160} 161 162static void 163musbotg_clocks_off(struct musbotg_softc *sc) 164{ 165 if (!sc->sc_flags.clocks_off) { 166 167 DPRINTFN(4, "\n"); 168 169 /* XXX disable Transceiver */ 170 171 if (sc->sc_clocks_off) { 172 (sc->sc_clocks_off) (sc->sc_clocks_arg); 173 } 174 sc->sc_flags.clocks_off = 1; 175 } 176} 177 178static void 179musbotg_pull_common(struct musbotg_softc *sc, uint8_t on) 180{ 181 uint8_t temp; 182 183 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER); 184 if (on) 185 temp |= MUSB2_MASK_SOFTC; 186 else 187 temp &= ~MUSB2_MASK_SOFTC; 188 189 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp); 190} 191 192static void 193musbotg_pull_up(struct musbotg_softc *sc) 194{ 195 /* pullup D+, if possible */ 196 197 if (!sc->sc_flags.d_pulled_up && 198 sc->sc_flags.port_powered) { 199 sc->sc_flags.d_pulled_up = 1; 200 musbotg_pull_common(sc, 1); 201 } 202} 203 204static void 205musbotg_pull_down(struct musbotg_softc *sc) 206{ 207 /* pulldown D+, if possible */ 208 209 if (sc->sc_flags.d_pulled_up) { 210 sc->sc_flags.d_pulled_up = 0; 211 musbotg_pull_common(sc, 0); 212 } 213} 214 215static void 216musbotg_wakeup_peer(struct musbotg_softc *sc) 217{ 218 uint8_t temp; 219 220 if (!(sc->sc_flags.status_suspend)) { 221 return; 222 } 223 224 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER); 225 temp |= MUSB2_MASK_RESUME; 226 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp); 227 228 /* wait 8 milliseconds */ 229 /* Wait for reset to complete. */ 230 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 125); 231 232 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER); 233 temp &= ~MUSB2_MASK_RESUME; 234 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp); 235} 236 237static void 238musbotg_set_address(struct musbotg_softc *sc, uint8_t addr) 239{ 240 DPRINTFN(4, "addr=%d\n", addr); 241 addr &= 0x7F; 242 MUSB2_WRITE_1(sc, MUSB2_REG_FADDR, addr); 243} 244 245static uint8_t 246musbotg_setup_rx(struct musbotg_td *td) 247{ 248 struct musbotg_softc *sc; 249 struct usb_device_request req; 250 uint16_t count; 251 uint8_t csr; 252 253 /* get pointer to softc */ 254 sc = MUSBOTG_PC2SC(td->pc); 255 256 /* select endpoint 0 */ 257 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); 258 259 /* read out FIFO status */ 260 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 261 262 DPRINTFN(4, "csr=0x%02x\n", csr); 263 264 /* 265 * NOTE: If DATAEND is set we should not call the 266 * callback, hence the status stage is not complete. 267 */ 268 if (csr & MUSB2_MASK_CSR0L_DATAEND) { 269 /* do not stall at this point */ 270 td->did_stall = 1; 271 /* wait for interrupt */ 272 goto not_complete; 273 } 274 if (csr & MUSB2_MASK_CSR0L_SENTSTALL) { 275 /* clear SENTSTALL */ 276 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0); 277 /* get latest status */ 278 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 279 /* update EP0 state */ 280 sc->sc_ep0_busy = 0; 281 } 282 if (csr & MUSB2_MASK_CSR0L_SETUPEND) { 283 /* clear SETUPEND */ 284 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 285 MUSB2_MASK_CSR0L_SETUPEND_CLR); 286 /* get latest status */ 287 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 288 /* update EP0 state */ 289 sc->sc_ep0_busy = 0; 290 } 291 if (sc->sc_ep0_busy) { 292 goto not_complete; 293 } 294 if (!(csr & MUSB2_MASK_CSR0L_RXPKTRDY)) { 295 goto not_complete; 296 } 297 /* clear did stall flag */ 298 td->did_stall = 0; 299 /* get the packet byte count */ 300 count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT); 301 302 /* verify data length */ 303 if (count != td->remainder) { 304 DPRINTFN(0, "Invalid SETUP packet " 305 "length, %d bytes\n", count); 306 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 307 MUSB2_MASK_CSR0L_RXPKTRDY_CLR); 308 goto not_complete; 309 } 310 if (count != sizeof(req)) { 311 DPRINTFN(0, "Unsupported SETUP packet " 312 "length, %d bytes\n", count); 313 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 314 MUSB2_MASK_CSR0L_RXPKTRDY_CLR); 315 goto not_complete; 316 } 317 /* receive data */ 318 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 319 MUSB2_REG_EPFIFO(0), (void *)&req, sizeof(req)); 320 321 /* copy data into real buffer */ 322 usbd_copy_in(td->pc, 0, &req, sizeof(req)); 323 324 td->offset = sizeof(req); 325 td->remainder = 0; 326 327 /* set pending command */ 328 sc->sc_ep0_cmd = MUSB2_MASK_CSR0L_RXPKTRDY_CLR; 329 330 /* we need set stall or dataend after this */ 331 sc->sc_ep0_busy = 1; 332 333 /* sneak peek the set address */ 334 if ((req.bmRequestType == UT_WRITE_DEVICE) && 335 (req.bRequest == UR_SET_ADDRESS)) { 336 sc->sc_dv_addr = req.wValue[0] & 0x7F; 337 } else { 338 sc->sc_dv_addr = 0xFF; 339 } 340 return (0); /* complete */ 341 342not_complete: 343 /* abort any ongoing transfer */ 344 if (!td->did_stall) { 345 DPRINTFN(4, "stalling\n"); 346 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 347 MUSB2_MASK_CSR0L_SENDSTALL); 348 td->did_stall = 1; 349 } 350 return (1); /* not complete */ 351} 352 353/* Control endpoint only data handling functions (RX/TX/SYNC) */ 354 355static uint8_t 356musbotg_setup_data_rx(struct musbotg_td *td) 357{ 358 struct usb_page_search buf_res; 359 struct musbotg_softc *sc; 360 uint16_t count; 361 uint8_t csr; 362 uint8_t got_short; 363 364 /* get pointer to softc */ 365 sc = MUSBOTG_PC2SC(td->pc); 366 367 /* select endpoint 0 */ 368 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); 369 370 /* check if a command is pending */ 371 if (sc->sc_ep0_cmd) { 372 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, sc->sc_ep0_cmd); 373 sc->sc_ep0_cmd = 0; 374 } 375 /* read out FIFO status */ 376 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 377 378 DPRINTFN(4, "csr=0x%02x\n", csr); 379 380 got_short = 0; 381 382 if (csr & (MUSB2_MASK_CSR0L_SETUPEND | 383 MUSB2_MASK_CSR0L_SENTSTALL)) { 384 if (td->remainder == 0) { 385 /* 386 * We are actually complete and have 387 * received the next SETUP 388 */ 389 DPRINTFN(4, "faking complete\n"); 390 return (0); /* complete */ 391 } 392 /* 393 * USB Host Aborted the transfer. 394 */ 395 td->error = 1; 396 return (0); /* complete */ 397 } 398 if (!(csr & MUSB2_MASK_CSR0L_RXPKTRDY)) { 399 return (1); /* not complete */ 400 } 401 /* get the packet byte count */ 402 count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT); 403 404 /* verify the packet byte count */ 405 if (count != td->max_frame_size) { 406 if (count < td->max_frame_size) { 407 /* we have a short packet */ 408 td->short_pkt = 1; 409 got_short = 1; 410 } else { 411 /* invalid USB packet */ 412 td->error = 1; 413 return (0); /* we are complete */ 414 } 415 } 416 /* verify the packet byte count */ 417 if (count > td->remainder) { 418 /* invalid USB packet */ 419 td->error = 1; 420 return (0); /* we are complete */ 421 } 422 while (count > 0) { 423 uint32_t temp; 424 425 usbd_get_page(td->pc, td->offset, &buf_res); 426 427 /* get correct length */ 428 if (buf_res.length > count) { 429 buf_res.length = count; 430 } 431 /* check for unaligned memory address */ 432 if (USB_P2U(buf_res.buffer) & 3) { 433 434 temp = count & ~3; 435 436 if (temp) { 437 /* receive data 4 bytes at a time */ 438 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 439 MUSB2_REG_EPFIFO(0), sc->sc_bounce_buf, 440 temp / 4); 441 } 442 temp = count & 3; 443 if (temp) { 444 /* receive data 1 byte at a time */ 445 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 446 MUSB2_REG_EPFIFO(0), 447 (void *)(&sc->sc_bounce_buf[count / 4]), temp); 448 } 449 usbd_copy_in(td->pc, td->offset, 450 sc->sc_bounce_buf, count); 451 452 /* update offset and remainder */ 453 td->offset += count; 454 td->remainder -= count; 455 break; 456 } 457 /* check if we can optimise */ 458 if (buf_res.length >= 4) { 459 460 /* receive data 4 bytes at a time */ 461 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 462 MUSB2_REG_EPFIFO(0), buf_res.buffer, 463 buf_res.length / 4); 464 465 temp = buf_res.length & ~3; 466 467 /* update counters */ 468 count -= temp; 469 td->offset += temp; 470 td->remainder -= temp; 471 continue; 472 } 473 /* receive data */ 474 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 475 MUSB2_REG_EPFIFO(0), buf_res.buffer, buf_res.length); 476 477 /* update counters */ 478 count -= buf_res.length; 479 td->offset += buf_res.length; 480 td->remainder -= buf_res.length; 481 } 482 483 /* check if we are complete */ 484 if ((td->remainder == 0) || got_short) { 485 if (td->short_pkt) { 486 /* we are complete */ 487 sc->sc_ep0_cmd = MUSB2_MASK_CSR0L_RXPKTRDY_CLR; 488 return (0); 489 } 490 /* else need to receive a zero length packet */ 491 } 492 /* write command - need more data */ 493 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 494 MUSB2_MASK_CSR0L_RXPKTRDY_CLR); 495 return (1); /* not complete */ 496} 497 498static uint8_t 499musbotg_setup_data_tx(struct musbotg_td *td) 500{ 501 struct usb_page_search buf_res; 502 struct musbotg_softc *sc; 503 uint16_t count; 504 uint8_t csr; 505 506 /* get pointer to softc */ 507 sc = MUSBOTG_PC2SC(td->pc); 508 509 /* select endpoint 0 */ 510 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); 511 512 /* check if a command is pending */ 513 if (sc->sc_ep0_cmd) { 514 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, sc->sc_ep0_cmd); 515 sc->sc_ep0_cmd = 0; 516 } 517 /* read out FIFO status */ 518 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 519 520 DPRINTFN(4, "csr=0x%02x\n", csr); 521 522 if (csr & (MUSB2_MASK_CSR0L_SETUPEND | 523 MUSB2_MASK_CSR0L_SENTSTALL)) { 524 /* 525 * The current transfer was aborted 526 * by the USB Host 527 */ 528 td->error = 1; 529 return (0); /* complete */ 530 } 531 if (csr & MUSB2_MASK_CSR0L_TXPKTRDY) { 532 return (1); /* not complete */ 533 } 534 count = td->max_frame_size; 535 if (td->remainder < count) { 536 /* we have a short packet */ 537 td->short_pkt = 1; 538 count = td->remainder; 539 } 540 while (count > 0) { 541 uint32_t temp; 542 543 usbd_get_page(td->pc, td->offset, &buf_res); 544 545 /* get correct length */ 546 if (buf_res.length > count) { 547 buf_res.length = count; 548 } 549 /* check for unaligned memory address */ 550 if (USB_P2U(buf_res.buffer) & 3) { 551 552 usbd_copy_out(td->pc, td->offset, 553 sc->sc_bounce_buf, count); 554 555 temp = count & ~3; 556 557 if (temp) { 558 /* transmit data 4 bytes at a time */ 559 bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 560 MUSB2_REG_EPFIFO(0), sc->sc_bounce_buf, 561 temp / 4); 562 } 563 temp = count & 3; 564 if (temp) { 565 /* receive data 1 byte at a time */ 566 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 567 MUSB2_REG_EPFIFO(0), 568 ((void *)&sc->sc_bounce_buf[count / 4]), temp); 569 } 570 /* update offset and remainder */ 571 td->offset += count; 572 td->remainder -= count; 573 break; 574 } 575 /* check if we can optimise */ 576 if (buf_res.length >= 4) { 577 578 /* transmit data 4 bytes at a time */ 579 bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 580 MUSB2_REG_EPFIFO(0), buf_res.buffer, 581 buf_res.length / 4); 582 583 temp = buf_res.length & ~3; 584 585 /* update counters */ 586 count -= temp; 587 td->offset += temp; 588 td->remainder -= temp; 589 continue; 590 } 591 /* transmit data */ 592 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 593 MUSB2_REG_EPFIFO(0), buf_res.buffer, buf_res.length); 594 595 /* update counters */ 596 count -= buf_res.length; 597 td->offset += buf_res.length; 598 td->remainder -= buf_res.length; 599 } 600 601 /* check remainder */ 602 if (td->remainder == 0) { 603 if (td->short_pkt) { 604 sc->sc_ep0_cmd = MUSB2_MASK_CSR0L_TXPKTRDY; 605 return (0); /* complete */ 606 } 607 /* else we need to transmit a short packet */ 608 } 609 /* write command */ 610 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 611 MUSB2_MASK_CSR0L_TXPKTRDY); 612 613 return (1); /* not complete */ 614} 615 616static uint8_t 617musbotg_setup_status(struct musbotg_td *td) 618{ 619 struct musbotg_softc *sc; 620 uint8_t csr; 621 622 /* get pointer to softc */ 623 sc = MUSBOTG_PC2SC(td->pc); 624 625 /* select endpoint 0 */ 626 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); 627 628 if (sc->sc_ep0_busy) { 629 sc->sc_ep0_busy = 0; 630 sc->sc_ep0_cmd |= MUSB2_MASK_CSR0L_DATAEND; 631 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, sc->sc_ep0_cmd); 632 sc->sc_ep0_cmd = 0; 633 } 634 /* read out FIFO status */ 635 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 636 637 DPRINTFN(4, "csr=0x%02x\n", csr); 638 639 if (csr & MUSB2_MASK_CSR0L_DATAEND) { 640 /* wait for interrupt */ 641 return (1); /* not complete */ 642 } 643 if (sc->sc_dv_addr != 0xFF) { 644 /* write function address */ 645 musbotg_set_address(sc, sc->sc_dv_addr); 646 } 647 return (0); /* complete */ 648} 649 650static uint8_t 651musbotg_data_rx(struct musbotg_td *td) 652{ 653 struct usb_page_search buf_res; 654 struct musbotg_softc *sc; 655 uint16_t count; 656 uint8_t csr; 657 uint8_t to; 658 uint8_t got_short; 659 660 to = 8; /* don't loop forever! */ 661 got_short = 0; 662 663 /* get pointer to softc */ 664 sc = MUSBOTG_PC2SC(td->pc); 665 666 /* select endpoint */ 667 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, td->ep_no); 668 669repeat: 670 /* read out FIFO status */ 671 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL); 672 673 DPRINTFN(4, "csr=0x%02x\n", csr); 674 675 /* clear overrun */ 676 if (csr & MUSB2_MASK_CSRL_RXOVERRUN) { 677 /* make sure we don't clear "RXPKTRDY" */ 678 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 679 MUSB2_MASK_CSRL_RXPKTRDY); 680 } 681 /* check status */ 682 if (!(csr & MUSB2_MASK_CSRL_RXPKTRDY)) { 683 return (1); /* not complete */ 684 } 685 /* get the packet byte count */ 686 count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT); 687 688 DPRINTFN(4, "count=0x%04x\n", count); 689 690 /* 691 * Check for short or invalid packet: 692 */ 693 if (count != td->max_frame_size) { 694 if (count < td->max_frame_size) { 695 /* we have a short packet */ 696 td->short_pkt = 1; 697 got_short = 1; 698 } else { 699 /* invalid USB packet */ 700 td->error = 1; 701 return (0); /* we are complete */ 702 } 703 } 704 /* verify the packet byte count */ 705 if (count > td->remainder) { 706 /* invalid USB packet */ 707 td->error = 1; 708 return (0); /* we are complete */ 709 } 710 while (count > 0) { 711 uint32_t temp; 712 713 usbd_get_page(td->pc, td->offset, &buf_res); 714 715 /* get correct length */ 716 if (buf_res.length > count) { 717 buf_res.length = count; 718 } 719 /* check for unaligned memory address */ 720 if (USB_P2U(buf_res.buffer) & 3) { 721 722 temp = count & ~3; 723 724 if (temp) { 725 /* receive data 4 bytes at a time */ 726 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 727 MUSB2_REG_EPFIFO(td->ep_no), sc->sc_bounce_buf, 728 temp / 4); 729 } 730 temp = count & 3; 731 if (temp) { 732 /* receive data 1 byte at a time */ 733 bus_space_read_multi_1(sc->sc_io_tag, 734 sc->sc_io_hdl, MUSB2_REG_EPFIFO(td->ep_no), 735 ((void *)&sc->sc_bounce_buf[count / 4]), temp); 736 } 737 usbd_copy_in(td->pc, td->offset, 738 sc->sc_bounce_buf, count); 739 740 /* update offset and remainder */ 741 td->offset += count; 742 td->remainder -= count; 743 break; 744 } 745 /* check if we can optimise */ 746 if (buf_res.length >= 4) { 747 748 /* receive data 4 bytes at a time */ 749 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 750 MUSB2_REG_EPFIFO(td->ep_no), buf_res.buffer, 751 buf_res.length / 4); 752 753 temp = buf_res.length & ~3; 754 755 /* update counters */ 756 count -= temp; 757 td->offset += temp; 758 td->remainder -= temp; 759 continue; 760 } 761 /* receive data */ 762 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 763 MUSB2_REG_EPFIFO(td->ep_no), buf_res.buffer, 764 buf_res.length); 765 766 /* update counters */ 767 count -= buf_res.length; 768 td->offset += buf_res.length; 769 td->remainder -= buf_res.length; 770 } 771 772 /* clear status bits */ 773 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 0); 774 775 /* check if we are complete */ 776 if ((td->remainder == 0) || got_short) { 777 if (td->short_pkt) { 778 /* we are complete */ 779 return (0); 780 } 781 /* else need to receive a zero length packet */ 782 } 783 if (--to) { 784 goto repeat; 785 } 786 return (1); /* not complete */ 787} 788 789static uint8_t 790musbotg_data_tx(struct musbotg_td *td) 791{ 792 struct usb_page_search buf_res; 793 struct musbotg_softc *sc; 794 uint16_t count; 795 uint8_t csr; 796 uint8_t to; 797 798 to = 8; /* don't loop forever! */ 799 800 /* get pointer to softc */ 801 sc = MUSBOTG_PC2SC(td->pc); 802 803 /* select endpoint */ 804 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, td->ep_no); 805 806repeat: 807 808 /* read out FIFO status */ 809 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 810 811 DPRINTFN(4, "csr=0x%02x\n", csr); 812 813 if (csr & (MUSB2_MASK_CSRL_TXINCOMP | 814 MUSB2_MASK_CSRL_TXUNDERRUN)) { 815 /* clear status bits */ 816 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0); 817 } 818 if (csr & MUSB2_MASK_CSRL_TXPKTRDY) { 819 return (1); /* not complete */ 820 } 821 /* check for short packet */ 822 count = td->max_frame_size; 823 if (td->remainder < count) { 824 /* we have a short packet */ 825 td->short_pkt = 1; 826 count = td->remainder; 827 } 828 while (count > 0) { 829 uint32_t temp; 830 831 usbd_get_page(td->pc, td->offset, &buf_res); 832 833 /* get correct length */ 834 if (buf_res.length > count) { 835 buf_res.length = count; 836 } 837 /* check for unaligned memory address */ 838 if (USB_P2U(buf_res.buffer) & 3) { 839 840 usbd_copy_out(td->pc, td->offset, 841 sc->sc_bounce_buf, count); 842 843 temp = count & ~3; 844 845 if (temp) { 846 /* transmit data 4 bytes at a time */ 847 bus_space_write_multi_4(sc->sc_io_tag, 848 sc->sc_io_hdl, MUSB2_REG_EPFIFO(td->ep_no), 849 sc->sc_bounce_buf, temp / 4); 850 } 851 temp = count & 3; 852 if (temp) { 853 /* receive data 1 byte at a time */ 854 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 855 MUSB2_REG_EPFIFO(td->ep_no), 856 ((void *)&sc->sc_bounce_buf[count / 4]), temp); 857 } 858 /* update offset and remainder */ 859 td->offset += count; 860 td->remainder -= count; 861 break; 862 } 863 /* check if we can optimise */ 864 if (buf_res.length >= 4) { 865 866 /* transmit data 4 bytes at a time */ 867 bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 868 MUSB2_REG_EPFIFO(td->ep_no), buf_res.buffer, 869 buf_res.length / 4); 870 871 temp = buf_res.length & ~3; 872 873 /* update counters */ 874 count -= temp; 875 td->offset += temp; 876 td->remainder -= temp; 877 continue; 878 } 879 /* transmit data */ 880 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 881 MUSB2_REG_EPFIFO(td->ep_no), buf_res.buffer, 882 buf_res.length); 883 884 /* update counters */ 885 count -= buf_res.length; 886 td->offset += buf_res.length; 887 td->remainder -= buf_res.length; 888 } 889 890 /* write command */ 891 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 892 MUSB2_MASK_CSRL_TXPKTRDY); 893 894 /* check remainder */ 895 if (td->remainder == 0) { 896 if (td->short_pkt) { 897 return (0); /* complete */ 898 } 899 /* else we need to transmit a short packet */ 900 } 901 if (--to) { 902 goto repeat; 903 } 904 return (1); /* not complete */ 905} 906 907static uint8_t 908musbotg_xfer_do_fifo(struct usb_xfer *xfer) 909{ 910 struct musbotg_softc *sc; 911 struct musbotg_td *td; 912 913 DPRINTFN(8, "\n"); 914 915 td = xfer->td_transfer_cache; 916 while (1) { 917 if ((td->func) (td)) { 918 /* operation in progress */ 919 break; 920 } 921 if (((void *)td) == xfer->td_transfer_last) { 922 goto done; 923 } 924 if (td->error) { 925 goto done; 926 } else if (td->remainder > 0) { 927 /* 928 * We had a short transfer. If there is no alternate 929 * next, stop processing ! 930 */ 931 if (!td->alt_next) { 932 goto done; 933 } 934 } 935 /* 936 * Fetch the next transfer descriptor and transfer 937 * some flags to the next transfer descriptor 938 */ 939 td = td->obj_next; 940 xfer->td_transfer_cache = td; 941 } 942 return (1); /* not complete */ 943 944done: 945 sc = MUSBOTG_BUS2SC(xfer->xroot->bus); 946 947 /* compute all actual lengths */ 948 949 musbotg_standard_done(xfer); 950 951 return (0); /* complete */ 952} 953 954static void 955musbotg_interrupt_poll(struct musbotg_softc *sc) 956{ 957 struct usb_xfer *xfer; 958 959repeat: 960 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 961 if (!musbotg_xfer_do_fifo(xfer)) { 962 /* queue has been modified */ 963 goto repeat; 964 } 965 } 966} 967 968void 969musbotg_vbus_interrupt(struct musbotg_softc *sc, uint8_t is_on) 970{ 971 DPRINTFN(4, "vbus = %u\n", is_on); 972 973 USB_BUS_LOCK(&sc->sc_bus); 974 if (is_on) { 975 if (!sc->sc_flags.status_vbus) { 976 sc->sc_flags.status_vbus = 1; 977 978 /* complete root HUB interrupt endpoint */ 979 musbotg_root_intr(sc); 980 } 981 } else { 982 if (sc->sc_flags.status_vbus) { 983 sc->sc_flags.status_vbus = 0; 984 sc->sc_flags.status_bus_reset = 0; 985 sc->sc_flags.status_suspend = 0; 986 sc->sc_flags.change_suspend = 0; 987 sc->sc_flags.change_connect = 1; 988 989 /* complete root HUB interrupt endpoint */ 990 musbotg_root_intr(sc); 991 } 992 } 993 994 USB_BUS_UNLOCK(&sc->sc_bus); 995} 996 997void 998musbotg_interrupt(struct musbotg_softc *sc) 999{ 1000 uint16_t rx_status; 1001 uint16_t tx_status; 1002 uint8_t usb_status; 1003 uint8_t temp; 1004 uint8_t to = 2; 1005 1006 USB_BUS_LOCK(&sc->sc_bus); 1007 1008repeat: 1009 1010 /* read all interrupt registers */ 1011 usb_status = MUSB2_READ_1(sc, MUSB2_REG_INTUSB); 1012 1013 /* read all FIFO interrupts */ 1014 rx_status = MUSB2_READ_2(sc, MUSB2_REG_INTRX); 1015 tx_status = MUSB2_READ_2(sc, MUSB2_REG_INTTX); 1016 1017 /* check for any bus state change interrupts */ 1018 1019 if (usb_status & (MUSB2_MASK_IRESET | 1020 MUSB2_MASK_IRESUME | MUSB2_MASK_ISUSP)) { 1021 1022 DPRINTFN(4, "real bus interrupt 0x%08x\n", usb_status); 1023 1024 if (usb_status & MUSB2_MASK_IRESET) { 1025 1026 /* set correct state */ 1027 sc->sc_flags.status_bus_reset = 1; 1028 sc->sc_flags.status_suspend = 0; 1029 sc->sc_flags.change_suspend = 0; 1030 sc->sc_flags.change_connect = 1; 1031 1032 /* determine line speed */ 1033 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER); 1034 if (temp & MUSB2_MASK_HSMODE) 1035 sc->sc_flags.status_high_speed = 1; 1036 else 1037 sc->sc_flags.status_high_speed = 0; 1038 1039 /* 1040 * After reset all interrupts are on and we need to 1041 * turn them off! 1042 */ 1043 temp = MUSB2_MASK_IRESET; 1044 /* disable resume interrupt */ 1045 temp &= ~MUSB2_MASK_IRESUME; 1046 /* enable suspend interrupt */ 1047 temp |= MUSB2_MASK_ISUSP; 1048 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, temp); 1049 /* disable TX and RX interrupts */ 1050 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, 0); 1051 MUSB2_WRITE_2(sc, MUSB2_REG_INTRXE, 0); 1052 } 1053 /* 1054 * If RXRSM and RXSUSP is set at the same time we interpret 1055 * that like RESUME. Resume is set when there is at least 3 1056 * milliseconds of inactivity on the USB BUS. 1057 */ 1058 if (usb_status & MUSB2_MASK_IRESUME) { 1059 if (sc->sc_flags.status_suspend) { 1060 sc->sc_flags.status_suspend = 0; 1061 sc->sc_flags.change_suspend = 1; 1062 1063 temp = MUSB2_READ_1(sc, MUSB2_REG_INTUSBE); 1064 /* disable resume interrupt */ 1065 temp &= ~MUSB2_MASK_IRESUME; 1066 /* enable suspend interrupt */ 1067 temp |= MUSB2_MASK_ISUSP; 1068 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, temp); 1069 } 1070 } else if (usb_status & MUSB2_MASK_ISUSP) { 1071 if (!sc->sc_flags.status_suspend) { 1072 sc->sc_flags.status_suspend = 1; 1073 sc->sc_flags.change_suspend = 1; 1074 1075 temp = MUSB2_READ_1(sc, MUSB2_REG_INTUSBE); 1076 /* disable suspend interrupt */ 1077 temp &= ~MUSB2_MASK_ISUSP; 1078 /* enable resume interrupt */ 1079 temp |= MUSB2_MASK_IRESUME; 1080 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, temp); 1081 } 1082 } 1083 /* complete root HUB interrupt endpoint */ 1084 musbotg_root_intr(sc); 1085 } 1086 /* check for any endpoint interrupts */ 1087 1088 if (rx_status || tx_status) { 1089 DPRINTFN(4, "real endpoint interrupt " 1090 "rx=0x%04x, tx=0x%04x\n", rx_status, tx_status); 1091 } 1092 /* poll one time regardless of FIFO status */ 1093 1094 musbotg_interrupt_poll(sc); 1095 1096 if (--to) 1097 goto repeat; 1098 1099 USB_BUS_UNLOCK(&sc->sc_bus); 1100} 1101 1102static void 1103musbotg_setup_standard_chain_sub(struct musbotg_std_temp *temp) 1104{ 1105 struct musbotg_td *td; 1106 1107 /* get current Transfer Descriptor */ 1108 td = temp->td_next; 1109 temp->td = td; 1110 1111 /* prepare for next TD */ 1112 temp->td_next = td->obj_next; 1113 1114 /* fill out the Transfer Descriptor */ 1115 td->func = temp->func; 1116 td->pc = temp->pc; 1117 td->offset = temp->offset; 1118 td->remainder = temp->len; 1119 td->error = 0; 1120 td->did_stall = temp->did_stall; 1121 td->short_pkt = temp->short_pkt; 1122 td->alt_next = temp->setup_alt_next; 1123} 1124 1125static void 1126musbotg_setup_standard_chain(struct usb_xfer *xfer) 1127{ 1128 struct musbotg_std_temp temp; 1129 struct musbotg_softc *sc; 1130 struct musbotg_td *td; 1131 uint32_t x; 1132 uint8_t ep_no; 1133 1134 DPRINTFN(8, "addr=%d endpt=%d sumlen=%d speed=%d\n", 1135 xfer->address, UE_GET_ADDR(xfer->endpointno), 1136 xfer->sumlen, usbd_get_speed(xfer->xroot->udev)); 1137 1138 temp.max_frame_size = xfer->max_frame_size; 1139 1140 td = xfer->td_start[0]; 1141 xfer->td_transfer_first = td; 1142 xfer->td_transfer_cache = td; 1143 1144 /* setup temp */ 1145 1146 temp.pc = NULL; 1147 temp.td = NULL; 1148 temp.td_next = xfer->td_start[0]; 1149 temp.offset = 0; 1150 temp.setup_alt_next = xfer->flags_int.short_frames_ok; 1151 temp.did_stall = !xfer->flags_int.control_stall; 1152 1153 sc = MUSBOTG_BUS2SC(xfer->xroot->bus); 1154 ep_no = (xfer->endpointno & UE_ADDR); 1155 1156 /* check if we should prepend a setup message */ 1157 1158 if (xfer->flags_int.control_xfr) { 1159 if (xfer->flags_int.control_hdr) { 1160 1161 temp.func = &musbotg_setup_rx; 1162 temp.len = xfer->frlengths[0]; 1163 temp.pc = xfer->frbuffers + 0; 1164 temp.short_pkt = temp.len ? 1 : 0; 1165 1166 musbotg_setup_standard_chain_sub(&temp); 1167 } 1168 x = 1; 1169 } else { 1170 x = 0; 1171 } 1172 1173 if (x != xfer->nframes) { 1174 if (xfer->endpointno & UE_DIR_IN) { 1175 if (xfer->flags_int.control_xfr) 1176 temp.func = &musbotg_setup_data_tx; 1177 else 1178 temp.func = &musbotg_data_tx; 1179 } else { 1180 if (xfer->flags_int.control_xfr) 1181 temp.func = &musbotg_setup_data_rx; 1182 else 1183 temp.func = &musbotg_data_rx; 1184 } 1185 1186 /* setup "pc" pointer */ 1187 temp.pc = xfer->frbuffers + x; 1188 } 1189 while (x != xfer->nframes) { 1190 1191 /* DATA0 / DATA1 message */ 1192 1193 temp.len = xfer->frlengths[x]; 1194 1195 x++; 1196 1197 if (x == xfer->nframes) { 1198 if (xfer->flags_int.control_xfr) { 1199 if (xfer->flags_int.control_act) { 1200 temp.setup_alt_next = 0; 1201 } 1202 } else { 1203 temp.setup_alt_next = 0; 1204 } 1205 } 1206 if (temp.len == 0) { 1207 1208 /* make sure that we send an USB packet */ 1209 1210 temp.short_pkt = 0; 1211 1212 } else { 1213 1214 /* regular data transfer */ 1215 1216 temp.short_pkt = (xfer->flags.force_short_xfer) ? 0 : 1; 1217 } 1218 1219 musbotg_setup_standard_chain_sub(&temp); 1220 1221 if (xfer->flags_int.isochronous_xfr) { 1222 temp.offset += temp.len; 1223 } else { 1224 /* get next Page Cache pointer */ 1225 temp.pc = xfer->frbuffers + x; 1226 } 1227 } 1228 1229 /* check for control transfer */ 1230 if (xfer->flags_int.control_xfr) { 1231 1232 /* always setup a valid "pc" pointer for status and sync */ 1233 temp.pc = xfer->frbuffers + 0; 1234 temp.len = 0; 1235 temp.short_pkt = 0; 1236 temp.setup_alt_next = 0; 1237 1238 /* check if we should append a status stage */ 1239 if (!xfer->flags_int.control_act) { 1240 /* 1241 * Send a DATA1 message and invert the current 1242 * endpoint direction. 1243 */ 1244 temp.func = &musbotg_setup_status; 1245 musbotg_setup_standard_chain_sub(&temp); 1246 } 1247 } 1248 /* must have at least one frame! */ 1249 td = temp.td; 1250 xfer->td_transfer_last = td; 1251} 1252 1253static void 1254musbotg_timeout(void *arg) 1255{ 1256 struct usb_xfer *xfer = arg; 1257 1258 DPRINTFN(1, "xfer=%p\n", xfer); 1259 1260 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 1261 1262 /* transfer is transferred */ 1263 musbotg_device_done(xfer, USB_ERR_TIMEOUT); 1264} 1265 1266static void 1267musbotg_ep_int_set(struct usb_xfer *xfer, uint8_t on) 1268{ 1269 struct musbotg_softc *sc = MUSBOTG_BUS2SC(xfer->xroot->bus); 1270 uint16_t temp; 1271 uint8_t ep_no = xfer->endpointno & UE_ADDR; 1272 1273 /* 1274 * Only enable the endpoint interrupt when we are 1275 * actually waiting for data, hence we are dealing 1276 * with level triggered interrupts ! 1277 */ 1278 if (ep_no == 0) { 1279 temp = MUSB2_READ_2(sc, MUSB2_REG_INTTXE); 1280 if (on) 1281 temp |= MUSB2_MASK_EPINT(0); 1282 else 1283 temp &= ~MUSB2_MASK_EPINT(0); 1284 1285 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, temp); 1286 } else { 1287 if (USB_GET_DATA_ISREAD(xfer)) { 1288 temp = MUSB2_READ_2(sc, MUSB2_REG_INTRXE); 1289 if (on) 1290 temp |= MUSB2_MASK_EPINT(ep_no); 1291 else 1292 temp &= ~MUSB2_MASK_EPINT(ep_no); 1293 MUSB2_WRITE_2(sc, MUSB2_REG_INTRXE, temp); 1294 1295 } else { 1296 temp = MUSB2_READ_2(sc, MUSB2_REG_INTTXE); 1297 if (on) 1298 temp |= MUSB2_MASK_EPINT(ep_no); 1299 else 1300 temp &= ~MUSB2_MASK_EPINT(ep_no); 1301 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, temp); 1302 } 1303 } 1304} 1305 1306static void 1307musbotg_start_standard_chain(struct usb_xfer *xfer) 1308{ 1309 DPRINTFN(8, "\n"); 1310 1311 /* poll one time */ 1312 if (musbotg_xfer_do_fifo(xfer)) { 1313 1314 musbotg_ep_int_set(xfer, 1); 1315 1316 DPRINTFN(14, "enabled interrupts on endpoint\n"); 1317 1318 /* put transfer on interrupt queue */ 1319 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 1320 1321 /* start timeout, if any */ 1322 if (xfer->timeout != 0) { 1323 usbd_transfer_timeout_ms(xfer, 1324 &musbotg_timeout, xfer->timeout); 1325 } 1326 } 1327} 1328 1329static void 1330musbotg_root_intr(struct musbotg_softc *sc) 1331{ 1332 DPRINTFN(8, "\n"); 1333 1334 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1335 1336 /* set port bit */ 1337 sc->sc_hub_idata[0] = 0x02; /* we only have one port */ 1338 1339 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, 1340 sizeof(sc->sc_hub_idata)); 1341} 1342 1343static usb_error_t 1344musbotg_standard_done_sub(struct usb_xfer *xfer) 1345{ 1346 struct musbotg_td *td; 1347 uint32_t len; 1348 uint8_t error; 1349 1350 DPRINTFN(8, "\n"); 1351 1352 td = xfer->td_transfer_cache; 1353 1354 do { 1355 len = td->remainder; 1356 1357 if (xfer->aframes != xfer->nframes) { 1358 /* 1359 * Verify the length and subtract 1360 * the remainder from "frlengths[]": 1361 */ 1362 if (len > xfer->frlengths[xfer->aframes]) { 1363 td->error = 1; 1364 } else { 1365 xfer->frlengths[xfer->aframes] -= len; 1366 } 1367 } 1368 /* Check for transfer error */ 1369 if (td->error) { 1370 /* the transfer is finished */ 1371 error = 1; 1372 td = NULL; 1373 break; 1374 } 1375 /* Check for short transfer */ 1376 if (len > 0) { 1377 if (xfer->flags_int.short_frames_ok) { 1378 /* follow alt next */ 1379 if (td->alt_next) { 1380 td = td->obj_next; 1381 } else { 1382 td = NULL; 1383 } 1384 } else { 1385 /* the transfer is finished */ 1386 td = NULL; 1387 } 1388 error = 0; 1389 break; 1390 } 1391 td = td->obj_next; 1392 1393 /* this USB frame is complete */ 1394 error = 0; 1395 break; 1396 1397 } while (0); 1398 1399 /* update transfer cache */ 1400 1401 xfer->td_transfer_cache = td; 1402 1403 return (error ? 1404 USB_ERR_STALLED : USB_ERR_NORMAL_COMPLETION); 1405} 1406 1407static void 1408musbotg_standard_done(struct usb_xfer *xfer) 1409{ 1410 usb_error_t err = 0; 1411 1412 DPRINTFN(12, "xfer=%p endpoint=%p transfer done\n", 1413 xfer, xfer->endpoint); 1414 1415 /* reset scanner */ 1416 1417 xfer->td_transfer_cache = xfer->td_transfer_first; 1418 1419 if (xfer->flags_int.control_xfr) { 1420 1421 if (xfer->flags_int.control_hdr) { 1422 1423 err = musbotg_standard_done_sub(xfer); 1424 } 1425 xfer->aframes = 1; 1426 1427 if (xfer->td_transfer_cache == NULL) { 1428 goto done; 1429 } 1430 } 1431 while (xfer->aframes != xfer->nframes) { 1432 1433 err = musbotg_standard_done_sub(xfer); 1434 xfer->aframes++; 1435 1436 if (xfer->td_transfer_cache == NULL) { 1437 goto done; 1438 } 1439 } 1440 1441 if (xfer->flags_int.control_xfr && 1442 !xfer->flags_int.control_act) { 1443 1444 err = musbotg_standard_done_sub(xfer); 1445 } 1446done: 1447 musbotg_device_done(xfer, err); 1448} 1449 1450/*------------------------------------------------------------------------* 1451 * musbotg_device_done 1452 * 1453 * NOTE: this function can be called more than one time on the 1454 * same USB transfer! 1455 *------------------------------------------------------------------------*/ 1456static void 1457musbotg_device_done(struct usb_xfer *xfer, usb_error_t error) 1458{ 1459 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 1460 1461 DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n", 1462 xfer, xfer->endpoint, error); 1463 1464 if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) { 1465 1466 musbotg_ep_int_set(xfer, 0); 1467 1468 DPRINTFN(14, "disabled interrupts on endpoint\n"); 1469 } 1470 /* dequeue transfer and start next transfer */ 1471 usbd_transfer_done(xfer, error); 1472} 1473 1474static void 1475musbotg_set_stall(struct usb_device *udev, struct usb_xfer *xfer, 1476 struct usb_endpoint *ep, uint8_t *did_stall) 1477{ 1478 struct musbotg_softc *sc; 1479 uint8_t ep_no; 1480 1481 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 1482 1483 DPRINTFN(4, "endpoint=%p\n", ep); 1484 1485 if (xfer) { 1486 /* cancel any ongoing transfers */ 1487 musbotg_device_done(xfer, USB_ERR_STALLED); 1488 } 1489 /* set FORCESTALL */ 1490 sc = MUSBOTG_BUS2SC(udev->bus); 1491 1492 ep_no = (ep->edesc->bEndpointAddress & UE_ADDR); 1493 1494 /* select endpoint */ 1495 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, ep_no); 1496 1497 if (ep->edesc->bEndpointAddress & UE_DIR_IN) { 1498 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 1499 MUSB2_MASK_CSRL_TXSENDSTALL); 1500 } else { 1501 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 1502 MUSB2_MASK_CSRL_RXSENDSTALL); 1503 } 1504} 1505 1506static void 1507musbotg_clear_stall_sub(struct musbotg_softc *sc, uint16_t wMaxPacket, 1508 uint8_t ep_no, uint8_t ep_type, uint8_t ep_dir) 1509{ 1510 uint16_t mps; 1511 uint16_t temp; 1512 uint8_t csr; 1513 1514 if (ep_type == UE_CONTROL) { 1515 /* clearing stall is not needed */ 1516 return; 1517 } 1518 /* select endpoint */ 1519 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, ep_no); 1520 1521 /* compute max frame size */ 1522 mps = wMaxPacket & 0x7FF; 1523 switch ((wMaxPacket >> 11) & 3) { 1524 case 1: 1525 mps *= 2; 1526 break; 1527 case 2: 1528 mps *= 3; 1529 break; 1530 default: 1531 break; 1532 } 1533 1534 if (ep_dir == UE_DIR_IN) { 1535 1536 temp = 0; 1537 1538 /* Configure endpoint */ 1539 switch (ep_type) { 1540 case UE_INTERRUPT: 1541 MUSB2_WRITE_2(sc, MUSB2_REG_TXMAXP, wMaxPacket); 1542 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, 1543 MUSB2_MASK_CSRH_TXMODE | temp); 1544 break; 1545 case UE_ISOCHRONOUS: 1546 MUSB2_WRITE_2(sc, MUSB2_REG_TXMAXP, wMaxPacket); 1547 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, 1548 MUSB2_MASK_CSRH_TXMODE | 1549 MUSB2_MASK_CSRH_TXISO | temp); 1550 break; 1551 case UE_BULK: 1552 MUSB2_WRITE_2(sc, MUSB2_REG_TXMAXP, wMaxPacket); 1553 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, 1554 MUSB2_MASK_CSRH_TXMODE | temp); 1555 break; 1556 default: 1557 break; 1558 } 1559 1560 /* Need to flush twice in case of double bufring */ 1561 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 1562 if (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) { 1563 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 1564 MUSB2_MASK_CSRL_TXFFLUSH); 1565 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 1566 if (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) { 1567 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 1568 MUSB2_MASK_CSRL_TXFFLUSH); 1569 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 1570 } 1571 } 1572 /* reset data toggle */ 1573 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 1574 MUSB2_MASK_CSRL_TXDT_CLR); 1575 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0); 1576 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 1577 1578 /* set double/single buffering */ 1579 temp = MUSB2_READ_2(sc, MUSB2_REG_TXDBDIS); 1580 if (mps <= (sc->sc_hw_ep_profile[ep_no]. 1581 max_in_frame_size / 2)) { 1582 /* double buffer */ 1583 temp &= ~(1 << ep_no); 1584 } else { 1585 /* single buffer */ 1586 temp |= (1 << ep_no); 1587 } 1588 MUSB2_WRITE_2(sc, MUSB2_REG_TXDBDIS, temp); 1589 1590 /* clear sent stall */ 1591 if (csr & MUSB2_MASK_CSRL_TXSENTSTALL) { 1592 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0); 1593 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 1594 } 1595 } else { 1596 1597 temp = 0; 1598 1599 /* Configure endpoint */ 1600 switch (ep_type) { 1601 case UE_INTERRUPT: 1602 MUSB2_WRITE_2(sc, MUSB2_REG_RXMAXP, wMaxPacket); 1603 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH, 1604 MUSB2_MASK_CSRH_RXNYET | temp); 1605 break; 1606 case UE_ISOCHRONOUS: 1607 MUSB2_WRITE_2(sc, MUSB2_REG_RXMAXP, wMaxPacket); 1608 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH, 1609 MUSB2_MASK_CSRH_RXNYET | 1610 MUSB2_MASK_CSRH_RXISO | temp); 1611 break; 1612 case UE_BULK: 1613 MUSB2_WRITE_2(sc, MUSB2_REG_RXMAXP, wMaxPacket); 1614 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH, temp); 1615 break; 1616 default: 1617 break; 1618 } 1619 1620 /* Need to flush twice in case of double bufring */ 1621 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL); 1622 if (csr & MUSB2_MASK_CSRL_RXPKTRDY) { 1623 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 1624 MUSB2_MASK_CSRL_RXFFLUSH); 1625 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL); 1626 if (csr & MUSB2_MASK_CSRL_RXPKTRDY) { 1627 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 1628 MUSB2_MASK_CSRL_RXFFLUSH); 1629 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL); 1630 } 1631 } 1632 /* reset data toggle */ 1633 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 1634 MUSB2_MASK_CSRL_RXDT_CLR); 1635 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 0); 1636 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL); 1637 1638 /* set double/single buffering */ 1639 temp = MUSB2_READ_2(sc, MUSB2_REG_RXDBDIS); 1640 if (mps <= (sc->sc_hw_ep_profile[ep_no]. 1641 max_out_frame_size / 2)) { 1642 /* double buffer */ 1643 temp &= ~(1 << ep_no); 1644 } else { 1645 /* single buffer */ 1646 temp |= (1 << ep_no); 1647 } 1648 MUSB2_WRITE_2(sc, MUSB2_REG_RXDBDIS, temp); 1649 1650 /* clear sent stall */ 1651 if (csr & MUSB2_MASK_CSRL_RXSENTSTALL) { 1652 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 0); 1653 } 1654 } 1655} 1656 1657static void 1658musbotg_clear_stall(struct usb_device *udev, struct usb_endpoint *ep) 1659{ 1660 struct musbotg_softc *sc; 1661 struct usb_endpoint_descriptor *ed; 1662 1663 DPRINTFN(4, "endpoint=%p\n", ep); 1664 1665 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 1666 1667 /* check mode */ 1668 if (udev->flags.usb_mode != USB_MODE_DEVICE) { 1669 /* not supported */ 1670 return; 1671 } 1672 /* get softc */ 1673 sc = MUSBOTG_BUS2SC(udev->bus); 1674 1675 /* get endpoint descriptor */ 1676 ed = ep->edesc; 1677 1678 /* reset endpoint */ 1679 musbotg_clear_stall_sub(sc, 1680 UGETW(ed->wMaxPacketSize), 1681 (ed->bEndpointAddress & UE_ADDR), 1682 (ed->bmAttributes & UE_XFERTYPE), 1683 (ed->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT))); 1684} 1685 1686usb_error_t 1687musbotg_init(struct musbotg_softc *sc) 1688{ 1689 struct usb_hw_ep_profile *pf; 1690 uint16_t offset; 1691 uint8_t nrx; 1692 uint8_t ntx; 1693 uint8_t temp; 1694 uint8_t fsize; 1695 uint8_t frx; 1696 uint8_t ftx; 1697 uint8_t dynfifo; 1698 1699 DPRINTFN(1, "start\n"); 1700 1701 /* set up the bus structure */ 1702 sc->sc_bus.usbrev = USB_REV_2_0; 1703 sc->sc_bus.methods = &musbotg_bus_methods; 1704 1705 USB_BUS_LOCK(&sc->sc_bus); 1706 1707 /* turn on clocks */ 1708 1709 if (sc->sc_clocks_on) { 1710 (sc->sc_clocks_on) (sc->sc_clocks_arg); 1711 } 1712 /* wait a little for things to stabilise */ 1713 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 1000); 1714 1715 /* disable all interrupts */ 1716 1717 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, 0); 1718 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, 0); 1719 MUSB2_WRITE_2(sc, MUSB2_REG_INTRXE, 0); 1720 1721 /* disable pullup */ 1722 1723 musbotg_pull_common(sc, 0); 1724 1725 /* wait a little bit (10ms) */ 1726 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100); 1727 1728 /* disable double packet buffering */ 1729 MUSB2_WRITE_2(sc, MUSB2_REG_RXDBDIS, 0xFFFF); 1730 MUSB2_WRITE_2(sc, MUSB2_REG_TXDBDIS, 0xFFFF); 1731 1732 /* enable HighSpeed and ISO Update flags */ 1733 1734 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, 1735 MUSB2_MASK_HSENAB | MUSB2_MASK_ISOUPD); 1736 1737 /* clear Session bit, if set */ 1738 1739 temp = MUSB2_READ_1(sc, MUSB2_REG_DEVCTL); 1740 temp &= ~MUSB2_MASK_SESS; 1741 MUSB2_WRITE_1(sc, MUSB2_REG_DEVCTL, temp); 1742 1743 DPRINTF("DEVCTL=0x%02x\n", temp); 1744 1745 /* disable testmode */ 1746 1747 MUSB2_WRITE_1(sc, MUSB2_REG_TESTMODE, 0); 1748 1749 /* set default value */ 1750 1751 MUSB2_WRITE_1(sc, MUSB2_REG_MISC, 0); 1752 1753 /* select endpoint index 0 */ 1754 1755 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); 1756 1757 /* read out number of endpoints */ 1758 1759 nrx = 1760 (MUSB2_READ_1(sc, MUSB2_REG_EPINFO) / 16); 1761 1762 ntx = 1763 (MUSB2_READ_1(sc, MUSB2_REG_EPINFO) % 16); 1764 1765 /* these numbers exclude the control endpoint */ 1766 1767 DPRINTFN(2, "RX/TX endpoints: %u/%u\n", nrx, ntx); 1768 1769 sc->sc_ep_max = (nrx > ntx) ? nrx : ntx; 1770 if (sc->sc_ep_max == 0) { 1771 DPRINTFN(2, "ERROR: Looks like the clocks are off!\n"); 1772 } 1773 /* read out configuration data */ 1774 1775 sc->sc_conf_data = MUSB2_READ_1(sc, MUSB2_REG_CONFDATA); 1776 1777 DPRINTFN(2, "Config Data: 0x%02x\n", 1778 sc->sc_conf_data); 1779 1780 dynfifo = (sc->sc_conf_data & MUSB2_MASK_CD_DYNFIFOSZ) ? 1 : 0; 1781 1782 if (dynfifo) { 1783 device_printf(sc->sc_bus.bdev, "Dynamic FIFO sizing detected, " 1784 "assuming 16Kbytes of FIFO RAM\n"); 1785 } 1786 1787 DPRINTFN(2, "HW version: 0x%04x\n", 1788 MUSB2_READ_1(sc, MUSB2_REG_HWVERS)); 1789 1790 /* initialise endpoint profiles */ 1791 1792 offset = 0; 1793 1794 for (temp = 1; temp <= sc->sc_ep_max; temp++) { 1795 pf = sc->sc_hw_ep_profile + temp; 1796 1797 /* select endpoint */ 1798 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, temp); 1799 1800 fsize = MUSB2_READ_1(sc, MUSB2_REG_FSIZE); 1801 frx = (fsize & MUSB2_MASK_RX_FSIZE) / 16; 1802 ftx = (fsize & MUSB2_MASK_TX_FSIZE); 1803 1804 DPRINTF("Endpoint %u FIFO size: IN=%u, OUT=%u, DYN=%d\n", 1805 temp, ftx, frx, dynfifo); 1806 1807 if (dynfifo) { 1808 if (frx && (temp <= nrx)) { 1809 if (temp < 8) { 1810 frx = 10; /* 1K */ 1811 MUSB2_WRITE_1(sc, MUSB2_REG_RXFIFOSZ, 1812 MUSB2_VAL_FIFOSZ_512 | 1813 MUSB2_MASK_FIFODB); 1814 } else { 1815 frx = 7; /* 128 bytes */ 1816 MUSB2_WRITE_1(sc, MUSB2_REG_RXFIFOSZ, 1817 MUSB2_VAL_FIFOSZ_128); 1818 } 1819 1820 MUSB2_WRITE_2(sc, MUSB2_REG_RXFIFOADD, 1821 offset >> 3); 1822 1823 offset += (1 << frx); 1824 } 1825 if (ftx && (temp <= ntx)) { 1826 if (temp < 8) { 1827 ftx = 10; /* 1K */ 1828 MUSB2_WRITE_1(sc, MUSB2_REG_TXFIFOSZ, 1829 MUSB2_VAL_FIFOSZ_512 | 1830 MUSB2_MASK_FIFODB); 1831 } else { 1832 ftx = 7; /* 128 bytes */ 1833 MUSB2_WRITE_1(sc, MUSB2_REG_TXFIFOSZ, 1834 MUSB2_VAL_FIFOSZ_128); 1835 } 1836 1837 MUSB2_WRITE_2(sc, MUSB2_REG_TXFIFOADD, 1838 offset >> 3); 1839 1840 offset += (1 << ftx); 1841 } 1842 } 1843 1844 if (frx && ftx && (temp <= nrx) && (temp <= ntx)) { 1845 pf->max_in_frame_size = 1 << ftx; 1846 pf->max_out_frame_size = 1 << frx; 1847 pf->is_simplex = 0; /* duplex */ 1848 pf->support_multi_buffer = 1; 1849 pf->support_bulk = 1; 1850 pf->support_interrupt = 1; 1851 pf->support_isochronous = 1; 1852 pf->support_in = 1; 1853 pf->support_out = 1; 1854 } else if (frx && (temp <= nrx)) { 1855 pf->max_out_frame_size = 1 << frx; 1856 pf->is_simplex = 1; /* simplex */ 1857 pf->support_multi_buffer = 1; 1858 pf->support_bulk = 1; 1859 pf->support_interrupt = 1; 1860 pf->support_isochronous = 1; 1861 pf->support_out = 1; 1862 } else if (ftx && (temp <= ntx)) { 1863 pf->max_in_frame_size = 1 << ftx; 1864 pf->is_simplex = 1; /* simplex */ 1865 pf->support_multi_buffer = 1; 1866 pf->support_bulk = 1; 1867 pf->support_interrupt = 1; 1868 pf->support_isochronous = 1; 1869 pf->support_in = 1; 1870 } 1871 } 1872 1873 DPRINTFN(2, "Dynamic FIFO size = %d bytes\n", offset); 1874 1875 /* turn on default interrupts */ 1876 1877 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, 1878 MUSB2_MASK_IRESET); 1879 1880 musbotg_clocks_off(sc); 1881 1882 USB_BUS_UNLOCK(&sc->sc_bus); 1883 1884 /* catch any lost interrupts */ 1885 1886 musbotg_do_poll(&sc->sc_bus); 1887 1888 return (0); /* success */ 1889} 1890 1891void 1892musbotg_uninit(struct musbotg_softc *sc) 1893{ 1894 USB_BUS_LOCK(&sc->sc_bus); 1895 1896 /* disable all interrupts */ 1897 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, 0); 1898 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, 0); 1899 MUSB2_WRITE_2(sc, MUSB2_REG_INTRXE, 0); 1900 1901 sc->sc_flags.port_powered = 0; 1902 sc->sc_flags.status_vbus = 0; 1903 sc->sc_flags.status_bus_reset = 0; 1904 sc->sc_flags.status_suspend = 0; 1905 sc->sc_flags.change_suspend = 0; 1906 sc->sc_flags.change_connect = 1; 1907 1908 musbotg_pull_down(sc); 1909 musbotg_clocks_off(sc); 1910 USB_BUS_UNLOCK(&sc->sc_bus); 1911} 1912 1913static void 1914musbotg_suspend(struct musbotg_softc *sc) 1915{ 1916 /* TODO */ 1917} 1918 1919static void 1920musbotg_resume(struct musbotg_softc *sc) 1921{ 1922 /* TODO */ 1923} 1924 1925static void 1926musbotg_do_poll(struct usb_bus *bus) 1927{ 1928 struct musbotg_softc *sc = MUSBOTG_BUS2SC(bus); 1929 1930 USB_BUS_LOCK(&sc->sc_bus); 1931 musbotg_interrupt_poll(sc); 1932 USB_BUS_UNLOCK(&sc->sc_bus); 1933} 1934 1935/*------------------------------------------------------------------------* 1936 * musbotg bulk support 1937 *------------------------------------------------------------------------*/ 1938static void 1939musbotg_device_bulk_open(struct usb_xfer *xfer) 1940{ 1941 return; 1942} 1943 1944static void 1945musbotg_device_bulk_close(struct usb_xfer *xfer) 1946{ 1947 musbotg_device_done(xfer, USB_ERR_CANCELLED); 1948} 1949 1950static void 1951musbotg_device_bulk_enter(struct usb_xfer *xfer) 1952{ 1953 return; 1954} 1955 1956static void 1957musbotg_device_bulk_start(struct usb_xfer *xfer) 1958{ 1959 /* setup TDs */ 1960 musbotg_setup_standard_chain(xfer); 1961 musbotg_start_standard_chain(xfer); 1962} 1963 1964struct usb_pipe_methods musbotg_device_bulk_methods = 1965{ 1966 .open = musbotg_device_bulk_open, 1967 .close = musbotg_device_bulk_close, 1968 .enter = musbotg_device_bulk_enter, 1969 .start = musbotg_device_bulk_start, 1970}; 1971 1972/*------------------------------------------------------------------------* 1973 * musbotg control support 1974 *------------------------------------------------------------------------*/ 1975static void 1976musbotg_device_ctrl_open(struct usb_xfer *xfer) 1977{ 1978 return; 1979} 1980 1981static void 1982musbotg_device_ctrl_close(struct usb_xfer *xfer) 1983{ 1984 musbotg_device_done(xfer, USB_ERR_CANCELLED); 1985} 1986 1987static void 1988musbotg_device_ctrl_enter(struct usb_xfer *xfer) 1989{ 1990 return; 1991} 1992 1993static void 1994musbotg_device_ctrl_start(struct usb_xfer *xfer) 1995{ 1996 /* setup TDs */ 1997 musbotg_setup_standard_chain(xfer); 1998 musbotg_start_standard_chain(xfer); 1999} 2000 2001struct usb_pipe_methods musbotg_device_ctrl_methods = 2002{ 2003 .open = musbotg_device_ctrl_open, 2004 .close = musbotg_device_ctrl_close, 2005 .enter = musbotg_device_ctrl_enter, 2006 .start = musbotg_device_ctrl_start, 2007}; 2008 2009/*------------------------------------------------------------------------* 2010 * musbotg interrupt support 2011 *------------------------------------------------------------------------*/ 2012static void 2013musbotg_device_intr_open(struct usb_xfer *xfer) 2014{ 2015 return; 2016} 2017 2018static void 2019musbotg_device_intr_close(struct usb_xfer *xfer) 2020{ 2021 musbotg_device_done(xfer, USB_ERR_CANCELLED); 2022} 2023 2024static void 2025musbotg_device_intr_enter(struct usb_xfer *xfer) 2026{ 2027 return; 2028} 2029 2030static void 2031musbotg_device_intr_start(struct usb_xfer *xfer) 2032{ 2033 /* setup TDs */ 2034 musbotg_setup_standard_chain(xfer); 2035 musbotg_start_standard_chain(xfer); 2036} 2037 2038struct usb_pipe_methods musbotg_device_intr_methods = 2039{ 2040 .open = musbotg_device_intr_open, 2041 .close = musbotg_device_intr_close, 2042 .enter = musbotg_device_intr_enter, 2043 .start = musbotg_device_intr_start, 2044}; 2045 2046/*------------------------------------------------------------------------* 2047 * musbotg full speed isochronous support 2048 *------------------------------------------------------------------------*/ 2049static void 2050musbotg_device_isoc_open(struct usb_xfer *xfer) 2051{ 2052 return; 2053} 2054 2055static void 2056musbotg_device_isoc_close(struct usb_xfer *xfer) 2057{ 2058 musbotg_device_done(xfer, USB_ERR_CANCELLED); 2059} 2060 2061static void 2062musbotg_device_isoc_enter(struct usb_xfer *xfer) 2063{ 2064 struct musbotg_softc *sc = MUSBOTG_BUS2SC(xfer->xroot->bus); 2065 uint32_t temp; 2066 uint32_t nframes; 2067 uint32_t fs_frames; 2068 2069 DPRINTFN(5, "xfer=%p next=%d nframes=%d\n", 2070 xfer, xfer->endpoint->isoc_next, xfer->nframes); 2071 2072 /* get the current frame index */ 2073 2074 nframes = MUSB2_READ_2(sc, MUSB2_REG_FRAME); 2075 2076 /* 2077 * check if the frame index is within the window where the frames 2078 * will be inserted 2079 */ 2080 temp = (nframes - xfer->endpoint->isoc_next) & MUSB2_MASK_FRAME; 2081 2082 if (usbd_get_speed(xfer->xroot->udev) == USB_SPEED_HIGH) { 2083 fs_frames = (xfer->nframes + 7) / 8; 2084 } else { 2085 fs_frames = xfer->nframes; 2086 } 2087 2088 if ((xfer->endpoint->is_synced == 0) || 2089 (temp < fs_frames)) { 2090 /* 2091 * If there is data underflow or the pipe queue is 2092 * empty we schedule the transfer a few frames ahead 2093 * of the current frame position. Else two isochronous 2094 * transfers might overlap. 2095 */ 2096 xfer->endpoint->isoc_next = (nframes + 3) & MUSB2_MASK_FRAME; 2097 xfer->endpoint->is_synced = 1; 2098 DPRINTFN(2, "start next=%d\n", xfer->endpoint->isoc_next); 2099 } 2100 /* 2101 * compute how many milliseconds the insertion is ahead of the 2102 * current frame position: 2103 */ 2104 temp = (xfer->endpoint->isoc_next - nframes) & MUSB2_MASK_FRAME; 2105 2106 /* 2107 * pre-compute when the isochronous transfer will be finished: 2108 */ 2109 xfer->isoc_time_complete = 2110 usb_isoc_time_expand(&sc->sc_bus, nframes) + temp + 2111 fs_frames; 2112 2113 /* compute frame number for next insertion */ 2114 xfer->endpoint->isoc_next += fs_frames; 2115 2116 /* setup TDs */ 2117 musbotg_setup_standard_chain(xfer); 2118} 2119 2120static void 2121musbotg_device_isoc_start(struct usb_xfer *xfer) 2122{ 2123 /* start TD chain */ 2124 musbotg_start_standard_chain(xfer); 2125} 2126 2127struct usb_pipe_methods musbotg_device_isoc_methods = 2128{ 2129 .open = musbotg_device_isoc_open, 2130 .close = musbotg_device_isoc_close, 2131 .enter = musbotg_device_isoc_enter, 2132 .start = musbotg_device_isoc_start, 2133}; 2134 2135/*------------------------------------------------------------------------* 2136 * musbotg root control support 2137 *------------------------------------------------------------------------* 2138 * Simulate a hardware HUB by handling all the necessary requests. 2139 *------------------------------------------------------------------------*/ 2140 2141static const struct usb_device_descriptor musbotg_devd = { 2142 .bLength = sizeof(struct usb_device_descriptor), 2143 .bDescriptorType = UDESC_DEVICE, 2144 .bcdUSB = {0x00, 0x02}, 2145 .bDeviceClass = UDCLASS_HUB, 2146 .bDeviceSubClass = UDSUBCLASS_HUB, 2147 .bDeviceProtocol = UDPROTO_HSHUBSTT, 2148 .bMaxPacketSize = 64, 2149 .bcdDevice = {0x00, 0x01}, 2150 .iManufacturer = 1, 2151 .iProduct = 2, 2152 .bNumConfigurations = 1, 2153}; 2154 2155static const struct usb_device_qualifier musbotg_odevd = { 2156 .bLength = sizeof(struct usb_device_qualifier), 2157 .bDescriptorType = UDESC_DEVICE_QUALIFIER, 2158 .bcdUSB = {0x00, 0x02}, 2159 .bDeviceClass = UDCLASS_HUB, 2160 .bDeviceSubClass = UDSUBCLASS_HUB, 2161 .bDeviceProtocol = UDPROTO_FSHUB, 2162 .bMaxPacketSize0 = 0, 2163 .bNumConfigurations = 0, 2164}; 2165 2166static const struct musbotg_config_desc musbotg_confd = { 2167 .confd = { 2168 .bLength = sizeof(struct usb_config_descriptor), 2169 .bDescriptorType = UDESC_CONFIG, 2170 .wTotalLength[0] = sizeof(musbotg_confd), 2171 .bNumInterface = 1, 2172 .bConfigurationValue = 1, 2173 .iConfiguration = 0, 2174 .bmAttributes = UC_SELF_POWERED, 2175 .bMaxPower = 0, 2176 }, 2177 .ifcd = { 2178 .bLength = sizeof(struct usb_interface_descriptor), 2179 .bDescriptorType = UDESC_INTERFACE, 2180 .bNumEndpoints = 1, 2181 .bInterfaceClass = UICLASS_HUB, 2182 .bInterfaceSubClass = UISUBCLASS_HUB, 2183 .bInterfaceProtocol = 0, 2184 }, 2185 .endpd = { 2186 .bLength = sizeof(struct usb_endpoint_descriptor), 2187 .bDescriptorType = UDESC_ENDPOINT, 2188 .bEndpointAddress = (UE_DIR_IN | MUSBOTG_INTR_ENDPT), 2189 .bmAttributes = UE_INTERRUPT, 2190 .wMaxPacketSize[0] = 8, 2191 .bInterval = 255, 2192 }, 2193}; 2194 2195#define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) } 2196 2197static const struct usb_hub_descriptor_min musbotg_hubd = { 2198 .bDescLength = sizeof(musbotg_hubd), 2199 .bDescriptorType = UDESC_HUB, 2200 .bNbrPorts = 1, 2201 HSETW(.wHubCharacteristics, (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL)), 2202 .bPwrOn2PwrGood = 50, 2203 .bHubContrCurrent = 0, 2204 .DeviceRemovable = {0}, /* port is removable */ 2205}; 2206 2207#define STRING_LANG \ 2208 0x09, 0x04, /* American English */ 2209 2210#define STRING_VENDOR \ 2211 'M', 0, 'e', 0, 'n', 0, 't', 0, 'o', 0, 'r', 0, ' ', 0, \ 2212 'G', 0, 'r', 0, 'a', 0, 'p', 0, 'h', 0, 'i', 0, 'c', 0, 's', 0 2213 2214#define STRING_PRODUCT \ 2215 'O', 0, 'T', 0, 'G', 0, ' ', 0, 'R', 0, \ 2216 'o', 0, 'o', 0, 't', 0, ' ', 0, 'H', 0, \ 2217 'U', 0, 'B', 0, 2218 2219USB_MAKE_STRING_DESC(STRING_LANG, musbotg_langtab); 2220USB_MAKE_STRING_DESC(STRING_VENDOR, musbotg_vendor); 2221USB_MAKE_STRING_DESC(STRING_PRODUCT, musbotg_product); 2222 2223static usb_error_t 2224musbotg_roothub_exec(struct usb_device *udev, 2225 struct usb_device_request *req, const void **pptr, uint16_t *plength) 2226{ 2227 struct musbotg_softc *sc = MUSBOTG_BUS2SC(udev->bus); 2228 const void *ptr; 2229 uint16_t len; 2230 uint16_t value; 2231 uint16_t index; 2232 usb_error_t err; 2233 2234 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2235 2236 /* buffer reset */ 2237 ptr = (const void *)&sc->sc_hub_temp; 2238 len = 0; 2239 err = 0; 2240 2241 value = UGETW(req->wValue); 2242 index = UGETW(req->wIndex); 2243 2244 /* demultiplex the control request */ 2245 2246 switch (req->bmRequestType) { 2247 case UT_READ_DEVICE: 2248 switch (req->bRequest) { 2249 case UR_GET_DESCRIPTOR: 2250 goto tr_handle_get_descriptor; 2251 case UR_GET_CONFIG: 2252 goto tr_handle_get_config; 2253 case UR_GET_STATUS: 2254 goto tr_handle_get_status; 2255 default: 2256 goto tr_stalled; 2257 } 2258 break; 2259 2260 case UT_WRITE_DEVICE: 2261 switch (req->bRequest) { 2262 case UR_SET_ADDRESS: 2263 goto tr_handle_set_address; 2264 case UR_SET_CONFIG: 2265 goto tr_handle_set_config; 2266 case UR_CLEAR_FEATURE: 2267 goto tr_valid; /* nop */ 2268 case UR_SET_DESCRIPTOR: 2269 goto tr_valid; /* nop */ 2270 case UR_SET_FEATURE: 2271 default: 2272 goto tr_stalled; 2273 } 2274 break; 2275 2276 case UT_WRITE_ENDPOINT: 2277 switch (req->bRequest) { 2278 case UR_CLEAR_FEATURE: 2279 switch (UGETW(req->wValue)) { 2280 case UF_ENDPOINT_HALT: 2281 goto tr_handle_clear_halt; 2282 case UF_DEVICE_REMOTE_WAKEUP: 2283 goto tr_handle_clear_wakeup; 2284 default: 2285 goto tr_stalled; 2286 } 2287 break; 2288 case UR_SET_FEATURE: 2289 switch (UGETW(req->wValue)) { 2290 case UF_ENDPOINT_HALT: 2291 goto tr_handle_set_halt; 2292 case UF_DEVICE_REMOTE_WAKEUP: 2293 goto tr_handle_set_wakeup; 2294 default: 2295 goto tr_stalled; 2296 } 2297 break; 2298 case UR_SYNCH_FRAME: 2299 goto tr_valid; /* nop */ 2300 default: 2301 goto tr_stalled; 2302 } 2303 break; 2304 2305 case UT_READ_ENDPOINT: 2306 switch (req->bRequest) { 2307 case UR_GET_STATUS: 2308 goto tr_handle_get_ep_status; 2309 default: 2310 goto tr_stalled; 2311 } 2312 break; 2313 2314 case UT_WRITE_INTERFACE: 2315 switch (req->bRequest) { 2316 case UR_SET_INTERFACE: 2317 goto tr_handle_set_interface; 2318 case UR_CLEAR_FEATURE: 2319 goto tr_valid; /* nop */ 2320 case UR_SET_FEATURE: 2321 default: 2322 goto tr_stalled; 2323 } 2324 break; 2325 2326 case UT_READ_INTERFACE: 2327 switch (req->bRequest) { 2328 case UR_GET_INTERFACE: 2329 goto tr_handle_get_interface; 2330 case UR_GET_STATUS: 2331 goto tr_handle_get_iface_status; 2332 default: 2333 goto tr_stalled; 2334 } 2335 break; 2336 2337 case UT_WRITE_CLASS_INTERFACE: 2338 case UT_WRITE_VENDOR_INTERFACE: 2339 /* XXX forward */ 2340 break; 2341 2342 case UT_READ_CLASS_INTERFACE: 2343 case UT_READ_VENDOR_INTERFACE: 2344 /* XXX forward */ 2345 break; 2346 2347 case UT_WRITE_CLASS_DEVICE: 2348 switch (req->bRequest) { 2349 case UR_CLEAR_FEATURE: 2350 goto tr_valid; 2351 case UR_SET_DESCRIPTOR: 2352 case UR_SET_FEATURE: 2353 break; 2354 default: 2355 goto tr_stalled; 2356 } 2357 break; 2358 2359 case UT_WRITE_CLASS_OTHER: 2360 switch (req->bRequest) { 2361 case UR_CLEAR_FEATURE: 2362 goto tr_handle_clear_port_feature; 2363 case UR_SET_FEATURE: 2364 goto tr_handle_set_port_feature; 2365 case UR_CLEAR_TT_BUFFER: 2366 case UR_RESET_TT: 2367 case UR_STOP_TT: 2368 goto tr_valid; 2369 2370 default: 2371 goto tr_stalled; 2372 } 2373 break; 2374 2375 case UT_READ_CLASS_OTHER: 2376 switch (req->bRequest) { 2377 case UR_GET_TT_STATE: 2378 goto tr_handle_get_tt_state; 2379 case UR_GET_STATUS: 2380 goto tr_handle_get_port_status; 2381 default: 2382 goto tr_stalled; 2383 } 2384 break; 2385 2386 case UT_READ_CLASS_DEVICE: 2387 switch (req->bRequest) { 2388 case UR_GET_DESCRIPTOR: 2389 goto tr_handle_get_class_descriptor; 2390 case UR_GET_STATUS: 2391 goto tr_handle_get_class_status; 2392 2393 default: 2394 goto tr_stalled; 2395 } 2396 break; 2397 default: 2398 goto tr_stalled; 2399 } 2400 goto tr_valid; 2401 2402tr_handle_get_descriptor: 2403 switch (value >> 8) { 2404 case UDESC_DEVICE: 2405 if (value & 0xff) { 2406 goto tr_stalled; 2407 } 2408 len = sizeof(musbotg_devd); 2409 ptr = (const void *)&musbotg_devd; 2410 goto tr_valid; 2411 case UDESC_CONFIG: 2412 if (value & 0xff) { 2413 goto tr_stalled; 2414 } 2415 len = sizeof(musbotg_confd); 2416 ptr = (const void *)&musbotg_confd; 2417 goto tr_valid; 2418 case UDESC_STRING: 2419 switch (value & 0xff) { 2420 case 0: /* Language table */ 2421 len = sizeof(musbotg_langtab); 2422 ptr = (const void *)&musbotg_langtab; 2423 goto tr_valid; 2424 2425 case 1: /* Vendor */ 2426 len = sizeof(musbotg_vendor); 2427 ptr = (const void *)&musbotg_vendor; 2428 goto tr_valid; 2429 2430 case 2: /* Product */ 2431 len = sizeof(musbotg_product); 2432 ptr = (const void *)&musbotg_product; 2433 goto tr_valid; 2434 default: 2435 break; 2436 } 2437 break; 2438 default: 2439 goto tr_stalled; 2440 } 2441 goto tr_stalled; 2442 2443tr_handle_get_config: 2444 len = 1; 2445 sc->sc_hub_temp.wValue[0] = sc->sc_conf; 2446 goto tr_valid; 2447 2448tr_handle_get_status: 2449 len = 2; 2450 USETW(sc->sc_hub_temp.wValue, UDS_SELF_POWERED); 2451 goto tr_valid; 2452 2453tr_handle_set_address: 2454 if (value & 0xFF00) { 2455 goto tr_stalled; 2456 } 2457 sc->sc_rt_addr = value; 2458 goto tr_valid; 2459 2460tr_handle_set_config: 2461 if (value >= 2) { 2462 goto tr_stalled; 2463 } 2464 sc->sc_conf = value; 2465 goto tr_valid; 2466 2467tr_handle_get_interface: 2468 len = 1; 2469 sc->sc_hub_temp.wValue[0] = 0; 2470 goto tr_valid; 2471 2472tr_handle_get_tt_state: 2473tr_handle_get_class_status: 2474tr_handle_get_iface_status: 2475tr_handle_get_ep_status: 2476 len = 2; 2477 USETW(sc->sc_hub_temp.wValue, 0); 2478 goto tr_valid; 2479 2480tr_handle_set_halt: 2481tr_handle_set_interface: 2482tr_handle_set_wakeup: 2483tr_handle_clear_wakeup: 2484tr_handle_clear_halt: 2485 goto tr_valid; 2486 2487tr_handle_clear_port_feature: 2488 if (index != 1) { 2489 goto tr_stalled; 2490 } 2491 DPRINTFN(8, "UR_CLEAR_PORT_FEATURE on port %d\n", index); 2492 2493 switch (value) { 2494 case UHF_PORT_SUSPEND: 2495 musbotg_wakeup_peer(sc); 2496 break; 2497 2498 case UHF_PORT_ENABLE: 2499 sc->sc_flags.port_enabled = 0; 2500 break; 2501 2502 case UHF_PORT_TEST: 2503 case UHF_PORT_INDICATOR: 2504 case UHF_C_PORT_ENABLE: 2505 case UHF_C_PORT_OVER_CURRENT: 2506 case UHF_C_PORT_RESET: 2507 /* nops */ 2508 break; 2509 case UHF_PORT_POWER: 2510 sc->sc_flags.port_powered = 0; 2511 musbotg_pull_down(sc); 2512 musbotg_clocks_off(sc); 2513 break; 2514 case UHF_C_PORT_CONNECTION: 2515 sc->sc_flags.change_connect = 0; 2516 break; 2517 case UHF_C_PORT_SUSPEND: 2518 sc->sc_flags.change_suspend = 0; 2519 break; 2520 default: 2521 err = USB_ERR_IOERROR; 2522 goto done; 2523 } 2524 goto tr_valid; 2525 2526tr_handle_set_port_feature: 2527 if (index != 1) { 2528 goto tr_stalled; 2529 } 2530 DPRINTFN(8, "UR_SET_PORT_FEATURE\n"); 2531 2532 switch (value) { 2533 case UHF_PORT_ENABLE: 2534 sc->sc_flags.port_enabled = 1; 2535 break; 2536 case UHF_PORT_SUSPEND: 2537 case UHF_PORT_RESET: 2538 case UHF_PORT_TEST: 2539 case UHF_PORT_INDICATOR: 2540 /* nops */ 2541 break; 2542 case UHF_PORT_POWER: 2543 sc->sc_flags.port_powered = 1; 2544 break; 2545 default: 2546 err = USB_ERR_IOERROR; 2547 goto done; 2548 } 2549 goto tr_valid; 2550 2551tr_handle_get_port_status: 2552 2553 DPRINTFN(8, "UR_GET_PORT_STATUS\n"); 2554 2555 if (index != 1) { 2556 goto tr_stalled; 2557 } 2558 if (sc->sc_flags.status_vbus) { 2559 musbotg_clocks_on(sc); 2560 musbotg_pull_up(sc); 2561 } else { 2562 musbotg_pull_down(sc); 2563 musbotg_clocks_off(sc); 2564 } 2565 2566 /* Select Device Side Mode */ 2567 value = UPS_PORT_MODE_DEVICE; 2568 2569 if (sc->sc_flags.status_high_speed) { 2570 value |= UPS_HIGH_SPEED; 2571 } 2572 if (sc->sc_flags.port_powered) { 2573 value |= UPS_PORT_POWER; 2574 } 2575 if (sc->sc_flags.port_enabled) { 2576 value |= UPS_PORT_ENABLED; 2577 } 2578 if (sc->sc_flags.status_vbus && 2579 sc->sc_flags.status_bus_reset) { 2580 value |= UPS_CURRENT_CONNECT_STATUS; 2581 } 2582 if (sc->sc_flags.status_suspend) { 2583 value |= UPS_SUSPEND; 2584 } 2585 USETW(sc->sc_hub_temp.ps.wPortStatus, value); 2586 2587 value = 0; 2588 2589 if (sc->sc_flags.change_connect) { 2590 value |= UPS_C_CONNECT_STATUS; 2591 2592 if (sc->sc_flags.status_vbus && 2593 sc->sc_flags.status_bus_reset) { 2594 /* reset EP0 state */ 2595 sc->sc_ep0_busy = 0; 2596 sc->sc_ep0_cmd = 0; 2597 } 2598 } 2599 if (sc->sc_flags.change_suspend) { 2600 value |= UPS_C_SUSPEND; 2601 } 2602 USETW(sc->sc_hub_temp.ps.wPortChange, value); 2603 len = sizeof(sc->sc_hub_temp.ps); 2604 goto tr_valid; 2605 2606tr_handle_get_class_descriptor: 2607 if (value & 0xFF) { 2608 goto tr_stalled; 2609 } 2610 ptr = (const void *)&musbotg_hubd; 2611 len = sizeof(musbotg_hubd); 2612 goto tr_valid; 2613 2614tr_stalled: 2615 err = USB_ERR_STALLED; 2616tr_valid: 2617done: 2618 *plength = len; 2619 *pptr = ptr; 2620 return (err); 2621} 2622 2623static void 2624musbotg_xfer_setup(struct usb_setup_params *parm) 2625{ 2626 const struct usb_hw_ep_profile *pf; 2627 struct musbotg_softc *sc; 2628 struct usb_xfer *xfer; 2629 void *last_obj; 2630 uint32_t ntd; 2631 uint32_t n; 2632 uint8_t ep_no; 2633 2634 sc = MUSBOTG_BUS2SC(parm->udev->bus); 2635 xfer = parm->curr_xfer; 2636 2637 /* 2638 * NOTE: This driver does not use any of the parameters that 2639 * are computed from the following values. Just set some 2640 * reasonable dummies: 2641 */ 2642 parm->hc_max_packet_size = 0x400; 2643 parm->hc_max_frame_size = 0x400; 2644 2645 if ((parm->methods == &musbotg_device_isoc_methods) || 2646 (parm->methods == &musbotg_device_intr_methods)) 2647 parm->hc_max_packet_count = 3; 2648 else 2649 parm->hc_max_packet_count = 1; 2650 2651 usbd_transfer_setup_sub(parm); 2652 2653 /* 2654 * compute maximum number of TDs 2655 */ 2656 if (parm->methods == &musbotg_device_ctrl_methods) { 2657 2658 ntd = xfer->nframes + 1 /* STATUS */ + 1 /* SYNC */ ; 2659 2660 } else if (parm->methods == &musbotg_device_bulk_methods) { 2661 2662 ntd = xfer->nframes + 1 /* SYNC */ ; 2663 2664 } else if (parm->methods == &musbotg_device_intr_methods) { 2665 2666 ntd = xfer->nframes + 1 /* SYNC */ ; 2667 2668 } else if (parm->methods == &musbotg_device_isoc_methods) { 2669 2670 ntd = xfer->nframes + 1 /* SYNC */ ; 2671 2672 } else { 2673 2674 ntd = 0; 2675 } 2676 2677 /* 2678 * check if "usbd_transfer_setup_sub" set an error 2679 */ 2680 if (parm->err) { 2681 return; 2682 } 2683 /* 2684 * allocate transfer descriptors 2685 */ 2686 last_obj = NULL; 2687 2688 /* 2689 * get profile stuff 2690 */ 2691 if (ntd) { 2692 2693 ep_no = xfer->endpointno & UE_ADDR; 2694 musbotg_get_hw_ep_profile(parm->udev, &pf, ep_no); 2695 2696 if (pf == NULL) { 2697 /* should not happen */ 2698 parm->err = USB_ERR_INVAL; 2699 return; 2700 } 2701 } else { 2702 ep_no = 0; 2703 pf = NULL; 2704 } 2705 2706 /* align data */ 2707 parm->size[0] += ((-parm->size[0]) & (USB_HOST_ALIGN - 1)); 2708 2709 for (n = 0; n != ntd; n++) { 2710 2711 struct musbotg_td *td; 2712 2713 if (parm->buf) { 2714 2715 td = USB_ADD_BYTES(parm->buf, parm->size[0]); 2716 2717 /* init TD */ 2718 td->max_frame_size = xfer->max_frame_size; 2719 td->ep_no = ep_no; 2720 td->obj_next = last_obj; 2721 2722 last_obj = td; 2723 } 2724 parm->size[0] += sizeof(*td); 2725 } 2726 2727 xfer->td_start[0] = last_obj; 2728} 2729 2730static void 2731musbotg_xfer_unsetup(struct usb_xfer *xfer) 2732{ 2733 return; 2734} 2735 2736static void 2737musbotg_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc, 2738 struct usb_endpoint *ep) 2739{ 2740 struct musbotg_softc *sc = MUSBOTG_BUS2SC(udev->bus); 2741 2742 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d (%d)\n", 2743 ep, udev->address, 2744 edesc->bEndpointAddress, udev->flags.usb_mode, 2745 sc->sc_rt_addr); 2746 2747 if (udev->device_index != sc->sc_rt_addr) { 2748 2749 if ((udev->speed != USB_SPEED_FULL) && 2750 (udev->speed != USB_SPEED_HIGH)) { 2751 /* not supported */ 2752 return; 2753 } 2754 switch (edesc->bmAttributes & UE_XFERTYPE) { 2755 case UE_CONTROL: 2756 ep->methods = &musbotg_device_ctrl_methods; 2757 break; 2758 case UE_INTERRUPT: 2759 ep->methods = &musbotg_device_intr_methods; 2760 break; 2761 case UE_ISOCHRONOUS: 2762 ep->methods = &musbotg_device_isoc_methods; 2763 break; 2764 case UE_BULK: 2765 ep->methods = &musbotg_device_bulk_methods; 2766 break; 2767 default: 2768 /* do nothing */ 2769 break; 2770 } 2771 } 2772} 2773 2774static void 2775musbotg_set_hw_power_sleep(struct usb_bus *bus, uint32_t state) 2776{ 2777 struct musbotg_softc *sc = MUSBOTG_BUS2SC(bus); 2778 2779 switch (state) { 2780 case USB_HW_POWER_SUSPEND: 2781 musbotg_suspend(sc); 2782 break; 2783 case USB_HW_POWER_SHUTDOWN: 2784 musbotg_uninit(sc); 2785 break; 2786 case USB_HW_POWER_RESUME: 2787 musbotg_resume(sc); 2788 break; 2789 default: 2790 break; 2791 } 2792} 2793 2794struct usb_bus_methods musbotg_bus_methods = 2795{ 2796 .endpoint_init = &musbotg_ep_init, 2797 .xfer_setup = &musbotg_xfer_setup, 2798 .xfer_unsetup = &musbotg_xfer_unsetup, 2799 .get_hw_ep_profile = &musbotg_get_hw_ep_profile, 2800 .set_stall = &musbotg_set_stall, 2801 .clear_stall = &musbotg_clear_stall, 2802 .roothub_exec = &musbotg_roothub_exec, 2803 .xfer_poll = &musbotg_do_poll, 2804 .set_hw_power_sleep = &musbotg_set_hw_power_sleep, 2805}; 2806