musb_otg.c revision 201758
1/* $FreeBSD: head/sys/dev/usb/controller/musb_otg.c 201758 2010-01-07 21:01:37Z mbr $ */ 2/*- 3 * Copyright (c) 2008 Hans Petter Selasky. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27/* 28 * Thanks to Mentor Graphics for providing a reference driver for this USB chip 29 * at their homepage. 30 */ 31 32/* 33 * This file contains the driver for the Mentor Graphics Inventra USB 34 * 2.0 High Speed Dual-Role controller. 35 * 36 * NOTE: The current implementation only supports Device Side Mode! 37 */ 38 39#include <sys/stdint.h> 40#include <sys/stddef.h> 41#include <sys/param.h> 42#include <sys/queue.h> 43#include <sys/types.h> 44#include <sys/systm.h> 45#include <sys/kernel.h> 46#include <sys/bus.h> 47#include <sys/linker_set.h> 48#include <sys/module.h> 49#include <sys/lock.h> 50#include <sys/mutex.h> 51#include <sys/condvar.h> 52#include <sys/sysctl.h> 53#include <sys/sx.h> 54#include <sys/unistd.h> 55#include <sys/callout.h> 56#include <sys/malloc.h> 57#include <sys/priv.h> 58 59#include <dev/usb/usb.h> 60#include <dev/usb/usbdi.h> 61 62#define USB_DEBUG_VAR musbotgdebug 63 64#include <dev/usb/usb_core.h> 65#include <dev/usb/usb_debug.h> 66#include <dev/usb/usb_busdma.h> 67#include <dev/usb/usb_process.h> 68#include <dev/usb/usb_transfer.h> 69#include <dev/usb/usb_device.h> 70#include <dev/usb/usb_hub.h> 71#include <dev/usb/usb_util.h> 72 73#include <dev/usb/usb_controller.h> 74#include <dev/usb/usb_bus.h> 75#include <dev/usb/controller/musb_otg.h> 76 77#define MUSBOTG_INTR_ENDPT 1 78 79#define MUSBOTG_BUS2SC(bus) \ 80 ((struct musbotg_softc *)(((uint8_t *)(bus)) - \ 81 USB_P2U(&(((struct musbotg_softc *)0)->sc_bus)))) 82 83#define MUSBOTG_PC2SC(pc) \ 84 MUSBOTG_BUS2SC(USB_DMATAG_TO_XROOT((pc)->tag_parent)->bus) 85 86#ifdef USB_DEBUG 87static int musbotgdebug = 0; 88 89SYSCTL_NODE(_hw_usb, OID_AUTO, musbotg, CTLFLAG_RW, 0, "USB musbotg"); 90SYSCTL_INT(_hw_usb_musbotg, OID_AUTO, debug, CTLFLAG_RW, 91 &musbotgdebug, 0, "Debug level"); 92#endif 93 94/* prototypes */ 95 96struct usb_bus_methods musbotg_bus_methods; 97struct usb_pipe_methods musbotg_device_bulk_methods; 98struct usb_pipe_methods musbotg_device_ctrl_methods; 99struct usb_pipe_methods musbotg_device_intr_methods; 100struct usb_pipe_methods musbotg_device_isoc_methods; 101 102static musbotg_cmd_t musbotg_setup_rx; 103static musbotg_cmd_t musbotg_setup_data_rx; 104static musbotg_cmd_t musbotg_setup_data_tx; 105static musbotg_cmd_t musbotg_setup_status; 106static musbotg_cmd_t musbotg_data_rx; 107static musbotg_cmd_t musbotg_data_tx; 108static void musbotg_device_done(struct usb_xfer *, usb_error_t); 109static void musbotg_do_poll(struct usb_bus *); 110static void musbotg_standard_done(struct usb_xfer *); 111static void musbotg_interrupt_poll(struct musbotg_softc *); 112static void musbotg_root_intr(struct musbotg_softc *); 113 114/* 115 * Here is a configuration that the chip supports. 116 */ 117static const struct usb_hw_ep_profile musbotg_ep_profile[1] = { 118 119 [0] = { 120 .max_in_frame_size = 64,/* fixed */ 121 .max_out_frame_size = 64, /* fixed */ 122 .is_simplex = 1, 123 .support_control = 1, 124 } 125}; 126 127static void 128musbotg_get_hw_ep_profile(struct usb_device *udev, 129 const struct usb_hw_ep_profile **ppf, uint8_t ep_addr) 130{ 131 struct musbotg_softc *sc; 132 133 sc = MUSBOTG_BUS2SC(udev->bus); 134 135 if (ep_addr == 0) { 136 /* control endpoint */ 137 *ppf = musbotg_ep_profile; 138 } else if (ep_addr <= sc->sc_ep_max) { 139 /* other endpoints */ 140 *ppf = sc->sc_hw_ep_profile + ep_addr; 141 } else { 142 *ppf = NULL; 143 } 144} 145 146static void 147musbotg_clocks_on(struct musbotg_softc *sc) 148{ 149 if (sc->sc_flags.clocks_off && 150 sc->sc_flags.port_powered) { 151 152 DPRINTFN(4, "\n"); 153 154 if (sc->sc_clocks_on) { 155 (sc->sc_clocks_on) (sc->sc_clocks_arg); 156 } 157 sc->sc_flags.clocks_off = 0; 158 159 /* XXX enable Transceiver */ 160 } 161} 162 163static void 164musbotg_clocks_off(struct musbotg_softc *sc) 165{ 166 if (!sc->sc_flags.clocks_off) { 167 168 DPRINTFN(4, "\n"); 169 170 /* XXX disable Transceiver */ 171 172 if (sc->sc_clocks_off) { 173 (sc->sc_clocks_off) (sc->sc_clocks_arg); 174 } 175 sc->sc_flags.clocks_off = 1; 176 } 177} 178 179static void 180musbotg_pull_common(struct musbotg_softc *sc, uint8_t on) 181{ 182 uint8_t temp; 183 184 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER); 185 if (on) 186 temp |= MUSB2_MASK_SOFTC; 187 else 188 temp &= ~MUSB2_MASK_SOFTC; 189 190 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp); 191} 192 193static void 194musbotg_pull_up(struct musbotg_softc *sc) 195{ 196 /* pullup D+, if possible */ 197 198 if (!sc->sc_flags.d_pulled_up && 199 sc->sc_flags.port_powered) { 200 sc->sc_flags.d_pulled_up = 1; 201 musbotg_pull_common(sc, 1); 202 } 203} 204 205static void 206musbotg_pull_down(struct musbotg_softc *sc) 207{ 208 /* pulldown D+, if possible */ 209 210 if (sc->sc_flags.d_pulled_up) { 211 sc->sc_flags.d_pulled_up = 0; 212 musbotg_pull_common(sc, 0); 213 } 214} 215 216static void 217musbotg_wakeup_peer(struct musbotg_softc *sc) 218{ 219 uint8_t temp; 220 221 if (!(sc->sc_flags.status_suspend)) { 222 return; 223 } 224 225 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER); 226 temp |= MUSB2_MASK_RESUME; 227 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp); 228 229 /* wait 8 milliseconds */ 230 /* Wait for reset to complete. */ 231 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 125); 232 233 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER); 234 temp &= ~MUSB2_MASK_RESUME; 235 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp); 236} 237 238static void 239musbotg_set_address(struct musbotg_softc *sc, uint8_t addr) 240{ 241 DPRINTFN(4, "addr=%d\n", addr); 242 addr &= 0x7F; 243 MUSB2_WRITE_1(sc, MUSB2_REG_FADDR, addr); 244} 245 246static uint8_t 247musbotg_setup_rx(struct musbotg_td *td) 248{ 249 struct musbotg_softc *sc; 250 struct usb_device_request req; 251 uint16_t count; 252 uint8_t csr; 253 254 /* get pointer to softc */ 255 sc = MUSBOTG_PC2SC(td->pc); 256 257 /* select endpoint 0 */ 258 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); 259 260 /* read out FIFO status */ 261 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 262 263 DPRINTFN(4, "csr=0x%02x\n", csr); 264 265 /* 266 * NOTE: If DATAEND is set we should not call the 267 * callback, hence the status stage is not complete. 268 */ 269 if (csr & MUSB2_MASK_CSR0L_DATAEND) { 270 /* do not stall at this point */ 271 td->did_stall = 1; 272 /* wait for interrupt */ 273 goto not_complete; 274 } 275 if (csr & MUSB2_MASK_CSR0L_SENTSTALL) { 276 /* clear SENTSTALL */ 277 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0); 278 /* get latest status */ 279 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 280 /* update EP0 state */ 281 sc->sc_ep0_busy = 0; 282 } 283 if (csr & MUSB2_MASK_CSR0L_SETUPEND) { 284 /* clear SETUPEND */ 285 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 286 MUSB2_MASK_CSR0L_SETUPEND_CLR); 287 /* get latest status */ 288 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 289 /* update EP0 state */ 290 sc->sc_ep0_busy = 0; 291 } 292 if (sc->sc_ep0_busy) { 293 goto not_complete; 294 } 295 if (!(csr & MUSB2_MASK_CSR0L_RXPKTRDY)) { 296 goto not_complete; 297 } 298 /* clear did stall flag */ 299 td->did_stall = 0; 300 /* get the packet byte count */ 301 count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT); 302 303 /* verify data length */ 304 if (count != td->remainder) { 305 DPRINTFN(0, "Invalid SETUP packet " 306 "length, %d bytes\n", count); 307 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 308 MUSB2_MASK_CSR0L_RXPKTRDY_CLR); 309 goto not_complete; 310 } 311 if (count != sizeof(req)) { 312 DPRINTFN(0, "Unsupported SETUP packet " 313 "length, %d bytes\n", count); 314 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 315 MUSB2_MASK_CSR0L_RXPKTRDY_CLR); 316 goto not_complete; 317 } 318 /* receive data */ 319 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 320 MUSB2_REG_EPFIFO(0), (void *)&req, sizeof(req)); 321 322 /* copy data into real buffer */ 323 usbd_copy_in(td->pc, 0, &req, sizeof(req)); 324 325 td->offset = sizeof(req); 326 td->remainder = 0; 327 328 /* set pending command */ 329 sc->sc_ep0_cmd = MUSB2_MASK_CSR0L_RXPKTRDY_CLR; 330 331 /* we need set stall or dataend after this */ 332 sc->sc_ep0_busy = 1; 333 334 /* sneak peek the set address */ 335 if ((req.bmRequestType == UT_WRITE_DEVICE) && 336 (req.bRequest == UR_SET_ADDRESS)) { 337 sc->sc_dv_addr = req.wValue[0] & 0x7F; 338 } else { 339 sc->sc_dv_addr = 0xFF; 340 } 341 return (0); /* complete */ 342 343not_complete: 344 /* abort any ongoing transfer */ 345 if (!td->did_stall) { 346 DPRINTFN(4, "stalling\n"); 347 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 348 MUSB2_MASK_CSR0L_SENDSTALL); 349 td->did_stall = 1; 350 } 351 return (1); /* not complete */ 352} 353 354/* Control endpoint only data handling functions (RX/TX/SYNC) */ 355 356static uint8_t 357musbotg_setup_data_rx(struct musbotg_td *td) 358{ 359 struct usb_page_search buf_res; 360 struct musbotg_softc *sc; 361 uint16_t count; 362 uint8_t csr; 363 uint8_t got_short; 364 365 /* get pointer to softc */ 366 sc = MUSBOTG_PC2SC(td->pc); 367 368 /* select endpoint 0 */ 369 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); 370 371 /* check if a command is pending */ 372 if (sc->sc_ep0_cmd) { 373 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, sc->sc_ep0_cmd); 374 sc->sc_ep0_cmd = 0; 375 } 376 /* read out FIFO status */ 377 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 378 379 DPRINTFN(4, "csr=0x%02x\n", csr); 380 381 got_short = 0; 382 383 if (csr & (MUSB2_MASK_CSR0L_SETUPEND | 384 MUSB2_MASK_CSR0L_SENTSTALL)) { 385 if (td->remainder == 0) { 386 /* 387 * We are actually complete and have 388 * received the next SETUP 389 */ 390 DPRINTFN(4, "faking complete\n"); 391 return (0); /* complete */ 392 } 393 /* 394 * USB Host Aborted the transfer. 395 */ 396 td->error = 1; 397 return (0); /* complete */ 398 } 399 if (!(csr & MUSB2_MASK_CSR0L_RXPKTRDY)) { 400 return (1); /* not complete */ 401 } 402 /* get the packet byte count */ 403 count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT); 404 405 /* verify the packet byte count */ 406 if (count != td->max_frame_size) { 407 if (count < td->max_frame_size) { 408 /* we have a short packet */ 409 td->short_pkt = 1; 410 got_short = 1; 411 } else { 412 /* invalid USB packet */ 413 td->error = 1; 414 return (0); /* we are complete */ 415 } 416 } 417 /* verify the packet byte count */ 418 if (count > td->remainder) { 419 /* invalid USB packet */ 420 td->error = 1; 421 return (0); /* we are complete */ 422 } 423 while (count > 0) { 424 uint32_t temp; 425 426 usbd_get_page(td->pc, td->offset, &buf_res); 427 428 /* get correct length */ 429 if (buf_res.length > count) { 430 buf_res.length = count; 431 } 432 /* check for unaligned memory address */ 433 if (USB_P2U(buf_res.buffer) & 3) { 434 435 temp = count & ~3; 436 437 if (temp) { 438 /* receive data 4 bytes at a time */ 439 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 440 MUSB2_REG_EPFIFO(0), sc->sc_bounce_buf, 441 temp / 4); 442 } 443 temp = count & 3; 444 if (temp) { 445 /* receive data 1 byte at a time */ 446 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 447 MUSB2_REG_EPFIFO(0), 448 (void *)(&sc->sc_bounce_buf[count / 4]), temp); 449 } 450 usbd_copy_in(td->pc, td->offset, 451 sc->sc_bounce_buf, count); 452 453 /* update offset and remainder */ 454 td->offset += count; 455 td->remainder -= count; 456 break; 457 } 458 /* check if we can optimise */ 459 if (buf_res.length >= 4) { 460 461 /* receive data 4 bytes at a time */ 462 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 463 MUSB2_REG_EPFIFO(0), buf_res.buffer, 464 buf_res.length / 4); 465 466 temp = buf_res.length & ~3; 467 468 /* update counters */ 469 count -= temp; 470 td->offset += temp; 471 td->remainder -= temp; 472 continue; 473 } 474 /* receive data */ 475 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 476 MUSB2_REG_EPFIFO(0), buf_res.buffer, buf_res.length); 477 478 /* update counters */ 479 count -= buf_res.length; 480 td->offset += buf_res.length; 481 td->remainder -= buf_res.length; 482 } 483 484 /* check if we are complete */ 485 if ((td->remainder == 0) || got_short) { 486 if (td->short_pkt) { 487 /* we are complete */ 488 sc->sc_ep0_cmd = MUSB2_MASK_CSR0L_RXPKTRDY_CLR; 489 return (0); 490 } 491 /* else need to receive a zero length packet */ 492 } 493 /* write command - need more data */ 494 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 495 MUSB2_MASK_CSR0L_RXPKTRDY_CLR); 496 return (1); /* not complete */ 497} 498 499static uint8_t 500musbotg_setup_data_tx(struct musbotg_td *td) 501{ 502 struct usb_page_search buf_res; 503 struct musbotg_softc *sc; 504 uint16_t count; 505 uint8_t csr; 506 507 /* get pointer to softc */ 508 sc = MUSBOTG_PC2SC(td->pc); 509 510 /* select endpoint 0 */ 511 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); 512 513 /* check if a command is pending */ 514 if (sc->sc_ep0_cmd) { 515 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, sc->sc_ep0_cmd); 516 sc->sc_ep0_cmd = 0; 517 } 518 /* read out FIFO status */ 519 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 520 521 DPRINTFN(4, "csr=0x%02x\n", csr); 522 523 if (csr & (MUSB2_MASK_CSR0L_SETUPEND | 524 MUSB2_MASK_CSR0L_SENTSTALL)) { 525 /* 526 * The current transfer was aborted 527 * by the USB Host 528 */ 529 td->error = 1; 530 return (0); /* complete */ 531 } 532 if (csr & MUSB2_MASK_CSR0L_TXPKTRDY) { 533 return (1); /* not complete */ 534 } 535 count = td->max_frame_size; 536 if (td->remainder < count) { 537 /* we have a short packet */ 538 td->short_pkt = 1; 539 count = td->remainder; 540 } 541 while (count > 0) { 542 uint32_t temp; 543 544 usbd_get_page(td->pc, td->offset, &buf_res); 545 546 /* get correct length */ 547 if (buf_res.length > count) { 548 buf_res.length = count; 549 } 550 /* check for unaligned memory address */ 551 if (USB_P2U(buf_res.buffer) & 3) { 552 553 usbd_copy_out(td->pc, td->offset, 554 sc->sc_bounce_buf, count); 555 556 temp = count & ~3; 557 558 if (temp) { 559 /* transmit data 4 bytes at a time */ 560 bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 561 MUSB2_REG_EPFIFO(0), sc->sc_bounce_buf, 562 temp / 4); 563 } 564 temp = count & 3; 565 if (temp) { 566 /* receive data 1 byte at a time */ 567 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 568 MUSB2_REG_EPFIFO(0), 569 ((void *)&sc->sc_bounce_buf[count / 4]), temp); 570 } 571 /* update offset and remainder */ 572 td->offset += count; 573 td->remainder -= count; 574 break; 575 } 576 /* check if we can optimise */ 577 if (buf_res.length >= 4) { 578 579 /* transmit data 4 bytes at a time */ 580 bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 581 MUSB2_REG_EPFIFO(0), buf_res.buffer, 582 buf_res.length / 4); 583 584 temp = buf_res.length & ~3; 585 586 /* update counters */ 587 count -= temp; 588 td->offset += temp; 589 td->remainder -= temp; 590 continue; 591 } 592 /* transmit data */ 593 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 594 MUSB2_REG_EPFIFO(0), buf_res.buffer, buf_res.length); 595 596 /* update counters */ 597 count -= buf_res.length; 598 td->offset += buf_res.length; 599 td->remainder -= buf_res.length; 600 } 601 602 /* check remainder */ 603 if (td->remainder == 0) { 604 if (td->short_pkt) { 605 sc->sc_ep0_cmd = MUSB2_MASK_CSR0L_TXPKTRDY; 606 return (0); /* complete */ 607 } 608 /* else we need to transmit a short packet */ 609 } 610 /* write command */ 611 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 612 MUSB2_MASK_CSR0L_TXPKTRDY); 613 614 return (1); /* not complete */ 615} 616 617static uint8_t 618musbotg_setup_status(struct musbotg_td *td) 619{ 620 struct musbotg_softc *sc; 621 uint8_t csr; 622 623 /* get pointer to softc */ 624 sc = MUSBOTG_PC2SC(td->pc); 625 626 /* select endpoint 0 */ 627 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); 628 629 if (sc->sc_ep0_busy) { 630 sc->sc_ep0_busy = 0; 631 sc->sc_ep0_cmd |= MUSB2_MASK_CSR0L_DATAEND; 632 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, sc->sc_ep0_cmd); 633 sc->sc_ep0_cmd = 0; 634 } 635 /* read out FIFO status */ 636 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 637 638 DPRINTFN(4, "csr=0x%02x\n", csr); 639 640 if (csr & MUSB2_MASK_CSR0L_DATAEND) { 641 /* wait for interrupt */ 642 return (1); /* not complete */ 643 } 644 if (sc->sc_dv_addr != 0xFF) { 645 /* write function address */ 646 musbotg_set_address(sc, sc->sc_dv_addr); 647 } 648 return (0); /* complete */ 649} 650 651static uint8_t 652musbotg_data_rx(struct musbotg_td *td) 653{ 654 struct usb_page_search buf_res; 655 struct musbotg_softc *sc; 656 uint16_t count; 657 uint8_t csr; 658 uint8_t to; 659 uint8_t got_short; 660 661 to = 8; /* don't loop forever! */ 662 got_short = 0; 663 664 /* get pointer to softc */ 665 sc = MUSBOTG_PC2SC(td->pc); 666 667 /* select endpoint */ 668 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, td->ep_no); 669 670repeat: 671 /* read out FIFO status */ 672 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL); 673 674 DPRINTFN(4, "csr=0x%02x\n", csr); 675 676 /* clear overrun */ 677 if (csr & MUSB2_MASK_CSRL_RXOVERRUN) { 678 /* make sure we don't clear "RXPKTRDY" */ 679 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 680 MUSB2_MASK_CSRL_RXPKTRDY); 681 } 682 /* check status */ 683 if (!(csr & MUSB2_MASK_CSRL_RXPKTRDY)) { 684 return (1); /* not complete */ 685 } 686 /* get the packet byte count */ 687 count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT); 688 689 DPRINTFN(4, "count=0x%04x\n", count); 690 691 /* 692 * Check for short or invalid packet: 693 */ 694 if (count != td->max_frame_size) { 695 if (count < td->max_frame_size) { 696 /* we have a short packet */ 697 td->short_pkt = 1; 698 got_short = 1; 699 } else { 700 /* invalid USB packet */ 701 td->error = 1; 702 return (0); /* we are complete */ 703 } 704 } 705 /* verify the packet byte count */ 706 if (count > td->remainder) { 707 /* invalid USB packet */ 708 td->error = 1; 709 return (0); /* we are complete */ 710 } 711 while (count > 0) { 712 uint32_t temp; 713 714 usbd_get_page(td->pc, td->offset, &buf_res); 715 716 /* get correct length */ 717 if (buf_res.length > count) { 718 buf_res.length = count; 719 } 720 /* check for unaligned memory address */ 721 if (USB_P2U(buf_res.buffer) & 3) { 722 723 temp = count & ~3; 724 725 if (temp) { 726 /* receive data 4 bytes at a time */ 727 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 728 MUSB2_REG_EPFIFO(td->ep_no), sc->sc_bounce_buf, 729 temp / 4); 730 } 731 temp = count & 3; 732 if (temp) { 733 /* receive data 1 byte at a time */ 734 bus_space_read_multi_1(sc->sc_io_tag, 735 sc->sc_io_hdl, MUSB2_REG_EPFIFO(td->ep_no), 736 ((void *)&sc->sc_bounce_buf[count / 4]), temp); 737 } 738 usbd_copy_in(td->pc, td->offset, 739 sc->sc_bounce_buf, count); 740 741 /* update offset and remainder */ 742 td->offset += count; 743 td->remainder -= count; 744 break; 745 } 746 /* check if we can optimise */ 747 if (buf_res.length >= 4) { 748 749 /* receive data 4 bytes at a time */ 750 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 751 MUSB2_REG_EPFIFO(td->ep_no), buf_res.buffer, 752 buf_res.length / 4); 753 754 temp = buf_res.length & ~3; 755 756 /* update counters */ 757 count -= temp; 758 td->offset += temp; 759 td->remainder -= temp; 760 continue; 761 } 762 /* receive data */ 763 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 764 MUSB2_REG_EPFIFO(td->ep_no), buf_res.buffer, 765 buf_res.length); 766 767 /* update counters */ 768 count -= buf_res.length; 769 td->offset += buf_res.length; 770 td->remainder -= buf_res.length; 771 } 772 773 /* clear status bits */ 774 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 0); 775 776 /* check if we are complete */ 777 if ((td->remainder == 0) || got_short) { 778 if (td->short_pkt) { 779 /* we are complete */ 780 return (0); 781 } 782 /* else need to receive a zero length packet */ 783 } 784 if (--to) { 785 goto repeat; 786 } 787 return (1); /* not complete */ 788} 789 790static uint8_t 791musbotg_data_tx(struct musbotg_td *td) 792{ 793 struct usb_page_search buf_res; 794 struct musbotg_softc *sc; 795 uint16_t count; 796 uint8_t csr; 797 uint8_t to; 798 799 to = 8; /* don't loop forever! */ 800 801 /* get pointer to softc */ 802 sc = MUSBOTG_PC2SC(td->pc); 803 804 /* select endpoint */ 805 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, td->ep_no); 806 807repeat: 808 809 /* read out FIFO status */ 810 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 811 812 DPRINTFN(4, "csr=0x%02x\n", csr); 813 814 if (csr & (MUSB2_MASK_CSRL_TXINCOMP | 815 MUSB2_MASK_CSRL_TXUNDERRUN)) { 816 /* clear status bits */ 817 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0); 818 } 819 if (csr & MUSB2_MASK_CSRL_TXPKTRDY) { 820 return (1); /* not complete */ 821 } 822 /* check for short packet */ 823 count = td->max_frame_size; 824 if (td->remainder < count) { 825 /* we have a short packet */ 826 td->short_pkt = 1; 827 count = td->remainder; 828 } 829 while (count > 0) { 830 uint32_t temp; 831 832 usbd_get_page(td->pc, td->offset, &buf_res); 833 834 /* get correct length */ 835 if (buf_res.length > count) { 836 buf_res.length = count; 837 } 838 /* check for unaligned memory address */ 839 if (USB_P2U(buf_res.buffer) & 3) { 840 841 usbd_copy_out(td->pc, td->offset, 842 sc->sc_bounce_buf, count); 843 844 temp = count & ~3; 845 846 if (temp) { 847 /* transmit data 4 bytes at a time */ 848 bus_space_write_multi_4(sc->sc_io_tag, 849 sc->sc_io_hdl, MUSB2_REG_EPFIFO(td->ep_no), 850 sc->sc_bounce_buf, temp / 4); 851 } 852 temp = count & 3; 853 if (temp) { 854 /* receive data 1 byte at a time */ 855 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 856 MUSB2_REG_EPFIFO(td->ep_no), 857 ((void *)&sc->sc_bounce_buf[count / 4]), temp); 858 } 859 /* update offset and remainder */ 860 td->offset += count; 861 td->remainder -= count; 862 break; 863 } 864 /* check if we can optimise */ 865 if (buf_res.length >= 4) { 866 867 /* transmit data 4 bytes at a time */ 868 bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 869 MUSB2_REG_EPFIFO(td->ep_no), buf_res.buffer, 870 buf_res.length / 4); 871 872 temp = buf_res.length & ~3; 873 874 /* update counters */ 875 count -= temp; 876 td->offset += temp; 877 td->remainder -= temp; 878 continue; 879 } 880 /* transmit data */ 881 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 882 MUSB2_REG_EPFIFO(td->ep_no), buf_res.buffer, 883 buf_res.length); 884 885 /* update counters */ 886 count -= buf_res.length; 887 td->offset += buf_res.length; 888 td->remainder -= buf_res.length; 889 } 890 891 /* write command */ 892 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 893 MUSB2_MASK_CSRL_TXPKTRDY); 894 895 /* check remainder */ 896 if (td->remainder == 0) { 897 if (td->short_pkt) { 898 return (0); /* complete */ 899 } 900 /* else we need to transmit a short packet */ 901 } 902 if (--to) { 903 goto repeat; 904 } 905 return (1); /* not complete */ 906} 907 908static uint8_t 909musbotg_xfer_do_fifo(struct usb_xfer *xfer) 910{ 911 struct musbotg_softc *sc; 912 struct musbotg_td *td; 913 914 DPRINTFN(8, "\n"); 915 916 td = xfer->td_transfer_cache; 917 while (1) { 918 if ((td->func) (td)) { 919 /* operation in progress */ 920 break; 921 } 922 if (((void *)td) == xfer->td_transfer_last) { 923 goto done; 924 } 925 if (td->error) { 926 goto done; 927 } else if (td->remainder > 0) { 928 /* 929 * We had a short transfer. If there is no alternate 930 * next, stop processing ! 931 */ 932 if (!td->alt_next) { 933 goto done; 934 } 935 } 936 /* 937 * Fetch the next transfer descriptor and transfer 938 * some flags to the next transfer descriptor 939 */ 940 td = td->obj_next; 941 xfer->td_transfer_cache = td; 942 } 943 return (1); /* not complete */ 944 945done: 946 sc = MUSBOTG_BUS2SC(xfer->xroot->bus); 947 948 /* compute all actual lengths */ 949 950 musbotg_standard_done(xfer); 951 952 return (0); /* complete */ 953} 954 955static void 956musbotg_interrupt_poll(struct musbotg_softc *sc) 957{ 958 struct usb_xfer *xfer; 959 960repeat: 961 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 962 if (!musbotg_xfer_do_fifo(xfer)) { 963 /* queue has been modified */ 964 goto repeat; 965 } 966 } 967} 968 969void 970musbotg_vbus_interrupt(struct musbotg_softc *sc, uint8_t is_on) 971{ 972 DPRINTFN(4, "vbus = %u\n", is_on); 973 974 USB_BUS_LOCK(&sc->sc_bus); 975 if (is_on) { 976 if (!sc->sc_flags.status_vbus) { 977 sc->sc_flags.status_vbus = 1; 978 979 /* complete root HUB interrupt endpoint */ 980 musbotg_root_intr(sc); 981 } 982 } else { 983 if (sc->sc_flags.status_vbus) { 984 sc->sc_flags.status_vbus = 0; 985 sc->sc_flags.status_bus_reset = 0; 986 sc->sc_flags.status_suspend = 0; 987 sc->sc_flags.change_suspend = 0; 988 sc->sc_flags.change_connect = 1; 989 990 /* complete root HUB interrupt endpoint */ 991 musbotg_root_intr(sc); 992 } 993 } 994 995 USB_BUS_UNLOCK(&sc->sc_bus); 996} 997 998void 999musbotg_interrupt(struct musbotg_softc *sc) 1000{ 1001 uint16_t rx_status; 1002 uint16_t tx_status; 1003 uint8_t usb_status; 1004 uint8_t temp; 1005 uint8_t to = 2; 1006 1007 USB_BUS_LOCK(&sc->sc_bus); 1008 1009repeat: 1010 1011 /* read all interrupt registers */ 1012 usb_status = MUSB2_READ_1(sc, MUSB2_REG_INTUSB); 1013 1014 /* read all FIFO interrupts */ 1015 rx_status = MUSB2_READ_2(sc, MUSB2_REG_INTRX); 1016 tx_status = MUSB2_READ_2(sc, MUSB2_REG_INTTX); 1017 1018 /* check for any bus state change interrupts */ 1019 1020 if (usb_status & (MUSB2_MASK_IRESET | 1021 MUSB2_MASK_IRESUME | MUSB2_MASK_ISUSP)) { 1022 1023 DPRINTFN(4, "real bus interrupt 0x%08x\n", usb_status); 1024 1025 if (usb_status & MUSB2_MASK_IRESET) { 1026 1027 /* set correct state */ 1028 sc->sc_flags.status_bus_reset = 1; 1029 sc->sc_flags.status_suspend = 0; 1030 sc->sc_flags.change_suspend = 0; 1031 sc->sc_flags.change_connect = 1; 1032 1033 /* determine line speed */ 1034 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER); 1035 if (temp & MUSB2_MASK_HSMODE) 1036 sc->sc_flags.status_high_speed = 1; 1037 else 1038 sc->sc_flags.status_high_speed = 0; 1039 1040 /* 1041 * After reset all interrupts are on and we need to 1042 * turn them off! 1043 */ 1044 temp = MUSB2_MASK_IRESET; 1045 /* disable resume interrupt */ 1046 temp &= ~MUSB2_MASK_IRESUME; 1047 /* enable suspend interrupt */ 1048 temp |= MUSB2_MASK_ISUSP; 1049 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, temp); 1050 /* disable TX and RX interrupts */ 1051 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, 0); 1052 MUSB2_WRITE_2(sc, MUSB2_REG_INTRXE, 0); 1053 } 1054 /* 1055 * If RXRSM and RXSUSP is set at the same time we interpret 1056 * that like RESUME. Resume is set when there is at least 3 1057 * milliseconds of inactivity on the USB BUS. 1058 */ 1059 if (usb_status & MUSB2_MASK_IRESUME) { 1060 if (sc->sc_flags.status_suspend) { 1061 sc->sc_flags.status_suspend = 0; 1062 sc->sc_flags.change_suspend = 1; 1063 1064 temp = MUSB2_READ_1(sc, MUSB2_REG_INTUSBE); 1065 /* disable resume interrupt */ 1066 temp &= ~MUSB2_MASK_IRESUME; 1067 /* enable suspend interrupt */ 1068 temp |= MUSB2_MASK_ISUSP; 1069 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, temp); 1070 } 1071 } else if (usb_status & MUSB2_MASK_ISUSP) { 1072 if (!sc->sc_flags.status_suspend) { 1073 sc->sc_flags.status_suspend = 1; 1074 sc->sc_flags.change_suspend = 1; 1075 1076 temp = MUSB2_READ_1(sc, MUSB2_REG_INTUSBE); 1077 /* disable suspend interrupt */ 1078 temp &= ~MUSB2_MASK_ISUSP; 1079 /* enable resume interrupt */ 1080 temp |= MUSB2_MASK_IRESUME; 1081 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, temp); 1082 } 1083 } 1084 /* complete root HUB interrupt endpoint */ 1085 musbotg_root_intr(sc); 1086 } 1087 /* check for any endpoint interrupts */ 1088 1089 if (rx_status || tx_status) { 1090 DPRINTFN(4, "real endpoint interrupt " 1091 "rx=0x%04x, tx=0x%04x\n", rx_status, tx_status); 1092 } 1093 /* poll one time regardless of FIFO status */ 1094 1095 musbotg_interrupt_poll(sc); 1096 1097 if (--to) 1098 goto repeat; 1099 1100 USB_BUS_UNLOCK(&sc->sc_bus); 1101} 1102 1103static void 1104musbotg_setup_standard_chain_sub(struct musbotg_std_temp *temp) 1105{ 1106 struct musbotg_td *td; 1107 1108 /* get current Transfer Descriptor */ 1109 td = temp->td_next; 1110 temp->td = td; 1111 1112 /* prepare for next TD */ 1113 temp->td_next = td->obj_next; 1114 1115 /* fill out the Transfer Descriptor */ 1116 td->func = temp->func; 1117 td->pc = temp->pc; 1118 td->offset = temp->offset; 1119 td->remainder = temp->len; 1120 td->error = 0; 1121 td->did_stall = temp->did_stall; 1122 td->short_pkt = temp->short_pkt; 1123 td->alt_next = temp->setup_alt_next; 1124} 1125 1126static void 1127musbotg_setup_standard_chain(struct usb_xfer *xfer) 1128{ 1129 struct musbotg_std_temp temp; 1130 struct musbotg_softc *sc; 1131 struct musbotg_td *td; 1132 uint32_t x; 1133 uint8_t ep_no; 1134 1135 DPRINTFN(8, "addr=%d endpt=%d sumlen=%d speed=%d\n", 1136 xfer->address, UE_GET_ADDR(xfer->endpointno), 1137 xfer->sumlen, usbd_get_speed(xfer->xroot->udev)); 1138 1139 temp.max_frame_size = xfer->max_frame_size; 1140 1141 td = xfer->td_start[0]; 1142 xfer->td_transfer_first = td; 1143 xfer->td_transfer_cache = td; 1144 1145 /* setup temp */ 1146 1147 temp.pc = NULL; 1148 temp.td = NULL; 1149 temp.td_next = xfer->td_start[0]; 1150 temp.offset = 0; 1151 temp.setup_alt_next = xfer->flags_int.short_frames_ok; 1152 temp.did_stall = !xfer->flags_int.control_stall; 1153 1154 sc = MUSBOTG_BUS2SC(xfer->xroot->bus); 1155 ep_no = (xfer->endpointno & UE_ADDR); 1156 1157 /* check if we should prepend a setup message */ 1158 1159 if (xfer->flags_int.control_xfr) { 1160 if (xfer->flags_int.control_hdr) { 1161 1162 temp.func = &musbotg_setup_rx; 1163 temp.len = xfer->frlengths[0]; 1164 temp.pc = xfer->frbuffers + 0; 1165 temp.short_pkt = temp.len ? 1 : 0; 1166 1167 musbotg_setup_standard_chain_sub(&temp); 1168 } 1169 x = 1; 1170 } else { 1171 x = 0; 1172 } 1173 1174 if (x != xfer->nframes) { 1175 if (xfer->endpointno & UE_DIR_IN) { 1176 if (xfer->flags_int.control_xfr) 1177 temp.func = &musbotg_setup_data_tx; 1178 else 1179 temp.func = &musbotg_data_tx; 1180 } else { 1181 if (xfer->flags_int.control_xfr) 1182 temp.func = &musbotg_setup_data_rx; 1183 else 1184 temp.func = &musbotg_data_rx; 1185 } 1186 1187 /* setup "pc" pointer */ 1188 temp.pc = xfer->frbuffers + x; 1189 } 1190 while (x != xfer->nframes) { 1191 1192 /* DATA0 / DATA1 message */ 1193 1194 temp.len = xfer->frlengths[x]; 1195 1196 x++; 1197 1198 if (x == xfer->nframes) { 1199 if (xfer->flags_int.control_xfr) { 1200 if (xfer->flags_int.control_act) { 1201 temp.setup_alt_next = 0; 1202 } 1203 } else { 1204 temp.setup_alt_next = 0; 1205 } 1206 } 1207 if (temp.len == 0) { 1208 1209 /* make sure that we send an USB packet */ 1210 1211 temp.short_pkt = 0; 1212 1213 } else { 1214 1215 /* regular data transfer */ 1216 1217 temp.short_pkt = (xfer->flags.force_short_xfer) ? 0 : 1; 1218 } 1219 1220 musbotg_setup_standard_chain_sub(&temp); 1221 1222 if (xfer->flags_int.isochronous_xfr) { 1223 temp.offset += temp.len; 1224 } else { 1225 /* get next Page Cache pointer */ 1226 temp.pc = xfer->frbuffers + x; 1227 } 1228 } 1229 1230 /* check for control transfer */ 1231 if (xfer->flags_int.control_xfr) { 1232 1233 /* always setup a valid "pc" pointer for status and sync */ 1234 temp.pc = xfer->frbuffers + 0; 1235 temp.len = 0; 1236 temp.short_pkt = 0; 1237 temp.setup_alt_next = 0; 1238 1239 /* check if we should append a status stage */ 1240 if (!xfer->flags_int.control_act) { 1241 /* 1242 * Send a DATA1 message and invert the current 1243 * endpoint direction. 1244 */ 1245 temp.func = &musbotg_setup_status; 1246 musbotg_setup_standard_chain_sub(&temp); 1247 } 1248 } 1249 /* must have at least one frame! */ 1250 td = temp.td; 1251 xfer->td_transfer_last = td; 1252} 1253 1254static void 1255musbotg_timeout(void *arg) 1256{ 1257 struct usb_xfer *xfer = arg; 1258 1259 DPRINTFN(1, "xfer=%p\n", xfer); 1260 1261 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 1262 1263 /* transfer is transferred */ 1264 musbotg_device_done(xfer, USB_ERR_TIMEOUT); 1265} 1266 1267static void 1268musbotg_ep_int_set(struct usb_xfer *xfer, uint8_t on) 1269{ 1270 struct musbotg_softc *sc = MUSBOTG_BUS2SC(xfer->xroot->bus); 1271 uint16_t temp; 1272 uint8_t ep_no = xfer->endpointno & UE_ADDR; 1273 1274 /* 1275 * Only enable the endpoint interrupt when we are 1276 * actually waiting for data, hence we are dealing 1277 * with level triggered interrupts ! 1278 */ 1279 if (ep_no == 0) { 1280 temp = MUSB2_READ_2(sc, MUSB2_REG_INTTXE); 1281 if (on) 1282 temp |= MUSB2_MASK_EPINT(0); 1283 else 1284 temp &= ~MUSB2_MASK_EPINT(0); 1285 1286 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, temp); 1287 } else { 1288 if (USB_GET_DATA_ISREAD(xfer)) { 1289 temp = MUSB2_READ_2(sc, MUSB2_REG_INTRXE); 1290 if (on) 1291 temp |= MUSB2_MASK_EPINT(ep_no); 1292 else 1293 temp &= ~MUSB2_MASK_EPINT(ep_no); 1294 MUSB2_WRITE_2(sc, MUSB2_REG_INTRXE, temp); 1295 1296 } else { 1297 temp = MUSB2_READ_2(sc, MUSB2_REG_INTTXE); 1298 if (on) 1299 temp |= MUSB2_MASK_EPINT(ep_no); 1300 else 1301 temp &= ~MUSB2_MASK_EPINT(ep_no); 1302 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, temp); 1303 } 1304 } 1305} 1306 1307static void 1308musbotg_start_standard_chain(struct usb_xfer *xfer) 1309{ 1310 DPRINTFN(8, "\n"); 1311 1312 /* poll one time */ 1313 if (musbotg_xfer_do_fifo(xfer)) { 1314 1315 musbotg_ep_int_set(xfer, 1); 1316 1317 DPRINTFN(14, "enabled interrupts on endpoint\n"); 1318 1319 /* put transfer on interrupt queue */ 1320 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 1321 1322 /* start timeout, if any */ 1323 if (xfer->timeout != 0) { 1324 usbd_transfer_timeout_ms(xfer, 1325 &musbotg_timeout, xfer->timeout); 1326 } 1327 } 1328} 1329 1330static void 1331musbotg_root_intr(struct musbotg_softc *sc) 1332{ 1333 DPRINTFN(8, "\n"); 1334 1335 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1336 1337 /* set port bit */ 1338 sc->sc_hub_idata[0] = 0x02; /* we only have one port */ 1339 1340 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, 1341 sizeof(sc->sc_hub_idata)); 1342} 1343 1344static usb_error_t 1345musbotg_standard_done_sub(struct usb_xfer *xfer) 1346{ 1347 struct musbotg_td *td; 1348 uint32_t len; 1349 uint8_t error; 1350 1351 DPRINTFN(8, "\n"); 1352 1353 td = xfer->td_transfer_cache; 1354 1355 do { 1356 len = td->remainder; 1357 1358 if (xfer->aframes != xfer->nframes) { 1359 /* 1360 * Verify the length and subtract 1361 * the remainder from "frlengths[]": 1362 */ 1363 if (len > xfer->frlengths[xfer->aframes]) { 1364 td->error = 1; 1365 } else { 1366 xfer->frlengths[xfer->aframes] -= len; 1367 } 1368 } 1369 /* Check for transfer error */ 1370 if (td->error) { 1371 /* the transfer is finished */ 1372 error = 1; 1373 td = NULL; 1374 break; 1375 } 1376 /* Check for short transfer */ 1377 if (len > 0) { 1378 if (xfer->flags_int.short_frames_ok) { 1379 /* follow alt next */ 1380 if (td->alt_next) { 1381 td = td->obj_next; 1382 } else { 1383 td = NULL; 1384 } 1385 } else { 1386 /* the transfer is finished */ 1387 td = NULL; 1388 } 1389 error = 0; 1390 break; 1391 } 1392 td = td->obj_next; 1393 1394 /* this USB frame is complete */ 1395 error = 0; 1396 break; 1397 1398 } while (0); 1399 1400 /* update transfer cache */ 1401 1402 xfer->td_transfer_cache = td; 1403 1404 return (error ? 1405 USB_ERR_STALLED : USB_ERR_NORMAL_COMPLETION); 1406} 1407 1408static void 1409musbotg_standard_done(struct usb_xfer *xfer) 1410{ 1411 usb_error_t err = 0; 1412 1413 DPRINTFN(12, "xfer=%p endpoint=%p transfer done\n", 1414 xfer, xfer->endpoint); 1415 1416 /* reset scanner */ 1417 1418 xfer->td_transfer_cache = xfer->td_transfer_first; 1419 1420 if (xfer->flags_int.control_xfr) { 1421 1422 if (xfer->flags_int.control_hdr) { 1423 1424 err = musbotg_standard_done_sub(xfer); 1425 } 1426 xfer->aframes = 1; 1427 1428 if (xfer->td_transfer_cache == NULL) { 1429 goto done; 1430 } 1431 } 1432 while (xfer->aframes != xfer->nframes) { 1433 1434 err = musbotg_standard_done_sub(xfer); 1435 xfer->aframes++; 1436 1437 if (xfer->td_transfer_cache == NULL) { 1438 goto done; 1439 } 1440 } 1441 1442 if (xfer->flags_int.control_xfr && 1443 !xfer->flags_int.control_act) { 1444 1445 err = musbotg_standard_done_sub(xfer); 1446 } 1447done: 1448 musbotg_device_done(xfer, err); 1449} 1450 1451/*------------------------------------------------------------------------* 1452 * musbotg_device_done 1453 * 1454 * NOTE: this function can be called more than one time on the 1455 * same USB transfer! 1456 *------------------------------------------------------------------------*/ 1457static void 1458musbotg_device_done(struct usb_xfer *xfer, usb_error_t error) 1459{ 1460 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 1461 1462 DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n", 1463 xfer, xfer->endpoint, error); 1464 1465 if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) { 1466 1467 musbotg_ep_int_set(xfer, 0); 1468 1469 DPRINTFN(14, "disabled interrupts on endpoint\n"); 1470 } 1471 /* dequeue transfer and start next transfer */ 1472 usbd_transfer_done(xfer, error); 1473} 1474 1475static void 1476musbotg_set_stall(struct usb_device *udev, struct usb_xfer *xfer, 1477 struct usb_endpoint *ep, uint8_t *did_stall) 1478{ 1479 struct musbotg_softc *sc; 1480 uint8_t ep_no; 1481 1482 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 1483 1484 DPRINTFN(4, "endpoint=%p\n", ep); 1485 1486 if (xfer) { 1487 /* cancel any ongoing transfers */ 1488 musbotg_device_done(xfer, USB_ERR_STALLED); 1489 } 1490 /* set FORCESTALL */ 1491 sc = MUSBOTG_BUS2SC(udev->bus); 1492 1493 ep_no = (ep->edesc->bEndpointAddress & UE_ADDR); 1494 1495 /* select endpoint */ 1496 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, ep_no); 1497 1498 if (ep->edesc->bEndpointAddress & UE_DIR_IN) { 1499 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 1500 MUSB2_MASK_CSRL_TXSENDSTALL); 1501 } else { 1502 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 1503 MUSB2_MASK_CSRL_RXSENDSTALL); 1504 } 1505} 1506 1507static void 1508musbotg_clear_stall_sub(struct musbotg_softc *sc, uint16_t wMaxPacket, 1509 uint8_t ep_no, uint8_t ep_type, uint8_t ep_dir) 1510{ 1511 uint16_t mps; 1512 uint16_t temp; 1513 uint8_t csr; 1514 1515 if (ep_type == UE_CONTROL) { 1516 /* clearing stall is not needed */ 1517 return; 1518 } 1519 /* select endpoint */ 1520 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, ep_no); 1521 1522 /* compute max frame size */ 1523 mps = wMaxPacket & 0x7FF; 1524 switch ((wMaxPacket >> 11) & 3) { 1525 case 1: 1526 mps *= 2; 1527 break; 1528 case 2: 1529 mps *= 3; 1530 break; 1531 default: 1532 break; 1533 } 1534 1535 if (ep_dir == UE_DIR_IN) { 1536 1537 temp = 0; 1538 1539 /* Configure endpoint */ 1540 switch (ep_type) { 1541 case UE_INTERRUPT: 1542 MUSB2_WRITE_2(sc, MUSB2_REG_TXMAXP, wMaxPacket); 1543 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, 1544 MUSB2_MASK_CSRH_TXMODE | temp); 1545 break; 1546 case UE_ISOCHRONOUS: 1547 MUSB2_WRITE_2(sc, MUSB2_REG_TXMAXP, wMaxPacket); 1548 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, 1549 MUSB2_MASK_CSRH_TXMODE | 1550 MUSB2_MASK_CSRH_TXISO | temp); 1551 break; 1552 case UE_BULK: 1553 MUSB2_WRITE_2(sc, MUSB2_REG_TXMAXP, wMaxPacket); 1554 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, 1555 MUSB2_MASK_CSRH_TXMODE | temp); 1556 break; 1557 default: 1558 break; 1559 } 1560 1561 /* Need to flush twice in case of double bufring */ 1562 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 1563 if (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) { 1564 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 1565 MUSB2_MASK_CSRL_TXFFLUSH); 1566 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 1567 if (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) { 1568 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 1569 MUSB2_MASK_CSRL_TXFFLUSH); 1570 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 1571 } 1572 } 1573 /* reset data toggle */ 1574 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 1575 MUSB2_MASK_CSRL_TXDT_CLR); 1576 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0); 1577 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 1578 1579 /* set double/single buffering */ 1580 temp = MUSB2_READ_2(sc, MUSB2_REG_TXDBDIS); 1581 if (mps <= (sc->sc_hw_ep_profile[ep_no]. 1582 max_in_frame_size / 2)) { 1583 /* double buffer */ 1584 temp &= ~(1 << ep_no); 1585 } else { 1586 /* single buffer */ 1587 temp |= (1 << ep_no); 1588 } 1589 MUSB2_WRITE_2(sc, MUSB2_REG_TXDBDIS, temp); 1590 1591 /* clear sent stall */ 1592 if (csr & MUSB2_MASK_CSRL_TXSENTSTALL) { 1593 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0); 1594 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 1595 } 1596 } else { 1597 1598 temp = 0; 1599 1600 /* Configure endpoint */ 1601 switch (ep_type) { 1602 case UE_INTERRUPT: 1603 MUSB2_WRITE_2(sc, MUSB2_REG_RXMAXP, wMaxPacket); 1604 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH, 1605 MUSB2_MASK_CSRH_RXNYET | temp); 1606 break; 1607 case UE_ISOCHRONOUS: 1608 MUSB2_WRITE_2(sc, MUSB2_REG_RXMAXP, wMaxPacket); 1609 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH, 1610 MUSB2_MASK_CSRH_RXNYET | 1611 MUSB2_MASK_CSRH_RXISO | temp); 1612 break; 1613 case UE_BULK: 1614 MUSB2_WRITE_2(sc, MUSB2_REG_RXMAXP, wMaxPacket); 1615 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH, temp); 1616 break; 1617 default: 1618 break; 1619 } 1620 1621 /* Need to flush twice in case of double bufring */ 1622 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL); 1623 if (csr & MUSB2_MASK_CSRL_RXPKTRDY) { 1624 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 1625 MUSB2_MASK_CSRL_RXFFLUSH); 1626 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL); 1627 if (csr & MUSB2_MASK_CSRL_RXPKTRDY) { 1628 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 1629 MUSB2_MASK_CSRL_RXFFLUSH); 1630 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL); 1631 } 1632 } 1633 /* reset data toggle */ 1634 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 1635 MUSB2_MASK_CSRL_RXDT_CLR); 1636 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 0); 1637 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL); 1638 1639 /* set double/single buffering */ 1640 temp = MUSB2_READ_2(sc, MUSB2_REG_RXDBDIS); 1641 if (mps <= (sc->sc_hw_ep_profile[ep_no]. 1642 max_out_frame_size / 2)) { 1643 /* double buffer */ 1644 temp &= ~(1 << ep_no); 1645 } else { 1646 /* single buffer */ 1647 temp |= (1 << ep_no); 1648 } 1649 MUSB2_WRITE_2(sc, MUSB2_REG_RXDBDIS, temp); 1650 1651 /* clear sent stall */ 1652 if (csr & MUSB2_MASK_CSRL_RXSENTSTALL) { 1653 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 0); 1654 } 1655 } 1656} 1657 1658static void 1659musbotg_clear_stall(struct usb_device *udev, struct usb_endpoint *ep) 1660{ 1661 struct musbotg_softc *sc; 1662 struct usb_endpoint_descriptor *ed; 1663 1664 DPRINTFN(4, "endpoint=%p\n", ep); 1665 1666 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 1667 1668 /* check mode */ 1669 if (udev->flags.usb_mode != USB_MODE_DEVICE) { 1670 /* not supported */ 1671 return; 1672 } 1673 /* get softc */ 1674 sc = MUSBOTG_BUS2SC(udev->bus); 1675 1676 /* get endpoint descriptor */ 1677 ed = ep->edesc; 1678 1679 /* reset endpoint */ 1680 musbotg_clear_stall_sub(sc, 1681 UGETW(ed->wMaxPacketSize), 1682 (ed->bEndpointAddress & UE_ADDR), 1683 (ed->bmAttributes & UE_XFERTYPE), 1684 (ed->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT))); 1685} 1686 1687usb_error_t 1688musbotg_init(struct musbotg_softc *sc) 1689{ 1690 struct usb_hw_ep_profile *pf; 1691 uint16_t offset; 1692 uint8_t nrx; 1693 uint8_t ntx; 1694 uint8_t temp; 1695 uint8_t fsize; 1696 uint8_t frx; 1697 uint8_t ftx; 1698 uint8_t dynfifo; 1699 1700 DPRINTFN(1, "start\n"); 1701 1702 /* set up the bus structure */ 1703 sc->sc_bus.usbrev = USB_REV_2_0; 1704 sc->sc_bus.methods = &musbotg_bus_methods; 1705 1706 USB_BUS_LOCK(&sc->sc_bus); 1707 1708 /* turn on clocks */ 1709 1710 if (sc->sc_clocks_on) { 1711 (sc->sc_clocks_on) (sc->sc_clocks_arg); 1712 } 1713 /* wait a little for things to stabilise */ 1714 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 1000); 1715 1716 /* disable all interrupts */ 1717 1718 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, 0); 1719 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, 0); 1720 MUSB2_WRITE_2(sc, MUSB2_REG_INTRXE, 0); 1721 1722 /* disable pullup */ 1723 1724 musbotg_pull_common(sc, 0); 1725 1726 /* wait a little bit (10ms) */ 1727 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100); 1728 1729 /* disable double packet buffering */ 1730 MUSB2_WRITE_2(sc, MUSB2_REG_RXDBDIS, 0xFFFF); 1731 MUSB2_WRITE_2(sc, MUSB2_REG_TXDBDIS, 0xFFFF); 1732 1733 /* enable HighSpeed and ISO Update flags */ 1734 1735 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, 1736 MUSB2_MASK_HSENAB | MUSB2_MASK_ISOUPD); 1737 1738 /* clear Session bit, if set */ 1739 1740 temp = MUSB2_READ_1(sc, MUSB2_REG_DEVCTL); 1741 temp &= ~MUSB2_MASK_SESS; 1742 MUSB2_WRITE_1(sc, MUSB2_REG_DEVCTL, temp); 1743 1744 DPRINTF("DEVCTL=0x%02x\n", temp); 1745 1746 /* disable testmode */ 1747 1748 MUSB2_WRITE_1(sc, MUSB2_REG_TESTMODE, 0); 1749 1750 /* set default value */ 1751 1752 MUSB2_WRITE_1(sc, MUSB2_REG_MISC, 0); 1753 1754 /* select endpoint index 0 */ 1755 1756 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); 1757 1758 /* read out number of endpoints */ 1759 1760 nrx = 1761 (MUSB2_READ_1(sc, MUSB2_REG_EPINFO) / 16); 1762 1763 ntx = 1764 (MUSB2_READ_1(sc, MUSB2_REG_EPINFO) % 16); 1765 1766 /* these numbers exclude the control endpoint */ 1767 1768 DPRINTFN(2, "RX/TX endpoints: %u/%u\n", nrx, ntx); 1769 1770 sc->sc_ep_max = (nrx > ntx) ? nrx : ntx; 1771 if (sc->sc_ep_max == 0) { 1772 DPRINTFN(2, "ERROR: Looks like the clocks are off!\n"); 1773 } 1774 /* read out configuration data */ 1775 1776 sc->sc_conf_data = MUSB2_READ_1(sc, MUSB2_REG_CONFDATA); 1777 1778 DPRINTFN(2, "Config Data: 0x%02x\n", 1779 sc->sc_conf_data); 1780 1781 dynfifo = (sc->sc_conf_data & MUSB2_MASK_CD_DYNFIFOSZ) ? 1 : 0; 1782 1783 if (dynfifo) { 1784 device_printf(sc->sc_bus.bdev, "Dynamic FIFO sizing detected, " 1785 "assuming 16Kbytes of FIFO RAM\n"); 1786 } 1787 1788 DPRINTFN(2, "HW version: 0x%04x\n", 1789 MUSB2_READ_1(sc, MUSB2_REG_HWVERS)); 1790 1791 /* initialise endpoint profiles */ 1792 1793 offset = 0; 1794 1795 for (temp = 1; temp <= sc->sc_ep_max; temp++) { 1796 pf = sc->sc_hw_ep_profile + temp; 1797 1798 /* select endpoint */ 1799 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, temp); 1800 1801 fsize = MUSB2_READ_1(sc, MUSB2_REG_FSIZE); 1802 frx = (fsize & MUSB2_MASK_RX_FSIZE) / 16; 1803 ftx = (fsize & MUSB2_MASK_TX_FSIZE); 1804 1805 DPRINTF("Endpoint %u FIFO size: IN=%u, OUT=%u, DYN=%d\n", 1806 temp, ftx, frx, dynfifo); 1807 1808 if (dynfifo) { 1809 if (frx && (temp <= nrx)) { 1810 if (temp < 8) { 1811 frx = 10; /* 1K */ 1812 MUSB2_WRITE_1(sc, MUSB2_REG_RXFIFOSZ, 1813 MUSB2_VAL_FIFOSZ_512 | 1814 MUSB2_MASK_FIFODB); 1815 } else { 1816 frx = 7; /* 128 bytes */ 1817 MUSB2_WRITE_1(sc, MUSB2_REG_RXFIFOSZ, 1818 MUSB2_VAL_FIFOSZ_128); 1819 } 1820 1821 MUSB2_WRITE_2(sc, MUSB2_REG_RXFIFOADD, 1822 offset >> 3); 1823 1824 offset += (1 << frx); 1825 } 1826 if (ftx && (temp <= ntx)) { 1827 if (temp < 8) { 1828 ftx = 10; /* 1K */ 1829 MUSB2_WRITE_1(sc, MUSB2_REG_TXFIFOSZ, 1830 MUSB2_VAL_FIFOSZ_512 | 1831 MUSB2_MASK_FIFODB); 1832 } else { 1833 ftx = 7; /* 128 bytes */ 1834 MUSB2_WRITE_1(sc, MUSB2_REG_TXFIFOSZ, 1835 MUSB2_VAL_FIFOSZ_128); 1836 } 1837 1838 MUSB2_WRITE_2(sc, MUSB2_REG_TXFIFOADD, 1839 offset >> 3); 1840 1841 offset += (1 << ftx); 1842 } 1843 } 1844 1845 if (frx && ftx && (temp <= nrx) && (temp <= ntx)) { 1846 pf->max_in_frame_size = 1 << ftx; 1847 pf->max_out_frame_size = 1 << frx; 1848 pf->is_simplex = 0; /* duplex */ 1849 pf->support_multi_buffer = 1; 1850 pf->support_bulk = 1; 1851 pf->support_interrupt = 1; 1852 pf->support_isochronous = 1; 1853 pf->support_in = 1; 1854 pf->support_out = 1; 1855 } else if (frx && (temp <= nrx)) { 1856 pf->max_out_frame_size = 1 << frx; 1857 pf->is_simplex = 1; /* simplex */ 1858 pf->support_multi_buffer = 1; 1859 pf->support_bulk = 1; 1860 pf->support_interrupt = 1; 1861 pf->support_isochronous = 1; 1862 pf->support_out = 1; 1863 } else if (ftx && (temp <= ntx)) { 1864 pf->max_in_frame_size = 1 << ftx; 1865 pf->is_simplex = 1; /* simplex */ 1866 pf->support_multi_buffer = 1; 1867 pf->support_bulk = 1; 1868 pf->support_interrupt = 1; 1869 pf->support_isochronous = 1; 1870 pf->support_in = 1; 1871 } 1872 } 1873 1874 DPRINTFN(2, "Dynamic FIFO size = %d bytes\n", offset); 1875 1876 /* turn on default interrupts */ 1877 1878 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, 1879 MUSB2_MASK_IRESET); 1880 1881 musbotg_clocks_off(sc); 1882 1883 USB_BUS_UNLOCK(&sc->sc_bus); 1884 1885 /* catch any lost interrupts */ 1886 1887 musbotg_do_poll(&sc->sc_bus); 1888 1889 return (0); /* success */ 1890} 1891 1892void 1893musbotg_uninit(struct musbotg_softc *sc) 1894{ 1895 USB_BUS_LOCK(&sc->sc_bus); 1896 1897 /* disable all interrupts */ 1898 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, 0); 1899 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, 0); 1900 MUSB2_WRITE_2(sc, MUSB2_REG_INTRXE, 0); 1901 1902 sc->sc_flags.port_powered = 0; 1903 sc->sc_flags.status_vbus = 0; 1904 sc->sc_flags.status_bus_reset = 0; 1905 sc->sc_flags.status_suspend = 0; 1906 sc->sc_flags.change_suspend = 0; 1907 sc->sc_flags.change_connect = 1; 1908 1909 musbotg_pull_down(sc); 1910 musbotg_clocks_off(sc); 1911 USB_BUS_UNLOCK(&sc->sc_bus); 1912} 1913 1914void 1915musbotg_suspend(struct musbotg_softc *sc) 1916{ 1917 return; 1918} 1919 1920void 1921musbotg_resume(struct musbotg_softc *sc) 1922{ 1923 return; 1924} 1925 1926static void 1927musbotg_do_poll(struct usb_bus *bus) 1928{ 1929 struct musbotg_softc *sc = MUSBOTG_BUS2SC(bus); 1930 1931 USB_BUS_LOCK(&sc->sc_bus); 1932 musbotg_interrupt_poll(sc); 1933 USB_BUS_UNLOCK(&sc->sc_bus); 1934} 1935 1936/*------------------------------------------------------------------------* 1937 * musbotg bulk support 1938 *------------------------------------------------------------------------*/ 1939static void 1940musbotg_device_bulk_open(struct usb_xfer *xfer) 1941{ 1942 return; 1943} 1944 1945static void 1946musbotg_device_bulk_close(struct usb_xfer *xfer) 1947{ 1948 musbotg_device_done(xfer, USB_ERR_CANCELLED); 1949} 1950 1951static void 1952musbotg_device_bulk_enter(struct usb_xfer *xfer) 1953{ 1954 return; 1955} 1956 1957static void 1958musbotg_device_bulk_start(struct usb_xfer *xfer) 1959{ 1960 /* setup TDs */ 1961 musbotg_setup_standard_chain(xfer); 1962 musbotg_start_standard_chain(xfer); 1963} 1964 1965struct usb_pipe_methods musbotg_device_bulk_methods = 1966{ 1967 .open = musbotg_device_bulk_open, 1968 .close = musbotg_device_bulk_close, 1969 .enter = musbotg_device_bulk_enter, 1970 .start = musbotg_device_bulk_start, 1971}; 1972 1973/*------------------------------------------------------------------------* 1974 * musbotg control support 1975 *------------------------------------------------------------------------*/ 1976static void 1977musbotg_device_ctrl_open(struct usb_xfer *xfer) 1978{ 1979 return; 1980} 1981 1982static void 1983musbotg_device_ctrl_close(struct usb_xfer *xfer) 1984{ 1985 musbotg_device_done(xfer, USB_ERR_CANCELLED); 1986} 1987 1988static void 1989musbotg_device_ctrl_enter(struct usb_xfer *xfer) 1990{ 1991 return; 1992} 1993 1994static void 1995musbotg_device_ctrl_start(struct usb_xfer *xfer) 1996{ 1997 /* setup TDs */ 1998 musbotg_setup_standard_chain(xfer); 1999 musbotg_start_standard_chain(xfer); 2000} 2001 2002struct usb_pipe_methods musbotg_device_ctrl_methods = 2003{ 2004 .open = musbotg_device_ctrl_open, 2005 .close = musbotg_device_ctrl_close, 2006 .enter = musbotg_device_ctrl_enter, 2007 .start = musbotg_device_ctrl_start, 2008}; 2009 2010/*------------------------------------------------------------------------* 2011 * musbotg interrupt support 2012 *------------------------------------------------------------------------*/ 2013static void 2014musbotg_device_intr_open(struct usb_xfer *xfer) 2015{ 2016 return; 2017} 2018 2019static void 2020musbotg_device_intr_close(struct usb_xfer *xfer) 2021{ 2022 musbotg_device_done(xfer, USB_ERR_CANCELLED); 2023} 2024 2025static void 2026musbotg_device_intr_enter(struct usb_xfer *xfer) 2027{ 2028 return; 2029} 2030 2031static void 2032musbotg_device_intr_start(struct usb_xfer *xfer) 2033{ 2034 /* setup TDs */ 2035 musbotg_setup_standard_chain(xfer); 2036 musbotg_start_standard_chain(xfer); 2037} 2038 2039struct usb_pipe_methods musbotg_device_intr_methods = 2040{ 2041 .open = musbotg_device_intr_open, 2042 .close = musbotg_device_intr_close, 2043 .enter = musbotg_device_intr_enter, 2044 .start = musbotg_device_intr_start, 2045}; 2046 2047/*------------------------------------------------------------------------* 2048 * musbotg full speed isochronous support 2049 *------------------------------------------------------------------------*/ 2050static void 2051musbotg_device_isoc_open(struct usb_xfer *xfer) 2052{ 2053 return; 2054} 2055 2056static void 2057musbotg_device_isoc_close(struct usb_xfer *xfer) 2058{ 2059 musbotg_device_done(xfer, USB_ERR_CANCELLED); 2060} 2061 2062static void 2063musbotg_device_isoc_enter(struct usb_xfer *xfer) 2064{ 2065 struct musbotg_softc *sc = MUSBOTG_BUS2SC(xfer->xroot->bus); 2066 uint32_t temp; 2067 uint32_t nframes; 2068 uint32_t fs_frames; 2069 2070 DPRINTFN(5, "xfer=%p next=%d nframes=%d\n", 2071 xfer, xfer->endpoint->isoc_next, xfer->nframes); 2072 2073 /* get the current frame index */ 2074 2075 nframes = MUSB2_READ_2(sc, MUSB2_REG_FRAME); 2076 2077 /* 2078 * check if the frame index is within the window where the frames 2079 * will be inserted 2080 */ 2081 temp = (nframes - xfer->endpoint->isoc_next) & MUSB2_MASK_FRAME; 2082 2083 if (usbd_get_speed(xfer->xroot->udev) == USB_SPEED_HIGH) { 2084 fs_frames = (xfer->nframes + 7) / 8; 2085 } else { 2086 fs_frames = xfer->nframes; 2087 } 2088 2089 if ((xfer->endpoint->is_synced == 0) || 2090 (temp < fs_frames)) { 2091 /* 2092 * If there is data underflow or the pipe queue is 2093 * empty we schedule the transfer a few frames ahead 2094 * of the current frame position. Else two isochronous 2095 * transfers might overlap. 2096 */ 2097 xfer->endpoint->isoc_next = (nframes + 3) & MUSB2_MASK_FRAME; 2098 xfer->endpoint->is_synced = 1; 2099 DPRINTFN(2, "start next=%d\n", xfer->endpoint->isoc_next); 2100 } 2101 /* 2102 * compute how many milliseconds the insertion is ahead of the 2103 * current frame position: 2104 */ 2105 temp = (xfer->endpoint->isoc_next - nframes) & MUSB2_MASK_FRAME; 2106 2107 /* 2108 * pre-compute when the isochronous transfer will be finished: 2109 */ 2110 xfer->isoc_time_complete = 2111 usb_isoc_time_expand(&sc->sc_bus, nframes) + temp + 2112 fs_frames; 2113 2114 /* compute frame number for next insertion */ 2115 xfer->endpoint->isoc_next += fs_frames; 2116 2117 /* setup TDs */ 2118 musbotg_setup_standard_chain(xfer); 2119} 2120 2121static void 2122musbotg_device_isoc_start(struct usb_xfer *xfer) 2123{ 2124 /* start TD chain */ 2125 musbotg_start_standard_chain(xfer); 2126} 2127 2128struct usb_pipe_methods musbotg_device_isoc_methods = 2129{ 2130 .open = musbotg_device_isoc_open, 2131 .close = musbotg_device_isoc_close, 2132 .enter = musbotg_device_isoc_enter, 2133 .start = musbotg_device_isoc_start, 2134}; 2135 2136/*------------------------------------------------------------------------* 2137 * musbotg root control support 2138 *------------------------------------------------------------------------* 2139 * Simulate a hardware HUB by handling all the necessary requests. 2140 *------------------------------------------------------------------------*/ 2141 2142static const struct usb_device_descriptor musbotg_devd = { 2143 .bLength = sizeof(struct usb_device_descriptor), 2144 .bDescriptorType = UDESC_DEVICE, 2145 .bcdUSB = {0x00, 0x02}, 2146 .bDeviceClass = UDCLASS_HUB, 2147 .bDeviceSubClass = UDSUBCLASS_HUB, 2148 .bDeviceProtocol = UDPROTO_HSHUBSTT, 2149 .bMaxPacketSize = 64, 2150 .bcdDevice = {0x00, 0x01}, 2151 .iManufacturer = 1, 2152 .iProduct = 2, 2153 .bNumConfigurations = 1, 2154}; 2155 2156static const struct usb_device_qualifier musbotg_odevd = { 2157 .bLength = sizeof(struct usb_device_qualifier), 2158 .bDescriptorType = UDESC_DEVICE_QUALIFIER, 2159 .bcdUSB = {0x00, 0x02}, 2160 .bDeviceClass = UDCLASS_HUB, 2161 .bDeviceSubClass = UDSUBCLASS_HUB, 2162 .bDeviceProtocol = UDPROTO_FSHUB, 2163 .bMaxPacketSize0 = 0, 2164 .bNumConfigurations = 0, 2165}; 2166 2167static const struct musbotg_config_desc musbotg_confd = { 2168 .confd = { 2169 .bLength = sizeof(struct usb_config_descriptor), 2170 .bDescriptorType = UDESC_CONFIG, 2171 .wTotalLength[0] = sizeof(musbotg_confd), 2172 .bNumInterface = 1, 2173 .bConfigurationValue = 1, 2174 .iConfiguration = 0, 2175 .bmAttributes = UC_SELF_POWERED, 2176 .bMaxPower = 0, 2177 }, 2178 .ifcd = { 2179 .bLength = sizeof(struct usb_interface_descriptor), 2180 .bDescriptorType = UDESC_INTERFACE, 2181 .bNumEndpoints = 1, 2182 .bInterfaceClass = UICLASS_HUB, 2183 .bInterfaceSubClass = UISUBCLASS_HUB, 2184 .bInterfaceProtocol = UIPROTO_HSHUBSTT, 2185 }, 2186 .endpd = { 2187 .bLength = sizeof(struct usb_endpoint_descriptor), 2188 .bDescriptorType = UDESC_ENDPOINT, 2189 .bEndpointAddress = (UE_DIR_IN | MUSBOTG_INTR_ENDPT), 2190 .bmAttributes = UE_INTERRUPT, 2191 .wMaxPacketSize[0] = 8, 2192 .bInterval = 255, 2193 }, 2194}; 2195 2196static const struct usb_hub_descriptor_min musbotg_hubd = { 2197 .bDescLength = sizeof(musbotg_hubd), 2198 .bDescriptorType = UDESC_HUB, 2199 .bNbrPorts = 1, 2200 .wHubCharacteristics[0] = 2201 (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL) & 0xFF, 2202 .wHubCharacteristics[1] = 2203 (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL) >> 16, 2204 .bPwrOn2PwrGood = 50, 2205 .bHubContrCurrent = 0, 2206 .DeviceRemovable = {0}, /* port is removable */ 2207}; 2208 2209#define STRING_LANG \ 2210 0x09, 0x04, /* American English */ 2211 2212#define STRING_VENDOR \ 2213 'M', 0, 'e', 0, 'n', 0, 't', 0, 'o', 0, 'r', 0, ' ', 0, \ 2214 'G', 0, 'r', 0, 'a', 0, 'p', 0, 'h', 0, 'i', 0, 'c', 0, 's', 0 2215 2216#define STRING_PRODUCT \ 2217 'O', 0, 'T', 0, 'G', 0, ' ', 0, 'R', 0, \ 2218 'o', 0, 'o', 0, 't', 0, ' ', 0, 'H', 0, \ 2219 'U', 0, 'B', 0, 2220 2221USB_MAKE_STRING_DESC(STRING_LANG, musbotg_langtab); 2222USB_MAKE_STRING_DESC(STRING_VENDOR, musbotg_vendor); 2223USB_MAKE_STRING_DESC(STRING_PRODUCT, musbotg_product); 2224 2225static usb_error_t 2226musbotg_roothub_exec(struct usb_device *udev, 2227 struct usb_device_request *req, const void **pptr, uint16_t *plength) 2228{ 2229 struct musbotg_softc *sc = MUSBOTG_BUS2SC(udev->bus); 2230 const void *ptr; 2231 uint16_t len; 2232 uint16_t value; 2233 uint16_t index; 2234 usb_error_t err; 2235 2236 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2237 2238 /* buffer reset */ 2239 ptr = (const void *)&sc->sc_hub_temp; 2240 len = 0; 2241 err = 0; 2242 2243 value = UGETW(req->wValue); 2244 index = UGETW(req->wIndex); 2245 2246 /* demultiplex the control request */ 2247 2248 switch (req->bmRequestType) { 2249 case UT_READ_DEVICE: 2250 switch (req->bRequest) { 2251 case UR_GET_DESCRIPTOR: 2252 goto tr_handle_get_descriptor; 2253 case UR_GET_CONFIG: 2254 goto tr_handle_get_config; 2255 case UR_GET_STATUS: 2256 goto tr_handle_get_status; 2257 default: 2258 goto tr_stalled; 2259 } 2260 break; 2261 2262 case UT_WRITE_DEVICE: 2263 switch (req->bRequest) { 2264 case UR_SET_ADDRESS: 2265 goto tr_handle_set_address; 2266 case UR_SET_CONFIG: 2267 goto tr_handle_set_config; 2268 case UR_CLEAR_FEATURE: 2269 goto tr_valid; /* nop */ 2270 case UR_SET_DESCRIPTOR: 2271 goto tr_valid; /* nop */ 2272 case UR_SET_FEATURE: 2273 default: 2274 goto tr_stalled; 2275 } 2276 break; 2277 2278 case UT_WRITE_ENDPOINT: 2279 switch (req->bRequest) { 2280 case UR_CLEAR_FEATURE: 2281 switch (UGETW(req->wValue)) { 2282 case UF_ENDPOINT_HALT: 2283 goto tr_handle_clear_halt; 2284 case UF_DEVICE_REMOTE_WAKEUP: 2285 goto tr_handle_clear_wakeup; 2286 default: 2287 goto tr_stalled; 2288 } 2289 break; 2290 case UR_SET_FEATURE: 2291 switch (UGETW(req->wValue)) { 2292 case UF_ENDPOINT_HALT: 2293 goto tr_handle_set_halt; 2294 case UF_DEVICE_REMOTE_WAKEUP: 2295 goto tr_handle_set_wakeup; 2296 default: 2297 goto tr_stalled; 2298 } 2299 break; 2300 case UR_SYNCH_FRAME: 2301 goto tr_valid; /* nop */ 2302 default: 2303 goto tr_stalled; 2304 } 2305 break; 2306 2307 case UT_READ_ENDPOINT: 2308 switch (req->bRequest) { 2309 case UR_GET_STATUS: 2310 goto tr_handle_get_ep_status; 2311 default: 2312 goto tr_stalled; 2313 } 2314 break; 2315 2316 case UT_WRITE_INTERFACE: 2317 switch (req->bRequest) { 2318 case UR_SET_INTERFACE: 2319 goto tr_handle_set_interface; 2320 case UR_CLEAR_FEATURE: 2321 goto tr_valid; /* nop */ 2322 case UR_SET_FEATURE: 2323 default: 2324 goto tr_stalled; 2325 } 2326 break; 2327 2328 case UT_READ_INTERFACE: 2329 switch (req->bRequest) { 2330 case UR_GET_INTERFACE: 2331 goto tr_handle_get_interface; 2332 case UR_GET_STATUS: 2333 goto tr_handle_get_iface_status; 2334 default: 2335 goto tr_stalled; 2336 } 2337 break; 2338 2339 case UT_WRITE_CLASS_INTERFACE: 2340 case UT_WRITE_VENDOR_INTERFACE: 2341 /* XXX forward */ 2342 break; 2343 2344 case UT_READ_CLASS_INTERFACE: 2345 case UT_READ_VENDOR_INTERFACE: 2346 /* XXX forward */ 2347 break; 2348 2349 case UT_WRITE_CLASS_DEVICE: 2350 switch (req->bRequest) { 2351 case UR_CLEAR_FEATURE: 2352 goto tr_valid; 2353 case UR_SET_DESCRIPTOR: 2354 case UR_SET_FEATURE: 2355 break; 2356 default: 2357 goto tr_stalled; 2358 } 2359 break; 2360 2361 case UT_WRITE_CLASS_OTHER: 2362 switch (req->bRequest) { 2363 case UR_CLEAR_FEATURE: 2364 goto tr_handle_clear_port_feature; 2365 case UR_SET_FEATURE: 2366 goto tr_handle_set_port_feature; 2367 case UR_CLEAR_TT_BUFFER: 2368 case UR_RESET_TT: 2369 case UR_STOP_TT: 2370 goto tr_valid; 2371 2372 default: 2373 goto tr_stalled; 2374 } 2375 break; 2376 2377 case UT_READ_CLASS_OTHER: 2378 switch (req->bRequest) { 2379 case UR_GET_TT_STATE: 2380 goto tr_handle_get_tt_state; 2381 case UR_GET_STATUS: 2382 goto tr_handle_get_port_status; 2383 default: 2384 goto tr_stalled; 2385 } 2386 break; 2387 2388 case UT_READ_CLASS_DEVICE: 2389 switch (req->bRequest) { 2390 case UR_GET_DESCRIPTOR: 2391 goto tr_handle_get_class_descriptor; 2392 case UR_GET_STATUS: 2393 goto tr_handle_get_class_status; 2394 2395 default: 2396 goto tr_stalled; 2397 } 2398 break; 2399 default: 2400 goto tr_stalled; 2401 } 2402 goto tr_valid; 2403 2404tr_handle_get_descriptor: 2405 switch (value >> 8) { 2406 case UDESC_DEVICE: 2407 if (value & 0xff) { 2408 goto tr_stalled; 2409 } 2410 len = sizeof(musbotg_devd); 2411 ptr = (const void *)&musbotg_devd; 2412 goto tr_valid; 2413 case UDESC_CONFIG: 2414 if (value & 0xff) { 2415 goto tr_stalled; 2416 } 2417 len = sizeof(musbotg_confd); 2418 ptr = (const void *)&musbotg_confd; 2419 goto tr_valid; 2420 case UDESC_STRING: 2421 switch (value & 0xff) { 2422 case 0: /* Language table */ 2423 len = sizeof(musbotg_langtab); 2424 ptr = (const void *)&musbotg_langtab; 2425 goto tr_valid; 2426 2427 case 1: /* Vendor */ 2428 len = sizeof(musbotg_vendor); 2429 ptr = (const void *)&musbotg_vendor; 2430 goto tr_valid; 2431 2432 case 2: /* Product */ 2433 len = sizeof(musbotg_product); 2434 ptr = (const void *)&musbotg_product; 2435 goto tr_valid; 2436 default: 2437 break; 2438 } 2439 break; 2440 default: 2441 goto tr_stalled; 2442 } 2443 goto tr_stalled; 2444 2445tr_handle_get_config: 2446 len = 1; 2447 sc->sc_hub_temp.wValue[0] = sc->sc_conf; 2448 goto tr_valid; 2449 2450tr_handle_get_status: 2451 len = 2; 2452 USETW(sc->sc_hub_temp.wValue, UDS_SELF_POWERED); 2453 goto tr_valid; 2454 2455tr_handle_set_address: 2456 if (value & 0xFF00) { 2457 goto tr_stalled; 2458 } 2459 sc->sc_rt_addr = value; 2460 goto tr_valid; 2461 2462tr_handle_set_config: 2463 if (value >= 2) { 2464 goto tr_stalled; 2465 } 2466 sc->sc_conf = value; 2467 goto tr_valid; 2468 2469tr_handle_get_interface: 2470 len = 1; 2471 sc->sc_hub_temp.wValue[0] = 0; 2472 goto tr_valid; 2473 2474tr_handle_get_tt_state: 2475tr_handle_get_class_status: 2476tr_handle_get_iface_status: 2477tr_handle_get_ep_status: 2478 len = 2; 2479 USETW(sc->sc_hub_temp.wValue, 0); 2480 goto tr_valid; 2481 2482tr_handle_set_halt: 2483tr_handle_set_interface: 2484tr_handle_set_wakeup: 2485tr_handle_clear_wakeup: 2486tr_handle_clear_halt: 2487 goto tr_valid; 2488 2489tr_handle_clear_port_feature: 2490 if (index != 1) { 2491 goto tr_stalled; 2492 } 2493 DPRINTFN(8, "UR_CLEAR_PORT_FEATURE on port %d\n", index); 2494 2495 switch (value) { 2496 case UHF_PORT_SUSPEND: 2497 musbotg_wakeup_peer(sc); 2498 break; 2499 2500 case UHF_PORT_ENABLE: 2501 sc->sc_flags.port_enabled = 0; 2502 break; 2503 2504 case UHF_PORT_TEST: 2505 case UHF_PORT_INDICATOR: 2506 case UHF_C_PORT_ENABLE: 2507 case UHF_C_PORT_OVER_CURRENT: 2508 case UHF_C_PORT_RESET: 2509 /* nops */ 2510 break; 2511 case UHF_PORT_POWER: 2512 sc->sc_flags.port_powered = 0; 2513 musbotg_pull_down(sc); 2514 musbotg_clocks_off(sc); 2515 break; 2516 case UHF_C_PORT_CONNECTION: 2517 sc->sc_flags.change_connect = 0; 2518 break; 2519 case UHF_C_PORT_SUSPEND: 2520 sc->sc_flags.change_suspend = 0; 2521 break; 2522 default: 2523 err = USB_ERR_IOERROR; 2524 goto done; 2525 } 2526 goto tr_valid; 2527 2528tr_handle_set_port_feature: 2529 if (index != 1) { 2530 goto tr_stalled; 2531 } 2532 DPRINTFN(8, "UR_SET_PORT_FEATURE\n"); 2533 2534 switch (value) { 2535 case UHF_PORT_ENABLE: 2536 sc->sc_flags.port_enabled = 1; 2537 break; 2538 case UHF_PORT_SUSPEND: 2539 case UHF_PORT_RESET: 2540 case UHF_PORT_TEST: 2541 case UHF_PORT_INDICATOR: 2542 /* nops */ 2543 break; 2544 case UHF_PORT_POWER: 2545 sc->sc_flags.port_powered = 1; 2546 break; 2547 default: 2548 err = USB_ERR_IOERROR; 2549 goto done; 2550 } 2551 goto tr_valid; 2552 2553tr_handle_get_port_status: 2554 2555 DPRINTFN(8, "UR_GET_PORT_STATUS\n"); 2556 2557 if (index != 1) { 2558 goto tr_stalled; 2559 } 2560 if (sc->sc_flags.status_vbus) { 2561 musbotg_clocks_on(sc); 2562 musbotg_pull_up(sc); 2563 } else { 2564 musbotg_pull_down(sc); 2565 musbotg_clocks_off(sc); 2566 } 2567 2568 /* Select Device Side Mode */ 2569 value = UPS_PORT_MODE_DEVICE; 2570 2571 if (sc->sc_flags.status_high_speed) { 2572 value |= UPS_HIGH_SPEED; 2573 } 2574 if (sc->sc_flags.port_powered) { 2575 value |= UPS_PORT_POWER; 2576 } 2577 if (sc->sc_flags.port_enabled) { 2578 value |= UPS_PORT_ENABLED; 2579 } 2580 if (sc->sc_flags.status_vbus && 2581 sc->sc_flags.status_bus_reset) { 2582 value |= UPS_CURRENT_CONNECT_STATUS; 2583 } 2584 if (sc->sc_flags.status_suspend) { 2585 value |= UPS_SUSPEND; 2586 } 2587 USETW(sc->sc_hub_temp.ps.wPortStatus, value); 2588 2589 value = 0; 2590 2591 if (sc->sc_flags.change_connect) { 2592 value |= UPS_C_CONNECT_STATUS; 2593 2594 if (sc->sc_flags.status_vbus && 2595 sc->sc_flags.status_bus_reset) { 2596 /* reset EP0 state */ 2597 sc->sc_ep0_busy = 0; 2598 sc->sc_ep0_cmd = 0; 2599 } 2600 } 2601 if (sc->sc_flags.change_suspend) { 2602 value |= UPS_C_SUSPEND; 2603 } 2604 USETW(sc->sc_hub_temp.ps.wPortChange, value); 2605 len = sizeof(sc->sc_hub_temp.ps); 2606 goto tr_valid; 2607 2608tr_handle_get_class_descriptor: 2609 if (value & 0xFF) { 2610 goto tr_stalled; 2611 } 2612 ptr = (const void *)&musbotg_hubd; 2613 len = sizeof(musbotg_hubd); 2614 goto tr_valid; 2615 2616tr_stalled: 2617 err = USB_ERR_STALLED; 2618tr_valid: 2619done: 2620 *plength = len; 2621 *pptr = ptr; 2622 return (err); 2623} 2624 2625static void 2626musbotg_xfer_setup(struct usb_setup_params *parm) 2627{ 2628 const struct usb_hw_ep_profile *pf; 2629 struct musbotg_softc *sc; 2630 struct usb_xfer *xfer; 2631 void *last_obj; 2632 uint32_t ntd; 2633 uint32_t n; 2634 uint8_t ep_no; 2635 2636 sc = MUSBOTG_BUS2SC(parm->udev->bus); 2637 xfer = parm->curr_xfer; 2638 2639 /* 2640 * NOTE: This driver does not use any of the parameters that 2641 * are computed from the following values. Just set some 2642 * reasonable dummies: 2643 */ 2644 parm->hc_max_packet_size = 0x400; 2645 parm->hc_max_frame_size = 0x400; 2646 2647 if ((parm->methods == &musbotg_device_isoc_methods) || 2648 (parm->methods == &musbotg_device_intr_methods)) 2649 parm->hc_max_packet_count = 3; 2650 else 2651 parm->hc_max_packet_count = 1; 2652 2653 usbd_transfer_setup_sub(parm); 2654 2655 /* 2656 * compute maximum number of TDs 2657 */ 2658 if (parm->methods == &musbotg_device_ctrl_methods) { 2659 2660 ntd = xfer->nframes + 1 /* STATUS */ + 1 /* SYNC */ ; 2661 2662 } else if (parm->methods == &musbotg_device_bulk_methods) { 2663 2664 ntd = xfer->nframes + 1 /* SYNC */ ; 2665 2666 } else if (parm->methods == &musbotg_device_intr_methods) { 2667 2668 ntd = xfer->nframes + 1 /* SYNC */ ; 2669 2670 } else if (parm->methods == &musbotg_device_isoc_methods) { 2671 2672 ntd = xfer->nframes + 1 /* SYNC */ ; 2673 2674 } else { 2675 2676 ntd = 0; 2677 } 2678 2679 /* 2680 * check if "usbd_transfer_setup_sub" set an error 2681 */ 2682 if (parm->err) { 2683 return; 2684 } 2685 /* 2686 * allocate transfer descriptors 2687 */ 2688 last_obj = NULL; 2689 2690 /* 2691 * get profile stuff 2692 */ 2693 if (ntd) { 2694 2695 ep_no = xfer->endpointno & UE_ADDR; 2696 musbotg_get_hw_ep_profile(parm->udev, &pf, ep_no); 2697 2698 if (pf == NULL) { 2699 /* should not happen */ 2700 parm->err = USB_ERR_INVAL; 2701 return; 2702 } 2703 } else { 2704 ep_no = 0; 2705 pf = NULL; 2706 } 2707 2708 /* align data */ 2709 parm->size[0] += ((-parm->size[0]) & (USB_HOST_ALIGN - 1)); 2710 2711 for (n = 0; n != ntd; n++) { 2712 2713 struct musbotg_td *td; 2714 2715 if (parm->buf) { 2716 2717 td = USB_ADD_BYTES(parm->buf, parm->size[0]); 2718 2719 /* init TD */ 2720 td->max_frame_size = xfer->max_frame_size; 2721 td->ep_no = ep_no; 2722 td->obj_next = last_obj; 2723 2724 last_obj = td; 2725 } 2726 parm->size[0] += sizeof(*td); 2727 } 2728 2729 xfer->td_start[0] = last_obj; 2730} 2731 2732static void 2733musbotg_xfer_unsetup(struct usb_xfer *xfer) 2734{ 2735 return; 2736} 2737 2738static void 2739musbotg_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc, 2740 struct usb_endpoint *ep) 2741{ 2742 struct musbotg_softc *sc = MUSBOTG_BUS2SC(udev->bus); 2743 2744 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d (%d)\n", 2745 ep, udev->address, 2746 edesc->bEndpointAddress, udev->flags.usb_mode, 2747 sc->sc_rt_addr); 2748 2749 if (udev->device_index != sc->sc_rt_addr) { 2750 2751 if (udev->flags.usb_mode != USB_MODE_DEVICE) { 2752 /* not supported */ 2753 return; 2754 } 2755 if ((udev->speed != USB_SPEED_FULL) && 2756 (udev->speed != USB_SPEED_HIGH)) { 2757 /* not supported */ 2758 return; 2759 } 2760 switch (edesc->bmAttributes & UE_XFERTYPE) { 2761 case UE_CONTROL: 2762 ep->methods = &musbotg_device_ctrl_methods; 2763 break; 2764 case UE_INTERRUPT: 2765 ep->methods = &musbotg_device_intr_methods; 2766 break; 2767 case UE_ISOCHRONOUS: 2768 ep->methods = &musbotg_device_isoc_methods; 2769 break; 2770 case UE_BULK: 2771 ep->methods = &musbotg_device_bulk_methods; 2772 break; 2773 default: 2774 /* do nothing */ 2775 break; 2776 } 2777 } 2778} 2779 2780struct usb_bus_methods musbotg_bus_methods = 2781{ 2782 .endpoint_init = &musbotg_ep_init, 2783 .xfer_setup = &musbotg_xfer_setup, 2784 .xfer_unsetup = &musbotg_xfer_unsetup, 2785 .get_hw_ep_profile = &musbotg_get_hw_ep_profile, 2786 .set_stall = &musbotg_set_stall, 2787 .clear_stall = &musbotg_clear_stall, 2788 .roothub_exec = &musbotg_roothub_exec, 2789 .xfer_poll = &musbotg_do_poll, 2790}; 2791