musb_otg.c revision 192552
1/* $FreeBSD: head/sys/dev/usb/controller/musb_otg.c 192552 2009-05-21 17:39:21Z thompsa $ */ 2/*- 3 * Copyright (c) 2008 Hans Petter Selasky. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27/* 28 * Thanks to Mentor Graphics for providing a reference driver for this USB chip 29 * at their homepage. 30 */ 31 32/* 33 * This file contains the driver for the Mentor Graphics Inventra USB 34 * 2.0 High Speed Dual-Role controller. 35 * 36 * NOTE: The current implementation only supports Device Side Mode! 37 */ 38 39#include <dev/usb/usb.h> 40#include <dev/usb/usb_mfunc.h> 41#include <dev/usb/usb_error.h> 42 43#define USB_DEBUG_VAR musbotgdebug 44 45#include <dev/usb/usb_core.h> 46#include <dev/usb/usb_debug.h> 47#include <dev/usb/usb_busdma.h> 48#include <dev/usb/usb_process.h> 49#include <dev/usb/usb_transfer.h> 50#include <dev/usb/usb_device.h> 51#include <dev/usb/usb_hub.h> 52#include <dev/usb/usb_util.h> 53 54#include <dev/usb/usb_controller.h> 55#include <dev/usb/usb_bus.h> 56#include <dev/usb/controller/musb_otg.h> 57 58#define MUSBOTG_INTR_ENDPT 1 59 60#define MUSBOTG_BUS2SC(bus) \ 61 ((struct musbotg_softc *)(((uint8_t *)(bus)) - \ 62 USB_P2U(&(((struct musbotg_softc *)0)->sc_bus)))) 63 64#define MUSBOTG_PC2SC(pc) \ 65 MUSBOTG_BUS2SC(USB_DMATAG_TO_XROOT((pc)->tag_parent)->bus) 66 67#if USB_DEBUG 68static int musbotgdebug = 0; 69 70SYSCTL_NODE(_hw_usb, OID_AUTO, musbotg, CTLFLAG_RW, 0, "USB musbotg"); 71SYSCTL_INT(_hw_usb_musbotg, OID_AUTO, debug, CTLFLAG_RW, 72 &musbotgdebug, 0, "Debug level"); 73#endif 74 75/* prototypes */ 76 77struct usb2_bus_methods musbotg_bus_methods; 78struct usb2_pipe_methods musbotg_device_bulk_methods; 79struct usb2_pipe_methods musbotg_device_ctrl_methods; 80struct usb2_pipe_methods musbotg_device_intr_methods; 81struct usb2_pipe_methods musbotg_device_isoc_methods; 82 83static musbotg_cmd_t musbotg_setup_rx; 84static musbotg_cmd_t musbotg_setup_data_rx; 85static musbotg_cmd_t musbotg_setup_data_tx; 86static musbotg_cmd_t musbotg_setup_status; 87static musbotg_cmd_t musbotg_data_rx; 88static musbotg_cmd_t musbotg_data_tx; 89static void musbotg_device_done(struct usb2_xfer *, usb2_error_t); 90static void musbotg_do_poll(struct usb2_bus *); 91static void musbotg_standard_done(struct usb2_xfer *); 92static void musbotg_interrupt_poll(struct musbotg_softc *); 93static void musbotg_root_intr(struct musbotg_softc *); 94 95/* 96 * Here is a configuration that the chip supports. 97 */ 98static const struct usb2_hw_ep_profile musbotg_ep_profile[1] = { 99 100 [0] = { 101 .max_in_frame_size = 64,/* fixed */ 102 .max_out_frame_size = 64, /* fixed */ 103 .is_simplex = 1, 104 .support_control = 1, 105 } 106}; 107 108static void 109musbotg_get_hw_ep_profile(struct usb2_device *udev, 110 const struct usb2_hw_ep_profile **ppf, uint8_t ep_addr) 111{ 112 struct musbotg_softc *sc; 113 114 sc = MUSBOTG_BUS2SC(udev->bus); 115 116 if (ep_addr == 0) { 117 /* control endpoint */ 118 *ppf = musbotg_ep_profile; 119 } else if (ep_addr <= sc->sc_ep_max) { 120 /* other endpoints */ 121 *ppf = sc->sc_hw_ep_profile + ep_addr; 122 } else { 123 *ppf = NULL; 124 } 125} 126 127static void 128musbotg_clocks_on(struct musbotg_softc *sc) 129{ 130 if (sc->sc_flags.clocks_off && 131 sc->sc_flags.port_powered) { 132 133 DPRINTFN(4, "\n"); 134 135 if (sc->sc_clocks_on) { 136 (sc->sc_clocks_on) (sc->sc_clocks_arg); 137 } 138 sc->sc_flags.clocks_off = 0; 139 140 /* XXX enable Transceiver */ 141 } 142} 143 144static void 145musbotg_clocks_off(struct musbotg_softc *sc) 146{ 147 if (!sc->sc_flags.clocks_off) { 148 149 DPRINTFN(4, "\n"); 150 151 /* XXX disable Transceiver */ 152 153 if (sc->sc_clocks_off) { 154 (sc->sc_clocks_off) (sc->sc_clocks_arg); 155 } 156 sc->sc_flags.clocks_off = 1; 157 } 158} 159 160static void 161musbotg_pull_common(struct musbotg_softc *sc, uint8_t on) 162{ 163 uint8_t temp; 164 165 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER); 166 if (on) 167 temp |= MUSB2_MASK_SOFTC; 168 else 169 temp &= ~MUSB2_MASK_SOFTC; 170 171 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp); 172} 173 174static void 175musbotg_pull_up(struct musbotg_softc *sc) 176{ 177 /* pullup D+, if possible */ 178 179 if (!sc->sc_flags.d_pulled_up && 180 sc->sc_flags.port_powered) { 181 sc->sc_flags.d_pulled_up = 1; 182 musbotg_pull_common(sc, 1); 183 } 184} 185 186static void 187musbotg_pull_down(struct musbotg_softc *sc) 188{ 189 /* pulldown D+, if possible */ 190 191 if (sc->sc_flags.d_pulled_up) { 192 sc->sc_flags.d_pulled_up = 0; 193 musbotg_pull_common(sc, 0); 194 } 195} 196 197static void 198musbotg_wakeup_peer(struct musbotg_softc *sc) 199{ 200 uint8_t temp; 201 202 if (!(sc->sc_flags.status_suspend)) { 203 return; 204 } 205 206 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER); 207 temp |= MUSB2_MASK_RESUME; 208 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp); 209 210 /* wait 8 milliseconds */ 211 /* Wait for reset to complete. */ 212 usb2_pause_mtx(&sc->sc_bus.bus_mtx, hz / 125); 213 214 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER); 215 temp &= ~MUSB2_MASK_RESUME; 216 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp); 217} 218 219static void 220musbotg_set_address(struct musbotg_softc *sc, uint8_t addr) 221{ 222 DPRINTFN(4, "addr=%d\n", addr); 223 addr &= 0x7F; 224 MUSB2_WRITE_1(sc, MUSB2_REG_FADDR, addr); 225} 226 227static uint8_t 228musbotg_setup_rx(struct musbotg_td *td) 229{ 230 struct musbotg_softc *sc; 231 struct usb2_device_request req; 232 uint16_t count; 233 uint8_t csr; 234 235 /* get pointer to softc */ 236 sc = MUSBOTG_PC2SC(td->pc); 237 238 /* select endpoint 0 */ 239 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); 240 241 /* read out FIFO status */ 242 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 243 244 DPRINTFN(4, "csr=0x%02x\n", csr); 245 246 /* 247 * NOTE: If DATAEND is set we should not call the 248 * callback, hence the status stage is not complete. 249 */ 250 if (csr & MUSB2_MASK_CSR0L_DATAEND) { 251 /* do not stall at this point */ 252 td->did_stall = 1; 253 /* wait for interrupt */ 254 goto not_complete; 255 } 256 if (csr & MUSB2_MASK_CSR0L_SENTSTALL) { 257 /* clear SENTSTALL */ 258 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0); 259 /* get latest status */ 260 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 261 /* update EP0 state */ 262 sc->sc_ep0_busy = 0; 263 } 264 if (csr & MUSB2_MASK_CSR0L_SETUPEND) { 265 /* clear SETUPEND */ 266 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 267 MUSB2_MASK_CSR0L_SETUPEND_CLR); 268 /* get latest status */ 269 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 270 /* update EP0 state */ 271 sc->sc_ep0_busy = 0; 272 } 273 if (sc->sc_ep0_busy) { 274 goto not_complete; 275 } 276 if (!(csr & MUSB2_MASK_CSR0L_RXPKTRDY)) { 277 goto not_complete; 278 } 279 /* clear did stall flag */ 280 td->did_stall = 0; 281 /* get the packet byte count */ 282 count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT); 283 284 /* verify data length */ 285 if (count != td->remainder) { 286 DPRINTFN(0, "Invalid SETUP packet " 287 "length, %d bytes\n", count); 288 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 289 MUSB2_MASK_CSR0L_RXPKTRDY_CLR); 290 goto not_complete; 291 } 292 if (count != sizeof(req)) { 293 DPRINTFN(0, "Unsupported SETUP packet " 294 "length, %d bytes\n", count); 295 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 296 MUSB2_MASK_CSR0L_RXPKTRDY_CLR); 297 goto not_complete; 298 } 299 /* receive data */ 300 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 301 MUSB2_REG_EPFIFO(0), (void *)&req, sizeof(req)); 302 303 /* copy data into real buffer */ 304 usb2_copy_in(td->pc, 0, &req, sizeof(req)); 305 306 td->offset = sizeof(req); 307 td->remainder = 0; 308 309 /* set pending command */ 310 sc->sc_ep0_cmd = MUSB2_MASK_CSR0L_RXPKTRDY_CLR; 311 312 /* we need set stall or dataend after this */ 313 sc->sc_ep0_busy = 1; 314 315 /* sneak peek the set address */ 316 if ((req.bmRequestType == UT_WRITE_DEVICE) && 317 (req.bRequest == UR_SET_ADDRESS)) { 318 sc->sc_dv_addr = req.wValue[0] & 0x7F; 319 } else { 320 sc->sc_dv_addr = 0xFF; 321 } 322 return (0); /* complete */ 323 324not_complete: 325 /* abort any ongoing transfer */ 326 if (!td->did_stall) { 327 DPRINTFN(4, "stalling\n"); 328 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 329 MUSB2_MASK_CSR0L_SENDSTALL); 330 td->did_stall = 1; 331 } 332 return (1); /* not complete */ 333} 334 335/* Control endpoint only data handling functions (RX/TX/SYNC) */ 336 337static uint8_t 338musbotg_setup_data_rx(struct musbotg_td *td) 339{ 340 struct usb2_page_search buf_res; 341 struct musbotg_softc *sc; 342 uint16_t count; 343 uint8_t csr; 344 uint8_t got_short; 345 346 /* get pointer to softc */ 347 sc = MUSBOTG_PC2SC(td->pc); 348 349 /* select endpoint 0 */ 350 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); 351 352 /* check if a command is pending */ 353 if (sc->sc_ep0_cmd) { 354 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, sc->sc_ep0_cmd); 355 sc->sc_ep0_cmd = 0; 356 } 357 /* read out FIFO status */ 358 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 359 360 DPRINTFN(4, "csr=0x%02x\n", csr); 361 362 got_short = 0; 363 364 if (csr & (MUSB2_MASK_CSR0L_SETUPEND | 365 MUSB2_MASK_CSR0L_SENTSTALL)) { 366 if (td->remainder == 0) { 367 /* 368 * We are actually complete and have 369 * received the next SETUP 370 */ 371 DPRINTFN(4, "faking complete\n"); 372 return (0); /* complete */ 373 } 374 /* 375 * USB Host Aborted the transfer. 376 */ 377 td->error = 1; 378 return (0); /* complete */ 379 } 380 if (!(csr & MUSB2_MASK_CSR0L_RXPKTRDY)) { 381 return (1); /* not complete */ 382 } 383 /* get the packet byte count */ 384 count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT); 385 386 /* verify the packet byte count */ 387 if (count != td->max_frame_size) { 388 if (count < td->max_frame_size) { 389 /* we have a short packet */ 390 td->short_pkt = 1; 391 got_short = 1; 392 } else { 393 /* invalid USB packet */ 394 td->error = 1; 395 return (0); /* we are complete */ 396 } 397 } 398 /* verify the packet byte count */ 399 if (count > td->remainder) { 400 /* invalid USB packet */ 401 td->error = 1; 402 return (0); /* we are complete */ 403 } 404 while (count > 0) { 405 uint32_t temp; 406 407 usb2_get_page(td->pc, td->offset, &buf_res); 408 409 /* get correct length */ 410 if (buf_res.length > count) { 411 buf_res.length = count; 412 } 413 /* check for unaligned memory address */ 414 if (USB_P2U(buf_res.buffer) & 3) { 415 416 temp = count & ~3; 417 418 if (temp) { 419 /* receive data 4 bytes at a time */ 420 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 421 MUSB2_REG_EPFIFO(0), sc->sc_bounce_buf, 422 temp / 4); 423 } 424 temp = count & 3; 425 if (temp) { 426 /* receive data 1 byte at a time */ 427 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 428 MUSB2_REG_EPFIFO(0), 429 (void *)(&sc->sc_bounce_buf[count / 4]), temp); 430 } 431 usb2_copy_in(td->pc, td->offset, 432 sc->sc_bounce_buf, count); 433 434 /* update offset and remainder */ 435 td->offset += count; 436 td->remainder -= count; 437 break; 438 } 439 /* check if we can optimise */ 440 if (buf_res.length >= 4) { 441 442 /* receive data 4 bytes at a time */ 443 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 444 MUSB2_REG_EPFIFO(0), buf_res.buffer, 445 buf_res.length / 4); 446 447 temp = buf_res.length & ~3; 448 449 /* update counters */ 450 count -= temp; 451 td->offset += temp; 452 td->remainder -= temp; 453 continue; 454 } 455 /* receive data */ 456 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 457 MUSB2_REG_EPFIFO(0), buf_res.buffer, buf_res.length); 458 459 /* update counters */ 460 count -= buf_res.length; 461 td->offset += buf_res.length; 462 td->remainder -= buf_res.length; 463 } 464 465 /* check if we are complete */ 466 if ((td->remainder == 0) || got_short) { 467 if (td->short_pkt) { 468 /* we are complete */ 469 sc->sc_ep0_cmd = MUSB2_MASK_CSR0L_RXPKTRDY_CLR; 470 return (0); 471 } 472 /* else need to receive a zero length packet */ 473 } 474 /* write command - need more data */ 475 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 476 MUSB2_MASK_CSR0L_RXPKTRDY_CLR); 477 return (1); /* not complete */ 478} 479 480static uint8_t 481musbotg_setup_data_tx(struct musbotg_td *td) 482{ 483 struct usb2_page_search buf_res; 484 struct musbotg_softc *sc; 485 uint16_t count; 486 uint8_t csr; 487 488 /* get pointer to softc */ 489 sc = MUSBOTG_PC2SC(td->pc); 490 491 /* select endpoint 0 */ 492 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); 493 494 /* check if a command is pending */ 495 if (sc->sc_ep0_cmd) { 496 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, sc->sc_ep0_cmd); 497 sc->sc_ep0_cmd = 0; 498 } 499 /* read out FIFO status */ 500 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 501 502 DPRINTFN(4, "csr=0x%02x\n", csr); 503 504 if (csr & (MUSB2_MASK_CSR0L_SETUPEND | 505 MUSB2_MASK_CSR0L_SENTSTALL)) { 506 /* 507 * The current transfer was aborted 508 * by the USB Host 509 */ 510 td->error = 1; 511 return (0); /* complete */ 512 } 513 if (csr & MUSB2_MASK_CSR0L_TXPKTRDY) { 514 return (1); /* not complete */ 515 } 516 count = td->max_frame_size; 517 if (td->remainder < count) { 518 /* we have a short packet */ 519 td->short_pkt = 1; 520 count = td->remainder; 521 } 522 while (count > 0) { 523 uint32_t temp; 524 525 usb2_get_page(td->pc, td->offset, &buf_res); 526 527 /* get correct length */ 528 if (buf_res.length > count) { 529 buf_res.length = count; 530 } 531 /* check for unaligned memory address */ 532 if (USB_P2U(buf_res.buffer) & 3) { 533 534 usb2_copy_out(td->pc, td->offset, 535 sc->sc_bounce_buf, count); 536 537 temp = count & ~3; 538 539 if (temp) { 540 /* transmit data 4 bytes at a time */ 541 bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 542 MUSB2_REG_EPFIFO(0), sc->sc_bounce_buf, 543 temp / 4); 544 } 545 temp = count & 3; 546 if (temp) { 547 /* receive data 1 byte at a time */ 548 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 549 MUSB2_REG_EPFIFO(0), 550 ((void *)&sc->sc_bounce_buf[count / 4]), temp); 551 } 552 /* update offset and remainder */ 553 td->offset += count; 554 td->remainder -= count; 555 break; 556 } 557 /* check if we can optimise */ 558 if (buf_res.length >= 4) { 559 560 /* transmit data 4 bytes at a time */ 561 bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 562 MUSB2_REG_EPFIFO(0), buf_res.buffer, 563 buf_res.length / 4); 564 565 temp = buf_res.length & ~3; 566 567 /* update counters */ 568 count -= temp; 569 td->offset += temp; 570 td->remainder -= temp; 571 continue; 572 } 573 /* transmit data */ 574 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 575 MUSB2_REG_EPFIFO(0), buf_res.buffer, buf_res.length); 576 577 /* update counters */ 578 count -= buf_res.length; 579 td->offset += buf_res.length; 580 td->remainder -= buf_res.length; 581 } 582 583 /* check remainder */ 584 if (td->remainder == 0) { 585 if (td->short_pkt) { 586 sc->sc_ep0_cmd = MUSB2_MASK_CSR0L_TXPKTRDY; 587 return (0); /* complete */ 588 } 589 /* else we need to transmit a short packet */ 590 } 591 /* write command */ 592 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 593 MUSB2_MASK_CSR0L_TXPKTRDY); 594 595 return (1); /* not complete */ 596} 597 598static uint8_t 599musbotg_setup_status(struct musbotg_td *td) 600{ 601 struct musbotg_softc *sc; 602 uint8_t csr; 603 604 /* get pointer to softc */ 605 sc = MUSBOTG_PC2SC(td->pc); 606 607 /* select endpoint 0 */ 608 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); 609 610 if (sc->sc_ep0_busy) { 611 sc->sc_ep0_busy = 0; 612 sc->sc_ep0_cmd |= MUSB2_MASK_CSR0L_DATAEND; 613 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, sc->sc_ep0_cmd); 614 sc->sc_ep0_cmd = 0; 615 } 616 /* read out FIFO status */ 617 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 618 619 DPRINTFN(4, "csr=0x%02x\n", csr); 620 621 if (csr & MUSB2_MASK_CSR0L_DATAEND) { 622 /* wait for interrupt */ 623 return (1); /* not complete */ 624 } 625 if (sc->sc_dv_addr != 0xFF) { 626 /* write function address */ 627 musbotg_set_address(sc, sc->sc_dv_addr); 628 } 629 return (0); /* complete */ 630} 631 632static uint8_t 633musbotg_data_rx(struct musbotg_td *td) 634{ 635 struct usb2_page_search buf_res; 636 struct musbotg_softc *sc; 637 uint16_t count; 638 uint8_t csr; 639 uint8_t to; 640 uint8_t got_short; 641 642 to = 8; /* don't loop forever! */ 643 got_short = 0; 644 645 /* get pointer to softc */ 646 sc = MUSBOTG_PC2SC(td->pc); 647 648 /* select endpoint */ 649 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, td->ep_no); 650 651repeat: 652 /* read out FIFO status */ 653 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL); 654 655 DPRINTFN(4, "csr=0x%02x\n", csr); 656 657 /* clear overrun */ 658 if (csr & MUSB2_MASK_CSRL_RXOVERRUN) { 659 /* make sure we don't clear "RXPKTRDY" */ 660 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 661 MUSB2_MASK_CSRL_RXPKTRDY); 662 } 663 /* check status */ 664 if (!(csr & MUSB2_MASK_CSRL_RXPKTRDY)) { 665 return (1); /* not complete */ 666 } 667 /* get the packet byte count */ 668 count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT); 669 670 DPRINTFN(4, "count=0x%04x\n", count); 671 672 /* 673 * Check for short or invalid packet: 674 */ 675 if (count != td->max_frame_size) { 676 if (count < td->max_frame_size) { 677 /* we have a short packet */ 678 td->short_pkt = 1; 679 got_short = 1; 680 } else { 681 /* invalid USB packet */ 682 td->error = 1; 683 return (0); /* we are complete */ 684 } 685 } 686 /* verify the packet byte count */ 687 if (count > td->remainder) { 688 /* invalid USB packet */ 689 td->error = 1; 690 return (0); /* we are complete */ 691 } 692 while (count > 0) { 693 uint32_t temp; 694 695 usb2_get_page(td->pc, td->offset, &buf_res); 696 697 /* get correct length */ 698 if (buf_res.length > count) { 699 buf_res.length = count; 700 } 701 /* check for unaligned memory address */ 702 if (USB_P2U(buf_res.buffer) & 3) { 703 704 temp = count & ~3; 705 706 if (temp) { 707 /* receive data 4 bytes at a time */ 708 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 709 MUSB2_REG_EPFIFO(td->ep_no), sc->sc_bounce_buf, 710 temp / 4); 711 } 712 temp = count & 3; 713 if (temp) { 714 /* receive data 1 byte at a time */ 715 bus_space_read_multi_1(sc->sc_io_tag, 716 sc->sc_io_hdl, MUSB2_REG_EPFIFO(td->ep_no), 717 ((void *)&sc->sc_bounce_buf[count / 4]), temp); 718 } 719 usb2_copy_in(td->pc, td->offset, 720 sc->sc_bounce_buf, count); 721 722 /* update offset and remainder */ 723 td->offset += count; 724 td->remainder -= count; 725 break; 726 } 727 /* check if we can optimise */ 728 if (buf_res.length >= 4) { 729 730 /* receive data 4 bytes at a time */ 731 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 732 MUSB2_REG_EPFIFO(td->ep_no), buf_res.buffer, 733 buf_res.length / 4); 734 735 temp = buf_res.length & ~3; 736 737 /* update counters */ 738 count -= temp; 739 td->offset += temp; 740 td->remainder -= temp; 741 continue; 742 } 743 /* receive data */ 744 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 745 MUSB2_REG_EPFIFO(td->ep_no), buf_res.buffer, 746 buf_res.length); 747 748 /* update counters */ 749 count -= buf_res.length; 750 td->offset += buf_res.length; 751 td->remainder -= buf_res.length; 752 } 753 754 /* clear status bits */ 755 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 0); 756 757 /* check if we are complete */ 758 if ((td->remainder == 0) || got_short) { 759 if (td->short_pkt) { 760 /* we are complete */ 761 return (0); 762 } 763 /* else need to receive a zero length packet */ 764 } 765 if (--to) { 766 goto repeat; 767 } 768 return (1); /* not complete */ 769} 770 771static uint8_t 772musbotg_data_tx(struct musbotg_td *td) 773{ 774 struct usb2_page_search buf_res; 775 struct musbotg_softc *sc; 776 uint16_t count; 777 uint8_t csr; 778 uint8_t to; 779 780 to = 8; /* don't loop forever! */ 781 782 /* get pointer to softc */ 783 sc = MUSBOTG_PC2SC(td->pc); 784 785 /* select endpoint */ 786 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, td->ep_no); 787 788repeat: 789 790 /* read out FIFO status */ 791 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 792 793 DPRINTFN(4, "csr=0x%02x\n", csr); 794 795 if (csr & (MUSB2_MASK_CSRL_TXINCOMP | 796 MUSB2_MASK_CSRL_TXUNDERRUN)) { 797 /* clear status bits */ 798 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0); 799 } 800 if (csr & MUSB2_MASK_CSRL_TXPKTRDY) { 801 return (1); /* not complete */ 802 } 803 /* check for short packet */ 804 count = td->max_frame_size; 805 if (td->remainder < count) { 806 /* we have a short packet */ 807 td->short_pkt = 1; 808 count = td->remainder; 809 } 810 while (count > 0) { 811 uint32_t temp; 812 813 usb2_get_page(td->pc, td->offset, &buf_res); 814 815 /* get correct length */ 816 if (buf_res.length > count) { 817 buf_res.length = count; 818 } 819 /* check for unaligned memory address */ 820 if (USB_P2U(buf_res.buffer) & 3) { 821 822 usb2_copy_out(td->pc, td->offset, 823 sc->sc_bounce_buf, count); 824 825 temp = count & ~3; 826 827 if (temp) { 828 /* transmit data 4 bytes at a time */ 829 bus_space_write_multi_4(sc->sc_io_tag, 830 sc->sc_io_hdl, MUSB2_REG_EPFIFO(td->ep_no), 831 sc->sc_bounce_buf, temp / 4); 832 } 833 temp = count & 3; 834 if (temp) { 835 /* receive data 1 byte at a time */ 836 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 837 MUSB2_REG_EPFIFO(td->ep_no), 838 ((void *)&sc->sc_bounce_buf[count / 4]), temp); 839 } 840 /* update offset and remainder */ 841 td->offset += count; 842 td->remainder -= count; 843 break; 844 } 845 /* check if we can optimise */ 846 if (buf_res.length >= 4) { 847 848 /* transmit data 4 bytes at a time */ 849 bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 850 MUSB2_REG_EPFIFO(td->ep_no), buf_res.buffer, 851 buf_res.length / 4); 852 853 temp = buf_res.length & ~3; 854 855 /* update counters */ 856 count -= temp; 857 td->offset += temp; 858 td->remainder -= temp; 859 continue; 860 } 861 /* transmit data */ 862 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 863 MUSB2_REG_EPFIFO(td->ep_no), buf_res.buffer, 864 buf_res.length); 865 866 /* update counters */ 867 count -= buf_res.length; 868 td->offset += buf_res.length; 869 td->remainder -= buf_res.length; 870 } 871 872 /* write command */ 873 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 874 MUSB2_MASK_CSRL_TXPKTRDY); 875 876 /* check remainder */ 877 if (td->remainder == 0) { 878 if (td->short_pkt) { 879 return (0); /* complete */ 880 } 881 /* else we need to transmit a short packet */ 882 } 883 if (--to) { 884 goto repeat; 885 } 886 return (1); /* not complete */ 887} 888 889static uint8_t 890musbotg_xfer_do_fifo(struct usb2_xfer *xfer) 891{ 892 struct musbotg_softc *sc; 893 struct musbotg_td *td; 894 895 DPRINTFN(8, "\n"); 896 897 td = xfer->td_transfer_cache; 898 while (1) { 899 if ((td->func) (td)) { 900 /* operation in progress */ 901 break; 902 } 903 if (((void *)td) == xfer->td_transfer_last) { 904 goto done; 905 } 906 if (td->error) { 907 goto done; 908 } else if (td->remainder > 0) { 909 /* 910 * We had a short transfer. If there is no alternate 911 * next, stop processing ! 912 */ 913 if (!td->alt_next) { 914 goto done; 915 } 916 } 917 /* 918 * Fetch the next transfer descriptor and transfer 919 * some flags to the next transfer descriptor 920 */ 921 td = td->obj_next; 922 xfer->td_transfer_cache = td; 923 } 924 return (1); /* not complete */ 925 926done: 927 sc = MUSBOTG_BUS2SC(xfer->xroot->bus); 928 929 /* compute all actual lengths */ 930 931 musbotg_standard_done(xfer); 932 933 return (0); /* complete */ 934} 935 936static void 937musbotg_interrupt_poll(struct musbotg_softc *sc) 938{ 939 struct usb2_xfer *xfer; 940 941repeat: 942 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 943 if (!musbotg_xfer_do_fifo(xfer)) { 944 /* queue has been modified */ 945 goto repeat; 946 } 947 } 948} 949 950void 951musbotg_vbus_interrupt(struct musbotg_softc *sc, uint8_t is_on) 952{ 953 DPRINTFN(4, "vbus = %u\n", is_on); 954 955 USB_BUS_LOCK(&sc->sc_bus); 956 if (is_on) { 957 if (!sc->sc_flags.status_vbus) { 958 sc->sc_flags.status_vbus = 1; 959 960 /* complete root HUB interrupt endpoint */ 961 musbotg_root_intr(sc); 962 } 963 } else { 964 if (sc->sc_flags.status_vbus) { 965 sc->sc_flags.status_vbus = 0; 966 sc->sc_flags.status_bus_reset = 0; 967 sc->sc_flags.status_suspend = 0; 968 sc->sc_flags.change_suspend = 0; 969 sc->sc_flags.change_connect = 1; 970 971 /* complete root HUB interrupt endpoint */ 972 musbotg_root_intr(sc); 973 } 974 } 975 976 USB_BUS_UNLOCK(&sc->sc_bus); 977} 978 979void 980musbotg_interrupt(struct musbotg_softc *sc) 981{ 982 uint16_t rx_status; 983 uint16_t tx_status; 984 uint8_t usb_status; 985 uint8_t temp; 986 uint8_t to = 2; 987 988 USB_BUS_LOCK(&sc->sc_bus); 989 990repeat: 991 992 /* read all interrupt registers */ 993 usb_status = MUSB2_READ_1(sc, MUSB2_REG_INTUSB); 994 995 /* read all FIFO interrupts */ 996 rx_status = MUSB2_READ_2(sc, MUSB2_REG_INTRX); 997 tx_status = MUSB2_READ_2(sc, MUSB2_REG_INTTX); 998 999 /* check for any bus state change interrupts */ 1000 1001 if (usb_status & (MUSB2_MASK_IRESET | 1002 MUSB2_MASK_IRESUME | MUSB2_MASK_ISUSP)) { 1003 1004 DPRINTFN(4, "real bus interrupt 0x%08x\n", usb_status); 1005 1006 if (usb_status & MUSB2_MASK_IRESET) { 1007 1008 /* set correct state */ 1009 sc->sc_flags.status_bus_reset = 1; 1010 sc->sc_flags.status_suspend = 0; 1011 sc->sc_flags.change_suspend = 0; 1012 sc->sc_flags.change_connect = 1; 1013 1014 /* determine line speed */ 1015 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER); 1016 if (temp & MUSB2_MASK_HSMODE) 1017 sc->sc_flags.status_high_speed = 1; 1018 else 1019 sc->sc_flags.status_high_speed = 0; 1020 1021 /* 1022 * After reset all interrupts are on and we need to 1023 * turn them off! 1024 */ 1025 temp = MUSB2_MASK_IRESET; 1026 /* disable resume interrupt */ 1027 temp &= ~MUSB2_MASK_IRESUME; 1028 /* enable suspend interrupt */ 1029 temp |= MUSB2_MASK_ISUSP; 1030 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, temp); 1031 /* disable TX and RX interrupts */ 1032 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, 0); 1033 MUSB2_WRITE_2(sc, MUSB2_REG_INTRXE, 0); 1034 } 1035 /* 1036 * If RXRSM and RXSUSP is set at the same time we interpret 1037 * that like RESUME. Resume is set when there is at least 3 1038 * milliseconds of inactivity on the USB BUS. 1039 */ 1040 if (usb_status & MUSB2_MASK_IRESUME) { 1041 if (sc->sc_flags.status_suspend) { 1042 sc->sc_flags.status_suspend = 0; 1043 sc->sc_flags.change_suspend = 1; 1044 1045 temp = MUSB2_READ_1(sc, MUSB2_REG_INTUSBE); 1046 /* disable resume interrupt */ 1047 temp &= ~MUSB2_MASK_IRESUME; 1048 /* enable suspend interrupt */ 1049 temp |= MUSB2_MASK_ISUSP; 1050 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, temp); 1051 } 1052 } else if (usb_status & MUSB2_MASK_ISUSP) { 1053 if (!sc->sc_flags.status_suspend) { 1054 sc->sc_flags.status_suspend = 1; 1055 sc->sc_flags.change_suspend = 1; 1056 1057 temp = MUSB2_READ_1(sc, MUSB2_REG_INTUSBE); 1058 /* disable suspend interrupt */ 1059 temp &= ~MUSB2_MASK_ISUSP; 1060 /* enable resume interrupt */ 1061 temp |= MUSB2_MASK_IRESUME; 1062 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, temp); 1063 } 1064 } 1065 /* complete root HUB interrupt endpoint */ 1066 musbotg_root_intr(sc); 1067 } 1068 /* check for any endpoint interrupts */ 1069 1070 if (rx_status || tx_status) { 1071 DPRINTFN(4, "real endpoint interrupt " 1072 "rx=0x%04x, tx=0x%04x\n", rx_status, tx_status); 1073 } 1074 /* poll one time regardless of FIFO status */ 1075 1076 musbotg_interrupt_poll(sc); 1077 1078 if (--to) 1079 goto repeat; 1080 1081 USB_BUS_UNLOCK(&sc->sc_bus); 1082} 1083 1084static void 1085musbotg_setup_standard_chain_sub(struct musbotg_std_temp *temp) 1086{ 1087 struct musbotg_td *td; 1088 1089 /* get current Transfer Descriptor */ 1090 td = temp->td_next; 1091 temp->td = td; 1092 1093 /* prepare for next TD */ 1094 temp->td_next = td->obj_next; 1095 1096 /* fill out the Transfer Descriptor */ 1097 td->func = temp->func; 1098 td->pc = temp->pc; 1099 td->offset = temp->offset; 1100 td->remainder = temp->len; 1101 td->error = 0; 1102 td->did_stall = temp->did_stall; 1103 td->short_pkt = temp->short_pkt; 1104 td->alt_next = temp->setup_alt_next; 1105} 1106 1107static void 1108musbotg_setup_standard_chain(struct usb2_xfer *xfer) 1109{ 1110 struct musbotg_std_temp temp; 1111 struct musbotg_softc *sc; 1112 struct musbotg_td *td; 1113 uint32_t x; 1114 uint8_t ep_no; 1115 1116 DPRINTFN(8, "addr=%d endpt=%d sumlen=%d speed=%d\n", 1117 xfer->address, UE_GET_ADDR(xfer->endpoint), 1118 xfer->sumlen, usb2_get_speed(xfer->xroot->udev)); 1119 1120 temp.max_frame_size = xfer->max_frame_size; 1121 1122 td = xfer->td_start[0]; 1123 xfer->td_transfer_first = td; 1124 xfer->td_transfer_cache = td; 1125 1126 /* setup temp */ 1127 1128 temp.td = NULL; 1129 temp.td_next = xfer->td_start[0]; 1130 temp.offset = 0; 1131 temp.setup_alt_next = xfer->flags_int.short_frames_ok; 1132 temp.did_stall = !xfer->flags_int.control_stall; 1133 1134 sc = MUSBOTG_BUS2SC(xfer->xroot->bus); 1135 ep_no = (xfer->endpoint & UE_ADDR); 1136 1137 /* check if we should prepend a setup message */ 1138 1139 if (xfer->flags_int.control_xfr) { 1140 if (xfer->flags_int.control_hdr) { 1141 1142 temp.func = &musbotg_setup_rx; 1143 temp.len = xfer->frlengths[0]; 1144 temp.pc = xfer->frbuffers + 0; 1145 temp.short_pkt = temp.len ? 1 : 0; 1146 1147 musbotg_setup_standard_chain_sub(&temp); 1148 } 1149 x = 1; 1150 } else { 1151 x = 0; 1152 } 1153 1154 if (x != xfer->nframes) { 1155 if (xfer->endpoint & UE_DIR_IN) { 1156 if (xfer->flags_int.control_xfr) 1157 temp.func = &musbotg_setup_data_tx; 1158 else 1159 temp.func = &musbotg_data_tx; 1160 } else { 1161 if (xfer->flags_int.control_xfr) 1162 temp.func = &musbotg_setup_data_rx; 1163 else 1164 temp.func = &musbotg_data_rx; 1165 } 1166 1167 /* setup "pc" pointer */ 1168 temp.pc = xfer->frbuffers + x; 1169 } 1170 while (x != xfer->nframes) { 1171 1172 /* DATA0 / DATA1 message */ 1173 1174 temp.len = xfer->frlengths[x]; 1175 1176 x++; 1177 1178 if (x == xfer->nframes) { 1179 if (xfer->flags_int.control_xfr) { 1180 if (xfer->flags_int.control_act) { 1181 temp.setup_alt_next = 0; 1182 } 1183 } else { 1184 temp.setup_alt_next = 0; 1185 } 1186 } 1187 if (temp.len == 0) { 1188 1189 /* make sure that we send an USB packet */ 1190 1191 temp.short_pkt = 0; 1192 1193 } else { 1194 1195 /* regular data transfer */ 1196 1197 temp.short_pkt = (xfer->flags.force_short_xfer) ? 0 : 1; 1198 } 1199 1200 musbotg_setup_standard_chain_sub(&temp); 1201 1202 if (xfer->flags_int.isochronous_xfr) { 1203 temp.offset += temp.len; 1204 } else { 1205 /* get next Page Cache pointer */ 1206 temp.pc = xfer->frbuffers + x; 1207 } 1208 } 1209 1210 /* check for control transfer */ 1211 if (xfer->flags_int.control_xfr) { 1212 1213 /* always setup a valid "pc" pointer for status and sync */ 1214 temp.pc = xfer->frbuffers + 0; 1215 temp.len = 0; 1216 temp.short_pkt = 0; 1217 temp.setup_alt_next = 0; 1218 1219 /* check if we should append a status stage */ 1220 if (!xfer->flags_int.control_act) { 1221 /* 1222 * Send a DATA1 message and invert the current 1223 * endpoint direction. 1224 */ 1225 temp.func = &musbotg_setup_status; 1226 musbotg_setup_standard_chain_sub(&temp); 1227 } 1228 } 1229 /* must have at least one frame! */ 1230 td = temp.td; 1231 xfer->td_transfer_last = td; 1232} 1233 1234static void 1235musbotg_timeout(void *arg) 1236{ 1237 struct usb2_xfer *xfer = arg; 1238 1239 DPRINTFN(1, "xfer=%p\n", xfer); 1240 1241 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 1242 1243 /* transfer is transferred */ 1244 musbotg_device_done(xfer, USB_ERR_TIMEOUT); 1245} 1246 1247static void 1248musbotg_ep_int_set(struct usb2_xfer *xfer, uint8_t on) 1249{ 1250 struct musbotg_softc *sc = MUSBOTG_BUS2SC(xfer->xroot->bus); 1251 uint16_t temp; 1252 uint8_t ep_no = xfer->endpoint & UE_ADDR; 1253 1254 /* 1255 * Only enable the endpoint interrupt when we are 1256 * actually waiting for data, hence we are dealing 1257 * with level triggered interrupts ! 1258 */ 1259 if (ep_no == 0) { 1260 temp = MUSB2_READ_2(sc, MUSB2_REG_INTTXE); 1261 if (on) 1262 temp |= MUSB2_MASK_EPINT(0); 1263 else 1264 temp &= ~MUSB2_MASK_EPINT(0); 1265 1266 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, temp); 1267 } else { 1268 if (USB_GET_DATA_ISREAD(xfer)) { 1269 temp = MUSB2_READ_2(sc, MUSB2_REG_INTRXE); 1270 if (on) 1271 temp |= MUSB2_MASK_EPINT(ep_no); 1272 else 1273 temp &= ~MUSB2_MASK_EPINT(ep_no); 1274 MUSB2_WRITE_2(sc, MUSB2_REG_INTRXE, temp); 1275 1276 } else { 1277 temp = MUSB2_READ_2(sc, MUSB2_REG_INTTXE); 1278 if (on) 1279 temp |= MUSB2_MASK_EPINT(ep_no); 1280 else 1281 temp &= ~MUSB2_MASK_EPINT(ep_no); 1282 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, temp); 1283 } 1284 } 1285} 1286 1287static void 1288musbotg_start_standard_chain(struct usb2_xfer *xfer) 1289{ 1290 DPRINTFN(8, "\n"); 1291 1292 /* poll one time */ 1293 if (musbotg_xfer_do_fifo(xfer)) { 1294 1295 musbotg_ep_int_set(xfer, 1); 1296 1297 DPRINTFN(14, "enabled interrupts on endpoint\n"); 1298 1299 /* put transfer on interrupt queue */ 1300 usb2_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 1301 1302 /* start timeout, if any */ 1303 if (xfer->timeout != 0) { 1304 usb2_transfer_timeout_ms(xfer, 1305 &musbotg_timeout, xfer->timeout); 1306 } 1307 } 1308} 1309 1310static void 1311musbotg_root_intr(struct musbotg_softc *sc) 1312{ 1313 DPRINTFN(8, "\n"); 1314 1315 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1316 1317 /* set port bit */ 1318 sc->sc_hub_idata[0] = 0x02; /* we only have one port */ 1319 1320 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, 1321 sizeof(sc->sc_hub_idata)); 1322} 1323 1324static usb2_error_t 1325musbotg_standard_done_sub(struct usb2_xfer *xfer) 1326{ 1327 struct musbotg_td *td; 1328 uint32_t len; 1329 uint8_t error; 1330 1331 DPRINTFN(8, "\n"); 1332 1333 td = xfer->td_transfer_cache; 1334 1335 do { 1336 len = td->remainder; 1337 1338 if (xfer->aframes != xfer->nframes) { 1339 /* 1340 * Verify the length and subtract 1341 * the remainder from "frlengths[]": 1342 */ 1343 if (len > xfer->frlengths[xfer->aframes]) { 1344 td->error = 1; 1345 } else { 1346 xfer->frlengths[xfer->aframes] -= len; 1347 } 1348 } 1349 /* Check for transfer error */ 1350 if (td->error) { 1351 /* the transfer is finished */ 1352 error = 1; 1353 td = NULL; 1354 break; 1355 } 1356 /* Check for short transfer */ 1357 if (len > 0) { 1358 if (xfer->flags_int.short_frames_ok) { 1359 /* follow alt next */ 1360 if (td->alt_next) { 1361 td = td->obj_next; 1362 } else { 1363 td = NULL; 1364 } 1365 } else { 1366 /* the transfer is finished */ 1367 td = NULL; 1368 } 1369 error = 0; 1370 break; 1371 } 1372 td = td->obj_next; 1373 1374 /* this USB frame is complete */ 1375 error = 0; 1376 break; 1377 1378 } while (0); 1379 1380 /* update transfer cache */ 1381 1382 xfer->td_transfer_cache = td; 1383 1384 return (error ? 1385 USB_ERR_STALLED : USB_ERR_NORMAL_COMPLETION); 1386} 1387 1388static void 1389musbotg_standard_done(struct usb2_xfer *xfer) 1390{ 1391 usb2_error_t err = 0; 1392 1393 DPRINTFN(12, "xfer=%p pipe=%p transfer done\n", 1394 xfer, xfer->pipe); 1395 1396 /* reset scanner */ 1397 1398 xfer->td_transfer_cache = xfer->td_transfer_first; 1399 1400 if (xfer->flags_int.control_xfr) { 1401 1402 if (xfer->flags_int.control_hdr) { 1403 1404 err = musbotg_standard_done_sub(xfer); 1405 } 1406 xfer->aframes = 1; 1407 1408 if (xfer->td_transfer_cache == NULL) { 1409 goto done; 1410 } 1411 } 1412 while (xfer->aframes != xfer->nframes) { 1413 1414 err = musbotg_standard_done_sub(xfer); 1415 xfer->aframes++; 1416 1417 if (xfer->td_transfer_cache == NULL) { 1418 goto done; 1419 } 1420 } 1421 1422 if (xfer->flags_int.control_xfr && 1423 !xfer->flags_int.control_act) { 1424 1425 err = musbotg_standard_done_sub(xfer); 1426 } 1427done: 1428 musbotg_device_done(xfer, err); 1429} 1430 1431/*------------------------------------------------------------------------* 1432 * musbotg_device_done 1433 * 1434 * NOTE: this function can be called more than one time on the 1435 * same USB transfer! 1436 *------------------------------------------------------------------------*/ 1437static void 1438musbotg_device_done(struct usb2_xfer *xfer, usb2_error_t error) 1439{ 1440 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 1441 1442 DPRINTFN(2, "xfer=%p, pipe=%p, error=%d\n", 1443 xfer, xfer->pipe, error); 1444 1445 if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) { 1446 1447 musbotg_ep_int_set(xfer, 0); 1448 1449 DPRINTFN(14, "disabled interrupts on endpoint\n"); 1450 } 1451 /* dequeue transfer and start next transfer */ 1452 usb2_transfer_done(xfer, error); 1453} 1454 1455static void 1456musbotg_set_stall(struct usb2_device *udev, struct usb2_xfer *xfer, 1457 struct usb2_pipe *pipe) 1458{ 1459 struct musbotg_softc *sc; 1460 uint8_t ep_no; 1461 1462 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 1463 1464 DPRINTFN(4, "pipe=%p\n", pipe); 1465 1466 if (xfer) { 1467 /* cancel any ongoing transfers */ 1468 musbotg_device_done(xfer, USB_ERR_STALLED); 1469 } 1470 /* set FORCESTALL */ 1471 sc = MUSBOTG_BUS2SC(udev->bus); 1472 1473 ep_no = (pipe->edesc->bEndpointAddress & UE_ADDR); 1474 1475 /* select endpoint */ 1476 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, ep_no); 1477 1478 if (pipe->edesc->bEndpointAddress & UE_DIR_IN) { 1479 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 1480 MUSB2_MASK_CSRL_TXSENDSTALL); 1481 } else { 1482 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 1483 MUSB2_MASK_CSRL_RXSENDSTALL); 1484 } 1485} 1486 1487static void 1488musbotg_clear_stall_sub(struct musbotg_softc *sc, uint16_t wMaxPacket, 1489 uint8_t ep_no, uint8_t ep_type, uint8_t ep_dir) 1490{ 1491 uint16_t mps; 1492 uint16_t temp; 1493 uint8_t csr; 1494 1495 if (ep_type == UE_CONTROL) { 1496 /* clearing stall is not needed */ 1497 return; 1498 } 1499 /* select endpoint */ 1500 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, ep_no); 1501 1502 /* compute max frame size */ 1503 mps = wMaxPacket & 0x7FF; 1504 switch ((wMaxPacket >> 11) & 3) { 1505 case 1: 1506 mps *= 2; 1507 break; 1508 case 2: 1509 mps *= 3; 1510 break; 1511 default: 1512 break; 1513 } 1514 1515 if (ep_dir == UE_DIR_IN) { 1516 1517 temp = 0; 1518 1519 /* Configure endpoint */ 1520 switch (ep_type) { 1521 case UE_INTERRUPT: 1522 MUSB2_WRITE_1(sc, MUSB2_REG_TXMAXP, wMaxPacket); 1523 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, 1524 MUSB2_MASK_CSRH_TXMODE | temp); 1525 break; 1526 case UE_ISOCHRONOUS: 1527 MUSB2_WRITE_1(sc, MUSB2_REG_TXMAXP, wMaxPacket); 1528 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, 1529 MUSB2_MASK_CSRH_TXMODE | 1530 MUSB2_MASK_CSRH_TXISO | temp); 1531 break; 1532 case UE_BULK: 1533 MUSB2_WRITE_1(sc, MUSB2_REG_TXMAXP, wMaxPacket); 1534 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, 1535 MUSB2_MASK_CSRH_TXMODE | temp); 1536 break; 1537 default: 1538 break; 1539 } 1540 1541 /* Need to flush twice in case of double bufring */ 1542 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 1543 if (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) { 1544 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 1545 MUSB2_MASK_CSRL_TXFFLUSH); 1546 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 1547 if (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) { 1548 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 1549 MUSB2_MASK_CSRL_TXFFLUSH); 1550 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 1551 } 1552 } 1553 /* reset data toggle */ 1554 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 1555 MUSB2_MASK_CSRL_TXDT_CLR); 1556 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0); 1557 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 1558 1559 /* set double/single buffering */ 1560 temp = MUSB2_READ_2(sc, MUSB2_REG_TXDBDIS); 1561 if (mps <= (sc->sc_hw_ep_profile[ep_no]. 1562 max_in_frame_size / 2)) { 1563 /* double buffer */ 1564 temp &= ~(1 << ep_no); 1565 } else { 1566 /* single buffer */ 1567 temp |= (1 << ep_no); 1568 } 1569 MUSB2_WRITE_2(sc, MUSB2_REG_TXDBDIS, temp); 1570 1571 /* clear sent stall */ 1572 if (csr & MUSB2_MASK_CSRL_TXSENTSTALL) { 1573 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0); 1574 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 1575 } 1576 } else { 1577 1578 temp = 0; 1579 1580 /* Configure endpoint */ 1581 switch (ep_type) { 1582 case UE_INTERRUPT: 1583 MUSB2_WRITE_1(sc, MUSB2_REG_RXMAXP, wMaxPacket); 1584 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH, 1585 MUSB2_MASK_CSRH_RXNYET | temp); 1586 break; 1587 case UE_ISOCHRONOUS: 1588 MUSB2_WRITE_1(sc, MUSB2_REG_RXMAXP, wMaxPacket); 1589 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH, 1590 MUSB2_MASK_CSRH_RXNYET | 1591 MUSB2_MASK_CSRH_RXISO | temp); 1592 break; 1593 case UE_BULK: 1594 MUSB2_WRITE_1(sc, MUSB2_REG_RXMAXP, wMaxPacket); 1595 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH, temp); 1596 break; 1597 default: 1598 break; 1599 } 1600 1601 /* Need to flush twice in case of double bufring */ 1602 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL); 1603 if (csr & MUSB2_MASK_CSRL_RXPKTRDY) { 1604 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 1605 MUSB2_MASK_CSRL_RXFFLUSH); 1606 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL); 1607 if (csr & MUSB2_MASK_CSRL_RXPKTRDY) { 1608 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 1609 MUSB2_MASK_CSRL_RXFFLUSH); 1610 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL); 1611 } 1612 } 1613 /* reset data toggle */ 1614 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 1615 MUSB2_MASK_CSRL_RXDT_CLR); 1616 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 0); 1617 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL); 1618 1619 /* set double/single buffering */ 1620 temp = MUSB2_READ_2(sc, MUSB2_REG_RXDBDIS); 1621 if (mps <= (sc->sc_hw_ep_profile[ep_no]. 1622 max_out_frame_size / 2)) { 1623 /* double buffer */ 1624 temp &= ~(1 << ep_no); 1625 } else { 1626 /* single buffer */ 1627 temp |= (1 << ep_no); 1628 } 1629 MUSB2_WRITE_2(sc, MUSB2_REG_RXDBDIS, temp); 1630 1631 /* clear sent stall */ 1632 if (csr & MUSB2_MASK_CSRL_RXSENTSTALL) { 1633 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 0); 1634 } 1635 } 1636} 1637 1638static void 1639musbotg_clear_stall(struct usb2_device *udev, struct usb2_pipe *pipe) 1640{ 1641 struct musbotg_softc *sc; 1642 struct usb2_endpoint_descriptor *ed; 1643 1644 DPRINTFN(4, "pipe=%p\n", pipe); 1645 1646 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 1647 1648 /* check mode */ 1649 if (udev->flags.usb_mode != USB_MODE_DEVICE) { 1650 /* not supported */ 1651 return; 1652 } 1653 /* get softc */ 1654 sc = MUSBOTG_BUS2SC(udev->bus); 1655 1656 /* get endpoint descriptor */ 1657 ed = pipe->edesc; 1658 1659 /* reset endpoint */ 1660 musbotg_clear_stall_sub(sc, 1661 UGETW(ed->wMaxPacketSize), 1662 (ed->bEndpointAddress & UE_ADDR), 1663 (ed->bmAttributes & UE_XFERTYPE), 1664 (ed->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT))); 1665} 1666 1667usb2_error_t 1668musbotg_init(struct musbotg_softc *sc) 1669{ 1670 struct usb2_hw_ep_profile *pf; 1671 uint8_t nrx; 1672 uint8_t ntx; 1673 uint8_t temp; 1674 uint8_t fsize; 1675 uint8_t frx; 1676 uint8_t ftx; 1677 1678 DPRINTFN(1, "start\n"); 1679 1680 /* set up the bus structure */ 1681 sc->sc_bus.usbrev = USB_REV_2_0; 1682 sc->sc_bus.methods = &musbotg_bus_methods; 1683 1684 USB_BUS_LOCK(&sc->sc_bus); 1685 1686 /* turn on clocks */ 1687 1688 if (sc->sc_clocks_on) { 1689 (sc->sc_clocks_on) (sc->sc_clocks_arg); 1690 } 1691 /* wait a little for things to stabilise */ 1692 usb2_pause_mtx(&sc->sc_bus.bus_mtx, hz / 1000); 1693 1694 /* disable all interrupts */ 1695 1696 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, 0); 1697 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, 0); 1698 MUSB2_WRITE_2(sc, MUSB2_REG_INTRXE, 0); 1699 1700 /* disable pullup */ 1701 1702 musbotg_pull_common(sc, 0); 1703 1704 /* wait a little bit (10ms) */ 1705 usb2_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100); 1706 1707 /* disable double packet buffering */ 1708 MUSB2_WRITE_2(sc, MUSB2_REG_RXDBDIS, 0xFFFF); 1709 MUSB2_WRITE_2(sc, MUSB2_REG_TXDBDIS, 0xFFFF); 1710 1711 /* enable HighSpeed and ISO Update flags */ 1712 1713 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, 1714 MUSB2_MASK_HSENAB | MUSB2_MASK_ISOUPD); 1715 1716 /* clear Session bit, if set */ 1717 1718 temp = MUSB2_READ_1(sc, MUSB2_REG_DEVCTL); 1719 temp &= ~MUSB2_MASK_SESS; 1720 MUSB2_WRITE_1(sc, MUSB2_REG_DEVCTL, temp); 1721 1722 DPRINTF("DEVCTL=0x%02x\n", temp); 1723 1724 /* disable testmode */ 1725 1726 MUSB2_WRITE_1(sc, MUSB2_REG_TESTMODE, 0); 1727 1728 /* set default value */ 1729 1730 MUSB2_WRITE_1(sc, MUSB2_REG_MISC, 0); 1731 1732 /* select endpoint index 0 */ 1733 1734 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); 1735 1736 /* read out number of endpoints */ 1737 1738 nrx = 1739 (MUSB2_READ_1(sc, MUSB2_REG_EPINFO) / 16); 1740 1741 ntx = 1742 (MUSB2_READ_1(sc, MUSB2_REG_EPINFO) % 16); 1743 1744 /* these numbers exclude the control endpoint */ 1745 1746 DPRINTFN(2, "RX/TX endpoints: %u/%u\n", nrx, ntx); 1747 1748 sc->sc_ep_max = (nrx > ntx) ? nrx : ntx; 1749 if (sc->sc_ep_max == 0) { 1750 DPRINTFN(2, "ERROR: Looks like the clocks are off!\n"); 1751 } 1752 /* read out configuration data */ 1753 1754 sc->sc_conf_data = MUSB2_READ_1(sc, MUSB2_REG_CONFDATA); 1755 1756 DPRINTFN(2, "Config Data: 0x%02x\n", 1757 sc->sc_conf_data); 1758 1759 DPRINTFN(2, "HW version: 0x%04x\n", 1760 MUSB2_READ_1(sc, MUSB2_REG_HWVERS)); 1761 1762 /* initialise endpoint profiles */ 1763 1764 for (temp = 1; temp <= sc->sc_ep_max; temp++) { 1765 pf = sc->sc_hw_ep_profile + temp; 1766 1767 /* select endpoint */ 1768 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, temp); 1769 1770 fsize = MUSB2_READ_1(sc, MUSB2_REG_FSIZE); 1771 frx = (fsize & MUSB2_MASK_RX_FSIZE) / 16;; 1772 ftx = (fsize & MUSB2_MASK_TX_FSIZE); 1773 1774 DPRINTF("Endpoint %u FIFO size: IN=%u, OUT=%u\n", 1775 temp, pf->max_in_frame_size, 1776 pf->max_out_frame_size); 1777 1778 if (frx && ftx && (temp <= nrx) && (temp <= ntx)) { 1779 pf->max_in_frame_size = 1 << ftx; 1780 pf->max_out_frame_size = 1 << frx; 1781 pf->is_simplex = 0; /* duplex */ 1782 pf->support_multi_buffer = 1; 1783 pf->support_bulk = 1; 1784 pf->support_interrupt = 1; 1785 pf->support_isochronous = 1; 1786 pf->support_in = 1; 1787 pf->support_out = 1; 1788 } else if (frx && (temp <= nrx)) { 1789 pf->max_out_frame_size = 1 << frx; 1790 pf->is_simplex = 1; /* simplex */ 1791 pf->support_multi_buffer = 1; 1792 pf->support_bulk = 1; 1793 pf->support_interrupt = 1; 1794 pf->support_isochronous = 1; 1795 pf->support_out = 1; 1796 } else if (ftx && (temp <= ntx)) { 1797 pf->max_in_frame_size = 1 << ftx; 1798 pf->is_simplex = 1; /* simplex */ 1799 pf->support_multi_buffer = 1; 1800 pf->support_bulk = 1; 1801 pf->support_interrupt = 1; 1802 pf->support_isochronous = 1; 1803 pf->support_in = 1; 1804 } 1805 } 1806 1807 /* turn on default interrupts */ 1808 1809 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, 1810 MUSB2_MASK_IRESET); 1811 1812 musbotg_clocks_off(sc); 1813 1814 USB_BUS_UNLOCK(&sc->sc_bus); 1815 1816 /* catch any lost interrupts */ 1817 1818 musbotg_do_poll(&sc->sc_bus); 1819 1820 return (0); /* success */ 1821} 1822 1823void 1824musbotg_uninit(struct musbotg_softc *sc) 1825{ 1826 USB_BUS_LOCK(&sc->sc_bus); 1827 1828 /* disable all interrupts */ 1829 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, 0); 1830 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, 0); 1831 MUSB2_WRITE_2(sc, MUSB2_REG_INTRXE, 0); 1832 1833 sc->sc_flags.port_powered = 0; 1834 sc->sc_flags.status_vbus = 0; 1835 sc->sc_flags.status_bus_reset = 0; 1836 sc->sc_flags.status_suspend = 0; 1837 sc->sc_flags.change_suspend = 0; 1838 sc->sc_flags.change_connect = 1; 1839 1840 musbotg_pull_down(sc); 1841 musbotg_clocks_off(sc); 1842 USB_BUS_UNLOCK(&sc->sc_bus); 1843} 1844 1845void 1846musbotg_suspend(struct musbotg_softc *sc) 1847{ 1848 return; 1849} 1850 1851void 1852musbotg_resume(struct musbotg_softc *sc) 1853{ 1854 return; 1855} 1856 1857static void 1858musbotg_do_poll(struct usb2_bus *bus) 1859{ 1860 struct musbotg_softc *sc = MUSBOTG_BUS2SC(bus); 1861 1862 USB_BUS_LOCK(&sc->sc_bus); 1863 musbotg_interrupt_poll(sc); 1864 USB_BUS_UNLOCK(&sc->sc_bus); 1865} 1866 1867/*------------------------------------------------------------------------* 1868 * musbotg bulk support 1869 *------------------------------------------------------------------------*/ 1870static void 1871musbotg_device_bulk_open(struct usb2_xfer *xfer) 1872{ 1873 return; 1874} 1875 1876static void 1877musbotg_device_bulk_close(struct usb2_xfer *xfer) 1878{ 1879 musbotg_device_done(xfer, USB_ERR_CANCELLED); 1880} 1881 1882static void 1883musbotg_device_bulk_enter(struct usb2_xfer *xfer) 1884{ 1885 return; 1886} 1887 1888static void 1889musbotg_device_bulk_start(struct usb2_xfer *xfer) 1890{ 1891 /* setup TDs */ 1892 musbotg_setup_standard_chain(xfer); 1893 musbotg_start_standard_chain(xfer); 1894} 1895 1896struct usb2_pipe_methods musbotg_device_bulk_methods = 1897{ 1898 .open = musbotg_device_bulk_open, 1899 .close = musbotg_device_bulk_close, 1900 .enter = musbotg_device_bulk_enter, 1901 .start = musbotg_device_bulk_start, 1902}; 1903 1904/*------------------------------------------------------------------------* 1905 * musbotg control support 1906 *------------------------------------------------------------------------*/ 1907static void 1908musbotg_device_ctrl_open(struct usb2_xfer *xfer) 1909{ 1910 return; 1911} 1912 1913static void 1914musbotg_device_ctrl_close(struct usb2_xfer *xfer) 1915{ 1916 musbotg_device_done(xfer, USB_ERR_CANCELLED); 1917} 1918 1919static void 1920musbotg_device_ctrl_enter(struct usb2_xfer *xfer) 1921{ 1922 return; 1923} 1924 1925static void 1926musbotg_device_ctrl_start(struct usb2_xfer *xfer) 1927{ 1928 /* setup TDs */ 1929 musbotg_setup_standard_chain(xfer); 1930 musbotg_start_standard_chain(xfer); 1931} 1932 1933struct usb2_pipe_methods musbotg_device_ctrl_methods = 1934{ 1935 .open = musbotg_device_ctrl_open, 1936 .close = musbotg_device_ctrl_close, 1937 .enter = musbotg_device_ctrl_enter, 1938 .start = musbotg_device_ctrl_start, 1939}; 1940 1941/*------------------------------------------------------------------------* 1942 * musbotg interrupt support 1943 *------------------------------------------------------------------------*/ 1944static void 1945musbotg_device_intr_open(struct usb2_xfer *xfer) 1946{ 1947 return; 1948} 1949 1950static void 1951musbotg_device_intr_close(struct usb2_xfer *xfer) 1952{ 1953 musbotg_device_done(xfer, USB_ERR_CANCELLED); 1954} 1955 1956static void 1957musbotg_device_intr_enter(struct usb2_xfer *xfer) 1958{ 1959 return; 1960} 1961 1962static void 1963musbotg_device_intr_start(struct usb2_xfer *xfer) 1964{ 1965 /* setup TDs */ 1966 musbotg_setup_standard_chain(xfer); 1967 musbotg_start_standard_chain(xfer); 1968} 1969 1970struct usb2_pipe_methods musbotg_device_intr_methods = 1971{ 1972 .open = musbotg_device_intr_open, 1973 .close = musbotg_device_intr_close, 1974 .enter = musbotg_device_intr_enter, 1975 .start = musbotg_device_intr_start, 1976}; 1977 1978/*------------------------------------------------------------------------* 1979 * musbotg full speed isochronous support 1980 *------------------------------------------------------------------------*/ 1981static void 1982musbotg_device_isoc_open(struct usb2_xfer *xfer) 1983{ 1984 return; 1985} 1986 1987static void 1988musbotg_device_isoc_close(struct usb2_xfer *xfer) 1989{ 1990 musbotg_device_done(xfer, USB_ERR_CANCELLED); 1991} 1992 1993static void 1994musbotg_device_isoc_enter(struct usb2_xfer *xfer) 1995{ 1996 struct musbotg_softc *sc = MUSBOTG_BUS2SC(xfer->xroot->bus); 1997 uint32_t temp; 1998 uint32_t nframes; 1999 uint32_t fs_frames; 2000 2001 DPRINTFN(5, "xfer=%p next=%d nframes=%d\n", 2002 xfer, xfer->pipe->isoc_next, xfer->nframes); 2003 2004 /* get the current frame index */ 2005 2006 nframes = MUSB2_READ_2(sc, MUSB2_REG_FRAME); 2007 2008 /* 2009 * check if the frame index is within the window where the frames 2010 * will be inserted 2011 */ 2012 temp = (nframes - xfer->pipe->isoc_next) & MUSB2_MASK_FRAME; 2013 2014 if (usb2_get_speed(xfer->xroot->udev) == USB_SPEED_HIGH) { 2015 fs_frames = (xfer->nframes + 7) / 8; 2016 } else { 2017 fs_frames = xfer->nframes; 2018 } 2019 2020 if ((xfer->pipe->is_synced == 0) || 2021 (temp < fs_frames)) { 2022 /* 2023 * If there is data underflow or the pipe queue is 2024 * empty we schedule the transfer a few frames ahead 2025 * of the current frame position. Else two isochronous 2026 * transfers might overlap. 2027 */ 2028 xfer->pipe->isoc_next = (nframes + 3) & MUSB2_MASK_FRAME; 2029 xfer->pipe->is_synced = 1; 2030 DPRINTFN(2, "start next=%d\n", xfer->pipe->isoc_next); 2031 } 2032 /* 2033 * compute how many milliseconds the insertion is ahead of the 2034 * current frame position: 2035 */ 2036 temp = (xfer->pipe->isoc_next - nframes) & MUSB2_MASK_FRAME; 2037 2038 /* 2039 * pre-compute when the isochronous transfer will be finished: 2040 */ 2041 xfer->isoc_time_complete = 2042 usb2_isoc_time_expand(&sc->sc_bus, nframes) + temp + 2043 fs_frames; 2044 2045 /* compute frame number for next insertion */ 2046 xfer->pipe->isoc_next += fs_frames; 2047 2048 /* setup TDs */ 2049 musbotg_setup_standard_chain(xfer); 2050} 2051 2052static void 2053musbotg_device_isoc_start(struct usb2_xfer *xfer) 2054{ 2055 /* start TD chain */ 2056 musbotg_start_standard_chain(xfer); 2057} 2058 2059struct usb2_pipe_methods musbotg_device_isoc_methods = 2060{ 2061 .open = musbotg_device_isoc_open, 2062 .close = musbotg_device_isoc_close, 2063 .enter = musbotg_device_isoc_enter, 2064 .start = musbotg_device_isoc_start, 2065}; 2066 2067/*------------------------------------------------------------------------* 2068 * musbotg root control support 2069 *------------------------------------------------------------------------* 2070 * Simulate a hardware HUB by handling all the necessary requests. 2071 *------------------------------------------------------------------------*/ 2072 2073static const struct usb2_device_descriptor musbotg_devd = { 2074 .bLength = sizeof(struct usb2_device_descriptor), 2075 .bDescriptorType = UDESC_DEVICE, 2076 .bcdUSB = {0x00, 0x02}, 2077 .bDeviceClass = UDCLASS_HUB, 2078 .bDeviceSubClass = UDSUBCLASS_HUB, 2079 .bDeviceProtocol = UDPROTO_HSHUBSTT, 2080 .bMaxPacketSize = 64, 2081 .bcdDevice = {0x00, 0x01}, 2082 .iManufacturer = 1, 2083 .iProduct = 2, 2084 .bNumConfigurations = 1, 2085}; 2086 2087static const struct usb2_device_qualifier musbotg_odevd = { 2088 .bLength = sizeof(struct usb2_device_qualifier), 2089 .bDescriptorType = UDESC_DEVICE_QUALIFIER, 2090 .bcdUSB = {0x00, 0x02}, 2091 .bDeviceClass = UDCLASS_HUB, 2092 .bDeviceSubClass = UDSUBCLASS_HUB, 2093 .bDeviceProtocol = UDPROTO_FSHUB, 2094 .bMaxPacketSize0 = 0, 2095 .bNumConfigurations = 0, 2096}; 2097 2098static const struct musbotg_config_desc musbotg_confd = { 2099 .confd = { 2100 .bLength = sizeof(struct usb2_config_descriptor), 2101 .bDescriptorType = UDESC_CONFIG, 2102 .wTotalLength[0] = sizeof(musbotg_confd), 2103 .bNumInterface = 1, 2104 .bConfigurationValue = 1, 2105 .iConfiguration = 0, 2106 .bmAttributes = UC_SELF_POWERED, 2107 .bMaxPower = 0, 2108 }, 2109 .ifcd = { 2110 .bLength = sizeof(struct usb2_interface_descriptor), 2111 .bDescriptorType = UDESC_INTERFACE, 2112 .bNumEndpoints = 1, 2113 .bInterfaceClass = UICLASS_HUB, 2114 .bInterfaceSubClass = UISUBCLASS_HUB, 2115 .bInterfaceProtocol = UIPROTO_HSHUBSTT, 2116 }, 2117 .endpd = { 2118 .bLength = sizeof(struct usb2_endpoint_descriptor), 2119 .bDescriptorType = UDESC_ENDPOINT, 2120 .bEndpointAddress = (UE_DIR_IN | MUSBOTG_INTR_ENDPT), 2121 .bmAttributes = UE_INTERRUPT, 2122 .wMaxPacketSize[0] = 8, 2123 .bInterval = 255, 2124 }, 2125}; 2126 2127static const struct usb2_hub_descriptor_min musbotg_hubd = { 2128 .bDescLength = sizeof(musbotg_hubd), 2129 .bDescriptorType = UDESC_HUB, 2130 .bNbrPorts = 1, 2131 .wHubCharacteristics[0] = 2132 (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL) & 0xFF, 2133 .wHubCharacteristics[1] = 2134 (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL) >> 16, 2135 .bPwrOn2PwrGood = 50, 2136 .bHubContrCurrent = 0, 2137 .DeviceRemovable = {0}, /* port is removable */ 2138}; 2139 2140#define STRING_LANG \ 2141 0x09, 0x04, /* American English */ 2142 2143#define STRING_VENDOR \ 2144 'M', 0, 'e', 0, 'n', 0, 't', 0, 'o', 0, 'r', 0, ' ', 0, \ 2145 'G', 0, 'r', 0, 'a', 0, 'p', 0, 'h', 0, 'i', 0, 'c', 0, 's', 0 2146 2147#define STRING_PRODUCT \ 2148 'O', 0, 'T', 0, 'G', 0, ' ', 0, 'R', 0, \ 2149 'o', 0, 'o', 0, 't', 0, ' ', 0, 'H', 0, \ 2150 'U', 0, 'B', 0, 2151 2152USB_MAKE_STRING_DESC(STRING_LANG, musbotg_langtab); 2153USB_MAKE_STRING_DESC(STRING_VENDOR, musbotg_vendor); 2154USB_MAKE_STRING_DESC(STRING_PRODUCT, musbotg_product); 2155 2156static usb2_error_t 2157musbotg_roothub_exec(struct usb2_device *udev, 2158 struct usb2_device_request *req, const void **pptr, uint16_t *plength) 2159{ 2160 struct musbotg_softc *sc = MUSBOTG_BUS2SC(udev->bus); 2161 const void *ptr; 2162 uint16_t len; 2163 uint16_t value; 2164 uint16_t index; 2165 usb2_error_t err; 2166 2167 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2168 2169 /* buffer reset */ 2170 ptr = (const void *)&sc->sc_hub_temp; 2171 len = 0; 2172 err = 0; 2173 2174 value = UGETW(req->wValue); 2175 index = UGETW(req->wIndex); 2176 2177 /* demultiplex the control request */ 2178 2179 switch (req->bmRequestType) { 2180 case UT_READ_DEVICE: 2181 switch (req->bRequest) { 2182 case UR_GET_DESCRIPTOR: 2183 goto tr_handle_get_descriptor; 2184 case UR_GET_CONFIG: 2185 goto tr_handle_get_config; 2186 case UR_GET_STATUS: 2187 goto tr_handle_get_status; 2188 default: 2189 goto tr_stalled; 2190 } 2191 break; 2192 2193 case UT_WRITE_DEVICE: 2194 switch (req->bRequest) { 2195 case UR_SET_ADDRESS: 2196 goto tr_handle_set_address; 2197 case UR_SET_CONFIG: 2198 goto tr_handle_set_config; 2199 case UR_CLEAR_FEATURE: 2200 goto tr_valid; /* nop */ 2201 case UR_SET_DESCRIPTOR: 2202 goto tr_valid; /* nop */ 2203 case UR_SET_FEATURE: 2204 default: 2205 goto tr_stalled; 2206 } 2207 break; 2208 2209 case UT_WRITE_ENDPOINT: 2210 switch (req->bRequest) { 2211 case UR_CLEAR_FEATURE: 2212 switch (UGETW(req->wValue)) { 2213 case UF_ENDPOINT_HALT: 2214 goto tr_handle_clear_halt; 2215 case UF_DEVICE_REMOTE_WAKEUP: 2216 goto tr_handle_clear_wakeup; 2217 default: 2218 goto tr_stalled; 2219 } 2220 break; 2221 case UR_SET_FEATURE: 2222 switch (UGETW(req->wValue)) { 2223 case UF_ENDPOINT_HALT: 2224 goto tr_handle_set_halt; 2225 case UF_DEVICE_REMOTE_WAKEUP: 2226 goto tr_handle_set_wakeup; 2227 default: 2228 goto tr_stalled; 2229 } 2230 break; 2231 case UR_SYNCH_FRAME: 2232 goto tr_valid; /* nop */ 2233 default: 2234 goto tr_stalled; 2235 } 2236 break; 2237 2238 case UT_READ_ENDPOINT: 2239 switch (req->bRequest) { 2240 case UR_GET_STATUS: 2241 goto tr_handle_get_ep_status; 2242 default: 2243 goto tr_stalled; 2244 } 2245 break; 2246 2247 case UT_WRITE_INTERFACE: 2248 switch (req->bRequest) { 2249 case UR_SET_INTERFACE: 2250 goto tr_handle_set_interface; 2251 case UR_CLEAR_FEATURE: 2252 goto tr_valid; /* nop */ 2253 case UR_SET_FEATURE: 2254 default: 2255 goto tr_stalled; 2256 } 2257 break; 2258 2259 case UT_READ_INTERFACE: 2260 switch (req->bRequest) { 2261 case UR_GET_INTERFACE: 2262 goto tr_handle_get_interface; 2263 case UR_GET_STATUS: 2264 goto tr_handle_get_iface_status; 2265 default: 2266 goto tr_stalled; 2267 } 2268 break; 2269 2270 case UT_WRITE_CLASS_INTERFACE: 2271 case UT_WRITE_VENDOR_INTERFACE: 2272 /* XXX forward */ 2273 break; 2274 2275 case UT_READ_CLASS_INTERFACE: 2276 case UT_READ_VENDOR_INTERFACE: 2277 /* XXX forward */ 2278 break; 2279 2280 case UT_WRITE_CLASS_DEVICE: 2281 switch (req->bRequest) { 2282 case UR_CLEAR_FEATURE: 2283 goto tr_valid; 2284 case UR_SET_DESCRIPTOR: 2285 case UR_SET_FEATURE: 2286 break; 2287 default: 2288 goto tr_stalled; 2289 } 2290 break; 2291 2292 case UT_WRITE_CLASS_OTHER: 2293 switch (req->bRequest) { 2294 case UR_CLEAR_FEATURE: 2295 goto tr_handle_clear_port_feature; 2296 case UR_SET_FEATURE: 2297 goto tr_handle_set_port_feature; 2298 case UR_CLEAR_TT_BUFFER: 2299 case UR_RESET_TT: 2300 case UR_STOP_TT: 2301 goto tr_valid; 2302 2303 default: 2304 goto tr_stalled; 2305 } 2306 break; 2307 2308 case UT_READ_CLASS_OTHER: 2309 switch (req->bRequest) { 2310 case UR_GET_TT_STATE: 2311 goto tr_handle_get_tt_state; 2312 case UR_GET_STATUS: 2313 goto tr_handle_get_port_status; 2314 default: 2315 goto tr_stalled; 2316 } 2317 break; 2318 2319 case UT_READ_CLASS_DEVICE: 2320 switch (req->bRequest) { 2321 case UR_GET_DESCRIPTOR: 2322 goto tr_handle_get_class_descriptor; 2323 case UR_GET_STATUS: 2324 goto tr_handle_get_class_status; 2325 2326 default: 2327 goto tr_stalled; 2328 } 2329 break; 2330 default: 2331 goto tr_stalled; 2332 } 2333 goto tr_valid; 2334 2335tr_handle_get_descriptor: 2336 switch (value >> 8) { 2337 case UDESC_DEVICE: 2338 if (value & 0xff) { 2339 goto tr_stalled; 2340 } 2341 len = sizeof(musbotg_devd); 2342 ptr = (const void *)&musbotg_devd; 2343 goto tr_valid; 2344 case UDESC_CONFIG: 2345 if (value & 0xff) { 2346 goto tr_stalled; 2347 } 2348 len = sizeof(musbotg_confd); 2349 ptr = (const void *)&musbotg_confd; 2350 goto tr_valid; 2351 case UDESC_STRING: 2352 switch (value & 0xff) { 2353 case 0: /* Language table */ 2354 len = sizeof(musbotg_langtab); 2355 ptr = (const void *)&musbotg_langtab; 2356 goto tr_valid; 2357 2358 case 1: /* Vendor */ 2359 len = sizeof(musbotg_vendor); 2360 ptr = (const void *)&musbotg_vendor; 2361 goto tr_valid; 2362 2363 case 2: /* Product */ 2364 len = sizeof(musbotg_product); 2365 ptr = (const void *)&musbotg_product; 2366 goto tr_valid; 2367 default: 2368 break; 2369 } 2370 break; 2371 default: 2372 goto tr_stalled; 2373 } 2374 goto tr_stalled; 2375 2376tr_handle_get_config: 2377 len = 1; 2378 sc->sc_hub_temp.wValue[0] = sc->sc_conf; 2379 goto tr_valid; 2380 2381tr_handle_get_status: 2382 len = 2; 2383 USETW(sc->sc_hub_temp.wValue, UDS_SELF_POWERED); 2384 goto tr_valid; 2385 2386tr_handle_set_address: 2387 if (value & 0xFF00) { 2388 goto tr_stalled; 2389 } 2390 sc->sc_rt_addr = value; 2391 goto tr_valid; 2392 2393tr_handle_set_config: 2394 if (value >= 2) { 2395 goto tr_stalled; 2396 } 2397 sc->sc_conf = value; 2398 goto tr_valid; 2399 2400tr_handle_get_interface: 2401 len = 1; 2402 sc->sc_hub_temp.wValue[0] = 0; 2403 goto tr_valid; 2404 2405tr_handle_get_tt_state: 2406tr_handle_get_class_status: 2407tr_handle_get_iface_status: 2408tr_handle_get_ep_status: 2409 len = 2; 2410 USETW(sc->sc_hub_temp.wValue, 0); 2411 goto tr_valid; 2412 2413tr_handle_set_halt: 2414tr_handle_set_interface: 2415tr_handle_set_wakeup: 2416tr_handle_clear_wakeup: 2417tr_handle_clear_halt: 2418 goto tr_valid; 2419 2420tr_handle_clear_port_feature: 2421 if (index != 1) { 2422 goto tr_stalled; 2423 } 2424 DPRINTFN(8, "UR_CLEAR_PORT_FEATURE on port %d\n", index); 2425 2426 switch (value) { 2427 case UHF_PORT_SUSPEND: 2428 musbotg_wakeup_peer(sc); 2429 break; 2430 2431 case UHF_PORT_ENABLE: 2432 sc->sc_flags.port_enabled = 0; 2433 break; 2434 2435 case UHF_PORT_TEST: 2436 case UHF_PORT_INDICATOR: 2437 case UHF_C_PORT_ENABLE: 2438 case UHF_C_PORT_OVER_CURRENT: 2439 case UHF_C_PORT_RESET: 2440 /* nops */ 2441 break; 2442 case UHF_PORT_POWER: 2443 sc->sc_flags.port_powered = 0; 2444 musbotg_pull_down(sc); 2445 musbotg_clocks_off(sc); 2446 break; 2447 case UHF_C_PORT_CONNECTION: 2448 sc->sc_flags.change_connect = 0; 2449 break; 2450 case UHF_C_PORT_SUSPEND: 2451 sc->sc_flags.change_suspend = 0; 2452 break; 2453 default: 2454 err = USB_ERR_IOERROR; 2455 goto done; 2456 } 2457 goto tr_valid; 2458 2459tr_handle_set_port_feature: 2460 if (index != 1) { 2461 goto tr_stalled; 2462 } 2463 DPRINTFN(8, "UR_SET_PORT_FEATURE\n"); 2464 2465 switch (value) { 2466 case UHF_PORT_ENABLE: 2467 sc->sc_flags.port_enabled = 1; 2468 break; 2469 case UHF_PORT_SUSPEND: 2470 case UHF_PORT_RESET: 2471 case UHF_PORT_TEST: 2472 case UHF_PORT_INDICATOR: 2473 /* nops */ 2474 break; 2475 case UHF_PORT_POWER: 2476 sc->sc_flags.port_powered = 1; 2477 break; 2478 default: 2479 err = USB_ERR_IOERROR; 2480 goto done; 2481 } 2482 goto tr_valid; 2483 2484tr_handle_get_port_status: 2485 2486 DPRINTFN(8, "UR_GET_PORT_STATUS\n"); 2487 2488 if (index != 1) { 2489 goto tr_stalled; 2490 } 2491 if (sc->sc_flags.status_vbus) { 2492 musbotg_clocks_on(sc); 2493 musbotg_pull_up(sc); 2494 } else { 2495 musbotg_pull_down(sc); 2496 musbotg_clocks_off(sc); 2497 } 2498 2499 /* Select Device Side Mode */ 2500 value = UPS_PORT_MODE_DEVICE; 2501 2502 if (sc->sc_flags.status_high_speed) { 2503 value |= UPS_HIGH_SPEED; 2504 } 2505 if (sc->sc_flags.port_powered) { 2506 value |= UPS_PORT_POWER; 2507 } 2508 if (sc->sc_flags.port_enabled) { 2509 value |= UPS_PORT_ENABLED; 2510 } 2511 if (sc->sc_flags.status_vbus && 2512 sc->sc_flags.status_bus_reset) { 2513 value |= UPS_CURRENT_CONNECT_STATUS; 2514 } 2515 if (sc->sc_flags.status_suspend) { 2516 value |= UPS_SUSPEND; 2517 } 2518 USETW(sc->sc_hub_temp.ps.wPortStatus, value); 2519 2520 value = 0; 2521 2522 if (sc->sc_flags.change_connect) { 2523 value |= UPS_C_CONNECT_STATUS; 2524 2525 if (sc->sc_flags.status_vbus && 2526 sc->sc_flags.status_bus_reset) { 2527 /* reset EP0 state */ 2528 sc->sc_ep0_busy = 0; 2529 sc->sc_ep0_cmd = 0; 2530 } 2531 } 2532 if (sc->sc_flags.change_suspend) { 2533 value |= UPS_C_SUSPEND; 2534 } 2535 USETW(sc->sc_hub_temp.ps.wPortChange, value); 2536 len = sizeof(sc->sc_hub_temp.ps); 2537 goto tr_valid; 2538 2539tr_handle_get_class_descriptor: 2540 if (value & 0xFF) { 2541 goto tr_stalled; 2542 } 2543 ptr = (const void *)&musbotg_hubd; 2544 len = sizeof(musbotg_hubd); 2545 goto tr_valid; 2546 2547tr_stalled: 2548 err = USB_ERR_STALLED; 2549tr_valid: 2550done: 2551 *plength = len; 2552 *pptr = ptr; 2553 return (err); 2554} 2555 2556static void 2557musbotg_xfer_setup(struct usb2_setup_params *parm) 2558{ 2559 const struct usb2_hw_ep_profile *pf; 2560 struct musbotg_softc *sc; 2561 struct usb2_xfer *xfer; 2562 void *last_obj; 2563 uint32_t ntd; 2564 uint32_t n; 2565 uint8_t ep_no; 2566 2567 sc = MUSBOTG_BUS2SC(parm->udev->bus); 2568 xfer = parm->curr_xfer; 2569 2570 /* 2571 * NOTE: This driver does not use any of the parameters that 2572 * are computed from the following values. Just set some 2573 * reasonable dummies: 2574 */ 2575 parm->hc_max_packet_size = 0x400; 2576 parm->hc_max_frame_size = 0x400; 2577 2578 if ((parm->methods == &musbotg_device_isoc_methods) || 2579 (parm->methods == &musbotg_device_intr_methods)) 2580 parm->hc_max_packet_count = 3; 2581 else 2582 parm->hc_max_packet_count = 1; 2583 2584 usb2_transfer_setup_sub(parm); 2585 2586 /* 2587 * compute maximum number of TDs 2588 */ 2589 if (parm->methods == &musbotg_device_ctrl_methods) { 2590 2591 ntd = xfer->nframes + 1 /* STATUS */ + 1 /* SYNC */ ; 2592 2593 } else if (parm->methods == &musbotg_device_bulk_methods) { 2594 2595 ntd = xfer->nframes + 1 /* SYNC */ ; 2596 2597 } else if (parm->methods == &musbotg_device_intr_methods) { 2598 2599 ntd = xfer->nframes + 1 /* SYNC */ ; 2600 2601 } else if (parm->methods == &musbotg_device_isoc_methods) { 2602 2603 ntd = xfer->nframes + 1 /* SYNC */ ; 2604 2605 } else { 2606 2607 ntd = 0; 2608 } 2609 2610 /* 2611 * check if "usb2_transfer_setup_sub" set an error 2612 */ 2613 if (parm->err) { 2614 return; 2615 } 2616 /* 2617 * allocate transfer descriptors 2618 */ 2619 last_obj = NULL; 2620 2621 /* 2622 * get profile stuff 2623 */ 2624 if (ntd) { 2625 2626 ep_no = xfer->endpoint & UE_ADDR; 2627 musbotg_get_hw_ep_profile(parm->udev, &pf, ep_no); 2628 2629 if (pf == NULL) { 2630 /* should not happen */ 2631 parm->err = USB_ERR_INVAL; 2632 return; 2633 } 2634 } else { 2635 ep_no = 0; 2636 pf = NULL; 2637 } 2638 2639 /* align data */ 2640 parm->size[0] += ((-parm->size[0]) & (USB_HOST_ALIGN - 1)); 2641 2642 for (n = 0; n != ntd; n++) { 2643 2644 struct musbotg_td *td; 2645 2646 if (parm->buf) { 2647 2648 td = USB_ADD_BYTES(parm->buf, parm->size[0]); 2649 2650 /* init TD */ 2651 td->max_frame_size = xfer->max_frame_size; 2652 td->ep_no = ep_no; 2653 td->obj_next = last_obj; 2654 2655 last_obj = td; 2656 } 2657 parm->size[0] += sizeof(*td); 2658 } 2659 2660 xfer->td_start[0] = last_obj; 2661} 2662 2663static void 2664musbotg_xfer_unsetup(struct usb2_xfer *xfer) 2665{ 2666 return; 2667} 2668 2669static void 2670musbotg_pipe_init(struct usb2_device *udev, struct usb2_endpoint_descriptor *edesc, 2671 struct usb2_pipe *pipe) 2672{ 2673 struct musbotg_softc *sc = MUSBOTG_BUS2SC(udev->bus); 2674 2675 DPRINTFN(2, "pipe=%p, addr=%d, endpt=%d, mode=%d (%d)\n", 2676 pipe, udev->address, 2677 edesc->bEndpointAddress, udev->flags.usb_mode, 2678 sc->sc_rt_addr); 2679 2680 if (udev->device_index != sc->sc_rt_addr) { 2681 2682 if (udev->flags.usb_mode != USB_MODE_DEVICE) { 2683 /* not supported */ 2684 return; 2685 } 2686 if ((udev->speed != USB_SPEED_FULL) && 2687 (udev->speed != USB_SPEED_HIGH)) { 2688 /* not supported */ 2689 return; 2690 } 2691 switch (edesc->bmAttributes & UE_XFERTYPE) { 2692 case UE_CONTROL: 2693 pipe->methods = &musbotg_device_ctrl_methods; 2694 break; 2695 case UE_INTERRUPT: 2696 pipe->methods = &musbotg_device_intr_methods; 2697 break; 2698 case UE_ISOCHRONOUS: 2699 pipe->methods = &musbotg_device_isoc_methods; 2700 break; 2701 case UE_BULK: 2702 pipe->methods = &musbotg_device_bulk_methods; 2703 break; 2704 default: 2705 /* do nothing */ 2706 break; 2707 } 2708 } 2709} 2710 2711struct usb2_bus_methods musbotg_bus_methods = 2712{ 2713 .pipe_init = &musbotg_pipe_init, 2714 .xfer_setup = &musbotg_xfer_setup, 2715 .xfer_unsetup = &musbotg_xfer_unsetup, 2716 .get_hw_ep_profile = &musbotg_get_hw_ep_profile, 2717 .set_stall = &musbotg_set_stall, 2718 .clear_stall = &musbotg_clear_stall, 2719 .roothub_exec = &musbotg_roothub_exec, 2720}; 2721