musb_otg.c revision 190738
1/* $FreeBSD: head/sys/dev/usb/controller/musb_otg.c 190738 2009-04-05 18:21:21Z thompsa $ */ 2/*- 3 * Copyright (c) 2008 Hans Petter Selasky. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27/* 28 * Thanks to Mentor Graphics for providing a reference driver for this 29 * USB chip at their homepage. 30 */ 31 32/* 33 * This file contains the driver for the Mentor Graphics Inventra USB 34 * 2.0 High Speed Dual-Role controller. 35 * 36 * NOTE: The current implementation only supports Device Side Mode! 37 */ 38 39#include <dev/usb/usb.h> 40#include <dev/usb/usb_mfunc.h> 41#include <dev/usb/usb_error.h> 42 43#define USB_DEBUG_VAR musbotgdebug 44 45#include <dev/usb/usb_core.h> 46#include <dev/usb/usb_debug.h> 47#include <dev/usb/usb_busdma.h> 48#include <dev/usb/usb_process.h> 49#include <dev/usb/usb_sw_transfer.h> 50#include <dev/usb/usb_transfer.h> 51#include <dev/usb/usb_device.h> 52#include <dev/usb/usb_hub.h> 53#include <dev/usb/usb_util.h> 54 55#include <dev/usb/usb_controller.h> 56#include <dev/usb/usb_bus.h> 57#include <dev/usb/controller/musb_otg.h> 58 59#define MUSBOTG_INTR_ENDPT 1 60 61#define MUSBOTG_BUS2SC(bus) \ 62 ((struct musbotg_softc *)(((uint8_t *)(bus)) - \ 63 USB_P2U(&(((struct musbotg_softc *)0)->sc_bus)))) 64 65#define MUSBOTG_PC2SC(pc) \ 66 MUSBOTG_BUS2SC(USB_DMATAG_TO_XROOT((pc)->tag_parent)->bus) 67 68#if USB_DEBUG 69static int musbotgdebug = 0; 70 71SYSCTL_NODE(_hw_usb2, OID_AUTO, musbotg, CTLFLAG_RW, 0, "USB musbotg"); 72SYSCTL_INT(_hw_usb2_musbotg, OID_AUTO, debug, CTLFLAG_RW, 73 &musbotgdebug, 0, "Debug level"); 74#endif 75 76/* prototypes */ 77 78struct usb2_bus_methods musbotg_bus_methods; 79struct usb2_pipe_methods musbotg_device_bulk_methods; 80struct usb2_pipe_methods musbotg_device_ctrl_methods; 81struct usb2_pipe_methods musbotg_device_intr_methods; 82struct usb2_pipe_methods musbotg_device_isoc_methods; 83 84static musbotg_cmd_t musbotg_setup_rx; 85static musbotg_cmd_t musbotg_setup_data_rx; 86static musbotg_cmd_t musbotg_setup_data_tx; 87static musbotg_cmd_t musbotg_setup_status; 88static musbotg_cmd_t musbotg_data_rx; 89static musbotg_cmd_t musbotg_data_tx; 90static void musbotg_device_done(struct usb2_xfer *, usb2_error_t); 91static void musbotg_do_poll(struct usb2_bus *); 92static void musbotg_standard_done(struct usb2_xfer *); 93static void musbotg_interrupt_poll(struct musbotg_softc *); 94static void musbotg_root_intr(struct musbotg_softc *); 95 96/* 97 * Here is a configuration that the chip supports. 98 */ 99static const struct usb2_hw_ep_profile musbotg_ep_profile[1] = { 100 101 [0] = { 102 .max_in_frame_size = 64,/* fixed */ 103 .max_out_frame_size = 64, /* fixed */ 104 .is_simplex = 1, 105 .support_control = 1, 106 } 107}; 108 109static void 110musbotg_get_hw_ep_profile(struct usb2_device *udev, 111 const struct usb2_hw_ep_profile **ppf, uint8_t ep_addr) 112{ 113 struct musbotg_softc *sc; 114 115 sc = MUSBOTG_BUS2SC(udev->bus); 116 117 if (ep_addr == 0) { 118 /* control endpoint */ 119 *ppf = musbotg_ep_profile; 120 } else if (ep_addr <= sc->sc_ep_max) { 121 /* other endpoints */ 122 *ppf = sc->sc_hw_ep_profile + ep_addr; 123 } else { 124 *ppf = NULL; 125 } 126} 127 128static void 129musbotg_clocks_on(struct musbotg_softc *sc) 130{ 131 if (sc->sc_flags.clocks_off && 132 sc->sc_flags.port_powered) { 133 134 DPRINTFN(4, "\n"); 135 136 if (sc->sc_clocks_on) { 137 (sc->sc_clocks_on) (sc->sc_clocks_arg); 138 } 139 sc->sc_flags.clocks_off = 0; 140 141 /* XXX enable Transceiver */ 142 } 143} 144 145static void 146musbotg_clocks_off(struct musbotg_softc *sc) 147{ 148 if (!sc->sc_flags.clocks_off) { 149 150 DPRINTFN(4, "\n"); 151 152 /* XXX disable Transceiver */ 153 154 if (sc->sc_clocks_off) { 155 (sc->sc_clocks_off) (sc->sc_clocks_arg); 156 } 157 sc->sc_flags.clocks_off = 1; 158 } 159} 160 161static void 162musbotg_pull_common(struct musbotg_softc *sc, uint8_t on) 163{ 164 uint8_t temp; 165 166 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER); 167 if (on) 168 temp |= MUSB2_MASK_SOFTC; 169 else 170 temp &= ~MUSB2_MASK_SOFTC; 171 172 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp); 173} 174 175static void 176musbotg_pull_up(struct musbotg_softc *sc) 177{ 178 /* pullup D+, if possible */ 179 180 if (!sc->sc_flags.d_pulled_up && 181 sc->sc_flags.port_powered) { 182 sc->sc_flags.d_pulled_up = 1; 183 musbotg_pull_common(sc, 1); 184 } 185} 186 187static void 188musbotg_pull_down(struct musbotg_softc *sc) 189{ 190 /* pulldown D+, if possible */ 191 192 if (sc->sc_flags.d_pulled_up) { 193 sc->sc_flags.d_pulled_up = 0; 194 musbotg_pull_common(sc, 0); 195 } 196} 197 198static void 199musbotg_wakeup_peer(struct musbotg_softc *sc) 200{ 201 uint8_t temp; 202 203 if (!(sc->sc_flags.status_suspend)) { 204 return; 205 } 206 207 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER); 208 temp |= MUSB2_MASK_RESUME; 209 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp); 210 211 /* wait 8 milliseconds */ 212 /* Wait for reset to complete. */ 213 usb2_pause_mtx(&sc->sc_bus.bus_mtx, hz / 125); 214 215 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER); 216 temp &= ~MUSB2_MASK_RESUME; 217 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp); 218} 219 220static void 221musbotg_set_address(struct musbotg_softc *sc, uint8_t addr) 222{ 223 DPRINTFN(4, "addr=%d\n", addr); 224 addr &= 0x7F; 225 MUSB2_WRITE_1(sc, MUSB2_REG_FADDR, addr); 226} 227 228static uint8_t 229musbotg_setup_rx(struct musbotg_td *td) 230{ 231 struct musbotg_softc *sc; 232 struct usb2_device_request req; 233 uint16_t count; 234 uint8_t csr; 235 236 /* get pointer to softc */ 237 sc = MUSBOTG_PC2SC(td->pc); 238 239 /* select endpoint 0 */ 240 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); 241 242 /* read out FIFO status */ 243 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 244 245 DPRINTFN(4, "csr=0x%02x\n", csr); 246 247 /* 248 * NOTE: If DATAEND is set we should not call the 249 * callback, hence the status stage is not complete. 250 */ 251 if (csr & MUSB2_MASK_CSR0L_DATAEND) { 252 /* do not stall at this point */ 253 td->did_stall = 1; 254 /* wait for interrupt */ 255 goto not_complete; 256 } 257 if (csr & MUSB2_MASK_CSR0L_SENTSTALL) { 258 /* clear SENTSTALL */ 259 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0); 260 /* get latest status */ 261 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 262 /* update EP0 state */ 263 sc->sc_ep0_busy = 0; 264 } 265 if (csr & MUSB2_MASK_CSR0L_SETUPEND) { 266 /* clear SETUPEND */ 267 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 268 MUSB2_MASK_CSR0L_SETUPEND_CLR); 269 /* get latest status */ 270 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 271 /* update EP0 state */ 272 sc->sc_ep0_busy = 0; 273 } 274 if (sc->sc_ep0_busy) { 275 goto not_complete; 276 } 277 if (!(csr & MUSB2_MASK_CSR0L_RXPKTRDY)) { 278 goto not_complete; 279 } 280 /* clear did stall flag */ 281 td->did_stall = 0; 282 /* get the packet byte count */ 283 count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT); 284 285 /* verify data length */ 286 if (count != td->remainder) { 287 DPRINTFN(0, "Invalid SETUP packet " 288 "length, %d bytes\n", count); 289 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 290 MUSB2_MASK_CSR0L_RXPKTRDY_CLR); 291 goto not_complete; 292 } 293 if (count != sizeof(req)) { 294 DPRINTFN(0, "Unsupported SETUP packet " 295 "length, %d bytes\n", count); 296 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 297 MUSB2_MASK_CSR0L_RXPKTRDY_CLR); 298 goto not_complete; 299 } 300 /* receive data */ 301 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 302 MUSB2_REG_EPFIFO(0), (void *)&req, sizeof(req)); 303 304 /* copy data into real buffer */ 305 usb2_copy_in(td->pc, 0, &req, sizeof(req)); 306 307 td->offset = sizeof(req); 308 td->remainder = 0; 309 310 /* set pending command */ 311 sc->sc_ep0_cmd = MUSB2_MASK_CSR0L_RXPKTRDY_CLR; 312 313 /* we need set stall or dataend after this */ 314 sc->sc_ep0_busy = 1; 315 316 /* sneak peek the set address */ 317 if ((req.bmRequestType == UT_WRITE_DEVICE) && 318 (req.bRequest == UR_SET_ADDRESS)) { 319 sc->sc_dv_addr = req.wValue[0] & 0x7F; 320 } else { 321 sc->sc_dv_addr = 0xFF; 322 } 323 return (0); /* complete */ 324 325not_complete: 326 /* abort any ongoing transfer */ 327 if (!td->did_stall) { 328 DPRINTFN(4, "stalling\n"); 329 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 330 MUSB2_MASK_CSR0L_SENDSTALL); 331 td->did_stall = 1; 332 } 333 return (1); /* not complete */ 334} 335 336/* Control endpoint only data handling functions (RX/TX/SYNC) */ 337 338static uint8_t 339musbotg_setup_data_rx(struct musbotg_td *td) 340{ 341 struct usb2_page_search buf_res; 342 struct musbotg_softc *sc; 343 uint16_t count; 344 uint8_t csr; 345 uint8_t got_short; 346 347 /* get pointer to softc */ 348 sc = MUSBOTG_PC2SC(td->pc); 349 350 /* select endpoint 0 */ 351 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); 352 353 /* check if a command is pending */ 354 if (sc->sc_ep0_cmd) { 355 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, sc->sc_ep0_cmd); 356 sc->sc_ep0_cmd = 0; 357 } 358 /* read out FIFO status */ 359 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 360 361 DPRINTFN(4, "csr=0x%02x\n", csr); 362 363 got_short = 0; 364 365 if (csr & (MUSB2_MASK_CSR0L_SETUPEND | 366 MUSB2_MASK_CSR0L_SENTSTALL)) { 367 if (td->remainder == 0) { 368 /* 369 * We are actually complete and have 370 * received the next SETUP 371 */ 372 DPRINTFN(4, "faking complete\n"); 373 return (0); /* complete */ 374 } 375 /* 376 * USB Host Aborted the transfer. 377 */ 378 td->error = 1; 379 return (0); /* complete */ 380 } 381 if (!(csr & MUSB2_MASK_CSR0L_RXPKTRDY)) { 382 return (1); /* not complete */ 383 } 384 /* get the packet byte count */ 385 count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT); 386 387 /* verify the packet byte count */ 388 if (count != td->max_frame_size) { 389 if (count < td->max_frame_size) { 390 /* we have a short packet */ 391 td->short_pkt = 1; 392 got_short = 1; 393 } else { 394 /* invalid USB packet */ 395 td->error = 1; 396 return (0); /* we are complete */ 397 } 398 } 399 /* verify the packet byte count */ 400 if (count > td->remainder) { 401 /* invalid USB packet */ 402 td->error = 1; 403 return (0); /* we are complete */ 404 } 405 while (count > 0) { 406 uint32_t temp; 407 408 usb2_get_page(td->pc, td->offset, &buf_res); 409 410 /* get correct length */ 411 if (buf_res.length > count) { 412 buf_res.length = count; 413 } 414 /* check for unaligned memory address */ 415 if (USB_P2U(buf_res.buffer) & 3) { 416 417 temp = count & ~3; 418 419 if (temp) { 420 /* receive data 4 bytes at a time */ 421 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 422 MUSB2_REG_EPFIFO(0), sc->sc_bounce_buf, 423 temp / 4); 424 } 425 temp = count & 3; 426 if (temp) { 427 /* receive data 1 byte at a time */ 428 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 429 MUSB2_REG_EPFIFO(0), 430 (void *)(&sc->sc_bounce_buf[count / 4]), temp); 431 } 432 usb2_copy_in(td->pc, td->offset, 433 sc->sc_bounce_buf, count); 434 435 /* update offset and remainder */ 436 td->offset += count; 437 td->remainder -= count; 438 break; 439 } 440 /* check if we can optimise */ 441 if (buf_res.length >= 4) { 442 443 /* receive data 4 bytes at a time */ 444 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 445 MUSB2_REG_EPFIFO(0), buf_res.buffer, 446 buf_res.length / 4); 447 448 temp = buf_res.length & ~3; 449 450 /* update counters */ 451 count -= temp; 452 td->offset += temp; 453 td->remainder -= temp; 454 continue; 455 } 456 /* receive data */ 457 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 458 MUSB2_REG_EPFIFO(0), buf_res.buffer, buf_res.length); 459 460 /* update counters */ 461 count -= buf_res.length; 462 td->offset += buf_res.length; 463 td->remainder -= buf_res.length; 464 } 465 466 /* check if we are complete */ 467 if ((td->remainder == 0) || got_short) { 468 if (td->short_pkt) { 469 /* we are complete */ 470 sc->sc_ep0_cmd = MUSB2_MASK_CSR0L_RXPKTRDY_CLR; 471 return (0); 472 } 473 /* else need to receive a zero length packet */ 474 } 475 /* write command - need more data */ 476 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 477 MUSB2_MASK_CSR0L_RXPKTRDY_CLR); 478 return (1); /* not complete */ 479} 480 481static uint8_t 482musbotg_setup_data_tx(struct musbotg_td *td) 483{ 484 struct usb2_page_search buf_res; 485 struct musbotg_softc *sc; 486 uint16_t count; 487 uint8_t csr; 488 489 /* get pointer to softc */ 490 sc = MUSBOTG_PC2SC(td->pc); 491 492 /* select endpoint 0 */ 493 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); 494 495 /* check if a command is pending */ 496 if (sc->sc_ep0_cmd) { 497 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, sc->sc_ep0_cmd); 498 sc->sc_ep0_cmd = 0; 499 } 500 /* read out FIFO status */ 501 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 502 503 DPRINTFN(4, "csr=0x%02x\n", csr); 504 505 if (csr & (MUSB2_MASK_CSR0L_SETUPEND | 506 MUSB2_MASK_CSR0L_SENTSTALL)) { 507 /* 508 * The current transfer was aborted 509 * by the USB Host 510 */ 511 td->error = 1; 512 return (0); /* complete */ 513 } 514 if (csr & MUSB2_MASK_CSR0L_TXPKTRDY) { 515 return (1); /* not complete */ 516 } 517 count = td->max_frame_size; 518 if (td->remainder < count) { 519 /* we have a short packet */ 520 td->short_pkt = 1; 521 count = td->remainder; 522 } 523 while (count > 0) { 524 uint32_t temp; 525 526 usb2_get_page(td->pc, td->offset, &buf_res); 527 528 /* get correct length */ 529 if (buf_res.length > count) { 530 buf_res.length = count; 531 } 532 /* check for unaligned memory address */ 533 if (USB_P2U(buf_res.buffer) & 3) { 534 535 usb2_copy_out(td->pc, td->offset, 536 sc->sc_bounce_buf, count); 537 538 temp = count & ~3; 539 540 if (temp) { 541 /* transmit data 4 bytes at a time */ 542 bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 543 MUSB2_REG_EPFIFO(0), sc->sc_bounce_buf, 544 temp / 4); 545 } 546 temp = count & 3; 547 if (temp) { 548 /* receive data 1 byte at a time */ 549 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 550 MUSB2_REG_EPFIFO(0), 551 ((void *)&sc->sc_bounce_buf[count / 4]), temp); 552 } 553 /* update offset and remainder */ 554 td->offset += count; 555 td->remainder -= count; 556 break; 557 } 558 /* check if we can optimise */ 559 if (buf_res.length >= 4) { 560 561 /* transmit data 4 bytes at a time */ 562 bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 563 MUSB2_REG_EPFIFO(0), buf_res.buffer, 564 buf_res.length / 4); 565 566 temp = buf_res.length & ~3; 567 568 /* update counters */ 569 count -= temp; 570 td->offset += temp; 571 td->remainder -= temp; 572 continue; 573 } 574 /* transmit data */ 575 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 576 MUSB2_REG_EPFIFO(0), buf_res.buffer, buf_res.length); 577 578 /* update counters */ 579 count -= buf_res.length; 580 td->offset += buf_res.length; 581 td->remainder -= buf_res.length; 582 } 583 584 /* check remainder */ 585 if (td->remainder == 0) { 586 if (td->short_pkt) { 587 sc->sc_ep0_cmd = MUSB2_MASK_CSR0L_TXPKTRDY; 588 return (0); /* complete */ 589 } 590 /* else we need to transmit a short packet */ 591 } 592 /* write command */ 593 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 594 MUSB2_MASK_CSR0L_TXPKTRDY); 595 596 return (1); /* not complete */ 597} 598 599static uint8_t 600musbotg_setup_status(struct musbotg_td *td) 601{ 602 struct musbotg_softc *sc; 603 uint8_t csr; 604 605 /* get pointer to softc */ 606 sc = MUSBOTG_PC2SC(td->pc); 607 608 /* select endpoint 0 */ 609 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); 610 611 if (sc->sc_ep0_busy) { 612 sc->sc_ep0_busy = 0; 613 sc->sc_ep0_cmd |= MUSB2_MASK_CSR0L_DATAEND; 614 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, sc->sc_ep0_cmd); 615 sc->sc_ep0_cmd = 0; 616 } 617 /* read out FIFO status */ 618 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 619 620 DPRINTFN(4, "csr=0x%02x\n", csr); 621 622 if (csr & MUSB2_MASK_CSR0L_DATAEND) { 623 /* wait for interrupt */ 624 return (1); /* not complete */ 625 } 626 if (sc->sc_dv_addr != 0xFF) { 627 /* write function address */ 628 musbotg_set_address(sc, sc->sc_dv_addr); 629 } 630 return (0); /* complete */ 631} 632 633static uint8_t 634musbotg_data_rx(struct musbotg_td *td) 635{ 636 struct usb2_page_search buf_res; 637 struct musbotg_softc *sc; 638 uint16_t count; 639 uint8_t csr; 640 uint8_t to; 641 uint8_t got_short; 642 643 to = 8; /* don't loop forever! */ 644 got_short = 0; 645 646 /* get pointer to softc */ 647 sc = MUSBOTG_PC2SC(td->pc); 648 649 /* select endpoint */ 650 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, td->ep_no); 651 652repeat: 653 /* read out FIFO status */ 654 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL); 655 656 DPRINTFN(4, "csr=0x%02x\n", csr); 657 658 /* clear overrun */ 659 if (csr & MUSB2_MASK_CSRL_RXOVERRUN) { 660 /* make sure we don't clear "RXPKTRDY" */ 661 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 662 MUSB2_MASK_CSRL_RXPKTRDY); 663 } 664 /* check status */ 665 if (!(csr & MUSB2_MASK_CSRL_RXPKTRDY)) { 666 return (1); /* not complete */ 667 } 668 /* get the packet byte count */ 669 count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT); 670 671 DPRINTFN(4, "count=0x%04x\n", count); 672 673 /* 674 * Check for short or invalid packet: 675 */ 676 if (count != td->max_frame_size) { 677 if (count < td->max_frame_size) { 678 /* we have a short packet */ 679 td->short_pkt = 1; 680 got_short = 1; 681 } else { 682 /* invalid USB packet */ 683 td->error = 1; 684 return (0); /* we are complete */ 685 } 686 } 687 /* verify the packet byte count */ 688 if (count > td->remainder) { 689 /* invalid USB packet */ 690 td->error = 1; 691 return (0); /* we are complete */ 692 } 693 while (count > 0) { 694 uint32_t temp; 695 696 usb2_get_page(td->pc, td->offset, &buf_res); 697 698 /* get correct length */ 699 if (buf_res.length > count) { 700 buf_res.length = count; 701 } 702 /* check for unaligned memory address */ 703 if (USB_P2U(buf_res.buffer) & 3) { 704 705 temp = count & ~3; 706 707 if (temp) { 708 /* receive data 4 bytes at a time */ 709 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 710 MUSB2_REG_EPFIFO(td->ep_no), sc->sc_bounce_buf, 711 temp / 4); 712 } 713 temp = count & 3; 714 if (temp) { 715 /* receive data 1 byte at a time */ 716 bus_space_read_multi_1(sc->sc_io_tag, 717 sc->sc_io_hdl, MUSB2_REG_EPFIFO(td->ep_no), 718 ((void *)&sc->sc_bounce_buf[count / 4]), temp); 719 } 720 usb2_copy_in(td->pc, td->offset, 721 sc->sc_bounce_buf, count); 722 723 /* update offset and remainder */ 724 td->offset += count; 725 td->remainder -= count; 726 break; 727 } 728 /* check if we can optimise */ 729 if (buf_res.length >= 4) { 730 731 /* receive data 4 bytes at a time */ 732 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 733 MUSB2_REG_EPFIFO(td->ep_no), buf_res.buffer, 734 buf_res.length / 4); 735 736 temp = buf_res.length & ~3; 737 738 /* update counters */ 739 count -= temp; 740 td->offset += temp; 741 td->remainder -= temp; 742 continue; 743 } 744 /* receive data */ 745 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 746 MUSB2_REG_EPFIFO(td->ep_no), buf_res.buffer, 747 buf_res.length); 748 749 /* update counters */ 750 count -= buf_res.length; 751 td->offset += buf_res.length; 752 td->remainder -= buf_res.length; 753 } 754 755 /* clear status bits */ 756 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 0); 757 758 /* check if we are complete */ 759 if ((td->remainder == 0) || got_short) { 760 if (td->short_pkt) { 761 /* we are complete */ 762 return (0); 763 } 764 /* else need to receive a zero length packet */ 765 } 766 if (--to) { 767 goto repeat; 768 } 769 return (1); /* not complete */ 770} 771 772static uint8_t 773musbotg_data_tx(struct musbotg_td *td) 774{ 775 struct usb2_page_search buf_res; 776 struct musbotg_softc *sc; 777 uint16_t count; 778 uint8_t csr; 779 uint8_t to; 780 781 to = 8; /* don't loop forever! */ 782 783 /* get pointer to softc */ 784 sc = MUSBOTG_PC2SC(td->pc); 785 786 /* select endpoint */ 787 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, td->ep_no); 788 789repeat: 790 791 /* read out FIFO status */ 792 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 793 794 DPRINTFN(4, "csr=0x%02x\n", csr); 795 796 if (csr & (MUSB2_MASK_CSRL_TXINCOMP | 797 MUSB2_MASK_CSRL_TXUNDERRUN)) { 798 /* clear status bits */ 799 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0); 800 } 801 if (csr & MUSB2_MASK_CSRL_TXPKTRDY) { 802 return (1); /* not complete */ 803 } 804 /* check for short packet */ 805 count = td->max_frame_size; 806 if (td->remainder < count) { 807 /* we have a short packet */ 808 td->short_pkt = 1; 809 count = td->remainder; 810 } 811 while (count > 0) { 812 uint32_t temp; 813 814 usb2_get_page(td->pc, td->offset, &buf_res); 815 816 /* get correct length */ 817 if (buf_res.length > count) { 818 buf_res.length = count; 819 } 820 /* check for unaligned memory address */ 821 if (USB_P2U(buf_res.buffer) & 3) { 822 823 usb2_copy_out(td->pc, td->offset, 824 sc->sc_bounce_buf, count); 825 826 temp = count & ~3; 827 828 if (temp) { 829 /* transmit data 4 bytes at a time */ 830 bus_space_write_multi_4(sc->sc_io_tag, 831 sc->sc_io_hdl, MUSB2_REG_EPFIFO(td->ep_no), 832 sc->sc_bounce_buf, temp / 4); 833 } 834 temp = count & 3; 835 if (temp) { 836 /* receive data 1 byte at a time */ 837 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 838 MUSB2_REG_EPFIFO(td->ep_no), 839 ((void *)&sc->sc_bounce_buf[count / 4]), temp); 840 } 841 /* update offset and remainder */ 842 td->offset += count; 843 td->remainder -= count; 844 break; 845 } 846 /* check if we can optimise */ 847 if (buf_res.length >= 4) { 848 849 /* transmit data 4 bytes at a time */ 850 bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 851 MUSB2_REG_EPFIFO(td->ep_no), buf_res.buffer, 852 buf_res.length / 4); 853 854 temp = buf_res.length & ~3; 855 856 /* update counters */ 857 count -= temp; 858 td->offset += temp; 859 td->remainder -= temp; 860 continue; 861 } 862 /* transmit data */ 863 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 864 MUSB2_REG_EPFIFO(td->ep_no), buf_res.buffer, 865 buf_res.length); 866 867 /* update counters */ 868 count -= buf_res.length; 869 td->offset += buf_res.length; 870 td->remainder -= buf_res.length; 871 } 872 873 /* write command */ 874 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 875 MUSB2_MASK_CSRL_TXPKTRDY); 876 877 /* check remainder */ 878 if (td->remainder == 0) { 879 if (td->short_pkt) { 880 return (0); /* complete */ 881 } 882 /* else we need to transmit a short packet */ 883 } 884 if (--to) { 885 goto repeat; 886 } 887 return (1); /* not complete */ 888} 889 890static uint8_t 891musbotg_xfer_do_fifo(struct usb2_xfer *xfer) 892{ 893 struct musbotg_softc *sc; 894 struct musbotg_td *td; 895 896 DPRINTFN(8, "\n"); 897 898 td = xfer->td_transfer_cache; 899 while (1) { 900 if ((td->func) (td)) { 901 /* operation in progress */ 902 break; 903 } 904 if (((void *)td) == xfer->td_transfer_last) { 905 goto done; 906 } 907 if (td->error) { 908 goto done; 909 } else if (td->remainder > 0) { 910 /* 911 * We had a short transfer. If there is no alternate 912 * next, stop processing ! 913 */ 914 if (!td->alt_next) { 915 goto done; 916 } 917 } 918 /* 919 * Fetch the next transfer descriptor and transfer 920 * some flags to the next transfer descriptor 921 */ 922 td = td->obj_next; 923 xfer->td_transfer_cache = td; 924 } 925 return (1); /* not complete */ 926 927done: 928 sc = MUSBOTG_BUS2SC(xfer->xroot->bus); 929 930 /* compute all actual lengths */ 931 932 musbotg_standard_done(xfer); 933 934 return (0); /* complete */ 935} 936 937static void 938musbotg_interrupt_poll(struct musbotg_softc *sc) 939{ 940 struct usb2_xfer *xfer; 941 942repeat: 943 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 944 if (!musbotg_xfer_do_fifo(xfer)) { 945 /* queue has been modified */ 946 goto repeat; 947 } 948 } 949} 950 951void 952musbotg_vbus_interrupt(struct musbotg_softc *sc, uint8_t is_on) 953{ 954 DPRINTFN(4, "vbus = %u\n", is_on); 955 956 USB_BUS_LOCK(&sc->sc_bus); 957 if (is_on) { 958 if (!sc->sc_flags.status_vbus) { 959 sc->sc_flags.status_vbus = 1; 960 961 /* complete root HUB interrupt endpoint */ 962 musbotg_root_intr(sc); 963 } 964 } else { 965 if (sc->sc_flags.status_vbus) { 966 sc->sc_flags.status_vbus = 0; 967 sc->sc_flags.status_bus_reset = 0; 968 sc->sc_flags.status_suspend = 0; 969 sc->sc_flags.change_suspend = 0; 970 sc->sc_flags.change_connect = 1; 971 972 /* complete root HUB interrupt endpoint */ 973 musbotg_root_intr(sc); 974 } 975 } 976 977 USB_BUS_UNLOCK(&sc->sc_bus); 978} 979 980void 981musbotg_interrupt(struct musbotg_softc *sc) 982{ 983 uint16_t rx_status; 984 uint16_t tx_status; 985 uint8_t usb_status; 986 uint8_t temp; 987 uint8_t to = 2; 988 989 USB_BUS_LOCK(&sc->sc_bus); 990 991repeat: 992 993 /* read all interrupt registers */ 994 usb_status = MUSB2_READ_1(sc, MUSB2_REG_INTUSB); 995 996 /* read all FIFO interrupts */ 997 rx_status = MUSB2_READ_2(sc, MUSB2_REG_INTRX); 998 tx_status = MUSB2_READ_2(sc, MUSB2_REG_INTTX); 999 1000 /* check for any bus state change interrupts */ 1001 1002 if (usb_status & (MUSB2_MASK_IRESET | 1003 MUSB2_MASK_IRESUME | MUSB2_MASK_ISUSP)) { 1004 1005 DPRINTFN(4, "real bus interrupt 0x%08x\n", usb_status); 1006 1007 if (usb_status & MUSB2_MASK_IRESET) { 1008 1009 /* set correct state */ 1010 sc->sc_flags.status_bus_reset = 1; 1011 sc->sc_flags.status_suspend = 0; 1012 sc->sc_flags.change_suspend = 0; 1013 sc->sc_flags.change_connect = 1; 1014 1015 /* determine line speed */ 1016 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER); 1017 if (temp & MUSB2_MASK_HSMODE) 1018 sc->sc_flags.status_high_speed = 1; 1019 else 1020 sc->sc_flags.status_high_speed = 0; 1021 1022 /* 1023 * After reset all interrupts are on and we need to 1024 * turn them off! 1025 */ 1026 temp = MUSB2_MASK_IRESET; 1027 /* disable resume interrupt */ 1028 temp &= ~MUSB2_MASK_IRESUME; 1029 /* enable suspend interrupt */ 1030 temp |= MUSB2_MASK_ISUSP; 1031 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, temp); 1032 /* disable TX and RX interrupts */ 1033 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, 0); 1034 MUSB2_WRITE_2(sc, MUSB2_REG_INTRXE, 0); 1035 } 1036 /* 1037 * If RXRSM and RXSUSP is set at the same time we interpret 1038 * that like RESUME. Resume is set when there is at least 3 1039 * milliseconds of inactivity on the USB BUS. 1040 */ 1041 if (usb_status & MUSB2_MASK_IRESUME) { 1042 if (sc->sc_flags.status_suspend) { 1043 sc->sc_flags.status_suspend = 0; 1044 sc->sc_flags.change_suspend = 1; 1045 1046 temp = MUSB2_READ_1(sc, MUSB2_REG_INTUSBE); 1047 /* disable resume interrupt */ 1048 temp &= ~MUSB2_MASK_IRESUME; 1049 /* enable suspend interrupt */ 1050 temp |= MUSB2_MASK_ISUSP; 1051 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, temp); 1052 } 1053 } else if (usb_status & MUSB2_MASK_ISUSP) { 1054 if (!sc->sc_flags.status_suspend) { 1055 sc->sc_flags.status_suspend = 1; 1056 sc->sc_flags.change_suspend = 1; 1057 1058 temp = MUSB2_READ_1(sc, MUSB2_REG_INTUSBE); 1059 /* disable suspend interrupt */ 1060 temp &= ~MUSB2_MASK_ISUSP; 1061 /* enable resume interrupt */ 1062 temp |= MUSB2_MASK_IRESUME; 1063 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, temp); 1064 } 1065 } 1066 /* complete root HUB interrupt endpoint */ 1067 musbotg_root_intr(sc); 1068 } 1069 /* check for any endpoint interrupts */ 1070 1071 if (rx_status || tx_status) { 1072 DPRINTFN(4, "real endpoint interrupt " 1073 "rx=0x%04x, tx=0x%04x\n", rx_status, tx_status); 1074 } 1075 /* poll one time regardless of FIFO status */ 1076 1077 musbotg_interrupt_poll(sc); 1078 1079 if (--to) 1080 goto repeat; 1081 1082 USB_BUS_UNLOCK(&sc->sc_bus); 1083} 1084 1085static void 1086musbotg_setup_standard_chain_sub(struct musbotg_std_temp *temp) 1087{ 1088 struct musbotg_td *td; 1089 1090 /* get current Transfer Descriptor */ 1091 td = temp->td_next; 1092 temp->td = td; 1093 1094 /* prepare for next TD */ 1095 temp->td_next = td->obj_next; 1096 1097 /* fill out the Transfer Descriptor */ 1098 td->func = temp->func; 1099 td->pc = temp->pc; 1100 td->offset = temp->offset; 1101 td->remainder = temp->len; 1102 td->error = 0; 1103 td->did_stall = 0; 1104 td->short_pkt = temp->short_pkt; 1105 td->alt_next = temp->setup_alt_next; 1106} 1107 1108static void 1109musbotg_setup_standard_chain(struct usb2_xfer *xfer) 1110{ 1111 struct musbotg_std_temp temp; 1112 struct musbotg_softc *sc; 1113 struct musbotg_td *td; 1114 uint32_t x; 1115 uint8_t ep_no; 1116 1117 DPRINTFN(8, "addr=%d endpt=%d sumlen=%d speed=%d\n", 1118 xfer->address, UE_GET_ADDR(xfer->endpoint), 1119 xfer->sumlen, usb2_get_speed(xfer->xroot->udev)); 1120 1121 temp.max_frame_size = xfer->max_frame_size; 1122 1123 td = xfer->td_start[0]; 1124 xfer->td_transfer_first = td; 1125 xfer->td_transfer_cache = td; 1126 1127 /* setup temp */ 1128 1129 temp.td = NULL; 1130 temp.td_next = xfer->td_start[0]; 1131 temp.offset = 0; 1132 temp.setup_alt_next = xfer->flags_int.short_frames_ok; 1133 1134 sc = MUSBOTG_BUS2SC(xfer->xroot->bus); 1135 ep_no = (xfer->endpoint & UE_ADDR); 1136 1137 /* check if we should prepend a setup message */ 1138 1139 if (xfer->flags_int.control_xfr) { 1140 if (xfer->flags_int.control_hdr) { 1141 1142 temp.func = &musbotg_setup_rx; 1143 temp.len = xfer->frlengths[0]; 1144 temp.pc = xfer->frbuffers + 0; 1145 temp.short_pkt = temp.len ? 1 : 0; 1146 1147 musbotg_setup_standard_chain_sub(&temp); 1148 } 1149 x = 1; 1150 } else { 1151 x = 0; 1152 } 1153 1154 if (x != xfer->nframes) { 1155 if (xfer->endpoint & UE_DIR_IN) { 1156 if (xfer->flags_int.control_xfr) 1157 temp.func = &musbotg_setup_data_tx; 1158 else 1159 temp.func = &musbotg_data_tx; 1160 } else { 1161 if (xfer->flags_int.control_xfr) 1162 temp.func = &musbotg_setup_data_rx; 1163 else 1164 temp.func = &musbotg_data_rx; 1165 } 1166 1167 /* setup "pc" pointer */ 1168 temp.pc = xfer->frbuffers + x; 1169 } 1170 while (x != xfer->nframes) { 1171 1172 /* DATA0 / DATA1 message */ 1173 1174 temp.len = xfer->frlengths[x]; 1175 1176 x++; 1177 1178 if (x == xfer->nframes) { 1179 if (xfer->flags_int.control_xfr) { 1180 if (xfer->flags_int.control_act) { 1181 temp.setup_alt_next = 0; 1182 } 1183 } else { 1184 temp.setup_alt_next = 0; 1185 } 1186 } 1187 if (temp.len == 0) { 1188 1189 /* make sure that we send an USB packet */ 1190 1191 temp.short_pkt = 0; 1192 1193 } else { 1194 1195 /* regular data transfer */ 1196 1197 temp.short_pkt = (xfer->flags.force_short_xfer) ? 0 : 1; 1198 } 1199 1200 musbotg_setup_standard_chain_sub(&temp); 1201 1202 if (xfer->flags_int.isochronous_xfr) { 1203 temp.offset += temp.len; 1204 } else { 1205 /* get next Page Cache pointer */ 1206 temp.pc = xfer->frbuffers + x; 1207 } 1208 } 1209 1210 /* check for control transfer */ 1211 if (xfer->flags_int.control_xfr) { 1212 1213 /* always setup a valid "pc" pointer for status and sync */ 1214 temp.pc = xfer->frbuffers + 0; 1215 temp.len = 0; 1216 temp.short_pkt = 0; 1217 temp.setup_alt_next = 0; 1218 1219 /* check if we should append a status stage */ 1220 if (!xfer->flags_int.control_act) { 1221 /* 1222 * Send a DATA1 message and invert the current 1223 * endpoint direction. 1224 */ 1225 temp.func = &musbotg_setup_status; 1226 musbotg_setup_standard_chain_sub(&temp); 1227 } 1228 } 1229 /* must have at least one frame! */ 1230 td = temp.td; 1231 xfer->td_transfer_last = td; 1232} 1233 1234static void 1235musbotg_timeout(void *arg) 1236{ 1237 struct usb2_xfer *xfer = arg; 1238 1239 DPRINTFN(1, "xfer=%p\n", xfer); 1240 1241 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 1242 1243 /* transfer is transferred */ 1244 musbotg_device_done(xfer, USB_ERR_TIMEOUT); 1245} 1246 1247static void 1248musbotg_ep_int_set(struct usb2_xfer *xfer, uint8_t on) 1249{ 1250 struct musbotg_softc *sc = MUSBOTG_BUS2SC(xfer->xroot->bus); 1251 uint16_t temp; 1252 uint8_t ep_no = xfer->endpoint & UE_ADDR; 1253 1254 /* 1255 * Only enable the endpoint interrupt when we are 1256 * actually waiting for data, hence we are dealing 1257 * with level triggered interrupts ! 1258 */ 1259 if (ep_no == 0) { 1260 temp = MUSB2_READ_2(sc, MUSB2_REG_INTTXE); 1261 if (on) 1262 temp |= MUSB2_MASK_EPINT(0); 1263 else 1264 temp &= ~MUSB2_MASK_EPINT(0); 1265 1266 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, temp); 1267 } else { 1268 if (USB_GET_DATA_ISREAD(xfer)) { 1269 temp = MUSB2_READ_2(sc, MUSB2_REG_INTRXE); 1270 if (on) 1271 temp |= MUSB2_MASK_EPINT(ep_no); 1272 else 1273 temp &= ~MUSB2_MASK_EPINT(ep_no); 1274 MUSB2_WRITE_2(sc, MUSB2_REG_INTRXE, temp); 1275 1276 } else { 1277 temp = MUSB2_READ_2(sc, MUSB2_REG_INTTXE); 1278 if (on) 1279 temp |= MUSB2_MASK_EPINT(ep_no); 1280 else 1281 temp &= ~MUSB2_MASK_EPINT(ep_no); 1282 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, temp); 1283 } 1284 } 1285} 1286 1287static void 1288musbotg_start_standard_chain(struct usb2_xfer *xfer) 1289{ 1290 DPRINTFN(8, "\n"); 1291 1292 /* poll one time */ 1293 if (musbotg_xfer_do_fifo(xfer)) { 1294 1295 musbotg_ep_int_set(xfer, 1); 1296 1297 DPRINTFN(14, "enabled interrupts on endpoint\n"); 1298 1299 /* put transfer on interrupt queue */ 1300 usb2_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 1301 1302 /* start timeout, if any */ 1303 if (xfer->timeout != 0) { 1304 usb2_transfer_timeout_ms(xfer, 1305 &musbotg_timeout, xfer->timeout); 1306 } 1307 } 1308} 1309 1310static void 1311musbotg_root_intr(struct musbotg_softc *sc) 1312{ 1313 DPRINTFN(8, "\n"); 1314 1315 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1316 1317 /* set port bit */ 1318 sc->sc_hub_idata[0] = 0x02; /* we only have one port */ 1319 1320 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, 1321 sizeof(sc->sc_hub_idata)); 1322} 1323 1324static usb2_error_t 1325musbotg_standard_done_sub(struct usb2_xfer *xfer) 1326{ 1327 struct musbotg_td *td; 1328 uint32_t len; 1329 uint8_t error; 1330 1331 DPRINTFN(8, "\n"); 1332 1333 td = xfer->td_transfer_cache; 1334 1335 do { 1336 len = td->remainder; 1337 1338 if (xfer->aframes != xfer->nframes) { 1339 /* 1340 * Verify the length and subtract 1341 * the remainder from "frlengths[]": 1342 */ 1343 if (len > xfer->frlengths[xfer->aframes]) { 1344 td->error = 1; 1345 } else { 1346 xfer->frlengths[xfer->aframes] -= len; 1347 } 1348 } 1349 /* Check for transfer error */ 1350 if (td->error) { 1351 /* the transfer is finished */ 1352 error = 1; 1353 td = NULL; 1354 break; 1355 } 1356 /* Check for short transfer */ 1357 if (len > 0) { 1358 if (xfer->flags_int.short_frames_ok) { 1359 /* follow alt next */ 1360 if (td->alt_next) { 1361 td = td->obj_next; 1362 } else { 1363 td = NULL; 1364 } 1365 } else { 1366 /* the transfer is finished */ 1367 td = NULL; 1368 } 1369 error = 0; 1370 break; 1371 } 1372 td = td->obj_next; 1373 1374 /* this USB frame is complete */ 1375 error = 0; 1376 break; 1377 1378 } while (0); 1379 1380 /* update transfer cache */ 1381 1382 xfer->td_transfer_cache = td; 1383 1384 return (error ? 1385 USB_ERR_STALLED : USB_ERR_NORMAL_COMPLETION); 1386} 1387 1388static void 1389musbotg_standard_done(struct usb2_xfer *xfer) 1390{ 1391 usb2_error_t err = 0; 1392 1393 DPRINTFN(12, "xfer=%p pipe=%p transfer done\n", 1394 xfer, xfer->pipe); 1395 1396 /* reset scanner */ 1397 1398 xfer->td_transfer_cache = xfer->td_transfer_first; 1399 1400 if (xfer->flags_int.control_xfr) { 1401 1402 if (xfer->flags_int.control_hdr) { 1403 1404 err = musbotg_standard_done_sub(xfer); 1405 } 1406 xfer->aframes = 1; 1407 1408 if (xfer->td_transfer_cache == NULL) { 1409 goto done; 1410 } 1411 } 1412 while (xfer->aframes != xfer->nframes) { 1413 1414 err = musbotg_standard_done_sub(xfer); 1415 xfer->aframes++; 1416 1417 if (xfer->td_transfer_cache == NULL) { 1418 goto done; 1419 } 1420 } 1421 1422 if (xfer->flags_int.control_xfr && 1423 !xfer->flags_int.control_act) { 1424 1425 err = musbotg_standard_done_sub(xfer); 1426 } 1427done: 1428 musbotg_device_done(xfer, err); 1429} 1430 1431/*------------------------------------------------------------------------* 1432 * musbotg_device_done 1433 * 1434 * NOTE: this function can be called more than one time on the 1435 * same USB transfer! 1436 *------------------------------------------------------------------------*/ 1437static void 1438musbotg_device_done(struct usb2_xfer *xfer, usb2_error_t error) 1439{ 1440 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 1441 1442 DPRINTFN(2, "xfer=%p, pipe=%p, error=%d\n", 1443 xfer, xfer->pipe, error); 1444 1445 if (xfer->flags_int.usb2_mode == USB_MODE_DEVICE) { 1446 1447 musbotg_ep_int_set(xfer, 0); 1448 1449 DPRINTFN(14, "disabled interrupts on endpoint\n"); 1450 } 1451 /* dequeue transfer and start next transfer */ 1452 usb2_transfer_done(xfer, error); 1453} 1454 1455static void 1456musbotg_set_stall(struct usb2_device *udev, struct usb2_xfer *xfer, 1457 struct usb2_pipe *pipe) 1458{ 1459 struct musbotg_softc *sc; 1460 uint8_t ep_no; 1461 1462 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 1463 1464 DPRINTFN(4, "pipe=%p\n", pipe); 1465 1466 if (xfer) { 1467 /* cancel any ongoing transfers */ 1468 musbotg_device_done(xfer, USB_ERR_STALLED); 1469 } 1470 /* set FORCESTALL */ 1471 sc = MUSBOTG_BUS2SC(udev->bus); 1472 1473 ep_no = (pipe->edesc->bEndpointAddress & UE_ADDR); 1474 1475 /* select endpoint */ 1476 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, ep_no); 1477 1478 if (pipe->edesc->bEndpointAddress & UE_DIR_IN) { 1479 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 1480 MUSB2_MASK_CSRL_TXSENDSTALL); 1481 } else { 1482 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 1483 MUSB2_MASK_CSRL_RXSENDSTALL); 1484 } 1485} 1486 1487static void 1488musbotg_clear_stall_sub(struct musbotg_softc *sc, uint16_t wMaxPacket, 1489 uint8_t ep_no, uint8_t ep_type, uint8_t ep_dir) 1490{ 1491 uint16_t mps; 1492 uint16_t temp; 1493 uint8_t csr; 1494 1495 if (ep_type == UE_CONTROL) { 1496 /* clearing stall is not needed */ 1497 return; 1498 } 1499 /* select endpoint */ 1500 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, ep_no); 1501 1502 /* compute max frame size */ 1503 mps = wMaxPacket & 0x7FF; 1504 switch ((wMaxPacket >> 11) & 3) { 1505 case 1: 1506 mps *= 2; 1507 break; 1508 case 2: 1509 mps *= 3; 1510 break; 1511 default: 1512 break; 1513 } 1514 1515 if (ep_dir == UE_DIR_IN) { 1516 1517 temp = 0; 1518 1519 /* Configure endpoint */ 1520 switch (ep_type) { 1521 case UE_INTERRUPT: 1522 MUSB2_WRITE_1(sc, MUSB2_REG_TXMAXP, wMaxPacket); 1523 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, 1524 MUSB2_MASK_CSRH_TXMODE | temp); 1525 break; 1526 case UE_ISOCHRONOUS: 1527 MUSB2_WRITE_1(sc, MUSB2_REG_TXMAXP, wMaxPacket); 1528 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, 1529 MUSB2_MASK_CSRH_TXMODE | 1530 MUSB2_MASK_CSRH_TXISO | temp); 1531 break; 1532 case UE_BULK: 1533 MUSB2_WRITE_1(sc, MUSB2_REG_TXMAXP, wMaxPacket); 1534 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, 1535 MUSB2_MASK_CSRH_TXMODE | temp); 1536 break; 1537 default: 1538 break; 1539 } 1540 1541 /* Need to flush twice in case of double bufring */ 1542 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 1543 if (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) { 1544 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 1545 MUSB2_MASK_CSRL_TXFFLUSH); 1546 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 1547 if (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) { 1548 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 1549 MUSB2_MASK_CSRL_TXFFLUSH); 1550 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 1551 } 1552 } 1553 /* reset data toggle */ 1554 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 1555 MUSB2_MASK_CSRL_TXDT_CLR); 1556 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0); 1557 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 1558 1559 /* set double/single buffering */ 1560 temp = MUSB2_READ_2(sc, MUSB2_REG_TXDBDIS); 1561 if (mps <= (sc->sc_hw_ep_profile[ep_no]. 1562 max_in_frame_size / 2)) { 1563 /* double buffer */ 1564 temp &= ~(1 << ep_no); 1565 } else { 1566 /* single buffer */ 1567 temp |= (1 << ep_no); 1568 } 1569 MUSB2_WRITE_2(sc, MUSB2_REG_TXDBDIS, temp); 1570 1571 /* clear sent stall */ 1572 if (csr & MUSB2_MASK_CSRL_TXSENTSTALL) { 1573 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0); 1574 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 1575 } 1576 } else { 1577 1578 temp = 0; 1579 1580 /* Configure endpoint */ 1581 switch (ep_type) { 1582 case UE_INTERRUPT: 1583 MUSB2_WRITE_1(sc, MUSB2_REG_RXMAXP, wMaxPacket); 1584 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH, 1585 MUSB2_MASK_CSRH_RXNYET | temp); 1586 break; 1587 case UE_ISOCHRONOUS: 1588 MUSB2_WRITE_1(sc, MUSB2_REG_RXMAXP, wMaxPacket); 1589 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH, 1590 MUSB2_MASK_CSRH_RXNYET | 1591 MUSB2_MASK_CSRH_RXISO | temp); 1592 break; 1593 case UE_BULK: 1594 MUSB2_WRITE_1(sc, MUSB2_REG_RXMAXP, wMaxPacket); 1595 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH, temp); 1596 break; 1597 default: 1598 break; 1599 } 1600 1601 /* Need to flush twice in case of double bufring */ 1602 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL); 1603 if (csr & MUSB2_MASK_CSRL_RXPKTRDY) { 1604 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 1605 MUSB2_MASK_CSRL_RXFFLUSH); 1606 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL); 1607 if (csr & MUSB2_MASK_CSRL_RXPKTRDY) { 1608 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 1609 MUSB2_MASK_CSRL_RXFFLUSH); 1610 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL); 1611 } 1612 } 1613 /* reset data toggle */ 1614 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 1615 MUSB2_MASK_CSRL_RXDT_CLR); 1616 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 0); 1617 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL); 1618 1619 /* set double/single buffering */ 1620 temp = MUSB2_READ_2(sc, MUSB2_REG_RXDBDIS); 1621 if (mps <= (sc->sc_hw_ep_profile[ep_no]. 1622 max_out_frame_size / 2)) { 1623 /* double buffer */ 1624 temp &= ~(1 << ep_no); 1625 } else { 1626 /* single buffer */ 1627 temp |= (1 << ep_no); 1628 } 1629 MUSB2_WRITE_2(sc, MUSB2_REG_RXDBDIS, temp); 1630 1631 /* clear sent stall */ 1632 if (csr & MUSB2_MASK_CSRL_RXSENTSTALL) { 1633 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 0); 1634 } 1635 } 1636} 1637 1638static void 1639musbotg_clear_stall(struct usb2_device *udev, struct usb2_pipe *pipe) 1640{ 1641 struct musbotg_softc *sc; 1642 struct usb2_endpoint_descriptor *ed; 1643 1644 DPRINTFN(4, "pipe=%p\n", pipe); 1645 1646 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 1647 1648 /* check mode */ 1649 if (udev->flags.usb2_mode != USB_MODE_DEVICE) { 1650 /* not supported */ 1651 return; 1652 } 1653 /* get softc */ 1654 sc = MUSBOTG_BUS2SC(udev->bus); 1655 1656 /* get endpoint descriptor */ 1657 ed = pipe->edesc; 1658 1659 /* reset endpoint */ 1660 musbotg_clear_stall_sub(sc, 1661 UGETW(ed->wMaxPacketSize), 1662 (ed->bEndpointAddress & UE_ADDR), 1663 (ed->bmAttributes & UE_XFERTYPE), 1664 (ed->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT))); 1665} 1666 1667usb2_error_t 1668musbotg_init(struct musbotg_softc *sc) 1669{ 1670 struct usb2_hw_ep_profile *pf; 1671 uint8_t nrx; 1672 uint8_t ntx; 1673 uint8_t temp; 1674 uint8_t fsize; 1675 uint8_t frx; 1676 uint8_t ftx; 1677 1678 DPRINTFN(1, "start\n"); 1679 1680 /* set up the bus structure */ 1681 sc->sc_bus.usbrev = USB_REV_2_0; 1682 sc->sc_bus.methods = &musbotg_bus_methods; 1683 1684 USB_BUS_LOCK(&sc->sc_bus); 1685 1686 /* turn on clocks */ 1687 1688 if (sc->sc_clocks_on) { 1689 (sc->sc_clocks_on) (sc->sc_clocks_arg); 1690 } 1691 /* wait a little for things to stabilise */ 1692 usb2_pause_mtx(&sc->sc_bus.bus_mtx, hz / 1000); 1693 1694 /* disable all interrupts */ 1695 1696 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, 0); 1697 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, 0); 1698 MUSB2_WRITE_2(sc, MUSB2_REG_INTRXE, 0); 1699 1700 /* disable pullup */ 1701 1702 musbotg_pull_common(sc, 0); 1703 1704 /* wait a little bit (10ms) */ 1705 usb2_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100); 1706 1707 /* disable double packet buffering */ 1708 MUSB2_WRITE_2(sc, MUSB2_REG_RXDBDIS, 0xFFFF); 1709 MUSB2_WRITE_2(sc, MUSB2_REG_TXDBDIS, 0xFFFF); 1710 1711 /* enable HighSpeed and ISO Update flags */ 1712 1713 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, 1714 MUSB2_MASK_HSENAB | MUSB2_MASK_ISOUPD); 1715 1716 /* clear Session bit, if set */ 1717 1718 temp = MUSB2_READ_1(sc, MUSB2_REG_DEVCTL); 1719 temp &= ~MUSB2_MASK_SESS; 1720 MUSB2_WRITE_1(sc, MUSB2_REG_DEVCTL, temp); 1721 1722 DPRINTF("DEVCTL=0x%02x\n", temp); 1723 1724 /* disable testmode */ 1725 1726 MUSB2_WRITE_1(sc, MUSB2_REG_TESTMODE, 0); 1727 1728 /* set default value */ 1729 1730 MUSB2_WRITE_1(sc, MUSB2_REG_MISC, 0); 1731 1732 /* select endpoint index 0 */ 1733 1734 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); 1735 1736 /* read out number of endpoints */ 1737 1738 nrx = 1739 (MUSB2_READ_1(sc, MUSB2_REG_EPINFO) / 16); 1740 1741 ntx = 1742 (MUSB2_READ_1(sc, MUSB2_REG_EPINFO) % 16); 1743 1744 /* these numbers exclude the control endpoint */ 1745 1746 DPRINTFN(2, "RX/TX endpoints: %u/%u\n", nrx, ntx); 1747 1748 sc->sc_ep_max = (nrx > ntx) ? nrx : ntx; 1749 if (sc->sc_ep_max == 0) { 1750 DPRINTFN(2, "ERROR: Looks like the clocks are off!\n"); 1751 } 1752 /* read out configuration data */ 1753 1754 sc->sc_conf_data = MUSB2_READ_1(sc, MUSB2_REG_CONFDATA); 1755 1756 DPRINTFN(2, "Config Data: 0x%02x\n", 1757 sc->sc_conf_data); 1758 1759 DPRINTFN(2, "HW version: 0x%04x\n", 1760 MUSB2_READ_1(sc, MUSB2_REG_HWVERS)); 1761 1762 /* initialise endpoint profiles */ 1763 1764 for (temp = 1; temp <= sc->sc_ep_max; temp++) { 1765 pf = sc->sc_hw_ep_profile + temp; 1766 1767 /* select endpoint */ 1768 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, temp); 1769 1770 fsize = MUSB2_READ_1(sc, MUSB2_REG_FSIZE); 1771 frx = (fsize & MUSB2_MASK_RX_FSIZE) / 16;; 1772 ftx = (fsize & MUSB2_MASK_TX_FSIZE); 1773 1774 DPRINTF("Endpoint %u FIFO size: IN=%u, OUT=%u\n", 1775 temp, pf->max_in_frame_size, 1776 pf->max_out_frame_size); 1777 1778 if (frx && ftx && (temp <= nrx) && (temp <= ntx)) { 1779 pf->max_in_frame_size = 1 << ftx; 1780 pf->max_out_frame_size = 1 << frx; 1781 pf->is_simplex = 0; /* duplex */ 1782 pf->support_multi_buffer = 1; 1783 pf->support_bulk = 1; 1784 pf->support_interrupt = 1; 1785 pf->support_isochronous = 1; 1786 pf->support_in = 1; 1787 pf->support_out = 1; 1788 } else if (frx && (temp <= nrx)) { 1789 pf->max_out_frame_size = 1 << frx; 1790 pf->is_simplex = 1; /* simplex */ 1791 pf->support_multi_buffer = 1; 1792 pf->support_bulk = 1; 1793 pf->support_interrupt = 1; 1794 pf->support_isochronous = 1; 1795 pf->support_out = 1; 1796 } else if (ftx && (temp <= ntx)) { 1797 pf->max_in_frame_size = 1 << ftx; 1798 pf->is_simplex = 1; /* simplex */ 1799 pf->support_multi_buffer = 1; 1800 pf->support_bulk = 1; 1801 pf->support_interrupt = 1; 1802 pf->support_isochronous = 1; 1803 pf->support_in = 1; 1804 } 1805 } 1806 1807 /* turn on default interrupts */ 1808 1809 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, 1810 MUSB2_MASK_IRESET); 1811 1812 musbotg_clocks_off(sc); 1813 1814 USB_BUS_UNLOCK(&sc->sc_bus); 1815 1816 /* catch any lost interrupts */ 1817 1818 musbotg_do_poll(&sc->sc_bus); 1819 1820 return (0); /* success */ 1821} 1822 1823void 1824musbotg_uninit(struct musbotg_softc *sc) 1825{ 1826 USB_BUS_LOCK(&sc->sc_bus); 1827 1828 /* disable all interrupts */ 1829 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, 0); 1830 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, 0); 1831 MUSB2_WRITE_2(sc, MUSB2_REG_INTRXE, 0); 1832 1833 sc->sc_flags.port_powered = 0; 1834 sc->sc_flags.status_vbus = 0; 1835 sc->sc_flags.status_bus_reset = 0; 1836 sc->sc_flags.status_suspend = 0; 1837 sc->sc_flags.change_suspend = 0; 1838 sc->sc_flags.change_connect = 1; 1839 1840 musbotg_pull_down(sc); 1841 musbotg_clocks_off(sc); 1842 USB_BUS_UNLOCK(&sc->sc_bus); 1843} 1844 1845void 1846musbotg_suspend(struct musbotg_softc *sc) 1847{ 1848 return; 1849} 1850 1851void 1852musbotg_resume(struct musbotg_softc *sc) 1853{ 1854 return; 1855} 1856 1857static void 1858musbotg_do_poll(struct usb2_bus *bus) 1859{ 1860 struct musbotg_softc *sc = MUSBOTG_BUS2SC(bus); 1861 1862 USB_BUS_LOCK(&sc->sc_bus); 1863 musbotg_interrupt_poll(sc); 1864 USB_BUS_UNLOCK(&sc->sc_bus); 1865} 1866 1867/*------------------------------------------------------------------------* 1868 * musbotg bulk support 1869 *------------------------------------------------------------------------*/ 1870static void 1871musbotg_device_bulk_open(struct usb2_xfer *xfer) 1872{ 1873 return; 1874} 1875 1876static void 1877musbotg_device_bulk_close(struct usb2_xfer *xfer) 1878{ 1879 musbotg_device_done(xfer, USB_ERR_CANCELLED); 1880} 1881 1882static void 1883musbotg_device_bulk_enter(struct usb2_xfer *xfer) 1884{ 1885 return; 1886} 1887 1888static void 1889musbotg_device_bulk_start(struct usb2_xfer *xfer) 1890{ 1891 /* setup TDs */ 1892 musbotg_setup_standard_chain(xfer); 1893 musbotg_start_standard_chain(xfer); 1894} 1895 1896struct usb2_pipe_methods musbotg_device_bulk_methods = 1897{ 1898 .open = musbotg_device_bulk_open, 1899 .close = musbotg_device_bulk_close, 1900 .enter = musbotg_device_bulk_enter, 1901 .start = musbotg_device_bulk_start, 1902}; 1903 1904/*------------------------------------------------------------------------* 1905 * musbotg control support 1906 *------------------------------------------------------------------------*/ 1907static void 1908musbotg_device_ctrl_open(struct usb2_xfer *xfer) 1909{ 1910 return; 1911} 1912 1913static void 1914musbotg_device_ctrl_close(struct usb2_xfer *xfer) 1915{ 1916 musbotg_device_done(xfer, USB_ERR_CANCELLED); 1917} 1918 1919static void 1920musbotg_device_ctrl_enter(struct usb2_xfer *xfer) 1921{ 1922 return; 1923} 1924 1925static void 1926musbotg_device_ctrl_start(struct usb2_xfer *xfer) 1927{ 1928 /* setup TDs */ 1929 musbotg_setup_standard_chain(xfer); 1930 musbotg_start_standard_chain(xfer); 1931} 1932 1933struct usb2_pipe_methods musbotg_device_ctrl_methods = 1934{ 1935 .open = musbotg_device_ctrl_open, 1936 .close = musbotg_device_ctrl_close, 1937 .enter = musbotg_device_ctrl_enter, 1938 .start = musbotg_device_ctrl_start, 1939}; 1940 1941/*------------------------------------------------------------------------* 1942 * musbotg interrupt support 1943 *------------------------------------------------------------------------*/ 1944static void 1945musbotg_device_intr_open(struct usb2_xfer *xfer) 1946{ 1947 return; 1948} 1949 1950static void 1951musbotg_device_intr_close(struct usb2_xfer *xfer) 1952{ 1953 musbotg_device_done(xfer, USB_ERR_CANCELLED); 1954} 1955 1956static void 1957musbotg_device_intr_enter(struct usb2_xfer *xfer) 1958{ 1959 return; 1960} 1961 1962static void 1963musbotg_device_intr_start(struct usb2_xfer *xfer) 1964{ 1965 /* setup TDs */ 1966 musbotg_setup_standard_chain(xfer); 1967 musbotg_start_standard_chain(xfer); 1968} 1969 1970struct usb2_pipe_methods musbotg_device_intr_methods = 1971{ 1972 .open = musbotg_device_intr_open, 1973 .close = musbotg_device_intr_close, 1974 .enter = musbotg_device_intr_enter, 1975 .start = musbotg_device_intr_start, 1976}; 1977 1978/*------------------------------------------------------------------------* 1979 * musbotg full speed isochronous support 1980 *------------------------------------------------------------------------*/ 1981static void 1982musbotg_device_isoc_open(struct usb2_xfer *xfer) 1983{ 1984 return; 1985} 1986 1987static void 1988musbotg_device_isoc_close(struct usb2_xfer *xfer) 1989{ 1990 musbotg_device_done(xfer, USB_ERR_CANCELLED); 1991} 1992 1993static void 1994musbotg_device_isoc_enter(struct usb2_xfer *xfer) 1995{ 1996 struct musbotg_softc *sc = MUSBOTG_BUS2SC(xfer->xroot->bus); 1997 uint32_t temp; 1998 uint32_t nframes; 1999 uint32_t fs_frames; 2000 2001 DPRINTFN(5, "xfer=%p next=%d nframes=%d\n", 2002 xfer, xfer->pipe->isoc_next, xfer->nframes); 2003 2004 /* get the current frame index */ 2005 2006 nframes = MUSB2_READ_2(sc, MUSB2_REG_FRAME); 2007 2008 /* 2009 * check if the frame index is within the window where the frames 2010 * will be inserted 2011 */ 2012 temp = (nframes - xfer->pipe->isoc_next) & MUSB2_MASK_FRAME; 2013 2014 if (usb2_get_speed(xfer->xroot->udev) == USB_SPEED_HIGH) { 2015 fs_frames = (xfer->nframes + 7) / 8; 2016 } else { 2017 fs_frames = xfer->nframes; 2018 } 2019 2020 if ((xfer->pipe->is_synced == 0) || 2021 (temp < fs_frames)) { 2022 /* 2023 * If there is data underflow or the pipe queue is 2024 * empty we schedule the transfer a few frames ahead 2025 * of the current frame position. Else two isochronous 2026 * transfers might overlap. 2027 */ 2028 xfer->pipe->isoc_next = (nframes + 3) & MUSB2_MASK_FRAME; 2029 xfer->pipe->is_synced = 1; 2030 DPRINTFN(2, "start next=%d\n", xfer->pipe->isoc_next); 2031 } 2032 /* 2033 * compute how many milliseconds the insertion is ahead of the 2034 * current frame position: 2035 */ 2036 temp = (xfer->pipe->isoc_next - nframes) & MUSB2_MASK_FRAME; 2037 2038 /* 2039 * pre-compute when the isochronous transfer will be finished: 2040 */ 2041 xfer->isoc_time_complete = 2042 usb2_isoc_time_expand(&sc->sc_bus, nframes) + temp + 2043 fs_frames; 2044 2045 /* compute frame number for next insertion */ 2046 xfer->pipe->isoc_next += fs_frames; 2047 2048 /* setup TDs */ 2049 musbotg_setup_standard_chain(xfer); 2050} 2051 2052static void 2053musbotg_device_isoc_start(struct usb2_xfer *xfer) 2054{ 2055 /* start TD chain */ 2056 musbotg_start_standard_chain(xfer); 2057} 2058 2059struct usb2_pipe_methods musbotg_device_isoc_methods = 2060{ 2061 .open = musbotg_device_isoc_open, 2062 .close = musbotg_device_isoc_close, 2063 .enter = musbotg_device_isoc_enter, 2064 .start = musbotg_device_isoc_start, 2065}; 2066 2067/*------------------------------------------------------------------------* 2068 * musbotg root control support 2069 *------------------------------------------------------------------------* 2070 * Simulate a hardware HUB by handling all the necessary requests. 2071 *------------------------------------------------------------------------*/ 2072 2073static const struct usb2_device_descriptor musbotg_devd = { 2074 .bLength = sizeof(struct usb2_device_descriptor), 2075 .bDescriptorType = UDESC_DEVICE, 2076 .bcdUSB = {0x00, 0x02}, 2077 .bDeviceClass = UDCLASS_HUB, 2078 .bDeviceSubClass = UDSUBCLASS_HUB, 2079 .bDeviceProtocol = UDPROTO_HSHUBSTT, 2080 .bMaxPacketSize = 64, 2081 .bcdDevice = {0x00, 0x01}, 2082 .iManufacturer = 1, 2083 .iProduct = 2, 2084 .bNumConfigurations = 1, 2085}; 2086 2087static const struct usb2_device_qualifier musbotg_odevd = { 2088 .bLength = sizeof(struct usb2_device_qualifier), 2089 .bDescriptorType = UDESC_DEVICE_QUALIFIER, 2090 .bcdUSB = {0x00, 0x02}, 2091 .bDeviceClass = UDCLASS_HUB, 2092 .bDeviceSubClass = UDSUBCLASS_HUB, 2093 .bDeviceProtocol = UDPROTO_FSHUB, 2094 .bMaxPacketSize0 = 0, 2095 .bNumConfigurations = 0, 2096}; 2097 2098static const struct musbotg_config_desc musbotg_confd = { 2099 .confd = { 2100 .bLength = sizeof(struct usb2_config_descriptor), 2101 .bDescriptorType = UDESC_CONFIG, 2102 .wTotalLength[0] = sizeof(musbotg_confd), 2103 .bNumInterface = 1, 2104 .bConfigurationValue = 1, 2105 .iConfiguration = 0, 2106 .bmAttributes = UC_SELF_POWERED, 2107 .bMaxPower = 0, 2108 }, 2109 .ifcd = { 2110 .bLength = sizeof(struct usb2_interface_descriptor), 2111 .bDescriptorType = UDESC_INTERFACE, 2112 .bNumEndpoints = 1, 2113 .bInterfaceClass = UICLASS_HUB, 2114 .bInterfaceSubClass = UISUBCLASS_HUB, 2115 .bInterfaceProtocol = UIPROTO_HSHUBSTT, 2116 }, 2117 .endpd = { 2118 .bLength = sizeof(struct usb2_endpoint_descriptor), 2119 .bDescriptorType = UDESC_ENDPOINT, 2120 .bEndpointAddress = (UE_DIR_IN | MUSBOTG_INTR_ENDPT), 2121 .bmAttributes = UE_INTERRUPT, 2122 .wMaxPacketSize[0] = 8, 2123 .bInterval = 255, 2124 }, 2125}; 2126 2127static const struct usb2_hub_descriptor_min musbotg_hubd = { 2128 .bDescLength = sizeof(musbotg_hubd), 2129 .bDescriptorType = UDESC_HUB, 2130 .bNbrPorts = 1, 2131 .wHubCharacteristics[0] = 2132 (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL) & 0xFF, 2133 .wHubCharacteristics[1] = 2134 (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL) >> 16, 2135 .bPwrOn2PwrGood = 50, 2136 .bHubContrCurrent = 0, 2137 .DeviceRemovable = {0}, /* port is removable */ 2138}; 2139 2140#define STRING_LANG \ 2141 0x09, 0x04, /* American English */ 2142 2143#define STRING_VENDOR \ 2144 'M', 0, 'e', 0, 'n', 0, 't', 0, 'o', 0, 'r', 0, ' ', 0, \ 2145 'G', 0, 'r', 0, 'a', 0, 'p', 0, 'h', 0, 'i', 0, 'c', 0, 's', 0 2146 2147#define STRING_PRODUCT \ 2148 'O', 0, 'T', 0, 'G', 0, ' ', 0, 'R', 0, \ 2149 'o', 0, 'o', 0, 't', 0, ' ', 0, 'H', 0, \ 2150 'U', 0, 'B', 0, 2151 2152USB_MAKE_STRING_DESC(STRING_LANG, musbotg_langtab); 2153USB_MAKE_STRING_DESC(STRING_VENDOR, musbotg_vendor); 2154USB_MAKE_STRING_DESC(STRING_PRODUCT, musbotg_product); 2155 2156static void 2157musbotg_roothub_exec(struct usb2_bus *bus) 2158{ 2159 struct musbotg_softc *sc = MUSBOTG_BUS2SC(bus); 2160 struct usb2_sw_transfer *std = &sc->sc_bus.roothub_req; 2161 uint16_t value; 2162 uint16_t index; 2163 2164 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2165 2166 /* buffer reset */ 2167 std->ptr = USB_ADD_BYTES(&sc->sc_hub_temp, 0); 2168 std->len = 0; 2169 2170 value = UGETW(std->req.wValue); 2171 index = UGETW(std->req.wIndex); 2172 2173 /* demultiplex the control request */ 2174 2175 switch (std->req.bmRequestType) { 2176 case UT_READ_DEVICE: 2177 switch (std->req.bRequest) { 2178 case UR_GET_DESCRIPTOR: 2179 goto tr_handle_get_descriptor; 2180 case UR_GET_CONFIG: 2181 goto tr_handle_get_config; 2182 case UR_GET_STATUS: 2183 goto tr_handle_get_status; 2184 default: 2185 goto tr_stalled; 2186 } 2187 break; 2188 2189 case UT_WRITE_DEVICE: 2190 switch (std->req.bRequest) { 2191 case UR_SET_ADDRESS: 2192 goto tr_handle_set_address; 2193 case UR_SET_CONFIG: 2194 goto tr_handle_set_config; 2195 case UR_CLEAR_FEATURE: 2196 goto tr_valid; /* nop */ 2197 case UR_SET_DESCRIPTOR: 2198 goto tr_valid; /* nop */ 2199 case UR_SET_FEATURE: 2200 default: 2201 goto tr_stalled; 2202 } 2203 break; 2204 2205 case UT_WRITE_ENDPOINT: 2206 switch (std->req.bRequest) { 2207 case UR_CLEAR_FEATURE: 2208 switch (UGETW(std->req.wValue)) { 2209 case UF_ENDPOINT_HALT: 2210 goto tr_handle_clear_halt; 2211 case UF_DEVICE_REMOTE_WAKEUP: 2212 goto tr_handle_clear_wakeup; 2213 default: 2214 goto tr_stalled; 2215 } 2216 break; 2217 case UR_SET_FEATURE: 2218 switch (UGETW(std->req.wValue)) { 2219 case UF_ENDPOINT_HALT: 2220 goto tr_handle_set_halt; 2221 case UF_DEVICE_REMOTE_WAKEUP: 2222 goto tr_handle_set_wakeup; 2223 default: 2224 goto tr_stalled; 2225 } 2226 break; 2227 case UR_SYNCH_FRAME: 2228 goto tr_valid; /* nop */ 2229 default: 2230 goto tr_stalled; 2231 } 2232 break; 2233 2234 case UT_READ_ENDPOINT: 2235 switch (std->req.bRequest) { 2236 case UR_GET_STATUS: 2237 goto tr_handle_get_ep_status; 2238 default: 2239 goto tr_stalled; 2240 } 2241 break; 2242 2243 case UT_WRITE_INTERFACE: 2244 switch (std->req.bRequest) { 2245 case UR_SET_INTERFACE: 2246 goto tr_handle_set_interface; 2247 case UR_CLEAR_FEATURE: 2248 goto tr_valid; /* nop */ 2249 case UR_SET_FEATURE: 2250 default: 2251 goto tr_stalled; 2252 } 2253 break; 2254 2255 case UT_READ_INTERFACE: 2256 switch (std->req.bRequest) { 2257 case UR_GET_INTERFACE: 2258 goto tr_handle_get_interface; 2259 case UR_GET_STATUS: 2260 goto tr_handle_get_iface_status; 2261 default: 2262 goto tr_stalled; 2263 } 2264 break; 2265 2266 case UT_WRITE_CLASS_INTERFACE: 2267 case UT_WRITE_VENDOR_INTERFACE: 2268 /* XXX forward */ 2269 break; 2270 2271 case UT_READ_CLASS_INTERFACE: 2272 case UT_READ_VENDOR_INTERFACE: 2273 /* XXX forward */ 2274 break; 2275 2276 case UT_WRITE_CLASS_DEVICE: 2277 switch (std->req.bRequest) { 2278 case UR_CLEAR_FEATURE: 2279 goto tr_valid; 2280 case UR_SET_DESCRIPTOR: 2281 case UR_SET_FEATURE: 2282 break; 2283 default: 2284 goto tr_stalled; 2285 } 2286 break; 2287 2288 case UT_WRITE_CLASS_OTHER: 2289 switch (std->req.bRequest) { 2290 case UR_CLEAR_FEATURE: 2291 goto tr_handle_clear_port_feature; 2292 case UR_SET_FEATURE: 2293 goto tr_handle_set_port_feature; 2294 case UR_CLEAR_TT_BUFFER: 2295 case UR_RESET_TT: 2296 case UR_STOP_TT: 2297 goto tr_valid; 2298 2299 default: 2300 goto tr_stalled; 2301 } 2302 break; 2303 2304 case UT_READ_CLASS_OTHER: 2305 switch (std->req.bRequest) { 2306 case UR_GET_TT_STATE: 2307 goto tr_handle_get_tt_state; 2308 case UR_GET_STATUS: 2309 goto tr_handle_get_port_status; 2310 default: 2311 goto tr_stalled; 2312 } 2313 break; 2314 2315 case UT_READ_CLASS_DEVICE: 2316 switch (std->req.bRequest) { 2317 case UR_GET_DESCRIPTOR: 2318 goto tr_handle_get_class_descriptor; 2319 case UR_GET_STATUS: 2320 goto tr_handle_get_class_status; 2321 2322 default: 2323 goto tr_stalled; 2324 } 2325 break; 2326 default: 2327 goto tr_stalled; 2328 } 2329 goto tr_valid; 2330 2331tr_handle_get_descriptor: 2332 switch (value >> 8) { 2333 case UDESC_DEVICE: 2334 if (value & 0xff) { 2335 goto tr_stalled; 2336 } 2337 std->len = sizeof(musbotg_devd); 2338 std->ptr = USB_ADD_BYTES(&musbotg_devd, 0); 2339 goto tr_valid; 2340 case UDESC_CONFIG: 2341 if (value & 0xff) { 2342 goto tr_stalled; 2343 } 2344 std->len = sizeof(musbotg_confd); 2345 std->ptr = USB_ADD_BYTES(&musbotg_confd, 0); 2346 goto tr_valid; 2347 case UDESC_STRING: 2348 switch (value & 0xff) { 2349 case 0: /* Language table */ 2350 std->len = sizeof(musbotg_langtab); 2351 std->ptr = USB_ADD_BYTES(&musbotg_langtab, 0); 2352 goto tr_valid; 2353 2354 case 1: /* Vendor */ 2355 std->len = sizeof(musbotg_vendor); 2356 std->ptr = USB_ADD_BYTES(&musbotg_vendor, 0); 2357 goto tr_valid; 2358 2359 case 2: /* Product */ 2360 std->len = sizeof(musbotg_product); 2361 std->ptr = USB_ADD_BYTES(&musbotg_product, 0); 2362 goto tr_valid; 2363 default: 2364 break; 2365 } 2366 break; 2367 default: 2368 goto tr_stalled; 2369 } 2370 goto tr_stalled; 2371 2372tr_handle_get_config: 2373 std->len = 1; 2374 sc->sc_hub_temp.wValue[0] = sc->sc_conf; 2375 goto tr_valid; 2376 2377tr_handle_get_status: 2378 std->len = 2; 2379 USETW(sc->sc_hub_temp.wValue, UDS_SELF_POWERED); 2380 goto tr_valid; 2381 2382tr_handle_set_address: 2383 if (value & 0xFF00) { 2384 goto tr_stalled; 2385 } 2386 sc->sc_rt_addr = value; 2387 goto tr_valid; 2388 2389tr_handle_set_config: 2390 if (value >= 2) { 2391 goto tr_stalled; 2392 } 2393 sc->sc_conf = value; 2394 goto tr_valid; 2395 2396tr_handle_get_interface: 2397 std->len = 1; 2398 sc->sc_hub_temp.wValue[0] = 0; 2399 goto tr_valid; 2400 2401tr_handle_get_tt_state: 2402tr_handle_get_class_status: 2403tr_handle_get_iface_status: 2404tr_handle_get_ep_status: 2405 std->len = 2; 2406 USETW(sc->sc_hub_temp.wValue, 0); 2407 goto tr_valid; 2408 2409tr_handle_set_halt: 2410tr_handle_set_interface: 2411tr_handle_set_wakeup: 2412tr_handle_clear_wakeup: 2413tr_handle_clear_halt: 2414 goto tr_valid; 2415 2416tr_handle_clear_port_feature: 2417 if (index != 1) { 2418 goto tr_stalled; 2419 } 2420 DPRINTFN(8, "UR_CLEAR_PORT_FEATURE on port %d\n", index); 2421 2422 switch (value) { 2423 case UHF_PORT_SUSPEND: 2424 musbotg_wakeup_peer(sc); 2425 break; 2426 2427 case UHF_PORT_ENABLE: 2428 sc->sc_flags.port_enabled = 0; 2429 break; 2430 2431 case UHF_PORT_TEST: 2432 case UHF_PORT_INDICATOR: 2433 case UHF_C_PORT_ENABLE: 2434 case UHF_C_PORT_OVER_CURRENT: 2435 case UHF_C_PORT_RESET: 2436 /* nops */ 2437 break; 2438 case UHF_PORT_POWER: 2439 sc->sc_flags.port_powered = 0; 2440 musbotg_pull_down(sc); 2441 musbotg_clocks_off(sc); 2442 break; 2443 case UHF_C_PORT_CONNECTION: 2444 sc->sc_flags.change_connect = 0; 2445 break; 2446 case UHF_C_PORT_SUSPEND: 2447 sc->sc_flags.change_suspend = 0; 2448 break; 2449 default: 2450 std->err = USB_ERR_IOERROR; 2451 goto done; 2452 } 2453 goto tr_valid; 2454 2455tr_handle_set_port_feature: 2456 if (index != 1) { 2457 goto tr_stalled; 2458 } 2459 DPRINTFN(8, "UR_SET_PORT_FEATURE\n"); 2460 2461 switch (value) { 2462 case UHF_PORT_ENABLE: 2463 sc->sc_flags.port_enabled = 1; 2464 break; 2465 case UHF_PORT_SUSPEND: 2466 case UHF_PORT_RESET: 2467 case UHF_PORT_TEST: 2468 case UHF_PORT_INDICATOR: 2469 /* nops */ 2470 break; 2471 case UHF_PORT_POWER: 2472 sc->sc_flags.port_powered = 1; 2473 break; 2474 default: 2475 std->err = USB_ERR_IOERROR; 2476 goto done; 2477 } 2478 goto tr_valid; 2479 2480tr_handle_get_port_status: 2481 2482 DPRINTFN(8, "UR_GET_PORT_STATUS\n"); 2483 2484 if (index != 1) { 2485 goto tr_stalled; 2486 } 2487 if (sc->sc_flags.status_vbus) { 2488 musbotg_clocks_on(sc); 2489 musbotg_pull_up(sc); 2490 } else { 2491 musbotg_pull_down(sc); 2492 musbotg_clocks_off(sc); 2493 } 2494 2495 /* Select Device Side Mode */ 2496 value = UPS_PORT_MODE_DEVICE; 2497 2498 if (sc->sc_flags.status_high_speed) { 2499 value |= UPS_HIGH_SPEED; 2500 } 2501 if (sc->sc_flags.port_powered) { 2502 value |= UPS_PORT_POWER; 2503 } 2504 if (sc->sc_flags.port_enabled) { 2505 value |= UPS_PORT_ENABLED; 2506 } 2507 if (sc->sc_flags.status_vbus && 2508 sc->sc_flags.status_bus_reset) { 2509 value |= UPS_CURRENT_CONNECT_STATUS; 2510 } 2511 if (sc->sc_flags.status_suspend) { 2512 value |= UPS_SUSPEND; 2513 } 2514 USETW(sc->sc_hub_temp.ps.wPortStatus, value); 2515 2516 value = 0; 2517 2518 if (sc->sc_flags.change_connect) { 2519 value |= UPS_C_CONNECT_STATUS; 2520 2521 if (sc->sc_flags.status_vbus && 2522 sc->sc_flags.status_bus_reset) { 2523 /* reset EP0 state */ 2524 sc->sc_ep0_busy = 0; 2525 sc->sc_ep0_cmd = 0; 2526 } 2527 } 2528 if (sc->sc_flags.change_suspend) { 2529 value |= UPS_C_SUSPEND; 2530 } 2531 USETW(sc->sc_hub_temp.ps.wPortChange, value); 2532 std->len = sizeof(sc->sc_hub_temp.ps); 2533 goto tr_valid; 2534 2535tr_handle_get_class_descriptor: 2536 if (value & 0xFF) { 2537 goto tr_stalled; 2538 } 2539 std->ptr = USB_ADD_BYTES(&musbotg_hubd, 0); 2540 std->len = sizeof(musbotg_hubd); 2541 goto tr_valid; 2542 2543tr_stalled: 2544 std->err = USB_ERR_STALLED; 2545tr_valid: 2546done: 2547 return; 2548} 2549 2550static void 2551musbotg_xfer_setup(struct usb2_setup_params *parm) 2552{ 2553 const struct usb2_hw_ep_profile *pf; 2554 struct musbotg_softc *sc; 2555 struct usb2_xfer *xfer; 2556 void *last_obj; 2557 uint32_t ntd; 2558 uint32_t n; 2559 uint8_t ep_no; 2560 2561 sc = MUSBOTG_BUS2SC(parm->udev->bus); 2562 xfer = parm->curr_xfer; 2563 2564 /* 2565 * NOTE: This driver does not use any of the parameters that 2566 * are computed from the following values. Just set some 2567 * reasonable dummies: 2568 */ 2569 parm->hc_max_packet_size = 0x400; 2570 parm->hc_max_frame_size = 0x400; 2571 2572 if ((parm->methods == &musbotg_device_isoc_methods) || 2573 (parm->methods == &musbotg_device_intr_methods)) 2574 parm->hc_max_packet_count = 3; 2575 else 2576 parm->hc_max_packet_count = 1; 2577 2578 usb2_transfer_setup_sub(parm); 2579 2580 /* 2581 * compute maximum number of TDs 2582 */ 2583 if (parm->methods == &musbotg_device_ctrl_methods) { 2584 2585 ntd = xfer->nframes + 1 /* STATUS */ + 1 /* SYNC */ ; 2586 2587 } else if (parm->methods == &musbotg_device_bulk_methods) { 2588 2589 ntd = xfer->nframes + 1 /* SYNC */ ; 2590 2591 } else if (parm->methods == &musbotg_device_intr_methods) { 2592 2593 ntd = xfer->nframes + 1 /* SYNC */ ; 2594 2595 } else if (parm->methods == &musbotg_device_isoc_methods) { 2596 2597 ntd = xfer->nframes + 1 /* SYNC */ ; 2598 2599 } else { 2600 2601 ntd = 0; 2602 } 2603 2604 /* 2605 * check if "usb2_transfer_setup_sub" set an error 2606 */ 2607 if (parm->err) { 2608 return; 2609 } 2610 /* 2611 * allocate transfer descriptors 2612 */ 2613 last_obj = NULL; 2614 2615 /* 2616 * get profile stuff 2617 */ 2618 if (ntd) { 2619 2620 ep_no = xfer->endpoint & UE_ADDR; 2621 musbotg_get_hw_ep_profile(parm->udev, &pf, ep_no); 2622 2623 if (pf == NULL) { 2624 /* should not happen */ 2625 parm->err = USB_ERR_INVAL; 2626 return; 2627 } 2628 } else { 2629 ep_no = 0; 2630 pf = NULL; 2631 } 2632 2633 /* align data */ 2634 parm->size[0] += ((-parm->size[0]) & (USB_HOST_ALIGN - 1)); 2635 2636 for (n = 0; n != ntd; n++) { 2637 2638 struct musbotg_td *td; 2639 2640 if (parm->buf) { 2641 2642 td = USB_ADD_BYTES(parm->buf, parm->size[0]); 2643 2644 /* init TD */ 2645 td->max_frame_size = xfer->max_frame_size; 2646 td->ep_no = ep_no; 2647 td->obj_next = last_obj; 2648 2649 last_obj = td; 2650 } 2651 parm->size[0] += sizeof(*td); 2652 } 2653 2654 xfer->td_start[0] = last_obj; 2655} 2656 2657static void 2658musbotg_xfer_unsetup(struct usb2_xfer *xfer) 2659{ 2660 return; 2661} 2662 2663static void 2664musbotg_pipe_init(struct usb2_device *udev, struct usb2_endpoint_descriptor *edesc, 2665 struct usb2_pipe *pipe) 2666{ 2667 struct musbotg_softc *sc = MUSBOTG_BUS2SC(udev->bus); 2668 2669 DPRINTFN(2, "pipe=%p, addr=%d, endpt=%d, mode=%d (%d)\n", 2670 pipe, udev->address, 2671 edesc->bEndpointAddress, udev->flags.usb2_mode, 2672 sc->sc_rt_addr); 2673 2674 if (udev->device_index != sc->sc_rt_addr) { 2675 2676 if (udev->flags.usb2_mode != USB_MODE_DEVICE) { 2677 /* not supported */ 2678 return; 2679 } 2680 if ((udev->speed != USB_SPEED_FULL) && 2681 (udev->speed != USB_SPEED_HIGH)) { 2682 /* not supported */ 2683 return; 2684 } 2685 switch (edesc->bmAttributes & UE_XFERTYPE) { 2686 case UE_CONTROL: 2687 pipe->methods = &musbotg_device_ctrl_methods; 2688 break; 2689 case UE_INTERRUPT: 2690 pipe->methods = &musbotg_device_intr_methods; 2691 break; 2692 case UE_ISOCHRONOUS: 2693 pipe->methods = &musbotg_device_isoc_methods; 2694 break; 2695 case UE_BULK: 2696 pipe->methods = &musbotg_device_bulk_methods; 2697 break; 2698 default: 2699 /* do nothing */ 2700 break; 2701 } 2702 } 2703} 2704 2705struct usb2_bus_methods musbotg_bus_methods = 2706{ 2707 .pipe_init = &musbotg_pipe_init, 2708 .xfer_setup = &musbotg_xfer_setup, 2709 .xfer_unsetup = &musbotg_xfer_unsetup, 2710 .get_hw_ep_profile = &musbotg_get_hw_ep_profile, 2711 .set_stall = &musbotg_set_stall, 2712 .clear_stall = &musbotg_clear_stall, 2713 .roothub_exec = &musbotg_roothub_exec, 2714}; 2715