musb_otg.c revision 190722
1/* $FreeBSD: head/sys/dev/usb/controller/musb_otg.c 190722 2009-04-05 18:18:25Z thompsa $ */ 2/*- 3 * Copyright (c) 2008 Hans Petter Selasky. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27/* 28 * Thanks to Mentor Graphics for providing a reference driver for this 29 * USB chip at their homepage. 30 */ 31 32/* 33 * This file contains the driver for the Mentor Graphics Inventra USB 34 * 2.0 High Speed Dual-Role controller. 35 * 36 * NOTE: The current implementation only supports Device Side Mode! 37 */ 38 39#include <dev/usb/usb.h> 40#include <dev/usb/usb_mfunc.h> 41#include <dev/usb/usb_error.h> 42 43#define USB_DEBUG_VAR musbotgdebug 44 45#include <dev/usb/usb_core.h> 46#include <dev/usb/usb_debug.h> 47#include <dev/usb/usb_busdma.h> 48#include <dev/usb/usb_process.h> 49#include <dev/usb/usb_sw_transfer.h> 50#include <dev/usb/usb_transfer.h> 51#include <dev/usb/usb_device.h> 52#include <dev/usb/usb_hub.h> 53#include <dev/usb/usb_util.h> 54 55#include <dev/usb/usb_controller.h> 56#include <dev/usb/usb_bus.h> 57#include <dev/usb/controller/musb_otg.h> 58 59#define MUSBOTG_INTR_ENDPT 1 60 61#define MUSBOTG_BUS2SC(bus) \ 62 ((struct musbotg_softc *)(((uint8_t *)(bus)) - \ 63 USB_P2U(&(((struct musbotg_softc *)0)->sc_bus)))) 64 65#define MUSBOTG_PC2SC(pc) \ 66 MUSBOTG_BUS2SC(USB_DMATAG_TO_XROOT((pc)->tag_parent)->bus) 67 68#if USB_DEBUG 69static int musbotgdebug = 0; 70 71SYSCTL_NODE(_hw_usb2, OID_AUTO, musbotg, CTLFLAG_RW, 0, "USB musbotg"); 72SYSCTL_INT(_hw_usb2_musbotg, OID_AUTO, debug, CTLFLAG_RW, 73 &musbotgdebug, 0, "Debug level"); 74#endif 75 76/* prototypes */ 77 78struct usb2_bus_methods musbotg_bus_methods; 79struct usb2_pipe_methods musbotg_device_bulk_methods; 80struct usb2_pipe_methods musbotg_device_ctrl_methods; 81struct usb2_pipe_methods musbotg_device_intr_methods; 82struct usb2_pipe_methods musbotg_device_isoc_methods; 83struct usb2_pipe_methods musbotg_root_ctrl_methods; 84struct usb2_pipe_methods musbotg_root_intr_methods; 85 86static musbotg_cmd_t musbotg_setup_rx; 87static musbotg_cmd_t musbotg_setup_data_rx; 88static musbotg_cmd_t musbotg_setup_data_tx; 89static musbotg_cmd_t musbotg_setup_status; 90static musbotg_cmd_t musbotg_data_rx; 91static musbotg_cmd_t musbotg_data_tx; 92static void musbotg_device_done(struct usb2_xfer *, usb2_error_t); 93static void musbotg_do_poll(struct usb2_bus *); 94static void musbotg_root_ctrl_poll(struct musbotg_softc *); 95static void musbotg_standard_done(struct usb2_xfer *); 96static void musbotg_interrupt_poll(struct musbotg_softc *); 97 98static usb2_sw_transfer_func_t musbotg_root_intr_done; 99static usb2_sw_transfer_func_t musbotg_root_ctrl_done; 100 101/* 102 * Here is a configuration that the chip supports. 103 */ 104static const struct usb2_hw_ep_profile musbotg_ep_profile[1] = { 105 106 [0] = { 107 .max_in_frame_size = 64,/* fixed */ 108 .max_out_frame_size = 64, /* fixed */ 109 .is_simplex = 1, 110 .support_control = 1, 111 } 112}; 113 114static void 115musbotg_get_hw_ep_profile(struct usb2_device *udev, 116 const struct usb2_hw_ep_profile **ppf, uint8_t ep_addr) 117{ 118 struct musbotg_softc *sc; 119 120 sc = MUSBOTG_BUS2SC(udev->bus); 121 122 if (ep_addr == 0) { 123 /* control endpoint */ 124 *ppf = musbotg_ep_profile; 125 } else if (ep_addr <= sc->sc_ep_max) { 126 /* other endpoints */ 127 *ppf = sc->sc_hw_ep_profile + ep_addr; 128 } else { 129 *ppf = NULL; 130 } 131} 132 133static void 134musbotg_clocks_on(struct musbotg_softc *sc) 135{ 136 if (sc->sc_flags.clocks_off && 137 sc->sc_flags.port_powered) { 138 139 DPRINTFN(4, "\n"); 140 141 if (sc->sc_clocks_on) { 142 (sc->sc_clocks_on) (sc->sc_clocks_arg); 143 } 144 sc->sc_flags.clocks_off = 0; 145 146 /* XXX enable Transceiver */ 147 } 148} 149 150static void 151musbotg_clocks_off(struct musbotg_softc *sc) 152{ 153 if (!sc->sc_flags.clocks_off) { 154 155 DPRINTFN(4, "\n"); 156 157 /* XXX disable Transceiver */ 158 159 if (sc->sc_clocks_off) { 160 (sc->sc_clocks_off) (sc->sc_clocks_arg); 161 } 162 sc->sc_flags.clocks_off = 1; 163 } 164} 165 166static void 167musbotg_pull_common(struct musbotg_softc *sc, uint8_t on) 168{ 169 uint8_t temp; 170 171 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER); 172 if (on) 173 temp |= MUSB2_MASK_SOFTC; 174 else 175 temp &= ~MUSB2_MASK_SOFTC; 176 177 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp); 178} 179 180static void 181musbotg_pull_up(struct musbotg_softc *sc) 182{ 183 /* pullup D+, if possible */ 184 185 if (!sc->sc_flags.d_pulled_up && 186 sc->sc_flags.port_powered) { 187 sc->sc_flags.d_pulled_up = 1; 188 musbotg_pull_common(sc, 1); 189 } 190} 191 192static void 193musbotg_pull_down(struct musbotg_softc *sc) 194{ 195 /* pulldown D+, if possible */ 196 197 if (sc->sc_flags.d_pulled_up) { 198 sc->sc_flags.d_pulled_up = 0; 199 musbotg_pull_common(sc, 0); 200 } 201} 202 203static void 204musbotg_wakeup_peer(struct usb2_xfer *xfer) 205{ 206 struct musbotg_softc *sc = MUSBOTG_BUS2SC(xfer->xroot->bus); 207 uint8_t temp; 208 209 if (!(sc->sc_flags.status_suspend)) { 210 return; 211 } 212 213 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER); 214 temp |= MUSB2_MASK_RESUME; 215 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp); 216 217 /* wait 8 milliseconds */ 218 /* Wait for reset to complete. */ 219 usb2_pause_mtx(&sc->sc_bus.bus_mtx, hz / 125); 220 221 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER); 222 temp &= ~MUSB2_MASK_RESUME; 223 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp); 224} 225 226static void 227musbotg_set_address(struct musbotg_softc *sc, uint8_t addr) 228{ 229 DPRINTFN(4, "addr=%d\n", addr); 230 addr &= 0x7F; 231 MUSB2_WRITE_1(sc, MUSB2_REG_FADDR, addr); 232} 233 234static uint8_t 235musbotg_setup_rx(struct musbotg_td *td) 236{ 237 struct musbotg_softc *sc; 238 struct usb2_device_request req; 239 uint16_t count; 240 uint8_t csr; 241 242 /* get pointer to softc */ 243 sc = MUSBOTG_PC2SC(td->pc); 244 245 /* select endpoint 0 */ 246 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); 247 248 /* read out FIFO status */ 249 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 250 251 DPRINTFN(4, "csr=0x%02x\n", csr); 252 253 /* 254 * NOTE: If DATAEND is set we should not call the 255 * callback, hence the status stage is not complete. 256 */ 257 if (csr & MUSB2_MASK_CSR0L_DATAEND) { 258 /* do not stall at this point */ 259 td->did_stall = 1; 260 /* wait for interrupt */ 261 goto not_complete; 262 } 263 if (csr & MUSB2_MASK_CSR0L_SENTSTALL) { 264 /* clear SENTSTALL */ 265 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0); 266 /* get latest status */ 267 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 268 /* update EP0 state */ 269 sc->sc_ep0_busy = 0; 270 } 271 if (csr & MUSB2_MASK_CSR0L_SETUPEND) { 272 /* clear SETUPEND */ 273 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 274 MUSB2_MASK_CSR0L_SETUPEND_CLR); 275 /* get latest status */ 276 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 277 /* update EP0 state */ 278 sc->sc_ep0_busy = 0; 279 } 280 if (sc->sc_ep0_busy) { 281 goto not_complete; 282 } 283 if (!(csr & MUSB2_MASK_CSR0L_RXPKTRDY)) { 284 goto not_complete; 285 } 286 /* clear did stall flag */ 287 td->did_stall = 0; 288 /* get the packet byte count */ 289 count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT); 290 291 /* verify data length */ 292 if (count != td->remainder) { 293 DPRINTFN(0, "Invalid SETUP packet " 294 "length, %d bytes\n", count); 295 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 296 MUSB2_MASK_CSR0L_RXPKTRDY_CLR); 297 goto not_complete; 298 } 299 if (count != sizeof(req)) { 300 DPRINTFN(0, "Unsupported SETUP packet " 301 "length, %d bytes\n", count); 302 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 303 MUSB2_MASK_CSR0L_RXPKTRDY_CLR); 304 goto not_complete; 305 } 306 /* receive data */ 307 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 308 MUSB2_REG_EPFIFO(0), (void *)&req, sizeof(req)); 309 310 /* copy data into real buffer */ 311 usb2_copy_in(td->pc, 0, &req, sizeof(req)); 312 313 td->offset = sizeof(req); 314 td->remainder = 0; 315 316 /* set pending command */ 317 sc->sc_ep0_cmd = MUSB2_MASK_CSR0L_RXPKTRDY_CLR; 318 319 /* we need set stall or dataend after this */ 320 sc->sc_ep0_busy = 1; 321 322 /* sneak peek the set address */ 323 if ((req.bmRequestType == UT_WRITE_DEVICE) && 324 (req.bRequest == UR_SET_ADDRESS)) { 325 sc->sc_dv_addr = req.wValue[0] & 0x7F; 326 } else { 327 sc->sc_dv_addr = 0xFF; 328 } 329 return (0); /* complete */ 330 331not_complete: 332 /* abort any ongoing transfer */ 333 if (!td->did_stall) { 334 DPRINTFN(4, "stalling\n"); 335 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 336 MUSB2_MASK_CSR0L_SENDSTALL); 337 td->did_stall = 1; 338 } 339 return (1); /* not complete */ 340} 341 342/* Control endpoint only data handling functions (RX/TX/SYNC) */ 343 344static uint8_t 345musbotg_setup_data_rx(struct musbotg_td *td) 346{ 347 struct usb2_page_search buf_res; 348 struct musbotg_softc *sc; 349 uint16_t count; 350 uint8_t csr; 351 uint8_t got_short; 352 353 /* get pointer to softc */ 354 sc = MUSBOTG_PC2SC(td->pc); 355 356 /* select endpoint 0 */ 357 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); 358 359 /* check if a command is pending */ 360 if (sc->sc_ep0_cmd) { 361 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, sc->sc_ep0_cmd); 362 sc->sc_ep0_cmd = 0; 363 } 364 /* read out FIFO status */ 365 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 366 367 DPRINTFN(4, "csr=0x%02x\n", csr); 368 369 got_short = 0; 370 371 if (csr & (MUSB2_MASK_CSR0L_SETUPEND | 372 MUSB2_MASK_CSR0L_SENTSTALL)) { 373 if (td->remainder == 0) { 374 /* 375 * We are actually complete and have 376 * received the next SETUP 377 */ 378 DPRINTFN(4, "faking complete\n"); 379 return (0); /* complete */ 380 } 381 /* 382 * USB Host Aborted the transfer. 383 */ 384 td->error = 1; 385 return (0); /* complete */ 386 } 387 if (!(csr & MUSB2_MASK_CSR0L_RXPKTRDY)) { 388 return (1); /* not complete */ 389 } 390 /* get the packet byte count */ 391 count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT); 392 393 /* verify the packet byte count */ 394 if (count != td->max_frame_size) { 395 if (count < td->max_frame_size) { 396 /* we have a short packet */ 397 td->short_pkt = 1; 398 got_short = 1; 399 } else { 400 /* invalid USB packet */ 401 td->error = 1; 402 return (0); /* we are complete */ 403 } 404 } 405 /* verify the packet byte count */ 406 if (count > td->remainder) { 407 /* invalid USB packet */ 408 td->error = 1; 409 return (0); /* we are complete */ 410 } 411 while (count > 0) { 412 uint32_t temp; 413 414 usb2_get_page(td->pc, td->offset, &buf_res); 415 416 /* get correct length */ 417 if (buf_res.length > count) { 418 buf_res.length = count; 419 } 420 /* check for unaligned memory address */ 421 if (USB_P2U(buf_res.buffer) & 3) { 422 423 temp = count & ~3; 424 425 if (temp) { 426 /* receive data 4 bytes at a time */ 427 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 428 MUSB2_REG_EPFIFO(0), sc->sc_bounce_buf, 429 temp / 4); 430 } 431 temp = count & 3; 432 if (temp) { 433 /* receive data 1 byte at a time */ 434 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 435 MUSB2_REG_EPFIFO(0), 436 (void *)(&sc->sc_bounce_buf[count / 4]), temp); 437 } 438 usb2_copy_in(td->pc, td->offset, 439 sc->sc_bounce_buf, count); 440 441 /* update offset and remainder */ 442 td->offset += count; 443 td->remainder -= count; 444 break; 445 } 446 /* check if we can optimise */ 447 if (buf_res.length >= 4) { 448 449 /* receive data 4 bytes at a time */ 450 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 451 MUSB2_REG_EPFIFO(0), buf_res.buffer, 452 buf_res.length / 4); 453 454 temp = buf_res.length & ~3; 455 456 /* update counters */ 457 count -= temp; 458 td->offset += temp; 459 td->remainder -= temp; 460 continue; 461 } 462 /* receive data */ 463 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 464 MUSB2_REG_EPFIFO(0), buf_res.buffer, buf_res.length); 465 466 /* update counters */ 467 count -= buf_res.length; 468 td->offset += buf_res.length; 469 td->remainder -= buf_res.length; 470 } 471 472 /* check if we are complete */ 473 if ((td->remainder == 0) || got_short) { 474 if (td->short_pkt) { 475 /* we are complete */ 476 sc->sc_ep0_cmd = MUSB2_MASK_CSR0L_RXPKTRDY_CLR; 477 return (0); 478 } 479 /* else need to receive a zero length packet */ 480 } 481 /* write command - need more data */ 482 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 483 MUSB2_MASK_CSR0L_RXPKTRDY_CLR); 484 return (1); /* not complete */ 485} 486 487static uint8_t 488musbotg_setup_data_tx(struct musbotg_td *td) 489{ 490 struct usb2_page_search buf_res; 491 struct musbotg_softc *sc; 492 uint16_t count; 493 uint8_t csr; 494 495 /* get pointer to softc */ 496 sc = MUSBOTG_PC2SC(td->pc); 497 498 /* select endpoint 0 */ 499 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); 500 501 /* check if a command is pending */ 502 if (sc->sc_ep0_cmd) { 503 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, sc->sc_ep0_cmd); 504 sc->sc_ep0_cmd = 0; 505 } 506 /* read out FIFO status */ 507 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 508 509 DPRINTFN(4, "csr=0x%02x\n", csr); 510 511 if (csr & (MUSB2_MASK_CSR0L_SETUPEND | 512 MUSB2_MASK_CSR0L_SENTSTALL)) { 513 /* 514 * The current transfer was aborted 515 * by the USB Host 516 */ 517 td->error = 1; 518 return (0); /* complete */ 519 } 520 if (csr & MUSB2_MASK_CSR0L_TXPKTRDY) { 521 return (1); /* not complete */ 522 } 523 count = td->max_frame_size; 524 if (td->remainder < count) { 525 /* we have a short packet */ 526 td->short_pkt = 1; 527 count = td->remainder; 528 } 529 while (count > 0) { 530 uint32_t temp; 531 532 usb2_get_page(td->pc, td->offset, &buf_res); 533 534 /* get correct length */ 535 if (buf_res.length > count) { 536 buf_res.length = count; 537 } 538 /* check for unaligned memory address */ 539 if (USB_P2U(buf_res.buffer) & 3) { 540 541 usb2_copy_out(td->pc, td->offset, 542 sc->sc_bounce_buf, count); 543 544 temp = count & ~3; 545 546 if (temp) { 547 /* transmit data 4 bytes at a time */ 548 bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 549 MUSB2_REG_EPFIFO(0), sc->sc_bounce_buf, 550 temp / 4); 551 } 552 temp = count & 3; 553 if (temp) { 554 /* receive data 1 byte at a time */ 555 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 556 MUSB2_REG_EPFIFO(0), 557 ((void *)&sc->sc_bounce_buf[count / 4]), temp); 558 } 559 /* update offset and remainder */ 560 td->offset += count; 561 td->remainder -= count; 562 break; 563 } 564 /* check if we can optimise */ 565 if (buf_res.length >= 4) { 566 567 /* transmit data 4 bytes at a time */ 568 bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 569 MUSB2_REG_EPFIFO(0), buf_res.buffer, 570 buf_res.length / 4); 571 572 temp = buf_res.length & ~3; 573 574 /* update counters */ 575 count -= temp; 576 td->offset += temp; 577 td->remainder -= temp; 578 continue; 579 } 580 /* transmit data */ 581 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 582 MUSB2_REG_EPFIFO(0), buf_res.buffer, buf_res.length); 583 584 /* update counters */ 585 count -= buf_res.length; 586 td->offset += buf_res.length; 587 td->remainder -= buf_res.length; 588 } 589 590 /* check remainder */ 591 if (td->remainder == 0) { 592 if (td->short_pkt) { 593 sc->sc_ep0_cmd = MUSB2_MASK_CSR0L_TXPKTRDY; 594 return (0); /* complete */ 595 } 596 /* else we need to transmit a short packet */ 597 } 598 /* write command */ 599 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 600 MUSB2_MASK_CSR0L_TXPKTRDY); 601 602 return (1); /* not complete */ 603} 604 605static uint8_t 606musbotg_setup_status(struct musbotg_td *td) 607{ 608 struct musbotg_softc *sc; 609 uint8_t csr; 610 611 /* get pointer to softc */ 612 sc = MUSBOTG_PC2SC(td->pc); 613 614 /* select endpoint 0 */ 615 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); 616 617 if (sc->sc_ep0_busy) { 618 sc->sc_ep0_busy = 0; 619 sc->sc_ep0_cmd |= MUSB2_MASK_CSR0L_DATAEND; 620 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, sc->sc_ep0_cmd); 621 sc->sc_ep0_cmd = 0; 622 } 623 /* read out FIFO status */ 624 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 625 626 DPRINTFN(4, "csr=0x%02x\n", csr); 627 628 if (csr & MUSB2_MASK_CSR0L_DATAEND) { 629 /* wait for interrupt */ 630 return (1); /* not complete */ 631 } 632 if (sc->sc_dv_addr != 0xFF) { 633 /* write function address */ 634 musbotg_set_address(sc, sc->sc_dv_addr); 635 } 636 return (0); /* complete */ 637} 638 639static uint8_t 640musbotg_data_rx(struct musbotg_td *td) 641{ 642 struct usb2_page_search buf_res; 643 struct musbotg_softc *sc; 644 uint16_t count; 645 uint8_t csr; 646 uint8_t to; 647 uint8_t got_short; 648 649 to = 8; /* don't loop forever! */ 650 got_short = 0; 651 652 /* get pointer to softc */ 653 sc = MUSBOTG_PC2SC(td->pc); 654 655 /* select endpoint */ 656 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, td->ep_no); 657 658repeat: 659 /* read out FIFO status */ 660 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL); 661 662 DPRINTFN(4, "csr=0x%02x\n", csr); 663 664 /* clear overrun */ 665 if (csr & MUSB2_MASK_CSRL_RXOVERRUN) { 666 /* make sure we don't clear "RXPKTRDY" */ 667 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 668 MUSB2_MASK_CSRL_RXPKTRDY); 669 } 670 /* check status */ 671 if (!(csr & MUSB2_MASK_CSRL_RXPKTRDY)) { 672 return (1); /* not complete */ 673 } 674 /* get the packet byte count */ 675 count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT); 676 677 DPRINTFN(4, "count=0x%04x\n", count); 678 679 /* 680 * Check for short or invalid packet: 681 */ 682 if (count != td->max_frame_size) { 683 if (count < td->max_frame_size) { 684 /* we have a short packet */ 685 td->short_pkt = 1; 686 got_short = 1; 687 } else { 688 /* invalid USB packet */ 689 td->error = 1; 690 return (0); /* we are complete */ 691 } 692 } 693 /* verify the packet byte count */ 694 if (count > td->remainder) { 695 /* invalid USB packet */ 696 td->error = 1; 697 return (0); /* we are complete */ 698 } 699 while (count > 0) { 700 uint32_t temp; 701 702 usb2_get_page(td->pc, td->offset, &buf_res); 703 704 /* get correct length */ 705 if (buf_res.length > count) { 706 buf_res.length = count; 707 } 708 /* check for unaligned memory address */ 709 if (USB_P2U(buf_res.buffer) & 3) { 710 711 temp = count & ~3; 712 713 if (temp) { 714 /* receive data 4 bytes at a time */ 715 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 716 MUSB2_REG_EPFIFO(td->ep_no), sc->sc_bounce_buf, 717 temp / 4); 718 } 719 temp = count & 3; 720 if (temp) { 721 /* receive data 1 byte at a time */ 722 bus_space_read_multi_1(sc->sc_io_tag, 723 sc->sc_io_hdl, MUSB2_REG_EPFIFO(td->ep_no), 724 ((void *)&sc->sc_bounce_buf[count / 4]), temp); 725 } 726 usb2_copy_in(td->pc, td->offset, 727 sc->sc_bounce_buf, count); 728 729 /* update offset and remainder */ 730 td->offset += count; 731 td->remainder -= count; 732 break; 733 } 734 /* check if we can optimise */ 735 if (buf_res.length >= 4) { 736 737 /* receive data 4 bytes at a time */ 738 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 739 MUSB2_REG_EPFIFO(td->ep_no), buf_res.buffer, 740 buf_res.length / 4); 741 742 temp = buf_res.length & ~3; 743 744 /* update counters */ 745 count -= temp; 746 td->offset += temp; 747 td->remainder -= temp; 748 continue; 749 } 750 /* receive data */ 751 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 752 MUSB2_REG_EPFIFO(td->ep_no), buf_res.buffer, 753 buf_res.length); 754 755 /* update counters */ 756 count -= buf_res.length; 757 td->offset += buf_res.length; 758 td->remainder -= buf_res.length; 759 } 760 761 /* clear status bits */ 762 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 0); 763 764 /* check if we are complete */ 765 if ((td->remainder == 0) || got_short) { 766 if (td->short_pkt) { 767 /* we are complete */ 768 return (0); 769 } 770 /* else need to receive a zero length packet */ 771 } 772 if (--to) { 773 goto repeat; 774 } 775 return (1); /* not complete */ 776} 777 778static uint8_t 779musbotg_data_tx(struct musbotg_td *td) 780{ 781 struct usb2_page_search buf_res; 782 struct musbotg_softc *sc; 783 uint16_t count; 784 uint8_t csr; 785 uint8_t to; 786 787 to = 8; /* don't loop forever! */ 788 789 /* get pointer to softc */ 790 sc = MUSBOTG_PC2SC(td->pc); 791 792 /* select endpoint */ 793 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, td->ep_no); 794 795repeat: 796 797 /* read out FIFO status */ 798 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 799 800 DPRINTFN(4, "csr=0x%02x\n", csr); 801 802 if (csr & (MUSB2_MASK_CSRL_TXINCOMP | 803 MUSB2_MASK_CSRL_TXUNDERRUN)) { 804 /* clear status bits */ 805 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0); 806 } 807 if (csr & MUSB2_MASK_CSRL_TXPKTRDY) { 808 return (1); /* not complete */ 809 } 810 /* check for short packet */ 811 count = td->max_frame_size; 812 if (td->remainder < count) { 813 /* we have a short packet */ 814 td->short_pkt = 1; 815 count = td->remainder; 816 } 817 while (count > 0) { 818 uint32_t temp; 819 820 usb2_get_page(td->pc, td->offset, &buf_res); 821 822 /* get correct length */ 823 if (buf_res.length > count) { 824 buf_res.length = count; 825 } 826 /* check for unaligned memory address */ 827 if (USB_P2U(buf_res.buffer) & 3) { 828 829 usb2_copy_out(td->pc, td->offset, 830 sc->sc_bounce_buf, count); 831 832 temp = count & ~3; 833 834 if (temp) { 835 /* transmit data 4 bytes at a time */ 836 bus_space_write_multi_4(sc->sc_io_tag, 837 sc->sc_io_hdl, MUSB2_REG_EPFIFO(td->ep_no), 838 sc->sc_bounce_buf, temp / 4); 839 } 840 temp = count & 3; 841 if (temp) { 842 /* receive data 1 byte at a time */ 843 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 844 MUSB2_REG_EPFIFO(td->ep_no), 845 ((void *)&sc->sc_bounce_buf[count / 4]), temp); 846 } 847 /* update offset and remainder */ 848 td->offset += count; 849 td->remainder -= count; 850 break; 851 } 852 /* check if we can optimise */ 853 if (buf_res.length >= 4) { 854 855 /* transmit data 4 bytes at a time */ 856 bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 857 MUSB2_REG_EPFIFO(td->ep_no), buf_res.buffer, 858 buf_res.length / 4); 859 860 temp = buf_res.length & ~3; 861 862 /* update counters */ 863 count -= temp; 864 td->offset += temp; 865 td->remainder -= temp; 866 continue; 867 } 868 /* transmit data */ 869 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 870 MUSB2_REG_EPFIFO(td->ep_no), buf_res.buffer, 871 buf_res.length); 872 873 /* update counters */ 874 count -= buf_res.length; 875 td->offset += buf_res.length; 876 td->remainder -= buf_res.length; 877 } 878 879 /* write command */ 880 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 881 MUSB2_MASK_CSRL_TXPKTRDY); 882 883 /* check remainder */ 884 if (td->remainder == 0) { 885 if (td->short_pkt) { 886 return (0); /* complete */ 887 } 888 /* else we need to transmit a short packet */ 889 } 890 if (--to) { 891 goto repeat; 892 } 893 return (1); /* not complete */ 894} 895 896static uint8_t 897musbotg_xfer_do_fifo(struct usb2_xfer *xfer) 898{ 899 struct musbotg_softc *sc; 900 struct musbotg_td *td; 901 902 DPRINTFN(8, "\n"); 903 904 td = xfer->td_transfer_cache; 905 while (1) { 906 if ((td->func) (td)) { 907 /* operation in progress */ 908 break; 909 } 910 if (((void *)td) == xfer->td_transfer_last) { 911 goto done; 912 } 913 if (td->error) { 914 goto done; 915 } else if (td->remainder > 0) { 916 /* 917 * We had a short transfer. If there is no alternate 918 * next, stop processing ! 919 */ 920 if (!td->alt_next) { 921 goto done; 922 } 923 } 924 /* 925 * Fetch the next transfer descriptor and transfer 926 * some flags to the next transfer descriptor 927 */ 928 td = td->obj_next; 929 xfer->td_transfer_cache = td; 930 } 931 return (1); /* not complete */ 932 933done: 934 sc = MUSBOTG_BUS2SC(xfer->xroot->bus); 935 936 /* compute all actual lengths */ 937 938 musbotg_standard_done(xfer); 939 940 return (0); /* complete */ 941} 942 943static void 944musbotg_interrupt_poll(struct musbotg_softc *sc) 945{ 946 struct usb2_xfer *xfer; 947 948repeat: 949 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 950 if (!musbotg_xfer_do_fifo(xfer)) { 951 /* queue has been modified */ 952 goto repeat; 953 } 954 } 955} 956 957void 958musbotg_vbus_interrupt(struct musbotg_softc *sc, uint8_t is_on) 959{ 960 DPRINTFN(4, "vbus = %u\n", is_on); 961 962 USB_BUS_LOCK(&sc->sc_bus); 963 if (is_on) { 964 if (!sc->sc_flags.status_vbus) { 965 sc->sc_flags.status_vbus = 1; 966 967 /* complete root HUB interrupt endpoint */ 968 969 usb2_sw_transfer(&sc->sc_root_intr, 970 &musbotg_root_intr_done); 971 } 972 } else { 973 if (sc->sc_flags.status_vbus) { 974 sc->sc_flags.status_vbus = 0; 975 sc->sc_flags.status_bus_reset = 0; 976 sc->sc_flags.status_suspend = 0; 977 sc->sc_flags.change_suspend = 0; 978 sc->sc_flags.change_connect = 1; 979 980 /* complete root HUB interrupt endpoint */ 981 982 usb2_sw_transfer(&sc->sc_root_intr, 983 &musbotg_root_intr_done); 984 } 985 } 986 987 USB_BUS_UNLOCK(&sc->sc_bus); 988} 989 990void 991musbotg_interrupt(struct musbotg_softc *sc) 992{ 993 uint16_t rx_status; 994 uint16_t tx_status; 995 uint8_t usb_status; 996 uint8_t temp; 997 uint8_t to = 2; 998 999 USB_BUS_LOCK(&sc->sc_bus); 1000 1001repeat: 1002 1003 /* read all interrupt registers */ 1004 usb_status = MUSB2_READ_1(sc, MUSB2_REG_INTUSB); 1005 1006 /* read all FIFO interrupts */ 1007 rx_status = MUSB2_READ_2(sc, MUSB2_REG_INTRX); 1008 tx_status = MUSB2_READ_2(sc, MUSB2_REG_INTTX); 1009 1010 /* check for any bus state change interrupts */ 1011 1012 if (usb_status & (MUSB2_MASK_IRESET | 1013 MUSB2_MASK_IRESUME | MUSB2_MASK_ISUSP)) { 1014 1015 DPRINTFN(4, "real bus interrupt 0x%08x\n", usb_status); 1016 1017 if (usb_status & MUSB2_MASK_IRESET) { 1018 1019 /* set correct state */ 1020 sc->sc_flags.status_bus_reset = 1; 1021 sc->sc_flags.status_suspend = 0; 1022 sc->sc_flags.change_suspend = 0; 1023 sc->sc_flags.change_connect = 1; 1024 1025 /* determine line speed */ 1026 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER); 1027 if (temp & MUSB2_MASK_HSMODE) 1028 sc->sc_flags.status_high_speed = 1; 1029 else 1030 sc->sc_flags.status_high_speed = 0; 1031 1032 /* 1033 * After reset all interrupts are on and we need to 1034 * turn them off! 1035 */ 1036 temp = MUSB2_MASK_IRESET; 1037 /* disable resume interrupt */ 1038 temp &= ~MUSB2_MASK_IRESUME; 1039 /* enable suspend interrupt */ 1040 temp |= MUSB2_MASK_ISUSP; 1041 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, temp); 1042 /* disable TX and RX interrupts */ 1043 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, 0); 1044 MUSB2_WRITE_2(sc, MUSB2_REG_INTRXE, 0); 1045 } 1046 /* 1047 * If RXRSM and RXSUSP is set at the same time we interpret 1048 * that like RESUME. Resume is set when there is at least 3 1049 * milliseconds of inactivity on the USB BUS. 1050 */ 1051 if (usb_status & MUSB2_MASK_IRESUME) { 1052 if (sc->sc_flags.status_suspend) { 1053 sc->sc_flags.status_suspend = 0; 1054 sc->sc_flags.change_suspend = 1; 1055 1056 temp = MUSB2_READ_1(sc, MUSB2_REG_INTUSBE); 1057 /* disable resume interrupt */ 1058 temp &= ~MUSB2_MASK_IRESUME; 1059 /* enable suspend interrupt */ 1060 temp |= MUSB2_MASK_ISUSP; 1061 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, temp); 1062 } 1063 } else if (usb_status & MUSB2_MASK_ISUSP) { 1064 if (!sc->sc_flags.status_suspend) { 1065 sc->sc_flags.status_suspend = 1; 1066 sc->sc_flags.change_suspend = 1; 1067 1068 temp = MUSB2_READ_1(sc, MUSB2_REG_INTUSBE); 1069 /* disable suspend interrupt */ 1070 temp &= ~MUSB2_MASK_ISUSP; 1071 /* enable resume interrupt */ 1072 temp |= MUSB2_MASK_IRESUME; 1073 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, temp); 1074 } 1075 } 1076 /* complete root HUB interrupt endpoint */ 1077 1078 usb2_sw_transfer(&sc->sc_root_intr, 1079 &musbotg_root_intr_done); 1080 } 1081 /* check for any endpoint interrupts */ 1082 1083 if (rx_status || tx_status) { 1084 DPRINTFN(4, "real endpoint interrupt " 1085 "rx=0x%04x, tx=0x%04x\n", rx_status, tx_status); 1086 } 1087 /* poll one time regardless of FIFO status */ 1088 1089 musbotg_interrupt_poll(sc); 1090 1091 if (--to) 1092 goto repeat; 1093 1094 USB_BUS_UNLOCK(&sc->sc_bus); 1095} 1096 1097static void 1098musbotg_setup_standard_chain_sub(struct musbotg_std_temp *temp) 1099{ 1100 struct musbotg_td *td; 1101 1102 /* get current Transfer Descriptor */ 1103 td = temp->td_next; 1104 temp->td = td; 1105 1106 /* prepare for next TD */ 1107 temp->td_next = td->obj_next; 1108 1109 /* fill out the Transfer Descriptor */ 1110 td->func = temp->func; 1111 td->pc = temp->pc; 1112 td->offset = temp->offset; 1113 td->remainder = temp->len; 1114 td->error = 0; 1115 td->did_stall = 0; 1116 td->short_pkt = temp->short_pkt; 1117 td->alt_next = temp->setup_alt_next; 1118} 1119 1120static void 1121musbotg_setup_standard_chain(struct usb2_xfer *xfer) 1122{ 1123 struct musbotg_std_temp temp; 1124 struct musbotg_softc *sc; 1125 struct musbotg_td *td; 1126 uint32_t x; 1127 uint8_t ep_no; 1128 1129 DPRINTFN(8, "addr=%d endpt=%d sumlen=%d speed=%d\n", 1130 xfer->address, UE_GET_ADDR(xfer->endpoint), 1131 xfer->sumlen, usb2_get_speed(xfer->xroot->udev)); 1132 1133 temp.max_frame_size = xfer->max_frame_size; 1134 1135 td = xfer->td_start[0]; 1136 xfer->td_transfer_first = td; 1137 xfer->td_transfer_cache = td; 1138 1139 /* setup temp */ 1140 1141 temp.td = NULL; 1142 temp.td_next = xfer->td_start[0]; 1143 temp.offset = 0; 1144 temp.setup_alt_next = xfer->flags_int.short_frames_ok; 1145 1146 sc = MUSBOTG_BUS2SC(xfer->xroot->bus); 1147 ep_no = (xfer->endpoint & UE_ADDR); 1148 1149 /* check if we should prepend a setup message */ 1150 1151 if (xfer->flags_int.control_xfr) { 1152 if (xfer->flags_int.control_hdr) { 1153 1154 temp.func = &musbotg_setup_rx; 1155 temp.len = xfer->frlengths[0]; 1156 temp.pc = xfer->frbuffers + 0; 1157 temp.short_pkt = temp.len ? 1 : 0; 1158 1159 musbotg_setup_standard_chain_sub(&temp); 1160 } 1161 x = 1; 1162 } else { 1163 x = 0; 1164 } 1165 1166 if (x != xfer->nframes) { 1167 if (xfer->endpoint & UE_DIR_IN) { 1168 if (xfer->flags_int.control_xfr) 1169 temp.func = &musbotg_setup_data_tx; 1170 else 1171 temp.func = &musbotg_data_tx; 1172 } else { 1173 if (xfer->flags_int.control_xfr) 1174 temp.func = &musbotg_setup_data_rx; 1175 else 1176 temp.func = &musbotg_data_rx; 1177 } 1178 1179 /* setup "pc" pointer */ 1180 temp.pc = xfer->frbuffers + x; 1181 } 1182 while (x != xfer->nframes) { 1183 1184 /* DATA0 / DATA1 message */ 1185 1186 temp.len = xfer->frlengths[x]; 1187 1188 x++; 1189 1190 if (x == xfer->nframes) { 1191 if (xfer->flags_int.control_xfr) { 1192 if (xfer->flags_int.control_act) { 1193 temp.setup_alt_next = 0; 1194 } 1195 } else { 1196 temp.setup_alt_next = 0; 1197 } 1198 } 1199 if (temp.len == 0) { 1200 1201 /* make sure that we send an USB packet */ 1202 1203 temp.short_pkt = 0; 1204 1205 } else { 1206 1207 /* regular data transfer */ 1208 1209 temp.short_pkt = (xfer->flags.force_short_xfer) ? 0 : 1; 1210 } 1211 1212 musbotg_setup_standard_chain_sub(&temp); 1213 1214 if (xfer->flags_int.isochronous_xfr) { 1215 temp.offset += temp.len; 1216 } else { 1217 /* get next Page Cache pointer */ 1218 temp.pc = xfer->frbuffers + x; 1219 } 1220 } 1221 1222 /* check for control transfer */ 1223 if (xfer->flags_int.control_xfr) { 1224 1225 /* always setup a valid "pc" pointer for status and sync */ 1226 temp.pc = xfer->frbuffers + 0; 1227 temp.len = 0; 1228 temp.short_pkt = 0; 1229 temp.setup_alt_next = 0; 1230 1231 /* check if we should append a status stage */ 1232 if (!xfer->flags_int.control_act) { 1233 /* 1234 * Send a DATA1 message and invert the current 1235 * endpoint direction. 1236 */ 1237 temp.func = &musbotg_setup_status; 1238 musbotg_setup_standard_chain_sub(&temp); 1239 } 1240 } 1241 /* must have at least one frame! */ 1242 td = temp.td; 1243 xfer->td_transfer_last = td; 1244} 1245 1246static void 1247musbotg_timeout(void *arg) 1248{ 1249 struct usb2_xfer *xfer = arg; 1250 1251 DPRINTFN(1, "xfer=%p\n", xfer); 1252 1253 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 1254 1255 /* transfer is transferred */ 1256 musbotg_device_done(xfer, USB_ERR_TIMEOUT); 1257} 1258 1259static void 1260musbotg_ep_int_set(struct usb2_xfer *xfer, uint8_t on) 1261{ 1262 struct musbotg_softc *sc = MUSBOTG_BUS2SC(xfer->xroot->bus); 1263 uint16_t temp; 1264 uint8_t ep_no = xfer->endpoint & UE_ADDR; 1265 1266 /* 1267 * Only enable the endpoint interrupt when we are 1268 * actually waiting for data, hence we are dealing 1269 * with level triggered interrupts ! 1270 */ 1271 if (ep_no == 0) { 1272 temp = MUSB2_READ_2(sc, MUSB2_REG_INTTXE); 1273 if (on) 1274 temp |= MUSB2_MASK_EPINT(0); 1275 else 1276 temp &= ~MUSB2_MASK_EPINT(0); 1277 1278 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, temp); 1279 } else { 1280 if (USB_GET_DATA_ISREAD(xfer)) { 1281 temp = MUSB2_READ_2(sc, MUSB2_REG_INTRXE); 1282 if (on) 1283 temp |= MUSB2_MASK_EPINT(ep_no); 1284 else 1285 temp &= ~MUSB2_MASK_EPINT(ep_no); 1286 MUSB2_WRITE_2(sc, MUSB2_REG_INTRXE, temp); 1287 1288 } else { 1289 temp = MUSB2_READ_2(sc, MUSB2_REG_INTTXE); 1290 if (on) 1291 temp |= MUSB2_MASK_EPINT(ep_no); 1292 else 1293 temp &= ~MUSB2_MASK_EPINT(ep_no); 1294 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, temp); 1295 } 1296 } 1297} 1298 1299static void 1300musbotg_start_standard_chain(struct usb2_xfer *xfer) 1301{ 1302 DPRINTFN(8, "\n"); 1303 1304 /* poll one time */ 1305 if (musbotg_xfer_do_fifo(xfer)) { 1306 1307 musbotg_ep_int_set(xfer, 1); 1308 1309 DPRINTFN(14, "enabled interrupts on endpoint\n"); 1310 1311 /* put transfer on interrupt queue */ 1312 usb2_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 1313 1314 /* start timeout, if any */ 1315 if (xfer->timeout != 0) { 1316 usb2_transfer_timeout_ms(xfer, 1317 &musbotg_timeout, xfer->timeout); 1318 } 1319 } 1320} 1321 1322static void 1323musbotg_root_intr_done(struct usb2_xfer *xfer, 1324 struct usb2_sw_transfer *std) 1325{ 1326 struct musbotg_softc *sc = MUSBOTG_BUS2SC(xfer->xroot->bus); 1327 1328 DPRINTFN(8, "\n"); 1329 1330 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1331 1332 if (std->state != USB_SW_TR_PRE_DATA) { 1333 if (std->state == USB_SW_TR_PRE_CALLBACK) { 1334 /* transfer transferred */ 1335 musbotg_device_done(xfer, std->err); 1336 } 1337 goto done; 1338 } 1339 /* setup buffer */ 1340 std->ptr = sc->sc_hub_idata; 1341 std->len = sizeof(sc->sc_hub_idata); 1342 1343 /* set port bit */ 1344 sc->sc_hub_idata[0] = 0x02; /* we only have one port */ 1345 1346done: 1347 return; 1348} 1349 1350static usb2_error_t 1351musbotg_standard_done_sub(struct usb2_xfer *xfer) 1352{ 1353 struct musbotg_td *td; 1354 uint32_t len; 1355 uint8_t error; 1356 1357 DPRINTFN(8, "\n"); 1358 1359 td = xfer->td_transfer_cache; 1360 1361 do { 1362 len = td->remainder; 1363 1364 if (xfer->aframes != xfer->nframes) { 1365 /* 1366 * Verify the length and subtract 1367 * the remainder from "frlengths[]": 1368 */ 1369 if (len > xfer->frlengths[xfer->aframes]) { 1370 td->error = 1; 1371 } else { 1372 xfer->frlengths[xfer->aframes] -= len; 1373 } 1374 } 1375 /* Check for transfer error */ 1376 if (td->error) { 1377 /* the transfer is finished */ 1378 error = 1; 1379 td = NULL; 1380 break; 1381 } 1382 /* Check for short transfer */ 1383 if (len > 0) { 1384 if (xfer->flags_int.short_frames_ok) { 1385 /* follow alt next */ 1386 if (td->alt_next) { 1387 td = td->obj_next; 1388 } else { 1389 td = NULL; 1390 } 1391 } else { 1392 /* the transfer is finished */ 1393 td = NULL; 1394 } 1395 error = 0; 1396 break; 1397 } 1398 td = td->obj_next; 1399 1400 /* this USB frame is complete */ 1401 error = 0; 1402 break; 1403 1404 } while (0); 1405 1406 /* update transfer cache */ 1407 1408 xfer->td_transfer_cache = td; 1409 1410 return (error ? 1411 USB_ERR_STALLED : USB_ERR_NORMAL_COMPLETION); 1412} 1413 1414static void 1415musbotg_standard_done(struct usb2_xfer *xfer) 1416{ 1417 usb2_error_t err = 0; 1418 1419 DPRINTFN(12, "xfer=%p pipe=%p transfer done\n", 1420 xfer, xfer->pipe); 1421 1422 /* reset scanner */ 1423 1424 xfer->td_transfer_cache = xfer->td_transfer_first; 1425 1426 if (xfer->flags_int.control_xfr) { 1427 1428 if (xfer->flags_int.control_hdr) { 1429 1430 err = musbotg_standard_done_sub(xfer); 1431 } 1432 xfer->aframes = 1; 1433 1434 if (xfer->td_transfer_cache == NULL) { 1435 goto done; 1436 } 1437 } 1438 while (xfer->aframes != xfer->nframes) { 1439 1440 err = musbotg_standard_done_sub(xfer); 1441 xfer->aframes++; 1442 1443 if (xfer->td_transfer_cache == NULL) { 1444 goto done; 1445 } 1446 } 1447 1448 if (xfer->flags_int.control_xfr && 1449 !xfer->flags_int.control_act) { 1450 1451 err = musbotg_standard_done_sub(xfer); 1452 } 1453done: 1454 musbotg_device_done(xfer, err); 1455} 1456 1457/*------------------------------------------------------------------------* 1458 * musbotg_device_done 1459 * 1460 * NOTE: this function can be called more than one time on the 1461 * same USB transfer! 1462 *------------------------------------------------------------------------*/ 1463static void 1464musbotg_device_done(struct usb2_xfer *xfer, usb2_error_t error) 1465{ 1466 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 1467 1468 DPRINTFN(2, "xfer=%p, pipe=%p, error=%d\n", 1469 xfer, xfer->pipe, error); 1470 1471 if (xfer->flags_int.usb2_mode == USB_MODE_DEVICE) { 1472 1473 musbotg_ep_int_set(xfer, 0); 1474 1475 DPRINTFN(14, "disabled interrupts on endpoint\n"); 1476 } 1477 /* dequeue transfer and start next transfer */ 1478 usb2_transfer_done(xfer, error); 1479} 1480 1481static void 1482musbotg_set_stall(struct usb2_device *udev, struct usb2_xfer *xfer, 1483 struct usb2_pipe *pipe) 1484{ 1485 struct musbotg_softc *sc; 1486 uint8_t ep_no; 1487 1488 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 1489 1490 DPRINTFN(4, "pipe=%p\n", pipe); 1491 1492 if (xfer) { 1493 /* cancel any ongoing transfers */ 1494 musbotg_device_done(xfer, USB_ERR_STALLED); 1495 } 1496 /* set FORCESTALL */ 1497 sc = MUSBOTG_BUS2SC(udev->bus); 1498 1499 ep_no = (pipe->edesc->bEndpointAddress & UE_ADDR); 1500 1501 /* select endpoint */ 1502 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, ep_no); 1503 1504 if (pipe->edesc->bEndpointAddress & UE_DIR_IN) { 1505 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 1506 MUSB2_MASK_CSRL_TXSENDSTALL); 1507 } else { 1508 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 1509 MUSB2_MASK_CSRL_RXSENDSTALL); 1510 } 1511} 1512 1513static void 1514musbotg_clear_stall_sub(struct musbotg_softc *sc, uint16_t wMaxPacket, 1515 uint8_t ep_no, uint8_t ep_type, uint8_t ep_dir) 1516{ 1517 uint16_t mps; 1518 uint16_t temp; 1519 uint8_t csr; 1520 1521 if (ep_type == UE_CONTROL) { 1522 /* clearing stall is not needed */ 1523 return; 1524 } 1525 /* select endpoint */ 1526 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, ep_no); 1527 1528 /* compute max frame size */ 1529 mps = wMaxPacket & 0x7FF; 1530 switch ((wMaxPacket >> 11) & 3) { 1531 case 1: 1532 mps *= 2; 1533 break; 1534 case 2: 1535 mps *= 3; 1536 break; 1537 default: 1538 break; 1539 } 1540 1541 if (ep_dir == UE_DIR_IN) { 1542 1543 temp = 0; 1544 1545 /* Configure endpoint */ 1546 switch (ep_type) { 1547 case UE_INTERRUPT: 1548 MUSB2_WRITE_1(sc, MUSB2_REG_TXMAXP, wMaxPacket); 1549 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, 1550 MUSB2_MASK_CSRH_TXMODE | temp); 1551 break; 1552 case UE_ISOCHRONOUS: 1553 MUSB2_WRITE_1(sc, MUSB2_REG_TXMAXP, wMaxPacket); 1554 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, 1555 MUSB2_MASK_CSRH_TXMODE | 1556 MUSB2_MASK_CSRH_TXISO | temp); 1557 break; 1558 case UE_BULK: 1559 MUSB2_WRITE_1(sc, MUSB2_REG_TXMAXP, wMaxPacket); 1560 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, 1561 MUSB2_MASK_CSRH_TXMODE | temp); 1562 break; 1563 default: 1564 break; 1565 } 1566 1567 /* Need to flush twice in case of double bufring */ 1568 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 1569 if (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) { 1570 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 1571 MUSB2_MASK_CSRL_TXFFLUSH); 1572 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 1573 if (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) { 1574 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 1575 MUSB2_MASK_CSRL_TXFFLUSH); 1576 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 1577 } 1578 } 1579 /* reset data toggle */ 1580 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 1581 MUSB2_MASK_CSRL_TXDT_CLR); 1582 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0); 1583 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 1584 1585 /* set double/single buffering */ 1586 temp = MUSB2_READ_2(sc, MUSB2_REG_TXDBDIS); 1587 if (mps <= (sc->sc_hw_ep_profile[ep_no]. 1588 max_in_frame_size / 2)) { 1589 /* double buffer */ 1590 temp &= ~(1 << ep_no); 1591 } else { 1592 /* single buffer */ 1593 temp |= (1 << ep_no); 1594 } 1595 MUSB2_WRITE_2(sc, MUSB2_REG_TXDBDIS, temp); 1596 1597 /* clear sent stall */ 1598 if (csr & MUSB2_MASK_CSRL_TXSENTSTALL) { 1599 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0); 1600 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 1601 } 1602 } else { 1603 1604 temp = 0; 1605 1606 /* Configure endpoint */ 1607 switch (ep_type) { 1608 case UE_INTERRUPT: 1609 MUSB2_WRITE_1(sc, MUSB2_REG_RXMAXP, wMaxPacket); 1610 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH, 1611 MUSB2_MASK_CSRH_RXNYET | temp); 1612 break; 1613 case UE_ISOCHRONOUS: 1614 MUSB2_WRITE_1(sc, MUSB2_REG_RXMAXP, wMaxPacket); 1615 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH, 1616 MUSB2_MASK_CSRH_RXNYET | 1617 MUSB2_MASK_CSRH_RXISO | temp); 1618 break; 1619 case UE_BULK: 1620 MUSB2_WRITE_1(sc, MUSB2_REG_RXMAXP, wMaxPacket); 1621 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH, temp); 1622 break; 1623 default: 1624 break; 1625 } 1626 1627 /* Need to flush twice in case of double bufring */ 1628 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL); 1629 if (csr & MUSB2_MASK_CSRL_RXPKTRDY) { 1630 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 1631 MUSB2_MASK_CSRL_RXFFLUSH); 1632 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL); 1633 if (csr & MUSB2_MASK_CSRL_RXPKTRDY) { 1634 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 1635 MUSB2_MASK_CSRL_RXFFLUSH); 1636 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL); 1637 } 1638 } 1639 /* reset data toggle */ 1640 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 1641 MUSB2_MASK_CSRL_RXDT_CLR); 1642 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 0); 1643 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL); 1644 1645 /* set double/single buffering */ 1646 temp = MUSB2_READ_2(sc, MUSB2_REG_RXDBDIS); 1647 if (mps <= (sc->sc_hw_ep_profile[ep_no]. 1648 max_out_frame_size / 2)) { 1649 /* double buffer */ 1650 temp &= ~(1 << ep_no); 1651 } else { 1652 /* single buffer */ 1653 temp |= (1 << ep_no); 1654 } 1655 MUSB2_WRITE_2(sc, MUSB2_REG_RXDBDIS, temp); 1656 1657 /* clear sent stall */ 1658 if (csr & MUSB2_MASK_CSRL_RXSENTSTALL) { 1659 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 0); 1660 } 1661 } 1662} 1663 1664static void 1665musbotg_clear_stall(struct usb2_device *udev, struct usb2_pipe *pipe) 1666{ 1667 struct musbotg_softc *sc; 1668 struct usb2_endpoint_descriptor *ed; 1669 1670 DPRINTFN(4, "pipe=%p\n", pipe); 1671 1672 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 1673 1674 /* check mode */ 1675 if (udev->flags.usb2_mode != USB_MODE_DEVICE) { 1676 /* not supported */ 1677 return; 1678 } 1679 /* get softc */ 1680 sc = MUSBOTG_BUS2SC(udev->bus); 1681 1682 /* get endpoint descriptor */ 1683 ed = pipe->edesc; 1684 1685 /* reset endpoint */ 1686 musbotg_clear_stall_sub(sc, 1687 UGETW(ed->wMaxPacketSize), 1688 (ed->bEndpointAddress & UE_ADDR), 1689 (ed->bmAttributes & UE_XFERTYPE), 1690 (ed->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT))); 1691} 1692 1693usb2_error_t 1694musbotg_init(struct musbotg_softc *sc) 1695{ 1696 struct usb2_hw_ep_profile *pf; 1697 uint8_t nrx; 1698 uint8_t ntx; 1699 uint8_t temp; 1700 uint8_t fsize; 1701 uint8_t frx; 1702 uint8_t ftx; 1703 1704 DPRINTFN(1, "start\n"); 1705 1706 /* set up the bus structure */ 1707 sc->sc_bus.usbrev = USB_REV_2_0; 1708 sc->sc_bus.methods = &musbotg_bus_methods; 1709 1710 USB_BUS_LOCK(&sc->sc_bus); 1711 1712 /* turn on clocks */ 1713 1714 if (sc->sc_clocks_on) { 1715 (sc->sc_clocks_on) (sc->sc_clocks_arg); 1716 } 1717 /* wait a little for things to stabilise */ 1718 usb2_pause_mtx(&sc->sc_bus.bus_mtx, hz / 1000); 1719 1720 /* disable all interrupts */ 1721 1722 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, 0); 1723 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, 0); 1724 MUSB2_WRITE_2(sc, MUSB2_REG_INTRXE, 0); 1725 1726 /* disable pullup */ 1727 1728 musbotg_pull_common(sc, 0); 1729 1730 /* wait a little bit (10ms) */ 1731 usb2_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100); 1732 1733 /* disable double packet buffering */ 1734 MUSB2_WRITE_2(sc, MUSB2_REG_RXDBDIS, 0xFFFF); 1735 MUSB2_WRITE_2(sc, MUSB2_REG_TXDBDIS, 0xFFFF); 1736 1737 /* enable HighSpeed and ISO Update flags */ 1738 1739 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, 1740 MUSB2_MASK_HSENAB | MUSB2_MASK_ISOUPD); 1741 1742 /* clear Session bit, if set */ 1743 1744 temp = MUSB2_READ_1(sc, MUSB2_REG_DEVCTL); 1745 temp &= ~MUSB2_MASK_SESS; 1746 MUSB2_WRITE_1(sc, MUSB2_REG_DEVCTL, temp); 1747 1748 DPRINTF("DEVCTL=0x%02x\n", temp); 1749 1750 /* disable testmode */ 1751 1752 MUSB2_WRITE_1(sc, MUSB2_REG_TESTMODE, 0); 1753 1754 /* set default value */ 1755 1756 MUSB2_WRITE_1(sc, MUSB2_REG_MISC, 0); 1757 1758 /* select endpoint index 0 */ 1759 1760 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); 1761 1762 /* read out number of endpoints */ 1763 1764 nrx = 1765 (MUSB2_READ_1(sc, MUSB2_REG_EPINFO) / 16); 1766 1767 ntx = 1768 (MUSB2_READ_1(sc, MUSB2_REG_EPINFO) % 16); 1769 1770 /* these numbers exclude the control endpoint */ 1771 1772 DPRINTFN(2, "RX/TX endpoints: %u/%u\n", nrx, ntx); 1773 1774 sc->sc_ep_max = (nrx > ntx) ? nrx : ntx; 1775 if (sc->sc_ep_max == 0) { 1776 DPRINTFN(2, "ERROR: Looks like the clocks are off!\n"); 1777 } 1778 /* read out configuration data */ 1779 1780 sc->sc_conf_data = MUSB2_READ_1(sc, MUSB2_REG_CONFDATA); 1781 1782 DPRINTFN(2, "Config Data: 0x%02x\n", 1783 sc->sc_conf_data); 1784 1785 DPRINTFN(2, "HW version: 0x%04x\n", 1786 MUSB2_READ_1(sc, MUSB2_REG_HWVERS)); 1787 1788 /* initialise endpoint profiles */ 1789 1790 for (temp = 1; temp <= sc->sc_ep_max; temp++) { 1791 pf = sc->sc_hw_ep_profile + temp; 1792 1793 /* select endpoint */ 1794 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, temp); 1795 1796 fsize = MUSB2_READ_1(sc, MUSB2_REG_FSIZE); 1797 frx = (fsize & MUSB2_MASK_RX_FSIZE) / 16;; 1798 ftx = (fsize & MUSB2_MASK_TX_FSIZE); 1799 1800 DPRINTF("Endpoint %u FIFO size: IN=%u, OUT=%u\n", 1801 temp, pf->max_in_frame_size, 1802 pf->max_out_frame_size); 1803 1804 if (frx && ftx && (temp <= nrx) && (temp <= ntx)) { 1805 pf->max_in_frame_size = 1 << ftx; 1806 pf->max_out_frame_size = 1 << frx; 1807 pf->is_simplex = 0; /* duplex */ 1808 pf->support_multi_buffer = 1; 1809 pf->support_bulk = 1; 1810 pf->support_interrupt = 1; 1811 pf->support_isochronous = 1; 1812 pf->support_in = 1; 1813 pf->support_out = 1; 1814 } else if (frx && (temp <= nrx)) { 1815 pf->max_out_frame_size = 1 << frx; 1816 pf->is_simplex = 1; /* simplex */ 1817 pf->support_multi_buffer = 1; 1818 pf->support_bulk = 1; 1819 pf->support_interrupt = 1; 1820 pf->support_isochronous = 1; 1821 pf->support_out = 1; 1822 } else if (ftx && (temp <= ntx)) { 1823 pf->max_in_frame_size = 1 << ftx; 1824 pf->is_simplex = 1; /* simplex */ 1825 pf->support_multi_buffer = 1; 1826 pf->support_bulk = 1; 1827 pf->support_interrupt = 1; 1828 pf->support_isochronous = 1; 1829 pf->support_in = 1; 1830 } 1831 } 1832 1833 /* turn on default interrupts */ 1834 1835 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, 1836 MUSB2_MASK_IRESET); 1837 1838 musbotg_clocks_off(sc); 1839 1840 USB_BUS_UNLOCK(&sc->sc_bus); 1841 1842 /* catch any lost interrupts */ 1843 1844 musbotg_do_poll(&sc->sc_bus); 1845 1846 return (0); /* success */ 1847} 1848 1849void 1850musbotg_uninit(struct musbotg_softc *sc) 1851{ 1852 USB_BUS_LOCK(&sc->sc_bus); 1853 1854 /* disable all interrupts */ 1855 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, 0); 1856 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, 0); 1857 MUSB2_WRITE_2(sc, MUSB2_REG_INTRXE, 0); 1858 1859 sc->sc_flags.port_powered = 0; 1860 sc->sc_flags.status_vbus = 0; 1861 sc->sc_flags.status_bus_reset = 0; 1862 sc->sc_flags.status_suspend = 0; 1863 sc->sc_flags.change_suspend = 0; 1864 sc->sc_flags.change_connect = 1; 1865 1866 musbotg_pull_down(sc); 1867 musbotg_clocks_off(sc); 1868 USB_BUS_UNLOCK(&sc->sc_bus); 1869} 1870 1871void 1872musbotg_suspend(struct musbotg_softc *sc) 1873{ 1874 return; 1875} 1876 1877void 1878musbotg_resume(struct musbotg_softc *sc) 1879{ 1880 return; 1881} 1882 1883static void 1884musbotg_do_poll(struct usb2_bus *bus) 1885{ 1886 struct musbotg_softc *sc = MUSBOTG_BUS2SC(bus); 1887 1888 USB_BUS_LOCK(&sc->sc_bus); 1889 musbotg_interrupt_poll(sc); 1890 musbotg_root_ctrl_poll(sc); 1891 USB_BUS_UNLOCK(&sc->sc_bus); 1892} 1893 1894/*------------------------------------------------------------------------* 1895 * musbotg bulk support 1896 *------------------------------------------------------------------------*/ 1897static void 1898musbotg_device_bulk_open(struct usb2_xfer *xfer) 1899{ 1900 return; 1901} 1902 1903static void 1904musbotg_device_bulk_close(struct usb2_xfer *xfer) 1905{ 1906 musbotg_device_done(xfer, USB_ERR_CANCELLED); 1907} 1908 1909static void 1910musbotg_device_bulk_enter(struct usb2_xfer *xfer) 1911{ 1912 return; 1913} 1914 1915static void 1916musbotg_device_bulk_start(struct usb2_xfer *xfer) 1917{ 1918 /* setup TDs */ 1919 musbotg_setup_standard_chain(xfer); 1920 musbotg_start_standard_chain(xfer); 1921} 1922 1923struct usb2_pipe_methods musbotg_device_bulk_methods = 1924{ 1925 .open = musbotg_device_bulk_open, 1926 .close = musbotg_device_bulk_close, 1927 .enter = musbotg_device_bulk_enter, 1928 .start = musbotg_device_bulk_start, 1929 .enter_is_cancelable = 1, 1930 .start_is_cancelable = 1, 1931}; 1932 1933/*------------------------------------------------------------------------* 1934 * musbotg control support 1935 *------------------------------------------------------------------------*/ 1936static void 1937musbotg_device_ctrl_open(struct usb2_xfer *xfer) 1938{ 1939 return; 1940} 1941 1942static void 1943musbotg_device_ctrl_close(struct usb2_xfer *xfer) 1944{ 1945 musbotg_device_done(xfer, USB_ERR_CANCELLED); 1946} 1947 1948static void 1949musbotg_device_ctrl_enter(struct usb2_xfer *xfer) 1950{ 1951 return; 1952} 1953 1954static void 1955musbotg_device_ctrl_start(struct usb2_xfer *xfer) 1956{ 1957 /* setup TDs */ 1958 musbotg_setup_standard_chain(xfer); 1959 musbotg_start_standard_chain(xfer); 1960} 1961 1962struct usb2_pipe_methods musbotg_device_ctrl_methods = 1963{ 1964 .open = musbotg_device_ctrl_open, 1965 .close = musbotg_device_ctrl_close, 1966 .enter = musbotg_device_ctrl_enter, 1967 .start = musbotg_device_ctrl_start, 1968 .enter_is_cancelable = 1, 1969 .start_is_cancelable = 1, 1970}; 1971 1972/*------------------------------------------------------------------------* 1973 * musbotg interrupt support 1974 *------------------------------------------------------------------------*/ 1975static void 1976musbotg_device_intr_open(struct usb2_xfer *xfer) 1977{ 1978 return; 1979} 1980 1981static void 1982musbotg_device_intr_close(struct usb2_xfer *xfer) 1983{ 1984 musbotg_device_done(xfer, USB_ERR_CANCELLED); 1985} 1986 1987static void 1988musbotg_device_intr_enter(struct usb2_xfer *xfer) 1989{ 1990 return; 1991} 1992 1993static void 1994musbotg_device_intr_start(struct usb2_xfer *xfer) 1995{ 1996 /* setup TDs */ 1997 musbotg_setup_standard_chain(xfer); 1998 musbotg_start_standard_chain(xfer); 1999} 2000 2001struct usb2_pipe_methods musbotg_device_intr_methods = 2002{ 2003 .open = musbotg_device_intr_open, 2004 .close = musbotg_device_intr_close, 2005 .enter = musbotg_device_intr_enter, 2006 .start = musbotg_device_intr_start, 2007 .enter_is_cancelable = 1, 2008 .start_is_cancelable = 1, 2009}; 2010 2011/*------------------------------------------------------------------------* 2012 * musbotg full speed isochronous support 2013 *------------------------------------------------------------------------*/ 2014static void 2015musbotg_device_isoc_open(struct usb2_xfer *xfer) 2016{ 2017 return; 2018} 2019 2020static void 2021musbotg_device_isoc_close(struct usb2_xfer *xfer) 2022{ 2023 musbotg_device_done(xfer, USB_ERR_CANCELLED); 2024} 2025 2026static void 2027musbotg_device_isoc_enter(struct usb2_xfer *xfer) 2028{ 2029 struct musbotg_softc *sc = MUSBOTG_BUS2SC(xfer->xroot->bus); 2030 uint32_t temp; 2031 uint32_t nframes; 2032 uint32_t fs_frames; 2033 2034 DPRINTFN(5, "xfer=%p next=%d nframes=%d\n", 2035 xfer, xfer->pipe->isoc_next, xfer->nframes); 2036 2037 /* get the current frame index */ 2038 2039 nframes = MUSB2_READ_2(sc, MUSB2_REG_FRAME); 2040 2041 /* 2042 * check if the frame index is within the window where the frames 2043 * will be inserted 2044 */ 2045 temp = (nframes - xfer->pipe->isoc_next) & MUSB2_MASK_FRAME; 2046 2047 if (usb2_get_speed(xfer->xroot->udev) == USB_SPEED_HIGH) { 2048 fs_frames = (xfer->nframes + 7) / 8; 2049 } else { 2050 fs_frames = xfer->nframes; 2051 } 2052 2053 if ((xfer->pipe->is_synced == 0) || 2054 (temp < fs_frames)) { 2055 /* 2056 * If there is data underflow or the pipe queue is 2057 * empty we schedule the transfer a few frames ahead 2058 * of the current frame position. Else two isochronous 2059 * transfers might overlap. 2060 */ 2061 xfer->pipe->isoc_next = (nframes + 3) & MUSB2_MASK_FRAME; 2062 xfer->pipe->is_synced = 1; 2063 DPRINTFN(2, "start next=%d\n", xfer->pipe->isoc_next); 2064 } 2065 /* 2066 * compute how many milliseconds the insertion is ahead of the 2067 * current frame position: 2068 */ 2069 temp = (xfer->pipe->isoc_next - nframes) & MUSB2_MASK_FRAME; 2070 2071 /* 2072 * pre-compute when the isochronous transfer will be finished: 2073 */ 2074 xfer->isoc_time_complete = 2075 usb2_isoc_time_expand(&sc->sc_bus, nframes) + temp + 2076 fs_frames; 2077 2078 /* compute frame number for next insertion */ 2079 xfer->pipe->isoc_next += fs_frames; 2080 2081 /* setup TDs */ 2082 musbotg_setup_standard_chain(xfer); 2083} 2084 2085static void 2086musbotg_device_isoc_start(struct usb2_xfer *xfer) 2087{ 2088 /* start TD chain */ 2089 musbotg_start_standard_chain(xfer); 2090} 2091 2092struct usb2_pipe_methods musbotg_device_isoc_methods = 2093{ 2094 .open = musbotg_device_isoc_open, 2095 .close = musbotg_device_isoc_close, 2096 .enter = musbotg_device_isoc_enter, 2097 .start = musbotg_device_isoc_start, 2098 .enter_is_cancelable = 1, 2099 .start_is_cancelable = 1, 2100}; 2101 2102/*------------------------------------------------------------------------* 2103 * musbotg root control support 2104 *------------------------------------------------------------------------* 2105 * simulate a hardware HUB by handling 2106 * all the necessary requests 2107 *------------------------------------------------------------------------*/ 2108static void 2109musbotg_root_ctrl_open(struct usb2_xfer *xfer) 2110{ 2111 return; 2112} 2113 2114static void 2115musbotg_root_ctrl_close(struct usb2_xfer *xfer) 2116{ 2117 struct musbotg_softc *sc = MUSBOTG_BUS2SC(xfer->xroot->bus); 2118 2119 if (sc->sc_root_ctrl.xfer == xfer) { 2120 sc->sc_root_ctrl.xfer = NULL; 2121 } 2122 musbotg_device_done(xfer, USB_ERR_CANCELLED); 2123} 2124 2125/* 2126 * USB descriptors for the virtual Root HUB: 2127 */ 2128 2129static const struct usb2_device_descriptor musbotg_devd = { 2130 .bLength = sizeof(struct usb2_device_descriptor), 2131 .bDescriptorType = UDESC_DEVICE, 2132 .bcdUSB = {0x00, 0x02}, 2133 .bDeviceClass = UDCLASS_HUB, 2134 .bDeviceSubClass = UDSUBCLASS_HUB, 2135 .bDeviceProtocol = UDPROTO_HSHUBSTT, 2136 .bMaxPacketSize = 64, 2137 .bcdDevice = {0x00, 0x01}, 2138 .iManufacturer = 1, 2139 .iProduct = 2, 2140 .bNumConfigurations = 1, 2141}; 2142 2143static const struct usb2_device_qualifier musbotg_odevd = { 2144 .bLength = sizeof(struct usb2_device_qualifier), 2145 .bDescriptorType = UDESC_DEVICE_QUALIFIER, 2146 .bcdUSB = {0x00, 0x02}, 2147 .bDeviceClass = UDCLASS_HUB, 2148 .bDeviceSubClass = UDSUBCLASS_HUB, 2149 .bDeviceProtocol = UDPROTO_FSHUB, 2150 .bMaxPacketSize0 = 0, 2151 .bNumConfigurations = 0, 2152}; 2153 2154static const struct musbotg_config_desc musbotg_confd = { 2155 .confd = { 2156 .bLength = sizeof(struct usb2_config_descriptor), 2157 .bDescriptorType = UDESC_CONFIG, 2158 .wTotalLength[0] = sizeof(musbotg_confd), 2159 .bNumInterface = 1, 2160 .bConfigurationValue = 1, 2161 .iConfiguration = 0, 2162 .bmAttributes = UC_SELF_POWERED, 2163 .bMaxPower = 0, 2164 }, 2165 .ifcd = { 2166 .bLength = sizeof(struct usb2_interface_descriptor), 2167 .bDescriptorType = UDESC_INTERFACE, 2168 .bNumEndpoints = 1, 2169 .bInterfaceClass = UICLASS_HUB, 2170 .bInterfaceSubClass = UISUBCLASS_HUB, 2171 .bInterfaceProtocol = UIPROTO_HSHUBSTT, 2172 }, 2173 2174 .endpd = { 2175 .bLength = sizeof(struct usb2_endpoint_descriptor), 2176 .bDescriptorType = UDESC_ENDPOINT, 2177 .bEndpointAddress = (UE_DIR_IN | MUSBOTG_INTR_ENDPT), 2178 .bmAttributes = UE_INTERRUPT, 2179 .wMaxPacketSize[0] = 8, 2180 .bInterval = 255, 2181 }, 2182}; 2183 2184static const struct usb2_hub_descriptor_min musbotg_hubd = { 2185 .bDescLength = sizeof(musbotg_hubd), 2186 .bDescriptorType = UDESC_HUB, 2187 .bNbrPorts = 1, 2188 .wHubCharacteristics[0] = 2189 (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL) & 0xFF, 2190 .wHubCharacteristics[1] = 2191 (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL) >> 16, 2192 .bPwrOn2PwrGood = 50, 2193 .bHubContrCurrent = 0, 2194 .DeviceRemovable = {0}, /* port is removable */ 2195}; 2196 2197#define STRING_LANG \ 2198 0x09, 0x04, /* American English */ 2199 2200#define STRING_VENDOR \ 2201 'M', 0, 'e', 0, 'n', 0, 't', 0, 'o', 0, 'r', 0, ' ', 0, \ 2202 'G', 0, 'r', 0, 'a', 0, 'p', 0, 'h', 0, 'i', 0, 'c', 0, 's', 0 2203 2204#define STRING_PRODUCT \ 2205 'O', 0, 'T', 0, 'G', 0, ' ', 0, 'R', 0, \ 2206 'o', 0, 'o', 0, 't', 0, ' ', 0, 'H', 0, \ 2207 'U', 0, 'B', 0, 2208 2209USB_MAKE_STRING_DESC(STRING_LANG, musbotg_langtab); 2210USB_MAKE_STRING_DESC(STRING_VENDOR, musbotg_vendor); 2211USB_MAKE_STRING_DESC(STRING_PRODUCT, musbotg_product); 2212 2213static void 2214musbotg_root_ctrl_enter(struct usb2_xfer *xfer) 2215{ 2216 return; 2217} 2218 2219static void 2220musbotg_root_ctrl_start(struct usb2_xfer *xfer) 2221{ 2222 struct musbotg_softc *sc = MUSBOTG_BUS2SC(xfer->xroot->bus); 2223 2224 sc->sc_root_ctrl.xfer = xfer; 2225 2226 usb2_bus_roothub_exec(xfer->xroot->bus); 2227} 2228 2229static void 2230musbotg_root_ctrl_task(struct usb2_bus *bus) 2231{ 2232 musbotg_root_ctrl_poll(MUSBOTG_BUS2SC(bus)); 2233} 2234 2235static void 2236musbotg_root_ctrl_done(struct usb2_xfer *xfer, 2237 struct usb2_sw_transfer *std) 2238{ 2239 struct musbotg_softc *sc = MUSBOTG_BUS2SC(xfer->xroot->bus); 2240 uint16_t value; 2241 uint16_t index; 2242 2243 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2244 2245 if (std->state != USB_SW_TR_SETUP) { 2246 if (std->state == USB_SW_TR_PRE_CALLBACK) { 2247 /* transfer transferred */ 2248 musbotg_device_done(xfer, std->err); 2249 } 2250 goto done; 2251 } 2252 /* buffer reset */ 2253 std->ptr = USB_ADD_BYTES(&sc->sc_hub_temp, 0); 2254 std->len = 0; 2255 2256 value = UGETW(std->req.wValue); 2257 index = UGETW(std->req.wIndex); 2258 2259 /* demultiplex the control request */ 2260 2261 switch (std->req.bmRequestType) { 2262 case UT_READ_DEVICE: 2263 switch (std->req.bRequest) { 2264 case UR_GET_DESCRIPTOR: 2265 goto tr_handle_get_descriptor; 2266 case UR_GET_CONFIG: 2267 goto tr_handle_get_config; 2268 case UR_GET_STATUS: 2269 goto tr_handle_get_status; 2270 default: 2271 goto tr_stalled; 2272 } 2273 break; 2274 2275 case UT_WRITE_DEVICE: 2276 switch (std->req.bRequest) { 2277 case UR_SET_ADDRESS: 2278 goto tr_handle_set_address; 2279 case UR_SET_CONFIG: 2280 goto tr_handle_set_config; 2281 case UR_CLEAR_FEATURE: 2282 goto tr_valid; /* nop */ 2283 case UR_SET_DESCRIPTOR: 2284 goto tr_valid; /* nop */ 2285 case UR_SET_FEATURE: 2286 default: 2287 goto tr_stalled; 2288 } 2289 break; 2290 2291 case UT_WRITE_ENDPOINT: 2292 switch (std->req.bRequest) { 2293 case UR_CLEAR_FEATURE: 2294 switch (UGETW(std->req.wValue)) { 2295 case UF_ENDPOINT_HALT: 2296 goto tr_handle_clear_halt; 2297 case UF_DEVICE_REMOTE_WAKEUP: 2298 goto tr_handle_clear_wakeup; 2299 default: 2300 goto tr_stalled; 2301 } 2302 break; 2303 case UR_SET_FEATURE: 2304 switch (UGETW(std->req.wValue)) { 2305 case UF_ENDPOINT_HALT: 2306 goto tr_handle_set_halt; 2307 case UF_DEVICE_REMOTE_WAKEUP: 2308 goto tr_handle_set_wakeup; 2309 default: 2310 goto tr_stalled; 2311 } 2312 break; 2313 case UR_SYNCH_FRAME: 2314 goto tr_valid; /* nop */ 2315 default: 2316 goto tr_stalled; 2317 } 2318 break; 2319 2320 case UT_READ_ENDPOINT: 2321 switch (std->req.bRequest) { 2322 case UR_GET_STATUS: 2323 goto tr_handle_get_ep_status; 2324 default: 2325 goto tr_stalled; 2326 } 2327 break; 2328 2329 case UT_WRITE_INTERFACE: 2330 switch (std->req.bRequest) { 2331 case UR_SET_INTERFACE: 2332 goto tr_handle_set_interface; 2333 case UR_CLEAR_FEATURE: 2334 goto tr_valid; /* nop */ 2335 case UR_SET_FEATURE: 2336 default: 2337 goto tr_stalled; 2338 } 2339 break; 2340 2341 case UT_READ_INTERFACE: 2342 switch (std->req.bRequest) { 2343 case UR_GET_INTERFACE: 2344 goto tr_handle_get_interface; 2345 case UR_GET_STATUS: 2346 goto tr_handle_get_iface_status; 2347 default: 2348 goto tr_stalled; 2349 } 2350 break; 2351 2352 case UT_WRITE_CLASS_INTERFACE: 2353 case UT_WRITE_VENDOR_INTERFACE: 2354 /* XXX forward */ 2355 break; 2356 2357 case UT_READ_CLASS_INTERFACE: 2358 case UT_READ_VENDOR_INTERFACE: 2359 /* XXX forward */ 2360 break; 2361 2362 case UT_WRITE_CLASS_DEVICE: 2363 switch (std->req.bRequest) { 2364 case UR_CLEAR_FEATURE: 2365 goto tr_valid; 2366 case UR_SET_DESCRIPTOR: 2367 case UR_SET_FEATURE: 2368 break; 2369 default: 2370 goto tr_stalled; 2371 } 2372 break; 2373 2374 case UT_WRITE_CLASS_OTHER: 2375 switch (std->req.bRequest) { 2376 case UR_CLEAR_FEATURE: 2377 goto tr_handle_clear_port_feature; 2378 case UR_SET_FEATURE: 2379 goto tr_handle_set_port_feature; 2380 case UR_CLEAR_TT_BUFFER: 2381 case UR_RESET_TT: 2382 case UR_STOP_TT: 2383 goto tr_valid; 2384 2385 default: 2386 goto tr_stalled; 2387 } 2388 break; 2389 2390 case UT_READ_CLASS_OTHER: 2391 switch (std->req.bRequest) { 2392 case UR_GET_TT_STATE: 2393 goto tr_handle_get_tt_state; 2394 case UR_GET_STATUS: 2395 goto tr_handle_get_port_status; 2396 default: 2397 goto tr_stalled; 2398 } 2399 break; 2400 2401 case UT_READ_CLASS_DEVICE: 2402 switch (std->req.bRequest) { 2403 case UR_GET_DESCRIPTOR: 2404 goto tr_handle_get_class_descriptor; 2405 case UR_GET_STATUS: 2406 goto tr_handle_get_class_status; 2407 2408 default: 2409 goto tr_stalled; 2410 } 2411 break; 2412 default: 2413 goto tr_stalled; 2414 } 2415 goto tr_valid; 2416 2417tr_handle_get_descriptor: 2418 switch (value >> 8) { 2419 case UDESC_DEVICE: 2420 if (value & 0xff) { 2421 goto tr_stalled; 2422 } 2423 std->len = sizeof(musbotg_devd); 2424 std->ptr = USB_ADD_BYTES(&musbotg_devd, 0); 2425 goto tr_valid; 2426 case UDESC_CONFIG: 2427 if (value & 0xff) { 2428 goto tr_stalled; 2429 } 2430 std->len = sizeof(musbotg_confd); 2431 std->ptr = USB_ADD_BYTES(&musbotg_confd, 0); 2432 goto tr_valid; 2433 case UDESC_STRING: 2434 switch (value & 0xff) { 2435 case 0: /* Language table */ 2436 std->len = sizeof(musbotg_langtab); 2437 std->ptr = USB_ADD_BYTES(&musbotg_langtab, 0); 2438 goto tr_valid; 2439 2440 case 1: /* Vendor */ 2441 std->len = sizeof(musbotg_vendor); 2442 std->ptr = USB_ADD_BYTES(&musbotg_vendor, 0); 2443 goto tr_valid; 2444 2445 case 2: /* Product */ 2446 std->len = sizeof(musbotg_product); 2447 std->ptr = USB_ADD_BYTES(&musbotg_product, 0); 2448 goto tr_valid; 2449 default: 2450 break; 2451 } 2452 break; 2453 default: 2454 goto tr_stalled; 2455 } 2456 goto tr_stalled; 2457 2458tr_handle_get_config: 2459 std->len = 1; 2460 sc->sc_hub_temp.wValue[0] = sc->sc_conf; 2461 goto tr_valid; 2462 2463tr_handle_get_status: 2464 std->len = 2; 2465 USETW(sc->sc_hub_temp.wValue, UDS_SELF_POWERED); 2466 goto tr_valid; 2467 2468tr_handle_set_address: 2469 if (value & 0xFF00) { 2470 goto tr_stalled; 2471 } 2472 sc->sc_rt_addr = value; 2473 goto tr_valid; 2474 2475tr_handle_set_config: 2476 if (value >= 2) { 2477 goto tr_stalled; 2478 } 2479 sc->sc_conf = value; 2480 goto tr_valid; 2481 2482tr_handle_get_interface: 2483 std->len = 1; 2484 sc->sc_hub_temp.wValue[0] = 0; 2485 goto tr_valid; 2486 2487tr_handle_get_tt_state: 2488tr_handle_get_class_status: 2489tr_handle_get_iface_status: 2490tr_handle_get_ep_status: 2491 std->len = 2; 2492 USETW(sc->sc_hub_temp.wValue, 0); 2493 goto tr_valid; 2494 2495tr_handle_set_halt: 2496tr_handle_set_interface: 2497tr_handle_set_wakeup: 2498tr_handle_clear_wakeup: 2499tr_handle_clear_halt: 2500 goto tr_valid; 2501 2502tr_handle_clear_port_feature: 2503 if (index != 1) { 2504 goto tr_stalled; 2505 } 2506 DPRINTFN(8, "UR_CLEAR_PORT_FEATURE on port %d\n", index); 2507 2508 switch (value) { 2509 case UHF_PORT_SUSPEND: 2510 musbotg_wakeup_peer(xfer); 2511 break; 2512 2513 case UHF_PORT_ENABLE: 2514 sc->sc_flags.port_enabled = 0; 2515 break; 2516 2517 case UHF_PORT_TEST: 2518 case UHF_PORT_INDICATOR: 2519 case UHF_C_PORT_ENABLE: 2520 case UHF_C_PORT_OVER_CURRENT: 2521 case UHF_C_PORT_RESET: 2522 /* nops */ 2523 break; 2524 case UHF_PORT_POWER: 2525 sc->sc_flags.port_powered = 0; 2526 musbotg_pull_down(sc); 2527 musbotg_clocks_off(sc); 2528 break; 2529 case UHF_C_PORT_CONNECTION: 2530 sc->sc_flags.change_connect = 0; 2531 break; 2532 case UHF_C_PORT_SUSPEND: 2533 sc->sc_flags.change_suspend = 0; 2534 break; 2535 default: 2536 std->err = USB_ERR_IOERROR; 2537 goto done; 2538 } 2539 goto tr_valid; 2540 2541tr_handle_set_port_feature: 2542 if (index != 1) { 2543 goto tr_stalled; 2544 } 2545 DPRINTFN(8, "UR_SET_PORT_FEATURE\n"); 2546 2547 switch (value) { 2548 case UHF_PORT_ENABLE: 2549 sc->sc_flags.port_enabled = 1; 2550 break; 2551 case UHF_PORT_SUSPEND: 2552 case UHF_PORT_RESET: 2553 case UHF_PORT_TEST: 2554 case UHF_PORT_INDICATOR: 2555 /* nops */ 2556 break; 2557 case UHF_PORT_POWER: 2558 sc->sc_flags.port_powered = 1; 2559 break; 2560 default: 2561 std->err = USB_ERR_IOERROR; 2562 goto done; 2563 } 2564 goto tr_valid; 2565 2566tr_handle_get_port_status: 2567 2568 DPRINTFN(8, "UR_GET_PORT_STATUS\n"); 2569 2570 if (index != 1) { 2571 goto tr_stalled; 2572 } 2573 if (sc->sc_flags.status_vbus) { 2574 musbotg_clocks_on(sc); 2575 musbotg_pull_up(sc); 2576 } else { 2577 musbotg_pull_down(sc); 2578 musbotg_clocks_off(sc); 2579 } 2580 2581 /* Select Device Side Mode */ 2582 value = UPS_PORT_MODE_DEVICE; 2583 2584 if (sc->sc_flags.status_high_speed) { 2585 value |= UPS_HIGH_SPEED; 2586 } 2587 if (sc->sc_flags.port_powered) { 2588 value |= UPS_PORT_POWER; 2589 } 2590 if (sc->sc_flags.port_enabled) { 2591 value |= UPS_PORT_ENABLED; 2592 } 2593 if (sc->sc_flags.status_vbus && 2594 sc->sc_flags.status_bus_reset) { 2595 value |= UPS_CURRENT_CONNECT_STATUS; 2596 } 2597 if (sc->sc_flags.status_suspend) { 2598 value |= UPS_SUSPEND; 2599 } 2600 USETW(sc->sc_hub_temp.ps.wPortStatus, value); 2601 2602 value = 0; 2603 2604 if (sc->sc_flags.change_connect) { 2605 value |= UPS_C_CONNECT_STATUS; 2606 2607 if (sc->sc_flags.status_vbus && 2608 sc->sc_flags.status_bus_reset) { 2609 /* reset EP0 state */ 2610 sc->sc_ep0_busy = 0; 2611 sc->sc_ep0_cmd = 0; 2612 } 2613 } 2614 if (sc->sc_flags.change_suspend) { 2615 value |= UPS_C_SUSPEND; 2616 } 2617 USETW(sc->sc_hub_temp.ps.wPortChange, value); 2618 std->len = sizeof(sc->sc_hub_temp.ps); 2619 goto tr_valid; 2620 2621tr_handle_get_class_descriptor: 2622 if (value & 0xFF) { 2623 goto tr_stalled; 2624 } 2625 std->ptr = USB_ADD_BYTES(&musbotg_hubd, 0); 2626 std->len = sizeof(musbotg_hubd); 2627 goto tr_valid; 2628 2629tr_stalled: 2630 std->err = USB_ERR_STALLED; 2631tr_valid: 2632done: 2633 return; 2634} 2635 2636static void 2637musbotg_root_ctrl_poll(struct musbotg_softc *sc) 2638{ 2639 usb2_sw_transfer(&sc->sc_root_ctrl, 2640 &musbotg_root_ctrl_done); 2641} 2642 2643struct usb2_pipe_methods musbotg_root_ctrl_methods = 2644{ 2645 .open = musbotg_root_ctrl_open, 2646 .close = musbotg_root_ctrl_close, 2647 .enter = musbotg_root_ctrl_enter, 2648 .start = musbotg_root_ctrl_start, 2649 .enter_is_cancelable = 1, 2650 .start_is_cancelable = 0, 2651}; 2652 2653/*------------------------------------------------------------------------* 2654 * musbotg root interrupt support 2655 *------------------------------------------------------------------------*/ 2656static void 2657musbotg_root_intr_open(struct usb2_xfer *xfer) 2658{ 2659 return; 2660} 2661 2662static void 2663musbotg_root_intr_close(struct usb2_xfer *xfer) 2664{ 2665 struct musbotg_softc *sc = MUSBOTG_BUS2SC(xfer->xroot->bus); 2666 2667 if (sc->sc_root_intr.xfer == xfer) { 2668 sc->sc_root_intr.xfer = NULL; 2669 } 2670 musbotg_device_done(xfer, USB_ERR_CANCELLED); 2671} 2672 2673static void 2674musbotg_root_intr_enter(struct usb2_xfer *xfer) 2675{ 2676 return; 2677} 2678 2679static void 2680musbotg_root_intr_start(struct usb2_xfer *xfer) 2681{ 2682 struct musbotg_softc *sc = MUSBOTG_BUS2SC(xfer->xroot->bus); 2683 2684 sc->sc_root_intr.xfer = xfer; 2685} 2686 2687struct usb2_pipe_methods musbotg_root_intr_methods = 2688{ 2689 .open = musbotg_root_intr_open, 2690 .close = musbotg_root_intr_close, 2691 .enter = musbotg_root_intr_enter, 2692 .start = musbotg_root_intr_start, 2693 .enter_is_cancelable = 1, 2694 .start_is_cancelable = 1, 2695}; 2696 2697static void 2698musbotg_xfer_setup(struct usb2_setup_params *parm) 2699{ 2700 const struct usb2_hw_ep_profile *pf; 2701 struct musbotg_softc *sc; 2702 struct usb2_xfer *xfer; 2703 void *last_obj; 2704 uint32_t ntd; 2705 uint32_t n; 2706 uint8_t ep_no; 2707 2708 sc = MUSBOTG_BUS2SC(parm->udev->bus); 2709 xfer = parm->curr_xfer; 2710 2711 /* 2712 * NOTE: This driver does not use any of the parameters that 2713 * are computed from the following values. Just set some 2714 * reasonable dummies: 2715 */ 2716 parm->hc_max_packet_size = 0x400; 2717 parm->hc_max_frame_size = 0x400; 2718 2719 if ((parm->methods == &musbotg_device_isoc_methods) || 2720 (parm->methods == &musbotg_device_intr_methods)) 2721 parm->hc_max_packet_count = 3; 2722 else 2723 parm->hc_max_packet_count = 1; 2724 2725 usb2_transfer_setup_sub(parm); 2726 2727 /* 2728 * compute maximum number of TDs 2729 */ 2730 if (parm->methods == &musbotg_device_ctrl_methods) { 2731 2732 ntd = xfer->nframes + 1 /* STATUS */ + 1 /* SYNC */ ; 2733 2734 } else if (parm->methods == &musbotg_device_bulk_methods) { 2735 2736 ntd = xfer->nframes + 1 /* SYNC */ ; 2737 2738 } else if (parm->methods == &musbotg_device_intr_methods) { 2739 2740 ntd = xfer->nframes + 1 /* SYNC */ ; 2741 2742 } else if (parm->methods == &musbotg_device_isoc_methods) { 2743 2744 ntd = xfer->nframes + 1 /* SYNC */ ; 2745 2746 } else { 2747 2748 ntd = 0; 2749 } 2750 2751 /* 2752 * check if "usb2_transfer_setup_sub" set an error 2753 */ 2754 if (parm->err) { 2755 return; 2756 } 2757 /* 2758 * allocate transfer descriptors 2759 */ 2760 last_obj = NULL; 2761 2762 /* 2763 * get profile stuff 2764 */ 2765 if (ntd) { 2766 2767 ep_no = xfer->endpoint & UE_ADDR; 2768 musbotg_get_hw_ep_profile(parm->udev, &pf, ep_no); 2769 2770 if (pf == NULL) { 2771 /* should not happen */ 2772 parm->err = USB_ERR_INVAL; 2773 return; 2774 } 2775 } else { 2776 ep_no = 0; 2777 pf = NULL; 2778 } 2779 2780 /* align data */ 2781 parm->size[0] += ((-parm->size[0]) & (USB_HOST_ALIGN - 1)); 2782 2783 for (n = 0; n != ntd; n++) { 2784 2785 struct musbotg_td *td; 2786 2787 if (parm->buf) { 2788 2789 td = USB_ADD_BYTES(parm->buf, parm->size[0]); 2790 2791 /* init TD */ 2792 td->max_frame_size = xfer->max_frame_size; 2793 td->ep_no = ep_no; 2794 td->obj_next = last_obj; 2795 2796 last_obj = td; 2797 } 2798 parm->size[0] += sizeof(*td); 2799 } 2800 2801 xfer->td_start[0] = last_obj; 2802} 2803 2804static void 2805musbotg_xfer_unsetup(struct usb2_xfer *xfer) 2806{ 2807 return; 2808} 2809 2810static void 2811musbotg_pipe_init(struct usb2_device *udev, struct usb2_endpoint_descriptor *edesc, 2812 struct usb2_pipe *pipe) 2813{ 2814 struct musbotg_softc *sc = MUSBOTG_BUS2SC(udev->bus); 2815 2816 DPRINTFN(2, "pipe=%p, addr=%d, endpt=%d, mode=%d (%d)\n", 2817 pipe, udev->address, 2818 edesc->bEndpointAddress, udev->flags.usb2_mode, 2819 sc->sc_rt_addr); 2820 2821 if (udev->device_index == sc->sc_rt_addr) { 2822 2823 if (udev->flags.usb2_mode != USB_MODE_HOST) { 2824 /* not supported */ 2825 return; 2826 } 2827 switch (edesc->bEndpointAddress) { 2828 case USB_CONTROL_ENDPOINT: 2829 pipe->methods = &musbotg_root_ctrl_methods; 2830 break; 2831 case UE_DIR_IN | MUSBOTG_INTR_ENDPT: 2832 pipe->methods = &musbotg_root_intr_methods; 2833 break; 2834 default: 2835 /* do nothing */ 2836 break; 2837 } 2838 } else { 2839 2840 if (udev->flags.usb2_mode != USB_MODE_DEVICE) { 2841 /* not supported */ 2842 return; 2843 } 2844 if ((udev->speed != USB_SPEED_FULL) && 2845 (udev->speed != USB_SPEED_HIGH)) { 2846 /* not supported */ 2847 return; 2848 } 2849 switch (edesc->bmAttributes & UE_XFERTYPE) { 2850 case UE_CONTROL: 2851 pipe->methods = &musbotg_device_ctrl_methods; 2852 break; 2853 case UE_INTERRUPT: 2854 pipe->methods = &musbotg_device_intr_methods; 2855 break; 2856 case UE_ISOCHRONOUS: 2857 pipe->methods = &musbotg_device_isoc_methods; 2858 break; 2859 case UE_BULK: 2860 pipe->methods = &musbotg_device_bulk_methods; 2861 break; 2862 default: 2863 /* do nothing */ 2864 break; 2865 } 2866 } 2867} 2868 2869struct usb2_bus_methods musbotg_bus_methods = 2870{ 2871 .pipe_init = &musbotg_pipe_init, 2872 .xfer_setup = &musbotg_xfer_setup, 2873 .xfer_unsetup = &musbotg_xfer_unsetup, 2874 .get_hw_ep_profile = &musbotg_get_hw_ep_profile, 2875 .set_stall = &musbotg_set_stall, 2876 .clear_stall = &musbotg_clear_stall, 2877 .roothub_exec = &musbotg_root_ctrl_task, 2878}; 2879