musb_otg.c revision 190721
1/* $FreeBSD: head/sys/dev/usb/controller/musb_otg.c 190721 2009-04-05 18:18:16Z thompsa $ */ 2/*- 3 * Copyright (c) 2008 Hans Petter Selasky. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27/* 28 * Thanks to Mentor Graphics for providing a reference driver for this 29 * USB chip at their homepage. 30 */ 31 32/* 33 * This file contains the driver for the Mentor Graphics Inventra USB 34 * 2.0 High Speed Dual-Role controller. 35 * 36 * NOTE: The current implementation only supports Device Side Mode! 37 */ 38 39#include <dev/usb/usb.h> 40#include <dev/usb/usb_mfunc.h> 41#include <dev/usb/usb_error.h> 42 43#define USB_DEBUG_VAR musbotgdebug 44 45#include <dev/usb/usb_core.h> 46#include <dev/usb/usb_debug.h> 47#include <dev/usb/usb_busdma.h> 48#include <dev/usb/usb_process.h> 49#include <dev/usb/usb_sw_transfer.h> 50#include <dev/usb/usb_transfer.h> 51#include <dev/usb/usb_device.h> 52#include <dev/usb/usb_hub.h> 53#include <dev/usb/usb_util.h> 54 55#include <dev/usb/usb_controller.h> 56#include <dev/usb/usb_bus.h> 57#include <dev/usb/controller/musb_otg.h> 58 59#define MUSBOTG_INTR_ENDPT 1 60 61#define MUSBOTG_BUS2SC(bus) \ 62 ((struct musbotg_softc *)(((uint8_t *)(bus)) - \ 63 USB_P2U(&(((struct musbotg_softc *)0)->sc_bus)))) 64 65#define MUSBOTG_PC2SC(pc) \ 66 MUSBOTG_BUS2SC(USB_DMATAG_TO_XROOT((pc)->tag_parent)->bus) 67 68#if USB_DEBUG 69static int musbotgdebug = 0; 70 71SYSCTL_NODE(_hw_usb2, OID_AUTO, musbotg, CTLFLAG_RW, 0, "USB musbotg"); 72SYSCTL_INT(_hw_usb2_musbotg, OID_AUTO, debug, CTLFLAG_RW, 73 &musbotgdebug, 0, "Debug level"); 74#endif 75 76/* prototypes */ 77 78struct usb2_bus_methods musbotg_bus_methods; 79struct usb2_pipe_methods musbotg_device_bulk_methods; 80struct usb2_pipe_methods musbotg_device_ctrl_methods; 81struct usb2_pipe_methods musbotg_device_intr_methods; 82struct usb2_pipe_methods musbotg_device_isoc_methods; 83struct usb2_pipe_methods musbotg_root_ctrl_methods; 84struct usb2_pipe_methods musbotg_root_intr_methods; 85 86static musbotg_cmd_t musbotg_setup_rx; 87static musbotg_cmd_t musbotg_setup_data_rx; 88static musbotg_cmd_t musbotg_setup_data_tx; 89static musbotg_cmd_t musbotg_setup_status; 90static musbotg_cmd_t musbotg_data_rx; 91static musbotg_cmd_t musbotg_data_tx; 92static void musbotg_device_done(struct usb2_xfer *, usb2_error_t); 93static void musbotg_do_poll(struct usb2_bus *); 94static void musbotg_root_ctrl_poll(struct musbotg_softc *); 95static void musbotg_standard_done(struct usb2_xfer *); 96static void musbotg_interrupt_poll(struct musbotg_softc *); 97 98static usb2_sw_transfer_func_t musbotg_root_intr_done; 99static usb2_sw_transfer_func_t musbotg_root_ctrl_done; 100 101/* 102 * Here is a configuration that the chip supports. 103 */ 104static const struct usb2_hw_ep_profile musbotg_ep_profile[1] = { 105 106 [0] = { 107 .max_in_frame_size = 64,/* fixed */ 108 .max_out_frame_size = 64, /* fixed */ 109 .is_simplex = 1, 110 .support_control = 1, 111 } 112}; 113 114static void 115musbotg_get_hw_ep_profile(struct usb2_device *udev, 116 const struct usb2_hw_ep_profile **ppf, uint8_t ep_addr) 117{ 118 struct musbotg_softc *sc; 119 120 sc = MUSBOTG_BUS2SC(udev->bus); 121 122 if (ep_addr == 0) { 123 /* control endpoint */ 124 *ppf = musbotg_ep_profile; 125 } else if (ep_addr <= sc->sc_ep_max) { 126 /* other endpoints */ 127 *ppf = sc->sc_hw_ep_profile + ep_addr; 128 } else { 129 *ppf = NULL; 130 } 131} 132 133static void 134musbotg_clocks_on(struct musbotg_softc *sc) 135{ 136 if (sc->sc_flags.clocks_off && 137 sc->sc_flags.port_powered) { 138 139 DPRINTFN(4, "\n"); 140 141 if (sc->sc_clocks_on) { 142 (sc->sc_clocks_on) (sc->sc_clocks_arg); 143 } 144 sc->sc_flags.clocks_off = 0; 145 146 /* XXX enable Transceiver */ 147 } 148} 149 150static void 151musbotg_clocks_off(struct musbotg_softc *sc) 152{ 153 if (!sc->sc_flags.clocks_off) { 154 155 DPRINTFN(4, "\n"); 156 157 /* XXX disable Transceiver */ 158 159 if (sc->sc_clocks_off) { 160 (sc->sc_clocks_off) (sc->sc_clocks_arg); 161 } 162 sc->sc_flags.clocks_off = 1; 163 } 164} 165 166static void 167musbotg_pull_common(struct musbotg_softc *sc, uint8_t on) 168{ 169 uint8_t temp; 170 171 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER); 172 if (on) 173 temp |= MUSB2_MASK_SOFTC; 174 else 175 temp &= ~MUSB2_MASK_SOFTC; 176 177 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp); 178} 179 180static void 181musbotg_pull_up(struct musbotg_softc *sc) 182{ 183 /* pullup D+, if possible */ 184 185 if (!sc->sc_flags.d_pulled_up && 186 sc->sc_flags.port_powered) { 187 sc->sc_flags.d_pulled_up = 1; 188 musbotg_pull_common(sc, 1); 189 } 190} 191 192static void 193musbotg_pull_down(struct musbotg_softc *sc) 194{ 195 /* pulldown D+, if possible */ 196 197 if (sc->sc_flags.d_pulled_up) { 198 sc->sc_flags.d_pulled_up = 0; 199 musbotg_pull_common(sc, 0); 200 } 201} 202 203static void 204musbotg_wakeup_peer(struct usb2_xfer *xfer) 205{ 206 struct musbotg_softc *sc = MUSBOTG_BUS2SC(xfer->xroot->bus); 207 uint8_t temp; 208 209 if (!(sc->sc_flags.status_suspend)) { 210 return; 211 } 212 213 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER); 214 temp |= MUSB2_MASK_RESUME; 215 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp); 216 217 /* wait 8 milliseconds */ 218 /* Wait for reset to complete. */ 219 usb2_pause_mtx(&sc->sc_bus.bus_mtx, hz / 125); 220 221 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER); 222 temp &= ~MUSB2_MASK_RESUME; 223 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp); 224} 225 226static void 227musbotg_set_address(struct musbotg_softc *sc, uint8_t addr) 228{ 229 DPRINTFN(4, "addr=%d\n", addr); 230 addr &= 0x7F; 231 MUSB2_WRITE_1(sc, MUSB2_REG_FADDR, addr); 232} 233 234static uint8_t 235musbotg_setup_rx(struct musbotg_td *td) 236{ 237 struct musbotg_softc *sc; 238 struct usb2_device_request req; 239 uint16_t count; 240 uint8_t csr; 241 242 /* get pointer to softc */ 243 sc = MUSBOTG_PC2SC(td->pc); 244 245 /* select endpoint 0 */ 246 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); 247 248 /* read out FIFO status */ 249 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 250 251 DPRINTFN(4, "csr=0x%02x\n", csr); 252 253 /* 254 * NOTE: If DATAEND is set we should not call the 255 * callback, hence the status stage is not complete. 256 */ 257 if (csr & MUSB2_MASK_CSR0L_DATAEND) { 258 /* do not stall at this point */ 259 td->did_stall = 1; 260 /* wait for interrupt */ 261 goto not_complete; 262 } 263 if (csr & MUSB2_MASK_CSR0L_SENTSTALL) { 264 /* clear SENTSTALL */ 265 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0); 266 /* get latest status */ 267 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 268 /* update EP0 state */ 269 sc->sc_ep0_busy = 0; 270 } 271 if (csr & MUSB2_MASK_CSR0L_SETUPEND) { 272 /* clear SETUPEND */ 273 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 274 MUSB2_MASK_CSR0L_SETUPEND_CLR); 275 /* get latest status */ 276 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 277 /* update EP0 state */ 278 sc->sc_ep0_busy = 0; 279 } 280 if (sc->sc_ep0_busy) { 281 goto not_complete; 282 } 283 if (!(csr & MUSB2_MASK_CSR0L_RXPKTRDY)) { 284 goto not_complete; 285 } 286 /* clear did stall flag */ 287 td->did_stall = 0; 288 /* get the packet byte count */ 289 count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT); 290 291 /* verify data length */ 292 if (count != td->remainder) { 293 DPRINTFN(0, "Invalid SETUP packet " 294 "length, %d bytes\n", count); 295 goto not_complete; 296 } 297 if (count != sizeof(req)) { 298 DPRINTFN(0, "Unsupported SETUP packet " 299 "length, %d bytes\n", count); 300 goto not_complete; 301 } 302 /* receive data */ 303 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 304 MUSB2_REG_EPFIFO(0), (void *)&req, sizeof(req)); 305 306 /* copy data into real buffer */ 307 usb2_copy_in(td->pc, 0, &req, sizeof(req)); 308 309 td->offset = sizeof(req); 310 td->remainder = 0; 311 312 /* set pending command */ 313 sc->sc_ep0_cmd = MUSB2_MASK_CSR0L_RXPKTRDY_CLR; 314 315 /* we need set stall or dataend after this */ 316 sc->sc_ep0_busy = 1; 317 318 /* sneak peek the set address */ 319 if ((req.bmRequestType == UT_WRITE_DEVICE) && 320 (req.bRequest == UR_SET_ADDRESS)) { 321 sc->sc_dv_addr = req.wValue[0] & 0x7F; 322 } else { 323 sc->sc_dv_addr = 0xFF; 324 } 325 return (0); /* complete */ 326 327not_complete: 328 /* abort any ongoing transfer */ 329 if (!td->did_stall) { 330 DPRINTFN(4, "stalling\n"); 331 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 332 MUSB2_MASK_CSR0L_SENDSTALL); 333 td->did_stall = 1; 334 } 335 return (1); /* not complete */ 336} 337 338/* Control endpoint only data handling functions (RX/TX/SYNC) */ 339 340static uint8_t 341musbotg_setup_data_rx(struct musbotg_td *td) 342{ 343 struct usb2_page_search buf_res; 344 struct musbotg_softc *sc; 345 uint16_t count; 346 uint8_t csr; 347 uint8_t got_short; 348 349 /* get pointer to softc */ 350 sc = MUSBOTG_PC2SC(td->pc); 351 352 /* select endpoint 0 */ 353 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); 354 355 /* check if a command is pending */ 356 if (sc->sc_ep0_cmd) { 357 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, sc->sc_ep0_cmd); 358 sc->sc_ep0_cmd = 0; 359 } 360 /* read out FIFO status */ 361 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 362 363 DPRINTFN(4, "csr=0x%02x\n", csr); 364 365 got_short = 0; 366 367 if (csr & (MUSB2_MASK_CSR0L_SETUPEND | 368 MUSB2_MASK_CSR0L_SENTSTALL)) { 369 if (td->remainder == 0) { 370 /* 371 * We are actually complete and have 372 * received the next SETUP 373 */ 374 DPRINTFN(4, "faking complete\n"); 375 return (0); /* complete */ 376 } 377 /* 378 * USB Host Aborted the transfer. 379 */ 380 td->error = 1; 381 return (0); /* complete */ 382 } 383 if (!(csr & MUSB2_MASK_CSR0L_RXPKTRDY)) { 384 return (1); /* not complete */ 385 } 386 /* get the packet byte count */ 387 count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT); 388 389 /* verify the packet byte count */ 390 if (count != td->max_frame_size) { 391 if (count < td->max_frame_size) { 392 /* we have a short packet */ 393 td->short_pkt = 1; 394 got_short = 1; 395 } else { 396 /* invalid USB packet */ 397 td->error = 1; 398 return (0); /* we are complete */ 399 } 400 } 401 /* verify the packet byte count */ 402 if (count > td->remainder) { 403 /* invalid USB packet */ 404 td->error = 1; 405 return (0); /* we are complete */ 406 } 407 while (count > 0) { 408 uint32_t temp; 409 410 usb2_get_page(td->pc, td->offset, &buf_res); 411 412 /* get correct length */ 413 if (buf_res.length > count) { 414 buf_res.length = count; 415 } 416 /* check for unaligned memory address */ 417 if (USB_P2U(buf_res.buffer) & 3) { 418 419 temp = count & ~3; 420 421 if (temp) { 422 /* receive data 4 bytes at a time */ 423 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 424 MUSB2_REG_EPFIFO(0), sc->sc_bounce_buf, 425 temp / 4); 426 } 427 temp = count & 3; 428 if (temp) { 429 /* receive data 1 byte at a time */ 430 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 431 MUSB2_REG_EPFIFO(0), 432 (void *)(&sc->sc_bounce_buf[count / 4]), temp); 433 } 434 usb2_copy_in(td->pc, td->offset, 435 sc->sc_bounce_buf, count); 436 437 /* update offset and remainder */ 438 td->offset += count; 439 td->remainder -= count; 440 break; 441 } 442 /* check if we can optimise */ 443 if (buf_res.length >= 4) { 444 445 /* receive data 4 bytes at a time */ 446 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 447 MUSB2_REG_EPFIFO(0), buf_res.buffer, 448 buf_res.length / 4); 449 450 temp = buf_res.length & ~3; 451 452 /* update counters */ 453 count -= temp; 454 td->offset += temp; 455 td->remainder -= temp; 456 continue; 457 } 458 /* receive data */ 459 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 460 MUSB2_REG_EPFIFO(0), buf_res.buffer, buf_res.length); 461 462 /* update counters */ 463 count -= buf_res.length; 464 td->offset += buf_res.length; 465 td->remainder -= buf_res.length; 466 } 467 468 /* check if we are complete */ 469 if ((td->remainder == 0) || got_short) { 470 if (td->short_pkt) { 471 /* we are complete */ 472 sc->sc_ep0_cmd = MUSB2_MASK_CSR0L_RXPKTRDY_CLR; 473 return (0); 474 } 475 /* else need to receive a zero length packet */ 476 } 477 /* write command - need more data */ 478 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 479 MUSB2_MASK_CSR0L_RXPKTRDY_CLR); 480 return (1); /* not complete */ 481} 482 483static uint8_t 484musbotg_setup_data_tx(struct musbotg_td *td) 485{ 486 struct usb2_page_search buf_res; 487 struct musbotg_softc *sc; 488 uint16_t count; 489 uint8_t csr; 490 491 /* get pointer to softc */ 492 sc = MUSBOTG_PC2SC(td->pc); 493 494 /* select endpoint 0 */ 495 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); 496 497 /* check if a command is pending */ 498 if (sc->sc_ep0_cmd) { 499 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, sc->sc_ep0_cmd); 500 sc->sc_ep0_cmd = 0; 501 } 502 /* read out FIFO status */ 503 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 504 505 DPRINTFN(4, "csr=0x%02x\n", csr); 506 507 if (csr & (MUSB2_MASK_CSR0L_SETUPEND | 508 MUSB2_MASK_CSR0L_SENTSTALL)) { 509 /* 510 * The current transfer was aborted 511 * by the USB Host 512 */ 513 td->error = 1; 514 return (0); /* complete */ 515 } 516 if (csr & MUSB2_MASK_CSR0L_TXPKTRDY) { 517 return (1); /* not complete */ 518 } 519 count = td->max_frame_size; 520 if (td->remainder < count) { 521 /* we have a short packet */ 522 td->short_pkt = 1; 523 count = td->remainder; 524 } 525 while (count > 0) { 526 uint32_t temp; 527 528 usb2_get_page(td->pc, td->offset, &buf_res); 529 530 /* get correct length */ 531 if (buf_res.length > count) { 532 buf_res.length = count; 533 } 534 /* check for unaligned memory address */ 535 if (USB_P2U(buf_res.buffer) & 3) { 536 537 usb2_copy_out(td->pc, td->offset, 538 sc->sc_bounce_buf, count); 539 540 temp = count & ~3; 541 542 if (temp) { 543 /* transmit data 4 bytes at a time */ 544 bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 545 MUSB2_REG_EPFIFO(0), sc->sc_bounce_buf, 546 temp / 4); 547 } 548 temp = count & 3; 549 if (temp) { 550 /* receive data 1 byte at a time */ 551 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 552 MUSB2_REG_EPFIFO(0), 553 ((void *)&sc->sc_bounce_buf[count / 4]), temp); 554 } 555 /* update offset and remainder */ 556 td->offset += count; 557 td->remainder -= count; 558 break; 559 } 560 /* check if we can optimise */ 561 if (buf_res.length >= 4) { 562 563 /* transmit data 4 bytes at a time */ 564 bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 565 MUSB2_REG_EPFIFO(0), buf_res.buffer, 566 buf_res.length / 4); 567 568 temp = buf_res.length & ~3; 569 570 /* update counters */ 571 count -= temp; 572 td->offset += temp; 573 td->remainder -= temp; 574 continue; 575 } 576 /* transmit data */ 577 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 578 MUSB2_REG_EPFIFO(0), buf_res.buffer, buf_res.length); 579 580 /* update counters */ 581 count -= buf_res.length; 582 td->offset += buf_res.length; 583 td->remainder -= buf_res.length; 584 } 585 586 /* check remainder */ 587 if (td->remainder == 0) { 588 if (td->short_pkt) { 589 sc->sc_ep0_cmd = MUSB2_MASK_CSR0L_TXPKTRDY; 590 return (0); /* complete */ 591 } 592 /* else we need to transmit a short packet */ 593 } 594 /* write command */ 595 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 596 MUSB2_MASK_CSR0L_TXPKTRDY); 597 598 return (1); /* not complete */ 599} 600 601static uint8_t 602musbotg_setup_status(struct musbotg_td *td) 603{ 604 struct musbotg_softc *sc; 605 uint8_t csr; 606 607 /* get pointer to softc */ 608 sc = MUSBOTG_PC2SC(td->pc); 609 610 /* select endpoint 0 */ 611 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); 612 613 if (sc->sc_ep0_busy) { 614 sc->sc_ep0_busy = 0; 615 sc->sc_ep0_cmd |= MUSB2_MASK_CSR0L_DATAEND; 616 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, sc->sc_ep0_cmd); 617 sc->sc_ep0_cmd = 0; 618 } 619 /* read out FIFO status */ 620 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 621 622 DPRINTFN(4, "csr=0x%02x\n", csr); 623 624 if (csr & MUSB2_MASK_CSR0L_DATAEND) { 625 /* wait for interrupt */ 626 return (1); /* not complete */ 627 } 628 if (sc->sc_dv_addr != 0xFF) { 629 /* write function address */ 630 musbotg_set_address(sc, sc->sc_dv_addr); 631 } 632 return (0); /* complete */ 633} 634 635static uint8_t 636musbotg_data_rx(struct musbotg_td *td) 637{ 638 struct usb2_page_search buf_res; 639 struct musbotg_softc *sc; 640 uint16_t count; 641 uint8_t csr; 642 uint8_t to; 643 uint8_t got_short; 644 645 to = 8; /* don't loop forever! */ 646 got_short = 0; 647 648 /* get pointer to softc */ 649 sc = MUSBOTG_PC2SC(td->pc); 650 651 /* select endpoint */ 652 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, td->ep_no); 653 654repeat: 655 /* read out FIFO status */ 656 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL); 657 658 DPRINTFN(4, "csr=0x%02x\n", csr); 659 660 /* clear overrun */ 661 if (csr & MUSB2_MASK_CSRL_RXOVERRUN) { 662 /* make sure we don't clear "RXPKTRDY" */ 663 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 664 MUSB2_MASK_CSRL_RXPKTRDY); 665 } 666 /* check status */ 667 if (!(csr & MUSB2_MASK_CSRL_RXPKTRDY)) { 668 return (1); /* not complete */ 669 } 670 /* get the packet byte count */ 671 count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT); 672 673 DPRINTFN(4, "count=0x%04x\n", count); 674 675 /* 676 * Check for short or invalid packet: 677 */ 678 if (count != td->max_frame_size) { 679 if (count < td->max_frame_size) { 680 /* we have a short packet */ 681 td->short_pkt = 1; 682 got_short = 1; 683 } else { 684 /* invalid USB packet */ 685 td->error = 1; 686 return (0); /* we are complete */ 687 } 688 } 689 /* verify the packet byte count */ 690 if (count > td->remainder) { 691 /* invalid USB packet */ 692 td->error = 1; 693 return (0); /* we are complete */ 694 } 695 while (count > 0) { 696 uint32_t temp; 697 698 usb2_get_page(td->pc, td->offset, &buf_res); 699 700 /* get correct length */ 701 if (buf_res.length > count) { 702 buf_res.length = count; 703 } 704 /* check for unaligned memory address */ 705 if (USB_P2U(buf_res.buffer) & 3) { 706 707 temp = count & ~3; 708 709 if (temp) { 710 /* receive data 4 bytes at a time */ 711 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 712 MUSB2_REG_EPFIFO(td->ep_no), sc->sc_bounce_buf, 713 temp / 4); 714 } 715 temp = count & 3; 716 if (temp) { 717 /* receive data 1 byte at a time */ 718 bus_space_read_multi_1(sc->sc_io_tag, 719 sc->sc_io_hdl, MUSB2_REG_EPFIFO(td->ep_no), 720 ((void *)&sc->sc_bounce_buf[count / 4]), temp); 721 } 722 usb2_copy_in(td->pc, td->offset, 723 sc->sc_bounce_buf, count); 724 725 /* update offset and remainder */ 726 td->offset += count; 727 td->remainder -= count; 728 break; 729 } 730 /* check if we can optimise */ 731 if (buf_res.length >= 4) { 732 733 /* receive data 4 bytes at a time */ 734 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 735 MUSB2_REG_EPFIFO(td->ep_no), buf_res.buffer, 736 buf_res.length / 4); 737 738 temp = buf_res.length & ~3; 739 740 /* update counters */ 741 count -= temp; 742 td->offset += temp; 743 td->remainder -= temp; 744 continue; 745 } 746 /* receive data */ 747 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 748 MUSB2_REG_EPFIFO(td->ep_no), buf_res.buffer, 749 buf_res.length); 750 751 /* update counters */ 752 count -= buf_res.length; 753 td->offset += buf_res.length; 754 td->remainder -= buf_res.length; 755 } 756 757 /* clear status bits */ 758 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 0); 759 760 /* check if we are complete */ 761 if ((td->remainder == 0) || got_short) { 762 if (td->short_pkt) { 763 /* we are complete */ 764 return (0); 765 } 766 /* else need to receive a zero length packet */ 767 } 768 if (--to) { 769 goto repeat; 770 } 771 return (1); /* not complete */ 772} 773 774static uint8_t 775musbotg_data_tx(struct musbotg_td *td) 776{ 777 struct usb2_page_search buf_res; 778 struct musbotg_softc *sc; 779 uint16_t count; 780 uint8_t csr; 781 uint8_t to; 782 783 to = 8; /* don't loop forever! */ 784 785 /* get pointer to softc */ 786 sc = MUSBOTG_PC2SC(td->pc); 787 788 /* select endpoint */ 789 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, td->ep_no); 790 791repeat: 792 793 /* read out FIFO status */ 794 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 795 796 DPRINTFN(4, "csr=0x%02x\n", csr); 797 798 if (csr & (MUSB2_MASK_CSRL_TXINCOMP | 799 MUSB2_MASK_CSRL_TXUNDERRUN)) { 800 /* clear status bits */ 801 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0); 802 } 803 if (csr & MUSB2_MASK_CSRL_TXPKTRDY) { 804 return (1); /* not complete */ 805 } 806 /* check for short packet */ 807 count = td->max_frame_size; 808 if (td->remainder < count) { 809 /* we have a short packet */ 810 td->short_pkt = 1; 811 count = td->remainder; 812 } 813 while (count > 0) { 814 uint32_t temp; 815 816 usb2_get_page(td->pc, td->offset, &buf_res); 817 818 /* get correct length */ 819 if (buf_res.length > count) { 820 buf_res.length = count; 821 } 822 /* check for unaligned memory address */ 823 if (USB_P2U(buf_res.buffer) & 3) { 824 825 usb2_copy_out(td->pc, td->offset, 826 sc->sc_bounce_buf, count); 827 828 temp = count & ~3; 829 830 if (temp) { 831 /* transmit data 4 bytes at a time */ 832 bus_space_write_multi_4(sc->sc_io_tag, 833 sc->sc_io_hdl, MUSB2_REG_EPFIFO(td->ep_no), 834 sc->sc_bounce_buf, temp / 4); 835 } 836 temp = count & 3; 837 if (temp) { 838 /* receive data 1 byte at a time */ 839 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 840 MUSB2_REG_EPFIFO(td->ep_no), 841 ((void *)&sc->sc_bounce_buf[count / 4]), temp); 842 } 843 /* update offset and remainder */ 844 td->offset += count; 845 td->remainder -= count; 846 break; 847 } 848 /* check if we can optimise */ 849 if (buf_res.length >= 4) { 850 851 /* transmit data 4 bytes at a time */ 852 bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 853 MUSB2_REG_EPFIFO(td->ep_no), buf_res.buffer, 854 buf_res.length / 4); 855 856 temp = buf_res.length & ~3; 857 858 /* update counters */ 859 count -= temp; 860 td->offset += temp; 861 td->remainder -= temp; 862 continue; 863 } 864 /* transmit data */ 865 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 866 MUSB2_REG_EPFIFO(td->ep_no), buf_res.buffer, 867 buf_res.length); 868 869 /* update counters */ 870 count -= buf_res.length; 871 td->offset += buf_res.length; 872 td->remainder -= buf_res.length; 873 } 874 875 /* write command */ 876 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 877 MUSB2_MASK_CSRL_TXPKTRDY); 878 879 /* check remainder */ 880 if (td->remainder == 0) { 881 if (td->short_pkt) { 882 return (0); /* complete */ 883 } 884 /* else we need to transmit a short packet */ 885 } 886 if (--to) { 887 goto repeat; 888 } 889 return (1); /* not complete */ 890} 891 892static uint8_t 893musbotg_xfer_do_fifo(struct usb2_xfer *xfer) 894{ 895 struct musbotg_softc *sc; 896 struct musbotg_td *td; 897 898 DPRINTFN(8, "\n"); 899 900 td = xfer->td_transfer_cache; 901 while (1) { 902 if ((td->func) (td)) { 903 /* operation in progress */ 904 break; 905 } 906 if (((void *)td) == xfer->td_transfer_last) { 907 goto done; 908 } 909 if (td->error) { 910 goto done; 911 } else if (td->remainder > 0) { 912 /* 913 * We had a short transfer. If there is no alternate 914 * next, stop processing ! 915 */ 916 if (!td->alt_next) { 917 goto done; 918 } 919 } 920 /* 921 * Fetch the next transfer descriptor and transfer 922 * some flags to the next transfer descriptor 923 */ 924 td = td->obj_next; 925 xfer->td_transfer_cache = td; 926 } 927 return (1); /* not complete */ 928 929done: 930 sc = MUSBOTG_BUS2SC(xfer->xroot->bus); 931 932 /* compute all actual lengths */ 933 934 musbotg_standard_done(xfer); 935 936 return (0); /* complete */ 937} 938 939static void 940musbotg_interrupt_poll(struct musbotg_softc *sc) 941{ 942 struct usb2_xfer *xfer; 943 944repeat: 945 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 946 if (!musbotg_xfer_do_fifo(xfer)) { 947 /* queue has been modified */ 948 goto repeat; 949 } 950 } 951} 952 953void 954musbotg_vbus_interrupt(struct musbotg_softc *sc, uint8_t is_on) 955{ 956 DPRINTFN(4, "vbus = %u\n", is_on); 957 958 USB_BUS_LOCK(&sc->sc_bus); 959 if (is_on) { 960 if (!sc->sc_flags.status_vbus) { 961 sc->sc_flags.status_vbus = 1; 962 963 /* complete root HUB interrupt endpoint */ 964 965 usb2_sw_transfer(&sc->sc_root_intr, 966 &musbotg_root_intr_done); 967 } 968 } else { 969 if (sc->sc_flags.status_vbus) { 970 sc->sc_flags.status_vbus = 0; 971 sc->sc_flags.status_bus_reset = 0; 972 sc->sc_flags.status_suspend = 0; 973 sc->sc_flags.change_suspend = 0; 974 sc->sc_flags.change_connect = 1; 975 976 /* complete root HUB interrupt endpoint */ 977 978 usb2_sw_transfer(&sc->sc_root_intr, 979 &musbotg_root_intr_done); 980 } 981 } 982 983 USB_BUS_UNLOCK(&sc->sc_bus); 984} 985 986void 987musbotg_interrupt(struct musbotg_softc *sc) 988{ 989 uint16_t rx_status; 990 uint16_t tx_status; 991 uint8_t usb_status; 992 uint8_t temp; 993 uint8_t to = 2; 994 995 USB_BUS_LOCK(&sc->sc_bus); 996 997repeat: 998 999 /* read all interrupt registers */ 1000 usb_status = MUSB2_READ_1(sc, MUSB2_REG_INTUSB); 1001 1002 /* read all FIFO interrupts */ 1003 rx_status = MUSB2_READ_2(sc, MUSB2_REG_INTRX); 1004 tx_status = MUSB2_READ_2(sc, MUSB2_REG_INTTX); 1005 1006 /* check for any bus state change interrupts */ 1007 1008 if (usb_status & (MUSB2_MASK_IRESET | 1009 MUSB2_MASK_IRESUME | MUSB2_MASK_ISUSP)) { 1010 1011 DPRINTFN(4, "real bus interrupt 0x%08x\n", usb_status); 1012 1013 if (usb_status & MUSB2_MASK_IRESET) { 1014 1015 /* set correct state */ 1016 sc->sc_flags.status_bus_reset = 1; 1017 sc->sc_flags.status_suspend = 0; 1018 sc->sc_flags.change_suspend = 0; 1019 sc->sc_flags.change_connect = 1; 1020 1021 /* determine line speed */ 1022 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER); 1023 if (temp & MUSB2_MASK_HSMODE) 1024 sc->sc_flags.status_high_speed = 1; 1025 else 1026 sc->sc_flags.status_high_speed = 0; 1027 1028 /* 1029 * After reset all interrupts are on and we need to 1030 * turn them off! 1031 */ 1032 temp = MUSB2_MASK_IRESET; 1033 /* disable resume interrupt */ 1034 temp &= ~MUSB2_MASK_IRESUME; 1035 /* enable suspend interrupt */ 1036 temp |= MUSB2_MASK_ISUSP; 1037 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, temp); 1038 /* disable TX and RX interrupts */ 1039 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, 0); 1040 MUSB2_WRITE_2(sc, MUSB2_REG_INTRXE, 0); 1041 } 1042 /* 1043 * If RXRSM and RXSUSP is set at the same time we interpret 1044 * that like RESUME. Resume is set when there is at least 3 1045 * milliseconds of inactivity on the USB BUS. 1046 */ 1047 if (usb_status & MUSB2_MASK_IRESUME) { 1048 if (sc->sc_flags.status_suspend) { 1049 sc->sc_flags.status_suspend = 0; 1050 sc->sc_flags.change_suspend = 1; 1051 1052 temp = MUSB2_READ_1(sc, MUSB2_REG_INTUSBE); 1053 /* disable resume interrupt */ 1054 temp &= ~MUSB2_MASK_IRESUME; 1055 /* enable suspend interrupt */ 1056 temp |= MUSB2_MASK_ISUSP; 1057 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, temp); 1058 } 1059 } else if (usb_status & MUSB2_MASK_ISUSP) { 1060 if (!sc->sc_flags.status_suspend) { 1061 sc->sc_flags.status_suspend = 1; 1062 sc->sc_flags.change_suspend = 1; 1063 1064 temp = MUSB2_READ_1(sc, MUSB2_REG_INTUSBE); 1065 /* disable suspend interrupt */ 1066 temp &= ~MUSB2_MASK_ISUSP; 1067 /* enable resume interrupt */ 1068 temp |= MUSB2_MASK_IRESUME; 1069 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, temp); 1070 } 1071 } 1072 /* complete root HUB interrupt endpoint */ 1073 1074 usb2_sw_transfer(&sc->sc_root_intr, 1075 &musbotg_root_intr_done); 1076 } 1077 /* check for any endpoint interrupts */ 1078 1079 if (rx_status || tx_status) { 1080 DPRINTFN(4, "real endpoint interrupt " 1081 "rx=0x%04x, tx=0x%04x\n", rx_status, tx_status); 1082 } 1083 /* poll one time regardless of FIFO status */ 1084 1085 musbotg_interrupt_poll(sc); 1086 1087 if (--to) 1088 goto repeat; 1089 1090 USB_BUS_UNLOCK(&sc->sc_bus); 1091} 1092 1093static void 1094musbotg_setup_standard_chain_sub(struct musbotg_std_temp *temp) 1095{ 1096 struct musbotg_td *td; 1097 1098 /* get current Transfer Descriptor */ 1099 td = temp->td_next; 1100 temp->td = td; 1101 1102 /* prepare for next TD */ 1103 temp->td_next = td->obj_next; 1104 1105 /* fill out the Transfer Descriptor */ 1106 td->func = temp->func; 1107 td->pc = temp->pc; 1108 td->offset = temp->offset; 1109 td->remainder = temp->len; 1110 td->error = 0; 1111 td->did_stall = 0; 1112 td->short_pkt = temp->short_pkt; 1113 td->alt_next = temp->setup_alt_next; 1114} 1115 1116static void 1117musbotg_setup_standard_chain(struct usb2_xfer *xfer) 1118{ 1119 struct musbotg_std_temp temp; 1120 struct musbotg_softc *sc; 1121 struct musbotg_td *td; 1122 uint32_t x; 1123 uint8_t ep_no; 1124 1125 DPRINTFN(8, "addr=%d endpt=%d sumlen=%d speed=%d\n", 1126 xfer->address, UE_GET_ADDR(xfer->endpoint), 1127 xfer->sumlen, usb2_get_speed(xfer->xroot->udev)); 1128 1129 temp.max_frame_size = xfer->max_frame_size; 1130 1131 td = xfer->td_start[0]; 1132 xfer->td_transfer_first = td; 1133 xfer->td_transfer_cache = td; 1134 1135 /* setup temp */ 1136 1137 temp.td = NULL; 1138 temp.td_next = xfer->td_start[0]; 1139 temp.offset = 0; 1140 temp.setup_alt_next = xfer->flags_int.short_frames_ok; 1141 1142 sc = MUSBOTG_BUS2SC(xfer->xroot->bus); 1143 ep_no = (xfer->endpoint & UE_ADDR); 1144 1145 /* check if we should prepend a setup message */ 1146 1147 if (xfer->flags_int.control_xfr) { 1148 if (xfer->flags_int.control_hdr) { 1149 1150 temp.func = &musbotg_setup_rx; 1151 temp.len = xfer->frlengths[0]; 1152 temp.pc = xfer->frbuffers + 0; 1153 temp.short_pkt = temp.len ? 1 : 0; 1154 1155 musbotg_setup_standard_chain_sub(&temp); 1156 } 1157 x = 1; 1158 } else { 1159 x = 0; 1160 } 1161 1162 if (x != xfer->nframes) { 1163 if (xfer->endpoint & UE_DIR_IN) { 1164 if (xfer->flags_int.control_xfr) 1165 temp.func = &musbotg_setup_data_tx; 1166 else 1167 temp.func = &musbotg_data_tx; 1168 } else { 1169 if (xfer->flags_int.control_xfr) 1170 temp.func = &musbotg_setup_data_rx; 1171 else 1172 temp.func = &musbotg_data_rx; 1173 } 1174 1175 /* setup "pc" pointer */ 1176 temp.pc = xfer->frbuffers + x; 1177 } 1178 while (x != xfer->nframes) { 1179 1180 /* DATA0 / DATA1 message */ 1181 1182 temp.len = xfer->frlengths[x]; 1183 1184 x++; 1185 1186 if (x == xfer->nframes) { 1187 if (xfer->flags_int.control_xfr) { 1188 if (xfer->flags_int.control_act) { 1189 temp.setup_alt_next = 0; 1190 } 1191 } else { 1192 temp.setup_alt_next = 0; 1193 } 1194 } 1195 if (temp.len == 0) { 1196 1197 /* make sure that we send an USB packet */ 1198 1199 temp.short_pkt = 0; 1200 1201 } else { 1202 1203 /* regular data transfer */ 1204 1205 temp.short_pkt = (xfer->flags.force_short_xfer) ? 0 : 1; 1206 } 1207 1208 musbotg_setup_standard_chain_sub(&temp); 1209 1210 if (xfer->flags_int.isochronous_xfr) { 1211 temp.offset += temp.len; 1212 } else { 1213 /* get next Page Cache pointer */ 1214 temp.pc = xfer->frbuffers + x; 1215 } 1216 } 1217 1218 /* check for control transfer */ 1219 if (xfer->flags_int.control_xfr) { 1220 1221 /* always setup a valid "pc" pointer for status and sync */ 1222 temp.pc = xfer->frbuffers + 0; 1223 temp.len = 0; 1224 temp.short_pkt = 0; 1225 temp.setup_alt_next = 0; 1226 1227 /* check if we should append a status stage */ 1228 if (!xfer->flags_int.control_act) { 1229 /* 1230 * Send a DATA1 message and invert the current 1231 * endpoint direction. 1232 */ 1233 temp.func = &musbotg_setup_status; 1234 musbotg_setup_standard_chain_sub(&temp); 1235 } 1236 } 1237 /* must have at least one frame! */ 1238 td = temp.td; 1239 xfer->td_transfer_last = td; 1240} 1241 1242static void 1243musbotg_timeout(void *arg) 1244{ 1245 struct usb2_xfer *xfer = arg; 1246 1247 DPRINTFN(1, "xfer=%p\n", xfer); 1248 1249 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 1250 1251 /* transfer is transferred */ 1252 musbotg_device_done(xfer, USB_ERR_TIMEOUT); 1253} 1254 1255static void 1256musbotg_ep_int_set(struct usb2_xfer *xfer, uint8_t on) 1257{ 1258 struct musbotg_softc *sc = MUSBOTG_BUS2SC(xfer->xroot->bus); 1259 uint16_t temp; 1260 uint8_t ep_no = xfer->endpoint & UE_ADDR; 1261 1262 /* 1263 * Only enable the endpoint interrupt when we are 1264 * actually waiting for data, hence we are dealing 1265 * with level triggered interrupts ! 1266 */ 1267 if (ep_no == 0) { 1268 temp = MUSB2_READ_2(sc, MUSB2_REG_INTTXE); 1269 if (on) 1270 temp |= MUSB2_MASK_EPINT(0); 1271 else 1272 temp &= ~MUSB2_MASK_EPINT(0); 1273 1274 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, temp); 1275 } else { 1276 if (USB_GET_DATA_ISREAD(xfer)) { 1277 temp = MUSB2_READ_2(sc, MUSB2_REG_INTRXE); 1278 if (on) 1279 temp |= MUSB2_MASK_EPINT(ep_no); 1280 else 1281 temp &= ~MUSB2_MASK_EPINT(ep_no); 1282 MUSB2_WRITE_2(sc, MUSB2_REG_INTRXE, temp); 1283 1284 } else { 1285 temp = MUSB2_READ_2(sc, MUSB2_REG_INTTXE); 1286 if (on) 1287 temp |= MUSB2_MASK_EPINT(ep_no); 1288 else 1289 temp &= ~MUSB2_MASK_EPINT(ep_no); 1290 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, temp); 1291 } 1292 } 1293} 1294 1295static void 1296musbotg_start_standard_chain(struct usb2_xfer *xfer) 1297{ 1298 DPRINTFN(8, "\n"); 1299 1300 /* poll one time */ 1301 if (musbotg_xfer_do_fifo(xfer)) { 1302 1303 musbotg_ep_int_set(xfer, 1); 1304 1305 DPRINTFN(14, "enabled interrupts on endpoint\n"); 1306 1307 /* put transfer on interrupt queue */ 1308 usb2_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 1309 1310 /* start timeout, if any */ 1311 if (xfer->timeout != 0) { 1312 usb2_transfer_timeout_ms(xfer, 1313 &musbotg_timeout, xfer->timeout); 1314 } 1315 } 1316} 1317 1318static void 1319musbotg_root_intr_done(struct usb2_xfer *xfer, 1320 struct usb2_sw_transfer *std) 1321{ 1322 struct musbotg_softc *sc = MUSBOTG_BUS2SC(xfer->xroot->bus); 1323 1324 DPRINTFN(8, "\n"); 1325 1326 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1327 1328 if (std->state != USB_SW_TR_PRE_DATA) { 1329 if (std->state == USB_SW_TR_PRE_CALLBACK) { 1330 /* transfer transferred */ 1331 musbotg_device_done(xfer, std->err); 1332 } 1333 goto done; 1334 } 1335 /* setup buffer */ 1336 std->ptr = sc->sc_hub_idata; 1337 std->len = sizeof(sc->sc_hub_idata); 1338 1339 /* set port bit */ 1340 sc->sc_hub_idata[0] = 0x02; /* we only have one port */ 1341 1342done: 1343 return; 1344} 1345 1346static usb2_error_t 1347musbotg_standard_done_sub(struct usb2_xfer *xfer) 1348{ 1349 struct musbotg_td *td; 1350 uint32_t len; 1351 uint8_t error; 1352 1353 DPRINTFN(8, "\n"); 1354 1355 td = xfer->td_transfer_cache; 1356 1357 do { 1358 len = td->remainder; 1359 1360 if (xfer->aframes != xfer->nframes) { 1361 /* 1362 * Verify the length and subtract 1363 * the remainder from "frlengths[]": 1364 */ 1365 if (len > xfer->frlengths[xfer->aframes]) { 1366 td->error = 1; 1367 } else { 1368 xfer->frlengths[xfer->aframes] -= len; 1369 } 1370 } 1371 /* Check for transfer error */ 1372 if (td->error) { 1373 /* the transfer is finished */ 1374 error = 1; 1375 td = NULL; 1376 break; 1377 } 1378 /* Check for short transfer */ 1379 if (len > 0) { 1380 if (xfer->flags_int.short_frames_ok) { 1381 /* follow alt next */ 1382 if (td->alt_next) { 1383 td = td->obj_next; 1384 } else { 1385 td = NULL; 1386 } 1387 } else { 1388 /* the transfer is finished */ 1389 td = NULL; 1390 } 1391 error = 0; 1392 break; 1393 } 1394 td = td->obj_next; 1395 1396 /* this USB frame is complete */ 1397 error = 0; 1398 break; 1399 1400 } while (0); 1401 1402 /* update transfer cache */ 1403 1404 xfer->td_transfer_cache = td; 1405 1406 return (error ? 1407 USB_ERR_STALLED : USB_ERR_NORMAL_COMPLETION); 1408} 1409 1410static void 1411musbotg_standard_done(struct usb2_xfer *xfer) 1412{ 1413 usb2_error_t err = 0; 1414 1415 DPRINTFN(12, "xfer=%p pipe=%p transfer done\n", 1416 xfer, xfer->pipe); 1417 1418 /* reset scanner */ 1419 1420 xfer->td_transfer_cache = xfer->td_transfer_first; 1421 1422 if (xfer->flags_int.control_xfr) { 1423 1424 if (xfer->flags_int.control_hdr) { 1425 1426 err = musbotg_standard_done_sub(xfer); 1427 } 1428 xfer->aframes = 1; 1429 1430 if (xfer->td_transfer_cache == NULL) { 1431 goto done; 1432 } 1433 } 1434 while (xfer->aframes != xfer->nframes) { 1435 1436 err = musbotg_standard_done_sub(xfer); 1437 xfer->aframes++; 1438 1439 if (xfer->td_transfer_cache == NULL) { 1440 goto done; 1441 } 1442 } 1443 1444 if (xfer->flags_int.control_xfr && 1445 !xfer->flags_int.control_act) { 1446 1447 err = musbotg_standard_done_sub(xfer); 1448 } 1449done: 1450 musbotg_device_done(xfer, err); 1451} 1452 1453/*------------------------------------------------------------------------* 1454 * musbotg_device_done 1455 * 1456 * NOTE: this function can be called more than one time on the 1457 * same USB transfer! 1458 *------------------------------------------------------------------------*/ 1459static void 1460musbotg_device_done(struct usb2_xfer *xfer, usb2_error_t error) 1461{ 1462 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 1463 1464 DPRINTFN(2, "xfer=%p, pipe=%p, error=%d\n", 1465 xfer, xfer->pipe, error); 1466 1467 if (xfer->flags_int.usb2_mode == USB_MODE_DEVICE) { 1468 1469 musbotg_ep_int_set(xfer, 0); 1470 1471 DPRINTFN(14, "disabled interrupts on endpoint\n"); 1472 } 1473 /* dequeue transfer and start next transfer */ 1474 usb2_transfer_done(xfer, error); 1475} 1476 1477static void 1478musbotg_set_stall(struct usb2_device *udev, struct usb2_xfer *xfer, 1479 struct usb2_pipe *pipe) 1480{ 1481 struct musbotg_softc *sc; 1482 uint8_t ep_no; 1483 1484 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 1485 1486 DPRINTFN(4, "pipe=%p\n", pipe); 1487 1488 if (xfer) { 1489 /* cancel any ongoing transfers */ 1490 musbotg_device_done(xfer, USB_ERR_STALLED); 1491 } 1492 /* set FORCESTALL */ 1493 sc = MUSBOTG_BUS2SC(udev->bus); 1494 1495 ep_no = (pipe->edesc->bEndpointAddress & UE_ADDR); 1496 1497 /* select endpoint */ 1498 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, ep_no); 1499 1500 if (pipe->edesc->bEndpointAddress & UE_DIR_IN) { 1501 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 1502 MUSB2_MASK_CSRL_TXSENDSTALL); 1503 } else { 1504 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 1505 MUSB2_MASK_CSRL_RXSENDSTALL); 1506 } 1507} 1508 1509static void 1510musbotg_clear_stall_sub(struct musbotg_softc *sc, uint16_t wMaxPacket, 1511 uint8_t ep_no, uint8_t ep_type, uint8_t ep_dir) 1512{ 1513 uint16_t mps; 1514 uint16_t temp; 1515 uint8_t csr; 1516 1517 if (ep_type == UE_CONTROL) { 1518 /* clearing stall is not needed */ 1519 return; 1520 } 1521 /* select endpoint */ 1522 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, ep_no); 1523 1524 /* compute max frame size */ 1525 mps = wMaxPacket & 0x7FF; 1526 switch ((wMaxPacket >> 11) & 3) { 1527 case 1: 1528 mps *= 2; 1529 break; 1530 case 2: 1531 mps *= 3; 1532 break; 1533 default: 1534 break; 1535 } 1536 1537 if (ep_dir == UE_DIR_IN) { 1538 1539 temp = 0; 1540 1541 /* Configure endpoint */ 1542 switch (ep_type) { 1543 case UE_INTERRUPT: 1544 MUSB2_WRITE_1(sc, MUSB2_REG_TXMAXP, wMaxPacket); 1545 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, 1546 MUSB2_MASK_CSRH_TXMODE | temp); 1547 break; 1548 case UE_ISOCHRONOUS: 1549 MUSB2_WRITE_1(sc, MUSB2_REG_TXMAXP, wMaxPacket); 1550 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, 1551 MUSB2_MASK_CSRH_TXMODE | 1552 MUSB2_MASK_CSRH_TXISO | temp); 1553 break; 1554 case UE_BULK: 1555 MUSB2_WRITE_1(sc, MUSB2_REG_TXMAXP, wMaxPacket); 1556 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, 1557 MUSB2_MASK_CSRH_TXMODE | temp); 1558 break; 1559 default: 1560 break; 1561 } 1562 1563 /* Need to flush twice in case of double bufring */ 1564 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 1565 if (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) { 1566 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 1567 MUSB2_MASK_CSRL_TXFFLUSH); 1568 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 1569 if (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) { 1570 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 1571 MUSB2_MASK_CSRL_TXFFLUSH); 1572 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 1573 } 1574 } 1575 /* reset data toggle */ 1576 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 1577 MUSB2_MASK_CSRL_TXDT_CLR); 1578 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0); 1579 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 1580 1581 /* set double/single buffering */ 1582 temp = MUSB2_READ_2(sc, MUSB2_REG_TXDBDIS); 1583 if (mps <= (sc->sc_hw_ep_profile[ep_no]. 1584 max_in_frame_size / 2)) { 1585 /* double buffer */ 1586 temp &= ~(1 << ep_no); 1587 } else { 1588 /* single buffer */ 1589 temp |= (1 << ep_no); 1590 } 1591 MUSB2_WRITE_2(sc, MUSB2_REG_TXDBDIS, temp); 1592 1593 /* clear sent stall */ 1594 if (csr & MUSB2_MASK_CSRL_TXSENTSTALL) { 1595 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0); 1596 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 1597 } 1598 } else { 1599 1600 temp = 0; 1601 1602 /* Configure endpoint */ 1603 switch (ep_type) { 1604 case UE_INTERRUPT: 1605 MUSB2_WRITE_1(sc, MUSB2_REG_RXMAXP, wMaxPacket); 1606 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH, 1607 MUSB2_MASK_CSRH_RXNYET | temp); 1608 break; 1609 case UE_ISOCHRONOUS: 1610 MUSB2_WRITE_1(sc, MUSB2_REG_RXMAXP, wMaxPacket); 1611 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH, 1612 MUSB2_MASK_CSRH_RXNYET | 1613 MUSB2_MASK_CSRH_RXISO | temp); 1614 break; 1615 case UE_BULK: 1616 MUSB2_WRITE_1(sc, MUSB2_REG_RXMAXP, wMaxPacket); 1617 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH, temp); 1618 break; 1619 default: 1620 break; 1621 } 1622 1623 /* Need to flush twice in case of double bufring */ 1624 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL); 1625 if (csr & MUSB2_MASK_CSRL_RXPKTRDY) { 1626 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 1627 MUSB2_MASK_CSRL_RXFFLUSH); 1628 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL); 1629 if (csr & MUSB2_MASK_CSRL_RXPKTRDY) { 1630 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 1631 MUSB2_MASK_CSRL_RXFFLUSH); 1632 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL); 1633 } 1634 } 1635 /* reset data toggle */ 1636 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 1637 MUSB2_MASK_CSRL_RXDT_CLR); 1638 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 0); 1639 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL); 1640 1641 /* set double/single buffering */ 1642 temp = MUSB2_READ_2(sc, MUSB2_REG_RXDBDIS); 1643 if (mps <= (sc->sc_hw_ep_profile[ep_no]. 1644 max_out_frame_size / 2)) { 1645 /* double buffer */ 1646 temp &= ~(1 << ep_no); 1647 } else { 1648 /* single buffer */ 1649 temp |= (1 << ep_no); 1650 } 1651 MUSB2_WRITE_2(sc, MUSB2_REG_RXDBDIS, temp); 1652 1653 /* clear sent stall */ 1654 if (csr & MUSB2_MASK_CSRL_RXSENTSTALL) { 1655 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 0); 1656 } 1657 } 1658} 1659 1660static void 1661musbotg_clear_stall(struct usb2_device *udev, struct usb2_pipe *pipe) 1662{ 1663 struct musbotg_softc *sc; 1664 struct usb2_endpoint_descriptor *ed; 1665 1666 DPRINTFN(4, "pipe=%p\n", pipe); 1667 1668 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 1669 1670 /* check mode */ 1671 if (udev->flags.usb2_mode != USB_MODE_DEVICE) { 1672 /* not supported */ 1673 return; 1674 } 1675 /* get softc */ 1676 sc = MUSBOTG_BUS2SC(udev->bus); 1677 1678 /* get endpoint descriptor */ 1679 ed = pipe->edesc; 1680 1681 /* reset endpoint */ 1682 musbotg_clear_stall_sub(sc, 1683 UGETW(ed->wMaxPacketSize), 1684 (ed->bEndpointAddress & UE_ADDR), 1685 (ed->bmAttributes & UE_XFERTYPE), 1686 (ed->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT))); 1687} 1688 1689usb2_error_t 1690musbotg_init(struct musbotg_softc *sc) 1691{ 1692 struct usb2_hw_ep_profile *pf; 1693 uint8_t nrx; 1694 uint8_t ntx; 1695 uint8_t temp; 1696 uint8_t fsize; 1697 uint8_t frx; 1698 uint8_t ftx; 1699 1700 DPRINTFN(1, "start\n"); 1701 1702 /* set up the bus structure */ 1703 sc->sc_bus.usbrev = USB_REV_2_0; 1704 sc->sc_bus.methods = &musbotg_bus_methods; 1705 1706 USB_BUS_LOCK(&sc->sc_bus); 1707 1708 /* turn on clocks */ 1709 1710 if (sc->sc_clocks_on) { 1711 (sc->sc_clocks_on) (sc->sc_clocks_arg); 1712 } 1713 /* wait a little for things to stabilise */ 1714 usb2_pause_mtx(&sc->sc_bus.bus_mtx, hz / 1000); 1715 1716 /* disable all interrupts */ 1717 1718 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, 0); 1719 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, 0); 1720 MUSB2_WRITE_2(sc, MUSB2_REG_INTRXE, 0); 1721 1722 /* disable pullup */ 1723 1724 musbotg_pull_common(sc, 0); 1725 1726 /* wait a little bit (10ms) */ 1727 usb2_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100); 1728 1729 /* disable double packet buffering */ 1730 MUSB2_WRITE_2(sc, MUSB2_REG_RXDBDIS, 0xFFFF); 1731 MUSB2_WRITE_2(sc, MUSB2_REG_TXDBDIS, 0xFFFF); 1732 1733 /* enable HighSpeed and ISO Update flags */ 1734 1735 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, 1736 MUSB2_MASK_HSENAB | MUSB2_MASK_ISOUPD); 1737 1738 /* clear Session bit, if set */ 1739 1740 temp = MUSB2_READ_1(sc, MUSB2_REG_DEVCTL); 1741 temp &= ~MUSB2_MASK_SESS; 1742 MUSB2_WRITE_1(sc, MUSB2_REG_DEVCTL, temp); 1743 1744 DPRINTF("DEVCTL=0x%02x\n", temp); 1745 1746 /* disable testmode */ 1747 1748 MUSB2_WRITE_1(sc, MUSB2_REG_TESTMODE, 0); 1749 1750 /* set default value */ 1751 1752 MUSB2_WRITE_1(sc, MUSB2_REG_MISC, 0); 1753 1754 /* select endpoint index 0 */ 1755 1756 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); 1757 1758 /* read out number of endpoints */ 1759 1760 nrx = 1761 (MUSB2_READ_1(sc, MUSB2_REG_EPINFO) / 16); 1762 1763 ntx = 1764 (MUSB2_READ_1(sc, MUSB2_REG_EPINFO) % 16); 1765 1766 /* these numbers exclude the control endpoint */ 1767 1768 DPRINTFN(2, "RX/TX endpoints: %u/%u\n", nrx, ntx); 1769 1770 sc->sc_ep_max = (nrx > ntx) ? nrx : ntx; 1771 if (sc->sc_ep_max == 0) { 1772 DPRINTFN(2, "ERROR: Looks like the clocks are off!\n"); 1773 } 1774 /* read out configuration data */ 1775 1776 sc->sc_conf_data = MUSB2_READ_1(sc, MUSB2_REG_CONFDATA); 1777 1778 DPRINTFN(2, "Config Data: 0x%02x\n", 1779 sc->sc_conf_data); 1780 1781 DPRINTFN(2, "HW version: 0x%04x\n", 1782 MUSB2_READ_1(sc, MUSB2_REG_HWVERS)); 1783 1784 /* initialise endpoint profiles */ 1785 1786 for (temp = 1; temp <= sc->sc_ep_max; temp++) { 1787 pf = sc->sc_hw_ep_profile + temp; 1788 1789 /* select endpoint */ 1790 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, temp); 1791 1792 fsize = MUSB2_READ_1(sc, MUSB2_REG_FSIZE); 1793 frx = (fsize & MUSB2_MASK_RX_FSIZE) / 16;; 1794 ftx = (fsize & MUSB2_MASK_TX_FSIZE); 1795 1796 DPRINTF("Endpoint %u FIFO size: IN=%u, OUT=%u\n", 1797 temp, pf->max_in_frame_size, 1798 pf->max_out_frame_size); 1799 1800 if (frx && ftx && (temp <= nrx) && (temp <= ntx)) { 1801 pf->max_in_frame_size = 1 << ftx; 1802 pf->max_out_frame_size = 1 << frx; 1803 pf->is_simplex = 0; /* duplex */ 1804 pf->support_multi_buffer = 1; 1805 pf->support_bulk = 1; 1806 pf->support_interrupt = 1; 1807 pf->support_isochronous = 1; 1808 pf->support_in = 1; 1809 pf->support_out = 1; 1810 } else if (frx && (temp <= nrx)) { 1811 pf->max_out_frame_size = 1 << frx; 1812 pf->is_simplex = 1; /* simplex */ 1813 pf->support_multi_buffer = 1; 1814 pf->support_bulk = 1; 1815 pf->support_interrupt = 1; 1816 pf->support_isochronous = 1; 1817 pf->support_out = 1; 1818 } else if (ftx && (temp <= ntx)) { 1819 pf->max_in_frame_size = 1 << ftx; 1820 pf->is_simplex = 1; /* simplex */ 1821 pf->support_multi_buffer = 1; 1822 pf->support_bulk = 1; 1823 pf->support_interrupt = 1; 1824 pf->support_isochronous = 1; 1825 pf->support_in = 1; 1826 } 1827 } 1828 1829 /* turn on default interrupts */ 1830 1831 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, 1832 MUSB2_MASK_IRESET); 1833 1834 musbotg_clocks_off(sc); 1835 1836 USB_BUS_UNLOCK(&sc->sc_bus); 1837 1838 /* catch any lost interrupts */ 1839 1840 musbotg_do_poll(&sc->sc_bus); 1841 1842 return (0); /* success */ 1843} 1844 1845void 1846musbotg_uninit(struct musbotg_softc *sc) 1847{ 1848 USB_BUS_LOCK(&sc->sc_bus); 1849 1850 /* disable all interrupts */ 1851 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, 0); 1852 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, 0); 1853 MUSB2_WRITE_2(sc, MUSB2_REG_INTRXE, 0); 1854 1855 sc->sc_flags.port_powered = 0; 1856 sc->sc_flags.status_vbus = 0; 1857 sc->sc_flags.status_bus_reset = 0; 1858 sc->sc_flags.status_suspend = 0; 1859 sc->sc_flags.change_suspend = 0; 1860 sc->sc_flags.change_connect = 1; 1861 1862 musbotg_pull_down(sc); 1863 musbotg_clocks_off(sc); 1864 USB_BUS_UNLOCK(&sc->sc_bus); 1865} 1866 1867void 1868musbotg_suspend(struct musbotg_softc *sc) 1869{ 1870 return; 1871} 1872 1873void 1874musbotg_resume(struct musbotg_softc *sc) 1875{ 1876 return; 1877} 1878 1879static void 1880musbotg_do_poll(struct usb2_bus *bus) 1881{ 1882 struct musbotg_softc *sc = MUSBOTG_BUS2SC(bus); 1883 1884 USB_BUS_LOCK(&sc->sc_bus); 1885 musbotg_interrupt_poll(sc); 1886 musbotg_root_ctrl_poll(sc); 1887 USB_BUS_UNLOCK(&sc->sc_bus); 1888} 1889 1890/*------------------------------------------------------------------------* 1891 * musbotg bulk support 1892 *------------------------------------------------------------------------*/ 1893static void 1894musbotg_device_bulk_open(struct usb2_xfer *xfer) 1895{ 1896 return; 1897} 1898 1899static void 1900musbotg_device_bulk_close(struct usb2_xfer *xfer) 1901{ 1902 musbotg_device_done(xfer, USB_ERR_CANCELLED); 1903} 1904 1905static void 1906musbotg_device_bulk_enter(struct usb2_xfer *xfer) 1907{ 1908 return; 1909} 1910 1911static void 1912musbotg_device_bulk_start(struct usb2_xfer *xfer) 1913{ 1914 /* setup TDs */ 1915 musbotg_setup_standard_chain(xfer); 1916 musbotg_start_standard_chain(xfer); 1917} 1918 1919struct usb2_pipe_methods musbotg_device_bulk_methods = 1920{ 1921 .open = musbotg_device_bulk_open, 1922 .close = musbotg_device_bulk_close, 1923 .enter = musbotg_device_bulk_enter, 1924 .start = musbotg_device_bulk_start, 1925 .enter_is_cancelable = 1, 1926 .start_is_cancelable = 1, 1927}; 1928 1929/*------------------------------------------------------------------------* 1930 * musbotg control support 1931 *------------------------------------------------------------------------*/ 1932static void 1933musbotg_device_ctrl_open(struct usb2_xfer *xfer) 1934{ 1935 return; 1936} 1937 1938static void 1939musbotg_device_ctrl_close(struct usb2_xfer *xfer) 1940{ 1941 musbotg_device_done(xfer, USB_ERR_CANCELLED); 1942} 1943 1944static void 1945musbotg_device_ctrl_enter(struct usb2_xfer *xfer) 1946{ 1947 return; 1948} 1949 1950static void 1951musbotg_device_ctrl_start(struct usb2_xfer *xfer) 1952{ 1953 /* setup TDs */ 1954 musbotg_setup_standard_chain(xfer); 1955 musbotg_start_standard_chain(xfer); 1956} 1957 1958struct usb2_pipe_methods musbotg_device_ctrl_methods = 1959{ 1960 .open = musbotg_device_ctrl_open, 1961 .close = musbotg_device_ctrl_close, 1962 .enter = musbotg_device_ctrl_enter, 1963 .start = musbotg_device_ctrl_start, 1964 .enter_is_cancelable = 1, 1965 .start_is_cancelable = 1, 1966}; 1967 1968/*------------------------------------------------------------------------* 1969 * musbotg interrupt support 1970 *------------------------------------------------------------------------*/ 1971static void 1972musbotg_device_intr_open(struct usb2_xfer *xfer) 1973{ 1974 return; 1975} 1976 1977static void 1978musbotg_device_intr_close(struct usb2_xfer *xfer) 1979{ 1980 musbotg_device_done(xfer, USB_ERR_CANCELLED); 1981} 1982 1983static void 1984musbotg_device_intr_enter(struct usb2_xfer *xfer) 1985{ 1986 return; 1987} 1988 1989static void 1990musbotg_device_intr_start(struct usb2_xfer *xfer) 1991{ 1992 /* setup TDs */ 1993 musbotg_setup_standard_chain(xfer); 1994 musbotg_start_standard_chain(xfer); 1995} 1996 1997struct usb2_pipe_methods musbotg_device_intr_methods = 1998{ 1999 .open = musbotg_device_intr_open, 2000 .close = musbotg_device_intr_close, 2001 .enter = musbotg_device_intr_enter, 2002 .start = musbotg_device_intr_start, 2003 .enter_is_cancelable = 1, 2004 .start_is_cancelable = 1, 2005}; 2006 2007/*------------------------------------------------------------------------* 2008 * musbotg full speed isochronous support 2009 *------------------------------------------------------------------------*/ 2010static void 2011musbotg_device_isoc_open(struct usb2_xfer *xfer) 2012{ 2013 return; 2014} 2015 2016static void 2017musbotg_device_isoc_close(struct usb2_xfer *xfer) 2018{ 2019 musbotg_device_done(xfer, USB_ERR_CANCELLED); 2020} 2021 2022static void 2023musbotg_device_isoc_enter(struct usb2_xfer *xfer) 2024{ 2025 struct musbotg_softc *sc = MUSBOTG_BUS2SC(xfer->xroot->bus); 2026 uint32_t temp; 2027 uint32_t nframes; 2028 uint32_t fs_frames; 2029 2030 DPRINTFN(5, "xfer=%p next=%d nframes=%d\n", 2031 xfer, xfer->pipe->isoc_next, xfer->nframes); 2032 2033 /* get the current frame index */ 2034 2035 nframes = MUSB2_READ_2(sc, MUSB2_REG_FRAME); 2036 2037 /* 2038 * check if the frame index is within the window where the frames 2039 * will be inserted 2040 */ 2041 temp = (nframes - xfer->pipe->isoc_next) & MUSB2_MASK_FRAME; 2042 2043 if (usb2_get_speed(xfer->xroot->udev) == USB_SPEED_HIGH) { 2044 fs_frames = (xfer->nframes + 7) / 8; 2045 } else { 2046 fs_frames = xfer->nframes; 2047 } 2048 2049 if ((xfer->pipe->is_synced == 0) || 2050 (temp < fs_frames)) { 2051 /* 2052 * If there is data underflow or the pipe queue is 2053 * empty we schedule the transfer a few frames ahead 2054 * of the current frame position. Else two isochronous 2055 * transfers might overlap. 2056 */ 2057 xfer->pipe->isoc_next = (nframes + 3) & MUSB2_MASK_FRAME; 2058 xfer->pipe->is_synced = 1; 2059 DPRINTFN(2, "start next=%d\n", xfer->pipe->isoc_next); 2060 } 2061 /* 2062 * compute how many milliseconds the insertion is ahead of the 2063 * current frame position: 2064 */ 2065 temp = (xfer->pipe->isoc_next - nframes) & MUSB2_MASK_FRAME; 2066 2067 /* 2068 * pre-compute when the isochronous transfer will be finished: 2069 */ 2070 xfer->isoc_time_complete = 2071 usb2_isoc_time_expand(&sc->sc_bus, nframes) + temp + 2072 fs_frames; 2073 2074 /* compute frame number for next insertion */ 2075 xfer->pipe->isoc_next += fs_frames; 2076 2077 /* setup TDs */ 2078 musbotg_setup_standard_chain(xfer); 2079} 2080 2081static void 2082musbotg_device_isoc_start(struct usb2_xfer *xfer) 2083{ 2084 /* start TD chain */ 2085 musbotg_start_standard_chain(xfer); 2086} 2087 2088struct usb2_pipe_methods musbotg_device_isoc_methods = 2089{ 2090 .open = musbotg_device_isoc_open, 2091 .close = musbotg_device_isoc_close, 2092 .enter = musbotg_device_isoc_enter, 2093 .start = musbotg_device_isoc_start, 2094 .enter_is_cancelable = 1, 2095 .start_is_cancelable = 1, 2096}; 2097 2098/*------------------------------------------------------------------------* 2099 * musbotg root control support 2100 *------------------------------------------------------------------------* 2101 * simulate a hardware HUB by handling 2102 * all the necessary requests 2103 *------------------------------------------------------------------------*/ 2104static void 2105musbotg_root_ctrl_open(struct usb2_xfer *xfer) 2106{ 2107 return; 2108} 2109 2110static void 2111musbotg_root_ctrl_close(struct usb2_xfer *xfer) 2112{ 2113 struct musbotg_softc *sc = MUSBOTG_BUS2SC(xfer->xroot->bus); 2114 2115 if (sc->sc_root_ctrl.xfer == xfer) { 2116 sc->sc_root_ctrl.xfer = NULL; 2117 } 2118 musbotg_device_done(xfer, USB_ERR_CANCELLED); 2119} 2120 2121/* 2122 * USB descriptors for the virtual Root HUB: 2123 */ 2124 2125static const struct usb2_device_descriptor musbotg_devd = { 2126 .bLength = sizeof(struct usb2_device_descriptor), 2127 .bDescriptorType = UDESC_DEVICE, 2128 .bcdUSB = {0x00, 0x02}, 2129 .bDeviceClass = UDCLASS_HUB, 2130 .bDeviceSubClass = UDSUBCLASS_HUB, 2131 .bDeviceProtocol = UDPROTO_HSHUBSTT, 2132 .bMaxPacketSize = 64, 2133 .bcdDevice = {0x00, 0x01}, 2134 .iManufacturer = 1, 2135 .iProduct = 2, 2136 .bNumConfigurations = 1, 2137}; 2138 2139static const struct usb2_device_qualifier musbotg_odevd = { 2140 .bLength = sizeof(struct usb2_device_qualifier), 2141 .bDescriptorType = UDESC_DEVICE_QUALIFIER, 2142 .bcdUSB = {0x00, 0x02}, 2143 .bDeviceClass = UDCLASS_HUB, 2144 .bDeviceSubClass = UDSUBCLASS_HUB, 2145 .bDeviceProtocol = UDPROTO_FSHUB, 2146 .bMaxPacketSize0 = 0, 2147 .bNumConfigurations = 0, 2148}; 2149 2150static const struct musbotg_config_desc musbotg_confd = { 2151 .confd = { 2152 .bLength = sizeof(struct usb2_config_descriptor), 2153 .bDescriptorType = UDESC_CONFIG, 2154 .wTotalLength[0] = sizeof(musbotg_confd), 2155 .bNumInterface = 1, 2156 .bConfigurationValue = 1, 2157 .iConfiguration = 0, 2158 .bmAttributes = UC_SELF_POWERED, 2159 .bMaxPower = 0, 2160 }, 2161 .ifcd = { 2162 .bLength = sizeof(struct usb2_interface_descriptor), 2163 .bDescriptorType = UDESC_INTERFACE, 2164 .bNumEndpoints = 1, 2165 .bInterfaceClass = UICLASS_HUB, 2166 .bInterfaceSubClass = UISUBCLASS_HUB, 2167 .bInterfaceProtocol = UIPROTO_HSHUBSTT, 2168 }, 2169 2170 .endpd = { 2171 .bLength = sizeof(struct usb2_endpoint_descriptor), 2172 .bDescriptorType = UDESC_ENDPOINT, 2173 .bEndpointAddress = (UE_DIR_IN | MUSBOTG_INTR_ENDPT), 2174 .bmAttributes = UE_INTERRUPT, 2175 .wMaxPacketSize[0] = 8, 2176 .bInterval = 255, 2177 }, 2178}; 2179 2180static const struct usb2_hub_descriptor_min musbotg_hubd = { 2181 .bDescLength = sizeof(musbotg_hubd), 2182 .bDescriptorType = UDESC_HUB, 2183 .bNbrPorts = 1, 2184 .wHubCharacteristics[0] = 2185 (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL) & 0xFF, 2186 .wHubCharacteristics[1] = 2187 (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL) >> 16, 2188 .bPwrOn2PwrGood = 50, 2189 .bHubContrCurrent = 0, 2190 .DeviceRemovable = {0}, /* port is removable */ 2191}; 2192 2193#define STRING_LANG \ 2194 0x09, 0x04, /* American English */ 2195 2196#define STRING_VENDOR \ 2197 'M', 0, 'e', 0, 'n', 0, 't', 0, 'o', 0, 'r', 0, ' ', 0, \ 2198 'G', 0, 'r', 0, 'a', 0, 'p', 0, 'h', 0, 'i', 0, 'c', 0, 's', 0 2199 2200#define STRING_PRODUCT \ 2201 'O', 0, 'T', 0, 'G', 0, ' ', 0, 'R', 0, \ 2202 'o', 0, 'o', 0, 't', 0, ' ', 0, 'H', 0, \ 2203 'U', 0, 'B', 0, 2204 2205USB_MAKE_STRING_DESC(STRING_LANG, musbotg_langtab); 2206USB_MAKE_STRING_DESC(STRING_VENDOR, musbotg_vendor); 2207USB_MAKE_STRING_DESC(STRING_PRODUCT, musbotg_product); 2208 2209static void 2210musbotg_root_ctrl_enter(struct usb2_xfer *xfer) 2211{ 2212 return; 2213} 2214 2215static void 2216musbotg_root_ctrl_start(struct usb2_xfer *xfer) 2217{ 2218 struct musbotg_softc *sc = MUSBOTG_BUS2SC(xfer->xroot->bus); 2219 2220 sc->sc_root_ctrl.xfer = xfer; 2221 2222 usb2_bus_roothub_exec(xfer->xroot->bus); 2223} 2224 2225static void 2226musbotg_root_ctrl_task(struct usb2_bus *bus) 2227{ 2228 musbotg_root_ctrl_poll(MUSBOTG_BUS2SC(bus)); 2229} 2230 2231static void 2232musbotg_root_ctrl_done(struct usb2_xfer *xfer, 2233 struct usb2_sw_transfer *std) 2234{ 2235 struct musbotg_softc *sc = MUSBOTG_BUS2SC(xfer->xroot->bus); 2236 uint16_t value; 2237 uint16_t index; 2238 2239 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2240 2241 if (std->state != USB_SW_TR_SETUP) { 2242 if (std->state == USB_SW_TR_PRE_CALLBACK) { 2243 /* transfer transferred */ 2244 musbotg_device_done(xfer, std->err); 2245 } 2246 goto done; 2247 } 2248 /* buffer reset */ 2249 std->ptr = USB_ADD_BYTES(&sc->sc_hub_temp, 0); 2250 std->len = 0; 2251 2252 value = UGETW(std->req.wValue); 2253 index = UGETW(std->req.wIndex); 2254 2255 /* demultiplex the control request */ 2256 2257 switch (std->req.bmRequestType) { 2258 case UT_READ_DEVICE: 2259 switch (std->req.bRequest) { 2260 case UR_GET_DESCRIPTOR: 2261 goto tr_handle_get_descriptor; 2262 case UR_GET_CONFIG: 2263 goto tr_handle_get_config; 2264 case UR_GET_STATUS: 2265 goto tr_handle_get_status; 2266 default: 2267 goto tr_stalled; 2268 } 2269 break; 2270 2271 case UT_WRITE_DEVICE: 2272 switch (std->req.bRequest) { 2273 case UR_SET_ADDRESS: 2274 goto tr_handle_set_address; 2275 case UR_SET_CONFIG: 2276 goto tr_handle_set_config; 2277 case UR_CLEAR_FEATURE: 2278 goto tr_valid; /* nop */ 2279 case UR_SET_DESCRIPTOR: 2280 goto tr_valid; /* nop */ 2281 case UR_SET_FEATURE: 2282 default: 2283 goto tr_stalled; 2284 } 2285 break; 2286 2287 case UT_WRITE_ENDPOINT: 2288 switch (std->req.bRequest) { 2289 case UR_CLEAR_FEATURE: 2290 switch (UGETW(std->req.wValue)) { 2291 case UF_ENDPOINT_HALT: 2292 goto tr_handle_clear_halt; 2293 case UF_DEVICE_REMOTE_WAKEUP: 2294 goto tr_handle_clear_wakeup; 2295 default: 2296 goto tr_stalled; 2297 } 2298 break; 2299 case UR_SET_FEATURE: 2300 switch (UGETW(std->req.wValue)) { 2301 case UF_ENDPOINT_HALT: 2302 goto tr_handle_set_halt; 2303 case UF_DEVICE_REMOTE_WAKEUP: 2304 goto tr_handle_set_wakeup; 2305 default: 2306 goto tr_stalled; 2307 } 2308 break; 2309 case UR_SYNCH_FRAME: 2310 goto tr_valid; /* nop */ 2311 default: 2312 goto tr_stalled; 2313 } 2314 break; 2315 2316 case UT_READ_ENDPOINT: 2317 switch (std->req.bRequest) { 2318 case UR_GET_STATUS: 2319 goto tr_handle_get_ep_status; 2320 default: 2321 goto tr_stalled; 2322 } 2323 break; 2324 2325 case UT_WRITE_INTERFACE: 2326 switch (std->req.bRequest) { 2327 case UR_SET_INTERFACE: 2328 goto tr_handle_set_interface; 2329 case UR_CLEAR_FEATURE: 2330 goto tr_valid; /* nop */ 2331 case UR_SET_FEATURE: 2332 default: 2333 goto tr_stalled; 2334 } 2335 break; 2336 2337 case UT_READ_INTERFACE: 2338 switch (std->req.bRequest) { 2339 case UR_GET_INTERFACE: 2340 goto tr_handle_get_interface; 2341 case UR_GET_STATUS: 2342 goto tr_handle_get_iface_status; 2343 default: 2344 goto tr_stalled; 2345 } 2346 break; 2347 2348 case UT_WRITE_CLASS_INTERFACE: 2349 case UT_WRITE_VENDOR_INTERFACE: 2350 /* XXX forward */ 2351 break; 2352 2353 case UT_READ_CLASS_INTERFACE: 2354 case UT_READ_VENDOR_INTERFACE: 2355 /* XXX forward */ 2356 break; 2357 2358 case UT_WRITE_CLASS_DEVICE: 2359 switch (std->req.bRequest) { 2360 case UR_CLEAR_FEATURE: 2361 goto tr_valid; 2362 case UR_SET_DESCRIPTOR: 2363 case UR_SET_FEATURE: 2364 break; 2365 default: 2366 goto tr_stalled; 2367 } 2368 break; 2369 2370 case UT_WRITE_CLASS_OTHER: 2371 switch (std->req.bRequest) { 2372 case UR_CLEAR_FEATURE: 2373 goto tr_handle_clear_port_feature; 2374 case UR_SET_FEATURE: 2375 goto tr_handle_set_port_feature; 2376 case UR_CLEAR_TT_BUFFER: 2377 case UR_RESET_TT: 2378 case UR_STOP_TT: 2379 goto tr_valid; 2380 2381 default: 2382 goto tr_stalled; 2383 } 2384 break; 2385 2386 case UT_READ_CLASS_OTHER: 2387 switch (std->req.bRequest) { 2388 case UR_GET_TT_STATE: 2389 goto tr_handle_get_tt_state; 2390 case UR_GET_STATUS: 2391 goto tr_handle_get_port_status; 2392 default: 2393 goto tr_stalled; 2394 } 2395 break; 2396 2397 case UT_READ_CLASS_DEVICE: 2398 switch (std->req.bRequest) { 2399 case UR_GET_DESCRIPTOR: 2400 goto tr_handle_get_class_descriptor; 2401 case UR_GET_STATUS: 2402 goto tr_handle_get_class_status; 2403 2404 default: 2405 goto tr_stalled; 2406 } 2407 break; 2408 default: 2409 goto tr_stalled; 2410 } 2411 goto tr_valid; 2412 2413tr_handle_get_descriptor: 2414 switch (value >> 8) { 2415 case UDESC_DEVICE: 2416 if (value & 0xff) { 2417 goto tr_stalled; 2418 } 2419 std->len = sizeof(musbotg_devd); 2420 std->ptr = USB_ADD_BYTES(&musbotg_devd, 0); 2421 goto tr_valid; 2422 case UDESC_CONFIG: 2423 if (value & 0xff) { 2424 goto tr_stalled; 2425 } 2426 std->len = sizeof(musbotg_confd); 2427 std->ptr = USB_ADD_BYTES(&musbotg_confd, 0); 2428 goto tr_valid; 2429 case UDESC_STRING: 2430 switch (value & 0xff) { 2431 case 0: /* Language table */ 2432 std->len = sizeof(musbotg_langtab); 2433 std->ptr = USB_ADD_BYTES(&musbotg_langtab, 0); 2434 goto tr_valid; 2435 2436 case 1: /* Vendor */ 2437 std->len = sizeof(musbotg_vendor); 2438 std->ptr = USB_ADD_BYTES(&musbotg_vendor, 0); 2439 goto tr_valid; 2440 2441 case 2: /* Product */ 2442 std->len = sizeof(musbotg_product); 2443 std->ptr = USB_ADD_BYTES(&musbotg_product, 0); 2444 goto tr_valid; 2445 default: 2446 break; 2447 } 2448 break; 2449 default: 2450 goto tr_stalled; 2451 } 2452 goto tr_stalled; 2453 2454tr_handle_get_config: 2455 std->len = 1; 2456 sc->sc_hub_temp.wValue[0] = sc->sc_conf; 2457 goto tr_valid; 2458 2459tr_handle_get_status: 2460 std->len = 2; 2461 USETW(sc->sc_hub_temp.wValue, UDS_SELF_POWERED); 2462 goto tr_valid; 2463 2464tr_handle_set_address: 2465 if (value & 0xFF00) { 2466 goto tr_stalled; 2467 } 2468 sc->sc_rt_addr = value; 2469 goto tr_valid; 2470 2471tr_handle_set_config: 2472 if (value >= 2) { 2473 goto tr_stalled; 2474 } 2475 sc->sc_conf = value; 2476 goto tr_valid; 2477 2478tr_handle_get_interface: 2479 std->len = 1; 2480 sc->sc_hub_temp.wValue[0] = 0; 2481 goto tr_valid; 2482 2483tr_handle_get_tt_state: 2484tr_handle_get_class_status: 2485tr_handle_get_iface_status: 2486tr_handle_get_ep_status: 2487 std->len = 2; 2488 USETW(sc->sc_hub_temp.wValue, 0); 2489 goto tr_valid; 2490 2491tr_handle_set_halt: 2492tr_handle_set_interface: 2493tr_handle_set_wakeup: 2494tr_handle_clear_wakeup: 2495tr_handle_clear_halt: 2496 goto tr_valid; 2497 2498tr_handle_clear_port_feature: 2499 if (index != 1) { 2500 goto tr_stalled; 2501 } 2502 DPRINTFN(8, "UR_CLEAR_PORT_FEATURE on port %d\n", index); 2503 2504 switch (value) { 2505 case UHF_PORT_SUSPEND: 2506 musbotg_wakeup_peer(xfer); 2507 break; 2508 2509 case UHF_PORT_ENABLE: 2510 sc->sc_flags.port_enabled = 0; 2511 break; 2512 2513 case UHF_PORT_TEST: 2514 case UHF_PORT_INDICATOR: 2515 case UHF_C_PORT_ENABLE: 2516 case UHF_C_PORT_OVER_CURRENT: 2517 case UHF_C_PORT_RESET: 2518 /* nops */ 2519 break; 2520 case UHF_PORT_POWER: 2521 sc->sc_flags.port_powered = 0; 2522 musbotg_pull_down(sc); 2523 musbotg_clocks_off(sc); 2524 break; 2525 case UHF_C_PORT_CONNECTION: 2526 sc->sc_flags.change_connect = 0; 2527 break; 2528 case UHF_C_PORT_SUSPEND: 2529 sc->sc_flags.change_suspend = 0; 2530 break; 2531 default: 2532 std->err = USB_ERR_IOERROR; 2533 goto done; 2534 } 2535 goto tr_valid; 2536 2537tr_handle_set_port_feature: 2538 if (index != 1) { 2539 goto tr_stalled; 2540 } 2541 DPRINTFN(8, "UR_SET_PORT_FEATURE\n"); 2542 2543 switch (value) { 2544 case UHF_PORT_ENABLE: 2545 sc->sc_flags.port_enabled = 1; 2546 break; 2547 case UHF_PORT_SUSPEND: 2548 case UHF_PORT_RESET: 2549 case UHF_PORT_TEST: 2550 case UHF_PORT_INDICATOR: 2551 /* nops */ 2552 break; 2553 case UHF_PORT_POWER: 2554 sc->sc_flags.port_powered = 1; 2555 break; 2556 default: 2557 std->err = USB_ERR_IOERROR; 2558 goto done; 2559 } 2560 goto tr_valid; 2561 2562tr_handle_get_port_status: 2563 2564 DPRINTFN(8, "UR_GET_PORT_STATUS\n"); 2565 2566 if (index != 1) { 2567 goto tr_stalled; 2568 } 2569 if (sc->sc_flags.status_vbus) { 2570 musbotg_clocks_on(sc); 2571 musbotg_pull_up(sc); 2572 } else { 2573 musbotg_pull_down(sc); 2574 musbotg_clocks_off(sc); 2575 } 2576 2577 /* Select Device Side Mode */ 2578 value = UPS_PORT_MODE_DEVICE; 2579 2580 if (sc->sc_flags.status_high_speed) { 2581 value |= UPS_HIGH_SPEED; 2582 } 2583 if (sc->sc_flags.port_powered) { 2584 value |= UPS_PORT_POWER; 2585 } 2586 if (sc->sc_flags.port_enabled) { 2587 value |= UPS_PORT_ENABLED; 2588 } 2589 if (sc->sc_flags.status_vbus && 2590 sc->sc_flags.status_bus_reset) { 2591 value |= UPS_CURRENT_CONNECT_STATUS; 2592 } 2593 if (sc->sc_flags.status_suspend) { 2594 value |= UPS_SUSPEND; 2595 } 2596 USETW(sc->sc_hub_temp.ps.wPortStatus, value); 2597 2598 value = 0; 2599 2600 if (sc->sc_flags.change_connect) { 2601 value |= UPS_C_CONNECT_STATUS; 2602 2603 if (sc->sc_flags.status_vbus && 2604 sc->sc_flags.status_bus_reset) { 2605 /* reset EP0 state */ 2606 sc->sc_ep0_busy = 0; 2607 sc->sc_ep0_cmd = 0; 2608 } 2609 } 2610 if (sc->sc_flags.change_suspend) { 2611 value |= UPS_C_SUSPEND; 2612 } 2613 USETW(sc->sc_hub_temp.ps.wPortChange, value); 2614 std->len = sizeof(sc->sc_hub_temp.ps); 2615 goto tr_valid; 2616 2617tr_handle_get_class_descriptor: 2618 if (value & 0xFF) { 2619 goto tr_stalled; 2620 } 2621 std->ptr = USB_ADD_BYTES(&musbotg_hubd, 0); 2622 std->len = sizeof(musbotg_hubd); 2623 goto tr_valid; 2624 2625tr_stalled: 2626 std->err = USB_ERR_STALLED; 2627tr_valid: 2628done: 2629 return; 2630} 2631 2632static void 2633musbotg_root_ctrl_poll(struct musbotg_softc *sc) 2634{ 2635 usb2_sw_transfer(&sc->sc_root_ctrl, 2636 &musbotg_root_ctrl_done); 2637} 2638 2639struct usb2_pipe_methods musbotg_root_ctrl_methods = 2640{ 2641 .open = musbotg_root_ctrl_open, 2642 .close = musbotg_root_ctrl_close, 2643 .enter = musbotg_root_ctrl_enter, 2644 .start = musbotg_root_ctrl_start, 2645 .enter_is_cancelable = 1, 2646 .start_is_cancelable = 0, 2647}; 2648 2649/*------------------------------------------------------------------------* 2650 * musbotg root interrupt support 2651 *------------------------------------------------------------------------*/ 2652static void 2653musbotg_root_intr_open(struct usb2_xfer *xfer) 2654{ 2655 return; 2656} 2657 2658static void 2659musbotg_root_intr_close(struct usb2_xfer *xfer) 2660{ 2661 struct musbotg_softc *sc = MUSBOTG_BUS2SC(xfer->xroot->bus); 2662 2663 if (sc->sc_root_intr.xfer == xfer) { 2664 sc->sc_root_intr.xfer = NULL; 2665 } 2666 musbotg_device_done(xfer, USB_ERR_CANCELLED); 2667} 2668 2669static void 2670musbotg_root_intr_enter(struct usb2_xfer *xfer) 2671{ 2672 return; 2673} 2674 2675static void 2676musbotg_root_intr_start(struct usb2_xfer *xfer) 2677{ 2678 struct musbotg_softc *sc = MUSBOTG_BUS2SC(xfer->xroot->bus); 2679 2680 sc->sc_root_intr.xfer = xfer; 2681} 2682 2683struct usb2_pipe_methods musbotg_root_intr_methods = 2684{ 2685 .open = musbotg_root_intr_open, 2686 .close = musbotg_root_intr_close, 2687 .enter = musbotg_root_intr_enter, 2688 .start = musbotg_root_intr_start, 2689 .enter_is_cancelable = 1, 2690 .start_is_cancelable = 1, 2691}; 2692 2693static void 2694musbotg_xfer_setup(struct usb2_setup_params *parm) 2695{ 2696 const struct usb2_hw_ep_profile *pf; 2697 struct musbotg_softc *sc; 2698 struct usb2_xfer *xfer; 2699 void *last_obj; 2700 uint32_t ntd; 2701 uint32_t n; 2702 uint8_t ep_no; 2703 2704 sc = MUSBOTG_BUS2SC(parm->udev->bus); 2705 xfer = parm->curr_xfer; 2706 2707 /* 2708 * NOTE: This driver does not use any of the parameters that 2709 * are computed from the following values. Just set some 2710 * reasonable dummies: 2711 */ 2712 parm->hc_max_packet_size = 0x400; 2713 parm->hc_max_frame_size = 0x400; 2714 2715 if ((parm->methods == &musbotg_device_isoc_methods) || 2716 (parm->methods == &musbotg_device_intr_methods)) 2717 parm->hc_max_packet_count = 3; 2718 else 2719 parm->hc_max_packet_count = 1; 2720 2721 usb2_transfer_setup_sub(parm); 2722 2723 /* 2724 * compute maximum number of TDs 2725 */ 2726 if (parm->methods == &musbotg_device_ctrl_methods) { 2727 2728 ntd = xfer->nframes + 1 /* STATUS */ + 1 /* SYNC */ ; 2729 2730 } else if (parm->methods == &musbotg_device_bulk_methods) { 2731 2732 ntd = xfer->nframes + 1 /* SYNC */ ; 2733 2734 } else if (parm->methods == &musbotg_device_intr_methods) { 2735 2736 ntd = xfer->nframes + 1 /* SYNC */ ; 2737 2738 } else if (parm->methods == &musbotg_device_isoc_methods) { 2739 2740 ntd = xfer->nframes + 1 /* SYNC */ ; 2741 2742 } else { 2743 2744 ntd = 0; 2745 } 2746 2747 /* 2748 * check if "usb2_transfer_setup_sub" set an error 2749 */ 2750 if (parm->err) { 2751 return; 2752 } 2753 /* 2754 * allocate transfer descriptors 2755 */ 2756 last_obj = NULL; 2757 2758 /* 2759 * get profile stuff 2760 */ 2761 if (ntd) { 2762 2763 ep_no = xfer->endpoint & UE_ADDR; 2764 musbotg_get_hw_ep_profile(parm->udev, &pf, ep_no); 2765 2766 if (pf == NULL) { 2767 /* should not happen */ 2768 parm->err = USB_ERR_INVAL; 2769 return; 2770 } 2771 } else { 2772 ep_no = 0; 2773 pf = NULL; 2774 } 2775 2776 /* align data */ 2777 parm->size[0] += ((-parm->size[0]) & (USB_HOST_ALIGN - 1)); 2778 2779 for (n = 0; n != ntd; n++) { 2780 2781 struct musbotg_td *td; 2782 2783 if (parm->buf) { 2784 2785 td = USB_ADD_BYTES(parm->buf, parm->size[0]); 2786 2787 /* init TD */ 2788 td->max_frame_size = xfer->max_frame_size; 2789 td->ep_no = ep_no; 2790 td->obj_next = last_obj; 2791 2792 last_obj = td; 2793 } 2794 parm->size[0] += sizeof(*td); 2795 } 2796 2797 xfer->td_start[0] = last_obj; 2798} 2799 2800static void 2801musbotg_xfer_unsetup(struct usb2_xfer *xfer) 2802{ 2803 return; 2804} 2805 2806static void 2807musbotg_pipe_init(struct usb2_device *udev, struct usb2_endpoint_descriptor *edesc, 2808 struct usb2_pipe *pipe) 2809{ 2810 struct musbotg_softc *sc = MUSBOTG_BUS2SC(udev->bus); 2811 2812 DPRINTFN(2, "pipe=%p, addr=%d, endpt=%d, mode=%d (%d)\n", 2813 pipe, udev->address, 2814 edesc->bEndpointAddress, udev->flags.usb2_mode, 2815 sc->sc_rt_addr); 2816 2817 if (udev->device_index == sc->sc_rt_addr) { 2818 2819 if (udev->flags.usb2_mode != USB_MODE_HOST) { 2820 /* not supported */ 2821 return; 2822 } 2823 switch (edesc->bEndpointAddress) { 2824 case USB_CONTROL_ENDPOINT: 2825 pipe->methods = &musbotg_root_ctrl_methods; 2826 break; 2827 case UE_DIR_IN | MUSBOTG_INTR_ENDPT: 2828 pipe->methods = &musbotg_root_intr_methods; 2829 break; 2830 default: 2831 /* do nothing */ 2832 break; 2833 } 2834 } else { 2835 2836 if (udev->flags.usb2_mode != USB_MODE_DEVICE) { 2837 /* not supported */ 2838 return; 2839 } 2840 if ((udev->speed != USB_SPEED_FULL) && 2841 (udev->speed != USB_SPEED_HIGH)) { 2842 /* not supported */ 2843 return; 2844 } 2845 switch (edesc->bmAttributes & UE_XFERTYPE) { 2846 case UE_CONTROL: 2847 pipe->methods = &musbotg_device_ctrl_methods; 2848 break; 2849 case UE_INTERRUPT: 2850 pipe->methods = &musbotg_device_intr_methods; 2851 break; 2852 case UE_ISOCHRONOUS: 2853 pipe->methods = &musbotg_device_isoc_methods; 2854 break; 2855 case UE_BULK: 2856 pipe->methods = &musbotg_device_bulk_methods; 2857 break; 2858 default: 2859 /* do nothing */ 2860 break; 2861 } 2862 } 2863} 2864 2865struct usb2_bus_methods musbotg_bus_methods = 2866{ 2867 .pipe_init = &musbotg_pipe_init, 2868 .xfer_setup = &musbotg_xfer_setup, 2869 .xfer_unsetup = &musbotg_xfer_unsetup, 2870 .get_hw_ep_profile = &musbotg_get_hw_ep_profile, 2871 .set_stall = &musbotg_set_stall, 2872 .clear_stall = &musbotg_clear_stall, 2873 .roothub_exec = &musbotg_root_ctrl_task, 2874}; 2875