musb_otg.c revision 190174
1/* $FreeBSD: head/sys/dev/usb/controller/musb_otg.c 190174 2009-03-20 19:04:31Z thompsa $ */ 2/*- 3 * Copyright (c) 2008 Hans Petter Selasky. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27/* 28 * Thanks to Mentor Graphics for providing a reference driver for this 29 * USB chip at their homepage. 30 */ 31 32/* 33 * This file contains the driver for the Mentor Graphics Inventra USB 34 * 2.0 High Speed Dual-Role controller. 35 * 36 * NOTE: The current implementation only supports Device Side Mode! 37 */ 38 39#include <dev/usb/usb.h> 40#include <dev/usb/usb_mfunc.h> 41#include <dev/usb/usb_error.h> 42 43#define USB_DEBUG_VAR musbotgdebug 44 45#include <dev/usb/usb_core.h> 46#include <dev/usb/usb_debug.h> 47#include <dev/usb/usb_busdma.h> 48#include <dev/usb/usb_process.h> 49#include <dev/usb/usb_sw_transfer.h> 50#include <dev/usb/usb_transfer.h> 51#include <dev/usb/usb_device.h> 52#include <dev/usb/usb_hub.h> 53#include <dev/usb/usb_util.h> 54 55#include <dev/usb/usb_controller.h> 56#include <dev/usb/usb_bus.h> 57#include <dev/usb/controller/musb_otg.h> 58 59#define MUSBOTG_INTR_ENDPT 1 60 61#define MUSBOTG_BUS2SC(bus) \ 62 ((struct musbotg_softc *)(((uint8_t *)(bus)) - \ 63 USB_P2U(&(((struct musbotg_softc *)0)->sc_bus)))) 64 65#define MUSBOTG_PC2SC(pc) \ 66 MUSBOTG_BUS2SC((pc)->tag_parent->info->bus) 67 68#if USB_DEBUG 69static int musbotgdebug = 0; 70 71SYSCTL_NODE(_hw_usb2, OID_AUTO, musbotg, CTLFLAG_RW, 0, "USB musbotg"); 72SYSCTL_INT(_hw_usb2_musbotg, OID_AUTO, debug, CTLFLAG_RW, 73 &musbotgdebug, 0, "Debug level"); 74#endif 75 76/* prototypes */ 77 78struct usb2_bus_methods musbotg_bus_methods; 79struct usb2_pipe_methods musbotg_device_bulk_methods; 80struct usb2_pipe_methods musbotg_device_ctrl_methods; 81struct usb2_pipe_methods musbotg_device_intr_methods; 82struct usb2_pipe_methods musbotg_device_isoc_methods; 83struct usb2_pipe_methods musbotg_root_ctrl_methods; 84struct usb2_pipe_methods musbotg_root_intr_methods; 85 86static musbotg_cmd_t musbotg_setup_rx; 87static musbotg_cmd_t musbotg_setup_data_rx; 88static musbotg_cmd_t musbotg_setup_data_tx; 89static musbotg_cmd_t musbotg_setup_status; 90static musbotg_cmd_t musbotg_data_rx; 91static musbotg_cmd_t musbotg_data_tx; 92static void musbotg_device_done(struct usb2_xfer *, usb2_error_t); 93static void musbotg_do_poll(struct usb2_bus *); 94static void musbotg_root_ctrl_poll(struct musbotg_softc *); 95static void musbotg_standard_done(struct usb2_xfer *); 96static void musbotg_interrupt_poll(struct musbotg_softc *); 97 98static usb2_sw_transfer_func_t musbotg_root_intr_done; 99static usb2_sw_transfer_func_t musbotg_root_ctrl_done; 100 101/* 102 * Here is a configuration that the chip supports. 103 */ 104static const struct usb2_hw_ep_profile musbotg_ep_profile[1] = { 105 106 [0] = { 107 .max_in_frame_size = 64,/* fixed */ 108 .max_out_frame_size = 64, /* fixed */ 109 .is_simplex = 1, 110 .support_control = 1, 111 } 112}; 113 114static void 115musbotg_get_hw_ep_profile(struct usb2_device *udev, 116 const struct usb2_hw_ep_profile **ppf, uint8_t ep_addr) 117{ 118 struct musbotg_softc *sc; 119 120 sc = MUSBOTG_BUS2SC(udev->bus); 121 122 if (ep_addr == 0) { 123 /* control endpoint */ 124 *ppf = musbotg_ep_profile; 125 } else if (ep_addr <= sc->sc_ep_max) { 126 /* other endpoints */ 127 *ppf = sc->sc_hw_ep_profile + ep_addr; 128 } else { 129 *ppf = NULL; 130 } 131} 132 133static void 134musbotg_clocks_on(struct musbotg_softc *sc) 135{ 136 if (sc->sc_flags.clocks_off && 137 sc->sc_flags.port_powered) { 138 139 DPRINTFN(4, "\n"); 140 141 if (sc->sc_clocks_on) { 142 (sc->sc_clocks_on) (sc->sc_clocks_arg); 143 } 144 sc->sc_flags.clocks_off = 0; 145 146 /* XXX enable Transceiver */ 147 } 148} 149 150static void 151musbotg_clocks_off(struct musbotg_softc *sc) 152{ 153 if (!sc->sc_flags.clocks_off) { 154 155 DPRINTFN(4, "\n"); 156 157 /* XXX disable Transceiver */ 158 159 if (sc->sc_clocks_off) { 160 (sc->sc_clocks_off) (sc->sc_clocks_arg); 161 } 162 sc->sc_flags.clocks_off = 1; 163 } 164} 165 166static void 167musbotg_pull_common(struct musbotg_softc *sc, uint8_t on) 168{ 169 uint8_t temp; 170 171 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER); 172 if (on) 173 temp |= MUSB2_MASK_SOFTC; 174 else 175 temp &= ~MUSB2_MASK_SOFTC; 176 177 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp); 178} 179 180static void 181musbotg_pull_up(struct musbotg_softc *sc) 182{ 183 /* pullup D+, if possible */ 184 185 if (!sc->sc_flags.d_pulled_up && 186 sc->sc_flags.port_powered) { 187 sc->sc_flags.d_pulled_up = 1; 188 musbotg_pull_common(sc, 1); 189 } 190} 191 192static void 193musbotg_pull_down(struct musbotg_softc *sc) 194{ 195 /* pulldown D+, if possible */ 196 197 if (sc->sc_flags.d_pulled_up) { 198 sc->sc_flags.d_pulled_up = 0; 199 musbotg_pull_common(sc, 0); 200 } 201} 202 203static void 204musbotg_wakeup_peer(struct usb2_xfer *xfer) 205{ 206 struct musbotg_softc *sc = MUSBOTG_BUS2SC(xfer->xroot->bus); 207 uint8_t temp; 208 209 if (!(sc->sc_flags.status_suspend)) { 210 return; 211 } 212 213 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER); 214 temp |= MUSB2_MASK_RESUME; 215 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp); 216 217 /* wait 8 milliseconds */ 218 /* Wait for reset to complete. */ 219 usb2_pause_mtx(&sc->sc_bus.bus_mtx, hz / 125); 220 221 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER); 222 temp &= ~MUSB2_MASK_RESUME; 223 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp); 224} 225 226static void 227musbotg_set_address(struct musbotg_softc *sc, uint8_t addr) 228{ 229 DPRINTFN(4, "addr=%d\n", addr); 230 addr &= 0x7F; 231 MUSB2_WRITE_1(sc, MUSB2_REG_FADDR, addr); 232} 233 234static uint8_t 235musbotg_setup_rx(struct musbotg_td *td) 236{ 237 struct musbotg_softc *sc; 238 struct usb2_device_request req; 239 uint16_t count; 240 uint8_t csr; 241 242 /* get pointer to softc */ 243 sc = MUSBOTG_PC2SC(td->pc); 244 245 /* select endpoint 0 */ 246 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); 247 248 /* read out FIFO status */ 249 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 250 251 DPRINTFN(4, "csr=0x%02x\n", csr); 252 253 /* 254 * NOTE: If DATAEND is set we should not call the 255 * callback, hence the status stage is not complete. 256 */ 257 if (csr & MUSB2_MASK_CSR0L_DATAEND) { 258 /* wait for interrupt */ 259 goto not_complete; 260 } 261 if (csr & MUSB2_MASK_CSR0L_SENTSTALL) { 262 /* clear SENTSTALL */ 263 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0); 264 /* get latest status */ 265 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 266 /* update EP0 state */ 267 sc->sc_ep0_busy = 0; 268 } 269 if (csr & MUSB2_MASK_CSR0L_SETUPEND) { 270 /* clear SETUPEND */ 271 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 272 MUSB2_MASK_CSR0L_SETUPEND_CLR); 273 /* get latest status */ 274 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 275 /* update EP0 state */ 276 sc->sc_ep0_busy = 0; 277 } 278 if (sc->sc_ep0_busy) { 279 /* abort any ongoing transfer */ 280 if (!td->did_stall) { 281 DPRINTFN(4, "stalling\n"); 282 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 283 MUSB2_MASK_CSR0L_SENDSTALL); 284 td->did_stall = 1; 285 } 286 goto not_complete; 287 } 288 if (!(csr & MUSB2_MASK_CSR0L_RXPKTRDY)) { 289 goto not_complete; 290 } 291 /* get the packet byte count */ 292 count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT); 293 294 /* verify data length */ 295 if (count != td->remainder) { 296 DPRINTFN(0, "Invalid SETUP packet " 297 "length, %d bytes\n", count); 298 goto not_complete; 299 } 300 if (count != sizeof(req)) { 301 DPRINTFN(0, "Unsupported SETUP packet " 302 "length, %d bytes\n", count); 303 goto not_complete; 304 } 305 /* receive data */ 306 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 307 MUSB2_REG_EPFIFO(0), (void *)&req, sizeof(req)); 308 309 /* copy data into real buffer */ 310 usb2_copy_in(td->pc, 0, &req, sizeof(req)); 311 312 td->offset = sizeof(req); 313 td->remainder = 0; 314 315 /* set pending command */ 316 sc->sc_ep0_cmd = MUSB2_MASK_CSR0L_RXPKTRDY_CLR; 317 318 /* we need set stall or dataend after this */ 319 sc->sc_ep0_busy = 1; 320 321 /* sneak peek the set address */ 322 if ((req.bmRequestType == UT_WRITE_DEVICE) && 323 (req.bRequest == UR_SET_ADDRESS)) { 324 sc->sc_dv_addr = req.wValue[0] & 0x7F; 325 } else { 326 sc->sc_dv_addr = 0xFF; 327 } 328 return (0); /* complete */ 329 330not_complete: 331 return (1); /* not complete */ 332} 333 334/* Control endpoint only data handling functions (RX/TX/SYNC) */ 335 336static uint8_t 337musbotg_setup_data_rx(struct musbotg_td *td) 338{ 339 struct usb2_page_search buf_res; 340 struct musbotg_softc *sc; 341 uint16_t count; 342 uint8_t csr; 343 uint8_t got_short; 344 345 /* get pointer to softc */ 346 sc = MUSBOTG_PC2SC(td->pc); 347 348 /* select endpoint 0 */ 349 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); 350 351 /* check if a command is pending */ 352 if (sc->sc_ep0_cmd) { 353 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, sc->sc_ep0_cmd); 354 sc->sc_ep0_cmd = 0; 355 } 356 /* read out FIFO status */ 357 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 358 359 DPRINTFN(4, "csr=0x%02x\n", csr); 360 361 got_short = 0; 362 363 if (csr & (MUSB2_MASK_CSR0L_SETUPEND | 364 MUSB2_MASK_CSR0L_SENTSTALL)) { 365 if (td->remainder == 0) { 366 /* 367 * We are actually complete and have 368 * received the next SETUP 369 */ 370 DPRINTFN(4, "faking complete\n"); 371 return (0); /* complete */ 372 } 373 /* 374 * USB Host Aborted the transfer. 375 */ 376 td->error = 1; 377 return (0); /* complete */ 378 } 379 if (!(csr & MUSB2_MASK_CSR0L_RXPKTRDY)) { 380 return (1); /* not complete */ 381 } 382 /* get the packet byte count */ 383 count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT); 384 385 /* verify the packet byte count */ 386 if (count != td->max_frame_size) { 387 if (count < td->max_frame_size) { 388 /* we have a short packet */ 389 td->short_pkt = 1; 390 got_short = 1; 391 } else { 392 /* invalid USB packet */ 393 td->error = 1; 394 return (0); /* we are complete */ 395 } 396 } 397 /* verify the packet byte count */ 398 if (count > td->remainder) { 399 /* invalid USB packet */ 400 td->error = 1; 401 return (0); /* we are complete */ 402 } 403 while (count > 0) { 404 uint32_t temp; 405 406 usb2_get_page(td->pc, td->offset, &buf_res); 407 408 /* get correct length */ 409 if (buf_res.length > count) { 410 buf_res.length = count; 411 } 412 /* check for unaligned memory address */ 413 if (USB_P2U(buf_res.buffer) & 3) { 414 415 temp = count & ~3; 416 417 if (temp) { 418 /* receive data 4 bytes at a time */ 419 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 420 MUSB2_REG_EPFIFO(0), sc->sc_bounce_buf, 421 temp / 4); 422 } 423 temp = count & 3; 424 if (temp) { 425 /* receive data 1 byte at a time */ 426 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 427 MUSB2_REG_EPFIFO(0), 428 (void *)(&sc->sc_bounce_buf[count / 4]), temp); 429 } 430 usb2_copy_in(td->pc, td->offset, 431 sc->sc_bounce_buf, count); 432 433 /* update offset and remainder */ 434 td->offset += count; 435 td->remainder -= count; 436 break; 437 } 438 /* check if we can optimise */ 439 if (buf_res.length >= 4) { 440 441 /* receive data 4 bytes at a time */ 442 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 443 MUSB2_REG_EPFIFO(0), buf_res.buffer, 444 buf_res.length / 4); 445 446 temp = buf_res.length & ~3; 447 448 /* update counters */ 449 count -= temp; 450 td->offset += temp; 451 td->remainder -= temp; 452 continue; 453 } 454 /* receive data */ 455 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 456 MUSB2_REG_EPFIFO(0), buf_res.buffer, buf_res.length); 457 458 /* update counters */ 459 count -= buf_res.length; 460 td->offset += buf_res.length; 461 td->remainder -= buf_res.length; 462 } 463 464 /* check if we are complete */ 465 if ((td->remainder == 0) || got_short) { 466 if (td->short_pkt) { 467 /* we are complete */ 468 sc->sc_ep0_cmd = MUSB2_MASK_CSR0L_RXPKTRDY_CLR; 469 return (0); 470 } 471 /* else need to receive a zero length packet */ 472 } 473 /* write command - need more data */ 474 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 475 MUSB2_MASK_CSR0L_RXPKTRDY_CLR); 476 return (1); /* not complete */ 477} 478 479static uint8_t 480musbotg_setup_data_tx(struct musbotg_td *td) 481{ 482 struct usb2_page_search buf_res; 483 struct musbotg_softc *sc; 484 uint16_t count; 485 uint8_t csr; 486 487 /* get pointer to softc */ 488 sc = MUSBOTG_PC2SC(td->pc); 489 490 /* select endpoint 0 */ 491 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); 492 493 /* check if a command is pending */ 494 if (sc->sc_ep0_cmd) { 495 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, sc->sc_ep0_cmd); 496 sc->sc_ep0_cmd = 0; 497 } 498 /* read out FIFO status */ 499 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 500 501 DPRINTFN(4, "csr=0x%02x\n", csr); 502 503 if (csr & (MUSB2_MASK_CSR0L_SETUPEND | 504 MUSB2_MASK_CSR0L_SENTSTALL)) { 505 /* 506 * The current transfer was aborted 507 * by the USB Host 508 */ 509 td->error = 1; 510 return (0); /* complete */ 511 } 512 if (csr & MUSB2_MASK_CSR0L_TXPKTRDY) { 513 return (1); /* not complete */ 514 } 515 count = td->max_frame_size; 516 if (td->remainder < count) { 517 /* we have a short packet */ 518 td->short_pkt = 1; 519 count = td->remainder; 520 } 521 while (count > 0) { 522 uint32_t temp; 523 524 usb2_get_page(td->pc, td->offset, &buf_res); 525 526 /* get correct length */ 527 if (buf_res.length > count) { 528 buf_res.length = count; 529 } 530 /* check for unaligned memory address */ 531 if (USB_P2U(buf_res.buffer) & 3) { 532 533 usb2_copy_out(td->pc, td->offset, 534 sc->sc_bounce_buf, count); 535 536 temp = count & ~3; 537 538 if (temp) { 539 /* transmit data 4 bytes at a time */ 540 bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 541 MUSB2_REG_EPFIFO(0), sc->sc_bounce_buf, 542 temp / 4); 543 } 544 temp = count & 3; 545 if (temp) { 546 /* receive data 1 byte at a time */ 547 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 548 MUSB2_REG_EPFIFO(0), 549 ((void *)&sc->sc_bounce_buf[count / 4]), temp); 550 } 551 /* update offset and remainder */ 552 td->offset += count; 553 td->remainder -= count; 554 break; 555 } 556 /* check if we can optimise */ 557 if (buf_res.length >= 4) { 558 559 /* transmit data 4 bytes at a time */ 560 bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 561 MUSB2_REG_EPFIFO(0), buf_res.buffer, 562 buf_res.length / 4); 563 564 temp = buf_res.length & ~3; 565 566 /* update counters */ 567 count -= temp; 568 td->offset += temp; 569 td->remainder -= temp; 570 continue; 571 } 572 /* transmit data */ 573 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 574 MUSB2_REG_EPFIFO(0), buf_res.buffer, buf_res.length); 575 576 /* update counters */ 577 count -= buf_res.length; 578 td->offset += buf_res.length; 579 td->remainder -= buf_res.length; 580 } 581 582 /* check remainder */ 583 if (td->remainder == 0) { 584 if (td->short_pkt) { 585 sc->sc_ep0_cmd = MUSB2_MASK_CSR0L_TXPKTRDY; 586 return (0); /* complete */ 587 } 588 /* else we need to transmit a short packet */ 589 } 590 /* write command */ 591 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 592 MUSB2_MASK_CSR0L_TXPKTRDY); 593 594 return (1); /* not complete */ 595} 596 597static uint8_t 598musbotg_setup_status(struct musbotg_td *td) 599{ 600 struct musbotg_softc *sc; 601 uint8_t csr; 602 603 /* get pointer to softc */ 604 sc = MUSBOTG_PC2SC(td->pc); 605 606 /* select endpoint 0 */ 607 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); 608 609 if (sc->sc_ep0_busy) { 610 sc->sc_ep0_busy = 0; 611 sc->sc_ep0_cmd |= MUSB2_MASK_CSR0L_DATAEND; 612 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, sc->sc_ep0_cmd); 613 sc->sc_ep0_cmd = 0; 614 } 615 /* read out FIFO status */ 616 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 617 618 DPRINTFN(4, "csr=0x%02x\n", csr); 619 620 if (csr & MUSB2_MASK_CSR0L_DATAEND) { 621 /* wait for interrupt */ 622 return (1); /* not complete */ 623 } 624 if (sc->sc_dv_addr != 0xFF) { 625 /* write function address */ 626 musbotg_set_address(sc, sc->sc_dv_addr); 627 } 628 return (0); /* complete */ 629} 630 631static uint8_t 632musbotg_data_rx(struct musbotg_td *td) 633{ 634 struct usb2_page_search buf_res; 635 struct musbotg_softc *sc; 636 uint16_t count; 637 uint8_t csr; 638 uint8_t to; 639 uint8_t got_short; 640 641 to = 8; /* don't loop forever! */ 642 got_short = 0; 643 644 /* get pointer to softc */ 645 sc = MUSBOTG_PC2SC(td->pc); 646 647 /* select endpoint */ 648 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, td->ep_no); 649 650repeat: 651 /* read out FIFO status */ 652 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL); 653 654 DPRINTFN(4, "csr=0x%02x\n", csr); 655 656 /* clear overrun */ 657 if (csr & MUSB2_MASK_CSRL_RXOVERRUN) { 658 /* make sure we don't clear "RXPKTRDY" */ 659 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 660 MUSB2_MASK_CSRL_RXPKTRDY); 661 } 662 /* check status */ 663 if (!(csr & MUSB2_MASK_CSRL_RXPKTRDY)) { 664 return (1); /* not complete */ 665 } 666 /* get the packet byte count */ 667 count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT); 668 669 DPRINTFN(4, "count=0x%04x\n", count); 670 671 /* 672 * Check for short or invalid packet: 673 */ 674 if (count != td->max_frame_size) { 675 if (count < td->max_frame_size) { 676 /* we have a short packet */ 677 td->short_pkt = 1; 678 got_short = 1; 679 } else { 680 /* invalid USB packet */ 681 td->error = 1; 682 return (0); /* we are complete */ 683 } 684 } 685 /* verify the packet byte count */ 686 if (count > td->remainder) { 687 /* invalid USB packet */ 688 td->error = 1; 689 return (0); /* we are complete */ 690 } 691 while (count > 0) { 692 uint32_t temp; 693 694 usb2_get_page(td->pc, td->offset, &buf_res); 695 696 /* get correct length */ 697 if (buf_res.length > count) { 698 buf_res.length = count; 699 } 700 /* check for unaligned memory address */ 701 if (USB_P2U(buf_res.buffer) & 3) { 702 703 temp = count & ~3; 704 705 if (temp) { 706 /* receive data 4 bytes at a time */ 707 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 708 MUSB2_REG_EPFIFO(td->ep_no), sc->sc_bounce_buf, 709 temp / 4); 710 } 711 temp = count & 3; 712 if (temp) { 713 /* receive data 1 byte at a time */ 714 bus_space_read_multi_1(sc->sc_io_tag, 715 sc->sc_io_hdl, MUSB2_REG_EPFIFO(td->ep_no), 716 ((void *)&sc->sc_bounce_buf[count / 4]), temp); 717 } 718 usb2_copy_in(td->pc, td->offset, 719 sc->sc_bounce_buf, count); 720 721 /* update offset and remainder */ 722 td->offset += count; 723 td->remainder -= count; 724 break; 725 } 726 /* check if we can optimise */ 727 if (buf_res.length >= 4) { 728 729 /* receive data 4 bytes at a time */ 730 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 731 MUSB2_REG_EPFIFO(td->ep_no), buf_res.buffer, 732 buf_res.length / 4); 733 734 temp = buf_res.length & ~3; 735 736 /* update counters */ 737 count -= temp; 738 td->offset += temp; 739 td->remainder -= temp; 740 continue; 741 } 742 /* receive data */ 743 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 744 MUSB2_REG_EPFIFO(td->ep_no), buf_res.buffer, 745 buf_res.length); 746 747 /* update counters */ 748 count -= buf_res.length; 749 td->offset += buf_res.length; 750 td->remainder -= buf_res.length; 751 } 752 753 /* clear status bits */ 754 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 0); 755 756 /* check if we are complete */ 757 if ((td->remainder == 0) || got_short) { 758 if (td->short_pkt) { 759 /* we are complete */ 760 return (0); 761 } 762 /* else need to receive a zero length packet */ 763 } 764 if (--to) { 765 goto repeat; 766 } 767 return (1); /* not complete */ 768} 769 770static uint8_t 771musbotg_data_tx(struct musbotg_td *td) 772{ 773 struct usb2_page_search buf_res; 774 struct musbotg_softc *sc; 775 uint16_t count; 776 uint8_t csr; 777 uint8_t to; 778 779 to = 8; /* don't loop forever! */ 780 781 /* get pointer to softc */ 782 sc = MUSBOTG_PC2SC(td->pc); 783 784 /* select endpoint */ 785 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, td->ep_no); 786 787repeat: 788 789 /* read out FIFO status */ 790 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 791 792 DPRINTFN(4, "csr=0x%02x\n", csr); 793 794 if (csr & (MUSB2_MASK_CSRL_TXINCOMP | 795 MUSB2_MASK_CSRL_TXUNDERRUN)) { 796 /* clear status bits */ 797 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0); 798 } 799 if (csr & MUSB2_MASK_CSRL_TXPKTRDY) { 800 return (1); /* not complete */ 801 } 802 /* check for short packet */ 803 count = td->max_frame_size; 804 if (td->remainder < count) { 805 /* we have a short packet */ 806 td->short_pkt = 1; 807 count = td->remainder; 808 } 809 while (count > 0) { 810 uint32_t temp; 811 812 usb2_get_page(td->pc, td->offset, &buf_res); 813 814 /* get correct length */ 815 if (buf_res.length > count) { 816 buf_res.length = count; 817 } 818 /* check for unaligned memory address */ 819 if (USB_P2U(buf_res.buffer) & 3) { 820 821 usb2_copy_out(td->pc, td->offset, 822 sc->sc_bounce_buf, count); 823 824 temp = count & ~3; 825 826 if (temp) { 827 /* transmit data 4 bytes at a time */ 828 bus_space_write_multi_4(sc->sc_io_tag, 829 sc->sc_io_hdl, MUSB2_REG_EPFIFO(td->ep_no), 830 sc->sc_bounce_buf, temp / 4); 831 } 832 temp = count & 3; 833 if (temp) { 834 /* receive data 1 byte at a time */ 835 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 836 MUSB2_REG_EPFIFO(td->ep_no), 837 ((void *)&sc->sc_bounce_buf[count / 4]), temp); 838 } 839 /* update offset and remainder */ 840 td->offset += count; 841 td->remainder -= count; 842 break; 843 } 844 /* check if we can optimise */ 845 if (buf_res.length >= 4) { 846 847 /* transmit data 4 bytes at a time */ 848 bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 849 MUSB2_REG_EPFIFO(td->ep_no), buf_res.buffer, 850 buf_res.length / 4); 851 852 temp = buf_res.length & ~3; 853 854 /* update counters */ 855 count -= temp; 856 td->offset += temp; 857 td->remainder -= temp; 858 continue; 859 } 860 /* transmit data */ 861 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 862 MUSB2_REG_EPFIFO(td->ep_no), buf_res.buffer, 863 buf_res.length); 864 865 /* update counters */ 866 count -= buf_res.length; 867 td->offset += buf_res.length; 868 td->remainder -= buf_res.length; 869 } 870 871 /* write command */ 872 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 873 MUSB2_MASK_CSRL_TXPKTRDY); 874 875 /* check remainder */ 876 if (td->remainder == 0) { 877 if (td->short_pkt) { 878 return (0); /* complete */ 879 } 880 /* else we need to transmit a short packet */ 881 } 882 if (--to) { 883 goto repeat; 884 } 885 return (1); /* not complete */ 886} 887 888static uint8_t 889musbotg_xfer_do_fifo(struct usb2_xfer *xfer) 890{ 891 struct musbotg_softc *sc; 892 struct musbotg_td *td; 893 894 DPRINTFN(8, "\n"); 895 896 td = xfer->td_transfer_cache; 897 while (1) { 898 if ((td->func) (td)) { 899 /* operation in progress */ 900 break; 901 } 902 if (((void *)td) == xfer->td_transfer_last) { 903 goto done; 904 } 905 if (td->error) { 906 goto done; 907 } else if (td->remainder > 0) { 908 /* 909 * We had a short transfer. If there is no alternate 910 * next, stop processing ! 911 */ 912 if (!td->alt_next) { 913 goto done; 914 } 915 } 916 /* 917 * Fetch the next transfer descriptor and transfer 918 * some flags to the next transfer descriptor 919 */ 920 td = td->obj_next; 921 xfer->td_transfer_cache = td; 922 } 923 return (1); /* not complete */ 924 925done: 926 sc = MUSBOTG_BUS2SC(xfer->xroot->bus); 927 928 /* compute all actual lengths */ 929 930 musbotg_standard_done(xfer); 931 932 return (0); /* complete */ 933} 934 935static void 936musbotg_interrupt_poll(struct musbotg_softc *sc) 937{ 938 struct usb2_xfer *xfer; 939 940repeat: 941 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 942 if (!musbotg_xfer_do_fifo(xfer)) { 943 /* queue has been modified */ 944 goto repeat; 945 } 946 } 947} 948 949void 950musbotg_vbus_interrupt(struct musbotg_softc *sc, uint8_t is_on) 951{ 952 DPRINTFN(4, "vbus = %u\n", is_on); 953 954 USB_BUS_LOCK(&sc->sc_bus); 955 if (is_on) { 956 if (!sc->sc_flags.status_vbus) { 957 sc->sc_flags.status_vbus = 1; 958 959 /* complete root HUB interrupt endpoint */ 960 961 usb2_sw_transfer(&sc->sc_root_intr, 962 &musbotg_root_intr_done); 963 } 964 } else { 965 if (sc->sc_flags.status_vbus) { 966 sc->sc_flags.status_vbus = 0; 967 sc->sc_flags.status_bus_reset = 0; 968 sc->sc_flags.status_suspend = 0; 969 sc->sc_flags.change_suspend = 0; 970 sc->sc_flags.change_connect = 1; 971 972 /* complete root HUB interrupt endpoint */ 973 974 usb2_sw_transfer(&sc->sc_root_intr, 975 &musbotg_root_intr_done); 976 } 977 } 978 979 USB_BUS_UNLOCK(&sc->sc_bus); 980} 981 982void 983musbotg_interrupt(struct musbotg_softc *sc) 984{ 985 uint16_t rx_status; 986 uint16_t tx_status; 987 uint8_t usb_status; 988 uint8_t temp; 989 uint8_t to = 2; 990 991 USB_BUS_LOCK(&sc->sc_bus); 992 993repeat: 994 995 /* read all interrupt registers */ 996 usb_status = MUSB2_READ_1(sc, MUSB2_REG_INTUSB); 997 998 /* read all FIFO interrupts */ 999 rx_status = MUSB2_READ_2(sc, MUSB2_REG_INTRX); 1000 tx_status = MUSB2_READ_2(sc, MUSB2_REG_INTTX); 1001 1002 /* check for any bus state change interrupts */ 1003 1004 if (usb_status & (MUSB2_MASK_IRESET | 1005 MUSB2_MASK_IRESUME | MUSB2_MASK_ISUSP)) { 1006 1007 DPRINTFN(4, "real bus interrupt 0x%08x\n", usb_status); 1008 1009 if (usb_status & MUSB2_MASK_IRESET) { 1010 1011 /* set correct state */ 1012 sc->sc_flags.status_bus_reset = 1; 1013 sc->sc_flags.status_suspend = 0; 1014 sc->sc_flags.change_suspend = 0; 1015 sc->sc_flags.change_connect = 1; 1016 1017 /* determine line speed */ 1018 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER); 1019 if (temp & MUSB2_MASK_HSMODE) 1020 sc->sc_flags.status_high_speed = 1; 1021 else 1022 sc->sc_flags.status_high_speed = 0; 1023 1024 /* 1025 * After reset all interrupts are on and we need to 1026 * turn them off! 1027 */ 1028 temp = MUSB2_MASK_IRESET; 1029 /* disable resume interrupt */ 1030 temp &= ~MUSB2_MASK_IRESUME; 1031 /* enable suspend interrupt */ 1032 temp |= MUSB2_MASK_ISUSP; 1033 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, temp); 1034 /* disable TX and RX interrupts */ 1035 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, 0); 1036 MUSB2_WRITE_2(sc, MUSB2_REG_INTRXE, 0); 1037 } 1038 /* 1039 * If RXRSM and RXSUSP is set at the same time we interpret 1040 * that like RESUME. Resume is set when there is at least 3 1041 * milliseconds of inactivity on the USB BUS. 1042 */ 1043 if (usb_status & MUSB2_MASK_IRESUME) { 1044 if (sc->sc_flags.status_suspend) { 1045 sc->sc_flags.status_suspend = 0; 1046 sc->sc_flags.change_suspend = 1; 1047 1048 temp = MUSB2_READ_1(sc, MUSB2_REG_INTUSBE); 1049 /* disable resume interrupt */ 1050 temp &= ~MUSB2_MASK_IRESUME; 1051 /* enable suspend interrupt */ 1052 temp |= MUSB2_MASK_ISUSP; 1053 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, temp); 1054 } 1055 } else if (usb_status & MUSB2_MASK_ISUSP) { 1056 if (!sc->sc_flags.status_suspend) { 1057 sc->sc_flags.status_suspend = 1; 1058 sc->sc_flags.change_suspend = 1; 1059 1060 temp = MUSB2_READ_1(sc, MUSB2_REG_INTUSBE); 1061 /* disable suspend interrupt */ 1062 temp &= ~MUSB2_MASK_ISUSP; 1063 /* enable resume interrupt */ 1064 temp |= MUSB2_MASK_IRESUME; 1065 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, temp); 1066 } 1067 } 1068 /* complete root HUB interrupt endpoint */ 1069 1070 usb2_sw_transfer(&sc->sc_root_intr, 1071 &musbotg_root_intr_done); 1072 } 1073 /* check for any endpoint interrupts */ 1074 1075 if (rx_status || tx_status) { 1076 DPRINTFN(4, "real endpoint interrupt " 1077 "rx=0x%04x, tx=0x%04x\n", rx_status, tx_status); 1078 } 1079 /* poll one time regardless of FIFO status */ 1080 1081 musbotg_interrupt_poll(sc); 1082 1083 if (--to) 1084 goto repeat; 1085 1086 USB_BUS_UNLOCK(&sc->sc_bus); 1087} 1088 1089static void 1090musbotg_setup_standard_chain_sub(struct musbotg_std_temp *temp) 1091{ 1092 struct musbotg_td *td; 1093 1094 /* get current Transfer Descriptor */ 1095 td = temp->td_next; 1096 temp->td = td; 1097 1098 /* prepare for next TD */ 1099 temp->td_next = td->obj_next; 1100 1101 /* fill out the Transfer Descriptor */ 1102 td->func = temp->func; 1103 td->pc = temp->pc; 1104 td->offset = temp->offset; 1105 td->remainder = temp->len; 1106 td->error = 0; 1107 td->did_stall = 0; 1108 td->short_pkt = temp->short_pkt; 1109 td->alt_next = temp->setup_alt_next; 1110} 1111 1112static void 1113musbotg_setup_standard_chain(struct usb2_xfer *xfer) 1114{ 1115 struct musbotg_std_temp temp; 1116 struct musbotg_softc *sc; 1117 struct musbotg_td *td; 1118 uint32_t x; 1119 uint8_t ep_no; 1120 1121 DPRINTFN(8, "addr=%d endpt=%d sumlen=%d speed=%d\n", 1122 xfer->address, UE_GET_ADDR(xfer->endpoint), 1123 xfer->sumlen, usb2_get_speed(xfer->xroot->udev)); 1124 1125 temp.max_frame_size = xfer->max_frame_size; 1126 1127 td = xfer->td_start[0]; 1128 xfer->td_transfer_first = td; 1129 xfer->td_transfer_cache = td; 1130 1131 /* setup temp */ 1132 1133 temp.td = NULL; 1134 temp.td_next = xfer->td_start[0]; 1135 temp.setup_alt_next = xfer->flags_int.short_frames_ok; 1136 temp.offset = 0; 1137 1138 sc = MUSBOTG_BUS2SC(xfer->xroot->bus); 1139 ep_no = (xfer->endpoint & UE_ADDR); 1140 1141 /* check if we should prepend a setup message */ 1142 1143 if (xfer->flags_int.control_xfr) { 1144 if (xfer->flags_int.control_hdr) { 1145 1146 temp.func = &musbotg_setup_rx; 1147 temp.len = xfer->frlengths[0]; 1148 temp.pc = xfer->frbuffers + 0; 1149 temp.short_pkt = temp.len ? 1 : 0; 1150 1151 musbotg_setup_standard_chain_sub(&temp); 1152 } 1153 x = 1; 1154 } else { 1155 x = 0; 1156 } 1157 1158 if (x != xfer->nframes) { 1159 if (xfer->endpoint & UE_DIR_IN) { 1160 if (xfer->flags_int.control_xfr) 1161 temp.func = &musbotg_setup_data_tx; 1162 else 1163 temp.func = &musbotg_data_tx; 1164 } else { 1165 if (xfer->flags_int.control_xfr) 1166 temp.func = &musbotg_setup_data_rx; 1167 else 1168 temp.func = &musbotg_data_rx; 1169 } 1170 1171 /* setup "pc" pointer */ 1172 temp.pc = xfer->frbuffers + x; 1173 } 1174 while (x != xfer->nframes) { 1175 1176 /* DATA0 / DATA1 message */ 1177 1178 temp.len = xfer->frlengths[x]; 1179 1180 x++; 1181 1182 if (x == xfer->nframes) { 1183 temp.setup_alt_next = 0; 1184 } 1185 if (temp.len == 0) { 1186 1187 /* make sure that we send an USB packet */ 1188 1189 temp.short_pkt = 0; 1190 1191 } else { 1192 1193 /* regular data transfer */ 1194 1195 temp.short_pkt = (xfer->flags.force_short_xfer) ? 0 : 1; 1196 } 1197 1198 musbotg_setup_standard_chain_sub(&temp); 1199 1200 if (xfer->flags_int.isochronous_xfr) { 1201 temp.offset += temp.len; 1202 } else { 1203 /* get next Page Cache pointer */ 1204 temp.pc = xfer->frbuffers + x; 1205 } 1206 } 1207 1208 /* always setup a valid "pc" pointer for status and sync */ 1209 temp.pc = xfer->frbuffers + 0; 1210 1211 /* check if we should append a status stage */ 1212 1213 if (xfer->flags_int.control_xfr && 1214 !xfer->flags_int.control_act) { 1215 1216 /* 1217 * Send a DATA1 message and invert the current 1218 * endpoint direction. 1219 */ 1220 temp.func = &musbotg_setup_status; 1221 temp.len = 0; 1222 temp.short_pkt = 0; 1223 1224 musbotg_setup_standard_chain_sub(&temp); 1225 } 1226 /* must have at least one frame! */ 1227 td = temp.td; 1228 xfer->td_transfer_last = td; 1229} 1230 1231static void 1232musbotg_timeout(void *arg) 1233{ 1234 struct usb2_xfer *xfer = arg; 1235 1236 DPRINTFN(1, "xfer=%p\n", xfer); 1237 1238 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 1239 1240 /* transfer is transferred */ 1241 musbotg_device_done(xfer, USB_ERR_TIMEOUT); 1242} 1243 1244static void 1245musbotg_ep_int_set(struct usb2_xfer *xfer, uint8_t on) 1246{ 1247 struct musbotg_softc *sc = MUSBOTG_BUS2SC(xfer->xroot->bus); 1248 uint16_t temp; 1249 uint8_t ep_no = xfer->endpoint & UE_ADDR; 1250 1251 /* 1252 * Only enable the endpoint interrupt when we are 1253 * actually waiting for data, hence we are dealing 1254 * with level triggered interrupts ! 1255 */ 1256 if (ep_no == 0) { 1257 temp = MUSB2_READ_2(sc, MUSB2_REG_INTTXE); 1258 if (on) 1259 temp |= MUSB2_MASK_EPINT(0); 1260 else 1261 temp &= ~MUSB2_MASK_EPINT(0); 1262 1263 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, temp); 1264 } else { 1265 if (USB_GET_DATA_ISREAD(xfer)) { 1266 temp = MUSB2_READ_2(sc, MUSB2_REG_INTRXE); 1267 if (on) 1268 temp |= MUSB2_MASK_EPINT(ep_no); 1269 else 1270 temp &= ~MUSB2_MASK_EPINT(ep_no); 1271 MUSB2_WRITE_2(sc, MUSB2_REG_INTRXE, temp); 1272 1273 } else { 1274 temp = MUSB2_READ_2(sc, MUSB2_REG_INTTXE); 1275 if (on) 1276 temp |= MUSB2_MASK_EPINT(ep_no); 1277 else 1278 temp &= ~MUSB2_MASK_EPINT(ep_no); 1279 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, temp); 1280 } 1281 } 1282} 1283 1284static void 1285musbotg_start_standard_chain(struct usb2_xfer *xfer) 1286{ 1287 DPRINTFN(8, "\n"); 1288 1289 /* poll one time */ 1290 if (musbotg_xfer_do_fifo(xfer)) { 1291 1292 musbotg_ep_int_set(xfer, 1); 1293 1294 DPRINTFN(14, "enabled interrupts on endpoint\n"); 1295 1296 /* put transfer on interrupt queue */ 1297 usb2_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 1298 1299 /* start timeout, if any */ 1300 if (xfer->timeout != 0) { 1301 usb2_transfer_timeout_ms(xfer, 1302 &musbotg_timeout, xfer->timeout); 1303 } 1304 } 1305} 1306 1307static void 1308musbotg_root_intr_done(struct usb2_xfer *xfer, 1309 struct usb2_sw_transfer *std) 1310{ 1311 struct musbotg_softc *sc = MUSBOTG_BUS2SC(xfer->xroot->bus); 1312 1313 DPRINTFN(8, "\n"); 1314 1315 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1316 1317 if (std->state != USB_SW_TR_PRE_DATA) { 1318 if (std->state == USB_SW_TR_PRE_CALLBACK) { 1319 /* transfer transferred */ 1320 musbotg_device_done(xfer, std->err); 1321 } 1322 goto done; 1323 } 1324 /* setup buffer */ 1325 std->ptr = sc->sc_hub_idata; 1326 std->len = sizeof(sc->sc_hub_idata); 1327 1328 /* set port bit */ 1329 sc->sc_hub_idata[0] = 0x02; /* we only have one port */ 1330 1331done: 1332 return; 1333} 1334 1335static usb2_error_t 1336musbotg_standard_done_sub(struct usb2_xfer *xfer) 1337{ 1338 struct musbotg_td *td; 1339 uint32_t len; 1340 uint8_t error; 1341 1342 DPRINTFN(8, "\n"); 1343 1344 td = xfer->td_transfer_cache; 1345 1346 do { 1347 len = td->remainder; 1348 1349 if (xfer->aframes != xfer->nframes) { 1350 /* 1351 * Verify the length and subtract 1352 * the remainder from "frlengths[]": 1353 */ 1354 if (len > xfer->frlengths[xfer->aframes]) { 1355 td->error = 1; 1356 } else { 1357 xfer->frlengths[xfer->aframes] -= len; 1358 } 1359 } 1360 /* Check for transfer error */ 1361 if (td->error) { 1362 /* the transfer is finished */ 1363 error = 1; 1364 td = NULL; 1365 break; 1366 } 1367 /* Check for short transfer */ 1368 if (len > 0) { 1369 if (xfer->flags_int.short_frames_ok) { 1370 /* follow alt next */ 1371 if (td->alt_next) { 1372 td = td->obj_next; 1373 } else { 1374 td = NULL; 1375 } 1376 } else { 1377 /* the transfer is finished */ 1378 td = NULL; 1379 } 1380 error = 0; 1381 break; 1382 } 1383 td = td->obj_next; 1384 1385 /* this USB frame is complete */ 1386 error = 0; 1387 break; 1388 1389 } while (0); 1390 1391 /* update transfer cache */ 1392 1393 xfer->td_transfer_cache = td; 1394 1395 return (error ? 1396 USB_ERR_STALLED : USB_ERR_NORMAL_COMPLETION); 1397} 1398 1399static void 1400musbotg_standard_done(struct usb2_xfer *xfer) 1401{ 1402 usb2_error_t err = 0; 1403 1404 DPRINTFN(12, "xfer=%p pipe=%p transfer done\n", 1405 xfer, xfer->pipe); 1406 1407 /* reset scanner */ 1408 1409 xfer->td_transfer_cache = xfer->td_transfer_first; 1410 1411 if (xfer->flags_int.control_xfr) { 1412 1413 if (xfer->flags_int.control_hdr) { 1414 1415 err = musbotg_standard_done_sub(xfer); 1416 } 1417 xfer->aframes = 1; 1418 1419 if (xfer->td_transfer_cache == NULL) { 1420 goto done; 1421 } 1422 } 1423 while (xfer->aframes != xfer->nframes) { 1424 1425 err = musbotg_standard_done_sub(xfer); 1426 xfer->aframes++; 1427 1428 if (xfer->td_transfer_cache == NULL) { 1429 goto done; 1430 } 1431 } 1432 1433 if (xfer->flags_int.control_xfr && 1434 !xfer->flags_int.control_act) { 1435 1436 err = musbotg_standard_done_sub(xfer); 1437 } 1438done: 1439 musbotg_device_done(xfer, err); 1440} 1441 1442/*------------------------------------------------------------------------* 1443 * musbotg_device_done 1444 * 1445 * NOTE: this function can be called more than one time on the 1446 * same USB transfer! 1447 *------------------------------------------------------------------------*/ 1448static void 1449musbotg_device_done(struct usb2_xfer *xfer, usb2_error_t error) 1450{ 1451 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 1452 1453 DPRINTFN(2, "xfer=%p, pipe=%p, error=%d\n", 1454 xfer, xfer->pipe, error); 1455 1456 if (xfer->flags_int.usb2_mode == USB_MODE_DEVICE) { 1457 1458 musbotg_ep_int_set(xfer, 0); 1459 1460 DPRINTFN(14, "disabled interrupts on endpoint\n"); 1461 } 1462 /* dequeue transfer and start next transfer */ 1463 usb2_transfer_done(xfer, error); 1464} 1465 1466static void 1467musbotg_set_stall(struct usb2_device *udev, struct usb2_xfer *xfer, 1468 struct usb2_pipe *pipe) 1469{ 1470 struct musbotg_softc *sc; 1471 uint8_t ep_no; 1472 1473 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 1474 1475 DPRINTFN(4, "pipe=%p\n", pipe); 1476 1477 if (xfer) { 1478 /* cancel any ongoing transfers */ 1479 musbotg_device_done(xfer, USB_ERR_STALLED); 1480 } 1481 /* set FORCESTALL */ 1482 sc = MUSBOTG_BUS2SC(udev->bus); 1483 1484 ep_no = (pipe->edesc->bEndpointAddress & UE_ADDR); 1485 1486 /* select endpoint */ 1487 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, ep_no); 1488 1489 if (pipe->edesc->bEndpointAddress & UE_DIR_IN) { 1490 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 1491 MUSB2_MASK_CSRL_TXSENDSTALL); 1492 } else { 1493 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 1494 MUSB2_MASK_CSRL_RXSENDSTALL); 1495 } 1496} 1497 1498static void 1499musbotg_clear_stall_sub(struct musbotg_softc *sc, uint16_t wMaxPacket, 1500 uint8_t ep_no, uint8_t ep_type, uint8_t ep_dir) 1501{ 1502 uint16_t mps; 1503 uint16_t temp; 1504 uint8_t csr; 1505 1506 if (ep_type == UE_CONTROL) { 1507 /* clearing stall is not needed */ 1508 return; 1509 } 1510 /* select endpoint */ 1511 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, ep_no); 1512 1513 /* compute max frame size */ 1514 mps = wMaxPacket & 0x7FF; 1515 switch ((wMaxPacket >> 11) & 3) { 1516 case 1: 1517 mps *= 2; 1518 break; 1519 case 2: 1520 mps *= 3; 1521 break; 1522 default: 1523 break; 1524 } 1525 1526 if (ep_dir == UE_DIR_IN) { 1527 1528 temp = 0; 1529 1530 /* Configure endpoint */ 1531 switch (ep_type) { 1532 case UE_INTERRUPT: 1533 MUSB2_WRITE_1(sc, MUSB2_REG_TXMAXP, wMaxPacket); 1534 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, 1535 MUSB2_MASK_CSRH_TXMODE | temp); 1536 break; 1537 case UE_ISOCHRONOUS: 1538 MUSB2_WRITE_1(sc, MUSB2_REG_TXMAXP, wMaxPacket); 1539 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, 1540 MUSB2_MASK_CSRH_TXMODE | 1541 MUSB2_MASK_CSRH_TXISO | temp); 1542 break; 1543 case UE_BULK: 1544 MUSB2_WRITE_1(sc, MUSB2_REG_TXMAXP, wMaxPacket); 1545 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, 1546 MUSB2_MASK_CSRH_TXMODE | temp); 1547 break; 1548 default: 1549 break; 1550 } 1551 1552 /* Need to flush twice in case of double bufring */ 1553 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 1554 if (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) { 1555 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 1556 MUSB2_MASK_CSRL_TXFFLUSH); 1557 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 1558 if (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) { 1559 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 1560 MUSB2_MASK_CSRL_TXFFLUSH); 1561 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 1562 } 1563 } 1564 /* reset data toggle */ 1565 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 1566 MUSB2_MASK_CSRL_TXDT_CLR); 1567 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0); 1568 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 1569 1570 /* set double/single buffering */ 1571 temp = MUSB2_READ_2(sc, MUSB2_REG_TXDBDIS); 1572 if (mps <= (sc->sc_hw_ep_profile[ep_no]. 1573 max_in_frame_size / 2)) { 1574 /* double buffer */ 1575 temp &= ~(1 << ep_no); 1576 } else { 1577 /* single buffer */ 1578 temp |= (1 << ep_no); 1579 } 1580 MUSB2_WRITE_2(sc, MUSB2_REG_TXDBDIS, temp); 1581 1582 /* clear sent stall */ 1583 if (csr & MUSB2_MASK_CSRL_TXSENTSTALL) { 1584 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0); 1585 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 1586 } 1587 } else { 1588 1589 temp = 0; 1590 1591 /* Configure endpoint */ 1592 switch (ep_type) { 1593 case UE_INTERRUPT: 1594 MUSB2_WRITE_1(sc, MUSB2_REG_RXMAXP, wMaxPacket); 1595 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH, 1596 MUSB2_MASK_CSRH_RXNYET | temp); 1597 break; 1598 case UE_ISOCHRONOUS: 1599 MUSB2_WRITE_1(sc, MUSB2_REG_RXMAXP, wMaxPacket); 1600 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH, 1601 MUSB2_MASK_CSRH_RXNYET | 1602 MUSB2_MASK_CSRH_RXISO | temp); 1603 break; 1604 case UE_BULK: 1605 MUSB2_WRITE_1(sc, MUSB2_REG_RXMAXP, wMaxPacket); 1606 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH, temp); 1607 break; 1608 default: 1609 break; 1610 } 1611 1612 /* Need to flush twice in case of double bufring */ 1613 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL); 1614 if (csr & MUSB2_MASK_CSRL_RXPKTRDY) { 1615 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 1616 MUSB2_MASK_CSRL_RXFFLUSH); 1617 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL); 1618 if (csr & MUSB2_MASK_CSRL_RXPKTRDY) { 1619 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 1620 MUSB2_MASK_CSRL_RXFFLUSH); 1621 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL); 1622 } 1623 } 1624 /* reset data toggle */ 1625 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 1626 MUSB2_MASK_CSRL_RXDT_CLR); 1627 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 0); 1628 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL); 1629 1630 /* set double/single buffering */ 1631 temp = MUSB2_READ_2(sc, MUSB2_REG_RXDBDIS); 1632 if (mps <= (sc->sc_hw_ep_profile[ep_no]. 1633 max_out_frame_size / 2)) { 1634 /* double buffer */ 1635 temp &= ~(1 << ep_no); 1636 } else { 1637 /* single buffer */ 1638 temp |= (1 << ep_no); 1639 } 1640 MUSB2_WRITE_2(sc, MUSB2_REG_RXDBDIS, temp); 1641 1642 /* clear sent stall */ 1643 if (csr & MUSB2_MASK_CSRL_RXSENTSTALL) { 1644 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 0); 1645 } 1646 } 1647} 1648 1649static void 1650musbotg_clear_stall(struct usb2_device *udev, struct usb2_pipe *pipe) 1651{ 1652 struct musbotg_softc *sc; 1653 struct usb2_endpoint_descriptor *ed; 1654 1655 DPRINTFN(4, "pipe=%p\n", pipe); 1656 1657 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 1658 1659 /* check mode */ 1660 if (udev->flags.usb2_mode != USB_MODE_DEVICE) { 1661 /* not supported */ 1662 return; 1663 } 1664 /* get softc */ 1665 sc = MUSBOTG_BUS2SC(udev->bus); 1666 1667 /* get endpoint descriptor */ 1668 ed = pipe->edesc; 1669 1670 /* reset endpoint */ 1671 musbotg_clear_stall_sub(sc, 1672 UGETW(ed->wMaxPacketSize), 1673 (ed->bEndpointAddress & UE_ADDR), 1674 (ed->bmAttributes & UE_XFERTYPE), 1675 (ed->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT))); 1676} 1677 1678usb2_error_t 1679musbotg_init(struct musbotg_softc *sc) 1680{ 1681 struct usb2_hw_ep_profile *pf; 1682 uint8_t nrx; 1683 uint8_t ntx; 1684 uint8_t temp; 1685 uint8_t fsize; 1686 uint8_t frx; 1687 uint8_t ftx; 1688 1689 DPRINTFN(1, "start\n"); 1690 1691 /* set up the bus structure */ 1692 sc->sc_bus.usbrev = USB_REV_2_0; 1693 sc->sc_bus.methods = &musbotg_bus_methods; 1694 1695 USB_BUS_LOCK(&sc->sc_bus); 1696 1697 /* turn on clocks */ 1698 1699 if (sc->sc_clocks_on) { 1700 (sc->sc_clocks_on) (sc->sc_clocks_arg); 1701 } 1702 /* wait a little for things to stabilise */ 1703 usb2_pause_mtx(&sc->sc_bus.bus_mtx, hz / 1000); 1704 1705 /* disable all interrupts */ 1706 1707 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, 0); 1708 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, 0); 1709 MUSB2_WRITE_2(sc, MUSB2_REG_INTRXE, 0); 1710 1711 /* disable pullup */ 1712 1713 musbotg_pull_common(sc, 0); 1714 1715 /* wait a little bit (10ms) */ 1716 usb2_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100); 1717 1718 /* disable double packet buffering */ 1719 MUSB2_WRITE_2(sc, MUSB2_REG_RXDBDIS, 0xFFFF); 1720 MUSB2_WRITE_2(sc, MUSB2_REG_TXDBDIS, 0xFFFF); 1721 1722 /* enable HighSpeed and ISO Update flags */ 1723 1724 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, 1725 MUSB2_MASK_HSENAB | MUSB2_MASK_ISOUPD); 1726 1727 /* clear Session bit, if set */ 1728 1729 temp = MUSB2_READ_1(sc, MUSB2_REG_DEVCTL); 1730 temp &= ~MUSB2_MASK_SESS; 1731 MUSB2_WRITE_1(sc, MUSB2_REG_DEVCTL, temp); 1732 1733 DPRINTF("DEVCTL=0x%02x\n", temp); 1734 1735 /* disable testmode */ 1736 1737 MUSB2_WRITE_1(sc, MUSB2_REG_TESTMODE, 0); 1738 1739 /* set default value */ 1740 1741 MUSB2_WRITE_1(sc, MUSB2_REG_MISC, 0); 1742 1743 /* select endpoint index 0 */ 1744 1745 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); 1746 1747 /* read out number of endpoints */ 1748 1749 nrx = 1750 (MUSB2_READ_1(sc, MUSB2_REG_EPINFO) / 16); 1751 1752 ntx = 1753 (MUSB2_READ_1(sc, MUSB2_REG_EPINFO) % 16); 1754 1755 /* these numbers exclude the control endpoint */ 1756 1757 DPRINTFN(2, "RX/TX endpoints: %u/%u\n", nrx, ntx); 1758 1759 sc->sc_ep_max = (nrx > ntx) ? nrx : ntx; 1760 if (sc->sc_ep_max == 0) { 1761 DPRINTFN(2, "ERROR: Looks like the clocks are off!\n"); 1762 } 1763 /* read out configuration data */ 1764 1765 sc->sc_conf_data = MUSB2_READ_1(sc, MUSB2_REG_CONFDATA); 1766 1767 DPRINTFN(2, "Config Data: 0x%02x\n", 1768 sc->sc_conf_data); 1769 1770 DPRINTFN(2, "HW version: 0x%04x\n", 1771 MUSB2_READ_1(sc, MUSB2_REG_HWVERS)); 1772 1773 /* initialise endpoint profiles */ 1774 1775 for (temp = 1; temp <= sc->sc_ep_max; temp++) { 1776 pf = sc->sc_hw_ep_profile + temp; 1777 1778 /* select endpoint */ 1779 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, temp); 1780 1781 fsize = MUSB2_READ_1(sc, MUSB2_REG_FSIZE); 1782 frx = (fsize & MUSB2_MASK_RX_FSIZE) / 16;; 1783 ftx = (fsize & MUSB2_MASK_TX_FSIZE); 1784 1785 DPRINTF("Endpoint %u FIFO size: IN=%u, OUT=%u\n", 1786 temp, pf->max_in_frame_size, 1787 pf->max_out_frame_size); 1788 1789 if (frx && ftx && (temp <= nrx) && (temp <= ntx)) { 1790 pf->max_in_frame_size = 1 << ftx; 1791 pf->max_out_frame_size = 1 << frx; 1792 pf->is_simplex = 0; /* duplex */ 1793 pf->support_multi_buffer = 1; 1794 pf->support_bulk = 1; 1795 pf->support_interrupt = 1; 1796 pf->support_isochronous = 1; 1797 pf->support_in = 1; 1798 pf->support_out = 1; 1799 } else if (frx && (temp <= nrx)) { 1800 pf->max_out_frame_size = 1 << frx; 1801 pf->is_simplex = 1; /* simplex */ 1802 pf->support_multi_buffer = 1; 1803 pf->support_bulk = 1; 1804 pf->support_interrupt = 1; 1805 pf->support_isochronous = 1; 1806 pf->support_out = 1; 1807 } else if (ftx && (temp <= ntx)) { 1808 pf->max_in_frame_size = 1 << ftx; 1809 pf->is_simplex = 1; /* simplex */ 1810 pf->support_multi_buffer = 1; 1811 pf->support_bulk = 1; 1812 pf->support_interrupt = 1; 1813 pf->support_isochronous = 1; 1814 pf->support_in = 1; 1815 } 1816 } 1817 1818 /* turn on default interrupts */ 1819 1820 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, 1821 MUSB2_MASK_IRESET); 1822 1823 musbotg_clocks_off(sc); 1824 1825 USB_BUS_UNLOCK(&sc->sc_bus); 1826 1827 /* catch any lost interrupts */ 1828 1829 musbotg_do_poll(&sc->sc_bus); 1830 1831 return (0); /* success */ 1832} 1833 1834void 1835musbotg_uninit(struct musbotg_softc *sc) 1836{ 1837 USB_BUS_LOCK(&sc->sc_bus); 1838 1839 /* disable all interrupts */ 1840 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, 0); 1841 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, 0); 1842 MUSB2_WRITE_2(sc, MUSB2_REG_INTRXE, 0); 1843 1844 sc->sc_flags.port_powered = 0; 1845 sc->sc_flags.status_vbus = 0; 1846 sc->sc_flags.status_bus_reset = 0; 1847 sc->sc_flags.status_suspend = 0; 1848 sc->sc_flags.change_suspend = 0; 1849 sc->sc_flags.change_connect = 1; 1850 1851 musbotg_pull_down(sc); 1852 musbotg_clocks_off(sc); 1853 USB_BUS_UNLOCK(&sc->sc_bus); 1854} 1855 1856void 1857musbotg_suspend(struct musbotg_softc *sc) 1858{ 1859 return; 1860} 1861 1862void 1863musbotg_resume(struct musbotg_softc *sc) 1864{ 1865 return; 1866} 1867 1868static void 1869musbotg_do_poll(struct usb2_bus *bus) 1870{ 1871 struct musbotg_softc *sc = MUSBOTG_BUS2SC(bus); 1872 1873 USB_BUS_LOCK(&sc->sc_bus); 1874 musbotg_interrupt_poll(sc); 1875 musbotg_root_ctrl_poll(sc); 1876 USB_BUS_UNLOCK(&sc->sc_bus); 1877} 1878 1879/*------------------------------------------------------------------------* 1880 * musbotg bulk support 1881 *------------------------------------------------------------------------*/ 1882static void 1883musbotg_device_bulk_open(struct usb2_xfer *xfer) 1884{ 1885 return; 1886} 1887 1888static void 1889musbotg_device_bulk_close(struct usb2_xfer *xfer) 1890{ 1891 musbotg_device_done(xfer, USB_ERR_CANCELLED); 1892} 1893 1894static void 1895musbotg_device_bulk_enter(struct usb2_xfer *xfer) 1896{ 1897 return; 1898} 1899 1900static void 1901musbotg_device_bulk_start(struct usb2_xfer *xfer) 1902{ 1903 /* setup TDs */ 1904 musbotg_setup_standard_chain(xfer); 1905 musbotg_start_standard_chain(xfer); 1906} 1907 1908struct usb2_pipe_methods musbotg_device_bulk_methods = 1909{ 1910 .open = musbotg_device_bulk_open, 1911 .close = musbotg_device_bulk_close, 1912 .enter = musbotg_device_bulk_enter, 1913 .start = musbotg_device_bulk_start, 1914 .enter_is_cancelable = 1, 1915 .start_is_cancelable = 1, 1916}; 1917 1918/*------------------------------------------------------------------------* 1919 * musbotg control support 1920 *------------------------------------------------------------------------*/ 1921static void 1922musbotg_device_ctrl_open(struct usb2_xfer *xfer) 1923{ 1924 return; 1925} 1926 1927static void 1928musbotg_device_ctrl_close(struct usb2_xfer *xfer) 1929{ 1930 musbotg_device_done(xfer, USB_ERR_CANCELLED); 1931} 1932 1933static void 1934musbotg_device_ctrl_enter(struct usb2_xfer *xfer) 1935{ 1936 return; 1937} 1938 1939static void 1940musbotg_device_ctrl_start(struct usb2_xfer *xfer) 1941{ 1942 /* setup TDs */ 1943 musbotg_setup_standard_chain(xfer); 1944 musbotg_start_standard_chain(xfer); 1945} 1946 1947struct usb2_pipe_methods musbotg_device_ctrl_methods = 1948{ 1949 .open = musbotg_device_ctrl_open, 1950 .close = musbotg_device_ctrl_close, 1951 .enter = musbotg_device_ctrl_enter, 1952 .start = musbotg_device_ctrl_start, 1953 .enter_is_cancelable = 1, 1954 .start_is_cancelable = 1, 1955}; 1956 1957/*------------------------------------------------------------------------* 1958 * musbotg interrupt support 1959 *------------------------------------------------------------------------*/ 1960static void 1961musbotg_device_intr_open(struct usb2_xfer *xfer) 1962{ 1963 return; 1964} 1965 1966static void 1967musbotg_device_intr_close(struct usb2_xfer *xfer) 1968{ 1969 musbotg_device_done(xfer, USB_ERR_CANCELLED); 1970} 1971 1972static void 1973musbotg_device_intr_enter(struct usb2_xfer *xfer) 1974{ 1975 return; 1976} 1977 1978static void 1979musbotg_device_intr_start(struct usb2_xfer *xfer) 1980{ 1981 /* setup TDs */ 1982 musbotg_setup_standard_chain(xfer); 1983 musbotg_start_standard_chain(xfer); 1984} 1985 1986struct usb2_pipe_methods musbotg_device_intr_methods = 1987{ 1988 .open = musbotg_device_intr_open, 1989 .close = musbotg_device_intr_close, 1990 .enter = musbotg_device_intr_enter, 1991 .start = musbotg_device_intr_start, 1992 .enter_is_cancelable = 1, 1993 .start_is_cancelable = 1, 1994}; 1995 1996/*------------------------------------------------------------------------* 1997 * musbotg full speed isochronous support 1998 *------------------------------------------------------------------------*/ 1999static void 2000musbotg_device_isoc_open(struct usb2_xfer *xfer) 2001{ 2002 return; 2003} 2004 2005static void 2006musbotg_device_isoc_close(struct usb2_xfer *xfer) 2007{ 2008 musbotg_device_done(xfer, USB_ERR_CANCELLED); 2009} 2010 2011static void 2012musbotg_device_isoc_enter(struct usb2_xfer *xfer) 2013{ 2014 struct musbotg_softc *sc = MUSBOTG_BUS2SC(xfer->xroot->bus); 2015 uint32_t temp; 2016 uint32_t nframes; 2017 uint32_t fs_frames; 2018 2019 DPRINTFN(5, "xfer=%p next=%d nframes=%d\n", 2020 xfer, xfer->pipe->isoc_next, xfer->nframes); 2021 2022 /* get the current frame index */ 2023 2024 nframes = MUSB2_READ_2(sc, MUSB2_REG_FRAME); 2025 2026 /* 2027 * check if the frame index is within the window where the frames 2028 * will be inserted 2029 */ 2030 temp = (nframes - xfer->pipe->isoc_next) & MUSB2_MASK_FRAME; 2031 2032 if (usb2_get_speed(xfer->xroot->udev) == USB_SPEED_HIGH) { 2033 fs_frames = (xfer->nframes + 7) / 8; 2034 } else { 2035 fs_frames = xfer->nframes; 2036 } 2037 2038 if ((xfer->pipe->is_synced == 0) || 2039 (temp < fs_frames)) { 2040 /* 2041 * If there is data underflow or the pipe queue is 2042 * empty we schedule the transfer a few frames ahead 2043 * of the current frame position. Else two isochronous 2044 * transfers might overlap. 2045 */ 2046 xfer->pipe->isoc_next = (nframes + 3) & MUSB2_MASK_FRAME; 2047 xfer->pipe->is_synced = 1; 2048 DPRINTFN(2, "start next=%d\n", xfer->pipe->isoc_next); 2049 } 2050 /* 2051 * compute how many milliseconds the insertion is ahead of the 2052 * current frame position: 2053 */ 2054 temp = (xfer->pipe->isoc_next - nframes) & MUSB2_MASK_FRAME; 2055 2056 /* 2057 * pre-compute when the isochronous transfer will be finished: 2058 */ 2059 xfer->isoc_time_complete = 2060 usb2_isoc_time_expand(&sc->sc_bus, nframes) + temp + 2061 fs_frames; 2062 2063 /* compute frame number for next insertion */ 2064 xfer->pipe->isoc_next += fs_frames; 2065 2066 /* setup TDs */ 2067 musbotg_setup_standard_chain(xfer); 2068} 2069 2070static void 2071musbotg_device_isoc_start(struct usb2_xfer *xfer) 2072{ 2073 /* start TD chain */ 2074 musbotg_start_standard_chain(xfer); 2075} 2076 2077struct usb2_pipe_methods musbotg_device_isoc_methods = 2078{ 2079 .open = musbotg_device_isoc_open, 2080 .close = musbotg_device_isoc_close, 2081 .enter = musbotg_device_isoc_enter, 2082 .start = musbotg_device_isoc_start, 2083 .enter_is_cancelable = 1, 2084 .start_is_cancelable = 1, 2085}; 2086 2087/*------------------------------------------------------------------------* 2088 * musbotg root control support 2089 *------------------------------------------------------------------------* 2090 * simulate a hardware HUB by handling 2091 * all the necessary requests 2092 *------------------------------------------------------------------------*/ 2093static void 2094musbotg_root_ctrl_open(struct usb2_xfer *xfer) 2095{ 2096 return; 2097} 2098 2099static void 2100musbotg_root_ctrl_close(struct usb2_xfer *xfer) 2101{ 2102 struct musbotg_softc *sc = MUSBOTG_BUS2SC(xfer->xroot->bus); 2103 2104 if (sc->sc_root_ctrl.xfer == xfer) { 2105 sc->sc_root_ctrl.xfer = NULL; 2106 } 2107 musbotg_device_done(xfer, USB_ERR_CANCELLED); 2108} 2109 2110/* 2111 * USB descriptors for the virtual Root HUB: 2112 */ 2113 2114static const struct usb2_device_descriptor musbotg_devd = { 2115 .bLength = sizeof(struct usb2_device_descriptor), 2116 .bDescriptorType = UDESC_DEVICE, 2117 .bcdUSB = {0x00, 0x02}, 2118 .bDeviceClass = UDCLASS_HUB, 2119 .bDeviceSubClass = UDSUBCLASS_HUB, 2120 .bDeviceProtocol = UDPROTO_HSHUBSTT, 2121 .bMaxPacketSize = 64, 2122 .bcdDevice = {0x00, 0x01}, 2123 .iManufacturer = 1, 2124 .iProduct = 2, 2125 .bNumConfigurations = 1, 2126}; 2127 2128static const struct usb2_device_qualifier musbotg_odevd = { 2129 .bLength = sizeof(struct usb2_device_qualifier), 2130 .bDescriptorType = UDESC_DEVICE_QUALIFIER, 2131 .bcdUSB = {0x00, 0x02}, 2132 .bDeviceClass = UDCLASS_HUB, 2133 .bDeviceSubClass = UDSUBCLASS_HUB, 2134 .bDeviceProtocol = UDPROTO_FSHUB, 2135 .bMaxPacketSize0 = 0, 2136 .bNumConfigurations = 0, 2137}; 2138 2139static const struct musbotg_config_desc musbotg_confd = { 2140 .confd = { 2141 .bLength = sizeof(struct usb2_config_descriptor), 2142 .bDescriptorType = UDESC_CONFIG, 2143 .wTotalLength[0] = sizeof(musbotg_confd), 2144 .bNumInterface = 1, 2145 .bConfigurationValue = 1, 2146 .iConfiguration = 0, 2147 .bmAttributes = UC_SELF_POWERED, 2148 .bMaxPower = 0, 2149 }, 2150 .ifcd = { 2151 .bLength = sizeof(struct usb2_interface_descriptor), 2152 .bDescriptorType = UDESC_INTERFACE, 2153 .bNumEndpoints = 1, 2154 .bInterfaceClass = UICLASS_HUB, 2155 .bInterfaceSubClass = UISUBCLASS_HUB, 2156 .bInterfaceProtocol = UIPROTO_HSHUBSTT, 2157 }, 2158 2159 .endpd = { 2160 .bLength = sizeof(struct usb2_endpoint_descriptor), 2161 .bDescriptorType = UDESC_ENDPOINT, 2162 .bEndpointAddress = (UE_DIR_IN | MUSBOTG_INTR_ENDPT), 2163 .bmAttributes = UE_INTERRUPT, 2164 .wMaxPacketSize[0] = 8, 2165 .bInterval = 255, 2166 }, 2167}; 2168 2169static const struct usb2_hub_descriptor_min musbotg_hubd = { 2170 .bDescLength = sizeof(musbotg_hubd), 2171 .bDescriptorType = UDESC_HUB, 2172 .bNbrPorts = 1, 2173 .wHubCharacteristics[0] = 2174 (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL) & 0xFF, 2175 .wHubCharacteristics[1] = 2176 (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL) >> 16, 2177 .bPwrOn2PwrGood = 50, 2178 .bHubContrCurrent = 0, 2179 .DeviceRemovable = {0}, /* port is removable */ 2180}; 2181 2182#define STRING_LANG \ 2183 0x09, 0x04, /* American English */ 2184 2185#define STRING_VENDOR \ 2186 'M', 0, 'e', 0, 'n', 0, 't', 0, 'o', 0, 'r', 0, ' ', 0, \ 2187 'G', 0, 'r', 0, 'a', 0, 'p', 0, 'h', 0, 'i', 0, 'c', 0, 's', 0 2188 2189#define STRING_PRODUCT \ 2190 'O', 0, 'T', 0, 'G', 0, ' ', 0, 'R', 0, \ 2191 'o', 0, 'o', 0, 't', 0, ' ', 0, 'H', 0, \ 2192 'U', 0, 'B', 0, 2193 2194USB_MAKE_STRING_DESC(STRING_LANG, musbotg_langtab); 2195USB_MAKE_STRING_DESC(STRING_VENDOR, musbotg_vendor); 2196USB_MAKE_STRING_DESC(STRING_PRODUCT, musbotg_product); 2197 2198static void 2199musbotg_root_ctrl_enter(struct usb2_xfer *xfer) 2200{ 2201 return; 2202} 2203 2204static void 2205musbotg_root_ctrl_start(struct usb2_xfer *xfer) 2206{ 2207 struct musbotg_softc *sc = MUSBOTG_BUS2SC(xfer->xroot->bus); 2208 2209 sc->sc_root_ctrl.xfer = xfer; 2210 2211 usb2_bus_roothub_exec(xfer->xroot->bus); 2212} 2213 2214static void 2215musbotg_root_ctrl_task(struct usb2_bus *bus) 2216{ 2217 musbotg_root_ctrl_poll(MUSBOTG_BUS2SC(bus)); 2218} 2219 2220static void 2221musbotg_root_ctrl_done(struct usb2_xfer *xfer, 2222 struct usb2_sw_transfer *std) 2223{ 2224 struct musbotg_softc *sc = MUSBOTG_BUS2SC(xfer->xroot->bus); 2225 uint16_t value; 2226 uint16_t index; 2227 2228 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2229 2230 if (std->state != USB_SW_TR_SETUP) { 2231 if (std->state == USB_SW_TR_PRE_CALLBACK) { 2232 /* transfer transferred */ 2233 musbotg_device_done(xfer, std->err); 2234 } 2235 goto done; 2236 } 2237 /* buffer reset */ 2238 std->ptr = USB_ADD_BYTES(&sc->sc_hub_temp, 0); 2239 std->len = 0; 2240 2241 value = UGETW(std->req.wValue); 2242 index = UGETW(std->req.wIndex); 2243 2244 /* demultiplex the control request */ 2245 2246 switch (std->req.bmRequestType) { 2247 case UT_READ_DEVICE: 2248 switch (std->req.bRequest) { 2249 case UR_GET_DESCRIPTOR: 2250 goto tr_handle_get_descriptor; 2251 case UR_GET_CONFIG: 2252 goto tr_handle_get_config; 2253 case UR_GET_STATUS: 2254 goto tr_handle_get_status; 2255 default: 2256 goto tr_stalled; 2257 } 2258 break; 2259 2260 case UT_WRITE_DEVICE: 2261 switch (std->req.bRequest) { 2262 case UR_SET_ADDRESS: 2263 goto tr_handle_set_address; 2264 case UR_SET_CONFIG: 2265 goto tr_handle_set_config; 2266 case UR_CLEAR_FEATURE: 2267 goto tr_valid; /* nop */ 2268 case UR_SET_DESCRIPTOR: 2269 goto tr_valid; /* nop */ 2270 case UR_SET_FEATURE: 2271 default: 2272 goto tr_stalled; 2273 } 2274 break; 2275 2276 case UT_WRITE_ENDPOINT: 2277 switch (std->req.bRequest) { 2278 case UR_CLEAR_FEATURE: 2279 switch (UGETW(std->req.wValue)) { 2280 case UF_ENDPOINT_HALT: 2281 goto tr_handle_clear_halt; 2282 case UF_DEVICE_REMOTE_WAKEUP: 2283 goto tr_handle_clear_wakeup; 2284 default: 2285 goto tr_stalled; 2286 } 2287 break; 2288 case UR_SET_FEATURE: 2289 switch (UGETW(std->req.wValue)) { 2290 case UF_ENDPOINT_HALT: 2291 goto tr_handle_set_halt; 2292 case UF_DEVICE_REMOTE_WAKEUP: 2293 goto tr_handle_set_wakeup; 2294 default: 2295 goto tr_stalled; 2296 } 2297 break; 2298 case UR_SYNCH_FRAME: 2299 goto tr_valid; /* nop */ 2300 default: 2301 goto tr_stalled; 2302 } 2303 break; 2304 2305 case UT_READ_ENDPOINT: 2306 switch (std->req.bRequest) { 2307 case UR_GET_STATUS: 2308 goto tr_handle_get_ep_status; 2309 default: 2310 goto tr_stalled; 2311 } 2312 break; 2313 2314 case UT_WRITE_INTERFACE: 2315 switch (std->req.bRequest) { 2316 case UR_SET_INTERFACE: 2317 goto tr_handle_set_interface; 2318 case UR_CLEAR_FEATURE: 2319 goto tr_valid; /* nop */ 2320 case UR_SET_FEATURE: 2321 default: 2322 goto tr_stalled; 2323 } 2324 break; 2325 2326 case UT_READ_INTERFACE: 2327 switch (std->req.bRequest) { 2328 case UR_GET_INTERFACE: 2329 goto tr_handle_get_interface; 2330 case UR_GET_STATUS: 2331 goto tr_handle_get_iface_status; 2332 default: 2333 goto tr_stalled; 2334 } 2335 break; 2336 2337 case UT_WRITE_CLASS_INTERFACE: 2338 case UT_WRITE_VENDOR_INTERFACE: 2339 /* XXX forward */ 2340 break; 2341 2342 case UT_READ_CLASS_INTERFACE: 2343 case UT_READ_VENDOR_INTERFACE: 2344 /* XXX forward */ 2345 break; 2346 2347 case UT_WRITE_CLASS_DEVICE: 2348 switch (std->req.bRequest) { 2349 case UR_CLEAR_FEATURE: 2350 goto tr_valid; 2351 case UR_SET_DESCRIPTOR: 2352 case UR_SET_FEATURE: 2353 break; 2354 default: 2355 goto tr_stalled; 2356 } 2357 break; 2358 2359 case UT_WRITE_CLASS_OTHER: 2360 switch (std->req.bRequest) { 2361 case UR_CLEAR_FEATURE: 2362 goto tr_handle_clear_port_feature; 2363 case UR_SET_FEATURE: 2364 goto tr_handle_set_port_feature; 2365 case UR_CLEAR_TT_BUFFER: 2366 case UR_RESET_TT: 2367 case UR_STOP_TT: 2368 goto tr_valid; 2369 2370 default: 2371 goto tr_stalled; 2372 } 2373 break; 2374 2375 case UT_READ_CLASS_OTHER: 2376 switch (std->req.bRequest) { 2377 case UR_GET_TT_STATE: 2378 goto tr_handle_get_tt_state; 2379 case UR_GET_STATUS: 2380 goto tr_handle_get_port_status; 2381 default: 2382 goto tr_stalled; 2383 } 2384 break; 2385 2386 case UT_READ_CLASS_DEVICE: 2387 switch (std->req.bRequest) { 2388 case UR_GET_DESCRIPTOR: 2389 goto tr_handle_get_class_descriptor; 2390 case UR_GET_STATUS: 2391 goto tr_handle_get_class_status; 2392 2393 default: 2394 goto tr_stalled; 2395 } 2396 break; 2397 default: 2398 goto tr_stalled; 2399 } 2400 goto tr_valid; 2401 2402tr_handle_get_descriptor: 2403 switch (value >> 8) { 2404 case UDESC_DEVICE: 2405 if (value & 0xff) { 2406 goto tr_stalled; 2407 } 2408 std->len = sizeof(musbotg_devd); 2409 std->ptr = USB_ADD_BYTES(&musbotg_devd, 0); 2410 goto tr_valid; 2411 case UDESC_CONFIG: 2412 if (value & 0xff) { 2413 goto tr_stalled; 2414 } 2415 std->len = sizeof(musbotg_confd); 2416 std->ptr = USB_ADD_BYTES(&musbotg_confd, 0); 2417 goto tr_valid; 2418 case UDESC_STRING: 2419 switch (value & 0xff) { 2420 case 0: /* Language table */ 2421 std->len = sizeof(musbotg_langtab); 2422 std->ptr = USB_ADD_BYTES(&musbotg_langtab, 0); 2423 goto tr_valid; 2424 2425 case 1: /* Vendor */ 2426 std->len = sizeof(musbotg_vendor); 2427 std->ptr = USB_ADD_BYTES(&musbotg_vendor, 0); 2428 goto tr_valid; 2429 2430 case 2: /* Product */ 2431 std->len = sizeof(musbotg_product); 2432 std->ptr = USB_ADD_BYTES(&musbotg_product, 0); 2433 goto tr_valid; 2434 default: 2435 break; 2436 } 2437 break; 2438 default: 2439 goto tr_stalled; 2440 } 2441 goto tr_stalled; 2442 2443tr_handle_get_config: 2444 std->len = 1; 2445 sc->sc_hub_temp.wValue[0] = sc->sc_conf; 2446 goto tr_valid; 2447 2448tr_handle_get_status: 2449 std->len = 2; 2450 USETW(sc->sc_hub_temp.wValue, UDS_SELF_POWERED); 2451 goto tr_valid; 2452 2453tr_handle_set_address: 2454 if (value & 0xFF00) { 2455 goto tr_stalled; 2456 } 2457 sc->sc_rt_addr = value; 2458 goto tr_valid; 2459 2460tr_handle_set_config: 2461 if (value >= 2) { 2462 goto tr_stalled; 2463 } 2464 sc->sc_conf = value; 2465 goto tr_valid; 2466 2467tr_handle_get_interface: 2468 std->len = 1; 2469 sc->sc_hub_temp.wValue[0] = 0; 2470 goto tr_valid; 2471 2472tr_handle_get_tt_state: 2473tr_handle_get_class_status: 2474tr_handle_get_iface_status: 2475tr_handle_get_ep_status: 2476 std->len = 2; 2477 USETW(sc->sc_hub_temp.wValue, 0); 2478 goto tr_valid; 2479 2480tr_handle_set_halt: 2481tr_handle_set_interface: 2482tr_handle_set_wakeup: 2483tr_handle_clear_wakeup: 2484tr_handle_clear_halt: 2485 goto tr_valid; 2486 2487tr_handle_clear_port_feature: 2488 if (index != 1) { 2489 goto tr_stalled; 2490 } 2491 DPRINTFN(8, "UR_CLEAR_PORT_FEATURE on port %d\n", index); 2492 2493 switch (value) { 2494 case UHF_PORT_SUSPEND: 2495 musbotg_wakeup_peer(xfer); 2496 break; 2497 2498 case UHF_PORT_ENABLE: 2499 sc->sc_flags.port_enabled = 0; 2500 break; 2501 2502 case UHF_PORT_TEST: 2503 case UHF_PORT_INDICATOR: 2504 case UHF_C_PORT_ENABLE: 2505 case UHF_C_PORT_OVER_CURRENT: 2506 case UHF_C_PORT_RESET: 2507 /* nops */ 2508 break; 2509 case UHF_PORT_POWER: 2510 sc->sc_flags.port_powered = 0; 2511 musbotg_pull_down(sc); 2512 musbotg_clocks_off(sc); 2513 break; 2514 case UHF_C_PORT_CONNECTION: 2515 sc->sc_flags.change_connect = 0; 2516 break; 2517 case UHF_C_PORT_SUSPEND: 2518 sc->sc_flags.change_suspend = 0; 2519 break; 2520 default: 2521 std->err = USB_ERR_IOERROR; 2522 goto done; 2523 } 2524 goto tr_valid; 2525 2526tr_handle_set_port_feature: 2527 if (index != 1) { 2528 goto tr_stalled; 2529 } 2530 DPRINTFN(8, "UR_SET_PORT_FEATURE\n"); 2531 2532 switch (value) { 2533 case UHF_PORT_ENABLE: 2534 sc->sc_flags.port_enabled = 1; 2535 break; 2536 case UHF_PORT_SUSPEND: 2537 case UHF_PORT_RESET: 2538 case UHF_PORT_TEST: 2539 case UHF_PORT_INDICATOR: 2540 /* nops */ 2541 break; 2542 case UHF_PORT_POWER: 2543 sc->sc_flags.port_powered = 1; 2544 break; 2545 default: 2546 std->err = USB_ERR_IOERROR; 2547 goto done; 2548 } 2549 goto tr_valid; 2550 2551tr_handle_get_port_status: 2552 2553 DPRINTFN(8, "UR_GET_PORT_STATUS\n"); 2554 2555 if (index != 1) { 2556 goto tr_stalled; 2557 } 2558 if (sc->sc_flags.status_vbus) { 2559 musbotg_clocks_on(sc); 2560 musbotg_pull_up(sc); 2561 } else { 2562 musbotg_pull_down(sc); 2563 musbotg_clocks_off(sc); 2564 } 2565 2566 /* Select Device Side Mode */ 2567 value = UPS_PORT_MODE_DEVICE; 2568 2569 if (sc->sc_flags.status_high_speed) { 2570 value |= UPS_HIGH_SPEED; 2571 } 2572 if (sc->sc_flags.port_powered) { 2573 value |= UPS_PORT_POWER; 2574 } 2575 if (sc->sc_flags.port_enabled) { 2576 value |= UPS_PORT_ENABLED; 2577 } 2578 if (sc->sc_flags.status_vbus && 2579 sc->sc_flags.status_bus_reset) { 2580 value |= UPS_CURRENT_CONNECT_STATUS; 2581 } 2582 if (sc->sc_flags.status_suspend) { 2583 value |= UPS_SUSPEND; 2584 } 2585 USETW(sc->sc_hub_temp.ps.wPortStatus, value); 2586 2587 value = 0; 2588 2589 if (sc->sc_flags.change_connect) { 2590 value |= UPS_C_CONNECT_STATUS; 2591 2592 if (sc->sc_flags.status_vbus && 2593 sc->sc_flags.status_bus_reset) { 2594 /* reset EP0 state */ 2595 sc->sc_ep0_busy = 0; 2596 sc->sc_ep0_cmd = 0; 2597 } 2598 } 2599 if (sc->sc_flags.change_suspend) { 2600 value |= UPS_C_SUSPEND; 2601 } 2602 USETW(sc->sc_hub_temp.ps.wPortChange, value); 2603 std->len = sizeof(sc->sc_hub_temp.ps); 2604 goto tr_valid; 2605 2606tr_handle_get_class_descriptor: 2607 if (value & 0xFF) { 2608 goto tr_stalled; 2609 } 2610 std->ptr = USB_ADD_BYTES(&musbotg_hubd, 0); 2611 std->len = sizeof(musbotg_hubd); 2612 goto tr_valid; 2613 2614tr_stalled: 2615 std->err = USB_ERR_STALLED; 2616tr_valid: 2617done: 2618 return; 2619} 2620 2621static void 2622musbotg_root_ctrl_poll(struct musbotg_softc *sc) 2623{ 2624 usb2_sw_transfer(&sc->sc_root_ctrl, 2625 &musbotg_root_ctrl_done); 2626} 2627 2628struct usb2_pipe_methods musbotg_root_ctrl_methods = 2629{ 2630 .open = musbotg_root_ctrl_open, 2631 .close = musbotg_root_ctrl_close, 2632 .enter = musbotg_root_ctrl_enter, 2633 .start = musbotg_root_ctrl_start, 2634 .enter_is_cancelable = 1, 2635 .start_is_cancelable = 0, 2636}; 2637 2638/*------------------------------------------------------------------------* 2639 * musbotg root interrupt support 2640 *------------------------------------------------------------------------*/ 2641static void 2642musbotg_root_intr_open(struct usb2_xfer *xfer) 2643{ 2644 return; 2645} 2646 2647static void 2648musbotg_root_intr_close(struct usb2_xfer *xfer) 2649{ 2650 struct musbotg_softc *sc = MUSBOTG_BUS2SC(xfer->xroot->bus); 2651 2652 if (sc->sc_root_intr.xfer == xfer) { 2653 sc->sc_root_intr.xfer = NULL; 2654 } 2655 musbotg_device_done(xfer, USB_ERR_CANCELLED); 2656} 2657 2658static void 2659musbotg_root_intr_enter(struct usb2_xfer *xfer) 2660{ 2661 return; 2662} 2663 2664static void 2665musbotg_root_intr_start(struct usb2_xfer *xfer) 2666{ 2667 struct musbotg_softc *sc = MUSBOTG_BUS2SC(xfer->xroot->bus); 2668 2669 sc->sc_root_intr.xfer = xfer; 2670} 2671 2672struct usb2_pipe_methods musbotg_root_intr_methods = 2673{ 2674 .open = musbotg_root_intr_open, 2675 .close = musbotg_root_intr_close, 2676 .enter = musbotg_root_intr_enter, 2677 .start = musbotg_root_intr_start, 2678 .enter_is_cancelable = 1, 2679 .start_is_cancelable = 1, 2680}; 2681 2682static void 2683musbotg_xfer_setup(struct usb2_setup_params *parm) 2684{ 2685 const struct usb2_hw_ep_profile *pf; 2686 struct musbotg_softc *sc; 2687 struct usb2_xfer *xfer; 2688 void *last_obj; 2689 uint32_t ntd; 2690 uint32_t n; 2691 uint8_t ep_no; 2692 2693 sc = MUSBOTG_BUS2SC(parm->udev->bus); 2694 xfer = parm->curr_xfer; 2695 2696 /* 2697 * NOTE: This driver does not use any of the parameters that 2698 * are computed from the following values. Just set some 2699 * reasonable dummies: 2700 */ 2701 parm->hc_max_packet_size = 0x400; 2702 parm->hc_max_frame_size = 0x400; 2703 2704 if ((parm->methods == &musbotg_device_isoc_methods) || 2705 (parm->methods == &musbotg_device_intr_methods)) 2706 parm->hc_max_packet_count = 3; 2707 else 2708 parm->hc_max_packet_count = 1; 2709 2710 usb2_transfer_setup_sub(parm); 2711 2712 /* 2713 * compute maximum number of TDs 2714 */ 2715 if (parm->methods == &musbotg_device_ctrl_methods) { 2716 2717 ntd = xfer->nframes + 1 /* STATUS */ + 1 /* SYNC */ ; 2718 2719 } else if (parm->methods == &musbotg_device_bulk_methods) { 2720 2721 ntd = xfer->nframes + 1 /* SYNC */ ; 2722 2723 } else if (parm->methods == &musbotg_device_intr_methods) { 2724 2725 ntd = xfer->nframes + 1 /* SYNC */ ; 2726 2727 } else if (parm->methods == &musbotg_device_isoc_methods) { 2728 2729 ntd = xfer->nframes + 1 /* SYNC */ ; 2730 2731 } else { 2732 2733 ntd = 0; 2734 } 2735 2736 /* 2737 * check if "usb2_transfer_setup_sub" set an error 2738 */ 2739 if (parm->err) { 2740 return; 2741 } 2742 /* 2743 * allocate transfer descriptors 2744 */ 2745 last_obj = NULL; 2746 2747 /* 2748 * get profile stuff 2749 */ 2750 if (ntd) { 2751 2752 ep_no = xfer->endpoint & UE_ADDR; 2753 musbotg_get_hw_ep_profile(parm->udev, &pf, ep_no); 2754 2755 if (pf == NULL) { 2756 /* should not happen */ 2757 parm->err = USB_ERR_INVAL; 2758 return; 2759 } 2760 } else { 2761 ep_no = 0; 2762 pf = NULL; 2763 } 2764 2765 /* align data */ 2766 parm->size[0] += ((-parm->size[0]) & (USB_HOST_ALIGN - 1)); 2767 2768 for (n = 0; n != ntd; n++) { 2769 2770 struct musbotg_td *td; 2771 2772 if (parm->buf) { 2773 2774 td = USB_ADD_BYTES(parm->buf, parm->size[0]); 2775 2776 /* init TD */ 2777 td->max_frame_size = xfer->max_frame_size; 2778 td->ep_no = ep_no; 2779 td->obj_next = last_obj; 2780 2781 last_obj = td; 2782 } 2783 parm->size[0] += sizeof(*td); 2784 } 2785 2786 xfer->td_start[0] = last_obj; 2787} 2788 2789static void 2790musbotg_xfer_unsetup(struct usb2_xfer *xfer) 2791{ 2792 return; 2793} 2794 2795static void 2796musbotg_pipe_init(struct usb2_device *udev, struct usb2_endpoint_descriptor *edesc, 2797 struct usb2_pipe *pipe) 2798{ 2799 struct musbotg_softc *sc = MUSBOTG_BUS2SC(udev->bus); 2800 2801 DPRINTFN(2, "pipe=%p, addr=%d, endpt=%d, mode=%d (%d)\n", 2802 pipe, udev->address, 2803 edesc->bEndpointAddress, udev->flags.usb2_mode, 2804 sc->sc_rt_addr); 2805 2806 if (udev->device_index == sc->sc_rt_addr) { 2807 2808 if (udev->flags.usb2_mode != USB_MODE_HOST) { 2809 /* not supported */ 2810 return; 2811 } 2812 switch (edesc->bEndpointAddress) { 2813 case USB_CONTROL_ENDPOINT: 2814 pipe->methods = &musbotg_root_ctrl_methods; 2815 break; 2816 case UE_DIR_IN | MUSBOTG_INTR_ENDPT: 2817 pipe->methods = &musbotg_root_intr_methods; 2818 break; 2819 default: 2820 /* do nothing */ 2821 break; 2822 } 2823 } else { 2824 2825 if (udev->flags.usb2_mode != USB_MODE_DEVICE) { 2826 /* not supported */ 2827 return; 2828 } 2829 if ((udev->speed != USB_SPEED_FULL) && 2830 (udev->speed != USB_SPEED_HIGH)) { 2831 /* not supported */ 2832 return; 2833 } 2834 switch (edesc->bmAttributes & UE_XFERTYPE) { 2835 case UE_CONTROL: 2836 pipe->methods = &musbotg_device_ctrl_methods; 2837 break; 2838 case UE_INTERRUPT: 2839 pipe->methods = &musbotg_device_intr_methods; 2840 break; 2841 case UE_ISOCHRONOUS: 2842 pipe->methods = &musbotg_device_isoc_methods; 2843 break; 2844 case UE_BULK: 2845 pipe->methods = &musbotg_device_bulk_methods; 2846 break; 2847 default: 2848 /* do nothing */ 2849 break; 2850 } 2851 } 2852} 2853 2854struct usb2_bus_methods musbotg_bus_methods = 2855{ 2856 .pipe_init = &musbotg_pipe_init, 2857 .xfer_setup = &musbotg_xfer_setup, 2858 .xfer_unsetup = &musbotg_xfer_unsetup, 2859 .get_hw_ep_profile = &musbotg_get_hw_ep_profile, 2860 .set_stall = &musbotg_set_stall, 2861 .clear_stall = &musbotg_clear_stall, 2862 .roothub_exec = &musbotg_root_ctrl_task, 2863}; 2864