musb_otg.c revision 186730
1/* $FreeBSD: head/sys/dev/usb2/controller/musb2_otg.c 186730 2009-01-04 00:12:01Z alfred $ */ 2/*- 3 * Copyright (c) 2008 Hans Petter Selasky. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27/* 28 * Thanks to Mentor Graphics for providing a reference driver for this 29 * USB chip at their homepage. 30 */ 31 32/* 33 * This file contains the driver for the Mentor Graphics Inventra USB 34 * 2.0 High Speed Dual-Role controller. 35 * 36 * NOTE: The current implementation only supports Device Side Mode! 37 */ 38 39#include <dev/usb2/include/usb2_standard.h> 40#include <dev/usb2/include/usb2_mfunc.h> 41#include <dev/usb2/include/usb2_error.h> 42#include <dev/usb2/include/usb2_defs.h> 43 44#define USB_DEBUG_VAR musbotgdebug 45#define usb2_config_td_cc musbotg_config_copy 46#define usb2_config_td_softc musbotg_softc 47 48#include <dev/usb2/core/usb2_core.h> 49#include <dev/usb2/core/usb2_debug.h> 50#include <dev/usb2/core/usb2_busdma.h> 51#include <dev/usb2/core/usb2_process.h> 52#include <dev/usb2/core/usb2_config_td.h> 53#include <dev/usb2/core/usb2_sw_transfer.h> 54#include <dev/usb2/core/usb2_transfer.h> 55#include <dev/usb2/core/usb2_device.h> 56#include <dev/usb2/core/usb2_hub.h> 57#include <dev/usb2/core/usb2_util.h> 58 59#include <dev/usb2/controller/usb2_controller.h> 60#include <dev/usb2/controller/usb2_bus.h> 61#include <dev/usb2/controller/musb2_otg.h> 62 63#define MUSBOTG_INTR_ENDPT 1 64 65#define MUSBOTG_BUS2SC(bus) \ 66 ((struct musbotg_softc *)(((uint8_t *)(bus)) - \ 67 USB_P2U(&(((struct musbotg_softc *)0)->sc_bus)))) 68 69#define MUSBOTG_PC2SC(pc) \ 70 MUSBOTG_BUS2SC((pc)->tag_parent->info->bus) 71 72#if USB_DEBUG 73static int musbotgdebug = 0; 74 75SYSCTL_NODE(_hw_usb2, OID_AUTO, musbotg, CTLFLAG_RW, 0, "USB musbotg"); 76SYSCTL_INT(_hw_usb2_musbotg, OID_AUTO, debug, CTLFLAG_RW, 77 &musbotgdebug, 0, "Debug level"); 78#endif 79 80/* prototypes */ 81 82struct usb2_bus_methods musbotg_bus_methods; 83struct usb2_pipe_methods musbotg_device_bulk_methods; 84struct usb2_pipe_methods musbotg_device_ctrl_methods; 85struct usb2_pipe_methods musbotg_device_intr_methods; 86struct usb2_pipe_methods musbotg_device_isoc_methods; 87struct usb2_pipe_methods musbotg_root_ctrl_methods; 88struct usb2_pipe_methods musbotg_root_intr_methods; 89 90static musbotg_cmd_t musbotg_setup_rx; 91static musbotg_cmd_t musbotg_setup_data_rx; 92static musbotg_cmd_t musbotg_setup_data_tx; 93static musbotg_cmd_t musbotg_setup_status; 94static musbotg_cmd_t musbotg_data_rx; 95static musbotg_cmd_t musbotg_data_tx; 96static void musbotg_device_done(struct usb2_xfer *, usb2_error_t); 97static void musbotg_do_poll(struct usb2_bus *); 98static void musbotg_root_ctrl_poll(struct musbotg_softc *); 99static void musbotg_standard_done(struct usb2_xfer *); 100static void musbotg_interrupt_poll(struct musbotg_softc *); 101 102static usb2_sw_transfer_func_t musbotg_root_intr_done; 103static usb2_sw_transfer_func_t musbotg_root_ctrl_done; 104static usb2_config_td_command_t musbotg_root_ctrl_task; 105 106/* 107 * Here is a configuration that the chip supports. 108 */ 109static const struct usb2_hw_ep_profile musbotg_ep_profile[1] = { 110 111 [0] = { 112 .max_in_frame_size = 64,/* fixed */ 113 .max_out_frame_size = 64, /* fixed */ 114 .is_simplex = 1, 115 .support_control = 1, 116 } 117}; 118 119static void 120musbotg_get_hw_ep_profile(struct usb2_device *udev, 121 const struct usb2_hw_ep_profile **ppf, uint8_t ep_addr) 122{ 123 struct musbotg_softc *sc; 124 125 sc = MUSBOTG_BUS2SC(udev->bus); 126 127 if (ep_addr == 0) { 128 /* control endpoint */ 129 *ppf = musbotg_ep_profile; 130 } else if (ep_addr <= sc->sc_ep_max) { 131 /* other endpoints */ 132 *ppf = sc->sc_hw_ep_profile + ep_addr; 133 } else { 134 *ppf = NULL; 135 } 136} 137 138static void 139musbotg_clocks_on(struct musbotg_softc *sc) 140{ 141 if (sc->sc_flags.clocks_off && 142 sc->sc_flags.port_powered) { 143 144 DPRINTFN(4, "\n"); 145 146 if (sc->sc_clocks_on) { 147 (sc->sc_clocks_on) (sc->sc_clocks_arg); 148 } 149 sc->sc_flags.clocks_off = 0; 150 151 /* XXX enable Transceiver */ 152 } 153} 154 155static void 156musbotg_clocks_off(struct musbotg_softc *sc) 157{ 158 if (!sc->sc_flags.clocks_off) { 159 160 DPRINTFN(4, "\n"); 161 162 /* XXX disable Transceiver */ 163 164 if (sc->sc_clocks_off) { 165 (sc->sc_clocks_off) (sc->sc_clocks_arg); 166 } 167 sc->sc_flags.clocks_off = 1; 168 } 169} 170 171static void 172musbotg_pull_common(struct musbotg_softc *sc, uint8_t on) 173{ 174 uint8_t temp; 175 176 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER); 177 if (on) 178 temp |= MUSB2_MASK_SOFTC; 179 else 180 temp &= ~MUSB2_MASK_SOFTC; 181 182 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp); 183} 184 185static void 186musbotg_pull_up(struct musbotg_softc *sc) 187{ 188 /* pullup D+, if possible */ 189 190 if (!sc->sc_flags.d_pulled_up && 191 sc->sc_flags.port_powered) { 192 sc->sc_flags.d_pulled_up = 1; 193 musbotg_pull_common(sc, 1); 194 } 195} 196 197static void 198musbotg_pull_down(struct musbotg_softc *sc) 199{ 200 /* pulldown D+, if possible */ 201 202 if (sc->sc_flags.d_pulled_up) { 203 sc->sc_flags.d_pulled_up = 0; 204 musbotg_pull_common(sc, 0); 205 } 206} 207 208static void 209musbotg_wakeup_peer(struct usb2_xfer *xfer) 210{ 211 struct musbotg_softc *sc = xfer->usb2_sc; 212 uint8_t temp; 213 uint8_t use_polling; 214 215 if (!(sc->sc_flags.status_suspend)) { 216 return; 217 } 218 use_polling = mtx_owned(xfer->xfer_mtx) ? 1 : 0; 219 220 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER); 221 temp |= MUSB2_MASK_RESUME; 222 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp); 223 224 /* wait 8 milliseconds */ 225 if (use_polling) { 226 /* polling */ 227 DELAY(8000); 228 } else { 229 /* Wait for reset to complete. */ 230 usb2_pause_mtx(&sc->sc_bus.bus_mtx, 8); 231 } 232 233 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER); 234 temp &= ~MUSB2_MASK_RESUME; 235 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp); 236} 237 238static void 239musbotg_set_address(struct musbotg_softc *sc, uint8_t addr) 240{ 241 DPRINTFN(4, "addr=%d\n", addr); 242 addr &= 0x7F; 243 MUSB2_WRITE_1(sc, MUSB2_REG_FADDR, addr); 244} 245 246static uint8_t 247musbotg_setup_rx(struct musbotg_td *td) 248{ 249 struct musbotg_softc *sc; 250 struct usb2_device_request req; 251 uint16_t count; 252 uint8_t csr; 253 254 /* get pointer to softc */ 255 sc = MUSBOTG_PC2SC(td->pc); 256 257 /* select endpoint 0 */ 258 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); 259 260 /* read out FIFO status */ 261 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 262 263 DPRINTFN(4, "csr=0x%02x\n", csr); 264 265 /* 266 * NOTE: If DATAEND is set we should not call the 267 * callback, hence the status stage is not complete. 268 */ 269 if (csr & MUSB2_MASK_CSR0L_DATAEND) { 270 /* wait for interrupt */ 271 goto not_complete; 272 } 273 if (csr & MUSB2_MASK_CSR0L_SENTSTALL) { 274 /* clear SENTSTALL */ 275 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0); 276 /* get latest status */ 277 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 278 /* update EP0 state */ 279 sc->sc_ep0_busy = 0; 280 } 281 if (csr & MUSB2_MASK_CSR0L_SETUPEND) { 282 /* clear SETUPEND */ 283 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 284 MUSB2_MASK_CSR0L_SETUPEND_CLR); 285 /* get latest status */ 286 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 287 /* update EP0 state */ 288 sc->sc_ep0_busy = 0; 289 } 290 if (sc->sc_ep0_busy) { 291 /* abort any ongoing transfer */ 292 if (!td->did_stall) { 293 DPRINTFN(4, "stalling\n"); 294 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 295 MUSB2_MASK_CSR0L_SENDSTALL); 296 td->did_stall = 1; 297 } 298 goto not_complete; 299 } 300 if (!(csr & MUSB2_MASK_CSR0L_RXPKTRDY)) { 301 goto not_complete; 302 } 303 /* get the packet byte count */ 304 count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT); 305 306 /* verify data length */ 307 if (count != td->remainder) { 308 DPRINTFN(0, "Invalid SETUP packet " 309 "length, %d bytes\n", count); 310 goto not_complete; 311 } 312 if (count != sizeof(req)) { 313 DPRINTFN(0, "Unsupported SETUP packet " 314 "length, %d bytes\n", count); 315 goto not_complete; 316 } 317 /* receive data */ 318 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 319 MUSB2_REG_EPFIFO(0), (void *)&req, sizeof(req)); 320 321 /* copy data into real buffer */ 322 usb2_copy_in(td->pc, 0, &req, sizeof(req)); 323 324 td->offset = sizeof(req); 325 td->remainder = 0; 326 327 /* set pending command */ 328 sc->sc_ep0_cmd = MUSB2_MASK_CSR0L_RXPKTRDY_CLR; 329 330 /* we need set stall or dataend after this */ 331 sc->sc_ep0_busy = 1; 332 333 /* sneak peek the set address */ 334 if ((req.bmRequestType == UT_WRITE_DEVICE) && 335 (req.bRequest == UR_SET_ADDRESS)) { 336 sc->sc_dv_addr = req.wValue[0] & 0x7F; 337 } else { 338 sc->sc_dv_addr = 0xFF; 339 } 340 return (0); /* complete */ 341 342not_complete: 343 return (1); /* not complete */ 344} 345 346/* Control endpoint only data handling functions (RX/TX/SYNC) */ 347 348static uint8_t 349musbotg_setup_data_rx(struct musbotg_td *td) 350{ 351 struct usb2_page_search buf_res; 352 struct musbotg_softc *sc; 353 uint16_t count; 354 uint8_t csr; 355 uint8_t got_short; 356 357 /* get pointer to softc */ 358 sc = MUSBOTG_PC2SC(td->pc); 359 360 /* select endpoint 0 */ 361 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); 362 363 /* check if a command is pending */ 364 if (sc->sc_ep0_cmd) { 365 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, sc->sc_ep0_cmd); 366 sc->sc_ep0_cmd = 0; 367 } 368 /* read out FIFO status */ 369 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 370 371 DPRINTFN(4, "csr=0x%02x\n", csr); 372 373 got_short = 0; 374 375 if (csr & (MUSB2_MASK_CSR0L_SETUPEND | 376 MUSB2_MASK_CSR0L_SENTSTALL)) { 377 if (td->remainder == 0) { 378 /* 379 * We are actually complete and have 380 * received the next SETUP 381 */ 382 DPRINTFN(4, "faking complete\n"); 383 return (0); /* complete */ 384 } 385 /* 386 * USB Host Aborted the transfer. 387 */ 388 td->error = 1; 389 return (0); /* complete */ 390 } 391 if (!(csr & MUSB2_MASK_CSR0L_RXPKTRDY)) { 392 return (1); /* not complete */ 393 } 394 /* get the packet byte count */ 395 count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT); 396 397 /* verify the packet byte count */ 398 if (count != td->max_frame_size) { 399 if (count < td->max_frame_size) { 400 /* we have a short packet */ 401 td->short_pkt = 1; 402 got_short = 1; 403 } else { 404 /* invalid USB packet */ 405 td->error = 1; 406 return (0); /* we are complete */ 407 } 408 } 409 /* verify the packet byte count */ 410 if (count > td->remainder) { 411 /* invalid USB packet */ 412 td->error = 1; 413 return (0); /* we are complete */ 414 } 415 while (count > 0) { 416 uint32_t temp; 417 418 usb2_get_page(td->pc, td->offset, &buf_res); 419 420 /* get correct length */ 421 if (buf_res.length > count) { 422 buf_res.length = count; 423 } 424 /* check for unaligned memory address */ 425 if (USB_P2U(buf_res.buffer) & 3) { 426 427 temp = count & ~3; 428 429 if (temp) { 430 /* receive data 4 bytes at a time */ 431 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 432 MUSB2_REG_EPFIFO(0), sc->sc_bounce_buf, 433 temp / 4); 434 } 435 temp = count & 3; 436 if (temp) { 437 /* receive data 1 byte at a time */ 438 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 439 MUSB2_REG_EPFIFO(0), 440 (void *)(&sc->sc_bounce_buf[count / 4]), temp); 441 } 442 usb2_copy_in(td->pc, td->offset, 443 sc->sc_bounce_buf, count); 444 445 /* update offset and remainder */ 446 td->offset += count; 447 td->remainder -= count; 448 break; 449 } 450 /* check if we can optimise */ 451 if (buf_res.length >= 4) { 452 453 /* receive data 4 bytes at a time */ 454 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 455 MUSB2_REG_EPFIFO(0), buf_res.buffer, 456 buf_res.length / 4); 457 458 temp = buf_res.length & ~3; 459 460 /* update counters */ 461 count -= temp; 462 td->offset += temp; 463 td->remainder -= temp; 464 continue; 465 } 466 /* receive data */ 467 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 468 MUSB2_REG_EPFIFO(0), buf_res.buffer, buf_res.length); 469 470 /* update counters */ 471 count -= buf_res.length; 472 td->offset += buf_res.length; 473 td->remainder -= buf_res.length; 474 } 475 476 /* check if we are complete */ 477 if ((td->remainder == 0) || got_short) { 478 if (td->short_pkt) { 479 /* we are complete */ 480 sc->sc_ep0_cmd = MUSB2_MASK_CSR0L_RXPKTRDY_CLR; 481 return (0); 482 } 483 /* else need to receive a zero length packet */ 484 } 485 /* write command - need more data */ 486 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 487 MUSB2_MASK_CSR0L_RXPKTRDY_CLR); 488 return (1); /* not complete */ 489} 490 491static uint8_t 492musbotg_setup_data_tx(struct musbotg_td *td) 493{ 494 struct usb2_page_search buf_res; 495 struct musbotg_softc *sc; 496 uint16_t count; 497 uint8_t csr; 498 499 /* get pointer to softc */ 500 sc = MUSBOTG_PC2SC(td->pc); 501 502 /* select endpoint 0 */ 503 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); 504 505 /* check if a command is pending */ 506 if (sc->sc_ep0_cmd) { 507 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, sc->sc_ep0_cmd); 508 sc->sc_ep0_cmd = 0; 509 } 510 /* read out FIFO status */ 511 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 512 513 DPRINTFN(4, "csr=0x%02x\n", csr); 514 515 if (csr & (MUSB2_MASK_CSR0L_SETUPEND | 516 MUSB2_MASK_CSR0L_SENTSTALL)) { 517 /* 518 * The current transfer was aborted 519 * by the USB Host 520 */ 521 td->error = 1; 522 return (0); /* complete */ 523 } 524 if (csr & MUSB2_MASK_CSR0L_TXPKTRDY) { 525 return (1); /* not complete */ 526 } 527 count = td->max_frame_size; 528 if (td->remainder < count) { 529 /* we have a short packet */ 530 td->short_pkt = 1; 531 count = td->remainder; 532 } 533 while (count > 0) { 534 uint32_t temp; 535 536 usb2_get_page(td->pc, td->offset, &buf_res); 537 538 /* get correct length */ 539 if (buf_res.length > count) { 540 buf_res.length = count; 541 } 542 /* check for unaligned memory address */ 543 if (USB_P2U(buf_res.buffer) & 3) { 544 545 usb2_copy_out(td->pc, td->offset, 546 sc->sc_bounce_buf, count); 547 548 temp = count & ~3; 549 550 if (temp) { 551 /* transmit data 4 bytes at a time */ 552 bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 553 MUSB2_REG_EPFIFO(0), sc->sc_bounce_buf, 554 temp / 4); 555 } 556 temp = count & 3; 557 if (temp) { 558 /* receive data 1 byte at a time */ 559 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 560 MUSB2_REG_EPFIFO(0), 561 ((void *)&sc->sc_bounce_buf[count / 4]), temp); 562 } 563 /* update offset and remainder */ 564 td->offset += count; 565 td->remainder -= count; 566 break; 567 } 568 /* check if we can optimise */ 569 if (buf_res.length >= 4) { 570 571 /* transmit data 4 bytes at a time */ 572 bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 573 MUSB2_REG_EPFIFO(0), buf_res.buffer, 574 buf_res.length / 4); 575 576 temp = buf_res.length & ~3; 577 578 /* update counters */ 579 count -= temp; 580 td->offset += temp; 581 td->remainder -= temp; 582 continue; 583 } 584 /* transmit data */ 585 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 586 MUSB2_REG_EPFIFO(0), buf_res.buffer, buf_res.length); 587 588 /* update counters */ 589 count -= buf_res.length; 590 td->offset += buf_res.length; 591 td->remainder -= buf_res.length; 592 } 593 594 /* check remainder */ 595 if (td->remainder == 0) { 596 if (td->short_pkt) { 597 sc->sc_ep0_cmd = MUSB2_MASK_CSR0L_TXPKTRDY; 598 return (0); /* complete */ 599 } 600 /* else we need to transmit a short packet */ 601 } 602 /* write command */ 603 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 604 MUSB2_MASK_CSR0L_TXPKTRDY); 605 606 return (1); /* not complete */ 607} 608 609static uint8_t 610musbotg_setup_status(struct musbotg_td *td) 611{ 612 struct musbotg_softc *sc; 613 uint8_t csr; 614 615 /* get pointer to softc */ 616 sc = MUSBOTG_PC2SC(td->pc); 617 618 /* select endpoint 0 */ 619 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); 620 621 if (sc->sc_ep0_busy) { 622 sc->sc_ep0_busy = 0; 623 sc->sc_ep0_cmd |= MUSB2_MASK_CSR0L_DATAEND; 624 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, sc->sc_ep0_cmd); 625 sc->sc_ep0_cmd = 0; 626 } 627 /* read out FIFO status */ 628 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 629 630 DPRINTFN(4, "csr=0x%02x\n", csr); 631 632 if (csr & MUSB2_MASK_CSR0L_DATAEND) { 633 /* wait for interrupt */ 634 return (1); /* not complete */ 635 } 636 if (sc->sc_dv_addr != 0xFF) { 637 /* write function address */ 638 musbotg_set_address(sc, sc->sc_dv_addr); 639 } 640 return (0); /* complete */ 641} 642 643static uint8_t 644musbotg_data_rx(struct musbotg_td *td) 645{ 646 struct usb2_page_search buf_res; 647 struct musbotg_softc *sc; 648 uint16_t count; 649 uint8_t csr; 650 uint8_t to; 651 uint8_t got_short; 652 653 to = 8; /* don't loop forever! */ 654 got_short = 0; 655 656 /* get pointer to softc */ 657 sc = MUSBOTG_PC2SC(td->pc); 658 659 /* select endpoint */ 660 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, td->ep_no); 661 662repeat: 663 /* read out FIFO status */ 664 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL); 665 666 DPRINTFN(4, "csr=0x%02x\n", csr); 667 668 /* clear overrun */ 669 if (csr & MUSB2_MASK_CSRL_RXOVERRUN) { 670 /* make sure we don't clear "RXPKTRDY" */ 671 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 672 MUSB2_MASK_CSRL_RXPKTRDY); 673 } 674 /* check status */ 675 if (!(csr & MUSB2_MASK_CSRL_RXPKTRDY)) { 676 return (1); /* not complete */ 677 } 678 /* get the packet byte count */ 679 count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT); 680 681 DPRINTFN(4, "count=0x%04x\n", count); 682 683 /* 684 * Check for short or invalid packet: 685 */ 686 if (count != td->max_frame_size) { 687 if (count < td->max_frame_size) { 688 /* we have a short packet */ 689 td->short_pkt = 1; 690 got_short = 1; 691 } else { 692 /* invalid USB packet */ 693 td->error = 1; 694 return (0); /* we are complete */ 695 } 696 } 697 /* verify the packet byte count */ 698 if (count > td->remainder) { 699 /* invalid USB packet */ 700 td->error = 1; 701 return (0); /* we are complete */ 702 } 703 while (count > 0) { 704 uint32_t temp; 705 706 usb2_get_page(td->pc, td->offset, &buf_res); 707 708 /* get correct length */ 709 if (buf_res.length > count) { 710 buf_res.length = count; 711 } 712 /* check for unaligned memory address */ 713 if (USB_P2U(buf_res.buffer) & 3) { 714 715 temp = count & ~3; 716 717 if (temp) { 718 /* receive data 4 bytes at a time */ 719 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 720 MUSB2_REG_EPFIFO(td->ep_no), sc->sc_bounce_buf, 721 temp / 4); 722 } 723 temp = count & 3; 724 if (temp) { 725 /* receive data 1 byte at a time */ 726 bus_space_read_multi_1(sc->sc_io_tag, 727 sc->sc_io_hdl, MUSB2_REG_EPFIFO(td->ep_no), 728 ((void *)&sc->sc_bounce_buf[count / 4]), temp); 729 } 730 usb2_copy_in(td->pc, td->offset, 731 sc->sc_bounce_buf, count); 732 733 /* update offset and remainder */ 734 td->offset += count; 735 td->remainder -= count; 736 break; 737 } 738 /* check if we can optimise */ 739 if (buf_res.length >= 4) { 740 741 /* receive data 4 bytes at a time */ 742 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 743 MUSB2_REG_EPFIFO(td->ep_no), buf_res.buffer, 744 buf_res.length / 4); 745 746 temp = buf_res.length & ~3; 747 748 /* update counters */ 749 count -= temp; 750 td->offset += temp; 751 td->remainder -= temp; 752 continue; 753 } 754 /* receive data */ 755 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 756 MUSB2_REG_EPFIFO(td->ep_no), buf_res.buffer, 757 buf_res.length); 758 759 /* update counters */ 760 count -= buf_res.length; 761 td->offset += buf_res.length; 762 td->remainder -= buf_res.length; 763 } 764 765 /* clear status bits */ 766 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 0); 767 768 /* check if we are complete */ 769 if ((td->remainder == 0) || got_short) { 770 if (td->short_pkt) { 771 /* we are complete */ 772 return (0); 773 } 774 /* else need to receive a zero length packet */ 775 } 776 if (--to) { 777 goto repeat; 778 } 779 return (1); /* not complete */ 780} 781 782static uint8_t 783musbotg_data_tx(struct musbotg_td *td) 784{ 785 struct usb2_page_search buf_res; 786 struct musbotg_softc *sc; 787 uint16_t count; 788 uint8_t csr; 789 uint8_t to; 790 791 to = 8; /* don't loop forever! */ 792 793 /* get pointer to softc */ 794 sc = MUSBOTG_PC2SC(td->pc); 795 796 /* select endpoint */ 797 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, td->ep_no); 798 799repeat: 800 801 /* read out FIFO status */ 802 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 803 804 DPRINTFN(4, "csr=0x%02x\n", csr); 805 806 if (csr & (MUSB2_MASK_CSRL_TXINCOMP | 807 MUSB2_MASK_CSRL_TXUNDERRUN)) { 808 /* clear status bits */ 809 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0); 810 } 811 if (csr & MUSB2_MASK_CSRL_TXPKTRDY) { 812 return (1); /* not complete */ 813 } 814 /* check for short packet */ 815 count = td->max_frame_size; 816 if (td->remainder < count) { 817 /* we have a short packet */ 818 td->short_pkt = 1; 819 count = td->remainder; 820 } 821 while (count > 0) { 822 uint32_t temp; 823 824 usb2_get_page(td->pc, td->offset, &buf_res); 825 826 /* get correct length */ 827 if (buf_res.length > count) { 828 buf_res.length = count; 829 } 830 /* check for unaligned memory address */ 831 if (USB_P2U(buf_res.buffer) & 3) { 832 833 usb2_copy_out(td->pc, td->offset, 834 sc->sc_bounce_buf, count); 835 836 temp = count & ~3; 837 838 if (temp) { 839 /* transmit data 4 bytes at a time */ 840 bus_space_write_multi_4(sc->sc_io_tag, 841 sc->sc_io_hdl, MUSB2_REG_EPFIFO(td->ep_no), 842 sc->sc_bounce_buf, temp / 4); 843 } 844 temp = count & 3; 845 if (temp) { 846 /* receive data 1 byte at a time */ 847 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 848 MUSB2_REG_EPFIFO(td->ep_no), 849 ((void *)&sc->sc_bounce_buf[count / 4]), temp); 850 } 851 /* update offset and remainder */ 852 td->offset += count; 853 td->remainder -= count; 854 break; 855 } 856 /* check if we can optimise */ 857 if (buf_res.length >= 4) { 858 859 /* transmit data 4 bytes at a time */ 860 bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 861 MUSB2_REG_EPFIFO(td->ep_no), buf_res.buffer, 862 buf_res.length / 4); 863 864 temp = buf_res.length & ~3; 865 866 /* update counters */ 867 count -= temp; 868 td->offset += temp; 869 td->remainder -= temp; 870 continue; 871 } 872 /* transmit data */ 873 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 874 MUSB2_REG_EPFIFO(td->ep_no), buf_res.buffer, 875 buf_res.length); 876 877 /* update counters */ 878 count -= buf_res.length; 879 td->offset += buf_res.length; 880 td->remainder -= buf_res.length; 881 } 882 883 /* write command */ 884 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 885 MUSB2_MASK_CSRL_TXPKTRDY); 886 887 /* check remainder */ 888 if (td->remainder == 0) { 889 if (td->short_pkt) { 890 return (0); /* complete */ 891 } 892 /* else we need to transmit a short packet */ 893 } 894 if (--to) { 895 goto repeat; 896 } 897 return (1); /* not complete */ 898} 899 900static uint8_t 901musbotg_xfer_do_fifo(struct usb2_xfer *xfer) 902{ 903 struct musbotg_softc *sc; 904 struct musbotg_td *td; 905 906 DPRINTFN(8, "\n"); 907 908 td = xfer->td_transfer_cache; 909 while (1) { 910 if ((td->func) (td)) { 911 /* operation in progress */ 912 break; 913 } 914 if (((void *)td) == xfer->td_transfer_last) { 915 goto done; 916 } 917 if (td->error) { 918 goto done; 919 } else if (td->remainder > 0) { 920 /* 921 * We had a short transfer. If there is no alternate 922 * next, stop processing ! 923 */ 924 if (!td->alt_next) { 925 goto done; 926 } 927 } 928 /* 929 * Fetch the next transfer descriptor and transfer 930 * some flags to the next transfer descriptor 931 */ 932 td = td->obj_next; 933 xfer->td_transfer_cache = td; 934 } 935 return (1); /* not complete */ 936 937done: 938 sc = xfer->usb2_sc; 939 940 /* compute all actual lengths */ 941 942 musbotg_standard_done(xfer); 943 944 return (0); /* complete */ 945} 946 947static void 948musbotg_interrupt_poll(struct musbotg_softc *sc) 949{ 950 struct usb2_xfer *xfer; 951 952repeat: 953 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 954 if (!musbotg_xfer_do_fifo(xfer)) { 955 /* queue has been modified */ 956 goto repeat; 957 } 958 } 959} 960 961static void 962musbotg_vbus_interrupt(struct usb2_bus *bus, uint8_t is_on) 963{ 964 struct musbotg_softc *sc = MUSBOTG_BUS2SC(bus); 965 966 DPRINTFN(4, "vbus = %u\n", is_on); 967 968 USB_BUS_LOCK(&sc->sc_bus); 969 if (is_on) { 970 if (!sc->sc_flags.status_vbus) { 971 sc->sc_flags.status_vbus = 1; 972 973 /* complete root HUB interrupt endpoint */ 974 975 usb2_sw_transfer(&sc->sc_root_intr, 976 &musbotg_root_intr_done); 977 } 978 } else { 979 if (sc->sc_flags.status_vbus) { 980 sc->sc_flags.status_vbus = 0; 981 sc->sc_flags.status_bus_reset = 0; 982 sc->sc_flags.status_suspend = 0; 983 sc->sc_flags.change_suspend = 0; 984 sc->sc_flags.change_connect = 1; 985 986 /* complete root HUB interrupt endpoint */ 987 988 usb2_sw_transfer(&sc->sc_root_intr, 989 &musbotg_root_intr_done); 990 } 991 } 992 993 USB_BUS_UNLOCK(&sc->sc_bus); 994} 995 996void 997musbotg_interrupt(struct musbotg_softc *sc) 998{ 999 uint16_t rx_status; 1000 uint16_t tx_status; 1001 uint8_t usb_status; 1002 uint8_t temp; 1003 uint8_t to = 2; 1004 1005 USB_BUS_LOCK(&sc->sc_bus); 1006 1007repeat: 1008 1009 /* read all interrupt registers */ 1010 usb_status = MUSB2_READ_1(sc, MUSB2_REG_INTUSB); 1011 1012 /* read all FIFO interrupts */ 1013 rx_status = MUSB2_READ_2(sc, MUSB2_REG_INTRX); 1014 tx_status = MUSB2_READ_2(sc, MUSB2_REG_INTTX); 1015 1016 /* check for any bus state change interrupts */ 1017 1018 if (usb_status & (MUSB2_MASK_IRESET | 1019 MUSB2_MASK_IRESUME | MUSB2_MASK_ISUSP)) { 1020 1021 DPRINTFN(4, "real bus interrupt 0x%08x\n", usb_status); 1022 1023 if (usb_status & MUSB2_MASK_IRESET) { 1024 1025 /* set correct state */ 1026 sc->sc_flags.status_bus_reset = 1; 1027 sc->sc_flags.status_suspend = 0; 1028 sc->sc_flags.change_suspend = 0; 1029 sc->sc_flags.change_connect = 1; 1030 1031 /* determine line speed */ 1032 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER); 1033 if (temp & MUSB2_MASK_HSMODE) 1034 sc->sc_flags.status_high_speed = 1; 1035 else 1036 sc->sc_flags.status_high_speed = 0; 1037 1038 /* 1039 * After reset all interrupts are on and we need to 1040 * turn them off! 1041 */ 1042 temp = MUSB2_MASK_IRESET; 1043 /* disable resume interrupt */ 1044 temp &= ~MUSB2_MASK_IRESUME; 1045 /* enable suspend interrupt */ 1046 temp |= MUSB2_MASK_ISUSP; 1047 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, temp); 1048 /* disable TX and RX interrupts */ 1049 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, 0); 1050 MUSB2_WRITE_2(sc, MUSB2_REG_INTRXE, 0); 1051 } 1052 /* 1053 * If RXRSM and RXSUSP is set at the same time we interpret 1054 * that like RESUME. Resume is set when there is at least 3 1055 * milliseconds of inactivity on the USB BUS. 1056 */ 1057 if (usb_status & MUSB2_MASK_IRESUME) { 1058 if (sc->sc_flags.status_suspend) { 1059 sc->sc_flags.status_suspend = 0; 1060 sc->sc_flags.change_suspend = 1; 1061 1062 temp = MUSB2_READ_1(sc, MUSB2_REG_INTUSBE); 1063 /* disable resume interrupt */ 1064 temp &= ~MUSB2_MASK_IRESUME; 1065 /* enable suspend interrupt */ 1066 temp |= MUSB2_MASK_ISUSP; 1067 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, temp); 1068 } 1069 } else if (usb_status & MUSB2_MASK_ISUSP) { 1070 if (!sc->sc_flags.status_suspend) { 1071 sc->sc_flags.status_suspend = 1; 1072 sc->sc_flags.change_suspend = 1; 1073 1074 temp = MUSB2_READ_1(sc, MUSB2_REG_INTUSBE); 1075 /* disable suspend interrupt */ 1076 temp &= ~MUSB2_MASK_ISUSP; 1077 /* enable resume interrupt */ 1078 temp |= MUSB2_MASK_IRESUME; 1079 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, temp); 1080 } 1081 } 1082 /* complete root HUB interrupt endpoint */ 1083 1084 usb2_sw_transfer(&sc->sc_root_intr, 1085 &musbotg_root_intr_done); 1086 } 1087 /* check for any endpoint interrupts */ 1088 1089 if (rx_status || tx_status) { 1090 DPRINTFN(4, "real endpoint interrupt " 1091 "rx=0x%04x, tx=0x%04x\n", rx_status, tx_status); 1092 } 1093 /* poll one time regardless of FIFO status */ 1094 1095 musbotg_interrupt_poll(sc); 1096 1097 if (--to) 1098 goto repeat; 1099 1100 USB_BUS_UNLOCK(&sc->sc_bus); 1101} 1102 1103static void 1104musbotg_setup_standard_chain_sub(struct musbotg_std_temp *temp) 1105{ 1106 struct musbotg_td *td; 1107 1108 /* get current Transfer Descriptor */ 1109 td = temp->td_next; 1110 temp->td = td; 1111 1112 /* prepare for next TD */ 1113 temp->td_next = td->obj_next; 1114 1115 /* fill out the Transfer Descriptor */ 1116 td->func = temp->func; 1117 td->pc = temp->pc; 1118 td->offset = temp->offset; 1119 td->remainder = temp->len; 1120 td->error = 0; 1121 td->did_stall = 0; 1122 td->short_pkt = temp->short_pkt; 1123 td->alt_next = temp->setup_alt_next; 1124} 1125 1126static void 1127musbotg_setup_standard_chain(struct usb2_xfer *xfer) 1128{ 1129 struct musbotg_std_temp temp; 1130 struct musbotg_softc *sc; 1131 struct musbotg_td *td; 1132 uint32_t x; 1133 uint8_t ep_no; 1134 1135 DPRINTFN(8, "addr=%d endpt=%d sumlen=%d speed=%d\n", 1136 xfer->address, UE_GET_ADDR(xfer->endpoint), 1137 xfer->sumlen, usb2_get_speed(xfer->udev)); 1138 1139 temp.max_frame_size = xfer->max_frame_size; 1140 1141 td = xfer->td_start[0]; 1142 xfer->td_transfer_first = td; 1143 xfer->td_transfer_cache = td; 1144 1145 /* setup temp */ 1146 1147 temp.td = NULL; 1148 temp.td_next = xfer->td_start[0]; 1149 temp.setup_alt_next = xfer->flags_int.short_frames_ok; 1150 temp.offset = 0; 1151 1152 sc = xfer->usb2_sc; 1153 ep_no = (xfer->endpoint & UE_ADDR); 1154 1155 /* check if we should prepend a setup message */ 1156 1157 if (xfer->flags_int.control_xfr) { 1158 if (xfer->flags_int.control_hdr) { 1159 1160 temp.func = &musbotg_setup_rx; 1161 temp.len = xfer->frlengths[0]; 1162 temp.pc = xfer->frbuffers + 0; 1163 temp.short_pkt = temp.len ? 1 : 0; 1164 1165 musbotg_setup_standard_chain_sub(&temp); 1166 } 1167 x = 1; 1168 } else { 1169 x = 0; 1170 } 1171 1172 if (x != xfer->nframes) { 1173 if (xfer->endpoint & UE_DIR_IN) { 1174 if (xfer->flags_int.control_xfr) 1175 temp.func = &musbotg_setup_data_tx; 1176 else 1177 temp.func = &musbotg_data_tx; 1178 } else { 1179 if (xfer->flags_int.control_xfr) 1180 temp.func = &musbotg_setup_data_rx; 1181 else 1182 temp.func = &musbotg_data_rx; 1183 } 1184 1185 /* setup "pc" pointer */ 1186 temp.pc = xfer->frbuffers + x; 1187 } 1188 while (x != xfer->nframes) { 1189 1190 /* DATA0 / DATA1 message */ 1191 1192 temp.len = xfer->frlengths[x]; 1193 1194 x++; 1195 1196 if (x == xfer->nframes) { 1197 temp.setup_alt_next = 0; 1198 } 1199 if (temp.len == 0) { 1200 1201 /* make sure that we send an USB packet */ 1202 1203 temp.short_pkt = 0; 1204 1205 } else { 1206 1207 /* regular data transfer */ 1208 1209 temp.short_pkt = (xfer->flags.force_short_xfer) ? 0 : 1; 1210 } 1211 1212 musbotg_setup_standard_chain_sub(&temp); 1213 1214 if (xfer->flags_int.isochronous_xfr) { 1215 temp.offset += temp.len; 1216 } else { 1217 /* get next Page Cache pointer */ 1218 temp.pc = xfer->frbuffers + x; 1219 } 1220 } 1221 1222 /* always setup a valid "pc" pointer for status and sync */ 1223 temp.pc = xfer->frbuffers + 0; 1224 1225 /* check if we should append a status stage */ 1226 1227 if (xfer->flags_int.control_xfr && 1228 !xfer->flags_int.control_act) { 1229 1230 /* 1231 * Send a DATA1 message and invert the current 1232 * endpoint direction. 1233 */ 1234 temp.func = &musbotg_setup_status; 1235 temp.len = 0; 1236 temp.short_pkt = 0; 1237 1238 musbotg_setup_standard_chain_sub(&temp); 1239 } 1240 /* must have at least one frame! */ 1241 td = temp.td; 1242 xfer->td_transfer_last = td; 1243} 1244 1245static void 1246musbotg_timeout(void *arg) 1247{ 1248 struct usb2_xfer *xfer = arg; 1249 1250 DPRINTFN(1, "xfer=%p\n", xfer); 1251 1252 USB_BUS_LOCK_ASSERT(xfer->udev->bus, MA_OWNED); 1253 1254 /* transfer is transferred */ 1255 musbotg_device_done(xfer, USB_ERR_TIMEOUT); 1256} 1257 1258static void 1259musbotg_ep_int_set(struct usb2_xfer *xfer, uint8_t on) 1260{ 1261 struct musbotg_softc *sc = xfer->usb2_sc; 1262 uint16_t temp; 1263 uint8_t ep_no = xfer->endpoint & UE_ADDR; 1264 1265 /* 1266 * Only enable the endpoint interrupt when we are 1267 * actually waiting for data, hence we are dealing 1268 * with level triggered interrupts ! 1269 */ 1270 if (ep_no == 0) { 1271 temp = MUSB2_READ_2(sc, MUSB2_REG_INTTXE); 1272 if (on) 1273 temp |= MUSB2_MASK_EPINT(0); 1274 else 1275 temp &= ~MUSB2_MASK_EPINT(0); 1276 1277 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, temp); 1278 } else { 1279 if (USB_GET_DATA_ISREAD(xfer)) { 1280 temp = MUSB2_READ_2(sc, MUSB2_REG_INTRXE); 1281 if (on) 1282 temp |= MUSB2_MASK_EPINT(ep_no); 1283 else 1284 temp &= ~MUSB2_MASK_EPINT(ep_no); 1285 MUSB2_WRITE_2(sc, MUSB2_REG_INTRXE, temp); 1286 1287 } else { 1288 temp = MUSB2_READ_2(sc, MUSB2_REG_INTTXE); 1289 if (on) 1290 temp |= MUSB2_MASK_EPINT(ep_no); 1291 else 1292 temp &= ~MUSB2_MASK_EPINT(ep_no); 1293 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, temp); 1294 } 1295 } 1296} 1297 1298static void 1299musbotg_start_standard_chain(struct usb2_xfer *xfer) 1300{ 1301 DPRINTFN(8, "\n"); 1302 1303 /* poll one time */ 1304 if (musbotg_xfer_do_fifo(xfer)) { 1305 1306 musbotg_ep_int_set(xfer, 1); 1307 1308 DPRINTFN(14, "enabled interrupts on endpoint\n"); 1309 1310 /* put transfer on interrupt queue */ 1311 usb2_transfer_enqueue(&xfer->udev->bus->intr_q, xfer); 1312 1313 /* start timeout, if any */ 1314 if (xfer->timeout != 0) { 1315 usb2_transfer_timeout_ms(xfer, 1316 &musbotg_timeout, xfer->timeout); 1317 } 1318 } 1319} 1320 1321static void 1322musbotg_root_intr_done(struct usb2_xfer *xfer, 1323 struct usb2_sw_transfer *std) 1324{ 1325 struct musbotg_softc *sc = xfer->usb2_sc; 1326 1327 DPRINTFN(8, "\n"); 1328 1329 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1330 1331 if (std->state != USB_SW_TR_PRE_DATA) { 1332 if (std->state == USB_SW_TR_PRE_CALLBACK) { 1333 /* transfer transferred */ 1334 musbotg_device_done(xfer, std->err); 1335 } 1336 goto done; 1337 } 1338 /* setup buffer */ 1339 std->ptr = sc->sc_hub_idata; 1340 std->len = sizeof(sc->sc_hub_idata); 1341 1342 /* set port bit */ 1343 sc->sc_hub_idata[0] = 0x02; /* we only have one port */ 1344 1345done: 1346 return; 1347} 1348 1349static usb2_error_t 1350musbotg_standard_done_sub(struct usb2_xfer *xfer) 1351{ 1352 struct musbotg_td *td; 1353 uint32_t len; 1354 uint8_t error; 1355 1356 DPRINTFN(8, "\n"); 1357 1358 td = xfer->td_transfer_cache; 1359 1360 do { 1361 len = td->remainder; 1362 1363 if (xfer->aframes != xfer->nframes) { 1364 /* 1365 * Verify the length and subtract 1366 * the remainder from "frlengths[]": 1367 */ 1368 if (len > xfer->frlengths[xfer->aframes]) { 1369 td->error = 1; 1370 } else { 1371 xfer->frlengths[xfer->aframes] -= len; 1372 } 1373 } 1374 /* Check for transfer error */ 1375 if (td->error) { 1376 /* the transfer is finished */ 1377 error = 1; 1378 td = NULL; 1379 break; 1380 } 1381 /* Check for short transfer */ 1382 if (len > 0) { 1383 if (xfer->flags_int.short_frames_ok) { 1384 /* follow alt next */ 1385 if (td->alt_next) { 1386 td = td->obj_next; 1387 } else { 1388 td = NULL; 1389 } 1390 } else { 1391 /* the transfer is finished */ 1392 td = NULL; 1393 } 1394 error = 0; 1395 break; 1396 } 1397 td = td->obj_next; 1398 1399 /* this USB frame is complete */ 1400 error = 0; 1401 break; 1402 1403 } while (0); 1404 1405 /* update transfer cache */ 1406 1407 xfer->td_transfer_cache = td; 1408 1409 return (error ? 1410 USB_ERR_STALLED : USB_ERR_NORMAL_COMPLETION); 1411} 1412 1413static void 1414musbotg_standard_done(struct usb2_xfer *xfer) 1415{ 1416 usb2_error_t err = 0; 1417 1418 DPRINTFN(12, "xfer=%p pipe=%p transfer done\n", 1419 xfer, xfer->pipe); 1420 1421 /* reset scanner */ 1422 1423 xfer->td_transfer_cache = xfer->td_transfer_first; 1424 1425 if (xfer->flags_int.control_xfr) { 1426 1427 if (xfer->flags_int.control_hdr) { 1428 1429 err = musbotg_standard_done_sub(xfer); 1430 } 1431 xfer->aframes = 1; 1432 1433 if (xfer->td_transfer_cache == NULL) { 1434 goto done; 1435 } 1436 } 1437 while (xfer->aframes != xfer->nframes) { 1438 1439 err = musbotg_standard_done_sub(xfer); 1440 xfer->aframes++; 1441 1442 if (xfer->td_transfer_cache == NULL) { 1443 goto done; 1444 } 1445 } 1446 1447 if (xfer->flags_int.control_xfr && 1448 !xfer->flags_int.control_act) { 1449 1450 err = musbotg_standard_done_sub(xfer); 1451 } 1452done: 1453 musbotg_device_done(xfer, err); 1454} 1455 1456/*------------------------------------------------------------------------* 1457 * musbotg_device_done 1458 * 1459 * NOTE: this function can be called more than one time on the 1460 * same USB transfer! 1461 *------------------------------------------------------------------------*/ 1462static void 1463musbotg_device_done(struct usb2_xfer *xfer, usb2_error_t error) 1464{ 1465 USB_BUS_LOCK_ASSERT(xfer->udev->bus, MA_OWNED); 1466 1467 DPRINTFN(2, "xfer=%p, pipe=%p, error=%d\n", 1468 xfer, xfer->pipe, error); 1469 1470 if (xfer->flags_int.usb2_mode == USB_MODE_DEVICE) { 1471 1472 musbotg_ep_int_set(xfer, 0); 1473 1474 DPRINTFN(14, "disabled interrupts on endpoint\n"); 1475 } 1476 /* dequeue transfer and start next transfer */ 1477 usb2_transfer_done(xfer, error); 1478} 1479 1480static void 1481musbotg_set_stall(struct usb2_device *udev, struct usb2_xfer *xfer, 1482 struct usb2_pipe *pipe) 1483{ 1484 struct musbotg_softc *sc; 1485 uint8_t ep_no; 1486 1487 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 1488 1489 DPRINTFN(4, "pipe=%p\n", pipe); 1490 1491 if (xfer) { 1492 /* cancel any ongoing transfers */ 1493 musbotg_device_done(xfer, USB_ERR_STALLED); 1494 } 1495 /* set FORCESTALL */ 1496 sc = MUSBOTG_BUS2SC(udev->bus); 1497 1498 ep_no = (pipe->edesc->bEndpointAddress & UE_ADDR); 1499 1500 /* select endpoint */ 1501 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, ep_no); 1502 1503 if (pipe->edesc->bEndpointAddress & UE_DIR_IN) { 1504 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 1505 MUSB2_MASK_CSRL_TXSENDSTALL); 1506 } else { 1507 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 1508 MUSB2_MASK_CSRL_RXSENDSTALL); 1509 } 1510} 1511 1512static void 1513musbotg_clear_stall_sub(struct musbotg_softc *sc, uint16_t wMaxPacket, 1514 uint8_t ep_no, uint8_t ep_type, uint8_t ep_dir) 1515{ 1516 uint16_t mps; 1517 uint16_t temp; 1518 uint8_t csr; 1519 1520 if (ep_type == UE_CONTROL) { 1521 /* clearing stall is not needed */ 1522 return; 1523 } 1524 /* select endpoint */ 1525 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, ep_no); 1526 1527 /* compute max frame size */ 1528 mps = wMaxPacket & 0x7FF; 1529 switch ((wMaxPacket >> 11) & 3) { 1530 case 1: 1531 mps *= 2; 1532 break; 1533 case 2: 1534 mps *= 3; 1535 break; 1536 default: 1537 break; 1538 } 1539 1540 if (ep_dir == UE_DIR_IN) { 1541 1542 temp = 0; 1543 1544 /* Configure endpoint */ 1545 switch (ep_type) { 1546 case UE_INTERRUPT: 1547 MUSB2_WRITE_1(sc, MUSB2_REG_TXMAXP, wMaxPacket); 1548 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, 1549 MUSB2_MASK_CSRH_TXMODE | temp); 1550 break; 1551 case UE_ISOCHRONOUS: 1552 MUSB2_WRITE_1(sc, MUSB2_REG_TXMAXP, wMaxPacket); 1553 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, 1554 MUSB2_MASK_CSRH_TXMODE | 1555 MUSB2_MASK_CSRH_TXISO | temp); 1556 break; 1557 case UE_BULK: 1558 MUSB2_WRITE_1(sc, MUSB2_REG_TXMAXP, wMaxPacket); 1559 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, 1560 MUSB2_MASK_CSRH_TXMODE | temp); 1561 break; 1562 default: 1563 break; 1564 } 1565 1566 /* Need to flush twice in case of double bufring */ 1567 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 1568 if (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) { 1569 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 1570 MUSB2_MASK_CSRL_TXFFLUSH); 1571 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 1572 if (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) { 1573 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 1574 MUSB2_MASK_CSRL_TXFFLUSH); 1575 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 1576 } 1577 } 1578 /* reset data toggle */ 1579 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 1580 MUSB2_MASK_CSRL_TXDT_CLR); 1581 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0); 1582 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 1583 1584 /* set double/single buffering */ 1585 temp = MUSB2_READ_2(sc, MUSB2_REG_TXDBDIS); 1586 if (mps <= (sc->sc_hw_ep_profile[ep_no]. 1587 max_in_frame_size / 2)) { 1588 /* double buffer */ 1589 temp &= ~(1 << ep_no); 1590 } else { 1591 /* single buffer */ 1592 temp |= (1 << ep_no); 1593 } 1594 MUSB2_WRITE_2(sc, MUSB2_REG_TXDBDIS, temp); 1595 1596 /* clear sent stall */ 1597 if (csr & MUSB2_MASK_CSRL_TXSENTSTALL) { 1598 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0); 1599 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 1600 } 1601 } else { 1602 1603 temp = 0; 1604 1605 /* Configure endpoint */ 1606 switch (ep_type) { 1607 case UE_INTERRUPT: 1608 MUSB2_WRITE_1(sc, MUSB2_REG_RXMAXP, wMaxPacket); 1609 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH, 1610 MUSB2_MASK_CSRH_RXNYET | temp); 1611 break; 1612 case UE_ISOCHRONOUS: 1613 MUSB2_WRITE_1(sc, MUSB2_REG_RXMAXP, wMaxPacket); 1614 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH, 1615 MUSB2_MASK_CSRH_RXNYET | 1616 MUSB2_MASK_CSRH_RXISO | temp); 1617 break; 1618 case UE_BULK: 1619 MUSB2_WRITE_1(sc, MUSB2_REG_RXMAXP, wMaxPacket); 1620 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH, temp); 1621 break; 1622 default: 1623 break; 1624 } 1625 1626 /* Need to flush twice in case of double bufring */ 1627 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL); 1628 if (csr & MUSB2_MASK_CSRL_RXPKTRDY) { 1629 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 1630 MUSB2_MASK_CSRL_RXFFLUSH); 1631 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL); 1632 if (csr & MUSB2_MASK_CSRL_RXPKTRDY) { 1633 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 1634 MUSB2_MASK_CSRL_RXFFLUSH); 1635 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL); 1636 } 1637 } 1638 /* reset data toggle */ 1639 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 1640 MUSB2_MASK_CSRL_RXDT_CLR); 1641 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 0); 1642 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL); 1643 1644 /* set double/single buffering */ 1645 temp = MUSB2_READ_2(sc, MUSB2_REG_RXDBDIS); 1646 if (mps <= (sc->sc_hw_ep_profile[ep_no]. 1647 max_out_frame_size / 2)) { 1648 /* double buffer */ 1649 temp &= ~(1 << ep_no); 1650 } else { 1651 /* single buffer */ 1652 temp |= (1 << ep_no); 1653 } 1654 MUSB2_WRITE_2(sc, MUSB2_REG_RXDBDIS, temp); 1655 1656 /* clear sent stall */ 1657 if (csr & MUSB2_MASK_CSRL_RXSENTSTALL) { 1658 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 0); 1659 } 1660 } 1661} 1662 1663static void 1664musbotg_clear_stall(struct usb2_device *udev, struct usb2_pipe *pipe) 1665{ 1666 struct musbotg_softc *sc; 1667 struct usb2_endpoint_descriptor *ed; 1668 1669 DPRINTFN(4, "pipe=%p\n", pipe); 1670 1671 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 1672 1673 /* check mode */ 1674 if (udev->flags.usb2_mode != USB_MODE_DEVICE) { 1675 /* not supported */ 1676 return; 1677 } 1678 /* get softc */ 1679 sc = MUSBOTG_BUS2SC(udev->bus); 1680 1681 /* get endpoint descriptor */ 1682 ed = pipe->edesc; 1683 1684 /* reset endpoint */ 1685 musbotg_clear_stall_sub(sc, 1686 UGETW(ed->wMaxPacketSize), 1687 (ed->bEndpointAddress & UE_ADDR), 1688 (ed->bmAttributes & UE_XFERTYPE), 1689 (ed->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT))); 1690} 1691 1692usb2_error_t 1693musbotg_init(struct musbotg_softc *sc) 1694{ 1695 struct usb2_hw_ep_profile *pf; 1696 uint8_t nrx; 1697 uint8_t ntx; 1698 uint8_t temp; 1699 uint8_t fsize; 1700 uint8_t frx; 1701 uint8_t ftx; 1702 1703 DPRINTFN(1, "start\n"); 1704 1705 /* set up the bus structure */ 1706 sc->sc_bus.usbrev = USB_REV_2_0; 1707 sc->sc_bus.methods = &musbotg_bus_methods; 1708 1709 USB_BUS_LOCK(&sc->sc_bus); 1710 1711 /* turn on clocks */ 1712 1713 if (sc->sc_clocks_on) { 1714 (sc->sc_clocks_on) (sc->sc_clocks_arg); 1715 } 1716 /* wait a little for things to stabilise */ 1717 usb2_pause_mtx(&sc->sc_bus.bus_mtx, 1); 1718 1719 /* disable all interrupts */ 1720 1721 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, 0); 1722 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, 0); 1723 MUSB2_WRITE_2(sc, MUSB2_REG_INTRXE, 0); 1724 1725 /* disable pullup */ 1726 1727 musbotg_pull_common(sc, 0); 1728 1729 /* wait a little bit (10ms) */ 1730 usb2_pause_mtx(&sc->sc_bus.bus_mtx, 10); 1731 1732 /* disable double packet buffering */ 1733 MUSB2_WRITE_2(sc, MUSB2_REG_RXDBDIS, 0xFFFF); 1734 MUSB2_WRITE_2(sc, MUSB2_REG_TXDBDIS, 0xFFFF); 1735 1736 /* enable HighSpeed and ISO Update flags */ 1737 1738 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, 1739 MUSB2_MASK_HSENAB | MUSB2_MASK_ISOUPD); 1740 1741 /* clear Session bit, if set */ 1742 1743 temp = MUSB2_READ_1(sc, MUSB2_REG_DEVCTL); 1744 temp &= ~MUSB2_MASK_SESS; 1745 MUSB2_WRITE_1(sc, MUSB2_REG_DEVCTL, temp); 1746 1747 DPRINTF("DEVCTL=0x%02x\n", temp); 1748 1749 /* disable testmode */ 1750 1751 MUSB2_WRITE_1(sc, MUSB2_REG_TESTMODE, 0); 1752 1753 /* set default value */ 1754 1755 MUSB2_WRITE_1(sc, MUSB2_REG_MISC, 0); 1756 1757 /* select endpoint index 0 */ 1758 1759 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); 1760 1761 /* read out number of endpoints */ 1762 1763 nrx = 1764 (MUSB2_READ_1(sc, MUSB2_REG_EPINFO) / 16); 1765 1766 ntx = 1767 (MUSB2_READ_1(sc, MUSB2_REG_EPINFO) % 16); 1768 1769 /* these numbers exclude the control endpoint */ 1770 1771 DPRINTFN(2, "RX/TX endpoints: %u/%u\n", nrx, ntx); 1772 1773 sc->sc_ep_max = (nrx > ntx) ? nrx : ntx; 1774 if (sc->sc_ep_max == 0) { 1775 DPRINTFN(2, "ERROR: Looks like the clocks are off!\n"); 1776 } 1777 /* read out configuration data */ 1778 1779 sc->sc_conf_data = MUSB2_READ_1(sc, MUSB2_REG_CONFDATA); 1780 1781 DPRINTFN(2, "Config Data: 0x%02x\n", 1782 sc->sc_conf_data); 1783 1784 DPRINTFN(2, "HW version: 0x%04x\n", 1785 MUSB2_READ_1(sc, MUSB2_REG_HWVERS)); 1786 1787 /* initialise endpoint profiles */ 1788 1789 for (temp = 1; temp <= sc->sc_ep_max; temp++) { 1790 pf = sc->sc_hw_ep_profile + temp; 1791 1792 /* select endpoint */ 1793 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, temp); 1794 1795 fsize = MUSB2_READ_1(sc, MUSB2_REG_FSIZE); 1796 frx = (fsize & MUSB2_MASK_RX_FSIZE) / 16;; 1797 ftx = (fsize & MUSB2_MASK_TX_FSIZE); 1798 1799 DPRINTF("Endpoint %u FIFO size: IN=%u, OUT=%u\n", 1800 temp, pf->max_in_frame_size, 1801 pf->max_out_frame_size); 1802 1803 if (frx && ftx && (temp <= nrx) && (temp <= ntx)) { 1804 pf->max_in_frame_size = 1 << ftx; 1805 pf->max_out_frame_size = 1 << frx; 1806 pf->is_simplex = 0; /* duplex */ 1807 pf->support_multi_buffer = 1; 1808 pf->support_bulk = 1; 1809 pf->support_interrupt = 1; 1810 pf->support_isochronous = 1; 1811 pf->support_in = 1; 1812 pf->support_out = 1; 1813 } else if (frx && (temp <= nrx)) { 1814 pf->max_out_frame_size = 1 << frx; 1815 pf->is_simplex = 1; /* simplex */ 1816 pf->support_multi_buffer = 1; 1817 pf->support_bulk = 1; 1818 pf->support_interrupt = 1; 1819 pf->support_isochronous = 1; 1820 pf->support_out = 1; 1821 } else if (ftx && (temp <= ntx)) { 1822 pf->max_in_frame_size = 1 << ftx; 1823 pf->is_simplex = 1; /* simplex */ 1824 pf->support_multi_buffer = 1; 1825 pf->support_bulk = 1; 1826 pf->support_interrupt = 1; 1827 pf->support_isochronous = 1; 1828 pf->support_in = 1; 1829 } 1830 } 1831 1832 /* turn on default interrupts */ 1833 1834 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, 1835 MUSB2_MASK_IRESET); 1836 1837 musbotg_clocks_off(sc); 1838 1839 USB_BUS_UNLOCK(&sc->sc_bus); 1840 1841 /* catch any lost interrupts */ 1842 1843 musbotg_do_poll(&sc->sc_bus); 1844 1845 return (0); /* success */ 1846} 1847 1848void 1849musbotg_uninit(struct musbotg_softc *sc) 1850{ 1851 USB_BUS_LOCK(&sc->sc_bus); 1852 1853 /* disable all interrupts */ 1854 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, 0); 1855 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, 0); 1856 MUSB2_WRITE_2(sc, MUSB2_REG_INTRXE, 0); 1857 1858 sc->sc_flags.port_powered = 0; 1859 sc->sc_flags.status_vbus = 0; 1860 sc->sc_flags.status_bus_reset = 0; 1861 sc->sc_flags.status_suspend = 0; 1862 sc->sc_flags.change_suspend = 0; 1863 sc->sc_flags.change_connect = 1; 1864 1865 musbotg_pull_down(sc); 1866 musbotg_clocks_off(sc); 1867 USB_BUS_UNLOCK(&sc->sc_bus); 1868} 1869 1870void 1871musbotg_suspend(struct musbotg_softc *sc) 1872{ 1873 return; 1874} 1875 1876void 1877musbotg_resume(struct musbotg_softc *sc) 1878{ 1879 return; 1880} 1881 1882static void 1883musbotg_do_poll(struct usb2_bus *bus) 1884{ 1885 struct musbotg_softc *sc = MUSBOTG_BUS2SC(bus); 1886 1887 USB_BUS_LOCK(&sc->sc_bus); 1888 musbotg_interrupt_poll(sc); 1889 musbotg_root_ctrl_poll(sc); 1890 USB_BUS_UNLOCK(&sc->sc_bus); 1891} 1892 1893/*------------------------------------------------------------------------* 1894 * musbotg bulk support 1895 *------------------------------------------------------------------------*/ 1896static void 1897musbotg_device_bulk_open(struct usb2_xfer *xfer) 1898{ 1899 return; 1900} 1901 1902static void 1903musbotg_device_bulk_close(struct usb2_xfer *xfer) 1904{ 1905 musbotg_device_done(xfer, USB_ERR_CANCELLED); 1906} 1907 1908static void 1909musbotg_device_bulk_enter(struct usb2_xfer *xfer) 1910{ 1911 return; 1912} 1913 1914static void 1915musbotg_device_bulk_start(struct usb2_xfer *xfer) 1916{ 1917 /* setup TDs */ 1918 musbotg_setup_standard_chain(xfer); 1919 musbotg_start_standard_chain(xfer); 1920} 1921 1922struct usb2_pipe_methods musbotg_device_bulk_methods = 1923{ 1924 .open = musbotg_device_bulk_open, 1925 .close = musbotg_device_bulk_close, 1926 .enter = musbotg_device_bulk_enter, 1927 .start = musbotg_device_bulk_start, 1928 .enter_is_cancelable = 1, 1929 .start_is_cancelable = 1, 1930}; 1931 1932/*------------------------------------------------------------------------* 1933 * musbotg control support 1934 *------------------------------------------------------------------------*/ 1935static void 1936musbotg_device_ctrl_open(struct usb2_xfer *xfer) 1937{ 1938 return; 1939} 1940 1941static void 1942musbotg_device_ctrl_close(struct usb2_xfer *xfer) 1943{ 1944 musbotg_device_done(xfer, USB_ERR_CANCELLED); 1945} 1946 1947static void 1948musbotg_device_ctrl_enter(struct usb2_xfer *xfer) 1949{ 1950 return; 1951} 1952 1953static void 1954musbotg_device_ctrl_start(struct usb2_xfer *xfer) 1955{ 1956 /* setup TDs */ 1957 musbotg_setup_standard_chain(xfer); 1958 musbotg_start_standard_chain(xfer); 1959} 1960 1961struct usb2_pipe_methods musbotg_device_ctrl_methods = 1962{ 1963 .open = musbotg_device_ctrl_open, 1964 .close = musbotg_device_ctrl_close, 1965 .enter = musbotg_device_ctrl_enter, 1966 .start = musbotg_device_ctrl_start, 1967 .enter_is_cancelable = 1, 1968 .start_is_cancelable = 1, 1969}; 1970 1971/*------------------------------------------------------------------------* 1972 * musbotg interrupt support 1973 *------------------------------------------------------------------------*/ 1974static void 1975musbotg_device_intr_open(struct usb2_xfer *xfer) 1976{ 1977 return; 1978} 1979 1980static void 1981musbotg_device_intr_close(struct usb2_xfer *xfer) 1982{ 1983 musbotg_device_done(xfer, USB_ERR_CANCELLED); 1984} 1985 1986static void 1987musbotg_device_intr_enter(struct usb2_xfer *xfer) 1988{ 1989 return; 1990} 1991 1992static void 1993musbotg_device_intr_start(struct usb2_xfer *xfer) 1994{ 1995 /* setup TDs */ 1996 musbotg_setup_standard_chain(xfer); 1997 musbotg_start_standard_chain(xfer); 1998} 1999 2000struct usb2_pipe_methods musbotg_device_intr_methods = 2001{ 2002 .open = musbotg_device_intr_open, 2003 .close = musbotg_device_intr_close, 2004 .enter = musbotg_device_intr_enter, 2005 .start = musbotg_device_intr_start, 2006 .enter_is_cancelable = 1, 2007 .start_is_cancelable = 1, 2008}; 2009 2010/*------------------------------------------------------------------------* 2011 * musbotg full speed isochronous support 2012 *------------------------------------------------------------------------*/ 2013static void 2014musbotg_device_isoc_open(struct usb2_xfer *xfer) 2015{ 2016 return; 2017} 2018 2019static void 2020musbotg_device_isoc_close(struct usb2_xfer *xfer) 2021{ 2022 musbotg_device_done(xfer, USB_ERR_CANCELLED); 2023} 2024 2025static void 2026musbotg_device_isoc_enter(struct usb2_xfer *xfer) 2027{ 2028 struct musbotg_softc *sc = xfer->usb2_sc; 2029 uint32_t temp; 2030 uint32_t nframes; 2031 uint32_t fs_frames; 2032 2033 DPRINTFN(5, "xfer=%p next=%d nframes=%d\n", 2034 xfer, xfer->pipe->isoc_next, xfer->nframes); 2035 2036 /* get the current frame index */ 2037 2038 nframes = MUSB2_READ_2(sc, MUSB2_REG_FRAME); 2039 2040 /* 2041 * check if the frame index is within the window where the frames 2042 * will be inserted 2043 */ 2044 temp = (nframes - xfer->pipe->isoc_next) & MUSB2_MASK_FRAME; 2045 2046 if (usb2_get_speed(xfer->udev) == USB_SPEED_HIGH) { 2047 fs_frames = (xfer->nframes + 7) / 8; 2048 } else { 2049 fs_frames = xfer->nframes; 2050 } 2051 2052 if ((xfer->pipe->is_synced == 0) || 2053 (temp < fs_frames)) { 2054 /* 2055 * If there is data underflow or the pipe queue is 2056 * empty we schedule the transfer a few frames ahead 2057 * of the current frame position. Else two isochronous 2058 * transfers might overlap. 2059 */ 2060 xfer->pipe->isoc_next = (nframes + 3) & MUSB2_MASK_FRAME; 2061 xfer->pipe->is_synced = 1; 2062 DPRINTFN(2, "start next=%d\n", xfer->pipe->isoc_next); 2063 } 2064 /* 2065 * compute how many milliseconds the insertion is ahead of the 2066 * current frame position: 2067 */ 2068 temp = (xfer->pipe->isoc_next - nframes) & MUSB2_MASK_FRAME; 2069 2070 /* 2071 * pre-compute when the isochronous transfer will be finished: 2072 */ 2073 xfer->isoc_time_complete = 2074 usb2_isoc_time_expand(&sc->sc_bus, nframes) + temp + 2075 fs_frames; 2076 2077 /* compute frame number for next insertion */ 2078 xfer->pipe->isoc_next += fs_frames; 2079 2080 /* setup TDs */ 2081 musbotg_setup_standard_chain(xfer); 2082} 2083 2084static void 2085musbotg_device_isoc_start(struct usb2_xfer *xfer) 2086{ 2087 /* start TD chain */ 2088 musbotg_start_standard_chain(xfer); 2089} 2090 2091struct usb2_pipe_methods musbotg_device_isoc_methods = 2092{ 2093 .open = musbotg_device_isoc_open, 2094 .close = musbotg_device_isoc_close, 2095 .enter = musbotg_device_isoc_enter, 2096 .start = musbotg_device_isoc_start, 2097 .enter_is_cancelable = 1, 2098 .start_is_cancelable = 1, 2099}; 2100 2101/*------------------------------------------------------------------------* 2102 * musbotg root control support 2103 *------------------------------------------------------------------------* 2104 * simulate a hardware HUB by handling 2105 * all the necessary requests 2106 *------------------------------------------------------------------------*/ 2107static void 2108musbotg_root_ctrl_open(struct usb2_xfer *xfer) 2109{ 2110 return; 2111} 2112 2113static void 2114musbotg_root_ctrl_close(struct usb2_xfer *xfer) 2115{ 2116 struct musbotg_softc *sc = xfer->usb2_sc; 2117 2118 if (sc->sc_root_ctrl.xfer == xfer) { 2119 sc->sc_root_ctrl.xfer = NULL; 2120 } 2121 musbotg_device_done(xfer, USB_ERR_CANCELLED); 2122} 2123 2124/* 2125 * USB descriptors for the virtual Root HUB: 2126 */ 2127 2128static const struct usb2_device_descriptor musbotg_devd = { 2129 .bLength = sizeof(struct usb2_device_descriptor), 2130 .bDescriptorType = UDESC_DEVICE, 2131 .bcdUSB = {0x00, 0x02}, 2132 .bDeviceClass = UDCLASS_HUB, 2133 .bDeviceSubClass = UDSUBCLASS_HUB, 2134 .bDeviceProtocol = UDPROTO_HSHUBSTT, 2135 .bMaxPacketSize = 64, 2136 .bcdDevice = {0x00, 0x01}, 2137 .iManufacturer = 1, 2138 .iProduct = 2, 2139 .bNumConfigurations = 1, 2140}; 2141 2142static const struct usb2_device_qualifier musbotg_odevd = { 2143 .bLength = sizeof(struct usb2_device_qualifier), 2144 .bDescriptorType = UDESC_DEVICE_QUALIFIER, 2145 .bcdUSB = {0x00, 0x02}, 2146 .bDeviceClass = UDCLASS_HUB, 2147 .bDeviceSubClass = UDSUBCLASS_HUB, 2148 .bDeviceProtocol = UDPROTO_FSHUB, 2149 .bMaxPacketSize0 = 0, 2150 .bNumConfigurations = 0, 2151}; 2152 2153static const struct musbotg_config_desc musbotg_confd = { 2154 .confd = { 2155 .bLength = sizeof(struct usb2_config_descriptor), 2156 .bDescriptorType = UDESC_CONFIG, 2157 .wTotalLength[0] = sizeof(musbotg_confd), 2158 .bNumInterface = 1, 2159 .bConfigurationValue = 1, 2160 .iConfiguration = 0, 2161 .bmAttributes = UC_SELF_POWERED, 2162 .bMaxPower = 0, 2163 }, 2164 .ifcd = { 2165 .bLength = sizeof(struct usb2_interface_descriptor), 2166 .bDescriptorType = UDESC_INTERFACE, 2167 .bNumEndpoints = 1, 2168 .bInterfaceClass = UICLASS_HUB, 2169 .bInterfaceSubClass = UISUBCLASS_HUB, 2170 .bInterfaceProtocol = UIPROTO_HSHUBSTT, 2171 }, 2172 2173 .endpd = { 2174 .bLength = sizeof(struct usb2_endpoint_descriptor), 2175 .bDescriptorType = UDESC_ENDPOINT, 2176 .bEndpointAddress = (UE_DIR_IN | MUSBOTG_INTR_ENDPT), 2177 .bmAttributes = UE_INTERRUPT, 2178 .wMaxPacketSize[0] = 8, 2179 .bInterval = 255, 2180 }, 2181}; 2182 2183static const struct usb2_hub_descriptor_min musbotg_hubd = { 2184 .bDescLength = sizeof(musbotg_hubd), 2185 .bDescriptorType = UDESC_HUB, 2186 .bNbrPorts = 1, 2187 .wHubCharacteristics[0] = 2188 (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL) & 0xFF, 2189 .wHubCharacteristics[1] = 2190 (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL) >> 16, 2191 .bPwrOn2PwrGood = 50, 2192 .bHubContrCurrent = 0, 2193 .DeviceRemovable = {0}, /* port is removable */ 2194}; 2195 2196#define STRING_LANG \ 2197 0x09, 0x04, /* American English */ 2198 2199#define STRING_VENDOR \ 2200 'M', 0, 'e', 0, 'n', 0, 't', 0, 'o', 0, 'r', 0, ' ', 0, \ 2201 'G', 0, 'r', 0, 'a', 0, 'p', 0, 'h', 0, 'i', 0, 'c', 0, 's', 0 2202 2203#define STRING_PRODUCT \ 2204 'O', 0, 'T', 0, 'G', 0, ' ', 0, 'R', 0, \ 2205 'o', 0, 'o', 0, 't', 0, ' ', 0, 'H', 0, \ 2206 'U', 0, 'B', 0, 2207 2208USB_MAKE_STRING_DESC(STRING_LANG, musbotg_langtab); 2209USB_MAKE_STRING_DESC(STRING_VENDOR, musbotg_vendor); 2210USB_MAKE_STRING_DESC(STRING_PRODUCT, musbotg_product); 2211 2212static void 2213musbotg_root_ctrl_enter(struct usb2_xfer *xfer) 2214{ 2215 return; 2216} 2217 2218static void 2219musbotg_root_ctrl_start(struct usb2_xfer *xfer) 2220{ 2221 struct musbotg_softc *sc = xfer->usb2_sc; 2222 2223 sc->sc_root_ctrl.xfer = xfer; 2224 2225 usb2_config_td_queue_command( 2226 &sc->sc_config_td, NULL, &musbotg_root_ctrl_task, 0, 0); 2227} 2228 2229static void 2230musbotg_root_ctrl_task(struct musbotg_softc *sc, 2231 struct musbotg_config_copy *cc, uint16_t refcount) 2232{ 2233 musbotg_root_ctrl_poll(sc); 2234} 2235 2236static void 2237musbotg_root_ctrl_done(struct usb2_xfer *xfer, 2238 struct usb2_sw_transfer *std) 2239{ 2240 struct musbotg_softc *sc = xfer->usb2_sc; 2241 uint16_t value; 2242 uint16_t index; 2243 uint8_t use_polling; 2244 2245 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2246 2247 if (std->state != USB_SW_TR_SETUP) { 2248 if (std->state == USB_SW_TR_PRE_CALLBACK) { 2249 /* transfer transferred */ 2250 musbotg_device_done(xfer, std->err); 2251 } 2252 goto done; 2253 } 2254 /* buffer reset */ 2255 std->ptr = USB_ADD_BYTES(&sc->sc_hub_temp, 0); 2256 std->len = 0; 2257 2258 value = UGETW(std->req.wValue); 2259 index = UGETW(std->req.wIndex); 2260 2261 use_polling = mtx_owned(xfer->xfer_mtx) ? 1 : 0; 2262 2263 /* demultiplex the control request */ 2264 2265 switch (std->req.bmRequestType) { 2266 case UT_READ_DEVICE: 2267 switch (std->req.bRequest) { 2268 case UR_GET_DESCRIPTOR: 2269 goto tr_handle_get_descriptor; 2270 case UR_GET_CONFIG: 2271 goto tr_handle_get_config; 2272 case UR_GET_STATUS: 2273 goto tr_handle_get_status; 2274 default: 2275 goto tr_stalled; 2276 } 2277 break; 2278 2279 case UT_WRITE_DEVICE: 2280 switch (std->req.bRequest) { 2281 case UR_SET_ADDRESS: 2282 goto tr_handle_set_address; 2283 case UR_SET_CONFIG: 2284 goto tr_handle_set_config; 2285 case UR_CLEAR_FEATURE: 2286 goto tr_valid; /* nop */ 2287 case UR_SET_DESCRIPTOR: 2288 goto tr_valid; /* nop */ 2289 case UR_SET_FEATURE: 2290 default: 2291 goto tr_stalled; 2292 } 2293 break; 2294 2295 case UT_WRITE_ENDPOINT: 2296 switch (std->req.bRequest) { 2297 case UR_CLEAR_FEATURE: 2298 switch (UGETW(std->req.wValue)) { 2299 case UF_ENDPOINT_HALT: 2300 goto tr_handle_clear_halt; 2301 case UF_DEVICE_REMOTE_WAKEUP: 2302 goto tr_handle_clear_wakeup; 2303 default: 2304 goto tr_stalled; 2305 } 2306 break; 2307 case UR_SET_FEATURE: 2308 switch (UGETW(std->req.wValue)) { 2309 case UF_ENDPOINT_HALT: 2310 goto tr_handle_set_halt; 2311 case UF_DEVICE_REMOTE_WAKEUP: 2312 goto tr_handle_set_wakeup; 2313 default: 2314 goto tr_stalled; 2315 } 2316 break; 2317 case UR_SYNCH_FRAME: 2318 goto tr_valid; /* nop */ 2319 default: 2320 goto tr_stalled; 2321 } 2322 break; 2323 2324 case UT_READ_ENDPOINT: 2325 switch (std->req.bRequest) { 2326 case UR_GET_STATUS: 2327 goto tr_handle_get_ep_status; 2328 default: 2329 goto tr_stalled; 2330 } 2331 break; 2332 2333 case UT_WRITE_INTERFACE: 2334 switch (std->req.bRequest) { 2335 case UR_SET_INTERFACE: 2336 goto tr_handle_set_interface; 2337 case UR_CLEAR_FEATURE: 2338 goto tr_valid; /* nop */ 2339 case UR_SET_FEATURE: 2340 default: 2341 goto tr_stalled; 2342 } 2343 break; 2344 2345 case UT_READ_INTERFACE: 2346 switch (std->req.bRequest) { 2347 case UR_GET_INTERFACE: 2348 goto tr_handle_get_interface; 2349 case UR_GET_STATUS: 2350 goto tr_handle_get_iface_status; 2351 default: 2352 goto tr_stalled; 2353 } 2354 break; 2355 2356 case UT_WRITE_CLASS_INTERFACE: 2357 case UT_WRITE_VENDOR_INTERFACE: 2358 /* XXX forward */ 2359 break; 2360 2361 case UT_READ_CLASS_INTERFACE: 2362 case UT_READ_VENDOR_INTERFACE: 2363 /* XXX forward */ 2364 break; 2365 2366 case UT_WRITE_CLASS_DEVICE: 2367 switch (std->req.bRequest) { 2368 case UR_CLEAR_FEATURE: 2369 goto tr_valid; 2370 case UR_SET_DESCRIPTOR: 2371 case UR_SET_FEATURE: 2372 break; 2373 default: 2374 goto tr_stalled; 2375 } 2376 break; 2377 2378 case UT_WRITE_CLASS_OTHER: 2379 switch (std->req.bRequest) { 2380 case UR_CLEAR_FEATURE: 2381 goto tr_handle_clear_port_feature; 2382 case UR_SET_FEATURE: 2383 goto tr_handle_set_port_feature; 2384 case UR_CLEAR_TT_BUFFER: 2385 case UR_RESET_TT: 2386 case UR_STOP_TT: 2387 goto tr_valid; 2388 2389 default: 2390 goto tr_stalled; 2391 } 2392 break; 2393 2394 case UT_READ_CLASS_OTHER: 2395 switch (std->req.bRequest) { 2396 case UR_GET_TT_STATE: 2397 goto tr_handle_get_tt_state; 2398 case UR_GET_STATUS: 2399 goto tr_handle_get_port_status; 2400 default: 2401 goto tr_stalled; 2402 } 2403 break; 2404 2405 case UT_READ_CLASS_DEVICE: 2406 switch (std->req.bRequest) { 2407 case UR_GET_DESCRIPTOR: 2408 goto tr_handle_get_class_descriptor; 2409 case UR_GET_STATUS: 2410 goto tr_handle_get_class_status; 2411 2412 default: 2413 goto tr_stalled; 2414 } 2415 break; 2416 default: 2417 goto tr_stalled; 2418 } 2419 goto tr_valid; 2420 2421tr_handle_get_descriptor: 2422 switch (value >> 8) { 2423 case UDESC_DEVICE: 2424 if (value & 0xff) { 2425 goto tr_stalled; 2426 } 2427 std->len = sizeof(musbotg_devd); 2428 std->ptr = USB_ADD_BYTES(&musbotg_devd, 0); 2429 goto tr_valid; 2430 case UDESC_CONFIG: 2431 if (value & 0xff) { 2432 goto tr_stalled; 2433 } 2434 std->len = sizeof(musbotg_confd); 2435 std->ptr = USB_ADD_BYTES(&musbotg_confd, 0); 2436 goto tr_valid; 2437 case UDESC_STRING: 2438 switch (value & 0xff) { 2439 case 0: /* Language table */ 2440 std->len = sizeof(musbotg_langtab); 2441 std->ptr = USB_ADD_BYTES(&musbotg_langtab, 0); 2442 goto tr_valid; 2443 2444 case 1: /* Vendor */ 2445 std->len = sizeof(musbotg_vendor); 2446 std->ptr = USB_ADD_BYTES(&musbotg_vendor, 0); 2447 goto tr_valid; 2448 2449 case 2: /* Product */ 2450 std->len = sizeof(musbotg_product); 2451 std->ptr = USB_ADD_BYTES(&musbotg_product, 0); 2452 goto tr_valid; 2453 default: 2454 break; 2455 } 2456 break; 2457 default: 2458 goto tr_stalled; 2459 } 2460 goto tr_stalled; 2461 2462tr_handle_get_config: 2463 std->len = 1; 2464 sc->sc_hub_temp.wValue[0] = sc->sc_conf; 2465 goto tr_valid; 2466 2467tr_handle_get_status: 2468 std->len = 2; 2469 USETW(sc->sc_hub_temp.wValue, UDS_SELF_POWERED); 2470 goto tr_valid; 2471 2472tr_handle_set_address: 2473 if (value & 0xFF00) { 2474 goto tr_stalled; 2475 } 2476 sc->sc_rt_addr = value; 2477 goto tr_valid; 2478 2479tr_handle_set_config: 2480 if (value >= 2) { 2481 goto tr_stalled; 2482 } 2483 sc->sc_conf = value; 2484 goto tr_valid; 2485 2486tr_handle_get_interface: 2487 std->len = 1; 2488 sc->sc_hub_temp.wValue[0] = 0; 2489 goto tr_valid; 2490 2491tr_handle_get_tt_state: 2492tr_handle_get_class_status: 2493tr_handle_get_iface_status: 2494tr_handle_get_ep_status: 2495 std->len = 2; 2496 USETW(sc->sc_hub_temp.wValue, 0); 2497 goto tr_valid; 2498 2499tr_handle_set_halt: 2500tr_handle_set_interface: 2501tr_handle_set_wakeup: 2502tr_handle_clear_wakeup: 2503tr_handle_clear_halt: 2504 goto tr_valid; 2505 2506tr_handle_clear_port_feature: 2507 if (index != 1) { 2508 goto tr_stalled; 2509 } 2510 DPRINTFN(8, "UR_CLEAR_PORT_FEATURE on port %d\n", index); 2511 2512 switch (value) { 2513 case UHF_PORT_SUSPEND: 2514 musbotg_wakeup_peer(xfer); 2515 break; 2516 2517 case UHF_PORT_ENABLE: 2518 sc->sc_flags.port_enabled = 0; 2519 break; 2520 2521 case UHF_PORT_TEST: 2522 case UHF_PORT_INDICATOR: 2523 case UHF_C_PORT_ENABLE: 2524 case UHF_C_PORT_OVER_CURRENT: 2525 case UHF_C_PORT_RESET: 2526 /* nops */ 2527 break; 2528 case UHF_PORT_POWER: 2529 sc->sc_flags.port_powered = 0; 2530 musbotg_pull_down(sc); 2531 musbotg_clocks_off(sc); 2532 break; 2533 case UHF_C_PORT_CONNECTION: 2534 sc->sc_flags.change_connect = 0; 2535 break; 2536 case UHF_C_PORT_SUSPEND: 2537 sc->sc_flags.change_suspend = 0; 2538 break; 2539 default: 2540 std->err = USB_ERR_IOERROR; 2541 goto done; 2542 } 2543 goto tr_valid; 2544 2545tr_handle_set_port_feature: 2546 if (index != 1) { 2547 goto tr_stalled; 2548 } 2549 DPRINTFN(8, "UR_SET_PORT_FEATURE\n"); 2550 2551 switch (value) { 2552 case UHF_PORT_ENABLE: 2553 sc->sc_flags.port_enabled = 1; 2554 break; 2555 case UHF_PORT_SUSPEND: 2556 case UHF_PORT_RESET: 2557 case UHF_PORT_TEST: 2558 case UHF_PORT_INDICATOR: 2559 /* nops */ 2560 break; 2561 case UHF_PORT_POWER: 2562 sc->sc_flags.port_powered = 1; 2563 break; 2564 default: 2565 std->err = USB_ERR_IOERROR; 2566 goto done; 2567 } 2568 goto tr_valid; 2569 2570tr_handle_get_port_status: 2571 2572 DPRINTFN(8, "UR_GET_PORT_STATUS\n"); 2573 2574 if (index != 1) { 2575 goto tr_stalled; 2576 } 2577 if (sc->sc_flags.status_vbus) { 2578 musbotg_clocks_on(sc); 2579 musbotg_pull_up(sc); 2580 } else { 2581 musbotg_pull_down(sc); 2582 musbotg_clocks_off(sc); 2583 } 2584 2585 /* Select Device Side Mode */ 2586 value = UPS_PORT_MODE_DEVICE; 2587 2588 if (sc->sc_flags.status_high_speed) { 2589 value |= UPS_HIGH_SPEED; 2590 } 2591 if (sc->sc_flags.port_powered) { 2592 value |= UPS_PORT_POWER; 2593 } 2594 if (sc->sc_flags.port_enabled) { 2595 value |= UPS_PORT_ENABLED; 2596 } 2597 if (sc->sc_flags.status_vbus && 2598 sc->sc_flags.status_bus_reset) { 2599 value |= UPS_CURRENT_CONNECT_STATUS; 2600 } 2601 if (sc->sc_flags.status_suspend) { 2602 value |= UPS_SUSPEND; 2603 } 2604 USETW(sc->sc_hub_temp.ps.wPortStatus, value); 2605 2606 value = 0; 2607 2608 if (sc->sc_flags.change_connect) { 2609 value |= UPS_C_CONNECT_STATUS; 2610 2611 if (sc->sc_flags.status_vbus && 2612 sc->sc_flags.status_bus_reset) { 2613 /* reset EP0 state */ 2614 sc->sc_ep0_busy = 0; 2615 sc->sc_ep0_cmd = 0; 2616 } 2617 } 2618 if (sc->sc_flags.change_suspend) { 2619 value |= UPS_C_SUSPEND; 2620 } 2621 USETW(sc->sc_hub_temp.ps.wPortChange, value); 2622 std->len = sizeof(sc->sc_hub_temp.ps); 2623 goto tr_valid; 2624 2625tr_handle_get_class_descriptor: 2626 if (value & 0xFF) { 2627 goto tr_stalled; 2628 } 2629 std->ptr = USB_ADD_BYTES(&musbotg_hubd, 0); 2630 std->len = sizeof(musbotg_hubd); 2631 goto tr_valid; 2632 2633tr_stalled: 2634 std->err = USB_ERR_STALLED; 2635tr_valid: 2636done: 2637 return; 2638} 2639 2640static void 2641musbotg_root_ctrl_poll(struct musbotg_softc *sc) 2642{ 2643 usb2_sw_transfer(&sc->sc_root_ctrl, 2644 &musbotg_root_ctrl_done); 2645} 2646 2647struct usb2_pipe_methods musbotg_root_ctrl_methods = 2648{ 2649 .open = musbotg_root_ctrl_open, 2650 .close = musbotg_root_ctrl_close, 2651 .enter = musbotg_root_ctrl_enter, 2652 .start = musbotg_root_ctrl_start, 2653 .enter_is_cancelable = 1, 2654 .start_is_cancelable = 0, 2655}; 2656 2657/*------------------------------------------------------------------------* 2658 * musbotg root interrupt support 2659 *------------------------------------------------------------------------*/ 2660static void 2661musbotg_root_intr_open(struct usb2_xfer *xfer) 2662{ 2663 return; 2664} 2665 2666static void 2667musbotg_root_intr_close(struct usb2_xfer *xfer) 2668{ 2669 struct musbotg_softc *sc = xfer->usb2_sc; 2670 2671 if (sc->sc_root_intr.xfer == xfer) { 2672 sc->sc_root_intr.xfer = NULL; 2673 } 2674 musbotg_device_done(xfer, USB_ERR_CANCELLED); 2675} 2676 2677static void 2678musbotg_root_intr_enter(struct usb2_xfer *xfer) 2679{ 2680 return; 2681} 2682 2683static void 2684musbotg_root_intr_start(struct usb2_xfer *xfer) 2685{ 2686 struct musbotg_softc *sc = xfer->usb2_sc; 2687 2688 sc->sc_root_intr.xfer = xfer; 2689} 2690 2691struct usb2_pipe_methods musbotg_root_intr_methods = 2692{ 2693 .open = musbotg_root_intr_open, 2694 .close = musbotg_root_intr_close, 2695 .enter = musbotg_root_intr_enter, 2696 .start = musbotg_root_intr_start, 2697 .enter_is_cancelable = 1, 2698 .start_is_cancelable = 1, 2699}; 2700 2701static void 2702musbotg_xfer_setup(struct usb2_setup_params *parm) 2703{ 2704 const struct usb2_hw_ep_profile *pf; 2705 struct musbotg_softc *sc; 2706 struct usb2_xfer *xfer; 2707 void *last_obj; 2708 uint32_t ntd; 2709 uint32_t n; 2710 uint8_t ep_no; 2711 2712 sc = MUSBOTG_BUS2SC(parm->udev->bus); 2713 xfer = parm->curr_xfer; 2714 2715 /* 2716 * setup xfer 2717 */ 2718 xfer->usb2_sc = sc; 2719 2720 /* 2721 * NOTE: This driver does not use any of the parameters that 2722 * are computed from the following values. Just set some 2723 * reasonable dummies: 2724 */ 2725 parm->hc_max_packet_size = 0x400; 2726 parm->hc_max_frame_size = 0x400; 2727 2728 if ((parm->methods == &musbotg_device_isoc_methods) || 2729 (parm->methods == &musbotg_device_intr_methods)) 2730 parm->hc_max_packet_count = 3; 2731 else 2732 parm->hc_max_packet_count = 1; 2733 2734 usb2_transfer_setup_sub(parm); 2735 2736 /* 2737 * compute maximum number of TDs 2738 */ 2739 if (parm->methods == &musbotg_device_ctrl_methods) { 2740 2741 ntd = xfer->nframes + 1 /* STATUS */ + 1 /* SYNC */ ; 2742 2743 } else if (parm->methods == &musbotg_device_bulk_methods) { 2744 2745 ntd = xfer->nframes + 1 /* SYNC */ ; 2746 2747 } else if (parm->methods == &musbotg_device_intr_methods) { 2748 2749 ntd = xfer->nframes + 1 /* SYNC */ ; 2750 2751 } else if (parm->methods == &musbotg_device_isoc_methods) { 2752 2753 ntd = xfer->nframes + 1 /* SYNC */ ; 2754 2755 } else { 2756 2757 ntd = 0; 2758 } 2759 2760 /* 2761 * check if "usb2_transfer_setup_sub" set an error 2762 */ 2763 if (parm->err) { 2764 return; 2765 } 2766 /* 2767 * allocate transfer descriptors 2768 */ 2769 last_obj = NULL; 2770 2771 /* 2772 * get profile stuff 2773 */ 2774 if (ntd) { 2775 2776 ep_no = xfer->endpoint & UE_ADDR; 2777 musbotg_get_hw_ep_profile(parm->udev, &pf, ep_no); 2778 2779 if (pf == NULL) { 2780 /* should not happen */ 2781 parm->err = USB_ERR_INVAL; 2782 return; 2783 } 2784 } else { 2785 ep_no = 0; 2786 pf = NULL; 2787 } 2788 2789 /* align data */ 2790 parm->size[0] += ((-parm->size[0]) & (USB_HOST_ALIGN - 1)); 2791 2792 for (n = 0; n != ntd; n++) { 2793 2794 struct musbotg_td *td; 2795 2796 if (parm->buf) { 2797 2798 td = USB_ADD_BYTES(parm->buf, parm->size[0]); 2799 2800 /* init TD */ 2801 td->max_frame_size = xfer->max_frame_size; 2802 td->ep_no = ep_no; 2803 td->obj_next = last_obj; 2804 2805 last_obj = td; 2806 } 2807 parm->size[0] += sizeof(*td); 2808 } 2809 2810 xfer->td_start[0] = last_obj; 2811} 2812 2813static void 2814musbotg_xfer_unsetup(struct usb2_xfer *xfer) 2815{ 2816 return; 2817} 2818 2819static void 2820musbotg_pipe_init(struct usb2_device *udev, struct usb2_endpoint_descriptor *edesc, 2821 struct usb2_pipe *pipe) 2822{ 2823 struct musbotg_softc *sc = MUSBOTG_BUS2SC(udev->bus); 2824 2825 DPRINTFN(2, "pipe=%p, addr=%d, endpt=%d, mode=%d (%d)\n", 2826 pipe, udev->address, 2827 edesc->bEndpointAddress, udev->flags.usb2_mode, 2828 sc->sc_rt_addr); 2829 2830 if (udev->device_index == sc->sc_rt_addr) { 2831 2832 if (udev->flags.usb2_mode != USB_MODE_HOST) { 2833 /* not supported */ 2834 return; 2835 } 2836 switch (edesc->bEndpointAddress) { 2837 case USB_CONTROL_ENDPOINT: 2838 pipe->methods = &musbotg_root_ctrl_methods; 2839 break; 2840 case UE_DIR_IN | MUSBOTG_INTR_ENDPT: 2841 pipe->methods = &musbotg_root_intr_methods; 2842 break; 2843 default: 2844 /* do nothing */ 2845 break; 2846 } 2847 } else { 2848 2849 if (udev->flags.usb2_mode != USB_MODE_DEVICE) { 2850 /* not supported */ 2851 return; 2852 } 2853 if ((udev->speed != USB_SPEED_FULL) && 2854 (udev->speed != USB_SPEED_HIGH)) { 2855 /* not supported */ 2856 return; 2857 } 2858 switch (edesc->bmAttributes & UE_XFERTYPE) { 2859 case UE_CONTROL: 2860 pipe->methods = &musbotg_device_ctrl_methods; 2861 break; 2862 case UE_INTERRUPT: 2863 pipe->methods = &musbotg_device_intr_methods; 2864 break; 2865 case UE_ISOCHRONOUS: 2866 pipe->methods = &musbotg_device_isoc_methods; 2867 break; 2868 case UE_BULK: 2869 pipe->methods = &musbotg_device_bulk_methods; 2870 break; 2871 default: 2872 /* do nothing */ 2873 break; 2874 } 2875 } 2876} 2877 2878struct usb2_bus_methods musbotg_bus_methods = 2879{ 2880 .pipe_init = &musbotg_pipe_init, 2881 .xfer_setup = &musbotg_xfer_setup, 2882 .xfer_unsetup = &musbotg_xfer_unsetup, 2883 .do_poll = &musbotg_do_poll, 2884 .get_hw_ep_profile = &musbotg_get_hw_ep_profile, 2885 .set_stall = &musbotg_set_stall, 2886 .clear_stall = &musbotg_clear_stall, 2887 .vbus_interrupt = &musbotg_vbus_interrupt, 2888}; 2889