musb_otg.c revision 185950
1/* $FreeBSD: head/sys/dev/usb2/controller/musb2_otg.c 185950 2008-12-11 23:17:48Z thompsa $ */ 2/*- 3 * Copyright (c) 2008 Hans Petter Selasky. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27/* 28 * Thanks to Mentor Graphics for providing a reference driver for this 29 * USB chip at their homepage. 30 */ 31 32/* 33 * This file contains the driver for the Mentor Graphics Inventra USB 34 * 2.0 High Speed Dual-Role controller. 35 * 36 * NOTE: The current implementation only supports Device Side Mode! 37 */ 38 39#include <dev/usb2/include/usb2_standard.h> 40#include <dev/usb2/include/usb2_mfunc.h> 41#include <dev/usb2/include/usb2_error.h> 42#include <dev/usb2/include/usb2_defs.h> 43 44#define USB_DEBUG_VAR musbotgdebug 45#define usb2_config_td_cc musbotg_config_copy 46#define usb2_config_td_softc musbotg_softc 47 48#include <dev/usb2/core/usb2_core.h> 49#include <dev/usb2/core/usb2_debug.h> 50#include <dev/usb2/core/usb2_busdma.h> 51#include <dev/usb2/core/usb2_process.h> 52#include <dev/usb2/core/usb2_config_td.h> 53#include <dev/usb2/core/usb2_sw_transfer.h> 54#include <dev/usb2/core/usb2_transfer.h> 55#include <dev/usb2/core/usb2_device.h> 56#include <dev/usb2/core/usb2_hub.h> 57#include <dev/usb2/core/usb2_util.h> 58 59#include <dev/usb2/controller/usb2_controller.h> 60#include <dev/usb2/controller/usb2_bus.h> 61#include <dev/usb2/controller/musb2_otg.h> 62 63#define MUSBOTG_INTR_ENDPT 1 64 65#define MUSBOTG_BUS2SC(bus) \ 66 ((struct musbotg_softc *)(((uint8_t *)(bus)) - \ 67 USB_P2U(&(((struct musbotg_softc *)0)->sc_bus)))) 68 69#define MUSBOTG_PC2SC(pc) \ 70 MUSBOTG_BUS2SC((pc)->tag_parent->info->bus) 71 72#if USB_DEBUG 73static int musbotgdebug = 0; 74 75SYSCTL_NODE(_hw_usb2, OID_AUTO, musbotg, CTLFLAG_RW, 0, "USB musbotg"); 76SYSCTL_INT(_hw_usb2_musbotg, OID_AUTO, debug, CTLFLAG_RW, 77 &musbotgdebug, 0, "Debug level"); 78#endif 79 80/* prototypes */ 81 82struct usb2_bus_methods musbotg_bus_methods; 83struct usb2_pipe_methods musbotg_device_bulk_methods; 84struct usb2_pipe_methods musbotg_device_ctrl_methods; 85struct usb2_pipe_methods musbotg_device_intr_methods; 86struct usb2_pipe_methods musbotg_device_isoc_methods; 87struct usb2_pipe_methods musbotg_root_ctrl_methods; 88struct usb2_pipe_methods musbotg_root_intr_methods; 89 90static musbotg_cmd_t musbotg_setup_rx; 91static musbotg_cmd_t musbotg_setup_data_rx; 92static musbotg_cmd_t musbotg_setup_data_tx; 93static musbotg_cmd_t musbotg_setup_status; 94static musbotg_cmd_t musbotg_data_rx; 95static musbotg_cmd_t musbotg_data_tx; 96static void musbotg_device_done(struct usb2_xfer *, usb2_error_t); 97static void musbotg_do_poll(struct usb2_bus *); 98static void musbotg_root_ctrl_poll(struct musbotg_softc *); 99static void musbotg_standard_done(struct usb2_xfer *); 100static void musbotg_interrupt_poll(struct musbotg_softc *); 101 102static usb2_sw_transfer_func_t musbotg_root_intr_done; 103static usb2_sw_transfer_func_t musbotg_root_ctrl_done; 104static usb2_config_td_command_t musbotg_root_ctrl_task; 105 106/* 107 * Here is a configuration that the chip supports. 108 */ 109static const struct usb2_hw_ep_profile musbotg_ep_profile[1] = { 110 111 [0] = { 112 .max_in_frame_size = 64,/* fixed */ 113 .max_out_frame_size = 64, /* fixed */ 114 .is_simplex = 1, 115 .support_control = 1, 116 } 117}; 118 119static void 120musbotg_get_hw_ep_profile(struct usb2_device *udev, 121 const struct usb2_hw_ep_profile **ppf, uint8_t ep_addr) 122{ 123 struct musbotg_softc *sc; 124 125 sc = MUSBOTG_BUS2SC(udev->bus); 126 127 if (ep_addr == 0) { 128 /* control endpoint */ 129 *ppf = musbotg_ep_profile; 130 } else if (ep_addr <= sc->sc_ep_max) { 131 /* other endpoints */ 132 *ppf = sc->sc_hw_ep_profile + ep_addr; 133 } else { 134 *ppf = NULL; 135 } 136} 137 138static void 139musbotg_clocks_on(struct musbotg_softc *sc) 140{ 141 if (sc->sc_flags.clocks_off && 142 sc->sc_flags.port_powered) { 143 144 DPRINTFN(4, "\n"); 145 146 if (sc->sc_clocks_on) { 147 (sc->sc_clocks_on) (sc->sc_clocks_arg); 148 } 149 sc->sc_flags.clocks_off = 0; 150 151 /* XXX enable Transceiver */ 152 } 153} 154 155static void 156musbotg_clocks_off(struct musbotg_softc *sc) 157{ 158 if (!sc->sc_flags.clocks_off) { 159 160 DPRINTFN(4, "\n"); 161 162 /* XXX disable Transceiver */ 163 164 if (sc->sc_clocks_off) { 165 (sc->sc_clocks_off) (sc->sc_clocks_arg); 166 } 167 sc->sc_flags.clocks_off = 1; 168 } 169} 170 171static void 172musbotg_pull_common(struct musbotg_softc *sc, uint8_t on) 173{ 174 uint8_t temp; 175 176 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER); 177 if (on) 178 temp |= MUSB2_MASK_SOFTC; 179 else 180 temp &= ~MUSB2_MASK_SOFTC; 181 182 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp); 183} 184 185static void 186musbotg_pull_up(struct musbotg_softc *sc) 187{ 188 /* pullup D+, if possible */ 189 190 if (!sc->sc_flags.d_pulled_up && 191 sc->sc_flags.port_powered) { 192 sc->sc_flags.d_pulled_up = 1; 193 musbotg_pull_common(sc, 1); 194 } 195} 196 197static void 198musbotg_pull_down(struct musbotg_softc *sc) 199{ 200 /* pulldown D+, if possible */ 201 202 if (sc->sc_flags.d_pulled_up) { 203 sc->sc_flags.d_pulled_up = 0; 204 musbotg_pull_common(sc, 0); 205 } 206} 207 208static void 209musbotg_wakeup_peer(struct usb2_xfer *xfer) 210{ 211 struct musbotg_softc *sc = xfer->usb2_sc; 212 uint8_t temp; 213 uint8_t use_polling; 214 215 if (!(sc->sc_flags.status_suspend)) { 216 return; 217 } 218 use_polling = mtx_owned(xfer->xfer_mtx) ? 1 : 0; 219 220 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER); 221 temp |= MUSB2_MASK_RESUME; 222 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp); 223 224 /* wait 8 milliseconds */ 225 if (use_polling) { 226 /* polling */ 227 DELAY(8000); 228 } else { 229 /* Wait for reset to complete. */ 230 usb2_pause_mtx(&sc->sc_bus.bus_mtx, 8); 231 } 232 233 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER); 234 temp &= ~MUSB2_MASK_RESUME; 235 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp); 236} 237 238static void 239musbotg_rem_wakeup_set(struct usb2_device *udev, uint8_t is_on) 240{ 241 DPRINTFN(4, "is_on=%u\n", is_on); 242} 243 244static void 245musbotg_set_address(struct musbotg_softc *sc, uint8_t addr) 246{ 247 DPRINTFN(4, "addr=%d\n", addr); 248 addr &= 0x7F; 249 MUSB2_WRITE_1(sc, MUSB2_REG_FADDR, addr); 250} 251 252static uint8_t 253musbotg_setup_rx(struct musbotg_td *td) 254{ 255 struct musbotg_softc *sc; 256 struct usb2_device_request req; 257 uint16_t count; 258 uint8_t csr; 259 260 /* get pointer to softc */ 261 sc = MUSBOTG_PC2SC(td->pc); 262 263 /* select endpoint 0 */ 264 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); 265 266 /* read out FIFO status */ 267 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 268 269 DPRINTFN(4, "csr=0x%02x\n", csr); 270 271 /* 272 * NOTE: If DATAEND is set we should not call the 273 * callback, hence the status stage is not complete. 274 */ 275 if (csr & MUSB2_MASK_CSR0L_DATAEND) { 276 /* wait for interrupt */ 277 goto not_complete; 278 } 279 if (csr & MUSB2_MASK_CSR0L_SENTSTALL) { 280 /* clear SENTSTALL */ 281 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0); 282 /* get latest status */ 283 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 284 /* update EP0 state */ 285 sc->sc_ep0_busy = 0; 286 } 287 if (csr & MUSB2_MASK_CSR0L_SETUPEND) { 288 /* clear SETUPEND */ 289 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 290 MUSB2_MASK_CSR0L_SETUPEND_CLR); 291 /* get latest status */ 292 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 293 /* update EP0 state */ 294 sc->sc_ep0_busy = 0; 295 } 296 if (sc->sc_ep0_busy) { 297 /* abort any ongoing transfer */ 298 if (!td->did_stall) { 299 DPRINTFN(4, "stalling\n"); 300 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 301 MUSB2_MASK_CSR0L_SENDSTALL); 302 td->did_stall = 1; 303 } 304 goto not_complete; 305 } 306 if (!(csr & MUSB2_MASK_CSR0L_RXPKTRDY)) { 307 goto not_complete; 308 } 309 /* get the packet byte count */ 310 count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT); 311 312 /* verify data length */ 313 if (count != td->remainder) { 314 DPRINTFN(0, "Invalid SETUP packet " 315 "length, %d bytes\n", count); 316 goto not_complete; 317 } 318 if (count != sizeof(req)) { 319 DPRINTFN(0, "Unsupported SETUP packet " 320 "length, %d bytes\n", count); 321 goto not_complete; 322 } 323 /* receive data */ 324 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 325 MUSB2_REG_EPFIFO(0), (void *)&req, sizeof(req)); 326 327 /* copy data into real buffer */ 328 usb2_copy_in(td->pc, 0, &req, sizeof(req)); 329 330 td->offset = sizeof(req); 331 td->remainder = 0; 332 333 /* set pending command */ 334 sc->sc_ep0_cmd = MUSB2_MASK_CSR0L_RXPKTRDY_CLR; 335 336 /* we need set stall or dataend after this */ 337 sc->sc_ep0_busy = 1; 338 339 /* sneak peek the set address */ 340 if ((req.bmRequestType == UT_WRITE_DEVICE) && 341 (req.bRequest == UR_SET_ADDRESS)) { 342 sc->sc_dv_addr = req.wValue[0] & 0x7F; 343 } else { 344 sc->sc_dv_addr = 0xFF; 345 } 346 return (0); /* complete */ 347 348not_complete: 349 return (1); /* not complete */ 350} 351 352/* Control endpoint only data handling functions (RX/TX/SYNC) */ 353 354static uint8_t 355musbotg_setup_data_rx(struct musbotg_td *td) 356{ 357 struct usb2_page_search buf_res; 358 struct musbotg_softc *sc; 359 uint16_t count; 360 uint8_t csr; 361 uint8_t got_short; 362 363 /* get pointer to softc */ 364 sc = MUSBOTG_PC2SC(td->pc); 365 366 /* select endpoint 0 */ 367 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); 368 369 /* check if a command is pending */ 370 if (sc->sc_ep0_cmd) { 371 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, sc->sc_ep0_cmd); 372 sc->sc_ep0_cmd = 0; 373 } 374 /* read out FIFO status */ 375 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 376 377 DPRINTFN(4, "csr=0x%02x\n", csr); 378 379 got_short = 0; 380 381 if (csr & (MUSB2_MASK_CSR0L_SETUPEND | 382 MUSB2_MASK_CSR0L_SENTSTALL)) { 383 if (td->remainder == 0) { 384 /* 385 * We are actually complete and have 386 * received the next SETUP 387 */ 388 DPRINTFN(4, "faking complete\n"); 389 return (0); /* complete */ 390 } 391 /* 392 * USB Host Aborted the transfer. 393 */ 394 td->error = 1; 395 return (0); /* complete */ 396 } 397 if (!(csr & MUSB2_MASK_CSR0L_RXPKTRDY)) { 398 return (1); /* not complete */ 399 } 400 /* get the packet byte count */ 401 count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT); 402 403 /* verify the packet byte count */ 404 if (count != td->max_frame_size) { 405 if (count < td->max_frame_size) { 406 /* we have a short packet */ 407 td->short_pkt = 1; 408 got_short = 1; 409 } else { 410 /* invalid USB packet */ 411 td->error = 1; 412 return (0); /* we are complete */ 413 } 414 } 415 /* verify the packet byte count */ 416 if (count > td->remainder) { 417 /* invalid USB packet */ 418 td->error = 1; 419 return (0); /* we are complete */ 420 } 421 while (count > 0) { 422 uint32_t temp; 423 424 usb2_get_page(td->pc, td->offset, &buf_res); 425 426 /* get correct length */ 427 if (buf_res.length > count) { 428 buf_res.length = count; 429 } 430 /* check for unaligned memory address */ 431 if (USB_P2U(buf_res.buffer) & 3) { 432 433 temp = count & ~3; 434 435 if (temp) { 436 /* receive data 4 bytes at a time */ 437 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 438 MUSB2_REG_EPFIFO(0), sc->sc_bounce_buf, 439 temp / 4); 440 } 441 temp = count & 3; 442 if (temp) { 443 /* receive data 1 byte at a time */ 444 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 445 MUSB2_REG_EPFIFO(0), 446 (void *)(&sc->sc_bounce_buf[count / 4]), temp); 447 } 448 usb2_copy_in(td->pc, td->offset, 449 sc->sc_bounce_buf, count); 450 451 /* update offset and remainder */ 452 td->offset += count; 453 td->remainder -= count; 454 break; 455 } 456 /* check if we can optimise */ 457 if (buf_res.length >= 4) { 458 459 /* receive data 4 bytes at a time */ 460 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 461 MUSB2_REG_EPFIFO(0), buf_res.buffer, 462 buf_res.length / 4); 463 464 temp = buf_res.length & ~3; 465 466 /* update counters */ 467 count -= temp; 468 td->offset += temp; 469 td->remainder -= temp; 470 continue; 471 } 472 /* receive data */ 473 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 474 MUSB2_REG_EPFIFO(0), buf_res.buffer, buf_res.length); 475 476 /* update counters */ 477 count -= buf_res.length; 478 td->offset += buf_res.length; 479 td->remainder -= buf_res.length; 480 } 481 482 /* check if we are complete */ 483 if ((td->remainder == 0) || got_short) { 484 if (td->short_pkt) { 485 /* we are complete */ 486 sc->sc_ep0_cmd = MUSB2_MASK_CSR0L_RXPKTRDY_CLR; 487 return (0); 488 } 489 /* else need to receive a zero length packet */ 490 } 491 /* write command - need more data */ 492 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 493 MUSB2_MASK_CSR0L_RXPKTRDY_CLR); 494 return (1); /* not complete */ 495} 496 497static uint8_t 498musbotg_setup_data_tx(struct musbotg_td *td) 499{ 500 struct usb2_page_search buf_res; 501 struct musbotg_softc *sc; 502 uint16_t count; 503 uint8_t csr; 504 505 /* get pointer to softc */ 506 sc = MUSBOTG_PC2SC(td->pc); 507 508 /* select endpoint 0 */ 509 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); 510 511 /* check if a command is pending */ 512 if (sc->sc_ep0_cmd) { 513 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, sc->sc_ep0_cmd); 514 sc->sc_ep0_cmd = 0; 515 } 516 /* read out FIFO status */ 517 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 518 519 DPRINTFN(4, "csr=0x%02x\n", csr); 520 521 if (csr & (MUSB2_MASK_CSR0L_SETUPEND | 522 MUSB2_MASK_CSR0L_SENTSTALL)) { 523 /* 524 * The current transfer was aborted 525 * by the USB Host 526 */ 527 td->error = 1; 528 return (0); /* complete */ 529 } 530 if (csr & MUSB2_MASK_CSR0L_TXPKTRDY) { 531 return (1); /* not complete */ 532 } 533 count = td->max_frame_size; 534 if (td->remainder < count) { 535 /* we have a short packet */ 536 td->short_pkt = 1; 537 count = td->remainder; 538 } 539 while (count > 0) { 540 uint32_t temp; 541 542 usb2_get_page(td->pc, td->offset, &buf_res); 543 544 /* get correct length */ 545 if (buf_res.length > count) { 546 buf_res.length = count; 547 } 548 /* check for unaligned memory address */ 549 if (USB_P2U(buf_res.buffer) & 3) { 550 551 usb2_copy_out(td->pc, td->offset, 552 sc->sc_bounce_buf, count); 553 554 temp = count & ~3; 555 556 if (temp) { 557 /* transmit data 4 bytes at a time */ 558 bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 559 MUSB2_REG_EPFIFO(0), sc->sc_bounce_buf, 560 temp / 4); 561 } 562 temp = count & 3; 563 if (temp) { 564 /* receive data 1 byte at a time */ 565 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 566 MUSB2_REG_EPFIFO(0), 567 ((void *)&sc->sc_bounce_buf[count / 4]), temp); 568 } 569 /* update offset and remainder */ 570 td->offset += count; 571 td->remainder -= count; 572 break; 573 } 574 /* check if we can optimise */ 575 if (buf_res.length >= 4) { 576 577 /* transmit data 4 bytes at a time */ 578 bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 579 MUSB2_REG_EPFIFO(0), buf_res.buffer, 580 buf_res.length / 4); 581 582 temp = buf_res.length & ~3; 583 584 /* update counters */ 585 count -= temp; 586 td->offset += temp; 587 td->remainder -= temp; 588 continue; 589 } 590 /* transmit data */ 591 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 592 MUSB2_REG_EPFIFO(0), buf_res.buffer, buf_res.length); 593 594 /* update counters */ 595 count -= buf_res.length; 596 td->offset += buf_res.length; 597 td->remainder -= buf_res.length; 598 } 599 600 /* check remainder */ 601 if (td->remainder == 0) { 602 if (td->short_pkt) { 603 sc->sc_ep0_cmd = MUSB2_MASK_CSR0L_TXPKTRDY; 604 return (0); /* complete */ 605 } 606 /* else we need to transmit a short packet */ 607 } 608 /* write command */ 609 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 610 MUSB2_MASK_CSR0L_TXPKTRDY); 611 612 return (1); /* not complete */ 613} 614 615static uint8_t 616musbotg_setup_status(struct musbotg_td *td) 617{ 618 struct musbotg_softc *sc; 619 uint8_t csr; 620 621 /* get pointer to softc */ 622 sc = MUSBOTG_PC2SC(td->pc); 623 624 /* select endpoint 0 */ 625 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); 626 627 if (sc->sc_ep0_busy) { 628 sc->sc_ep0_busy = 0; 629 sc->sc_ep0_cmd |= MUSB2_MASK_CSR0L_DATAEND; 630 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, sc->sc_ep0_cmd); 631 sc->sc_ep0_cmd = 0; 632 } 633 /* read out FIFO status */ 634 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 635 636 DPRINTFN(4, "csr=0x%02x\n", csr); 637 638 if (csr & MUSB2_MASK_CSR0L_DATAEND) { 639 /* wait for interrupt */ 640 return (1); /* not complete */ 641 } 642 if (sc->sc_dv_addr != 0xFF) { 643 /* write function address */ 644 musbotg_set_address(sc, sc->sc_dv_addr); 645 } 646 return (0); /* complete */ 647} 648 649static uint8_t 650musbotg_data_rx(struct musbotg_td *td) 651{ 652 struct usb2_page_search buf_res; 653 struct musbotg_softc *sc; 654 uint16_t count; 655 uint8_t csr; 656 uint8_t to; 657 uint8_t got_short; 658 659 to = 8; /* don't loop forever! */ 660 got_short = 0; 661 662 /* get pointer to softc */ 663 sc = MUSBOTG_PC2SC(td->pc); 664 665 /* select endpoint */ 666 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, td->ep_no); 667 668repeat: 669 /* read out FIFO status */ 670 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL); 671 672 DPRINTFN(4, "csr=0x%02x\n", csr); 673 674 /* clear overrun */ 675 if (csr & MUSB2_MASK_CSRL_RXOVERRUN) { 676 /* make sure we don't clear "RXPKTRDY" */ 677 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 678 MUSB2_MASK_CSRL_RXPKTRDY); 679 } 680 /* check status */ 681 if (!(csr & MUSB2_MASK_CSRL_RXPKTRDY)) { 682 return (1); /* not complete */ 683 } 684 /* get the packet byte count */ 685 count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT); 686 687 DPRINTFN(4, "count=0x%04x\n", count); 688 689 /* 690 * Check for short or invalid packet: 691 */ 692 if (count != td->max_frame_size) { 693 if (count < td->max_frame_size) { 694 /* we have a short packet */ 695 td->short_pkt = 1; 696 got_short = 1; 697 } else { 698 /* invalid USB packet */ 699 td->error = 1; 700 return (0); /* we are complete */ 701 } 702 } 703 /* verify the packet byte count */ 704 if (count > td->remainder) { 705 /* invalid USB packet */ 706 td->error = 1; 707 return (0); /* we are complete */ 708 } 709 while (count > 0) { 710 uint32_t temp; 711 712 usb2_get_page(td->pc, td->offset, &buf_res); 713 714 /* get correct length */ 715 if (buf_res.length > count) { 716 buf_res.length = count; 717 } 718 /* check for unaligned memory address */ 719 if (USB_P2U(buf_res.buffer) & 3) { 720 721 temp = count & ~3; 722 723 if (temp) { 724 /* receive data 4 bytes at a time */ 725 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 726 MUSB2_REG_EPFIFO(td->ep_no), sc->sc_bounce_buf, 727 temp / 4); 728 } 729 temp = count & 3; 730 if (temp) { 731 /* receive data 1 byte at a time */ 732 bus_space_read_multi_1(sc->sc_io_tag, 733 sc->sc_io_hdl, MUSB2_REG_EPFIFO(td->ep_no), 734 ((void *)&sc->sc_bounce_buf[count / 4]), temp); 735 } 736 usb2_copy_in(td->pc, td->offset, 737 sc->sc_bounce_buf, count); 738 739 /* update offset and remainder */ 740 td->offset += count; 741 td->remainder -= count; 742 break; 743 } 744 /* check if we can optimise */ 745 if (buf_res.length >= 4) { 746 747 /* receive data 4 bytes at a time */ 748 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 749 MUSB2_REG_EPFIFO(td->ep_no), buf_res.buffer, 750 buf_res.length / 4); 751 752 temp = buf_res.length & ~3; 753 754 /* update counters */ 755 count -= temp; 756 td->offset += temp; 757 td->remainder -= temp; 758 continue; 759 } 760 /* receive data */ 761 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 762 MUSB2_REG_EPFIFO(td->ep_no), buf_res.buffer, 763 buf_res.length); 764 765 /* update counters */ 766 count -= buf_res.length; 767 td->offset += buf_res.length; 768 td->remainder -= buf_res.length; 769 } 770 771 /* clear status bits */ 772 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 0); 773 774 /* check if we are complete */ 775 if ((td->remainder == 0) || got_short) { 776 if (td->short_pkt) { 777 /* we are complete */ 778 return (0); 779 } 780 /* else need to receive a zero length packet */ 781 } 782 if (--to) { 783 goto repeat; 784 } 785 return (1); /* not complete */ 786} 787 788static uint8_t 789musbotg_data_tx(struct musbotg_td *td) 790{ 791 struct usb2_page_search buf_res; 792 struct musbotg_softc *sc; 793 uint16_t count; 794 uint8_t csr; 795 uint8_t to; 796 797 to = 8; /* don't loop forever! */ 798 799 /* get pointer to softc */ 800 sc = MUSBOTG_PC2SC(td->pc); 801 802 /* select endpoint */ 803 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, td->ep_no); 804 805repeat: 806 807 /* read out FIFO status */ 808 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 809 810 DPRINTFN(4, "csr=0x%02x\n", csr); 811 812 if (csr & (MUSB2_MASK_CSRL_TXINCOMP | 813 MUSB2_MASK_CSRL_TXUNDERRUN)) { 814 /* clear status bits */ 815 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0); 816 } 817 if (csr & MUSB2_MASK_CSRL_TXPKTRDY) { 818 return (1); /* not complete */ 819 } 820 /* check for short packet */ 821 count = td->max_frame_size; 822 if (td->remainder < count) { 823 /* we have a short packet */ 824 td->short_pkt = 1; 825 count = td->remainder; 826 } 827 while (count > 0) { 828 uint32_t temp; 829 830 usb2_get_page(td->pc, td->offset, &buf_res); 831 832 /* get correct length */ 833 if (buf_res.length > count) { 834 buf_res.length = count; 835 } 836 /* check for unaligned memory address */ 837 if (USB_P2U(buf_res.buffer) & 3) { 838 839 usb2_copy_out(td->pc, td->offset, 840 sc->sc_bounce_buf, count); 841 842 temp = count & ~3; 843 844 if (temp) { 845 /* transmit data 4 bytes at a time */ 846 bus_space_write_multi_4(sc->sc_io_tag, 847 sc->sc_io_hdl, MUSB2_REG_EPFIFO(td->ep_no), 848 sc->sc_bounce_buf, temp / 4); 849 } 850 temp = count & 3; 851 if (temp) { 852 /* receive data 1 byte at a time */ 853 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 854 MUSB2_REG_EPFIFO(td->ep_no), 855 ((void *)&sc->sc_bounce_buf[count / 4]), temp); 856 } 857 /* update offset and remainder */ 858 td->offset += count; 859 td->remainder -= count; 860 break; 861 } 862 /* check if we can optimise */ 863 if (buf_res.length >= 4) { 864 865 /* transmit data 4 bytes at a time */ 866 bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 867 MUSB2_REG_EPFIFO(td->ep_no), buf_res.buffer, 868 buf_res.length / 4); 869 870 temp = buf_res.length & ~3; 871 872 /* update counters */ 873 count -= temp; 874 td->offset += temp; 875 td->remainder -= temp; 876 continue; 877 } 878 /* transmit data */ 879 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 880 MUSB2_REG_EPFIFO(td->ep_no), buf_res.buffer, 881 buf_res.length); 882 883 /* update counters */ 884 count -= buf_res.length; 885 td->offset += buf_res.length; 886 td->remainder -= buf_res.length; 887 } 888 889 /* write command */ 890 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 891 MUSB2_MASK_CSRL_TXPKTRDY); 892 893 /* check remainder */ 894 if (td->remainder == 0) { 895 if (td->short_pkt) { 896 return (0); /* complete */ 897 } 898 /* else we need to transmit a short packet */ 899 } 900 if (--to) { 901 goto repeat; 902 } 903 return (1); /* not complete */ 904} 905 906static uint8_t 907musbotg_xfer_do_fifo(struct usb2_xfer *xfer) 908{ 909 struct musbotg_softc *sc; 910 struct musbotg_td *td; 911 912 DPRINTFN(8, "\n"); 913 914 td = xfer->td_transfer_cache; 915 while (1) { 916 if ((td->func) (td)) { 917 /* operation in progress */ 918 break; 919 } 920 if (((void *)td) == xfer->td_transfer_last) { 921 goto done; 922 } 923 if (td->error) { 924 goto done; 925 } else if (td->remainder > 0) { 926 /* 927 * We had a short transfer. If there is no alternate 928 * next, stop processing ! 929 */ 930 if (!td->alt_next) { 931 goto done; 932 } 933 } 934 /* 935 * Fetch the next transfer descriptor and transfer 936 * some flags to the next transfer descriptor 937 */ 938 td = td->obj_next; 939 xfer->td_transfer_cache = td; 940 } 941 return (1); /* not complete */ 942 943done: 944 sc = xfer->usb2_sc; 945 946 /* compute all actual lengths */ 947 948 musbotg_standard_done(xfer); 949 950 return (0); /* complete */ 951} 952 953static void 954musbotg_interrupt_poll(struct musbotg_softc *sc) 955{ 956 struct usb2_xfer *xfer; 957 958repeat: 959 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 960 if (!musbotg_xfer_do_fifo(xfer)) { 961 /* queue has been modified */ 962 goto repeat; 963 } 964 } 965} 966 967static void 968musbotg_vbus_interrupt(struct usb2_bus *bus, uint8_t is_on) 969{ 970 struct musbotg_softc *sc = MUSBOTG_BUS2SC(bus); 971 972 DPRINTFN(4, "vbus = %u\n", is_on); 973 974 USB_BUS_LOCK(&sc->sc_bus); 975 if (is_on) { 976 if (!sc->sc_flags.status_vbus) { 977 sc->sc_flags.status_vbus = 1; 978 979 /* complete root HUB interrupt endpoint */ 980 981 usb2_sw_transfer(&sc->sc_root_intr, 982 &musbotg_root_intr_done); 983 } 984 } else { 985 if (sc->sc_flags.status_vbus) { 986 sc->sc_flags.status_vbus = 0; 987 sc->sc_flags.status_bus_reset = 0; 988 sc->sc_flags.status_suspend = 0; 989 sc->sc_flags.change_suspend = 0; 990 sc->sc_flags.change_connect = 1; 991 992 /* complete root HUB interrupt endpoint */ 993 994 usb2_sw_transfer(&sc->sc_root_intr, 995 &musbotg_root_intr_done); 996 } 997 } 998 999 USB_BUS_UNLOCK(&sc->sc_bus); 1000} 1001 1002void 1003musbotg_interrupt(struct musbotg_softc *sc) 1004{ 1005 uint16_t rx_status; 1006 uint16_t tx_status; 1007 uint8_t usb_status; 1008 uint8_t temp; 1009 uint8_t to = 2; 1010 1011 USB_BUS_LOCK(&sc->sc_bus); 1012 1013repeat: 1014 1015 /* read all interrupt registers */ 1016 usb_status = MUSB2_READ_1(sc, MUSB2_REG_INTUSB); 1017 1018 /* read all FIFO interrupts */ 1019 rx_status = MUSB2_READ_2(sc, MUSB2_REG_INTRX); 1020 tx_status = MUSB2_READ_2(sc, MUSB2_REG_INTTX); 1021 1022 /* check for any bus state change interrupts */ 1023 1024 if (usb_status & (MUSB2_MASK_IRESET | 1025 MUSB2_MASK_IRESUME | MUSB2_MASK_ISUSP)) { 1026 1027 DPRINTFN(4, "real bus interrupt 0x%08x\n", usb_status); 1028 1029 if (usb_status & MUSB2_MASK_IRESET) { 1030 1031 /* set correct state */ 1032 sc->sc_flags.status_bus_reset = 1; 1033 sc->sc_flags.status_suspend = 0; 1034 sc->sc_flags.change_suspend = 0; 1035 sc->sc_flags.change_connect = 1; 1036 1037 /* determine line speed */ 1038 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER); 1039 if (temp & MUSB2_MASK_HSMODE) 1040 sc->sc_flags.status_high_speed = 1; 1041 else 1042 sc->sc_flags.status_high_speed = 0; 1043 1044 /* 1045 * After reset all interrupts are on and we need to 1046 * turn them off! 1047 */ 1048 temp = MUSB2_MASK_IRESET; 1049 /* disable resume interrupt */ 1050 temp &= ~MUSB2_MASK_IRESUME; 1051 /* enable suspend interrupt */ 1052 temp |= MUSB2_MASK_ISUSP; 1053 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, temp); 1054 /* disable TX and RX interrupts */ 1055 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, 0); 1056 MUSB2_WRITE_2(sc, MUSB2_REG_INTRXE, 0); 1057 } 1058 /* 1059 * If RXRSM and RXSUSP is set at the same time we interpret 1060 * that like RESUME. Resume is set when there is at least 3 1061 * milliseconds of inactivity on the USB BUS. 1062 */ 1063 if (usb_status & MUSB2_MASK_IRESUME) { 1064 if (sc->sc_flags.status_suspend) { 1065 sc->sc_flags.status_suspend = 0; 1066 sc->sc_flags.change_suspend = 1; 1067 1068 temp = MUSB2_READ_1(sc, MUSB2_REG_INTUSBE); 1069 /* disable resume interrupt */ 1070 temp &= ~MUSB2_MASK_IRESUME; 1071 /* enable suspend interrupt */ 1072 temp |= MUSB2_MASK_ISUSP; 1073 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, temp); 1074 } 1075 } else if (usb_status & MUSB2_MASK_ISUSP) { 1076 if (!sc->sc_flags.status_suspend) { 1077 sc->sc_flags.status_suspend = 1; 1078 sc->sc_flags.change_suspend = 1; 1079 1080 temp = MUSB2_READ_1(sc, MUSB2_REG_INTUSBE); 1081 /* disable suspend interrupt */ 1082 temp &= ~MUSB2_MASK_ISUSP; 1083 /* enable resume interrupt */ 1084 temp |= MUSB2_MASK_IRESUME; 1085 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, temp); 1086 } 1087 } 1088 /* complete root HUB interrupt endpoint */ 1089 1090 usb2_sw_transfer(&sc->sc_root_intr, 1091 &musbotg_root_intr_done); 1092 } 1093 /* check for any endpoint interrupts */ 1094 1095 if (rx_status || tx_status) { 1096 DPRINTFN(4, "real endpoint interrupt " 1097 "rx=0x%04x, tx=0x%04x\n", rx_status, tx_status); 1098 } 1099 /* poll one time regardless of FIFO status */ 1100 1101 musbotg_interrupt_poll(sc); 1102 1103 if (--to) 1104 goto repeat; 1105 1106 USB_BUS_UNLOCK(&sc->sc_bus); 1107} 1108 1109static void 1110musbotg_setup_standard_chain_sub(struct musbotg_std_temp *temp) 1111{ 1112 struct musbotg_td *td; 1113 1114 /* get current Transfer Descriptor */ 1115 td = temp->td_next; 1116 temp->td = td; 1117 1118 /* prepare for next TD */ 1119 temp->td_next = td->obj_next; 1120 1121 /* fill out the Transfer Descriptor */ 1122 td->func = temp->func; 1123 td->pc = temp->pc; 1124 td->offset = temp->offset; 1125 td->remainder = temp->len; 1126 td->error = 0; 1127 td->did_stall = 0; 1128 td->short_pkt = temp->short_pkt; 1129 td->alt_next = temp->setup_alt_next; 1130} 1131 1132static void 1133musbotg_setup_standard_chain(struct usb2_xfer *xfer) 1134{ 1135 struct musbotg_std_temp temp; 1136 struct musbotg_softc *sc; 1137 struct musbotg_td *td; 1138 uint32_t x; 1139 uint8_t ep_no; 1140 1141 DPRINTFN(8, "addr=%d endpt=%d sumlen=%d speed=%d\n", 1142 xfer->address, UE_GET_ADDR(xfer->endpoint), 1143 xfer->sumlen, usb2_get_speed(xfer->udev)); 1144 1145 temp.max_frame_size = xfer->max_frame_size; 1146 1147 td = xfer->td_start[0]; 1148 xfer->td_transfer_first = td; 1149 xfer->td_transfer_cache = td; 1150 1151 /* setup temp */ 1152 1153 temp.td = NULL; 1154 temp.td_next = xfer->td_start[0]; 1155 temp.setup_alt_next = xfer->flags_int.short_frames_ok; 1156 temp.offset = 0; 1157 1158 sc = xfer->usb2_sc; 1159 ep_no = (xfer->endpoint & UE_ADDR); 1160 1161 /* check if we should prepend a setup message */ 1162 1163 if (xfer->flags_int.control_xfr) { 1164 if (xfer->flags_int.control_hdr) { 1165 1166 temp.func = &musbotg_setup_rx; 1167 temp.len = xfer->frlengths[0]; 1168 temp.pc = xfer->frbuffers + 0; 1169 temp.short_pkt = temp.len ? 1 : 0; 1170 1171 musbotg_setup_standard_chain_sub(&temp); 1172 } 1173 x = 1; 1174 } else { 1175 x = 0; 1176 } 1177 1178 if (x != xfer->nframes) { 1179 if (xfer->endpoint & UE_DIR_IN) { 1180 if (xfer->flags_int.control_xfr) 1181 temp.func = &musbotg_setup_data_tx; 1182 else 1183 temp.func = &musbotg_data_tx; 1184 } else { 1185 if (xfer->flags_int.control_xfr) 1186 temp.func = &musbotg_setup_data_rx; 1187 else 1188 temp.func = &musbotg_data_rx; 1189 } 1190 1191 /* setup "pc" pointer */ 1192 temp.pc = xfer->frbuffers + x; 1193 } 1194 while (x != xfer->nframes) { 1195 1196 /* DATA0 / DATA1 message */ 1197 1198 temp.len = xfer->frlengths[x]; 1199 1200 x++; 1201 1202 if (x == xfer->nframes) { 1203 temp.setup_alt_next = 0; 1204 } 1205 if (temp.len == 0) { 1206 1207 /* make sure that we send an USB packet */ 1208 1209 temp.short_pkt = 0; 1210 1211 } else { 1212 1213 /* regular data transfer */ 1214 1215 temp.short_pkt = (xfer->flags.force_short_xfer) ? 0 : 1; 1216 } 1217 1218 musbotg_setup_standard_chain_sub(&temp); 1219 1220 if (xfer->flags_int.isochronous_xfr) { 1221 temp.offset += temp.len; 1222 } else { 1223 /* get next Page Cache pointer */ 1224 temp.pc = xfer->frbuffers + x; 1225 } 1226 } 1227 1228 /* always setup a valid "pc" pointer for status and sync */ 1229 temp.pc = xfer->frbuffers + 0; 1230 1231 /* check if we should append a status stage */ 1232 1233 if (xfer->flags_int.control_xfr && 1234 !xfer->flags_int.control_act) { 1235 1236 /* 1237 * Send a DATA1 message and invert the current 1238 * endpoint direction. 1239 */ 1240 temp.func = &musbotg_setup_status; 1241 temp.len = 0; 1242 temp.short_pkt = 0; 1243 1244 musbotg_setup_standard_chain_sub(&temp); 1245 } 1246 /* must have at least one frame! */ 1247 td = temp.td; 1248 xfer->td_transfer_last = td; 1249} 1250 1251static void 1252musbotg_timeout(void *arg) 1253{ 1254 struct usb2_xfer *xfer = arg; 1255 struct musbotg_softc *sc = xfer->usb2_sc; 1256 1257 DPRINTFN(1, "xfer=%p\n", xfer); 1258 1259 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1260 1261 /* transfer is transferred */ 1262 musbotg_device_done(xfer, USB_ERR_TIMEOUT); 1263 1264 USB_BUS_UNLOCK(&sc->sc_bus); 1265} 1266 1267static void 1268musbotg_ep_int_set(struct usb2_xfer *xfer, uint8_t on) 1269{ 1270 struct musbotg_softc *sc = xfer->usb2_sc; 1271 uint16_t temp; 1272 uint8_t ep_no = xfer->endpoint & UE_ADDR; 1273 1274 /* 1275 * Only enable the endpoint interrupt when we are 1276 * actually waiting for data, hence we are dealing 1277 * with level triggered interrupts ! 1278 */ 1279 if (ep_no == 0) { 1280 temp = MUSB2_READ_2(sc, MUSB2_REG_INTTXE); 1281 if (on) 1282 temp |= MUSB2_MASK_EPINT(0); 1283 else 1284 temp &= ~MUSB2_MASK_EPINT(0); 1285 1286 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, temp); 1287 } else { 1288 if (USB_GET_DATA_ISREAD(xfer)) { 1289 temp = MUSB2_READ_2(sc, MUSB2_REG_INTRXE); 1290 if (on) 1291 temp |= MUSB2_MASK_EPINT(ep_no); 1292 else 1293 temp &= ~MUSB2_MASK_EPINT(ep_no); 1294 MUSB2_WRITE_2(sc, MUSB2_REG_INTRXE, temp); 1295 1296 } else { 1297 temp = MUSB2_READ_2(sc, MUSB2_REG_INTTXE); 1298 if (on) 1299 temp |= MUSB2_MASK_EPINT(ep_no); 1300 else 1301 temp &= ~MUSB2_MASK_EPINT(ep_no); 1302 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, temp); 1303 } 1304 } 1305} 1306 1307static void 1308musbotg_start_standard_chain(struct usb2_xfer *xfer) 1309{ 1310 DPRINTFN(8, "\n"); 1311 1312 /* poll one time */ 1313 if (musbotg_xfer_do_fifo(xfer)) { 1314 1315 musbotg_ep_int_set(xfer, 1); 1316 1317 DPRINTFN(14, "enabled interrupts on endpoint\n"); 1318 1319 /* put transfer on interrupt queue */ 1320 usb2_transfer_enqueue(&xfer->udev->bus->intr_q, xfer); 1321 1322 /* start timeout, if any */ 1323 if (xfer->timeout != 0) { 1324 usb2_transfer_timeout_ms(xfer, 1325 &musbotg_timeout, xfer->timeout); 1326 } 1327 } 1328} 1329 1330static void 1331musbotg_root_intr_done(struct usb2_xfer *xfer, 1332 struct usb2_sw_transfer *std) 1333{ 1334 struct musbotg_softc *sc = xfer->usb2_sc; 1335 1336 DPRINTFN(8, "\n"); 1337 1338 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1339 1340 if (std->state != USB_SW_TR_PRE_DATA) { 1341 if (std->state == USB_SW_TR_PRE_CALLBACK) { 1342 /* transfer transferred */ 1343 musbotg_device_done(xfer, std->err); 1344 } 1345 goto done; 1346 } 1347 /* setup buffer */ 1348 std->ptr = sc->sc_hub_idata; 1349 std->len = sizeof(sc->sc_hub_idata); 1350 1351 /* set port bit */ 1352 sc->sc_hub_idata[0] = 0x02; /* we only have one port */ 1353 1354done: 1355 return; 1356} 1357 1358static usb2_error_t 1359musbotg_standard_done_sub(struct usb2_xfer *xfer) 1360{ 1361 struct musbotg_td *td; 1362 uint32_t len; 1363 uint8_t error; 1364 1365 DPRINTFN(8, "\n"); 1366 1367 td = xfer->td_transfer_cache; 1368 1369 do { 1370 len = td->remainder; 1371 1372 if (xfer->aframes != xfer->nframes) { 1373 /* 1374 * Verify the length and subtract 1375 * the remainder from "frlengths[]": 1376 */ 1377 if (len > xfer->frlengths[xfer->aframes]) { 1378 td->error = 1; 1379 } else { 1380 xfer->frlengths[xfer->aframes] -= len; 1381 } 1382 } 1383 /* Check for transfer error */ 1384 if (td->error) { 1385 /* the transfer is finished */ 1386 error = 1; 1387 td = NULL; 1388 break; 1389 } 1390 /* Check for short transfer */ 1391 if (len > 0) { 1392 if (xfer->flags_int.short_frames_ok) { 1393 /* follow alt next */ 1394 if (td->alt_next) { 1395 td = td->obj_next; 1396 } else { 1397 td = NULL; 1398 } 1399 } else { 1400 /* the transfer is finished */ 1401 td = NULL; 1402 } 1403 error = 0; 1404 break; 1405 } 1406 td = td->obj_next; 1407 1408 /* this USB frame is complete */ 1409 error = 0; 1410 break; 1411 1412 } while (0); 1413 1414 /* update transfer cache */ 1415 1416 xfer->td_transfer_cache = td; 1417 1418 return (error ? 1419 USB_ERR_STALLED : USB_ERR_NORMAL_COMPLETION); 1420} 1421 1422static void 1423musbotg_standard_done(struct usb2_xfer *xfer) 1424{ 1425 usb2_error_t err = 0; 1426 1427 DPRINTFN(12, "xfer=%p pipe=%p transfer done\n", 1428 xfer, xfer->pipe); 1429 1430 /* reset scanner */ 1431 1432 xfer->td_transfer_cache = xfer->td_transfer_first; 1433 1434 if (xfer->flags_int.control_xfr) { 1435 1436 if (xfer->flags_int.control_hdr) { 1437 1438 err = musbotg_standard_done_sub(xfer); 1439 } 1440 xfer->aframes = 1; 1441 1442 if (xfer->td_transfer_cache == NULL) { 1443 goto done; 1444 } 1445 } 1446 while (xfer->aframes != xfer->nframes) { 1447 1448 err = musbotg_standard_done_sub(xfer); 1449 xfer->aframes++; 1450 1451 if (xfer->td_transfer_cache == NULL) { 1452 goto done; 1453 } 1454 } 1455 1456 if (xfer->flags_int.control_xfr && 1457 !xfer->flags_int.control_act) { 1458 1459 err = musbotg_standard_done_sub(xfer); 1460 } 1461done: 1462 musbotg_device_done(xfer, err); 1463} 1464 1465/*------------------------------------------------------------------------* 1466 * musbotg_device_done 1467 * 1468 * NOTE: this function can be called more than one time on the 1469 * same USB transfer! 1470 *------------------------------------------------------------------------*/ 1471static void 1472musbotg_device_done(struct usb2_xfer *xfer, usb2_error_t error) 1473{ 1474 USB_BUS_LOCK_ASSERT(xfer->udev->bus, MA_OWNED); 1475 1476 DPRINTFN(2, "xfer=%p, pipe=%p, error=%d\n", 1477 xfer, xfer->pipe, error); 1478 1479 if (xfer->flags_int.usb2_mode == USB_MODE_DEVICE) { 1480 1481 musbotg_ep_int_set(xfer, 0); 1482 1483 DPRINTFN(14, "disabled interrupts on endpoint\n"); 1484 } 1485 /* dequeue transfer and start next transfer */ 1486 usb2_transfer_done(xfer, error); 1487} 1488 1489static void 1490musbotg_set_stall(struct usb2_device *udev, struct usb2_xfer *xfer, 1491 struct usb2_pipe *pipe) 1492{ 1493 struct musbotg_softc *sc; 1494 uint8_t ep_no; 1495 1496 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 1497 1498 DPRINTFN(4, "pipe=%p\n", pipe); 1499 1500 if (xfer) { 1501 /* cancel any ongoing transfers */ 1502 musbotg_device_done(xfer, USB_ERR_STALLED); 1503 } 1504 /* set FORCESTALL */ 1505 sc = MUSBOTG_BUS2SC(udev->bus); 1506 1507 ep_no = (pipe->edesc->bEndpointAddress & UE_ADDR); 1508 1509 /* select endpoint */ 1510 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, ep_no); 1511 1512 if (pipe->edesc->bEndpointAddress & UE_DIR_IN) { 1513 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 1514 MUSB2_MASK_CSRL_TXSENDSTALL); 1515 } else { 1516 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 1517 MUSB2_MASK_CSRL_RXSENDSTALL); 1518 } 1519} 1520 1521static void 1522musbotg_clear_stall_sub(struct musbotg_softc *sc, uint16_t wMaxPacket, 1523 uint8_t ep_no, uint8_t ep_type, uint8_t ep_dir) 1524{ 1525 uint16_t mps; 1526 uint16_t temp; 1527 uint8_t csr; 1528 1529 if (ep_type == UE_CONTROL) { 1530 /* clearing stall is not needed */ 1531 return; 1532 } 1533 /* select endpoint */ 1534 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, ep_no); 1535 1536 /* compute max frame size */ 1537 mps = wMaxPacket & 0x7FF; 1538 switch ((wMaxPacket >> 11) & 3) { 1539 case 1: 1540 mps *= 2; 1541 break; 1542 case 2: 1543 mps *= 3; 1544 break; 1545 default: 1546 break; 1547 } 1548 1549 if (ep_dir == UE_DIR_IN) { 1550 1551 temp = 0; 1552 1553 /* Configure endpoint */ 1554 switch (ep_type) { 1555 case UE_INTERRUPT: 1556 MUSB2_WRITE_1(sc, MUSB2_REG_TXMAXP, wMaxPacket); 1557 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, 1558 MUSB2_MASK_CSRH_TXMODE | temp); 1559 break; 1560 case UE_ISOCHRONOUS: 1561 MUSB2_WRITE_1(sc, MUSB2_REG_TXMAXP, wMaxPacket); 1562 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, 1563 MUSB2_MASK_CSRH_TXMODE | 1564 MUSB2_MASK_CSRH_TXISO | temp); 1565 break; 1566 case UE_BULK: 1567 MUSB2_WRITE_1(sc, MUSB2_REG_TXMAXP, wMaxPacket); 1568 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, 1569 MUSB2_MASK_CSRH_TXMODE | temp); 1570 break; 1571 default: 1572 break; 1573 } 1574 1575 /* Need to flush twice in case of double bufring */ 1576 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 1577 if (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) { 1578 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 1579 MUSB2_MASK_CSRL_TXFFLUSH); 1580 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 1581 if (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) { 1582 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 1583 MUSB2_MASK_CSRL_TXFFLUSH); 1584 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 1585 } 1586 } 1587 /* reset data toggle */ 1588 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 1589 MUSB2_MASK_CSRL_TXDT_CLR); 1590 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0); 1591 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 1592 1593 /* set double/single buffering */ 1594 temp = MUSB2_READ_2(sc, MUSB2_REG_TXDBDIS); 1595 if (mps <= (sc->sc_hw_ep_profile[ep_no]. 1596 max_in_frame_size / 2)) { 1597 /* double buffer */ 1598 temp &= ~(1 << ep_no); 1599 } else { 1600 /* single buffer */ 1601 temp |= (1 << ep_no); 1602 } 1603 MUSB2_WRITE_2(sc, MUSB2_REG_TXDBDIS, temp); 1604 1605 /* clear sent stall */ 1606 if (csr & MUSB2_MASK_CSRL_TXSENTSTALL) { 1607 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0); 1608 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 1609 } 1610 } else { 1611 1612 temp = 0; 1613 1614 /* Configure endpoint */ 1615 switch (ep_type) { 1616 case UE_INTERRUPT: 1617 MUSB2_WRITE_1(sc, MUSB2_REG_RXMAXP, wMaxPacket); 1618 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH, 1619 MUSB2_MASK_CSRH_RXNYET | temp); 1620 break; 1621 case UE_ISOCHRONOUS: 1622 MUSB2_WRITE_1(sc, MUSB2_REG_RXMAXP, wMaxPacket); 1623 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH, 1624 MUSB2_MASK_CSRH_RXNYET | 1625 MUSB2_MASK_CSRH_RXISO | temp); 1626 break; 1627 case UE_BULK: 1628 MUSB2_WRITE_1(sc, MUSB2_REG_RXMAXP, wMaxPacket); 1629 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH, temp); 1630 break; 1631 default: 1632 break; 1633 } 1634 1635 /* Need to flush twice in case of double bufring */ 1636 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL); 1637 if (csr & MUSB2_MASK_CSRL_RXPKTRDY) { 1638 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 1639 MUSB2_MASK_CSRL_RXFFLUSH); 1640 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL); 1641 if (csr & MUSB2_MASK_CSRL_RXPKTRDY) { 1642 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 1643 MUSB2_MASK_CSRL_RXFFLUSH); 1644 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL); 1645 } 1646 } 1647 /* reset data toggle */ 1648 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 1649 MUSB2_MASK_CSRL_RXDT_CLR); 1650 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 0); 1651 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL); 1652 1653 /* set double/single buffering */ 1654 temp = MUSB2_READ_2(sc, MUSB2_REG_RXDBDIS); 1655 if (mps <= (sc->sc_hw_ep_profile[ep_no]. 1656 max_out_frame_size / 2)) { 1657 /* double buffer */ 1658 temp &= ~(1 << ep_no); 1659 } else { 1660 /* single buffer */ 1661 temp |= (1 << ep_no); 1662 } 1663 MUSB2_WRITE_2(sc, MUSB2_REG_RXDBDIS, temp); 1664 1665 /* clear sent stall */ 1666 if (csr & MUSB2_MASK_CSRL_RXSENTSTALL) { 1667 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 0); 1668 } 1669 } 1670} 1671 1672static void 1673musbotg_clear_stall(struct usb2_device *udev, struct usb2_pipe *pipe) 1674{ 1675 struct musbotg_softc *sc; 1676 struct usb2_endpoint_descriptor *ed; 1677 1678 DPRINTFN(4, "pipe=%p\n", pipe); 1679 1680 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 1681 1682 /* check mode */ 1683 if (udev->flags.usb2_mode != USB_MODE_DEVICE) { 1684 /* not supported */ 1685 return; 1686 } 1687 /* get softc */ 1688 sc = MUSBOTG_BUS2SC(udev->bus); 1689 1690 /* get endpoint descriptor */ 1691 ed = pipe->edesc; 1692 1693 /* reset endpoint */ 1694 musbotg_clear_stall_sub(sc, 1695 UGETW(ed->wMaxPacketSize), 1696 (ed->bEndpointAddress & UE_ADDR), 1697 (ed->bmAttributes & UE_XFERTYPE), 1698 (ed->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT))); 1699} 1700 1701usb2_error_t 1702musbotg_init(struct musbotg_softc *sc) 1703{ 1704 struct usb2_hw_ep_profile *pf; 1705 uint8_t nrx; 1706 uint8_t ntx; 1707 uint8_t temp; 1708 uint8_t fsize; 1709 uint8_t frx; 1710 uint8_t ftx; 1711 1712 DPRINTFN(1, "start\n"); 1713 1714 /* set up the bus structure */ 1715 sc->sc_bus.usbrev = USB_REV_2_0; 1716 sc->sc_bus.methods = &musbotg_bus_methods; 1717 1718 USB_BUS_LOCK(&sc->sc_bus); 1719 1720 /* turn on clocks */ 1721 1722 if (sc->sc_clocks_on) { 1723 (sc->sc_clocks_on) (sc->sc_clocks_arg); 1724 } 1725 /* wait a little for things to stabilise */ 1726 usb2_pause_mtx(&sc->sc_bus.bus_mtx, 1); 1727 1728 /* disable all interrupts */ 1729 1730 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, 0); 1731 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, 0); 1732 MUSB2_WRITE_2(sc, MUSB2_REG_INTRXE, 0); 1733 1734 /* disable pullup */ 1735 1736 musbotg_pull_common(sc, 0); 1737 1738 /* wait a little bit (10ms) */ 1739 usb2_pause_mtx(&sc->sc_bus.bus_mtx, 10); 1740 1741 /* disable double packet buffering */ 1742 MUSB2_WRITE_2(sc, MUSB2_REG_RXDBDIS, 0xFFFF); 1743 MUSB2_WRITE_2(sc, MUSB2_REG_TXDBDIS, 0xFFFF); 1744 1745 /* enable HighSpeed and ISO Update flags */ 1746 1747 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, 1748 MUSB2_MASK_HSENAB | MUSB2_MASK_ISOUPD); 1749 1750 /* clear Session bit, if set */ 1751 1752 temp = MUSB2_READ_1(sc, MUSB2_REG_DEVCTL); 1753 temp &= ~MUSB2_MASK_SESS; 1754 MUSB2_WRITE_1(sc, MUSB2_REG_DEVCTL, temp); 1755 1756 DPRINTF("DEVCTL=0x%02x\n", temp); 1757 1758 /* disable testmode */ 1759 1760 MUSB2_WRITE_1(sc, MUSB2_REG_TESTMODE, 0); 1761 1762 /* set default value */ 1763 1764 MUSB2_WRITE_1(sc, MUSB2_REG_MISC, 0); 1765 1766 /* select endpoint index 0 */ 1767 1768 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); 1769 1770 /* read out number of endpoints */ 1771 1772 nrx = 1773 (MUSB2_READ_1(sc, MUSB2_REG_EPINFO) / 16); 1774 1775 ntx = 1776 (MUSB2_READ_1(sc, MUSB2_REG_EPINFO) % 16); 1777 1778 /* these numbers exclude the control endpoint */ 1779 1780 DPRINTFN(2, "RX/TX endpoints: %u/%u\n", nrx, ntx); 1781 1782 sc->sc_ep_max = (nrx > ntx) ? nrx : ntx; 1783 if (sc->sc_ep_max == 0) { 1784 DPRINTFN(2, "ERROR: Looks like the clocks are off!\n"); 1785 } 1786 /* read out configuration data */ 1787 1788 sc->sc_conf_data = MUSB2_READ_1(sc, MUSB2_REG_CONFDATA); 1789 1790 DPRINTFN(2, "Config Data: 0x%02x\n", 1791 sc->sc_conf_data); 1792 1793 DPRINTFN(2, "HW version: 0x%04x\n", 1794 MUSB2_READ_1(sc, MUSB2_REG_HWVERS)); 1795 1796 /* initialise endpoint profiles */ 1797 1798 for (temp = 1; temp <= sc->sc_ep_max; temp++) { 1799 pf = sc->sc_hw_ep_profile + temp; 1800 1801 /* select endpoint */ 1802 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, temp); 1803 1804 fsize = MUSB2_READ_1(sc, MUSB2_REG_FSIZE); 1805 frx = (fsize & MUSB2_MASK_RX_FSIZE) / 16;; 1806 ftx = (fsize & MUSB2_MASK_TX_FSIZE); 1807 1808 DPRINTF("Endpoint %u FIFO size: IN=%u, OUT=%u\n", 1809 temp, pf->max_in_frame_size, 1810 pf->max_out_frame_size); 1811 1812 if (frx && ftx && (temp <= nrx) && (temp <= ntx)) { 1813 pf->max_in_frame_size = 1 << ftx; 1814 pf->max_out_frame_size = 1 << frx; 1815 pf->is_simplex = 0; /* duplex */ 1816 pf->support_multi_buffer = 1; 1817 pf->support_bulk = 1; 1818 pf->support_interrupt = 1; 1819 pf->support_isochronous = 1; 1820 pf->support_in = 1; 1821 pf->support_out = 1; 1822 } else if (frx && (temp <= nrx)) { 1823 pf->max_out_frame_size = 1 << frx; 1824 pf->is_simplex = 1; /* simplex */ 1825 pf->support_multi_buffer = 1; 1826 pf->support_bulk = 1; 1827 pf->support_interrupt = 1; 1828 pf->support_isochronous = 1; 1829 pf->support_out = 1; 1830 } else if (ftx && (temp <= ntx)) { 1831 pf->max_in_frame_size = 1 << ftx; 1832 pf->is_simplex = 1; /* simplex */ 1833 pf->support_multi_buffer = 1; 1834 pf->support_bulk = 1; 1835 pf->support_interrupt = 1; 1836 pf->support_isochronous = 1; 1837 pf->support_in = 1; 1838 } 1839 } 1840 1841 /* turn on default interrupts */ 1842 1843 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, 1844 MUSB2_MASK_IRESET); 1845 1846 musbotg_clocks_off(sc); 1847 1848 USB_BUS_UNLOCK(&sc->sc_bus); 1849 1850 /* catch any lost interrupts */ 1851 1852 musbotg_do_poll(&sc->sc_bus); 1853 1854 return (0); /* success */ 1855} 1856 1857void 1858musbotg_uninit(struct musbotg_softc *sc) 1859{ 1860 USB_BUS_LOCK(&sc->sc_bus); 1861 1862 /* disable all interrupts */ 1863 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, 0); 1864 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, 0); 1865 MUSB2_WRITE_2(sc, MUSB2_REG_INTRXE, 0); 1866 1867 sc->sc_flags.port_powered = 0; 1868 sc->sc_flags.status_vbus = 0; 1869 sc->sc_flags.status_bus_reset = 0; 1870 sc->sc_flags.status_suspend = 0; 1871 sc->sc_flags.change_suspend = 0; 1872 sc->sc_flags.change_connect = 1; 1873 1874 musbotg_pull_down(sc); 1875 musbotg_clocks_off(sc); 1876 USB_BUS_UNLOCK(&sc->sc_bus); 1877} 1878 1879void 1880musbotg_suspend(struct musbotg_softc *sc) 1881{ 1882 return; 1883} 1884 1885void 1886musbotg_resume(struct musbotg_softc *sc) 1887{ 1888 return; 1889} 1890 1891static void 1892musbotg_do_poll(struct usb2_bus *bus) 1893{ 1894 struct musbotg_softc *sc = MUSBOTG_BUS2SC(bus); 1895 1896 USB_BUS_LOCK(&sc->sc_bus); 1897 musbotg_interrupt_poll(sc); 1898 musbotg_root_ctrl_poll(sc); 1899 USB_BUS_UNLOCK(&sc->sc_bus); 1900} 1901 1902/*------------------------------------------------------------------------* 1903 * musbotg bulk support 1904 *------------------------------------------------------------------------*/ 1905static void 1906musbotg_device_bulk_open(struct usb2_xfer *xfer) 1907{ 1908 return; 1909} 1910 1911static void 1912musbotg_device_bulk_close(struct usb2_xfer *xfer) 1913{ 1914 musbotg_device_done(xfer, USB_ERR_CANCELLED); 1915} 1916 1917static void 1918musbotg_device_bulk_enter(struct usb2_xfer *xfer) 1919{ 1920 return; 1921} 1922 1923static void 1924musbotg_device_bulk_start(struct usb2_xfer *xfer) 1925{ 1926 /* setup TDs */ 1927 musbotg_setup_standard_chain(xfer); 1928 musbotg_start_standard_chain(xfer); 1929} 1930 1931struct usb2_pipe_methods musbotg_device_bulk_methods = 1932{ 1933 .open = musbotg_device_bulk_open, 1934 .close = musbotg_device_bulk_close, 1935 .enter = musbotg_device_bulk_enter, 1936 .start = musbotg_device_bulk_start, 1937 .enter_is_cancelable = 1, 1938 .start_is_cancelable = 1, 1939}; 1940 1941/*------------------------------------------------------------------------* 1942 * musbotg control support 1943 *------------------------------------------------------------------------*/ 1944static void 1945musbotg_device_ctrl_open(struct usb2_xfer *xfer) 1946{ 1947 return; 1948} 1949 1950static void 1951musbotg_device_ctrl_close(struct usb2_xfer *xfer) 1952{ 1953 musbotg_device_done(xfer, USB_ERR_CANCELLED); 1954} 1955 1956static void 1957musbotg_device_ctrl_enter(struct usb2_xfer *xfer) 1958{ 1959 return; 1960} 1961 1962static void 1963musbotg_device_ctrl_start(struct usb2_xfer *xfer) 1964{ 1965 /* setup TDs */ 1966 musbotg_setup_standard_chain(xfer); 1967 musbotg_start_standard_chain(xfer); 1968} 1969 1970struct usb2_pipe_methods musbotg_device_ctrl_methods = 1971{ 1972 .open = musbotg_device_ctrl_open, 1973 .close = musbotg_device_ctrl_close, 1974 .enter = musbotg_device_ctrl_enter, 1975 .start = musbotg_device_ctrl_start, 1976 .enter_is_cancelable = 1, 1977 .start_is_cancelable = 1, 1978}; 1979 1980/*------------------------------------------------------------------------* 1981 * musbotg interrupt support 1982 *------------------------------------------------------------------------*/ 1983static void 1984musbotg_device_intr_open(struct usb2_xfer *xfer) 1985{ 1986 return; 1987} 1988 1989static void 1990musbotg_device_intr_close(struct usb2_xfer *xfer) 1991{ 1992 musbotg_device_done(xfer, USB_ERR_CANCELLED); 1993} 1994 1995static void 1996musbotg_device_intr_enter(struct usb2_xfer *xfer) 1997{ 1998 return; 1999} 2000 2001static void 2002musbotg_device_intr_start(struct usb2_xfer *xfer) 2003{ 2004 /* setup TDs */ 2005 musbotg_setup_standard_chain(xfer); 2006 musbotg_start_standard_chain(xfer); 2007} 2008 2009struct usb2_pipe_methods musbotg_device_intr_methods = 2010{ 2011 .open = musbotg_device_intr_open, 2012 .close = musbotg_device_intr_close, 2013 .enter = musbotg_device_intr_enter, 2014 .start = musbotg_device_intr_start, 2015 .enter_is_cancelable = 1, 2016 .start_is_cancelable = 1, 2017}; 2018 2019/*------------------------------------------------------------------------* 2020 * musbotg full speed isochronous support 2021 *------------------------------------------------------------------------*/ 2022static void 2023musbotg_device_isoc_open(struct usb2_xfer *xfer) 2024{ 2025 return; 2026} 2027 2028static void 2029musbotg_device_isoc_close(struct usb2_xfer *xfer) 2030{ 2031 musbotg_device_done(xfer, USB_ERR_CANCELLED); 2032} 2033 2034static void 2035musbotg_device_isoc_enter(struct usb2_xfer *xfer) 2036{ 2037 struct musbotg_softc *sc = xfer->usb2_sc; 2038 uint32_t temp; 2039 uint32_t nframes; 2040 uint32_t fs_frames; 2041 2042 DPRINTFN(5, "xfer=%p next=%d nframes=%d\n", 2043 xfer, xfer->pipe->isoc_next, xfer->nframes); 2044 2045 /* get the current frame index */ 2046 2047 nframes = MUSB2_READ_2(sc, MUSB2_REG_FRAME); 2048 2049 /* 2050 * check if the frame index is within the window where the frames 2051 * will be inserted 2052 */ 2053 temp = (nframes - xfer->pipe->isoc_next) & MUSB2_MASK_FRAME; 2054 2055 if (usb2_get_speed(xfer->udev) == USB_SPEED_HIGH) { 2056 fs_frames = (xfer->nframes + 7) / 8; 2057 } else { 2058 fs_frames = xfer->nframes; 2059 } 2060 2061 if ((xfer->pipe->is_synced == 0) || 2062 (temp < fs_frames)) { 2063 /* 2064 * If there is data underflow or the pipe queue is 2065 * empty we schedule the transfer a few frames ahead 2066 * of the current frame position. Else two isochronous 2067 * transfers might overlap. 2068 */ 2069 xfer->pipe->isoc_next = (nframes + 3) & MUSB2_MASK_FRAME; 2070 xfer->pipe->is_synced = 1; 2071 DPRINTFN(2, "start next=%d\n", xfer->pipe->isoc_next); 2072 } 2073 /* 2074 * compute how many milliseconds the insertion is ahead of the 2075 * current frame position: 2076 */ 2077 temp = (xfer->pipe->isoc_next - nframes) & MUSB2_MASK_FRAME; 2078 2079 /* 2080 * pre-compute when the isochronous transfer will be finished: 2081 */ 2082 xfer->isoc_time_complete = 2083 usb2_isoc_time_expand(&sc->sc_bus, nframes) + temp + 2084 fs_frames; 2085 2086 /* compute frame number for next insertion */ 2087 xfer->pipe->isoc_next += fs_frames; 2088 2089 /* setup TDs */ 2090 musbotg_setup_standard_chain(xfer); 2091} 2092 2093static void 2094musbotg_device_isoc_start(struct usb2_xfer *xfer) 2095{ 2096 /* start TD chain */ 2097 musbotg_start_standard_chain(xfer); 2098} 2099 2100struct usb2_pipe_methods musbotg_device_isoc_methods = 2101{ 2102 .open = musbotg_device_isoc_open, 2103 .close = musbotg_device_isoc_close, 2104 .enter = musbotg_device_isoc_enter, 2105 .start = musbotg_device_isoc_start, 2106 .enter_is_cancelable = 1, 2107 .start_is_cancelable = 1, 2108}; 2109 2110/*------------------------------------------------------------------------* 2111 * musbotg root control support 2112 *------------------------------------------------------------------------* 2113 * simulate a hardware HUB by handling 2114 * all the necessary requests 2115 *------------------------------------------------------------------------*/ 2116static void 2117musbotg_root_ctrl_open(struct usb2_xfer *xfer) 2118{ 2119 return; 2120} 2121 2122static void 2123musbotg_root_ctrl_close(struct usb2_xfer *xfer) 2124{ 2125 struct musbotg_softc *sc = xfer->usb2_sc; 2126 2127 if (sc->sc_root_ctrl.xfer == xfer) { 2128 sc->sc_root_ctrl.xfer = NULL; 2129 } 2130 musbotg_device_done(xfer, USB_ERR_CANCELLED); 2131} 2132 2133/* 2134 * USB descriptors for the virtual Root HUB: 2135 */ 2136 2137static const struct usb2_device_descriptor musbotg_devd = { 2138 .bLength = sizeof(struct usb2_device_descriptor), 2139 .bDescriptorType = UDESC_DEVICE, 2140 .bcdUSB = {0x00, 0x02}, 2141 .bDeviceClass = UDCLASS_HUB, 2142 .bDeviceSubClass = UDSUBCLASS_HUB, 2143 .bDeviceProtocol = UDPROTO_HSHUBSTT, 2144 .bMaxPacketSize = 64, 2145 .bcdDevice = {0x00, 0x01}, 2146 .iManufacturer = 1, 2147 .iProduct = 2, 2148 .bNumConfigurations = 1, 2149}; 2150 2151static const struct usb2_device_qualifier musbotg_odevd = { 2152 .bLength = sizeof(struct usb2_device_qualifier), 2153 .bDescriptorType = UDESC_DEVICE_QUALIFIER, 2154 .bcdUSB = {0x00, 0x02}, 2155 .bDeviceClass = UDCLASS_HUB, 2156 .bDeviceSubClass = UDSUBCLASS_HUB, 2157 .bDeviceProtocol = UDPROTO_FSHUB, 2158 .bMaxPacketSize0 = 0, 2159 .bNumConfigurations = 0, 2160}; 2161 2162static const struct musbotg_config_desc musbotg_confd = { 2163 .confd = { 2164 .bLength = sizeof(struct usb2_config_descriptor), 2165 .bDescriptorType = UDESC_CONFIG, 2166 .wTotalLength[0] = sizeof(musbotg_confd), 2167 .bNumInterface = 1, 2168 .bConfigurationValue = 1, 2169 .iConfiguration = 0, 2170 .bmAttributes = UC_SELF_POWERED, 2171 .bMaxPower = 0, 2172 }, 2173 .ifcd = { 2174 .bLength = sizeof(struct usb2_interface_descriptor), 2175 .bDescriptorType = UDESC_INTERFACE, 2176 .bNumEndpoints = 1, 2177 .bInterfaceClass = UICLASS_HUB, 2178 .bInterfaceSubClass = UISUBCLASS_HUB, 2179 .bInterfaceProtocol = UIPROTO_HSHUBSTT, 2180 }, 2181 2182 .endpd = { 2183 .bLength = sizeof(struct usb2_endpoint_descriptor), 2184 .bDescriptorType = UDESC_ENDPOINT, 2185 .bEndpointAddress = (UE_DIR_IN | MUSBOTG_INTR_ENDPT), 2186 .bmAttributes = UE_INTERRUPT, 2187 .wMaxPacketSize[0] = 8, 2188 .bInterval = 255, 2189 }, 2190}; 2191 2192static const struct usb2_hub_descriptor_min musbotg_hubd = { 2193 .bDescLength = sizeof(musbotg_hubd), 2194 .bDescriptorType = UDESC_HUB, 2195 .bNbrPorts = 1, 2196 .wHubCharacteristics[0] = 2197 (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL) & 0xFF, 2198 .wHubCharacteristics[1] = 2199 (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL) >> 16, 2200 .bPwrOn2PwrGood = 50, 2201 .bHubContrCurrent = 0, 2202 .DeviceRemovable = {0}, /* port is removable */ 2203}; 2204 2205#define STRING_LANG \ 2206 0x09, 0x04, /* American English */ 2207 2208#define STRING_VENDOR \ 2209 'M', 0, 'e', 0, 'n', 0, 't', 0, 'o', 0, 'r', 0, ' ', 0, \ 2210 'G', 0, 'r', 0, 'a', 0, 'p', 0, 'h', 0, 'i', 0, 'c', 0, 's', 0 2211 2212#define STRING_PRODUCT \ 2213 'O', 0, 'T', 0, 'G', 0, ' ', 0, 'R', 0, \ 2214 'o', 0, 'o', 0, 't', 0, ' ', 0, 'H', 0, \ 2215 'U', 0, 'B', 0, 2216 2217USB_MAKE_STRING_DESC(STRING_LANG, musbotg_langtab); 2218USB_MAKE_STRING_DESC(STRING_VENDOR, musbotg_vendor); 2219USB_MAKE_STRING_DESC(STRING_PRODUCT, musbotg_product); 2220 2221static void 2222musbotg_root_ctrl_enter(struct usb2_xfer *xfer) 2223{ 2224 return; 2225} 2226 2227static void 2228musbotg_root_ctrl_start(struct usb2_xfer *xfer) 2229{ 2230 struct musbotg_softc *sc = xfer->usb2_sc; 2231 2232 sc->sc_root_ctrl.xfer = xfer; 2233 2234 usb2_config_td_queue_command( 2235 &sc->sc_config_td, NULL, &musbotg_root_ctrl_task, 0, 0); 2236} 2237 2238static void 2239musbotg_root_ctrl_task(struct musbotg_softc *sc, 2240 struct musbotg_config_copy *cc, uint16_t refcount) 2241{ 2242 musbotg_root_ctrl_poll(sc); 2243} 2244 2245static void 2246musbotg_root_ctrl_done(struct usb2_xfer *xfer, 2247 struct usb2_sw_transfer *std) 2248{ 2249 struct musbotg_softc *sc = xfer->usb2_sc; 2250 uint16_t value; 2251 uint16_t index; 2252 uint8_t use_polling; 2253 2254 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2255 2256 if (std->state != USB_SW_TR_SETUP) { 2257 if (std->state == USB_SW_TR_PRE_CALLBACK) { 2258 /* transfer transferred */ 2259 musbotg_device_done(xfer, std->err); 2260 } 2261 goto done; 2262 } 2263 /* buffer reset */ 2264 std->ptr = USB_ADD_BYTES(&sc->sc_hub_temp, 0); 2265 std->len = 0; 2266 2267 value = UGETW(std->req.wValue); 2268 index = UGETW(std->req.wIndex); 2269 2270 use_polling = mtx_owned(xfer->xfer_mtx) ? 1 : 0; 2271 2272 /* demultiplex the control request */ 2273 2274 switch (std->req.bmRequestType) { 2275 case UT_READ_DEVICE: 2276 switch (std->req.bRequest) { 2277 case UR_GET_DESCRIPTOR: 2278 goto tr_handle_get_descriptor; 2279 case UR_GET_CONFIG: 2280 goto tr_handle_get_config; 2281 case UR_GET_STATUS: 2282 goto tr_handle_get_status; 2283 default: 2284 goto tr_stalled; 2285 } 2286 break; 2287 2288 case UT_WRITE_DEVICE: 2289 switch (std->req.bRequest) { 2290 case UR_SET_ADDRESS: 2291 goto tr_handle_set_address; 2292 case UR_SET_CONFIG: 2293 goto tr_handle_set_config; 2294 case UR_CLEAR_FEATURE: 2295 goto tr_valid; /* nop */ 2296 case UR_SET_DESCRIPTOR: 2297 goto tr_valid; /* nop */ 2298 case UR_SET_FEATURE: 2299 default: 2300 goto tr_stalled; 2301 } 2302 break; 2303 2304 case UT_WRITE_ENDPOINT: 2305 switch (std->req.bRequest) { 2306 case UR_CLEAR_FEATURE: 2307 switch (UGETW(std->req.wValue)) { 2308 case UF_ENDPOINT_HALT: 2309 goto tr_handle_clear_halt; 2310 case UF_DEVICE_REMOTE_WAKEUP: 2311 goto tr_handle_clear_wakeup; 2312 default: 2313 goto tr_stalled; 2314 } 2315 break; 2316 case UR_SET_FEATURE: 2317 switch (UGETW(std->req.wValue)) { 2318 case UF_ENDPOINT_HALT: 2319 goto tr_handle_set_halt; 2320 case UF_DEVICE_REMOTE_WAKEUP: 2321 goto tr_handle_set_wakeup; 2322 default: 2323 goto tr_stalled; 2324 } 2325 break; 2326 case UR_SYNCH_FRAME: 2327 goto tr_valid; /* nop */ 2328 default: 2329 goto tr_stalled; 2330 } 2331 break; 2332 2333 case UT_READ_ENDPOINT: 2334 switch (std->req.bRequest) { 2335 case UR_GET_STATUS: 2336 goto tr_handle_get_ep_status; 2337 default: 2338 goto tr_stalled; 2339 } 2340 break; 2341 2342 case UT_WRITE_INTERFACE: 2343 switch (std->req.bRequest) { 2344 case UR_SET_INTERFACE: 2345 goto tr_handle_set_interface; 2346 case UR_CLEAR_FEATURE: 2347 goto tr_valid; /* nop */ 2348 case UR_SET_FEATURE: 2349 default: 2350 goto tr_stalled; 2351 } 2352 break; 2353 2354 case UT_READ_INTERFACE: 2355 switch (std->req.bRequest) { 2356 case UR_GET_INTERFACE: 2357 goto tr_handle_get_interface; 2358 case UR_GET_STATUS: 2359 goto tr_handle_get_iface_status; 2360 default: 2361 goto tr_stalled; 2362 } 2363 break; 2364 2365 case UT_WRITE_CLASS_INTERFACE: 2366 case UT_WRITE_VENDOR_INTERFACE: 2367 /* XXX forward */ 2368 break; 2369 2370 case UT_READ_CLASS_INTERFACE: 2371 case UT_READ_VENDOR_INTERFACE: 2372 /* XXX forward */ 2373 break; 2374 2375 case UT_WRITE_CLASS_DEVICE: 2376 switch (std->req.bRequest) { 2377 case UR_CLEAR_FEATURE: 2378 goto tr_valid; 2379 case UR_SET_DESCRIPTOR: 2380 case UR_SET_FEATURE: 2381 break; 2382 default: 2383 goto tr_stalled; 2384 } 2385 break; 2386 2387 case UT_WRITE_CLASS_OTHER: 2388 switch (std->req.bRequest) { 2389 case UR_CLEAR_FEATURE: 2390 goto tr_handle_clear_port_feature; 2391 case UR_SET_FEATURE: 2392 goto tr_handle_set_port_feature; 2393 case UR_CLEAR_TT_BUFFER: 2394 case UR_RESET_TT: 2395 case UR_STOP_TT: 2396 goto tr_valid; 2397 2398 default: 2399 goto tr_stalled; 2400 } 2401 break; 2402 2403 case UT_READ_CLASS_OTHER: 2404 switch (std->req.bRequest) { 2405 case UR_GET_TT_STATE: 2406 goto tr_handle_get_tt_state; 2407 case UR_GET_STATUS: 2408 goto tr_handle_get_port_status; 2409 default: 2410 goto tr_stalled; 2411 } 2412 break; 2413 2414 case UT_READ_CLASS_DEVICE: 2415 switch (std->req.bRequest) { 2416 case UR_GET_DESCRIPTOR: 2417 goto tr_handle_get_class_descriptor; 2418 case UR_GET_STATUS: 2419 goto tr_handle_get_class_status; 2420 2421 default: 2422 goto tr_stalled; 2423 } 2424 break; 2425 default: 2426 goto tr_stalled; 2427 } 2428 goto tr_valid; 2429 2430tr_handle_get_descriptor: 2431 switch (value >> 8) { 2432 case UDESC_DEVICE: 2433 if (value & 0xff) { 2434 goto tr_stalled; 2435 } 2436 std->len = sizeof(musbotg_devd); 2437 std->ptr = USB_ADD_BYTES(&musbotg_devd, 0); 2438 goto tr_valid; 2439 case UDESC_CONFIG: 2440 if (value & 0xff) { 2441 goto tr_stalled; 2442 } 2443 std->len = sizeof(musbotg_confd); 2444 std->ptr = USB_ADD_BYTES(&musbotg_confd, 0); 2445 goto tr_valid; 2446 case UDESC_STRING: 2447 switch (value & 0xff) { 2448 case 0: /* Language table */ 2449 std->len = sizeof(musbotg_langtab); 2450 std->ptr = USB_ADD_BYTES(&musbotg_langtab, 0); 2451 goto tr_valid; 2452 2453 case 1: /* Vendor */ 2454 std->len = sizeof(musbotg_vendor); 2455 std->ptr = USB_ADD_BYTES(&musbotg_vendor, 0); 2456 goto tr_valid; 2457 2458 case 2: /* Product */ 2459 std->len = sizeof(musbotg_product); 2460 std->ptr = USB_ADD_BYTES(&musbotg_product, 0); 2461 goto tr_valid; 2462 default: 2463 break; 2464 } 2465 break; 2466 default: 2467 goto tr_stalled; 2468 } 2469 goto tr_stalled; 2470 2471tr_handle_get_config: 2472 std->len = 1; 2473 sc->sc_hub_temp.wValue[0] = sc->sc_conf; 2474 goto tr_valid; 2475 2476tr_handle_get_status: 2477 std->len = 2; 2478 USETW(sc->sc_hub_temp.wValue, UDS_SELF_POWERED); 2479 goto tr_valid; 2480 2481tr_handle_set_address: 2482 if (value & 0xFF00) { 2483 goto tr_stalled; 2484 } 2485 sc->sc_rt_addr = value; 2486 goto tr_valid; 2487 2488tr_handle_set_config: 2489 if (value >= 2) { 2490 goto tr_stalled; 2491 } 2492 sc->sc_conf = value; 2493 goto tr_valid; 2494 2495tr_handle_get_interface: 2496 std->len = 1; 2497 sc->sc_hub_temp.wValue[0] = 0; 2498 goto tr_valid; 2499 2500tr_handle_get_tt_state: 2501tr_handle_get_class_status: 2502tr_handle_get_iface_status: 2503tr_handle_get_ep_status: 2504 std->len = 2; 2505 USETW(sc->sc_hub_temp.wValue, 0); 2506 goto tr_valid; 2507 2508tr_handle_set_halt: 2509tr_handle_set_interface: 2510tr_handle_set_wakeup: 2511tr_handle_clear_wakeup: 2512tr_handle_clear_halt: 2513 goto tr_valid; 2514 2515tr_handle_clear_port_feature: 2516 if (index != 1) { 2517 goto tr_stalled; 2518 } 2519 DPRINTFN(8, "UR_CLEAR_PORT_FEATURE on port %d\n", index); 2520 2521 switch (value) { 2522 case UHF_PORT_SUSPEND: 2523 musbotg_wakeup_peer(xfer); 2524 break; 2525 2526 case UHF_PORT_ENABLE: 2527 sc->sc_flags.port_enabled = 0; 2528 break; 2529 2530 case UHF_PORT_TEST: 2531 case UHF_PORT_INDICATOR: 2532 case UHF_C_PORT_ENABLE: 2533 case UHF_C_PORT_OVER_CURRENT: 2534 case UHF_C_PORT_RESET: 2535 /* nops */ 2536 break; 2537 case UHF_PORT_POWER: 2538 sc->sc_flags.port_powered = 0; 2539 musbotg_pull_down(sc); 2540 musbotg_clocks_off(sc); 2541 break; 2542 case UHF_C_PORT_CONNECTION: 2543 sc->sc_flags.change_connect = 0; 2544 break; 2545 case UHF_C_PORT_SUSPEND: 2546 sc->sc_flags.change_suspend = 0; 2547 break; 2548 default: 2549 std->err = USB_ERR_IOERROR; 2550 goto done; 2551 } 2552 goto tr_valid; 2553 2554tr_handle_set_port_feature: 2555 if (index != 1) { 2556 goto tr_stalled; 2557 } 2558 DPRINTFN(8, "UR_SET_PORT_FEATURE\n"); 2559 2560 switch (value) { 2561 case UHF_PORT_ENABLE: 2562 sc->sc_flags.port_enabled = 1; 2563 break; 2564 case UHF_PORT_SUSPEND: 2565 case UHF_PORT_RESET: 2566 case UHF_PORT_TEST: 2567 case UHF_PORT_INDICATOR: 2568 /* nops */ 2569 break; 2570 case UHF_PORT_POWER: 2571 sc->sc_flags.port_powered = 1; 2572 break; 2573 default: 2574 std->err = USB_ERR_IOERROR; 2575 goto done; 2576 } 2577 goto tr_valid; 2578 2579tr_handle_get_port_status: 2580 2581 DPRINTFN(8, "UR_GET_PORT_STATUS\n"); 2582 2583 if (index != 1) { 2584 goto tr_stalled; 2585 } 2586 if (sc->sc_flags.status_vbus) { 2587 musbotg_clocks_on(sc); 2588 musbotg_pull_up(sc); 2589 } else { 2590 musbotg_pull_down(sc); 2591 musbotg_clocks_off(sc); 2592 } 2593 2594 /* Select Device Side Mode */ 2595 value = UPS_PORT_MODE_DEVICE; 2596 2597 if (sc->sc_flags.status_high_speed) { 2598 value |= UPS_HIGH_SPEED; 2599 } 2600 if (sc->sc_flags.port_powered) { 2601 value |= UPS_PORT_POWER; 2602 } 2603 if (sc->sc_flags.port_enabled) { 2604 value |= UPS_PORT_ENABLED; 2605 } 2606 if (sc->sc_flags.status_vbus && 2607 sc->sc_flags.status_bus_reset) { 2608 value |= UPS_CURRENT_CONNECT_STATUS; 2609 } 2610 if (sc->sc_flags.status_suspend) { 2611 value |= UPS_SUSPEND; 2612 } 2613 USETW(sc->sc_hub_temp.ps.wPortStatus, value); 2614 2615 value = 0; 2616 2617 if (sc->sc_flags.change_connect) { 2618 value |= UPS_C_CONNECT_STATUS; 2619 2620 if (sc->sc_flags.status_vbus && 2621 sc->sc_flags.status_bus_reset) { 2622 /* reset EP0 state */ 2623 sc->sc_ep0_busy = 0; 2624 sc->sc_ep0_cmd = 0; 2625 } 2626 } 2627 if (sc->sc_flags.change_suspend) { 2628 value |= UPS_C_SUSPEND; 2629 } 2630 USETW(sc->sc_hub_temp.ps.wPortChange, value); 2631 std->len = sizeof(sc->sc_hub_temp.ps); 2632 goto tr_valid; 2633 2634tr_handle_get_class_descriptor: 2635 if (value & 0xFF) { 2636 goto tr_stalled; 2637 } 2638 std->ptr = USB_ADD_BYTES(&musbotg_hubd, 0); 2639 std->len = sizeof(musbotg_hubd); 2640 goto tr_valid; 2641 2642tr_stalled: 2643 std->err = USB_ERR_STALLED; 2644tr_valid: 2645done: 2646 return; 2647} 2648 2649static void 2650musbotg_root_ctrl_poll(struct musbotg_softc *sc) 2651{ 2652 usb2_sw_transfer(&sc->sc_root_ctrl, 2653 &musbotg_root_ctrl_done); 2654} 2655 2656struct usb2_pipe_methods musbotg_root_ctrl_methods = 2657{ 2658 .open = musbotg_root_ctrl_open, 2659 .close = musbotg_root_ctrl_close, 2660 .enter = musbotg_root_ctrl_enter, 2661 .start = musbotg_root_ctrl_start, 2662 .enter_is_cancelable = 1, 2663 .start_is_cancelable = 0, 2664}; 2665 2666/*------------------------------------------------------------------------* 2667 * musbotg root interrupt support 2668 *------------------------------------------------------------------------*/ 2669static void 2670musbotg_root_intr_open(struct usb2_xfer *xfer) 2671{ 2672 return; 2673} 2674 2675static void 2676musbotg_root_intr_close(struct usb2_xfer *xfer) 2677{ 2678 struct musbotg_softc *sc = xfer->usb2_sc; 2679 2680 if (sc->sc_root_intr.xfer == xfer) { 2681 sc->sc_root_intr.xfer = NULL; 2682 } 2683 musbotg_device_done(xfer, USB_ERR_CANCELLED); 2684} 2685 2686static void 2687musbotg_root_intr_enter(struct usb2_xfer *xfer) 2688{ 2689 return; 2690} 2691 2692static void 2693musbotg_root_intr_start(struct usb2_xfer *xfer) 2694{ 2695 struct musbotg_softc *sc = xfer->usb2_sc; 2696 2697 sc->sc_root_intr.xfer = xfer; 2698} 2699 2700struct usb2_pipe_methods musbotg_root_intr_methods = 2701{ 2702 .open = musbotg_root_intr_open, 2703 .close = musbotg_root_intr_close, 2704 .enter = musbotg_root_intr_enter, 2705 .start = musbotg_root_intr_start, 2706 .enter_is_cancelable = 1, 2707 .start_is_cancelable = 1, 2708}; 2709 2710static void 2711musbotg_xfer_setup(struct usb2_setup_params *parm) 2712{ 2713 const struct usb2_hw_ep_profile *pf; 2714 struct musbotg_softc *sc; 2715 struct usb2_xfer *xfer; 2716 void *last_obj; 2717 uint32_t ntd; 2718 uint32_t n; 2719 uint8_t ep_no; 2720 2721 sc = MUSBOTG_BUS2SC(parm->udev->bus); 2722 xfer = parm->curr_xfer; 2723 2724 /* 2725 * setup xfer 2726 */ 2727 xfer->usb2_sc = sc; 2728 2729 /* 2730 * NOTE: This driver does not use any of the parameters that 2731 * are computed from the following values. Just set some 2732 * reasonable dummies: 2733 */ 2734 parm->hc_max_packet_size = 0x400; 2735 parm->hc_max_frame_size = 0x400; 2736 2737 if ((parm->methods == &musbotg_device_isoc_methods) || 2738 (parm->methods == &musbotg_device_intr_methods)) 2739 parm->hc_max_packet_count = 3; 2740 else 2741 parm->hc_max_packet_count = 1; 2742 2743 usb2_transfer_setup_sub(parm); 2744 2745 /* 2746 * compute maximum number of TDs 2747 */ 2748 if (parm->methods == &musbotg_device_ctrl_methods) { 2749 2750 ntd = xfer->nframes + 1 /* STATUS */ + 1 /* SYNC */ ; 2751 2752 } else if (parm->methods == &musbotg_device_bulk_methods) { 2753 2754 ntd = xfer->nframes + 1 /* SYNC */ ; 2755 2756 } else if (parm->methods == &musbotg_device_intr_methods) { 2757 2758 ntd = xfer->nframes + 1 /* SYNC */ ; 2759 2760 } else if (parm->methods == &musbotg_device_isoc_methods) { 2761 2762 ntd = xfer->nframes + 1 /* SYNC */ ; 2763 2764 } else { 2765 2766 ntd = 0; 2767 } 2768 2769 /* 2770 * check if "usb2_transfer_setup_sub" set an error 2771 */ 2772 if (parm->err) { 2773 return; 2774 } 2775 /* 2776 * allocate transfer descriptors 2777 */ 2778 last_obj = NULL; 2779 2780 /* 2781 * get profile stuff 2782 */ 2783 if (ntd) { 2784 2785 ep_no = xfer->endpoint & UE_ADDR; 2786 musbotg_get_hw_ep_profile(parm->udev, &pf, ep_no); 2787 2788 if (pf == NULL) { 2789 /* should not happen */ 2790 parm->err = USB_ERR_INVAL; 2791 return; 2792 } 2793 } else { 2794 ep_no = 0; 2795 pf = NULL; 2796 } 2797 2798 /* align data */ 2799 parm->size[0] += ((-parm->size[0]) & (USB_HOST_ALIGN - 1)); 2800 2801 for (n = 0; n != ntd; n++) { 2802 2803 struct musbotg_td *td; 2804 2805 if (parm->buf) { 2806 2807 td = USB_ADD_BYTES(parm->buf, parm->size[0]); 2808 2809 /* init TD */ 2810 td->max_frame_size = xfer->max_frame_size; 2811 td->ep_no = ep_no; 2812 td->obj_next = last_obj; 2813 2814 last_obj = td; 2815 } 2816 parm->size[0] += sizeof(*td); 2817 } 2818 2819 xfer->td_start[0] = last_obj; 2820} 2821 2822static void 2823musbotg_xfer_unsetup(struct usb2_xfer *xfer) 2824{ 2825 return; 2826} 2827 2828static void 2829musbotg_pipe_init(struct usb2_device *udev, struct usb2_endpoint_descriptor *edesc, 2830 struct usb2_pipe *pipe) 2831{ 2832 struct musbotg_softc *sc = MUSBOTG_BUS2SC(udev->bus); 2833 2834 DPRINTFN(2, "pipe=%p, addr=%d, endpt=%d, mode=%d (%d)\n", 2835 pipe, udev->address, 2836 edesc->bEndpointAddress, udev->flags.usb2_mode, 2837 sc->sc_rt_addr); 2838 2839 if (udev->device_index == sc->sc_rt_addr) { 2840 2841 if (udev->flags.usb2_mode != USB_MODE_HOST) { 2842 /* not supported */ 2843 return; 2844 } 2845 switch (edesc->bEndpointAddress) { 2846 case USB_CONTROL_ENDPOINT: 2847 pipe->methods = &musbotg_root_ctrl_methods; 2848 break; 2849 case UE_DIR_IN | MUSBOTG_INTR_ENDPT: 2850 pipe->methods = &musbotg_root_intr_methods; 2851 break; 2852 default: 2853 /* do nothing */ 2854 break; 2855 } 2856 } else { 2857 2858 if (udev->flags.usb2_mode != USB_MODE_DEVICE) { 2859 /* not supported */ 2860 return; 2861 } 2862 if ((udev->speed != USB_SPEED_FULL) && 2863 (udev->speed != USB_SPEED_HIGH)) { 2864 /* not supported */ 2865 return; 2866 } 2867 switch (edesc->bmAttributes & UE_XFERTYPE) { 2868 case UE_CONTROL: 2869 pipe->methods = &musbotg_device_ctrl_methods; 2870 break; 2871 case UE_INTERRUPT: 2872 pipe->methods = &musbotg_device_intr_methods; 2873 break; 2874 case UE_ISOCHRONOUS: 2875 pipe->methods = &musbotg_device_isoc_methods; 2876 break; 2877 case UE_BULK: 2878 pipe->methods = &musbotg_device_bulk_methods; 2879 break; 2880 default: 2881 /* do nothing */ 2882 break; 2883 } 2884 } 2885} 2886 2887struct usb2_bus_methods musbotg_bus_methods = 2888{ 2889 .pipe_init = &musbotg_pipe_init, 2890 .xfer_setup = &musbotg_xfer_setup, 2891 .xfer_unsetup = &musbotg_xfer_unsetup, 2892 .do_poll = &musbotg_do_poll, 2893 .get_hw_ep_profile = &musbotg_get_hw_ep_profile, 2894 .set_stall = &musbotg_set_stall, 2895 .clear_stall = &musbotg_clear_stall, 2896 .vbus_interrupt = &musbotg_vbus_interrupt, 2897 .rem_wakeup_set = &musbotg_rem_wakeup_set, 2898}; 2899