1198151Sthompsa/* $FreeBSD$ */ 2198151Sthompsa/*- 3198151Sthompsa * Copyright (c) 2001 The NetBSD Foundation, Inc. 4198151Sthompsa * All rights reserved. 5198151Sthompsa * 6198151Sthompsa * This code is derived from software contributed to The NetBSD Foundation 7198151Sthompsa * by Lennart Augustsson (lennart@augustsson.net). 8198151Sthompsa * 9198151Sthompsa * Redistribution and use in source and binary forms, with or without 10198151Sthompsa * modification, are permitted provided that the following conditions 11198151Sthompsa * are met: 12198151Sthompsa * 1. Redistributions of source code must retain the above copyright 13198151Sthompsa * notice, this list of conditions and the following disclaimer. 14198151Sthompsa * 2. Redistributions in binary form must reproduce the above copyright 15198151Sthompsa * notice, this list of conditions and the following disclaimer in the 16198151Sthompsa * documentation and/or other materials provided with the distribution. 17198151Sthompsa * 18198151Sthompsa * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 19198151Sthompsa * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 20198151Sthompsa * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 21198151Sthompsa * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 22198151Sthompsa * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23198151Sthompsa * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24198151Sthompsa * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25198151Sthompsa * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26198151Sthompsa * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27198151Sthompsa * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28198151Sthompsa * POSSIBILITY OF SUCH DAMAGE. 29198151Sthompsa */ 30198151Sthompsa 31198151Sthompsa#ifndef _EHCIREG_H_ 32198151Sthompsa#define _EHCIREG_H_ 33198151Sthompsa 34198151Sthompsa/* PCI config registers */ 35198151Sthompsa#define PCI_CBMEM 0x10 /* configuration base MEM */ 36198151Sthompsa#define PCI_INTERFACE_EHCI 0x20 37198151Sthompsa#define PCI_USBREV 0x60 /* RO USB protocol revision */ 38198151Sthompsa#define PCI_USB_REV_MASK 0xff 39198151Sthompsa#define PCI_USB_REV_PRE_1_0 0x00 40198151Sthompsa#define PCI_USB_REV_1_0 0x10 41198151Sthompsa#define PCI_USB_REV_1_1 0x11 42198151Sthompsa#define PCI_USB_REV_2_0 0x20 43198151Sthompsa#define PCI_EHCI_FLADJ 0x61 /* RW Frame len adj, SOF=59488+6*fladj */ 44198151Sthompsa#define PCI_EHCI_PORTWAKECAP 0x62 /* RW Port wake caps (opt) */ 45198151Sthompsa 46198151Sthompsa/* EHCI Extended Capabilities */ 47198151Sthompsa#define EHCI_EC_LEGSUP 0x01 48198151Sthompsa#define EHCI_EECP_NEXT(x) (((x) >> 8) & 0xff) 49198151Sthompsa#define EHCI_EECP_ID(x) ((x) & 0xff) 50198151Sthompsa 51198151Sthompsa/* Legacy support extended capability */ 52198151Sthompsa#define EHCI_LEGSUP_BIOS_SEM 0x02 53198151Sthompsa#define EHCI_LEGSUP_OS_SEM 0x03 54198151Sthompsa#define EHCI_LEGSUP_USBLEGCTLSTS 0x04 55198151Sthompsa 56198151Sthompsa/* EHCI capability registers */ 57214349Snwhitehorn#define EHCI_CAPLEN_HCIVERSION 0x00 /* RO Capability register length 58214349Snwhitehorn * (least-significant byte) and 59214349Snwhitehorn * interface version number (two 60214349Snwhitehorn * most significant) 61214349Snwhitehorn */ 62214349Snwhitehorn#define EHCI_CAPLENGTH(x) ((x) & 0xff) 63214349Snwhitehorn#define EHCI_HCIVERSION(x) (((x) >> 16) & 0xffff) 64198151Sthompsa#define EHCI_HCSPARAMS 0x04 /* RO Structural parameters */ 65198151Sthompsa#define EHCI_HCS_DEBUGPORT(x) (((x) >> 20) & 0xf) 66198151Sthompsa#define EHCI_HCS_P_INDICATOR(x) ((x) & 0x10000) 67198151Sthompsa#define EHCI_HCS_N_CC(x) (((x) >> 12) & 0xf) /* # of companion ctlrs */ 68198151Sthompsa#define EHCI_HCS_N_PCC(x) (((x) >> 8) & 0xf) /* # of ports per comp. */ 69198151Sthompsa#define EHCI_HCS_PPC(x) ((x) & 0x10) /* port power control */ 70198151Sthompsa#define EHCI_HCS_N_PORTS(x) ((x) & 0xf) /* # of ports */ 71198151Sthompsa#define EHCI_HCCPARAMS 0x08 /* RO Capability parameters */ 72198151Sthompsa#define EHCI_HCC_EECP(x) (((x) >> 8) & 0xff) /* extended ports caps */ 73198151Sthompsa#define EHCI_HCC_IST(x) (((x) >> 4) & 0xf) /* isoc sched threshold */ 74198151Sthompsa#define EHCI_HCC_ASPC(x) ((x) & 0x4) /* async sched park cap */ 75198151Sthompsa#define EHCI_HCC_PFLF(x) ((x) & 0x2) /* prog frame list flag */ 76198151Sthompsa#define EHCI_HCC_64BIT(x) ((x) & 0x1) /* 64 bit address cap */ 77198151Sthompsa#define EHCI_HCSP_PORTROUTE 0x0c /* RO Companion port route description */ 78198151Sthompsa 79198151Sthompsa/* EHCI operational registers. Offset given by EHCI_CAPLENGTH register */ 80198151Sthompsa#define EHCI_USBCMD 0x00 /* RO, RW, WO Command register */ 81198151Sthompsa#define EHCI_CMD_ITC_M 0x00ff0000 /* RW interrupt threshold ctrl */ 82198151Sthompsa#define EHCI_CMD_ITC_1 0x00010000 83198151Sthompsa#define EHCI_CMD_ITC_2 0x00020000 84198151Sthompsa#define EHCI_CMD_ITC_4 0x00040000 85198151Sthompsa#define EHCI_CMD_ITC_8 0x00080000 86198151Sthompsa#define EHCI_CMD_ITC_16 0x00100000 87198151Sthompsa#define EHCI_CMD_ITC_32 0x00200000 88198151Sthompsa#define EHCI_CMD_ITC_64 0x00400000 89198151Sthompsa#define EHCI_CMD_ASPME 0x00000800 /* RW/RO async park enable */ 90198151Sthompsa#define EHCI_CMD_ASPMC 0x00000300 /* RW/RO async park count */ 91198151Sthompsa#define EHCI_CMD_LHCR 0x00000080 /* RW light host ctrl reset */ 92198151Sthompsa#define EHCI_CMD_IAAD 0x00000040 /* RW intr on async adv door 93198151Sthompsa * bell */ 94198151Sthompsa#define EHCI_CMD_ASE 0x00000020 /* RW async sched enable */ 95198151Sthompsa#define EHCI_CMD_PSE 0x00000010 /* RW periodic sched enable */ 96198151Sthompsa#define EHCI_CMD_FLS_M 0x0000000c /* RW/RO frame list size */ 97198151Sthompsa#define EHCI_CMD_FLS(x) (((x) >> 2) & 3) /* RW/RO frame list size */ 98198151Sthompsa#define EHCI_CMD_HCRESET 0x00000002 /* RW reset */ 99198151Sthompsa#define EHCI_CMD_RS 0x00000001 /* RW run/stop */ 100198151Sthompsa#define EHCI_USBSTS 0x04 /* RO, RW, RWC Status register */ 101198151Sthompsa#define EHCI_STS_ASS 0x00008000 /* RO async sched status */ 102198151Sthompsa#define EHCI_STS_PSS 0x00004000 /* RO periodic sched status */ 103198151Sthompsa#define EHCI_STS_REC 0x00002000 /* RO reclamation */ 104198151Sthompsa#define EHCI_STS_HCH 0x00001000 /* RO host controller halted */ 105198151Sthompsa#define EHCI_STS_IAA 0x00000020 /* RWC interrupt on async adv */ 106198151Sthompsa#define EHCI_STS_HSE 0x00000010 /* RWC host system error */ 107198151Sthompsa#define EHCI_STS_FLR 0x00000008 /* RWC frame list rollover */ 108198151Sthompsa#define EHCI_STS_PCD 0x00000004 /* RWC port change detect */ 109198151Sthompsa#define EHCI_STS_ERRINT 0x00000002 /* RWC error interrupt */ 110198151Sthompsa#define EHCI_STS_INT 0x00000001 /* RWC interrupt */ 111198151Sthompsa#define EHCI_STS_INTRS(x) ((x) & 0x3f) 112198151Sthompsa 113198151Sthompsa/* 114198151Sthompsa * NOTE: the doorbell interrupt is enabled, but the doorbell is never 115198151Sthompsa * used! SiS chipsets require this. 116198151Sthompsa */ 117198151Sthompsa#define EHCI_NORMAL_INTRS (EHCI_STS_IAA | EHCI_STS_HSE | \ 118198151Sthompsa EHCI_STS_PCD | EHCI_STS_ERRINT | EHCI_STS_INT) 119198151Sthompsa 120198151Sthompsa#define EHCI_USBINTR 0x08 /* RW Interrupt register */ 121198151Sthompsa#define EHCI_INTR_IAAE 0x00000020 /* interrupt on async advance 122198151Sthompsa * ena */ 123198151Sthompsa#define EHCI_INTR_HSEE 0x00000010 /* host system error ena */ 124198151Sthompsa#define EHCI_INTR_FLRE 0x00000008 /* frame list rollover ena */ 125198151Sthompsa#define EHCI_INTR_PCIE 0x00000004 /* port change ena */ 126198151Sthompsa#define EHCI_INTR_UEIE 0x00000002 /* USB error intr ena */ 127198151Sthompsa#define EHCI_INTR_UIE 0x00000001 /* USB intr ena */ 128198151Sthompsa 129198151Sthompsa#define EHCI_FRINDEX 0x0c /* RW Frame Index register */ 130198151Sthompsa 131198151Sthompsa#define EHCI_CTRLDSSEGMENT 0x10 /* RW Control Data Structure Segment */ 132198151Sthompsa 133198151Sthompsa#define EHCI_PERIODICLISTBASE 0x14 /* RW Periodic List Base */ 134198151Sthompsa#define EHCI_ASYNCLISTADDR 0x18 /* RW Async List Base */ 135198151Sthompsa 136198151Sthompsa#define EHCI_CONFIGFLAG 0x40 /* RW Configure Flag register */ 137198151Sthompsa#define EHCI_CONF_CF 0x00000001 /* RW configure flag */ 138198151Sthompsa 139198151Sthompsa#define EHCI_PORTSC(n) (0x40+(4*(n))) /* RO, RW, RWC Port Status reg */ 140198151Sthompsa#define EHCI_PS_WKOC_E 0x00400000 /* RW wake on over current ena */ 141198151Sthompsa#define EHCI_PS_WKDSCNNT_E 0x00200000 /* RW wake on disconnect ena */ 142198151Sthompsa#define EHCI_PS_WKCNNT_E 0x00100000 /* RW wake on connect ena */ 143198151Sthompsa#define EHCI_PS_PTC 0x000f0000 /* RW port test control */ 144198151Sthompsa#define EHCI_PS_PIC 0x0000c000 /* RW port indicator control */ 145198151Sthompsa#define EHCI_PS_PO 0x00002000 /* RW port owner */ 146198151Sthompsa#define EHCI_PS_PP 0x00001000 /* RW,RO port power */ 147198151Sthompsa#define EHCI_PS_LS 0x00000c00 /* RO line status */ 148198151Sthompsa#define EHCI_PS_IS_LOWSPEED(x) (((x) & EHCI_PS_LS) == 0x00000400) 149198151Sthompsa#define EHCI_PS_PR 0x00000100 /* RW port reset */ 150198151Sthompsa#define EHCI_PS_SUSP 0x00000080 /* RW suspend */ 151198151Sthompsa#define EHCI_PS_FPR 0x00000040 /* RW force port resume */ 152198151Sthompsa#define EHCI_PS_OCC 0x00000020 /* RWC over current change */ 153198151Sthompsa#define EHCI_PS_OCA 0x00000010 /* RO over current active */ 154198151Sthompsa#define EHCI_PS_PEC 0x00000008 /* RWC port enable change */ 155198151Sthompsa#define EHCI_PS_PE 0x00000004 /* RW port enable */ 156198151Sthompsa#define EHCI_PS_CSC 0x00000002 /* RWC connect status change */ 157198151Sthompsa#define EHCI_PS_CS 0x00000001 /* RO connect status */ 158198151Sthompsa#define EHCI_PS_CLEAR (EHCI_PS_OCC | EHCI_PS_PEC | EHCI_PS_CSC) 159198151Sthompsa 160198151Sthompsa#define EHCI_USBMODE 0x68 /* RW USB Device mode register */ 161198151Sthompsa#define EHCI_UM_CM 0x00000003 /* R/WO Controller Mode */ 162198151Sthompsa#define EHCI_UM_CM_IDLE 0x0 /* Idle */ 163198151Sthompsa#define EHCI_UM_CM_HOST 0x3 /* Host Controller */ 164198151Sthompsa#define EHCI_UM_ES 0x00000004 /* R/WO Endian Select */ 165198151Sthompsa#define EHCI_UM_ES_LE 0x0 /* Little-endian byte alignment */ 166198151Sthompsa#define EHCI_UM_ES_BE 0x4 /* Big-endian byte alignment */ 167198151Sthompsa#define EHCI_UM_SDIS 0x00000010 /* R/WO Stream Disable Mode */ 168198151Sthompsa 169198151Sthompsa#define EHCI_PORT_RESET_COMPLETE 2 /* ms */ 170198151Sthompsa 171198151Sthompsa#endif /* _EHCIREG_H_ */ 172