1192554Sthompsa/* $FreeBSD$ */ 2192554Sthompsa/*- 3192554Sthompsa * Copyright (c) 2009 Hans Petter Selasky. All rights reserved. 4192554Sthompsa * 5192554Sthompsa * Redistribution and use in source and binary forms, with or without 6192554Sthompsa * modification, are permitted provided that the following conditions 7192554Sthompsa * are met: 8192554Sthompsa * 1. Redistributions of source code must retain the above copyright 9192554Sthompsa * notice, this list of conditions and the following disclaimer. 10192554Sthompsa * 2. Redistributions in binary form must reproduce the above copyright 11192554Sthompsa * notice, this list of conditions and the following disclaimer in the 12192554Sthompsa * documentation and/or other materials provided with the distribution. 13192554Sthompsa * 14192554Sthompsa * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15192554Sthompsa * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16192554Sthompsa * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17192554Sthompsa * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18192554Sthompsa * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19192554Sthompsa * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20192554Sthompsa * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21192554Sthompsa * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22192554Sthompsa * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23192554Sthompsa * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24192554Sthompsa * SUCH DAMAGE. 25192554Sthompsa */ 26192554Sthompsa 27192554Sthompsa#ifndef _AVR32DCI_H_ 28192554Sthompsa#define _AVR32DCI_H_ 29192554Sthompsa 30192554Sthompsa#define AVR32_MAX_DEVICES (USB_MIN_DEVICES + 1) 31192554Sthompsa 32192554Sthompsa/* Register definitions */ 33192554Sthompsa 34192554Sthompsa#define AVR32_CTRL 0x00 /* Control */ 35192554Sthompsa#define AVR32_CTRL_DEV_ADDR 0x7F 36192554Sthompsa#define AVR32_CTRL_DEV_FADDR_EN 0x80 37192554Sthompsa#define AVR32_CTRL_DEV_EN_USBA 0x100 38192554Sthompsa#define AVR32_CTRL_DEV_DETACH 0x200 39192554Sthompsa#define AVR32_CTRL_DEV_REWAKEUP 0x400 40192554Sthompsa 41192554Sthompsa#define AVR32_FNUM 0x04 /* Frame Number */ 42192554Sthompsa#define AVR32_FNUM_MASK 0x3FFF 43192554Sthompsa#define AVR32_FRAME_MASK 0x7FF 44192554Sthompsa 45192554Sthompsa/* 0x08 - 0x0C Reserved */ 46192554Sthompsa#define AVR32_IEN 0x10 /* Interrupt Enable */ 47192554Sthompsa#define AVR32_INTSTA 0x14 /* Interrupt Status */ 48192554Sthompsa#define AVR32_CLRINT 0x18 /* Clear Interrupt */ 49192554Sthompsa 50192554Sthompsa#define AVR32_INT_SPEED 0x00000001 /* set if High Speed else Full Speed */ 51192554Sthompsa#define AVR32_INT_DET_SUSPD 0x00000002 52192554Sthompsa#define AVR32_INT_MICRO_SOF 0x00000004 53192554Sthompsa#define AVR32_INT_INT_SOF 0x00000008 54192554Sthompsa#define AVR32_INT_ENDRESET 0x00000010 55192554Sthompsa#define AVR32_INT_WAKE_UP 0x00000020 56192554Sthompsa#define AVR32_INT_ENDOFRSM 0x00000040 57192554Sthompsa#define AVR32_INT_UPSTR_RES 0x00000080 58192554Sthompsa#define AVR32_INT_EPT_INT(n) (0x00000100 << (n)) 59192554Sthompsa#define AVR32_INT_DMA_INT(n) (0x01000000 << (n)) 60192554Sthompsa 61192554Sthompsa#define AVR32_EPTRST 0x1C /* Endpoints Reset */ 62192554Sthompsa#define AVR32_EPTRST_MASK(n) (0x00000001 << (n)) 63192554Sthompsa 64192554Sthompsa/* 0x20 - 0xCC Reserved */ 65192554Sthompsa#define AVR32_TSTSOFCNT 0xD0 /* Test SOF Counter */ 66192554Sthompsa#define AVR32_TSTCNTA 0xD4 /* Test A Counter */ 67192554Sthompsa#define AVR32_TSTCNTB 0xD8 /* Test B Counter */ 68192554Sthompsa#define AVR32_TSTMODEREG 0xDC /* Test Mode */ 69192554Sthompsa#define AVR32_TST 0xE0 /* Test */ 70192554Sthompsa#define AVR32_TST_NORMAL 0x00000000 71192554Sthompsa#define AVR32_TST_HS_ONLY 0x00000002 72192554Sthompsa#define AVR32_TST_FS_ONLY 0x00000003 73192554Sthompsa 74192554Sthompsa/* 0xE4 - 0xE8 Reserved */ 75192554Sthompsa#define AVR32_IPPADDRSIZE 0xEC /* PADDRSIZE */ 76192554Sthompsa#define AVR32_IPNAME1 0xF0 /* Name1 */ 77192554Sthompsa#define AVR32_IPNAME2 0xF4 /* Name2 */ 78192554Sthompsa#define AVR32_IPFEATURES 0xF8 /* Features */ 79192554Sthompsa#define AVR32_IPFEATURES_NEP(x) (((x) & 0xF) ? ((x) & 0xF) : 0x10) 80192554Sthompsa 81192554Sthompsa#define AVR32_IPVERSION 0xFC /* IP Version */ 82192554Sthompsa 83192554Sthompsa#define _A(base,n) ((base) + (0x20*(n))) 84192554Sthompsa#define AVR32_EPTCFG(n) _A(0x100, n) /* Endpoint Configuration */ 85192554Sthompsa#define AVR32_EPTCFG_EPSIZE(n) ((n)-3) /* power of two */ 86192554Sthompsa#define AVR32_EPTCFG_EPDIR_OUT 0x00000000 87192554Sthompsa#define AVR32_EPTCFG_EPDIR_IN 0x00000008 88192554Sthompsa#define AVR32_EPTCFG_TYPE_CTRL 0x00000000 89192554Sthompsa#define AVR32_EPTCFG_TYPE_ISOC 0x00000100 90192554Sthompsa#define AVR32_EPTCFG_TYPE_BULK 0x00000200 91192554Sthompsa#define AVR32_EPTCFG_TYPE_INTR 0x00000300 92192554Sthompsa#define AVR32_EPTCFG_NBANK(n) (0x00000400*(n)) 93192554Sthompsa#define AVR32_EPTCFG_NB_TRANS(n) (0x00001000*(n)) 94192554Sthompsa#define AVR32_EPTCFG_EPT_MAPD 0x80000000 95192554Sthompsa 96192554Sthompsa#define AVR32_EPTCTLENB(n) _A(0x104, n) /* Endpoint Control Enable */ 97192554Sthompsa#define AVR32_EPTCTLDIS(n) _A(0x108, n) /* Endpoint Control Disable */ 98192554Sthompsa#define AVR32_EPTCTL(n) _A(0x10C, n) /* Endpoint Control */ 99192554Sthompsa#define AVR32_EPTCTL_EPT_ENABL 0x00000001 100192554Sthompsa#define AVR32_EPTCTL_AUTO_VALID 0x00000002 101192554Sthompsa#define AVR32_EPTCTL_INTDIS_DMA 0x00000008 102192554Sthompsa#define AVR32_EPTCTL_NYET_DIS 0x00000010 103192554Sthompsa#define AVR32_EPTCTL_DATAX_RX 0x00000040 104192554Sthompsa#define AVR32_EPTCTL_MDATA_RX 0x00000080 105192554Sthompsa#define AVR32_EPTCTL_ERR_OVFLW 0x00000100 106192554Sthompsa#define AVR32_EPTCTL_RX_BK_RDY 0x00000200 107192554Sthompsa#define AVR32_EPTCTL_TX_COMPLT 0x00000400 108192554Sthompsa#define AVR32_EPTCTL_TX_PK_RDY 0x00000800 109192554Sthompsa#define AVR32_EPTCTL_RX_SETUP 0x00001000 110192554Sthompsa#define AVR32_EPTCTL_STALL_SNT 0x00002000 111192554Sthompsa#define AVR32_EPTCTL_NAK_IN 0x00004000 112192554Sthompsa#define AVR32_EPTCTL_NAK_OUT 0x00008000 113192554Sthompsa#define AVR32_EPTCTL_BUSY_BANK 0x00040000 114192554Sthompsa#define AVR32_EPTCTL_SHORT_PCKT 0x80000000 115192554Sthompsa 116192554Sthompsa/* 0x110 Reserved */ 117192554Sthompsa#define AVR32_EPTSETSTA(n) _A(0x114, n) /* Endpoint Set Status */ 118192554Sthompsa#define AVR32_EPTCLRSTA(n) _A(0x118, n) /* Endpoint Clear Status */ 119192554Sthompsa#define AVR32_EPTSTA(n) _A(0x11C, n) /* Endpoint Status */ 120192554Sthompsa#define AVR32_EPTSTA_FRCESTALL 0x00000020 121192554Sthompsa#define AVR32_EPTSTA_TOGGLESQ_STA(x) (((x) & 0xC0) >> 6) 122192554Sthompsa#define AVR32_EPTSTA_TOGGLESQ 0x00000040 123192554Sthompsa#define AVR32_EPTSTA_ERR_OVFLW 0x00000100 124192554Sthompsa#define AVR32_EPTSTA_RX_BK_RDY 0x00000200 125192554Sthompsa#define AVR32_EPTSTA_TX_COMPLT 0x00000400 126192554Sthompsa#define AVR32_EPTSTA_TX_PK_RDY 0x00000800 127192554Sthompsa#define AVR32_EPTSTA_RX_SETUP 0x00001000 128192554Sthompsa#define AVR32_EPTSTA_STALL_SNT 0x00002000 129192554Sthompsa#define AVR32_EPTSTA_NAK_IN 0x00004000 130192554Sthompsa#define AVR32_EPTSTA_NAK_OUT 0x00008000 131192554Sthompsa#define AVR32_EPTSTA_CURRENT_BANK(x) (((x) & 0x00030000) >> 16) 132192554Sthompsa#define AVR32_EPTSTA_BUSY_BANK_STA(x) (((x) & 0x000C0000) >> 18) 133192554Sthompsa#define AVR32_EPTSTA_BYTE_COUNT(x) (((x) & 0x7FF00000) >> 20) 134192554Sthompsa#define AVR32_EPTSTA_SHRT_PCKT 0x80000000 135192554Sthompsa 136192554Sthompsa/* 0x300 - 0x30C Reserved */ 137192554Sthompsa#define AVR32_DMANXTDSC 0x310 /* DMA Next Descriptor Address */ 138192554Sthompsa#define AVR32_DMAADDRESS 0x314 /* DMA Channel Address */ 139192554Sthompsa 140192554Sthompsa#define AVR32_READ_4(sc, reg) \ 141192554Sthompsa bus_space_read_4((sc)->sc_io_tag, (sc)->sc_io_hdl, reg) 142192554Sthompsa 143192554Sthompsa#define AVR32_WRITE_4(sc, reg, data) \ 144192554Sthompsa bus_space_write_4((sc)->sc_io_tag, (sc)->sc_io_hdl, reg, data) 145192554Sthompsa 146192554Sthompsa#define AVR32_WRITE_MULTI_4(sc, reg, ptr, len) \ 147192554Sthompsa bus_space_write_multi_4((sc)->sc_io_tag, (sc)->sc_io_hdl, reg, ptr, len) 148192554Sthompsa 149192554Sthompsa#define AVR32_READ_MULTI_4(sc, reg, ptr, len) \ 150192554Sthompsa bus_space_read_multi_4((sc)->sc_io_tag, (sc)->sc_io_hdl, reg, ptr, len) 151192554Sthompsa 152192554Sthompsa/* 153192554Sthompsa * Maximum number of endpoints supported: 154192554Sthompsa */ 155192554Sthompsa#define AVR32_EP_MAX 7 156192554Sthompsa 157192554Sthompsastruct avr32dci_td; 158192554Sthompsa 159192554Sthompsatypedef uint8_t (avr32dci_cmd_t)(struct avr32dci_td *td); 160192984Sthompsatypedef void (avr32dci_clocks_t)(struct usb_bus *); 161192554Sthompsa 162192554Sthompsastruct avr32dci_td { 163192554Sthompsa struct avr32dci_td *obj_next; 164192554Sthompsa avr32dci_cmd_t *func; 165192984Sthompsa struct usb_page_cache *pc; 166192554Sthompsa uint32_t offset; 167192554Sthompsa uint32_t remainder; 168192554Sthompsa uint16_t max_packet_size; 169229096Shselasky uint8_t bank_shift; 170192554Sthompsa uint8_t error:1; 171192554Sthompsa uint8_t alt_next:1; 172192554Sthompsa uint8_t short_pkt:1; 173192554Sthompsa uint8_t support_multi_buffer:1; 174192554Sthompsa uint8_t did_stall:1; 175192554Sthompsa uint8_t ep_no:3; 176192554Sthompsa}; 177192554Sthompsa 178192554Sthompsastruct avr32dci_std_temp { 179192554Sthompsa avr32dci_cmd_t *func; 180192984Sthompsa struct usb_page_cache *pc; 181192554Sthompsa struct avr32dci_td *td; 182192554Sthompsa struct avr32dci_td *td_next; 183192554Sthompsa uint32_t len; 184192554Sthompsa uint32_t offset; 185192554Sthompsa uint16_t max_frame_size; 186192554Sthompsa uint8_t bank_shift; 187192554Sthompsa uint8_t short_pkt; 188192554Sthompsa /* 189192554Sthompsa * short_pkt = 0: transfer should be short terminated 190192554Sthompsa * short_pkt = 1: transfer should not be short terminated 191192554Sthompsa */ 192192554Sthompsa uint8_t setup_alt_next; 193192554Sthompsa uint8_t did_stall; 194192554Sthompsa}; 195192554Sthompsa 196192554Sthompsastruct avr32dci_config_desc { 197192984Sthompsa struct usb_config_descriptor confd; 198192984Sthompsa struct usb_interface_descriptor ifcd; 199192984Sthompsa struct usb_endpoint_descriptor endpd; 200192554Sthompsa} __packed; 201192554Sthompsa 202192554Sthompsaunion avr32dci_hub_temp { 203192554Sthompsa uWord wValue; 204192984Sthompsa struct usb_port_status ps; 205192554Sthompsa}; 206192554Sthompsa 207192554Sthompsastruct avr32dci_flags { 208192554Sthompsa uint8_t change_connect:1; 209192554Sthompsa uint8_t change_suspend:1; 210192554Sthompsa uint8_t status_suspend:1; /* set if suspended */ 211192554Sthompsa uint8_t status_vbus:1; /* set if present */ 212192554Sthompsa uint8_t status_bus_reset:1; /* set if reset complete */ 213192554Sthompsa uint8_t remote_wakeup:1; 214192554Sthompsa uint8_t self_powered:1; 215192554Sthompsa uint8_t clocks_off:1; 216192554Sthompsa uint8_t port_powered:1; 217192554Sthompsa uint8_t port_enabled:1; 218192554Sthompsa uint8_t d_pulled_up:1; 219192554Sthompsa}; 220192554Sthompsa 221192554Sthompsastruct avr32dci_softc { 222192984Sthompsa struct usb_bus sc_bus; 223192554Sthompsa union avr32dci_hub_temp sc_hub_temp; 224192554Sthompsa 225192554Sthompsa /* must be set by by the bus interface layer */ 226192554Sthompsa avr32dci_clocks_t *sc_clocks_on; 227192554Sthompsa avr32dci_clocks_t *sc_clocks_off; 228192554Sthompsa 229192984Sthompsa struct usb_device *sc_devices[AVR32_MAX_DEVICES]; 230192554Sthompsa struct resource *sc_irq_res; 231192554Sthompsa void *sc_intr_hdl; 232192554Sthompsa struct resource *sc_io_res; 233192554Sthompsa bus_space_tag_t sc_io_tag; 234192554Sthompsa bus_space_handle_t sc_io_hdl; 235192554Sthompsa uint8_t *physdata; 236192554Sthompsa 237192554Sthompsa uint8_t sc_rt_addr; /* root hub address */ 238192554Sthompsa uint8_t sc_dv_addr; /* device address */ 239192554Sthompsa uint8_t sc_conf; /* root hub config */ 240192554Sthompsa 241192554Sthompsa uint8_t sc_hub_idata[1]; 242192554Sthompsa 243192554Sthompsa struct avr32dci_flags sc_flags; 244192554Sthompsa}; 245192554Sthompsa 246192554Sthompsa/* prototypes */ 247192554Sthompsa 248193045Sthompsausb_error_t avr32dci_init(struct avr32dci_softc *sc); 249192554Sthompsavoid avr32dci_uninit(struct avr32dci_softc *sc); 250192554Sthompsavoid avr32dci_interrupt(struct avr32dci_softc *sc); 251192554Sthompsavoid avr32dci_vbus_interrupt(struct avr32dci_softc *sc, uint8_t is_on); 252192554Sthompsa 253192554Sthompsa#endif /* _AVR32DCI_H_ */ 254