1184610Salfred/* $FreeBSD$ */ 2184610Salfred/*- 3184610Salfred * Copyright (c) 2006 ATMEL 4189002Sed * Copyright (c) 2007 Hans Petter Selasky <hselasky@FreeBSD.org> 5184610Salfred * All rights reserved. 6184610Salfred * 7184610Salfred * Redistribution and use in source and binary forms, with or without 8184610Salfred * modification, are permitted provided that the following conditions 9184610Salfred * are met: 10184610Salfred * 1. Redistributions of source code must retain the above copyright 11184610Salfred * notice, this list of conditions and the following disclaimer. 12184610Salfred * 2. Redistributions in binary form must reproduce the above copyright 13184610Salfred * notice, this list of conditions and the following disclaimer in the 14184610Salfred * documentation and/or other materials provided with the distribution. 15184610Salfred * 16184610Salfred * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17184610Salfred * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18184610Salfred * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19184610Salfred * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20184610Salfred * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21184610Salfred * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22184610Salfred * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23184610Salfred * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24184610Salfred * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25184610Salfred * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26184610Salfred * SUCH DAMAGE. 27184610Salfred */ 28184610Salfred 29184610Salfred/* 30190754Sthompsa * USB Device Port (UDP) register definition, based on "AT91RM9200.h" provided 31190754Sthompsa * by ATMEL. 32184610Salfred */ 33184610Salfred 34184610Salfred#ifndef _AT9100_DCI_H_ 35184610Salfred#define _AT9100_DCI_H_ 36184610Salfred 37187170Sthompsa#define AT91_MAX_DEVICES (USB_MIN_DEVICES + 1) 38187170Sthompsa 39184610Salfred#define AT91_UDP_FRM 0x00 /* Frame number register */ 40184610Salfred#define AT91_UDP_FRM_MASK (0x7FF << 0) /* Frame Number as Defined in 41184610Salfred * the Packet Field Formats */ 42184610Salfred#define AT91_UDP_FRM_ERR (0x1 << 16) /* Frame Error */ 43184610Salfred#define AT91_UDP_FRM_OK (0x1 << 17) /* Frame OK */ 44184610Salfred 45184610Salfred#define AT91_UDP_GSTATE 0x04 /* Global state register */ 46184610Salfred#define AT91_UDP_GSTATE_ADDR (0x1 << 0) /* Addressed state */ 47184610Salfred#define AT91_UDP_GSTATE_CONFG (0x1 << 1) /* Configured */ 48184610Salfred#define AT91_UDP_GSTATE_ESR (0x1 << 2) /* Enable Send Resume */ 49184610Salfred#define AT91_UDP_GSTATE_RSM (0x1 << 3) /* A Resume Has Been Sent to 50184610Salfred * the Host */ 51184610Salfred#define AT91_UDP_GSTATE_RMW (0x1 << 4) /* Remote Wake Up Enable */ 52184610Salfred 53184610Salfred#define AT91_UDP_FADDR 0x08 /* Function Address Register */ 54184610Salfred#define AT91_UDP_FADDR_MASK (0x7F << 0)/* Function Address Mask */ 55184610Salfred#define AT91_UDP_FADDR_EN (0x1 << 8)/* Function Enable */ 56184610Salfred 57184610Salfred#define AT91_UDP_RES0 0x0C /* Reserved 0 */ 58184610Salfred 59184610Salfred#define AT91_UDP_IER 0x10 /* Interrupt Enable Register */ 60184610Salfred#define AT91_UDP_IDR 0x14 /* Interrupt Disable Register */ 61184610Salfred#define AT91_UDP_IMR 0x18 /* Interrupt Mask Register */ 62184610Salfred#define AT91_UDP_ISR 0x1C /* Interrupt Status Register */ 63184610Salfred#define AT91_UDP_ICR 0x20 /* Interrupt Clear Register */ 64184610Salfred#define AT91_UDP_INT_EP(n) (0x1 <<(n))/* Endpoint "n" Interrupt */ 65184610Salfred#define AT91_UDP_INT_RXSUSP (0x1 << 8)/* USB Suspend Interrupt */ 66184610Salfred#define AT91_UDP_INT_RXRSM (0x1 << 9)/* USB Resume Interrupt */ 67184610Salfred#define AT91_UDP_INT_EXTRSM (0x1 << 10)/* USB External Resume Interrupt */ 68184610Salfred#define AT91_UDP_INT_SOFINT (0x1 << 11)/* USB Start Of frame Interrupt */ 69184610Salfred#define AT91_UDP_INT_END_BR (0x1 << 12)/* USB End Of Bus Reset Interrupt */ 70184610Salfred#define AT91_UDP_INT_WAKEUP (0x1 << 13)/* USB Resume Interrupt */ 71184610Salfred 72184610Salfred#define AT91_UDP_INT_BUS \ 73184610Salfred (AT91_UDP_INT_RXSUSP|AT91_UDP_INT_RXRSM| \ 74184610Salfred AT91_UDP_INT_END_BR) 75184610Salfred 76184610Salfred#define AT91_UDP_INT_EPS \ 77184610Salfred (AT91_UDP_INT_EP(0)|AT91_UDP_INT_EP(1)| \ 78184610Salfred AT91_UDP_INT_EP(2)|AT91_UDP_INT_EP(3)| \ 79184610Salfred AT91_UDP_INT_EP(4)|AT91_UDP_INT_EP(5)) 80184610Salfred 81184610Salfred#define AT91_UDP_INT_DEFAULT \ 82184610Salfred (AT91_UDP_INT_EPS|AT91_UDP_INT_BUS) 83184610Salfred 84184610Salfred#define AT91_UDP_RES1 0x24 /* Reserved 1 */ 85184610Salfred#define AT91_UDP_RST 0x28 /* Reset Endpoint Register */ 86184610Salfred#define AT91_UDP_RST_EP(n) (0x1 << (n))/* Reset Endpoint "n" */ 87184610Salfred 88184610Salfred#define AT91_UDP_RES2 0x2C /* Reserved 2 */ 89184610Salfred 90184610Salfred#define AT91_UDP_CSR(n) (0x30 + (4*(n)))/* Endpoint Control and Status 91184610Salfred * Register */ 92184610Salfred#define AT91_UDP_CSR_TXCOMP (0x1 << 0) /* Generates an IN packet with data 93184610Salfred * previously written in the DPR */ 94184610Salfred#define AT91_UDP_CSR_RX_DATA_BK0 (0x1 << 1) /* Receive Data Bank 0 */ 95184610Salfred#define AT91_UDP_CSR_RXSETUP (0x1 << 2) /* Sends STALL to the Host 96184610Salfred * (Control endpoints) */ 97184610Salfred#define AT91_UDP_CSR_ISOERROR (0x1 << 3) /* Isochronous error 98184610Salfred * (Isochronous endpoints) */ 99184610Salfred#define AT91_UDP_CSR_STALLSENT (0x1 << 3) /* Stall sent (Control, bulk, 100184610Salfred * interrupt endpoints) */ 101184610Salfred#define AT91_UDP_CSR_TXPKTRDY (0x1 << 4) /* Transmit Packet Ready */ 102184610Salfred#define AT91_UDP_CSR_FORCESTALL (0x1 << 5) /* Force Stall (used by 103184610Salfred * Control, Bulk and 104184610Salfred * Isochronous endpoints). */ 105184610Salfred#define AT91_UDP_CSR_RX_DATA_BK1 (0x1 << 6) /* Receive Data Bank 1 (only 106184610Salfred * used by endpoints with 107184610Salfred * ping-pong attributes). */ 108184610Salfred#define AT91_UDP_CSR_DIR (0x1 << 7) /* Transfer Direction */ 109184610Salfred#define AT91_UDP_CSR_ET_MASK (0x7 << 8) /* Endpoint transfer type mask */ 110184610Salfred#define AT91_UDP_CSR_ET_CTRL (0x0 << 8) /* Control IN+OUT */ 111184610Salfred#define AT91_UDP_CSR_ET_ISO (0x1 << 8) /* Isochronous */ 112184610Salfred#define AT91_UDP_CSR_ET_BULK (0x2 << 8) /* Bulk */ 113184610Salfred#define AT91_UDP_CSR_ET_INT (0x3 << 8) /* Interrupt */ 114184610Salfred#define AT91_UDP_CSR_ET_DIR_OUT (0x0 << 8) /* OUT tokens */ 115184610Salfred#define AT91_UDP_CSR_ET_DIR_IN (0x4 << 8) /* IN tokens */ 116184610Salfred#define AT91_UDP_CSR_DTGLE (0x1 << 11) /* Data Toggle */ 117184610Salfred#define AT91_UDP_CSR_EPEDS (0x1 << 15) /* Endpoint Enable Disable */ 118184610Salfred#define AT91_UDP_CSR_RXBYTECNT (0x7FF << 16) /* Number Of Bytes Available 119184610Salfred * in the FIFO */ 120184610Salfred 121184610Salfred#define AT91_UDP_FDR(n) (0x50 + (4*(n)))/* Endpoint FIFO Data Register */ 122184610Salfred#define AT91_UDP_RES3 0x70 /* Reserved 3 */ 123184610Salfred#define AT91_UDP_TXVC 0x74 /* Transceiver Control Register */ 124184610Salfred#define AT91_UDP_TXVC_DIS (0x1 << 8) 125184610Salfred 126184610Salfred#define AT91_UDP_EP_MAX 6 /* maximum number of endpoints 127184610Salfred * supported */ 128184610Salfred 129184610Salfred#define AT91_UDP_READ_4(sc, reg) \ 130184610Salfred bus_space_read_4((sc)->sc_io_tag, (sc)->sc_io_hdl, reg) 131184610Salfred 132184610Salfred#define AT91_UDP_WRITE_4(sc, reg, data) \ 133184610Salfred bus_space_write_4((sc)->sc_io_tag, (sc)->sc_io_hdl, reg, data) 134184610Salfred 135184610Salfredstruct at91dci_td; 136184610Salfred 137184610Salfredtypedef uint8_t (at91dci_cmd_t)(struct at91dci_td *td); 138184610Salfred 139184610Salfredstruct at91dci_td { 140184610Salfred bus_space_tag_t io_tag; 141184610Salfred bus_space_handle_t io_hdl; 142184610Salfred struct at91dci_td *obj_next; 143184610Salfred at91dci_cmd_t *func; 144192984Sthompsa struct usb_page_cache *pc; 145184610Salfred uint32_t offset; 146184610Salfred uint32_t remainder; 147184610Salfred uint16_t max_packet_size; 148184610Salfred uint8_t status_reg; 149184610Salfred uint8_t fifo_reg; 150184610Salfred uint8_t fifo_bank:1; 151184610Salfred uint8_t error:1; 152184610Salfred uint8_t alt_next:1; 153184610Salfred uint8_t short_pkt:1; 154184610Salfred uint8_t support_multi_buffer:1; 155184610Salfred uint8_t did_stall:1; 156184610Salfred}; 157184610Salfred 158184610Salfredstruct at91dci_std_temp { 159184610Salfred at91dci_cmd_t *func; 160192984Sthompsa struct usb_page_cache *pc; 161184610Salfred struct at91dci_td *td; 162184610Salfred struct at91dci_td *td_next; 163184610Salfred uint32_t len; 164184610Salfred uint32_t offset; 165184610Salfred uint16_t max_frame_size; 166184610Salfred uint8_t short_pkt; 167184610Salfred /* 168184610Salfred * short_pkt = 0: transfer should be short terminated 169184610Salfred * short_pkt = 1: transfer should not be short terminated 170184610Salfred */ 171184610Salfred uint8_t setup_alt_next; 172192552Sthompsa uint8_t did_stall; 173184610Salfred}; 174184610Salfred 175184610Salfredstruct at91dci_config_desc { 176192984Sthompsa struct usb_config_descriptor confd; 177192984Sthompsa struct usb_interface_descriptor ifcd; 178192984Sthompsa struct usb_endpoint_descriptor endpd; 179184610Salfred} __packed; 180184610Salfred 181184610Salfredunion at91dci_hub_temp { 182184610Salfred uWord wValue; 183192984Sthompsa struct usb_port_status ps; 184184610Salfred}; 185184610Salfred 186184610Salfredstruct at91dci_ep_flags { 187184610Salfred uint8_t fifo_bank:1; /* hardware specific */ 188184610Salfred}; 189184610Salfred 190184610Salfredstruct at91dci_flags { 191184610Salfred uint8_t change_connect:1; 192184610Salfred uint8_t change_suspend:1; 193184610Salfred uint8_t status_suspend:1; /* set if suspended */ 194184610Salfred uint8_t status_vbus:1; /* set if present */ 195184610Salfred uint8_t status_bus_reset:1; /* set if reset complete */ 196184610Salfred uint8_t remote_wakeup:1; 197184610Salfred uint8_t self_powered:1; 198184610Salfred uint8_t clocks_off:1; 199184610Salfred uint8_t port_powered:1; 200184610Salfred uint8_t port_enabled:1; 201184610Salfred uint8_t d_pulled_up:1; 202184610Salfred}; 203184610Salfred 204184610Salfredstruct at91dci_softc { 205192984Sthompsa struct usb_bus sc_bus; 206184610Salfred union at91dci_hub_temp sc_hub_temp; 207184610Salfred 208192984Sthompsa struct usb_device *sc_devices[AT91_MAX_DEVICES]; 209184610Salfred struct resource *sc_io_res; 210184610Salfred struct resource *sc_irq_res; 211184610Salfred void *sc_intr_hdl; 212184610Salfred bus_size_t sc_io_size; 213184610Salfred bus_space_tag_t sc_io_tag; 214184610Salfred bus_space_handle_t sc_io_hdl; 215184610Salfred 216184610Salfred void (*sc_clocks_on) (void *arg); 217184610Salfred void (*sc_clocks_off) (void *arg); 218184610Salfred void *sc_clocks_arg; 219184610Salfred 220184610Salfred void (*sc_pull_up) (void *arg); 221184610Salfred void (*sc_pull_down) (void *arg); 222184610Salfred void *sc_pull_arg; 223184610Salfred 224184610Salfred uint8_t sc_rt_addr; /* root HUB address */ 225184610Salfred uint8_t sc_dv_addr; /* device address */ 226184610Salfred uint8_t sc_conf; /* root HUB config */ 227184610Salfred 228184610Salfred uint8_t sc_hub_idata[1]; 229184610Salfred 230184610Salfred struct at91dci_flags sc_flags; 231184610Salfred struct at91dci_ep_flags sc_ep_flags[AT91_UDP_EP_MAX]; 232184610Salfred}; 233184610Salfred 234184610Salfred/* prototypes */ 235184610Salfred 236193045Sthompsausb_error_t at91dci_init(struct at91dci_softc *sc); 237184610Salfredvoid at91dci_uninit(struct at91dci_softc *sc); 238184610Salfredvoid at91dci_interrupt(struct at91dci_softc *sc); 239187175Sthompsavoid at91dci_vbus_interrupt(struct at91dci_softc *sc, uint8_t is_on); 240184610Salfred 241184610Salfred#endif /* _AT9100_DCI_H_ */ 242