at91dci.c revision 229080
1#include <sys/cdefs.h> 2__FBSDID("$FreeBSD: stable/9/sys/dev/usb/controller/at91dci.c 229080 2011-12-31 13:07:09Z hselasky $"); 3 4/*- 5 * Copyright (c) 2007-2008 Hans Petter Selasky. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29/* 30 * This file contains the driver for the AT91 series USB Device 31 * Controller 32 */ 33 34/* 35 * Thanks to "David Brownell" for helping out regarding the hardware 36 * endpoint profiles. 37 */ 38 39/* 40 * NOTE: The "fifo_bank" is not reset in hardware when the endpoint is 41 * reset. 42 * 43 * NOTE: When the chip detects BUS-reset it will also reset the 44 * endpoints, Function-address and more. 45 */ 46 47#include <sys/stdint.h> 48#include <sys/stddef.h> 49#include <sys/param.h> 50#include <sys/queue.h> 51#include <sys/types.h> 52#include <sys/systm.h> 53#include <sys/kernel.h> 54#include <sys/bus.h> 55#include <sys/module.h> 56#include <sys/lock.h> 57#include <sys/mutex.h> 58#include <sys/condvar.h> 59#include <sys/sysctl.h> 60#include <sys/sx.h> 61#include <sys/unistd.h> 62#include <sys/callout.h> 63#include <sys/malloc.h> 64#include <sys/priv.h> 65 66#include <dev/usb/usb.h> 67#include <dev/usb/usbdi.h> 68 69#define USB_DEBUG_VAR at91dcidebug 70 71#include <dev/usb/usb_core.h> 72#include <dev/usb/usb_debug.h> 73#include <dev/usb/usb_busdma.h> 74#include <dev/usb/usb_process.h> 75#include <dev/usb/usb_transfer.h> 76#include <dev/usb/usb_device.h> 77#include <dev/usb/usb_hub.h> 78#include <dev/usb/usb_util.h> 79 80#include <dev/usb/usb_controller.h> 81#include <dev/usb/usb_bus.h> 82#include <dev/usb/controller/at91dci.h> 83 84#define AT9100_DCI_BUS2SC(bus) \ 85 ((struct at91dci_softc *)(((uint8_t *)(bus)) - \ 86 ((uint8_t *)&(((struct at91dci_softc *)0)->sc_bus)))) 87 88#define AT9100_DCI_PC2SC(pc) \ 89 AT9100_DCI_BUS2SC(USB_DMATAG_TO_XROOT((pc)->tag_parent)->bus) 90 91#ifdef USB_DEBUG 92static int at91dcidebug = 0; 93 94SYSCTL_NODE(_hw_usb, OID_AUTO, at91dci, CTLFLAG_RW, 0, "USB at91dci"); 95SYSCTL_INT(_hw_usb_at91dci, OID_AUTO, debug, CTLFLAG_RW, 96 &at91dcidebug, 0, "at91dci debug level"); 97#endif 98 99#define AT9100_DCI_INTR_ENDPT 1 100 101/* prototypes */ 102 103struct usb_bus_methods at91dci_bus_methods; 104struct usb_pipe_methods at91dci_device_bulk_methods; 105struct usb_pipe_methods at91dci_device_ctrl_methods; 106struct usb_pipe_methods at91dci_device_intr_methods; 107struct usb_pipe_methods at91dci_device_isoc_fs_methods; 108 109static at91dci_cmd_t at91dci_setup_rx; 110static at91dci_cmd_t at91dci_data_rx; 111static at91dci_cmd_t at91dci_data_tx; 112static at91dci_cmd_t at91dci_data_tx_sync; 113static void at91dci_device_done(struct usb_xfer *, usb_error_t); 114static void at91dci_do_poll(struct usb_bus *); 115static void at91dci_standard_done(struct usb_xfer *); 116static void at91dci_root_intr(struct at91dci_softc *sc); 117 118/* 119 * NOTE: Some of the bits in the CSR register have inverse meaning so 120 * we need a helper macro when acknowledging events: 121 */ 122#define AT91_CSR_ACK(csr, what) do { \ 123 (csr) &= ~((AT91_UDP_CSR_FORCESTALL| \ 124 AT91_UDP_CSR_TXPKTRDY| \ 125 AT91_UDP_CSR_RXBYTECNT) ^ (what));\ 126 (csr) |= ((AT91_UDP_CSR_RX_DATA_BK0| \ 127 AT91_UDP_CSR_RX_DATA_BK1| \ 128 AT91_UDP_CSR_TXCOMP| \ 129 AT91_UDP_CSR_RXSETUP| \ 130 AT91_UDP_CSR_STALLSENT) ^ (what)); \ 131} while (0) 132 133/* 134 * Here is a list of what the chip supports. 135 * Probably it supports more than listed here! 136 */ 137static const struct usb_hw_ep_profile 138 at91dci_ep_profile[AT91_UDP_EP_MAX] = { 139 140 [0] = { 141 .max_in_frame_size = 8, 142 .max_out_frame_size = 8, 143 .is_simplex = 1, 144 .support_control = 1, 145 }, 146 [1] = { 147 .max_in_frame_size = 64, 148 .max_out_frame_size = 64, 149 .is_simplex = 1, 150 .support_multi_buffer = 1, 151 .support_bulk = 1, 152 .support_interrupt = 1, 153 .support_isochronous = 1, 154 .support_in = 1, 155 .support_out = 1, 156 }, 157 [2] = { 158 .max_in_frame_size = 64, 159 .max_out_frame_size = 64, 160 .is_simplex = 1, 161 .support_multi_buffer = 1, 162 .support_bulk = 1, 163 .support_interrupt = 1, 164 .support_isochronous = 1, 165 .support_in = 1, 166 .support_out = 1, 167 }, 168 [3] = { 169 /* can also do BULK */ 170 .max_in_frame_size = 8, 171 .max_out_frame_size = 8, 172 .is_simplex = 1, 173 .support_interrupt = 1, 174 .support_in = 1, 175 .support_out = 1, 176 }, 177 [4] = { 178 .max_in_frame_size = 256, 179 .max_out_frame_size = 256, 180 .is_simplex = 1, 181 .support_multi_buffer = 1, 182 .support_bulk = 1, 183 .support_interrupt = 1, 184 .support_isochronous = 1, 185 .support_in = 1, 186 .support_out = 1, 187 }, 188 [5] = { 189 .max_in_frame_size = 256, 190 .max_out_frame_size = 256, 191 .is_simplex = 1, 192 .support_multi_buffer = 1, 193 .support_bulk = 1, 194 .support_interrupt = 1, 195 .support_isochronous = 1, 196 .support_in = 1, 197 .support_out = 1, 198 }, 199}; 200 201static void 202at91dci_get_hw_ep_profile(struct usb_device *udev, 203 const struct usb_hw_ep_profile **ppf, uint8_t ep_addr) 204{ 205 if (ep_addr < AT91_UDP_EP_MAX) { 206 *ppf = (at91dci_ep_profile + ep_addr); 207 } else { 208 *ppf = NULL; 209 } 210} 211 212static void 213at91dci_clocks_on(struct at91dci_softc *sc) 214{ 215 if (sc->sc_flags.clocks_off && 216 sc->sc_flags.port_powered) { 217 218 DPRINTFN(5, "\n"); 219 220 if (sc->sc_clocks_on) { 221 (sc->sc_clocks_on) (sc->sc_clocks_arg); 222 } 223 sc->sc_flags.clocks_off = 0; 224 225 /* enable Transceiver */ 226 AT91_UDP_WRITE_4(sc, AT91_UDP_TXVC, 0); 227 } 228} 229 230static void 231at91dci_clocks_off(struct at91dci_softc *sc) 232{ 233 if (!sc->sc_flags.clocks_off) { 234 235 DPRINTFN(5, "\n"); 236 237 /* disable Transceiver */ 238 AT91_UDP_WRITE_4(sc, AT91_UDP_TXVC, AT91_UDP_TXVC_DIS); 239 240 if (sc->sc_clocks_off) { 241 (sc->sc_clocks_off) (sc->sc_clocks_arg); 242 } 243 sc->sc_flags.clocks_off = 1; 244 } 245} 246 247static void 248at91dci_pull_up(struct at91dci_softc *sc) 249{ 250 /* pullup D+, if possible */ 251 252 if (!sc->sc_flags.d_pulled_up && 253 sc->sc_flags.port_powered) { 254 sc->sc_flags.d_pulled_up = 1; 255 (sc->sc_pull_up) (sc->sc_pull_arg); 256 } 257} 258 259static void 260at91dci_pull_down(struct at91dci_softc *sc) 261{ 262 /* pulldown D+, if possible */ 263 264 if (sc->sc_flags.d_pulled_up) { 265 sc->sc_flags.d_pulled_up = 0; 266 (sc->sc_pull_down) (sc->sc_pull_arg); 267 } 268} 269 270static void 271at91dci_wakeup_peer(struct at91dci_softc *sc) 272{ 273 if (!(sc->sc_flags.status_suspend)) { 274 return; 275 } 276 277 AT91_UDP_WRITE_4(sc, AT91_UDP_GSTATE, AT91_UDP_GSTATE_ESR); 278 279 /* wait 8 milliseconds */ 280 /* Wait for reset to complete. */ 281 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 125); 282 283 AT91_UDP_WRITE_4(sc, AT91_UDP_GSTATE, 0); 284} 285 286static void 287at91dci_set_address(struct at91dci_softc *sc, uint8_t addr) 288{ 289 DPRINTFN(5, "addr=%d\n", addr); 290 291 AT91_UDP_WRITE_4(sc, AT91_UDP_FADDR, addr | 292 AT91_UDP_FADDR_EN); 293} 294 295static uint8_t 296at91dci_setup_rx(struct at91dci_td *td) 297{ 298 struct at91dci_softc *sc; 299 struct usb_device_request req; 300 uint32_t csr; 301 uint32_t temp; 302 uint16_t count; 303 304 /* read out FIFO status */ 305 csr = bus_space_read_4(td->io_tag, td->io_hdl, 306 td->status_reg); 307 308 DPRINTFN(5, "csr=0x%08x rem=%u\n", csr, td->remainder); 309 310 temp = csr; 311 temp &= (AT91_UDP_CSR_RX_DATA_BK0 | 312 AT91_UDP_CSR_RX_DATA_BK1 | 313 AT91_UDP_CSR_STALLSENT | 314 AT91_UDP_CSR_RXSETUP | 315 AT91_UDP_CSR_TXCOMP); 316 317 if (!(csr & AT91_UDP_CSR_RXSETUP)) { 318 goto not_complete; 319 } 320 /* clear did stall */ 321 td->did_stall = 0; 322 323 /* get the packet byte count */ 324 count = (csr & AT91_UDP_CSR_RXBYTECNT) >> 16; 325 326 /* verify data length */ 327 if (count != td->remainder) { 328 DPRINTFN(0, "Invalid SETUP packet " 329 "length, %d bytes\n", count); 330 goto not_complete; 331 } 332 if (count != sizeof(req)) { 333 DPRINTFN(0, "Unsupported SETUP packet " 334 "length, %d bytes\n", count); 335 goto not_complete; 336 } 337 /* receive data */ 338 bus_space_read_multi_1(td->io_tag, td->io_hdl, 339 td->fifo_reg, (void *)&req, sizeof(req)); 340 341 /* copy data into real buffer */ 342 usbd_copy_in(td->pc, 0, &req, sizeof(req)); 343 344 td->offset = sizeof(req); 345 td->remainder = 0; 346 347 /* get pointer to softc */ 348 sc = AT9100_DCI_PC2SC(td->pc); 349 350 /* sneak peek the set address */ 351 if ((req.bmRequestType == UT_WRITE_DEVICE) && 352 (req.bRequest == UR_SET_ADDRESS)) { 353 sc->sc_dv_addr = req.wValue[0] & 0x7F; 354 } else { 355 sc->sc_dv_addr = 0xFF; 356 } 357 358 /* sneak peek the endpoint direction */ 359 if (req.bmRequestType & UE_DIR_IN) { 360 csr |= AT91_UDP_CSR_DIR; 361 } else { 362 csr &= ~AT91_UDP_CSR_DIR; 363 } 364 365 /* write the direction of the control transfer */ 366 AT91_CSR_ACK(csr, temp); 367 bus_space_write_4(td->io_tag, td->io_hdl, 368 td->status_reg, csr); 369 return (0); /* complete */ 370 371not_complete: 372 /* abort any ongoing transfer */ 373 if (!td->did_stall) { 374 DPRINTFN(5, "stalling\n"); 375 temp |= AT91_UDP_CSR_FORCESTALL; 376 td->did_stall = 1; 377 } 378 379 /* clear interrupts, if any */ 380 if (temp) { 381 DPRINTFN(5, "clearing 0x%08x\n", temp); 382 AT91_CSR_ACK(csr, temp); 383 bus_space_write_4(td->io_tag, td->io_hdl, 384 td->status_reg, csr); 385 } 386 return (1); /* not complete */ 387 388} 389 390static uint8_t 391at91dci_data_rx(struct at91dci_td *td) 392{ 393 struct usb_page_search buf_res; 394 uint32_t csr; 395 uint32_t temp; 396 uint16_t count; 397 uint8_t to; 398 uint8_t got_short; 399 400 to = 2; /* don't loop forever! */ 401 got_short = 0; 402 403 /* check if any of the FIFO banks have data */ 404repeat: 405 /* read out FIFO status */ 406 csr = bus_space_read_4(td->io_tag, td->io_hdl, 407 td->status_reg); 408 409 DPRINTFN(5, "csr=0x%08x rem=%u\n", csr, td->remainder); 410 411 if (csr & AT91_UDP_CSR_RXSETUP) { 412 if (td->remainder == 0) { 413 /* 414 * We are actually complete and have 415 * received the next SETUP 416 */ 417 DPRINTFN(5, "faking complete\n"); 418 return (0); /* complete */ 419 } 420 /* 421 * USB Host Aborted the transfer. 422 */ 423 td->error = 1; 424 return (0); /* complete */ 425 } 426 /* Make sure that "STALLSENT" gets cleared */ 427 temp = csr; 428 temp &= AT91_UDP_CSR_STALLSENT; 429 430 /* check status */ 431 if (!(csr & (AT91_UDP_CSR_RX_DATA_BK0 | 432 AT91_UDP_CSR_RX_DATA_BK1))) { 433 if (temp) { 434 /* write command */ 435 AT91_CSR_ACK(csr, temp); 436 bus_space_write_4(td->io_tag, td->io_hdl, 437 td->status_reg, csr); 438 } 439 return (1); /* not complete */ 440 } 441 /* get the packet byte count */ 442 count = (csr & AT91_UDP_CSR_RXBYTECNT) >> 16; 443 444 /* verify the packet byte count */ 445 if (count != td->max_packet_size) { 446 if (count < td->max_packet_size) { 447 /* we have a short packet */ 448 td->short_pkt = 1; 449 got_short = 1; 450 } else { 451 /* invalid USB packet */ 452 td->error = 1; 453 return (0); /* we are complete */ 454 } 455 } 456 /* verify the packet byte count */ 457 if (count > td->remainder) { 458 /* invalid USB packet */ 459 td->error = 1; 460 return (0); /* we are complete */ 461 } 462 while (count > 0) { 463 usbd_get_page(td->pc, td->offset, &buf_res); 464 465 /* get correct length */ 466 if (buf_res.length > count) { 467 buf_res.length = count; 468 } 469 /* receive data */ 470 bus_space_read_multi_1(td->io_tag, td->io_hdl, 471 td->fifo_reg, buf_res.buffer, buf_res.length); 472 473 /* update counters */ 474 count -= buf_res.length; 475 td->offset += buf_res.length; 476 td->remainder -= buf_res.length; 477 } 478 479 /* clear status bits */ 480 if (td->support_multi_buffer) { 481 if (td->fifo_bank) { 482 td->fifo_bank = 0; 483 temp |= AT91_UDP_CSR_RX_DATA_BK1; 484 } else { 485 td->fifo_bank = 1; 486 temp |= AT91_UDP_CSR_RX_DATA_BK0; 487 } 488 } else { 489 temp |= (AT91_UDP_CSR_RX_DATA_BK0 | 490 AT91_UDP_CSR_RX_DATA_BK1); 491 } 492 493 /* write command */ 494 AT91_CSR_ACK(csr, temp); 495 bus_space_write_4(td->io_tag, td->io_hdl, 496 td->status_reg, csr); 497 498 /* 499 * NOTE: We may have to delay a little bit before 500 * proceeding after clearing the DATA_BK bits. 501 */ 502 503 /* check if we are complete */ 504 if ((td->remainder == 0) || got_short) { 505 if (td->short_pkt) { 506 /* we are complete */ 507 return (0); 508 } 509 /* else need to receive a zero length packet */ 510 } 511 if (--to) { 512 goto repeat; 513 } 514 return (1); /* not complete */ 515} 516 517static uint8_t 518at91dci_data_tx(struct at91dci_td *td) 519{ 520 struct usb_page_search buf_res; 521 uint32_t csr; 522 uint32_t temp; 523 uint16_t count; 524 uint8_t to; 525 526 to = 2; /* don't loop forever! */ 527 528repeat: 529 530 /* read out FIFO status */ 531 csr = bus_space_read_4(td->io_tag, td->io_hdl, 532 td->status_reg); 533 534 DPRINTFN(5, "csr=0x%08x rem=%u\n", csr, td->remainder); 535 536 if (csr & AT91_UDP_CSR_RXSETUP) { 537 /* 538 * The current transfer was aborted 539 * by the USB Host 540 */ 541 td->error = 1; 542 return (0); /* complete */ 543 } 544 /* Make sure that "STALLSENT" gets cleared */ 545 temp = csr; 546 temp &= AT91_UDP_CSR_STALLSENT; 547 548 if (csr & AT91_UDP_CSR_TXPKTRDY) { 549 if (temp) { 550 /* write command */ 551 AT91_CSR_ACK(csr, temp); 552 bus_space_write_4(td->io_tag, td->io_hdl, 553 td->status_reg, csr); 554 } 555 return (1); /* not complete */ 556 } else { 557 /* clear TXCOMP and set TXPKTRDY */ 558 temp |= (AT91_UDP_CSR_TXCOMP | 559 AT91_UDP_CSR_TXPKTRDY); 560 } 561 562 count = td->max_packet_size; 563 if (td->remainder < count) { 564 /* we have a short packet */ 565 td->short_pkt = 1; 566 count = td->remainder; 567 } 568 while (count > 0) { 569 570 usbd_get_page(td->pc, td->offset, &buf_res); 571 572 /* get correct length */ 573 if (buf_res.length > count) { 574 buf_res.length = count; 575 } 576 /* transmit data */ 577 bus_space_write_multi_1(td->io_tag, td->io_hdl, 578 td->fifo_reg, buf_res.buffer, buf_res.length); 579 580 /* update counters */ 581 count -= buf_res.length; 582 td->offset += buf_res.length; 583 td->remainder -= buf_res.length; 584 } 585 586 /* write command */ 587 AT91_CSR_ACK(csr, temp); 588 bus_space_write_4(td->io_tag, td->io_hdl, 589 td->status_reg, csr); 590 591 /* check remainder */ 592 if (td->remainder == 0) { 593 if (td->short_pkt) { 594 return (0); /* complete */ 595 } 596 /* else we need to transmit a short packet */ 597 } 598 if (--to) { 599 goto repeat; 600 } 601 return (1); /* not complete */ 602} 603 604static uint8_t 605at91dci_data_tx_sync(struct at91dci_td *td) 606{ 607 struct at91dci_softc *sc; 608 uint32_t csr; 609 uint32_t temp; 610 611#if 0 612repeat: 613#endif 614 615 /* read out FIFO status */ 616 csr = bus_space_read_4(td->io_tag, td->io_hdl, 617 td->status_reg); 618 619 DPRINTFN(5, "csr=0x%08x\n", csr); 620 621 if (csr & AT91_UDP_CSR_RXSETUP) { 622 DPRINTFN(5, "faking complete\n"); 623 /* Race condition */ 624 return (0); /* complete */ 625 } 626 temp = csr; 627 temp &= (AT91_UDP_CSR_STALLSENT | 628 AT91_UDP_CSR_TXCOMP); 629 630 /* check status */ 631 if (csr & AT91_UDP_CSR_TXPKTRDY) { 632 goto not_complete; 633 } 634 if (!(csr & AT91_UDP_CSR_TXCOMP)) { 635 goto not_complete; 636 } 637 sc = AT9100_DCI_PC2SC(td->pc); 638 if (sc->sc_dv_addr != 0xFF) { 639 /* 640 * The AT91 has a special requirement with regard to 641 * setting the address and that is to write the new 642 * address before clearing TXCOMP: 643 */ 644 at91dci_set_address(sc, sc->sc_dv_addr); 645 } 646 /* write command */ 647 AT91_CSR_ACK(csr, temp); 648 bus_space_write_4(td->io_tag, td->io_hdl, 649 td->status_reg, csr); 650 651 return (0); /* complete */ 652 653not_complete: 654 if (temp) { 655 /* write command */ 656 AT91_CSR_ACK(csr, temp); 657 bus_space_write_4(td->io_tag, td->io_hdl, 658 td->status_reg, csr); 659 } 660 return (1); /* not complete */ 661} 662 663static uint8_t 664at91dci_xfer_do_fifo(struct usb_xfer *xfer) 665{ 666 struct at91dci_softc *sc; 667 struct at91dci_td *td; 668 uint8_t temp; 669 670 DPRINTFN(9, "\n"); 671 672 td = xfer->td_transfer_cache; 673 while (1) { 674 if ((td->func) (td)) { 675 /* operation in progress */ 676 break; 677 } 678 if (((void *)td) == xfer->td_transfer_last) { 679 goto done; 680 } 681 if (td->error) { 682 goto done; 683 } else if (td->remainder > 0) { 684 /* 685 * We had a short transfer. If there is no alternate 686 * next, stop processing ! 687 */ 688 if (!td->alt_next) { 689 goto done; 690 } 691 } 692 /* 693 * Fetch the next transfer descriptor and transfer 694 * some flags to the next transfer descriptor 695 */ 696 temp = 0; 697 if (td->fifo_bank) 698 temp |= 1; 699 td = td->obj_next; 700 xfer->td_transfer_cache = td; 701 if (temp & 1) 702 td->fifo_bank = 1; 703 } 704 return (1); /* not complete */ 705 706done: 707 sc = AT9100_DCI_BUS2SC(xfer->xroot->bus); 708 temp = (xfer->endpointno & UE_ADDR); 709 710 /* update FIFO bank flag and multi buffer */ 711 if (td->fifo_bank) { 712 sc->sc_ep_flags[temp].fifo_bank = 1; 713 } else { 714 sc->sc_ep_flags[temp].fifo_bank = 0; 715 } 716 717 /* compute all actual lengths */ 718 719 at91dci_standard_done(xfer); 720 721 return (0); /* complete */ 722} 723 724static void 725at91dci_interrupt_poll(struct at91dci_softc *sc) 726{ 727 struct usb_xfer *xfer; 728 729repeat: 730 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 731 if (!at91dci_xfer_do_fifo(xfer)) { 732 /* queue has been modified */ 733 goto repeat; 734 } 735 } 736} 737 738void 739at91dci_vbus_interrupt(struct at91dci_softc *sc, uint8_t is_on) 740{ 741 DPRINTFN(5, "vbus = %u\n", is_on); 742 743 USB_BUS_LOCK(&sc->sc_bus); 744 if (is_on) { 745 if (!sc->sc_flags.status_vbus) { 746 sc->sc_flags.status_vbus = 1; 747 748 /* complete root HUB interrupt endpoint */ 749 at91dci_root_intr(sc); 750 } 751 } else { 752 if (sc->sc_flags.status_vbus) { 753 sc->sc_flags.status_vbus = 0; 754 sc->sc_flags.status_bus_reset = 0; 755 sc->sc_flags.status_suspend = 0; 756 sc->sc_flags.change_suspend = 0; 757 sc->sc_flags.change_connect = 1; 758 759 /* complete root HUB interrupt endpoint */ 760 at91dci_root_intr(sc); 761 } 762 } 763 USB_BUS_UNLOCK(&sc->sc_bus); 764} 765 766void 767at91dci_interrupt(struct at91dci_softc *sc) 768{ 769 uint32_t status; 770 771 USB_BUS_LOCK(&sc->sc_bus); 772 773 status = AT91_UDP_READ_4(sc, AT91_UDP_ISR); 774 status &= AT91_UDP_INT_DEFAULT; 775 776 if (!status) { 777 USB_BUS_UNLOCK(&sc->sc_bus); 778 return; 779 } 780 /* acknowledge interrupts */ 781 782 AT91_UDP_WRITE_4(sc, AT91_UDP_ICR, status); 783 784 /* check for any bus state change interrupts */ 785 786 if (status & AT91_UDP_INT_BUS) { 787 788 DPRINTFN(5, "real bus interrupt 0x%08x\n", status); 789 790 if (status & AT91_UDP_INT_END_BR) { 791 792 /* set correct state */ 793 sc->sc_flags.status_bus_reset = 1; 794 sc->sc_flags.status_suspend = 0; 795 sc->sc_flags.change_suspend = 0; 796 sc->sc_flags.change_connect = 1; 797 798 /* disable resume interrupt */ 799 AT91_UDP_WRITE_4(sc, AT91_UDP_IDR, 800 AT91_UDP_INT_RXRSM); 801 /* enable suspend interrupt */ 802 AT91_UDP_WRITE_4(sc, AT91_UDP_IER, 803 AT91_UDP_INT_RXSUSP); 804 } 805 /* 806 * If RXRSM and RXSUSP is set at the same time we interpret 807 * that like RESUME. Resume is set when there is at least 3 808 * milliseconds of inactivity on the USB BUS. 809 */ 810 if (status & AT91_UDP_INT_RXRSM) { 811 if (sc->sc_flags.status_suspend) { 812 sc->sc_flags.status_suspend = 0; 813 sc->sc_flags.change_suspend = 1; 814 815 /* disable resume interrupt */ 816 AT91_UDP_WRITE_4(sc, AT91_UDP_IDR, 817 AT91_UDP_INT_RXRSM); 818 /* enable suspend interrupt */ 819 AT91_UDP_WRITE_4(sc, AT91_UDP_IER, 820 AT91_UDP_INT_RXSUSP); 821 } 822 } else if (status & AT91_UDP_INT_RXSUSP) { 823 if (!sc->sc_flags.status_suspend) { 824 sc->sc_flags.status_suspend = 1; 825 sc->sc_flags.change_suspend = 1; 826 827 /* disable suspend interrupt */ 828 AT91_UDP_WRITE_4(sc, AT91_UDP_IDR, 829 AT91_UDP_INT_RXSUSP); 830 831 /* enable resume interrupt */ 832 AT91_UDP_WRITE_4(sc, AT91_UDP_IER, 833 AT91_UDP_INT_RXRSM); 834 } 835 } 836 /* complete root HUB interrupt endpoint */ 837 at91dci_root_intr(sc); 838 } 839 /* check for any endpoint interrupts */ 840 841 if (status & AT91_UDP_INT_EPS) { 842 843 DPRINTFN(5, "real endpoint interrupt 0x%08x\n", status); 844 845 at91dci_interrupt_poll(sc); 846 } 847 USB_BUS_UNLOCK(&sc->sc_bus); 848} 849 850static void 851at91dci_setup_standard_chain_sub(struct at91dci_std_temp *temp) 852{ 853 struct at91dci_td *td; 854 855 /* get current Transfer Descriptor */ 856 td = temp->td_next; 857 temp->td = td; 858 859 /* prepare for next TD */ 860 temp->td_next = td->obj_next; 861 862 /* fill out the Transfer Descriptor */ 863 td->func = temp->func; 864 td->pc = temp->pc; 865 td->offset = temp->offset; 866 td->remainder = temp->len; 867 td->fifo_bank = 0; 868 td->error = 0; 869 td->did_stall = temp->did_stall; 870 td->short_pkt = temp->short_pkt; 871 td->alt_next = temp->setup_alt_next; 872} 873 874static void 875at91dci_setup_standard_chain(struct usb_xfer *xfer) 876{ 877 struct at91dci_std_temp temp; 878 struct at91dci_softc *sc; 879 struct at91dci_td *td; 880 uint32_t x; 881 uint8_t ep_no; 882 uint8_t need_sync; 883 884 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n", 885 xfer->address, UE_GET_ADDR(xfer->endpointno), 886 xfer->sumlen, usbd_get_speed(xfer->xroot->udev)); 887 888 temp.max_frame_size = xfer->max_frame_size; 889 890 td = xfer->td_start[0]; 891 xfer->td_transfer_first = td; 892 xfer->td_transfer_cache = td; 893 894 /* setup temp */ 895 896 temp.pc = NULL; 897 temp.td = NULL; 898 temp.td_next = xfer->td_start[0]; 899 temp.offset = 0; 900 temp.setup_alt_next = xfer->flags_int.short_frames_ok; 901 temp.did_stall = !xfer->flags_int.control_stall; 902 903 sc = AT9100_DCI_BUS2SC(xfer->xroot->bus); 904 ep_no = (xfer->endpointno & UE_ADDR); 905 906 /* check if we should prepend a setup message */ 907 908 if (xfer->flags_int.control_xfr) { 909 if (xfer->flags_int.control_hdr) { 910 911 temp.func = &at91dci_setup_rx; 912 temp.len = xfer->frlengths[0]; 913 temp.pc = xfer->frbuffers + 0; 914 temp.short_pkt = temp.len ? 1 : 0; 915 /* check for last frame */ 916 if (xfer->nframes == 1) { 917 /* no STATUS stage yet, SETUP is last */ 918 if (xfer->flags_int.control_act) 919 temp.setup_alt_next = 0; 920 } 921 922 at91dci_setup_standard_chain_sub(&temp); 923 } 924 x = 1; 925 } else { 926 x = 0; 927 } 928 929 if (x != xfer->nframes) { 930 if (xfer->endpointno & UE_DIR_IN) { 931 temp.func = &at91dci_data_tx; 932 need_sync = 1; 933 } else { 934 temp.func = &at91dci_data_rx; 935 need_sync = 0; 936 } 937 938 /* setup "pc" pointer */ 939 temp.pc = xfer->frbuffers + x; 940 } else { 941 need_sync = 0; 942 } 943 while (x != xfer->nframes) { 944 945 /* DATA0 / DATA1 message */ 946 947 temp.len = xfer->frlengths[x]; 948 949 x++; 950 951 if (x == xfer->nframes) { 952 if (xfer->flags_int.control_xfr) { 953 if (xfer->flags_int.control_act) { 954 temp.setup_alt_next = 0; 955 } 956 } else { 957 temp.setup_alt_next = 0; 958 } 959 } 960 if (temp.len == 0) { 961 962 /* make sure that we send an USB packet */ 963 964 temp.short_pkt = 0; 965 966 } else { 967 968 /* regular data transfer */ 969 970 temp.short_pkt = (xfer->flags.force_short_xfer) ? 0 : 1; 971 } 972 973 at91dci_setup_standard_chain_sub(&temp); 974 975 if (xfer->flags_int.isochronous_xfr) { 976 temp.offset += temp.len; 977 } else { 978 /* get next Page Cache pointer */ 979 temp.pc = xfer->frbuffers + x; 980 } 981 } 982 983 /* check for control transfer */ 984 if (xfer->flags_int.control_xfr) { 985 986 /* always setup a valid "pc" pointer for status and sync */ 987 temp.pc = xfer->frbuffers + 0; 988 temp.len = 0; 989 temp.short_pkt = 0; 990 temp.setup_alt_next = 0; 991 992 /* check if we need to sync */ 993 if (need_sync) { 994 /* we need a SYNC point after TX */ 995 temp.func = &at91dci_data_tx_sync; 996 at91dci_setup_standard_chain_sub(&temp); 997 } 998 999 /* check if we should append a status stage */ 1000 if (!xfer->flags_int.control_act) { 1001 1002 /* 1003 * Send a DATA1 message and invert the current 1004 * endpoint direction. 1005 */ 1006 if (xfer->endpointno & UE_DIR_IN) { 1007 temp.func = &at91dci_data_rx; 1008 need_sync = 0; 1009 } else { 1010 temp.func = &at91dci_data_tx; 1011 need_sync = 1; 1012 } 1013 1014 at91dci_setup_standard_chain_sub(&temp); 1015 if (need_sync) { 1016 /* we need a SYNC point after TX */ 1017 temp.func = &at91dci_data_tx_sync; 1018 at91dci_setup_standard_chain_sub(&temp); 1019 } 1020 } 1021 } 1022 1023 /* must have at least one frame! */ 1024 td = temp.td; 1025 xfer->td_transfer_last = td; 1026 1027 /* setup the correct fifo bank */ 1028 if (sc->sc_ep_flags[ep_no].fifo_bank) { 1029 td = xfer->td_transfer_first; 1030 td->fifo_bank = 1; 1031 } 1032} 1033 1034static void 1035at91dci_timeout(void *arg) 1036{ 1037 struct usb_xfer *xfer = arg; 1038 1039 DPRINTF("xfer=%p\n", xfer); 1040 1041 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 1042 1043 /* transfer is transferred */ 1044 at91dci_device_done(xfer, USB_ERR_TIMEOUT); 1045} 1046 1047static void 1048at91dci_start_standard_chain(struct usb_xfer *xfer) 1049{ 1050 DPRINTFN(9, "\n"); 1051 1052 /* poll one time */ 1053 if (at91dci_xfer_do_fifo(xfer)) { 1054 1055 struct at91dci_softc *sc = AT9100_DCI_BUS2SC(xfer->xroot->bus); 1056 uint8_t ep_no = xfer->endpointno & UE_ADDR; 1057 1058 /* 1059 * Only enable the endpoint interrupt when we are actually 1060 * waiting for data, hence we are dealing with level 1061 * triggered interrupts ! 1062 */ 1063 AT91_UDP_WRITE_4(sc, AT91_UDP_IER, AT91_UDP_INT_EP(ep_no)); 1064 1065 DPRINTFN(15, "enable interrupts on endpoint %d\n", ep_no); 1066 1067 /* put transfer on interrupt queue */ 1068 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 1069 1070 /* start timeout, if any */ 1071 if (xfer->timeout != 0) { 1072 usbd_transfer_timeout_ms(xfer, 1073 &at91dci_timeout, xfer->timeout); 1074 } 1075 } 1076} 1077 1078static void 1079at91dci_root_intr(struct at91dci_softc *sc) 1080{ 1081 DPRINTFN(9, "\n"); 1082 1083 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1084 1085 /* set port bit */ 1086 sc->sc_hub_idata[0] = 0x02; /* we only have one port */ 1087 1088 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, 1089 sizeof(sc->sc_hub_idata)); 1090} 1091 1092static usb_error_t 1093at91dci_standard_done_sub(struct usb_xfer *xfer) 1094{ 1095 struct at91dci_td *td; 1096 uint32_t len; 1097 uint8_t error; 1098 1099 DPRINTFN(9, "\n"); 1100 1101 td = xfer->td_transfer_cache; 1102 1103 do { 1104 len = td->remainder; 1105 1106 if (xfer->aframes != xfer->nframes) { 1107 /* 1108 * Verify the length and subtract 1109 * the remainder from "frlengths[]": 1110 */ 1111 if (len > xfer->frlengths[xfer->aframes]) { 1112 td->error = 1; 1113 } else { 1114 xfer->frlengths[xfer->aframes] -= len; 1115 } 1116 } 1117 /* Check for transfer error */ 1118 if (td->error) { 1119 /* the transfer is finished */ 1120 error = 1; 1121 td = NULL; 1122 break; 1123 } 1124 /* Check for short transfer */ 1125 if (len > 0) { 1126 if (xfer->flags_int.short_frames_ok) { 1127 /* follow alt next */ 1128 if (td->alt_next) { 1129 td = td->obj_next; 1130 } else { 1131 td = NULL; 1132 } 1133 } else { 1134 /* the transfer is finished */ 1135 td = NULL; 1136 } 1137 error = 0; 1138 break; 1139 } 1140 td = td->obj_next; 1141 1142 /* this USB frame is complete */ 1143 error = 0; 1144 break; 1145 1146 } while (0); 1147 1148 /* update transfer cache */ 1149 1150 xfer->td_transfer_cache = td; 1151 1152 return (error ? 1153 USB_ERR_STALLED : USB_ERR_NORMAL_COMPLETION); 1154} 1155 1156static void 1157at91dci_standard_done(struct usb_xfer *xfer) 1158{ 1159 usb_error_t err = 0; 1160 1161 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 1162 xfer, xfer->endpoint); 1163 1164 /* reset scanner */ 1165 1166 xfer->td_transfer_cache = xfer->td_transfer_first; 1167 1168 if (xfer->flags_int.control_xfr) { 1169 1170 if (xfer->flags_int.control_hdr) { 1171 1172 err = at91dci_standard_done_sub(xfer); 1173 } 1174 xfer->aframes = 1; 1175 1176 if (xfer->td_transfer_cache == NULL) { 1177 goto done; 1178 } 1179 } 1180 while (xfer->aframes != xfer->nframes) { 1181 1182 err = at91dci_standard_done_sub(xfer); 1183 xfer->aframes++; 1184 1185 if (xfer->td_transfer_cache == NULL) { 1186 goto done; 1187 } 1188 } 1189 1190 if (xfer->flags_int.control_xfr && 1191 !xfer->flags_int.control_act) { 1192 1193 err = at91dci_standard_done_sub(xfer); 1194 } 1195done: 1196 at91dci_device_done(xfer, err); 1197} 1198 1199/*------------------------------------------------------------------------* 1200 * at91dci_device_done 1201 * 1202 * NOTE: this function can be called more than one time on the 1203 * same USB transfer! 1204 *------------------------------------------------------------------------*/ 1205static void 1206at91dci_device_done(struct usb_xfer *xfer, usb_error_t error) 1207{ 1208 struct at91dci_softc *sc = AT9100_DCI_BUS2SC(xfer->xroot->bus); 1209 uint8_t ep_no; 1210 1211 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1212 1213 DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n", 1214 xfer, xfer->endpoint, error); 1215 1216 if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) { 1217 ep_no = (xfer->endpointno & UE_ADDR); 1218 1219 /* disable endpoint interrupt */ 1220 AT91_UDP_WRITE_4(sc, AT91_UDP_IDR, AT91_UDP_INT_EP(ep_no)); 1221 1222 DPRINTFN(15, "disable interrupts on endpoint %d\n", ep_no); 1223 } 1224 /* dequeue transfer and start next transfer */ 1225 usbd_transfer_done(xfer, error); 1226} 1227 1228static void 1229at91dci_set_stall(struct usb_device *udev, struct usb_xfer *xfer, 1230 struct usb_endpoint *ep, uint8_t *did_stall) 1231{ 1232 struct at91dci_softc *sc; 1233 uint32_t csr_val; 1234 uint8_t csr_reg; 1235 1236 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 1237 1238 DPRINTFN(5, "endpoint=%p\n", ep); 1239 1240 if (xfer) { 1241 /* cancel any ongoing transfers */ 1242 at91dci_device_done(xfer, USB_ERR_STALLED); 1243 } 1244 /* set FORCESTALL */ 1245 sc = AT9100_DCI_BUS2SC(udev->bus); 1246 csr_reg = (ep->edesc->bEndpointAddress & UE_ADDR); 1247 csr_reg = AT91_UDP_CSR(csr_reg); 1248 csr_val = AT91_UDP_READ_4(sc, csr_reg); 1249 AT91_CSR_ACK(csr_val, AT91_UDP_CSR_FORCESTALL); 1250 AT91_UDP_WRITE_4(sc, csr_reg, csr_val); 1251} 1252 1253static void 1254at91dci_clear_stall_sub(struct at91dci_softc *sc, uint8_t ep_no, 1255 uint8_t ep_type, uint8_t ep_dir) 1256{ 1257 const struct usb_hw_ep_profile *pf; 1258 uint32_t csr_val; 1259 uint32_t temp; 1260 uint8_t csr_reg; 1261 uint8_t to; 1262 1263 if (ep_type == UE_CONTROL) { 1264 /* clearing stall is not needed */ 1265 return; 1266 } 1267 /* compute CSR register offset */ 1268 csr_reg = AT91_UDP_CSR(ep_no); 1269 1270 /* compute default CSR value */ 1271 csr_val = 0; 1272 AT91_CSR_ACK(csr_val, 0); 1273 1274 /* disable endpoint */ 1275 AT91_UDP_WRITE_4(sc, csr_reg, csr_val); 1276 1277 /* get endpoint profile */ 1278 at91dci_get_hw_ep_profile(NULL, &pf, ep_no); 1279 1280 /* reset FIFO */ 1281 AT91_UDP_WRITE_4(sc, AT91_UDP_RST, AT91_UDP_RST_EP(ep_no)); 1282 AT91_UDP_WRITE_4(sc, AT91_UDP_RST, 0); 1283 1284 /* 1285 * NOTE: One would assume that a FIFO reset would release the 1286 * FIFO banks aswell, but it doesn't! We have to do this 1287 * manually! 1288 */ 1289 1290 /* release FIFO banks, if any */ 1291 for (to = 0; to != 2; to++) { 1292 1293 /* get csr value */ 1294 csr_val = AT91_UDP_READ_4(sc, csr_reg); 1295 1296 if (csr_val & (AT91_UDP_CSR_RX_DATA_BK0 | 1297 AT91_UDP_CSR_RX_DATA_BK1)) { 1298 /* clear status bits */ 1299 if (pf->support_multi_buffer) { 1300 if (sc->sc_ep_flags[ep_no].fifo_bank) { 1301 sc->sc_ep_flags[ep_no].fifo_bank = 0; 1302 temp = AT91_UDP_CSR_RX_DATA_BK1; 1303 } else { 1304 sc->sc_ep_flags[ep_no].fifo_bank = 1; 1305 temp = AT91_UDP_CSR_RX_DATA_BK0; 1306 } 1307 } else { 1308 temp = (AT91_UDP_CSR_RX_DATA_BK0 | 1309 AT91_UDP_CSR_RX_DATA_BK1); 1310 } 1311 } else { 1312 temp = 0; 1313 } 1314 1315 /* clear FORCESTALL */ 1316 temp |= AT91_UDP_CSR_STALLSENT; 1317 1318 AT91_CSR_ACK(csr_val, temp); 1319 AT91_UDP_WRITE_4(sc, csr_reg, csr_val); 1320 } 1321 1322 /* compute default CSR value */ 1323 csr_val = 0; 1324 AT91_CSR_ACK(csr_val, 0); 1325 1326 /* enable endpoint */ 1327 csr_val &= ~AT91_UDP_CSR_ET_MASK; 1328 csr_val |= AT91_UDP_CSR_EPEDS; 1329 1330 if (ep_type == UE_CONTROL) { 1331 csr_val |= AT91_UDP_CSR_ET_CTRL; 1332 } else { 1333 if (ep_type == UE_BULK) { 1334 csr_val |= AT91_UDP_CSR_ET_BULK; 1335 } else if (ep_type == UE_INTERRUPT) { 1336 csr_val |= AT91_UDP_CSR_ET_INT; 1337 } else { 1338 csr_val |= AT91_UDP_CSR_ET_ISO; 1339 } 1340 if (ep_dir & UE_DIR_IN) { 1341 csr_val |= AT91_UDP_CSR_ET_DIR_IN; 1342 } 1343 } 1344 1345 /* enable endpoint */ 1346 AT91_UDP_WRITE_4(sc, AT91_UDP_CSR(ep_no), csr_val); 1347} 1348 1349static void 1350at91dci_clear_stall(struct usb_device *udev, struct usb_endpoint *ep) 1351{ 1352 struct at91dci_softc *sc; 1353 struct usb_endpoint_descriptor *ed; 1354 1355 DPRINTFN(5, "endpoint=%p\n", ep); 1356 1357 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 1358 1359 /* check mode */ 1360 if (udev->flags.usb_mode != USB_MODE_DEVICE) { 1361 /* not supported */ 1362 return; 1363 } 1364 /* get softc */ 1365 sc = AT9100_DCI_BUS2SC(udev->bus); 1366 1367 /* get endpoint descriptor */ 1368 ed = ep->edesc; 1369 1370 /* reset endpoint */ 1371 at91dci_clear_stall_sub(sc, 1372 (ed->bEndpointAddress & UE_ADDR), 1373 (ed->bmAttributes & UE_XFERTYPE), 1374 (ed->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT))); 1375} 1376 1377usb_error_t 1378at91dci_init(struct at91dci_softc *sc) 1379{ 1380 uint32_t csr_val; 1381 uint8_t n; 1382 1383 DPRINTF("start\n"); 1384 1385 /* set up the bus structure */ 1386 sc->sc_bus.usbrev = USB_REV_1_1; 1387 sc->sc_bus.methods = &at91dci_bus_methods; 1388 1389 USB_BUS_LOCK(&sc->sc_bus); 1390 1391 /* turn on clocks */ 1392 1393 if (sc->sc_clocks_on) { 1394 (sc->sc_clocks_on) (sc->sc_clocks_arg); 1395 } 1396 /* wait a little for things to stabilise */ 1397 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 1000); 1398 1399 /* disable and clear all interrupts */ 1400 1401 AT91_UDP_WRITE_4(sc, AT91_UDP_IDR, 0xFFFFFFFF); 1402 AT91_UDP_WRITE_4(sc, AT91_UDP_ICR, 0xFFFFFFFF); 1403 1404 /* compute default CSR value */ 1405 1406 csr_val = 0; 1407 AT91_CSR_ACK(csr_val, 0); 1408 1409 /* disable all endpoints */ 1410 1411 for (n = 0; n != AT91_UDP_EP_MAX; n++) { 1412 1413 /* disable endpoint */ 1414 AT91_UDP_WRITE_4(sc, AT91_UDP_CSR(n), csr_val); 1415 } 1416 1417 /* enable the control endpoint */ 1418 1419 AT91_CSR_ACK(csr_val, AT91_UDP_CSR_ET_CTRL | 1420 AT91_UDP_CSR_EPEDS); 1421 1422 /* write to FIFO control register */ 1423 1424 AT91_UDP_WRITE_4(sc, AT91_UDP_CSR(0), csr_val); 1425 1426 /* enable the interrupts we want */ 1427 1428 AT91_UDP_WRITE_4(sc, AT91_UDP_IER, AT91_UDP_INT_BUS); 1429 1430 /* turn off clocks */ 1431 1432 at91dci_clocks_off(sc); 1433 1434 USB_BUS_UNLOCK(&sc->sc_bus); 1435 1436 /* catch any lost interrupts */ 1437 1438 at91dci_do_poll(&sc->sc_bus); 1439 1440 return (0); /* success */ 1441} 1442 1443void 1444at91dci_uninit(struct at91dci_softc *sc) 1445{ 1446 USB_BUS_LOCK(&sc->sc_bus); 1447 1448 /* disable and clear all interrupts */ 1449 AT91_UDP_WRITE_4(sc, AT91_UDP_IDR, 0xFFFFFFFF); 1450 AT91_UDP_WRITE_4(sc, AT91_UDP_ICR, 0xFFFFFFFF); 1451 1452 sc->sc_flags.port_powered = 0; 1453 sc->sc_flags.status_vbus = 0; 1454 sc->sc_flags.status_bus_reset = 0; 1455 sc->sc_flags.status_suspend = 0; 1456 sc->sc_flags.change_suspend = 0; 1457 sc->sc_flags.change_connect = 1; 1458 1459 at91dci_pull_down(sc); 1460 at91dci_clocks_off(sc); 1461 USB_BUS_UNLOCK(&sc->sc_bus); 1462} 1463 1464void 1465at91dci_suspend(struct at91dci_softc *sc) 1466{ 1467 return; 1468} 1469 1470void 1471at91dci_resume(struct at91dci_softc *sc) 1472{ 1473 return; 1474} 1475 1476static void 1477at91dci_do_poll(struct usb_bus *bus) 1478{ 1479 struct at91dci_softc *sc = AT9100_DCI_BUS2SC(bus); 1480 1481 USB_BUS_LOCK(&sc->sc_bus); 1482 at91dci_interrupt_poll(sc); 1483 USB_BUS_UNLOCK(&sc->sc_bus); 1484} 1485 1486/*------------------------------------------------------------------------* 1487 * at91dci bulk support 1488 *------------------------------------------------------------------------*/ 1489static void 1490at91dci_device_bulk_open(struct usb_xfer *xfer) 1491{ 1492 return; 1493} 1494 1495static void 1496at91dci_device_bulk_close(struct usb_xfer *xfer) 1497{ 1498 at91dci_device_done(xfer, USB_ERR_CANCELLED); 1499} 1500 1501static void 1502at91dci_device_bulk_enter(struct usb_xfer *xfer) 1503{ 1504 return; 1505} 1506 1507static void 1508at91dci_device_bulk_start(struct usb_xfer *xfer) 1509{ 1510 /* setup TDs */ 1511 at91dci_setup_standard_chain(xfer); 1512 at91dci_start_standard_chain(xfer); 1513} 1514 1515struct usb_pipe_methods at91dci_device_bulk_methods = 1516{ 1517 .open = at91dci_device_bulk_open, 1518 .close = at91dci_device_bulk_close, 1519 .enter = at91dci_device_bulk_enter, 1520 .start = at91dci_device_bulk_start, 1521}; 1522 1523/*------------------------------------------------------------------------* 1524 * at91dci control support 1525 *------------------------------------------------------------------------*/ 1526static void 1527at91dci_device_ctrl_open(struct usb_xfer *xfer) 1528{ 1529 return; 1530} 1531 1532static void 1533at91dci_device_ctrl_close(struct usb_xfer *xfer) 1534{ 1535 at91dci_device_done(xfer, USB_ERR_CANCELLED); 1536} 1537 1538static void 1539at91dci_device_ctrl_enter(struct usb_xfer *xfer) 1540{ 1541 return; 1542} 1543 1544static void 1545at91dci_device_ctrl_start(struct usb_xfer *xfer) 1546{ 1547 /* setup TDs */ 1548 at91dci_setup_standard_chain(xfer); 1549 at91dci_start_standard_chain(xfer); 1550} 1551 1552struct usb_pipe_methods at91dci_device_ctrl_methods = 1553{ 1554 .open = at91dci_device_ctrl_open, 1555 .close = at91dci_device_ctrl_close, 1556 .enter = at91dci_device_ctrl_enter, 1557 .start = at91dci_device_ctrl_start, 1558}; 1559 1560/*------------------------------------------------------------------------* 1561 * at91dci interrupt support 1562 *------------------------------------------------------------------------*/ 1563static void 1564at91dci_device_intr_open(struct usb_xfer *xfer) 1565{ 1566 return; 1567} 1568 1569static void 1570at91dci_device_intr_close(struct usb_xfer *xfer) 1571{ 1572 at91dci_device_done(xfer, USB_ERR_CANCELLED); 1573} 1574 1575static void 1576at91dci_device_intr_enter(struct usb_xfer *xfer) 1577{ 1578 return; 1579} 1580 1581static void 1582at91dci_device_intr_start(struct usb_xfer *xfer) 1583{ 1584 /* setup TDs */ 1585 at91dci_setup_standard_chain(xfer); 1586 at91dci_start_standard_chain(xfer); 1587} 1588 1589struct usb_pipe_methods at91dci_device_intr_methods = 1590{ 1591 .open = at91dci_device_intr_open, 1592 .close = at91dci_device_intr_close, 1593 .enter = at91dci_device_intr_enter, 1594 .start = at91dci_device_intr_start, 1595}; 1596 1597/*------------------------------------------------------------------------* 1598 * at91dci full speed isochronous support 1599 *------------------------------------------------------------------------*/ 1600static void 1601at91dci_device_isoc_fs_open(struct usb_xfer *xfer) 1602{ 1603 return; 1604} 1605 1606static void 1607at91dci_device_isoc_fs_close(struct usb_xfer *xfer) 1608{ 1609 at91dci_device_done(xfer, USB_ERR_CANCELLED); 1610} 1611 1612static void 1613at91dci_device_isoc_fs_enter(struct usb_xfer *xfer) 1614{ 1615 struct at91dci_softc *sc = AT9100_DCI_BUS2SC(xfer->xroot->bus); 1616 uint32_t temp; 1617 uint32_t nframes; 1618 1619 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n", 1620 xfer, xfer->endpoint->isoc_next, xfer->nframes); 1621 1622 /* get the current frame index */ 1623 1624 nframes = AT91_UDP_READ_4(sc, AT91_UDP_FRM); 1625 1626 /* 1627 * check if the frame index is within the window where the frames 1628 * will be inserted 1629 */ 1630 temp = (nframes - xfer->endpoint->isoc_next) & AT91_UDP_FRM_MASK; 1631 1632 if ((xfer->endpoint->is_synced == 0) || 1633 (temp < xfer->nframes)) { 1634 /* 1635 * If there is data underflow or the endpoint queue is 1636 * empty we schedule the transfer a few frames ahead 1637 * of the current frame position. Else two isochronous 1638 * transfers might overlap. 1639 */ 1640 xfer->endpoint->isoc_next = (nframes + 3) & AT91_UDP_FRM_MASK; 1641 xfer->endpoint->is_synced = 1; 1642 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next); 1643 } 1644 /* 1645 * compute how many milliseconds the insertion is ahead of the 1646 * current frame position: 1647 */ 1648 temp = (xfer->endpoint->isoc_next - nframes) & AT91_UDP_FRM_MASK; 1649 1650 /* 1651 * pre-compute when the isochronous transfer will be finished: 1652 */ 1653 xfer->isoc_time_complete = 1654 usb_isoc_time_expand(&sc->sc_bus, nframes) + temp + 1655 xfer->nframes; 1656 1657 /* compute frame number for next insertion */ 1658 xfer->endpoint->isoc_next += xfer->nframes; 1659 1660 /* setup TDs */ 1661 at91dci_setup_standard_chain(xfer); 1662} 1663 1664static void 1665at91dci_device_isoc_fs_start(struct usb_xfer *xfer) 1666{ 1667 /* start TD chain */ 1668 at91dci_start_standard_chain(xfer); 1669} 1670 1671struct usb_pipe_methods at91dci_device_isoc_fs_methods = 1672{ 1673 .open = at91dci_device_isoc_fs_open, 1674 .close = at91dci_device_isoc_fs_close, 1675 .enter = at91dci_device_isoc_fs_enter, 1676 .start = at91dci_device_isoc_fs_start, 1677}; 1678 1679/*------------------------------------------------------------------------* 1680 * at91dci root control support 1681 *------------------------------------------------------------------------* 1682 * Simulate a hardware HUB by handling all the necessary requests. 1683 *------------------------------------------------------------------------*/ 1684 1685static const struct usb_device_descriptor at91dci_devd = { 1686 .bLength = sizeof(struct usb_device_descriptor), 1687 .bDescriptorType = UDESC_DEVICE, 1688 .bcdUSB = {0x00, 0x02}, 1689 .bDeviceClass = UDCLASS_HUB, 1690 .bDeviceSubClass = UDSUBCLASS_HUB, 1691 .bDeviceProtocol = UDPROTO_FSHUB, 1692 .bMaxPacketSize = 64, 1693 .bcdDevice = {0x00, 0x01}, 1694 .iManufacturer = 1, 1695 .iProduct = 2, 1696 .bNumConfigurations = 1, 1697}; 1698 1699static const struct at91dci_config_desc at91dci_confd = { 1700 .confd = { 1701 .bLength = sizeof(struct usb_config_descriptor), 1702 .bDescriptorType = UDESC_CONFIG, 1703 .wTotalLength[0] = sizeof(at91dci_confd), 1704 .bNumInterface = 1, 1705 .bConfigurationValue = 1, 1706 .iConfiguration = 0, 1707 .bmAttributes = UC_SELF_POWERED, 1708 .bMaxPower = 0, 1709 }, 1710 .ifcd = { 1711 .bLength = sizeof(struct usb_interface_descriptor), 1712 .bDescriptorType = UDESC_INTERFACE, 1713 .bNumEndpoints = 1, 1714 .bInterfaceClass = UICLASS_HUB, 1715 .bInterfaceSubClass = UISUBCLASS_HUB, 1716 .bInterfaceProtocol = 0, 1717 }, 1718 .endpd = { 1719 .bLength = sizeof(struct usb_endpoint_descriptor), 1720 .bDescriptorType = UDESC_ENDPOINT, 1721 .bEndpointAddress = (UE_DIR_IN | AT9100_DCI_INTR_ENDPT), 1722 .bmAttributes = UE_INTERRUPT, 1723 .wMaxPacketSize[0] = 8, 1724 .bInterval = 255, 1725 }, 1726}; 1727 1728static const struct usb_hub_descriptor_min at91dci_hubd = { 1729 .bDescLength = sizeof(at91dci_hubd), 1730 .bDescriptorType = UDESC_HUB, 1731 .bNbrPorts = 1, 1732 .wHubCharacteristics[0] = 1733 (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL) & 0xFF, 1734 .wHubCharacteristics[1] = 1735 (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL) >> 8, 1736 .bPwrOn2PwrGood = 50, 1737 .bHubContrCurrent = 0, 1738 .DeviceRemovable = {0}, /* port is removable */ 1739}; 1740 1741#define STRING_LANG \ 1742 0x09, 0x04, /* American English */ 1743 1744#define STRING_VENDOR \ 1745 'A', 0, 'T', 0, 'M', 0, 'E', 0, 'L', 0 1746 1747#define STRING_PRODUCT \ 1748 'D', 0, 'C', 0, 'I', 0, ' ', 0, 'R', 0, \ 1749 'o', 0, 'o', 0, 't', 0, ' ', 0, 'H', 0, \ 1750 'U', 0, 'B', 0, 1751 1752USB_MAKE_STRING_DESC(STRING_LANG, at91dci_langtab); 1753USB_MAKE_STRING_DESC(STRING_VENDOR, at91dci_vendor); 1754USB_MAKE_STRING_DESC(STRING_PRODUCT, at91dci_product); 1755 1756static usb_error_t 1757at91dci_roothub_exec(struct usb_device *udev, 1758 struct usb_device_request *req, const void **pptr, uint16_t *plength) 1759{ 1760 struct at91dci_softc *sc = AT9100_DCI_BUS2SC(udev->bus); 1761 const void *ptr; 1762 uint16_t len; 1763 uint16_t value; 1764 uint16_t index; 1765 usb_error_t err; 1766 1767 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1768 1769 /* buffer reset */ 1770 ptr = (const void *)&sc->sc_hub_temp; 1771 len = 0; 1772 err = 0; 1773 1774 value = UGETW(req->wValue); 1775 index = UGETW(req->wIndex); 1776 1777 /* demultiplex the control request */ 1778 1779 switch (req->bmRequestType) { 1780 case UT_READ_DEVICE: 1781 switch (req->bRequest) { 1782 case UR_GET_DESCRIPTOR: 1783 goto tr_handle_get_descriptor; 1784 case UR_GET_CONFIG: 1785 goto tr_handle_get_config; 1786 case UR_GET_STATUS: 1787 goto tr_handle_get_status; 1788 default: 1789 goto tr_stalled; 1790 } 1791 break; 1792 1793 case UT_WRITE_DEVICE: 1794 switch (req->bRequest) { 1795 case UR_SET_ADDRESS: 1796 goto tr_handle_set_address; 1797 case UR_SET_CONFIG: 1798 goto tr_handle_set_config; 1799 case UR_CLEAR_FEATURE: 1800 goto tr_valid; /* nop */ 1801 case UR_SET_DESCRIPTOR: 1802 goto tr_valid; /* nop */ 1803 case UR_SET_FEATURE: 1804 default: 1805 goto tr_stalled; 1806 } 1807 break; 1808 1809 case UT_WRITE_ENDPOINT: 1810 switch (req->bRequest) { 1811 case UR_CLEAR_FEATURE: 1812 switch (UGETW(req->wValue)) { 1813 case UF_ENDPOINT_HALT: 1814 goto tr_handle_clear_halt; 1815 case UF_DEVICE_REMOTE_WAKEUP: 1816 goto tr_handle_clear_wakeup; 1817 default: 1818 goto tr_stalled; 1819 } 1820 break; 1821 case UR_SET_FEATURE: 1822 switch (UGETW(req->wValue)) { 1823 case UF_ENDPOINT_HALT: 1824 goto tr_handle_set_halt; 1825 case UF_DEVICE_REMOTE_WAKEUP: 1826 goto tr_handle_set_wakeup; 1827 default: 1828 goto tr_stalled; 1829 } 1830 break; 1831 case UR_SYNCH_FRAME: 1832 goto tr_valid; /* nop */ 1833 default: 1834 goto tr_stalled; 1835 } 1836 break; 1837 1838 case UT_READ_ENDPOINT: 1839 switch (req->bRequest) { 1840 case UR_GET_STATUS: 1841 goto tr_handle_get_ep_status; 1842 default: 1843 goto tr_stalled; 1844 } 1845 break; 1846 1847 case UT_WRITE_INTERFACE: 1848 switch (req->bRequest) { 1849 case UR_SET_INTERFACE: 1850 goto tr_handle_set_interface; 1851 case UR_CLEAR_FEATURE: 1852 goto tr_valid; /* nop */ 1853 case UR_SET_FEATURE: 1854 default: 1855 goto tr_stalled; 1856 } 1857 break; 1858 1859 case UT_READ_INTERFACE: 1860 switch (req->bRequest) { 1861 case UR_GET_INTERFACE: 1862 goto tr_handle_get_interface; 1863 case UR_GET_STATUS: 1864 goto tr_handle_get_iface_status; 1865 default: 1866 goto tr_stalled; 1867 } 1868 break; 1869 1870 case UT_WRITE_CLASS_INTERFACE: 1871 case UT_WRITE_VENDOR_INTERFACE: 1872 /* XXX forward */ 1873 break; 1874 1875 case UT_READ_CLASS_INTERFACE: 1876 case UT_READ_VENDOR_INTERFACE: 1877 /* XXX forward */ 1878 break; 1879 1880 case UT_WRITE_CLASS_DEVICE: 1881 switch (req->bRequest) { 1882 case UR_CLEAR_FEATURE: 1883 goto tr_valid; 1884 case UR_SET_DESCRIPTOR: 1885 case UR_SET_FEATURE: 1886 break; 1887 default: 1888 goto tr_stalled; 1889 } 1890 break; 1891 1892 case UT_WRITE_CLASS_OTHER: 1893 switch (req->bRequest) { 1894 case UR_CLEAR_FEATURE: 1895 goto tr_handle_clear_port_feature; 1896 case UR_SET_FEATURE: 1897 goto tr_handle_set_port_feature; 1898 case UR_CLEAR_TT_BUFFER: 1899 case UR_RESET_TT: 1900 case UR_STOP_TT: 1901 goto tr_valid; 1902 1903 default: 1904 goto tr_stalled; 1905 } 1906 break; 1907 1908 case UT_READ_CLASS_OTHER: 1909 switch (req->bRequest) { 1910 case UR_GET_TT_STATE: 1911 goto tr_handle_get_tt_state; 1912 case UR_GET_STATUS: 1913 goto tr_handle_get_port_status; 1914 default: 1915 goto tr_stalled; 1916 } 1917 break; 1918 1919 case UT_READ_CLASS_DEVICE: 1920 switch (req->bRequest) { 1921 case UR_GET_DESCRIPTOR: 1922 goto tr_handle_get_class_descriptor; 1923 case UR_GET_STATUS: 1924 goto tr_handle_get_class_status; 1925 1926 default: 1927 goto tr_stalled; 1928 } 1929 break; 1930 default: 1931 goto tr_stalled; 1932 } 1933 goto tr_valid; 1934 1935tr_handle_get_descriptor: 1936 switch (value >> 8) { 1937 case UDESC_DEVICE: 1938 if (value & 0xff) { 1939 goto tr_stalled; 1940 } 1941 len = sizeof(at91dci_devd); 1942 ptr = (const void *)&at91dci_devd; 1943 goto tr_valid; 1944 case UDESC_CONFIG: 1945 if (value & 0xff) { 1946 goto tr_stalled; 1947 } 1948 len = sizeof(at91dci_confd); 1949 ptr = (const void *)&at91dci_confd; 1950 goto tr_valid; 1951 case UDESC_STRING: 1952 switch (value & 0xff) { 1953 case 0: /* Language table */ 1954 len = sizeof(at91dci_langtab); 1955 ptr = (const void *)&at91dci_langtab; 1956 goto tr_valid; 1957 1958 case 1: /* Vendor */ 1959 len = sizeof(at91dci_vendor); 1960 ptr = (const void *)&at91dci_vendor; 1961 goto tr_valid; 1962 1963 case 2: /* Product */ 1964 len = sizeof(at91dci_product); 1965 ptr = (const void *)&at91dci_product; 1966 goto tr_valid; 1967 default: 1968 break; 1969 } 1970 break; 1971 default: 1972 goto tr_stalled; 1973 } 1974 goto tr_stalled; 1975 1976tr_handle_get_config: 1977 len = 1; 1978 sc->sc_hub_temp.wValue[0] = sc->sc_conf; 1979 goto tr_valid; 1980 1981tr_handle_get_status: 1982 len = 2; 1983 USETW(sc->sc_hub_temp.wValue, UDS_SELF_POWERED); 1984 goto tr_valid; 1985 1986tr_handle_set_address: 1987 if (value & 0xFF00) { 1988 goto tr_stalled; 1989 } 1990 sc->sc_rt_addr = value; 1991 goto tr_valid; 1992 1993tr_handle_set_config: 1994 if (value >= 2) { 1995 goto tr_stalled; 1996 } 1997 sc->sc_conf = value; 1998 goto tr_valid; 1999 2000tr_handle_get_interface: 2001 len = 1; 2002 sc->sc_hub_temp.wValue[0] = 0; 2003 goto tr_valid; 2004 2005tr_handle_get_tt_state: 2006tr_handle_get_class_status: 2007tr_handle_get_iface_status: 2008tr_handle_get_ep_status: 2009 len = 2; 2010 USETW(sc->sc_hub_temp.wValue, 0); 2011 goto tr_valid; 2012 2013tr_handle_set_halt: 2014tr_handle_set_interface: 2015tr_handle_set_wakeup: 2016tr_handle_clear_wakeup: 2017tr_handle_clear_halt: 2018 goto tr_valid; 2019 2020tr_handle_clear_port_feature: 2021 if (index != 1) { 2022 goto tr_stalled; 2023 } 2024 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE on port %d\n", index); 2025 2026 switch (value) { 2027 case UHF_PORT_SUSPEND: 2028 at91dci_wakeup_peer(sc); 2029 break; 2030 2031 case UHF_PORT_ENABLE: 2032 sc->sc_flags.port_enabled = 0; 2033 break; 2034 2035 case UHF_PORT_TEST: 2036 case UHF_PORT_INDICATOR: 2037 case UHF_C_PORT_ENABLE: 2038 case UHF_C_PORT_OVER_CURRENT: 2039 case UHF_C_PORT_RESET: 2040 /* nops */ 2041 break; 2042 case UHF_PORT_POWER: 2043 sc->sc_flags.port_powered = 0; 2044 at91dci_pull_down(sc); 2045 at91dci_clocks_off(sc); 2046 break; 2047 case UHF_C_PORT_CONNECTION: 2048 sc->sc_flags.change_connect = 0; 2049 break; 2050 case UHF_C_PORT_SUSPEND: 2051 sc->sc_flags.change_suspend = 0; 2052 break; 2053 default: 2054 err = USB_ERR_IOERROR; 2055 goto done; 2056 } 2057 goto tr_valid; 2058 2059tr_handle_set_port_feature: 2060 if (index != 1) { 2061 goto tr_stalled; 2062 } 2063 DPRINTFN(9, "UR_SET_PORT_FEATURE\n"); 2064 2065 switch (value) { 2066 case UHF_PORT_ENABLE: 2067 sc->sc_flags.port_enabled = 1; 2068 break; 2069 case UHF_PORT_SUSPEND: 2070 case UHF_PORT_RESET: 2071 case UHF_PORT_TEST: 2072 case UHF_PORT_INDICATOR: 2073 /* nops */ 2074 break; 2075 case UHF_PORT_POWER: 2076 sc->sc_flags.port_powered = 1; 2077 break; 2078 default: 2079 err = USB_ERR_IOERROR; 2080 goto done; 2081 } 2082 goto tr_valid; 2083 2084tr_handle_get_port_status: 2085 2086 DPRINTFN(9, "UR_GET_PORT_STATUS\n"); 2087 2088 if (index != 1) { 2089 goto tr_stalled; 2090 } 2091 if (sc->sc_flags.status_vbus) { 2092 at91dci_clocks_on(sc); 2093 at91dci_pull_up(sc); 2094 } else { 2095 at91dci_pull_down(sc); 2096 at91dci_clocks_off(sc); 2097 } 2098 2099 /* Select FULL-speed and Device Side Mode */ 2100 2101 value = UPS_PORT_MODE_DEVICE; 2102 2103 if (sc->sc_flags.port_powered) { 2104 value |= UPS_PORT_POWER; 2105 } 2106 if (sc->sc_flags.port_enabled) { 2107 value |= UPS_PORT_ENABLED; 2108 } 2109 if (sc->sc_flags.status_vbus && 2110 sc->sc_flags.status_bus_reset) { 2111 value |= UPS_CURRENT_CONNECT_STATUS; 2112 } 2113 if (sc->sc_flags.status_suspend) { 2114 value |= UPS_SUSPEND; 2115 } 2116 USETW(sc->sc_hub_temp.ps.wPortStatus, value); 2117 2118 value = 0; 2119 2120 if (sc->sc_flags.change_connect) { 2121 value |= UPS_C_CONNECT_STATUS; 2122 2123 if (sc->sc_flags.status_vbus && 2124 sc->sc_flags.status_bus_reset) { 2125 /* reset endpoint flags */ 2126 memset(sc->sc_ep_flags, 0, sizeof(sc->sc_ep_flags)); 2127 } 2128 } 2129 if (sc->sc_flags.change_suspend) { 2130 value |= UPS_C_SUSPEND; 2131 } 2132 USETW(sc->sc_hub_temp.ps.wPortChange, value); 2133 len = sizeof(sc->sc_hub_temp.ps); 2134 goto tr_valid; 2135 2136tr_handle_get_class_descriptor: 2137 if (value & 0xFF) { 2138 goto tr_stalled; 2139 } 2140 ptr = (const void *)&at91dci_hubd; 2141 len = sizeof(at91dci_hubd); 2142 goto tr_valid; 2143 2144tr_stalled: 2145 err = USB_ERR_STALLED; 2146tr_valid: 2147done: 2148 *plength = len; 2149 *pptr = ptr; 2150 return (err); 2151} 2152 2153static void 2154at91dci_xfer_setup(struct usb_setup_params *parm) 2155{ 2156 const struct usb_hw_ep_profile *pf; 2157 struct at91dci_softc *sc; 2158 struct usb_xfer *xfer; 2159 void *last_obj; 2160 uint32_t ntd; 2161 uint32_t n; 2162 uint8_t ep_no; 2163 2164 sc = AT9100_DCI_BUS2SC(parm->udev->bus); 2165 xfer = parm->curr_xfer; 2166 2167 /* 2168 * NOTE: This driver does not use any of the parameters that 2169 * are computed from the following values. Just set some 2170 * reasonable dummies: 2171 */ 2172 parm->hc_max_packet_size = 0x500; 2173 parm->hc_max_packet_count = 1; 2174 parm->hc_max_frame_size = 0x500; 2175 2176 usbd_transfer_setup_sub(parm); 2177 2178 /* 2179 * compute maximum number of TDs 2180 */ 2181 if (parm->methods == &at91dci_device_ctrl_methods) { 2182 2183 ntd = xfer->nframes + 1 /* STATUS */ + 1 /* SYNC 1 */ 2184 + 1 /* SYNC 2 */ ; 2185 2186 } else if (parm->methods == &at91dci_device_bulk_methods) { 2187 2188 ntd = xfer->nframes + 1 /* SYNC */ ; 2189 2190 } else if (parm->methods == &at91dci_device_intr_methods) { 2191 2192 ntd = xfer->nframes + 1 /* SYNC */ ; 2193 2194 } else if (parm->methods == &at91dci_device_isoc_fs_methods) { 2195 2196 ntd = xfer->nframes + 1 /* SYNC */ ; 2197 2198 } else { 2199 2200 ntd = 0; 2201 } 2202 2203 /* 2204 * check if "usbd_transfer_setup_sub" set an error 2205 */ 2206 if (parm->err) { 2207 return; 2208 } 2209 /* 2210 * allocate transfer descriptors 2211 */ 2212 last_obj = NULL; 2213 2214 /* 2215 * get profile stuff 2216 */ 2217 if (ntd) { 2218 2219 ep_no = xfer->endpointno & UE_ADDR; 2220 at91dci_get_hw_ep_profile(parm->udev, &pf, ep_no); 2221 2222 if (pf == NULL) { 2223 /* should not happen */ 2224 parm->err = USB_ERR_INVAL; 2225 return; 2226 } 2227 } else { 2228 ep_no = 0; 2229 pf = NULL; 2230 } 2231 2232 /* align data */ 2233 parm->size[0] += ((-parm->size[0]) & (USB_HOST_ALIGN - 1)); 2234 2235 for (n = 0; n != ntd; n++) { 2236 2237 struct at91dci_td *td; 2238 2239 if (parm->buf) { 2240 2241 td = USB_ADD_BYTES(parm->buf, parm->size[0]); 2242 2243 /* init TD */ 2244 td->io_tag = sc->sc_io_tag; 2245 td->io_hdl = sc->sc_io_hdl; 2246 td->max_packet_size = xfer->max_packet_size; 2247 td->status_reg = AT91_UDP_CSR(ep_no); 2248 td->fifo_reg = AT91_UDP_FDR(ep_no); 2249 if (pf->support_multi_buffer) { 2250 td->support_multi_buffer = 1; 2251 } 2252 td->obj_next = last_obj; 2253 2254 last_obj = td; 2255 } 2256 parm->size[0] += sizeof(*td); 2257 } 2258 2259 xfer->td_start[0] = last_obj; 2260} 2261 2262static void 2263at91dci_xfer_unsetup(struct usb_xfer *xfer) 2264{ 2265 return; 2266} 2267 2268static void 2269at91dci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc, 2270 struct usb_endpoint *ep) 2271{ 2272 struct at91dci_softc *sc = AT9100_DCI_BUS2SC(udev->bus); 2273 2274 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d (%d)\n", 2275 ep, udev->address, 2276 edesc->bEndpointAddress, udev->flags.usb_mode, 2277 sc->sc_rt_addr); 2278 2279 if (udev->device_index != sc->sc_rt_addr) { 2280 2281 if (udev->flags.usb_mode != USB_MODE_DEVICE) { 2282 /* not supported */ 2283 return; 2284 } 2285 if (udev->speed != USB_SPEED_FULL) { 2286 /* not supported */ 2287 return; 2288 } 2289 switch (edesc->bmAttributes & UE_XFERTYPE) { 2290 case UE_CONTROL: 2291 ep->methods = &at91dci_device_ctrl_methods; 2292 break; 2293 case UE_INTERRUPT: 2294 ep->methods = &at91dci_device_intr_methods; 2295 break; 2296 case UE_ISOCHRONOUS: 2297 ep->methods = &at91dci_device_isoc_fs_methods; 2298 break; 2299 case UE_BULK: 2300 ep->methods = &at91dci_device_bulk_methods; 2301 break; 2302 default: 2303 /* do nothing */ 2304 break; 2305 } 2306 } 2307} 2308 2309struct usb_bus_methods at91dci_bus_methods = 2310{ 2311 .endpoint_init = &at91dci_ep_init, 2312 .xfer_setup = &at91dci_xfer_setup, 2313 .xfer_unsetup = &at91dci_xfer_unsetup, 2314 .get_hw_ep_profile = &at91dci_get_hw_ep_profile, 2315 .set_stall = &at91dci_set_stall, 2316 .clear_stall = &at91dci_clear_stall, 2317 .roothub_exec = &at91dci_roothub_exec, 2318 .xfer_poll = &at91dci_do_poll, 2319}; 2320