at91dci.c revision 190738
1#include <sys/cdefs.h> 2__FBSDID("$FreeBSD: head/sys/dev/usb/controller/at91dci.c 190738 2009-04-05 18:21:21Z thompsa $"); 3 4/*- 5 * Copyright (c) 2007-2008 Hans Petter Selasky. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29/* 30 * This file contains the driver for the AT91 series USB Device 31 * Controller 32 */ 33 34/* 35 * Thanks to "David Brownell" for helping out regarding the hardware 36 * endpoint profiles. 37 */ 38 39/* 40 * NOTE: The "fifo_bank" is not reset in hardware when the endpoint is 41 * reset ! 42 * 43 * NOTE: When the chip detects BUS-reset it will also reset the 44 * endpoints, Function-address and more. 45 */ 46 47#include <dev/usb/usb.h> 48#include <dev/usb/usb_mfunc.h> 49#include <dev/usb/usb_error.h> 50 51#define USB_DEBUG_VAR at91dcidebug 52 53#include <dev/usb/usb_core.h> 54#include <dev/usb/usb_debug.h> 55#include <dev/usb/usb_busdma.h> 56#include <dev/usb/usb_process.h> 57#include <dev/usb/usb_sw_transfer.h> 58#include <dev/usb/usb_transfer.h> 59#include <dev/usb/usb_device.h> 60#include <dev/usb/usb_hub.h> 61#include <dev/usb/usb_util.h> 62 63#include <dev/usb/usb_controller.h> 64#include <dev/usb/usb_bus.h> 65#include <dev/usb/controller/at91dci.h> 66 67#define AT9100_DCI_BUS2SC(bus) \ 68 ((struct at91dci_softc *)(((uint8_t *)(bus)) - \ 69 ((uint8_t *)&(((struct at91dci_softc *)0)->sc_bus)))) 70 71#define AT9100_DCI_PC2SC(pc) \ 72 AT9100_DCI_BUS2SC(USB_DMATAG_TO_XROOT((pc)->tag_parent)->bus) 73 74#if USB_DEBUG 75static int at91dcidebug = 0; 76 77SYSCTL_NODE(_hw_usb2, OID_AUTO, at91dci, CTLFLAG_RW, 0, "USB at91dci"); 78SYSCTL_INT(_hw_usb2_at91dci, OID_AUTO, debug, CTLFLAG_RW, 79 &at91dcidebug, 0, "at91dci debug level"); 80#endif 81 82#define AT9100_DCI_INTR_ENDPT 1 83 84/* prototypes */ 85 86struct usb2_bus_methods at91dci_bus_methods; 87struct usb2_pipe_methods at91dci_device_bulk_methods; 88struct usb2_pipe_methods at91dci_device_ctrl_methods; 89struct usb2_pipe_methods at91dci_device_intr_methods; 90struct usb2_pipe_methods at91dci_device_isoc_fs_methods; 91 92static at91dci_cmd_t at91dci_setup_rx; 93static at91dci_cmd_t at91dci_data_rx; 94static at91dci_cmd_t at91dci_data_tx; 95static at91dci_cmd_t at91dci_data_tx_sync; 96static void at91dci_device_done(struct usb2_xfer *, usb2_error_t); 97static void at91dci_do_poll(struct usb2_bus *); 98static void at91dci_standard_done(struct usb2_xfer *); 99static void at91dci_root_intr(struct at91dci_softc *sc); 100 101/* 102 * NOTE: Some of the bits in the CSR register have inverse meaning so 103 * we need a helper macro when acknowledging events: 104 */ 105#define AT91_CSR_ACK(csr, what) do { \ 106 (csr) &= ~((AT91_UDP_CSR_FORCESTALL| \ 107 AT91_UDP_CSR_TXPKTRDY| \ 108 AT91_UDP_CSR_RXBYTECNT) ^ (what));\ 109 (csr) |= ((AT91_UDP_CSR_RX_DATA_BK0| \ 110 AT91_UDP_CSR_RX_DATA_BK1| \ 111 AT91_UDP_CSR_TXCOMP| \ 112 AT91_UDP_CSR_RXSETUP| \ 113 AT91_UDP_CSR_STALLSENT) ^ (what)); \ 114} while (0) 115 116/* 117 * Here is a list of what the chip supports. 118 * Probably it supports more than listed here! 119 */ 120static const struct usb2_hw_ep_profile 121 at91dci_ep_profile[AT91_UDP_EP_MAX] = { 122 123 [0] = { 124 .max_in_frame_size = 8, 125 .max_out_frame_size = 8, 126 .is_simplex = 1, 127 .support_control = 1, 128 }, 129 [1] = { 130 .max_in_frame_size = 64, 131 .max_out_frame_size = 64, 132 .is_simplex = 1, 133 .support_multi_buffer = 1, 134 .support_bulk = 1, 135 .support_interrupt = 1, 136 .support_isochronous = 1, 137 .support_in = 1, 138 .support_out = 1, 139 }, 140 [2] = { 141 .max_in_frame_size = 64, 142 .max_out_frame_size = 64, 143 .is_simplex = 1, 144 .support_multi_buffer = 1, 145 .support_bulk = 1, 146 .support_interrupt = 1, 147 .support_isochronous = 1, 148 .support_in = 1, 149 .support_out = 1, 150 }, 151 [3] = { 152 /* can also do BULK */ 153 .max_in_frame_size = 8, 154 .max_out_frame_size = 8, 155 .is_simplex = 1, 156 .support_interrupt = 1, 157 .support_in = 1, 158 .support_out = 1, 159 }, 160 [4] = { 161 .max_in_frame_size = 256, 162 .max_out_frame_size = 256, 163 .is_simplex = 1, 164 .support_multi_buffer = 1, 165 .support_bulk = 1, 166 .support_interrupt = 1, 167 .support_isochronous = 1, 168 .support_in = 1, 169 .support_out = 1, 170 }, 171 [5] = { 172 .max_in_frame_size = 256, 173 .max_out_frame_size = 256, 174 .is_simplex = 1, 175 .support_multi_buffer = 1, 176 .support_bulk = 1, 177 .support_interrupt = 1, 178 .support_isochronous = 1, 179 .support_in = 1, 180 .support_out = 1, 181 }, 182}; 183 184static void 185at91dci_get_hw_ep_profile(struct usb2_device *udev, 186 const struct usb2_hw_ep_profile **ppf, uint8_t ep_addr) 187{ 188 if (ep_addr < AT91_UDP_EP_MAX) { 189 *ppf = (at91dci_ep_profile + ep_addr); 190 } else { 191 *ppf = NULL; 192 } 193} 194 195static void 196at91dci_clocks_on(struct at91dci_softc *sc) 197{ 198 if (sc->sc_flags.clocks_off && 199 sc->sc_flags.port_powered) { 200 201 DPRINTFN(5, "\n"); 202 203 if (sc->sc_clocks_on) { 204 (sc->sc_clocks_on) (sc->sc_clocks_arg); 205 } 206 sc->sc_flags.clocks_off = 0; 207 208 /* enable Transceiver */ 209 AT91_UDP_WRITE_4(sc, AT91_UDP_TXVC, 0); 210 } 211} 212 213static void 214at91dci_clocks_off(struct at91dci_softc *sc) 215{ 216 if (!sc->sc_flags.clocks_off) { 217 218 DPRINTFN(5, "\n"); 219 220 /* disable Transceiver */ 221 AT91_UDP_WRITE_4(sc, AT91_UDP_TXVC, AT91_UDP_TXVC_DIS); 222 223 if (sc->sc_clocks_off) { 224 (sc->sc_clocks_off) (sc->sc_clocks_arg); 225 } 226 sc->sc_flags.clocks_off = 1; 227 } 228} 229 230static void 231at91dci_pull_up(struct at91dci_softc *sc) 232{ 233 /* pullup D+, if possible */ 234 235 if (!sc->sc_flags.d_pulled_up && 236 sc->sc_flags.port_powered) { 237 sc->sc_flags.d_pulled_up = 1; 238 (sc->sc_pull_up) (sc->sc_pull_arg); 239 } 240} 241 242static void 243at91dci_pull_down(struct at91dci_softc *sc) 244{ 245 /* pulldown D+, if possible */ 246 247 if (sc->sc_flags.d_pulled_up) { 248 sc->sc_flags.d_pulled_up = 0; 249 (sc->sc_pull_down) (sc->sc_pull_arg); 250 } 251} 252 253static void 254at91dci_wakeup_peer(struct at91dci_softc *sc) 255{ 256 if (!(sc->sc_flags.status_suspend)) { 257 return; 258 } 259 260 AT91_UDP_WRITE_4(sc, AT91_UDP_GSTATE, AT91_UDP_GSTATE_ESR); 261 262 /* wait 8 milliseconds */ 263 /* Wait for reset to complete. */ 264 usb2_pause_mtx(&sc->sc_bus.bus_mtx, hz / 125); 265 266 AT91_UDP_WRITE_4(sc, AT91_UDP_GSTATE, 0); 267} 268 269static void 270at91dci_set_address(struct at91dci_softc *sc, uint8_t addr) 271{ 272 DPRINTFN(5, "addr=%d\n", addr); 273 274 AT91_UDP_WRITE_4(sc, AT91_UDP_FADDR, addr | 275 AT91_UDP_FADDR_EN); 276} 277 278static uint8_t 279at91dci_setup_rx(struct at91dci_td *td) 280{ 281 struct at91dci_softc *sc; 282 struct usb2_device_request req; 283 uint32_t csr; 284 uint32_t temp; 285 uint16_t count; 286 287 /* read out FIFO status */ 288 csr = bus_space_read_4(td->io_tag, td->io_hdl, 289 td->status_reg); 290 291 DPRINTFN(5, "csr=0x%08x rem=%u\n", csr, td->remainder); 292 293 temp = csr; 294 temp &= (AT91_UDP_CSR_RX_DATA_BK0 | 295 AT91_UDP_CSR_RX_DATA_BK1 | 296 AT91_UDP_CSR_STALLSENT | 297 AT91_UDP_CSR_RXSETUP | 298 AT91_UDP_CSR_TXCOMP); 299 300 if (!(csr & AT91_UDP_CSR_RXSETUP)) { 301 goto not_complete; 302 } 303 /* clear did stall */ 304 td->did_stall = 0; 305 306 /* get the packet byte count */ 307 count = (csr & AT91_UDP_CSR_RXBYTECNT) >> 16; 308 309 /* verify data length */ 310 if (count != td->remainder) { 311 DPRINTFN(0, "Invalid SETUP packet " 312 "length, %d bytes\n", count); 313 goto not_complete; 314 } 315 if (count != sizeof(req)) { 316 DPRINTFN(0, "Unsupported SETUP packet " 317 "length, %d bytes\n", count); 318 goto not_complete; 319 } 320 /* receive data */ 321 bus_space_read_multi_1(td->io_tag, td->io_hdl, 322 td->fifo_reg, (void *)&req, sizeof(req)); 323 324 /* copy data into real buffer */ 325 usb2_copy_in(td->pc, 0, &req, sizeof(req)); 326 327 td->offset = sizeof(req); 328 td->remainder = 0; 329 330 /* get pointer to softc */ 331 sc = AT9100_DCI_PC2SC(td->pc); 332 333 /* sneak peek the set address */ 334 if ((req.bmRequestType == UT_WRITE_DEVICE) && 335 (req.bRequest == UR_SET_ADDRESS)) { 336 sc->sc_dv_addr = req.wValue[0] & 0x7F; 337 } else { 338 sc->sc_dv_addr = 0xFF; 339 } 340 341 /* sneak peek the endpoint direction */ 342 if (req.bmRequestType & UE_DIR_IN) { 343 csr |= AT91_UDP_CSR_DIR; 344 } else { 345 csr &= ~AT91_UDP_CSR_DIR; 346 } 347 348 /* write the direction of the control transfer */ 349 AT91_CSR_ACK(csr, temp); 350 bus_space_write_4(td->io_tag, td->io_hdl, 351 td->status_reg, csr); 352 return (0); /* complete */ 353 354not_complete: 355 /* abort any ongoing transfer */ 356 if (!td->did_stall) { 357 DPRINTFN(5, "stalling\n"); 358 temp |= AT91_UDP_CSR_FORCESTALL; 359 td->did_stall = 1; 360 } 361 362 /* clear interrupts, if any */ 363 if (temp) { 364 DPRINTFN(5, "clearing 0x%08x\n", temp); 365 AT91_CSR_ACK(csr, temp); 366 bus_space_write_4(td->io_tag, td->io_hdl, 367 td->status_reg, csr); 368 } 369 return (1); /* not complete */ 370 371} 372 373static uint8_t 374at91dci_data_rx(struct at91dci_td *td) 375{ 376 struct usb2_page_search buf_res; 377 uint32_t csr; 378 uint32_t temp; 379 uint16_t count; 380 uint8_t to; 381 uint8_t got_short; 382 383 to = 2; /* don't loop forever! */ 384 got_short = 0; 385 386 /* check if any of the FIFO banks have data */ 387repeat: 388 /* read out FIFO status */ 389 csr = bus_space_read_4(td->io_tag, td->io_hdl, 390 td->status_reg); 391 392 DPRINTFN(5, "csr=0x%08x rem=%u\n", csr, td->remainder); 393 394 if (csr & AT91_UDP_CSR_RXSETUP) { 395 if (td->remainder == 0) { 396 /* 397 * We are actually complete and have 398 * received the next SETUP 399 */ 400 DPRINTFN(5, "faking complete\n"); 401 return (0); /* complete */ 402 } 403 /* 404 * USB Host Aborted the transfer. 405 */ 406 td->error = 1; 407 return (0); /* complete */ 408 } 409 /* Make sure that "STALLSENT" gets cleared */ 410 temp = csr; 411 temp &= AT91_UDP_CSR_STALLSENT; 412 413 /* check status */ 414 if (!(csr & (AT91_UDP_CSR_RX_DATA_BK0 | 415 AT91_UDP_CSR_RX_DATA_BK1))) { 416 if (temp) { 417 /* write command */ 418 AT91_CSR_ACK(csr, temp); 419 bus_space_write_4(td->io_tag, td->io_hdl, 420 td->status_reg, csr); 421 } 422 return (1); /* not complete */ 423 } 424 /* get the packet byte count */ 425 count = (csr & AT91_UDP_CSR_RXBYTECNT) >> 16; 426 427 /* verify the packet byte count */ 428 if (count != td->max_packet_size) { 429 if (count < td->max_packet_size) { 430 /* we have a short packet */ 431 td->short_pkt = 1; 432 got_short = 1; 433 } else { 434 /* invalid USB packet */ 435 td->error = 1; 436 return (0); /* we are complete */ 437 } 438 } 439 /* verify the packet byte count */ 440 if (count > td->remainder) { 441 /* invalid USB packet */ 442 td->error = 1; 443 return (0); /* we are complete */ 444 } 445 while (count > 0) { 446 usb2_get_page(td->pc, td->offset, &buf_res); 447 448 /* get correct length */ 449 if (buf_res.length > count) { 450 buf_res.length = count; 451 } 452 /* receive data */ 453 bus_space_read_multi_1(td->io_tag, td->io_hdl, 454 td->fifo_reg, buf_res.buffer, buf_res.length); 455 456 /* update counters */ 457 count -= buf_res.length; 458 td->offset += buf_res.length; 459 td->remainder -= buf_res.length; 460 } 461 462 /* clear status bits */ 463 if (td->support_multi_buffer) { 464 if (td->fifo_bank) { 465 td->fifo_bank = 0; 466 temp |= AT91_UDP_CSR_RX_DATA_BK1; 467 } else { 468 td->fifo_bank = 1; 469 temp |= AT91_UDP_CSR_RX_DATA_BK0; 470 } 471 } else { 472 temp |= (AT91_UDP_CSR_RX_DATA_BK0 | 473 AT91_UDP_CSR_RX_DATA_BK1); 474 } 475 476 /* write command */ 477 AT91_CSR_ACK(csr, temp); 478 bus_space_write_4(td->io_tag, td->io_hdl, 479 td->status_reg, csr); 480 481 /* 482 * NOTE: We may have to delay a little bit before 483 * proceeding after clearing the DATA_BK bits. 484 */ 485 486 /* check if we are complete */ 487 if ((td->remainder == 0) || got_short) { 488 if (td->short_pkt) { 489 /* we are complete */ 490 return (0); 491 } 492 /* else need to receive a zero length packet */ 493 } 494 if (--to) { 495 goto repeat; 496 } 497 return (1); /* not complete */ 498} 499 500static uint8_t 501at91dci_data_tx(struct at91dci_td *td) 502{ 503 struct usb2_page_search buf_res; 504 uint32_t csr; 505 uint32_t temp; 506 uint16_t count; 507 uint8_t to; 508 509 to = 2; /* don't loop forever! */ 510 511repeat: 512 513 /* read out FIFO status */ 514 csr = bus_space_read_4(td->io_tag, td->io_hdl, 515 td->status_reg); 516 517 DPRINTFN(5, "csr=0x%08x rem=%u\n", csr, td->remainder); 518 519 if (csr & AT91_UDP_CSR_RXSETUP) { 520 /* 521 * The current transfer was aborted 522 * by the USB Host 523 */ 524 td->error = 1; 525 return (0); /* complete */ 526 } 527 /* Make sure that "STALLSENT" gets cleared */ 528 temp = csr; 529 temp &= AT91_UDP_CSR_STALLSENT; 530 531 if (csr & AT91_UDP_CSR_TXPKTRDY) { 532 if (temp) { 533 /* write command */ 534 AT91_CSR_ACK(csr, temp); 535 bus_space_write_4(td->io_tag, td->io_hdl, 536 td->status_reg, csr); 537 } 538 return (1); /* not complete */ 539 } else { 540 /* clear TXCOMP and set TXPKTRDY */ 541 temp |= (AT91_UDP_CSR_TXCOMP | 542 AT91_UDP_CSR_TXPKTRDY); 543 } 544 545 count = td->max_packet_size; 546 if (td->remainder < count) { 547 /* we have a short packet */ 548 td->short_pkt = 1; 549 count = td->remainder; 550 } 551 while (count > 0) { 552 553 usb2_get_page(td->pc, td->offset, &buf_res); 554 555 /* get correct length */ 556 if (buf_res.length > count) { 557 buf_res.length = count; 558 } 559 /* transmit data */ 560 bus_space_write_multi_1(td->io_tag, td->io_hdl, 561 td->fifo_reg, buf_res.buffer, buf_res.length); 562 563 /* update counters */ 564 count -= buf_res.length; 565 td->offset += buf_res.length; 566 td->remainder -= buf_res.length; 567 } 568 569 /* write command */ 570 AT91_CSR_ACK(csr, temp); 571 bus_space_write_4(td->io_tag, td->io_hdl, 572 td->status_reg, csr); 573 574 /* check remainder */ 575 if (td->remainder == 0) { 576 if (td->short_pkt) { 577 return (0); /* complete */ 578 } 579 /* else we need to transmit a short packet */ 580 } 581 if (--to) { 582 goto repeat; 583 } 584 return (1); /* not complete */ 585} 586 587static uint8_t 588at91dci_data_tx_sync(struct at91dci_td *td) 589{ 590 struct at91dci_softc *sc; 591 uint32_t csr; 592 uint32_t temp; 593 594#if 0 595repeat: 596#endif 597 598 /* read out FIFO status */ 599 csr = bus_space_read_4(td->io_tag, td->io_hdl, 600 td->status_reg); 601 602 DPRINTFN(5, "csr=0x%08x\n", csr); 603 604 if (csr & AT91_UDP_CSR_RXSETUP) { 605 DPRINTFN(5, "faking complete\n"); 606 /* Race condition */ 607 return (0); /* complete */ 608 } 609 temp = csr; 610 temp &= (AT91_UDP_CSR_STALLSENT | 611 AT91_UDP_CSR_TXCOMP); 612 613 /* check status */ 614 if (csr & AT91_UDP_CSR_TXPKTRDY) { 615 goto not_complete; 616 } 617 if (!(csr & AT91_UDP_CSR_TXCOMP)) { 618 goto not_complete; 619 } 620 sc = AT9100_DCI_PC2SC(td->pc); 621 if (sc->sc_dv_addr != 0xFF) { 622 /* 623 * The AT91 has a special requirement with regard to 624 * setting the address and that is to write the new 625 * address before clearing TXCOMP: 626 */ 627 at91dci_set_address(sc, sc->sc_dv_addr); 628 } 629 /* write command */ 630 AT91_CSR_ACK(csr, temp); 631 bus_space_write_4(td->io_tag, td->io_hdl, 632 td->status_reg, csr); 633 634 return (0); /* complete */ 635 636not_complete: 637 if (temp) { 638 /* write command */ 639 AT91_CSR_ACK(csr, temp); 640 bus_space_write_4(td->io_tag, td->io_hdl, 641 td->status_reg, csr); 642 } 643 return (1); /* not complete */ 644} 645 646static uint8_t 647at91dci_xfer_do_fifo(struct usb2_xfer *xfer) 648{ 649 struct at91dci_softc *sc; 650 struct at91dci_td *td; 651 uint8_t temp; 652 653 DPRINTFN(9, "\n"); 654 655 td = xfer->td_transfer_cache; 656 while (1) { 657 if ((td->func) (td)) { 658 /* operation in progress */ 659 break; 660 } 661 if (((void *)td) == xfer->td_transfer_last) { 662 goto done; 663 } 664 if (td->error) { 665 goto done; 666 } else if (td->remainder > 0) { 667 /* 668 * We had a short transfer. If there is no alternate 669 * next, stop processing ! 670 */ 671 if (!td->alt_next) { 672 goto done; 673 } 674 } 675 /* 676 * Fetch the next transfer descriptor and transfer 677 * some flags to the next transfer descriptor 678 */ 679 temp = 0; 680 if (td->fifo_bank) 681 temp |= 1; 682 td = td->obj_next; 683 xfer->td_transfer_cache = td; 684 if (temp & 1) 685 td->fifo_bank = 1; 686 } 687 return (1); /* not complete */ 688 689done: 690 sc = AT9100_DCI_BUS2SC(xfer->xroot->bus); 691 temp = (xfer->endpoint & UE_ADDR); 692 693 /* update FIFO bank flag and multi buffer */ 694 if (td->fifo_bank) { 695 sc->sc_ep_flags[temp].fifo_bank = 1; 696 } else { 697 sc->sc_ep_flags[temp].fifo_bank = 0; 698 } 699 700 /* compute all actual lengths */ 701 702 at91dci_standard_done(xfer); 703 704 return (0); /* complete */ 705} 706 707static void 708at91dci_interrupt_poll(struct at91dci_softc *sc) 709{ 710 struct usb2_xfer *xfer; 711 712repeat: 713 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 714 if (!at91dci_xfer_do_fifo(xfer)) { 715 /* queue has been modified */ 716 goto repeat; 717 } 718 } 719} 720 721void 722at91dci_vbus_interrupt(struct at91dci_softc *sc, uint8_t is_on) 723{ 724 DPRINTFN(5, "vbus = %u\n", is_on); 725 726 USB_BUS_LOCK(&sc->sc_bus); 727 if (is_on) { 728 if (!sc->sc_flags.status_vbus) { 729 sc->sc_flags.status_vbus = 1; 730 731 /* complete root HUB interrupt endpoint */ 732 at91dci_root_intr(sc); 733 } 734 } else { 735 if (sc->sc_flags.status_vbus) { 736 sc->sc_flags.status_vbus = 0; 737 sc->sc_flags.status_bus_reset = 0; 738 sc->sc_flags.status_suspend = 0; 739 sc->sc_flags.change_suspend = 0; 740 sc->sc_flags.change_connect = 1; 741 742 /* complete root HUB interrupt endpoint */ 743 at91dci_root_intr(sc); 744 } 745 } 746 USB_BUS_UNLOCK(&sc->sc_bus); 747} 748 749void 750at91dci_interrupt(struct at91dci_softc *sc) 751{ 752 uint32_t status; 753 754 USB_BUS_LOCK(&sc->sc_bus); 755 756 status = AT91_UDP_READ_4(sc, AT91_UDP_ISR); 757 status &= AT91_UDP_INT_DEFAULT; 758 759 if (!status) { 760 USB_BUS_UNLOCK(&sc->sc_bus); 761 return; 762 } 763 /* acknowledge interrupts */ 764 765 AT91_UDP_WRITE_4(sc, AT91_UDP_ICR, status); 766 767 /* check for any bus state change interrupts */ 768 769 if (status & AT91_UDP_INT_BUS) { 770 771 DPRINTFN(5, "real bus interrupt 0x%08x\n", status); 772 773 if (status & AT91_UDP_INT_END_BR) { 774 775 /* set correct state */ 776 sc->sc_flags.status_bus_reset = 1; 777 sc->sc_flags.status_suspend = 0; 778 sc->sc_flags.change_suspend = 0; 779 sc->sc_flags.change_connect = 1; 780 781 /* disable resume interrupt */ 782 AT91_UDP_WRITE_4(sc, AT91_UDP_IDR, 783 AT91_UDP_INT_RXRSM); 784 /* enable suspend interrupt */ 785 AT91_UDP_WRITE_4(sc, AT91_UDP_IER, 786 AT91_UDP_INT_RXSUSP); 787 } 788 /* 789 * If RXRSM and RXSUSP is set at the same time we interpret 790 * that like RESUME. Resume is set when there is at least 3 791 * milliseconds of inactivity on the USB BUS. 792 */ 793 if (status & AT91_UDP_INT_RXRSM) { 794 if (sc->sc_flags.status_suspend) { 795 sc->sc_flags.status_suspend = 0; 796 sc->sc_flags.change_suspend = 1; 797 798 /* disable resume interrupt */ 799 AT91_UDP_WRITE_4(sc, AT91_UDP_IDR, 800 AT91_UDP_INT_RXRSM); 801 /* enable suspend interrupt */ 802 AT91_UDP_WRITE_4(sc, AT91_UDP_IER, 803 AT91_UDP_INT_RXSUSP); 804 } 805 } else if (status & AT91_UDP_INT_RXSUSP) { 806 if (!sc->sc_flags.status_suspend) { 807 sc->sc_flags.status_suspend = 1; 808 sc->sc_flags.change_suspend = 1; 809 810 /* disable suspend interrupt */ 811 AT91_UDP_WRITE_4(sc, AT91_UDP_IDR, 812 AT91_UDP_INT_RXSUSP); 813 814 /* enable resume interrupt */ 815 AT91_UDP_WRITE_4(sc, AT91_UDP_IER, 816 AT91_UDP_INT_RXRSM); 817 } 818 } 819 /* complete root HUB interrupt endpoint */ 820 at91dci_root_intr(sc); 821 } 822 /* check for any endpoint interrupts */ 823 824 if (status & AT91_UDP_INT_EPS) { 825 826 DPRINTFN(5, "real endpoint interrupt 0x%08x\n", status); 827 828 at91dci_interrupt_poll(sc); 829 } 830 USB_BUS_UNLOCK(&sc->sc_bus); 831} 832 833static void 834at91dci_setup_standard_chain_sub(struct at91dci_std_temp *temp) 835{ 836 struct at91dci_td *td; 837 838 /* get current Transfer Descriptor */ 839 td = temp->td_next; 840 temp->td = td; 841 842 /* prepare for next TD */ 843 temp->td_next = td->obj_next; 844 845 /* fill out the Transfer Descriptor */ 846 td->func = temp->func; 847 td->pc = temp->pc; 848 td->offset = temp->offset; 849 td->remainder = temp->len; 850 td->fifo_bank = 0; 851 td->error = 0; 852 td->did_stall = 0; 853 td->short_pkt = temp->short_pkt; 854 td->alt_next = temp->setup_alt_next; 855} 856 857static void 858at91dci_setup_standard_chain(struct usb2_xfer *xfer) 859{ 860 struct at91dci_std_temp temp; 861 struct at91dci_softc *sc; 862 struct at91dci_td *td; 863 uint32_t x; 864 uint8_t ep_no; 865 uint8_t need_sync; 866 867 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n", 868 xfer->address, UE_GET_ADDR(xfer->endpoint), 869 xfer->sumlen, usb2_get_speed(xfer->xroot->udev)); 870 871 temp.max_frame_size = xfer->max_frame_size; 872 873 td = xfer->td_start[0]; 874 xfer->td_transfer_first = td; 875 xfer->td_transfer_cache = td; 876 877 /* setup temp */ 878 879 temp.td = NULL; 880 temp.td_next = xfer->td_start[0]; 881 temp.offset = 0; 882 temp.setup_alt_next = xfer->flags_int.short_frames_ok; 883 884 sc = AT9100_DCI_BUS2SC(xfer->xroot->bus); 885 ep_no = (xfer->endpoint & UE_ADDR); 886 887 /* check if we should prepend a setup message */ 888 889 if (xfer->flags_int.control_xfr) { 890 if (xfer->flags_int.control_hdr) { 891 892 temp.func = &at91dci_setup_rx; 893 temp.len = xfer->frlengths[0]; 894 temp.pc = xfer->frbuffers + 0; 895 temp.short_pkt = temp.len ? 1 : 0; 896 /* check for last frame */ 897 if (xfer->nframes == 1) { 898 /* no STATUS stage yet, SETUP is last */ 899 if (xfer->flags_int.control_act) 900 temp.setup_alt_next = 0; 901 } 902 903 at91dci_setup_standard_chain_sub(&temp); 904 } 905 x = 1; 906 } else { 907 x = 0; 908 } 909 910 if (x != xfer->nframes) { 911 if (xfer->endpoint & UE_DIR_IN) { 912 temp.func = &at91dci_data_tx; 913 need_sync = 1; 914 } else { 915 temp.func = &at91dci_data_rx; 916 need_sync = 0; 917 } 918 919 /* setup "pc" pointer */ 920 temp.pc = xfer->frbuffers + x; 921 } else { 922 need_sync = 0; 923 } 924 while (x != xfer->nframes) { 925 926 /* DATA0 / DATA1 message */ 927 928 temp.len = xfer->frlengths[x]; 929 930 x++; 931 932 if (x == xfer->nframes) { 933 if (xfer->flags_int.control_xfr) { 934 if (xfer->flags_int.control_act) { 935 temp.setup_alt_next = 0; 936 } 937 } else { 938 temp.setup_alt_next = 0; 939 } 940 } 941 if (temp.len == 0) { 942 943 /* make sure that we send an USB packet */ 944 945 temp.short_pkt = 0; 946 947 } else { 948 949 /* regular data transfer */ 950 951 temp.short_pkt = (xfer->flags.force_short_xfer) ? 0 : 1; 952 } 953 954 at91dci_setup_standard_chain_sub(&temp); 955 956 if (xfer->flags_int.isochronous_xfr) { 957 temp.offset += temp.len; 958 } else { 959 /* get next Page Cache pointer */ 960 temp.pc = xfer->frbuffers + x; 961 } 962 } 963 964 /* check for control transfer */ 965 if (xfer->flags_int.control_xfr) { 966 967 /* always setup a valid "pc" pointer for status and sync */ 968 temp.pc = xfer->frbuffers + 0; 969 temp.len = 0; 970 temp.short_pkt = 0; 971 temp.setup_alt_next = 0; 972 973 /* check if we need to sync */ 974 if (need_sync) { 975 /* we need a SYNC point after TX */ 976 temp.func = &at91dci_data_tx_sync; 977 at91dci_setup_standard_chain_sub(&temp); 978 } 979 980 /* check if we should append a status stage */ 981 if (!xfer->flags_int.control_act) { 982 983 /* 984 * Send a DATA1 message and invert the current 985 * endpoint direction. 986 */ 987 if (xfer->endpoint & UE_DIR_IN) { 988 temp.func = &at91dci_data_rx; 989 need_sync = 0; 990 } else { 991 temp.func = &at91dci_data_tx; 992 need_sync = 1; 993 } 994 995 at91dci_setup_standard_chain_sub(&temp); 996 if (need_sync) { 997 /* we need a SYNC point after TX */ 998 temp.func = &at91dci_data_tx_sync; 999 at91dci_setup_standard_chain_sub(&temp); 1000 } 1001 } 1002 } 1003 1004 /* must have at least one frame! */ 1005 td = temp.td; 1006 xfer->td_transfer_last = td; 1007 1008 /* setup the correct fifo bank */ 1009 if (sc->sc_ep_flags[ep_no].fifo_bank) { 1010 td = xfer->td_transfer_first; 1011 td->fifo_bank = 1; 1012 } 1013} 1014 1015static void 1016at91dci_timeout(void *arg) 1017{ 1018 struct usb2_xfer *xfer = arg; 1019 1020 DPRINTF("xfer=%p\n", xfer); 1021 1022 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 1023 1024 /* transfer is transferred */ 1025 at91dci_device_done(xfer, USB_ERR_TIMEOUT); 1026} 1027 1028static void 1029at91dci_start_standard_chain(struct usb2_xfer *xfer) 1030{ 1031 DPRINTFN(9, "\n"); 1032 1033 /* poll one time */ 1034 if (at91dci_xfer_do_fifo(xfer)) { 1035 1036 struct at91dci_softc *sc = AT9100_DCI_BUS2SC(xfer->xroot->bus); 1037 uint8_t ep_no = xfer->endpoint & UE_ADDR; 1038 1039 /* 1040 * Only enable the endpoint interrupt when we are actually 1041 * waiting for data, hence we are dealing with level 1042 * triggered interrupts ! 1043 */ 1044 AT91_UDP_WRITE_4(sc, AT91_UDP_IER, AT91_UDP_INT_EP(ep_no)); 1045 1046 DPRINTFN(15, "enable interrupts on endpoint %d\n", ep_no); 1047 1048 /* put transfer on interrupt queue */ 1049 usb2_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 1050 1051 /* start timeout, if any */ 1052 if (xfer->timeout != 0) { 1053 usb2_transfer_timeout_ms(xfer, 1054 &at91dci_timeout, xfer->timeout); 1055 } 1056 } 1057} 1058 1059static void 1060at91dci_root_intr(struct at91dci_softc *sc) 1061{ 1062 DPRINTFN(9, "\n"); 1063 1064 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1065 1066 /* set port bit */ 1067 sc->sc_hub_idata[0] = 0x02; /* we only have one port */ 1068 1069 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, 1070 sizeof(sc->sc_hub_idata)); 1071} 1072 1073static usb2_error_t 1074at91dci_standard_done_sub(struct usb2_xfer *xfer) 1075{ 1076 struct at91dci_td *td; 1077 uint32_t len; 1078 uint8_t error; 1079 1080 DPRINTFN(9, "\n"); 1081 1082 td = xfer->td_transfer_cache; 1083 1084 do { 1085 len = td->remainder; 1086 1087 if (xfer->aframes != xfer->nframes) { 1088 /* 1089 * Verify the length and subtract 1090 * the remainder from "frlengths[]": 1091 */ 1092 if (len > xfer->frlengths[xfer->aframes]) { 1093 td->error = 1; 1094 } else { 1095 xfer->frlengths[xfer->aframes] -= len; 1096 } 1097 } 1098 /* Check for transfer error */ 1099 if (td->error) { 1100 /* the transfer is finished */ 1101 error = 1; 1102 td = NULL; 1103 break; 1104 } 1105 /* Check for short transfer */ 1106 if (len > 0) { 1107 if (xfer->flags_int.short_frames_ok) { 1108 /* follow alt next */ 1109 if (td->alt_next) { 1110 td = td->obj_next; 1111 } else { 1112 td = NULL; 1113 } 1114 } else { 1115 /* the transfer is finished */ 1116 td = NULL; 1117 } 1118 error = 0; 1119 break; 1120 } 1121 td = td->obj_next; 1122 1123 /* this USB frame is complete */ 1124 error = 0; 1125 break; 1126 1127 } while (0); 1128 1129 /* update transfer cache */ 1130 1131 xfer->td_transfer_cache = td; 1132 1133 return (error ? 1134 USB_ERR_STALLED : USB_ERR_NORMAL_COMPLETION); 1135} 1136 1137static void 1138at91dci_standard_done(struct usb2_xfer *xfer) 1139{ 1140 usb2_error_t err = 0; 1141 1142 DPRINTFN(13, "xfer=%p pipe=%p transfer done\n", 1143 xfer, xfer->pipe); 1144 1145 /* reset scanner */ 1146 1147 xfer->td_transfer_cache = xfer->td_transfer_first; 1148 1149 if (xfer->flags_int.control_xfr) { 1150 1151 if (xfer->flags_int.control_hdr) { 1152 1153 err = at91dci_standard_done_sub(xfer); 1154 } 1155 xfer->aframes = 1; 1156 1157 if (xfer->td_transfer_cache == NULL) { 1158 goto done; 1159 } 1160 } 1161 while (xfer->aframes != xfer->nframes) { 1162 1163 err = at91dci_standard_done_sub(xfer); 1164 xfer->aframes++; 1165 1166 if (xfer->td_transfer_cache == NULL) { 1167 goto done; 1168 } 1169 } 1170 1171 if (xfer->flags_int.control_xfr && 1172 !xfer->flags_int.control_act) { 1173 1174 err = at91dci_standard_done_sub(xfer); 1175 } 1176done: 1177 at91dci_device_done(xfer, err); 1178} 1179 1180/*------------------------------------------------------------------------* 1181 * at91dci_device_done 1182 * 1183 * NOTE: this function can be called more than one time on the 1184 * same USB transfer! 1185 *------------------------------------------------------------------------*/ 1186static void 1187at91dci_device_done(struct usb2_xfer *xfer, usb2_error_t error) 1188{ 1189 struct at91dci_softc *sc = AT9100_DCI_BUS2SC(xfer->xroot->bus); 1190 uint8_t ep_no; 1191 1192 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1193 1194 DPRINTFN(2, "xfer=%p, pipe=%p, error=%d\n", 1195 xfer, xfer->pipe, error); 1196 1197 if (xfer->flags_int.usb2_mode == USB_MODE_DEVICE) { 1198 ep_no = (xfer->endpoint & UE_ADDR); 1199 1200 /* disable endpoint interrupt */ 1201 AT91_UDP_WRITE_4(sc, AT91_UDP_IDR, AT91_UDP_INT_EP(ep_no)); 1202 1203 DPRINTFN(15, "disable interrupts on endpoint %d\n", ep_no); 1204 } 1205 /* dequeue transfer and start next transfer */ 1206 usb2_transfer_done(xfer, error); 1207} 1208 1209static void 1210at91dci_set_stall(struct usb2_device *udev, struct usb2_xfer *xfer, 1211 struct usb2_pipe *pipe) 1212{ 1213 struct at91dci_softc *sc; 1214 uint32_t csr_val; 1215 uint8_t csr_reg; 1216 1217 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 1218 1219 DPRINTFN(5, "pipe=%p\n", pipe); 1220 1221 if (xfer) { 1222 /* cancel any ongoing transfers */ 1223 at91dci_device_done(xfer, USB_ERR_STALLED); 1224 } 1225 /* set FORCESTALL */ 1226 sc = AT9100_DCI_BUS2SC(udev->bus); 1227 csr_reg = (pipe->edesc->bEndpointAddress & UE_ADDR); 1228 csr_reg = AT91_UDP_CSR(csr_reg); 1229 csr_val = AT91_UDP_READ_4(sc, csr_reg); 1230 AT91_CSR_ACK(csr_val, AT91_UDP_CSR_FORCESTALL); 1231 AT91_UDP_WRITE_4(sc, csr_reg, csr_val); 1232} 1233 1234static void 1235at91dci_clear_stall_sub(struct at91dci_softc *sc, uint8_t ep_no, 1236 uint8_t ep_type, uint8_t ep_dir) 1237{ 1238 const struct usb2_hw_ep_profile *pf; 1239 uint32_t csr_val; 1240 uint32_t temp; 1241 uint8_t csr_reg; 1242 uint8_t to; 1243 1244 if (ep_type == UE_CONTROL) { 1245 /* clearing stall is not needed */ 1246 return; 1247 } 1248 /* compute CSR register offset */ 1249 csr_reg = AT91_UDP_CSR(ep_no); 1250 1251 /* compute default CSR value */ 1252 csr_val = 0; 1253 AT91_CSR_ACK(csr_val, 0); 1254 1255 /* disable endpoint */ 1256 AT91_UDP_WRITE_4(sc, csr_reg, csr_val); 1257 1258 /* get endpoint profile */ 1259 at91dci_get_hw_ep_profile(NULL, &pf, ep_no); 1260 1261 /* reset FIFO */ 1262 AT91_UDP_WRITE_4(sc, AT91_UDP_RST, AT91_UDP_RST_EP(ep_no)); 1263 AT91_UDP_WRITE_4(sc, AT91_UDP_RST, 0); 1264 1265 /* 1266 * NOTE: One would assume that a FIFO reset would release the 1267 * FIFO banks aswell, but it doesn't! We have to do this 1268 * manually! 1269 */ 1270 1271 /* release FIFO banks, if any */ 1272 for (to = 0; to != 2; to++) { 1273 1274 /* get csr value */ 1275 csr_val = AT91_UDP_READ_4(sc, csr_reg); 1276 1277 if (csr_val & (AT91_UDP_CSR_RX_DATA_BK0 | 1278 AT91_UDP_CSR_RX_DATA_BK1)) { 1279 /* clear status bits */ 1280 if (pf->support_multi_buffer) { 1281 if (sc->sc_ep_flags[ep_no].fifo_bank) { 1282 sc->sc_ep_flags[ep_no].fifo_bank = 0; 1283 temp = AT91_UDP_CSR_RX_DATA_BK1; 1284 } else { 1285 sc->sc_ep_flags[ep_no].fifo_bank = 1; 1286 temp = AT91_UDP_CSR_RX_DATA_BK0; 1287 } 1288 } else { 1289 temp = (AT91_UDP_CSR_RX_DATA_BK0 | 1290 AT91_UDP_CSR_RX_DATA_BK1); 1291 } 1292 } else { 1293 temp = 0; 1294 } 1295 1296 /* clear FORCESTALL */ 1297 temp |= AT91_UDP_CSR_STALLSENT; 1298 1299 AT91_CSR_ACK(csr_val, temp); 1300 AT91_UDP_WRITE_4(sc, csr_reg, csr_val); 1301 } 1302 1303 /* compute default CSR value */ 1304 csr_val = 0; 1305 AT91_CSR_ACK(csr_val, 0); 1306 1307 /* enable endpoint */ 1308 csr_val &= ~AT91_UDP_CSR_ET_MASK; 1309 csr_val |= AT91_UDP_CSR_EPEDS; 1310 1311 if (ep_type == UE_CONTROL) { 1312 csr_val |= AT91_UDP_CSR_ET_CTRL; 1313 } else { 1314 if (ep_type == UE_BULK) { 1315 csr_val |= AT91_UDP_CSR_ET_BULK; 1316 } else if (ep_type == UE_INTERRUPT) { 1317 csr_val |= AT91_UDP_CSR_ET_INT; 1318 } else { 1319 csr_val |= AT91_UDP_CSR_ET_ISO; 1320 } 1321 if (ep_dir & UE_DIR_IN) { 1322 csr_val |= AT91_UDP_CSR_ET_DIR_IN; 1323 } 1324 } 1325 1326 /* enable endpoint */ 1327 AT91_UDP_WRITE_4(sc, AT91_UDP_CSR(ep_no), csr_val); 1328} 1329 1330static void 1331at91dci_clear_stall(struct usb2_device *udev, struct usb2_pipe *pipe) 1332{ 1333 struct at91dci_softc *sc; 1334 struct usb2_endpoint_descriptor *ed; 1335 1336 DPRINTFN(5, "pipe=%p\n", pipe); 1337 1338 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 1339 1340 /* check mode */ 1341 if (udev->flags.usb2_mode != USB_MODE_DEVICE) { 1342 /* not supported */ 1343 return; 1344 } 1345 /* get softc */ 1346 sc = AT9100_DCI_BUS2SC(udev->bus); 1347 1348 /* get endpoint descriptor */ 1349 ed = pipe->edesc; 1350 1351 /* reset endpoint */ 1352 at91dci_clear_stall_sub(sc, 1353 (ed->bEndpointAddress & UE_ADDR), 1354 (ed->bmAttributes & UE_XFERTYPE), 1355 (ed->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT))); 1356} 1357 1358usb2_error_t 1359at91dci_init(struct at91dci_softc *sc) 1360{ 1361 uint32_t csr_val; 1362 uint8_t n; 1363 1364 DPRINTF("start\n"); 1365 1366 /* set up the bus structure */ 1367 sc->sc_bus.usbrev = USB_REV_1_1; 1368 sc->sc_bus.methods = &at91dci_bus_methods; 1369 1370 USB_BUS_LOCK(&sc->sc_bus); 1371 1372 /* turn on clocks */ 1373 1374 if (sc->sc_clocks_on) { 1375 (sc->sc_clocks_on) (sc->sc_clocks_arg); 1376 } 1377 /* wait a little for things to stabilise */ 1378 usb2_pause_mtx(&sc->sc_bus.bus_mtx, hz / 1000); 1379 1380 /* disable and clear all interrupts */ 1381 1382 AT91_UDP_WRITE_4(sc, AT91_UDP_IDR, 0xFFFFFFFF); 1383 AT91_UDP_WRITE_4(sc, AT91_UDP_ICR, 0xFFFFFFFF); 1384 1385 /* compute default CSR value */ 1386 1387 csr_val = 0; 1388 AT91_CSR_ACK(csr_val, 0); 1389 1390 /* disable all endpoints */ 1391 1392 for (n = 0; n != AT91_UDP_EP_MAX; n++) { 1393 1394 /* disable endpoint */ 1395 AT91_UDP_WRITE_4(sc, AT91_UDP_CSR(n), csr_val); 1396 } 1397 1398 /* enable the control endpoint */ 1399 1400 AT91_CSR_ACK(csr_val, AT91_UDP_CSR_ET_CTRL | 1401 AT91_UDP_CSR_EPEDS); 1402 1403 /* write to FIFO control register */ 1404 1405 AT91_UDP_WRITE_4(sc, AT91_UDP_CSR(0), csr_val); 1406 1407 /* enable the interrupts we want */ 1408 1409 AT91_UDP_WRITE_4(sc, AT91_UDP_IER, AT91_UDP_INT_BUS); 1410 1411 /* turn off clocks */ 1412 1413 at91dci_clocks_off(sc); 1414 1415 USB_BUS_UNLOCK(&sc->sc_bus); 1416 1417 /* catch any lost interrupts */ 1418 1419 at91dci_do_poll(&sc->sc_bus); 1420 1421 return (0); /* success */ 1422} 1423 1424void 1425at91dci_uninit(struct at91dci_softc *sc) 1426{ 1427 USB_BUS_LOCK(&sc->sc_bus); 1428 1429 /* disable and clear all interrupts */ 1430 AT91_UDP_WRITE_4(sc, AT91_UDP_IDR, 0xFFFFFFFF); 1431 AT91_UDP_WRITE_4(sc, AT91_UDP_ICR, 0xFFFFFFFF); 1432 1433 sc->sc_flags.port_powered = 0; 1434 sc->sc_flags.status_vbus = 0; 1435 sc->sc_flags.status_bus_reset = 0; 1436 sc->sc_flags.status_suspend = 0; 1437 sc->sc_flags.change_suspend = 0; 1438 sc->sc_flags.change_connect = 1; 1439 1440 at91dci_pull_down(sc); 1441 at91dci_clocks_off(sc); 1442 USB_BUS_UNLOCK(&sc->sc_bus); 1443} 1444 1445void 1446at91dci_suspend(struct at91dci_softc *sc) 1447{ 1448 return; 1449} 1450 1451void 1452at91dci_resume(struct at91dci_softc *sc) 1453{ 1454 return; 1455} 1456 1457static void 1458at91dci_do_poll(struct usb2_bus *bus) 1459{ 1460 struct at91dci_softc *sc = AT9100_DCI_BUS2SC(bus); 1461 1462 USB_BUS_LOCK(&sc->sc_bus); 1463 at91dci_interrupt_poll(sc); 1464 USB_BUS_UNLOCK(&sc->sc_bus); 1465} 1466 1467/*------------------------------------------------------------------------* 1468 * at91dci bulk support 1469 *------------------------------------------------------------------------*/ 1470static void 1471at91dci_device_bulk_open(struct usb2_xfer *xfer) 1472{ 1473 return; 1474} 1475 1476static void 1477at91dci_device_bulk_close(struct usb2_xfer *xfer) 1478{ 1479 at91dci_device_done(xfer, USB_ERR_CANCELLED); 1480} 1481 1482static void 1483at91dci_device_bulk_enter(struct usb2_xfer *xfer) 1484{ 1485 return; 1486} 1487 1488static void 1489at91dci_device_bulk_start(struct usb2_xfer *xfer) 1490{ 1491 /* setup TDs */ 1492 at91dci_setup_standard_chain(xfer); 1493 at91dci_start_standard_chain(xfer); 1494} 1495 1496struct usb2_pipe_methods at91dci_device_bulk_methods = 1497{ 1498 .open = at91dci_device_bulk_open, 1499 .close = at91dci_device_bulk_close, 1500 .enter = at91dci_device_bulk_enter, 1501 .start = at91dci_device_bulk_start, 1502}; 1503 1504/*------------------------------------------------------------------------* 1505 * at91dci control support 1506 *------------------------------------------------------------------------*/ 1507static void 1508at91dci_device_ctrl_open(struct usb2_xfer *xfer) 1509{ 1510 return; 1511} 1512 1513static void 1514at91dci_device_ctrl_close(struct usb2_xfer *xfer) 1515{ 1516 at91dci_device_done(xfer, USB_ERR_CANCELLED); 1517} 1518 1519static void 1520at91dci_device_ctrl_enter(struct usb2_xfer *xfer) 1521{ 1522 return; 1523} 1524 1525static void 1526at91dci_device_ctrl_start(struct usb2_xfer *xfer) 1527{ 1528 /* setup TDs */ 1529 at91dci_setup_standard_chain(xfer); 1530 at91dci_start_standard_chain(xfer); 1531} 1532 1533struct usb2_pipe_methods at91dci_device_ctrl_methods = 1534{ 1535 .open = at91dci_device_ctrl_open, 1536 .close = at91dci_device_ctrl_close, 1537 .enter = at91dci_device_ctrl_enter, 1538 .start = at91dci_device_ctrl_start, 1539}; 1540 1541/*------------------------------------------------------------------------* 1542 * at91dci interrupt support 1543 *------------------------------------------------------------------------*/ 1544static void 1545at91dci_device_intr_open(struct usb2_xfer *xfer) 1546{ 1547 return; 1548} 1549 1550static void 1551at91dci_device_intr_close(struct usb2_xfer *xfer) 1552{ 1553 at91dci_device_done(xfer, USB_ERR_CANCELLED); 1554} 1555 1556static void 1557at91dci_device_intr_enter(struct usb2_xfer *xfer) 1558{ 1559 return; 1560} 1561 1562static void 1563at91dci_device_intr_start(struct usb2_xfer *xfer) 1564{ 1565 /* setup TDs */ 1566 at91dci_setup_standard_chain(xfer); 1567 at91dci_start_standard_chain(xfer); 1568} 1569 1570struct usb2_pipe_methods at91dci_device_intr_methods = 1571{ 1572 .open = at91dci_device_intr_open, 1573 .close = at91dci_device_intr_close, 1574 .enter = at91dci_device_intr_enter, 1575 .start = at91dci_device_intr_start, 1576}; 1577 1578/*------------------------------------------------------------------------* 1579 * at91dci full speed isochronous support 1580 *------------------------------------------------------------------------*/ 1581static void 1582at91dci_device_isoc_fs_open(struct usb2_xfer *xfer) 1583{ 1584 return; 1585} 1586 1587static void 1588at91dci_device_isoc_fs_close(struct usb2_xfer *xfer) 1589{ 1590 at91dci_device_done(xfer, USB_ERR_CANCELLED); 1591} 1592 1593static void 1594at91dci_device_isoc_fs_enter(struct usb2_xfer *xfer) 1595{ 1596 struct at91dci_softc *sc = AT9100_DCI_BUS2SC(xfer->xroot->bus); 1597 uint32_t temp; 1598 uint32_t nframes; 1599 1600 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n", 1601 xfer, xfer->pipe->isoc_next, xfer->nframes); 1602 1603 /* get the current frame index */ 1604 1605 nframes = AT91_UDP_READ_4(sc, AT91_UDP_FRM); 1606 1607 /* 1608 * check if the frame index is within the window where the frames 1609 * will be inserted 1610 */ 1611 temp = (nframes - xfer->pipe->isoc_next) & AT91_UDP_FRM_MASK; 1612 1613 if ((xfer->pipe->is_synced == 0) || 1614 (temp < xfer->nframes)) { 1615 /* 1616 * If there is data underflow or the pipe queue is 1617 * empty we schedule the transfer a few frames ahead 1618 * of the current frame position. Else two isochronous 1619 * transfers might overlap. 1620 */ 1621 xfer->pipe->isoc_next = (nframes + 3) & AT91_UDP_FRM_MASK; 1622 xfer->pipe->is_synced = 1; 1623 DPRINTFN(3, "start next=%d\n", xfer->pipe->isoc_next); 1624 } 1625 /* 1626 * compute how many milliseconds the insertion is ahead of the 1627 * current frame position: 1628 */ 1629 temp = (xfer->pipe->isoc_next - nframes) & AT91_UDP_FRM_MASK; 1630 1631 /* 1632 * pre-compute when the isochronous transfer will be finished: 1633 */ 1634 xfer->isoc_time_complete = 1635 usb2_isoc_time_expand(&sc->sc_bus, nframes) + temp + 1636 xfer->nframes; 1637 1638 /* compute frame number for next insertion */ 1639 xfer->pipe->isoc_next += xfer->nframes; 1640 1641 /* setup TDs */ 1642 at91dci_setup_standard_chain(xfer); 1643} 1644 1645static void 1646at91dci_device_isoc_fs_start(struct usb2_xfer *xfer) 1647{ 1648 /* start TD chain */ 1649 at91dci_start_standard_chain(xfer); 1650} 1651 1652struct usb2_pipe_methods at91dci_device_isoc_fs_methods = 1653{ 1654 .open = at91dci_device_isoc_fs_open, 1655 .close = at91dci_device_isoc_fs_close, 1656 .enter = at91dci_device_isoc_fs_enter, 1657 .start = at91dci_device_isoc_fs_start, 1658}; 1659 1660/*------------------------------------------------------------------------* 1661 * at91dci root control support 1662 *------------------------------------------------------------------------* 1663 * Simulate a hardware HUB by handling all the necessary requests. 1664 *------------------------------------------------------------------------*/ 1665 1666static const struct usb2_device_descriptor at91dci_devd = { 1667 .bLength = sizeof(struct usb2_device_descriptor), 1668 .bDescriptorType = UDESC_DEVICE, 1669 .bcdUSB = {0x00, 0x02}, 1670 .bDeviceClass = UDCLASS_HUB, 1671 .bDeviceSubClass = UDSUBCLASS_HUB, 1672 .bDeviceProtocol = UDPROTO_HSHUBSTT, 1673 .bMaxPacketSize = 64, 1674 .bcdDevice = {0x00, 0x01}, 1675 .iManufacturer = 1, 1676 .iProduct = 2, 1677 .bNumConfigurations = 1, 1678}; 1679 1680static const struct usb2_device_qualifier at91dci_odevd = { 1681 .bLength = sizeof(struct usb2_device_qualifier), 1682 .bDescriptorType = UDESC_DEVICE_QUALIFIER, 1683 .bcdUSB = {0x00, 0x02}, 1684 .bDeviceClass = UDCLASS_HUB, 1685 .bDeviceSubClass = UDSUBCLASS_HUB, 1686 .bDeviceProtocol = UDPROTO_FSHUB, 1687 .bMaxPacketSize0 = 0, 1688 .bNumConfigurations = 0, 1689}; 1690 1691static const struct at91dci_config_desc at91dci_confd = { 1692 .confd = { 1693 .bLength = sizeof(struct usb2_config_descriptor), 1694 .bDescriptorType = UDESC_CONFIG, 1695 .wTotalLength[0] = sizeof(at91dci_confd), 1696 .bNumInterface = 1, 1697 .bConfigurationValue = 1, 1698 .iConfiguration = 0, 1699 .bmAttributes = UC_SELF_POWERED, 1700 .bMaxPower = 0, 1701 }, 1702 .ifcd = { 1703 .bLength = sizeof(struct usb2_interface_descriptor), 1704 .bDescriptorType = UDESC_INTERFACE, 1705 .bNumEndpoints = 1, 1706 .bInterfaceClass = UICLASS_HUB, 1707 .bInterfaceSubClass = UISUBCLASS_HUB, 1708 .bInterfaceProtocol = UIPROTO_HSHUBSTT, 1709 }, 1710 .endpd = { 1711 .bLength = sizeof(struct usb2_endpoint_descriptor), 1712 .bDescriptorType = UDESC_ENDPOINT, 1713 .bEndpointAddress = (UE_DIR_IN | AT9100_DCI_INTR_ENDPT), 1714 .bmAttributes = UE_INTERRUPT, 1715 .wMaxPacketSize[0] = 8, 1716 .bInterval = 255, 1717 }, 1718}; 1719 1720static const struct usb2_hub_descriptor_min at91dci_hubd = { 1721 .bDescLength = sizeof(at91dci_hubd), 1722 .bDescriptorType = UDESC_HUB, 1723 .bNbrPorts = 1, 1724 .wHubCharacteristics[0] = 1725 (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL) & 0xFF, 1726 .wHubCharacteristics[1] = 1727 (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL) >> 8, 1728 .bPwrOn2PwrGood = 50, 1729 .bHubContrCurrent = 0, 1730 .DeviceRemovable = {0}, /* port is removable */ 1731}; 1732 1733#define STRING_LANG \ 1734 0x09, 0x04, /* American English */ 1735 1736#define STRING_VENDOR \ 1737 'A', 0, 'T', 0, 'M', 0, 'E', 0, 'L', 0 1738 1739#define STRING_PRODUCT \ 1740 'D', 0, 'C', 0, 'I', 0, ' ', 0, 'R', 0, \ 1741 'o', 0, 'o', 0, 't', 0, ' ', 0, 'H', 0, \ 1742 'U', 0, 'B', 0, 1743 1744USB_MAKE_STRING_DESC(STRING_LANG, at91dci_langtab); 1745USB_MAKE_STRING_DESC(STRING_VENDOR, at91dci_vendor); 1746USB_MAKE_STRING_DESC(STRING_PRODUCT, at91dci_product); 1747 1748static void 1749at91dci_roothub_exec(struct usb2_bus *bus) 1750{ 1751 struct at91dci_softc *sc = AT9100_DCI_BUS2SC(bus); 1752 struct usb2_sw_transfer *std = &sc->sc_bus.roothub_req; 1753 uint16_t value; 1754 uint16_t index; 1755 1756 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1757 1758 /* buffer reset */ 1759 std->ptr = USB_ADD_BYTES(&sc->sc_hub_temp, 0); 1760 std->len = 0; 1761 1762 value = UGETW(std->req.wValue); 1763 index = UGETW(std->req.wIndex); 1764 1765 /* demultiplex the control request */ 1766 1767 switch (std->req.bmRequestType) { 1768 case UT_READ_DEVICE: 1769 switch (std->req.bRequest) { 1770 case UR_GET_DESCRIPTOR: 1771 goto tr_handle_get_descriptor; 1772 case UR_GET_CONFIG: 1773 goto tr_handle_get_config; 1774 case UR_GET_STATUS: 1775 goto tr_handle_get_status; 1776 default: 1777 goto tr_stalled; 1778 } 1779 break; 1780 1781 case UT_WRITE_DEVICE: 1782 switch (std->req.bRequest) { 1783 case UR_SET_ADDRESS: 1784 goto tr_handle_set_address; 1785 case UR_SET_CONFIG: 1786 goto tr_handle_set_config; 1787 case UR_CLEAR_FEATURE: 1788 goto tr_valid; /* nop */ 1789 case UR_SET_DESCRIPTOR: 1790 goto tr_valid; /* nop */ 1791 case UR_SET_FEATURE: 1792 default: 1793 goto tr_stalled; 1794 } 1795 break; 1796 1797 case UT_WRITE_ENDPOINT: 1798 switch (std->req.bRequest) { 1799 case UR_CLEAR_FEATURE: 1800 switch (UGETW(std->req.wValue)) { 1801 case UF_ENDPOINT_HALT: 1802 goto tr_handle_clear_halt; 1803 case UF_DEVICE_REMOTE_WAKEUP: 1804 goto tr_handle_clear_wakeup; 1805 default: 1806 goto tr_stalled; 1807 } 1808 break; 1809 case UR_SET_FEATURE: 1810 switch (UGETW(std->req.wValue)) { 1811 case UF_ENDPOINT_HALT: 1812 goto tr_handle_set_halt; 1813 case UF_DEVICE_REMOTE_WAKEUP: 1814 goto tr_handle_set_wakeup; 1815 default: 1816 goto tr_stalled; 1817 } 1818 break; 1819 case UR_SYNCH_FRAME: 1820 goto tr_valid; /* nop */ 1821 default: 1822 goto tr_stalled; 1823 } 1824 break; 1825 1826 case UT_READ_ENDPOINT: 1827 switch (std->req.bRequest) { 1828 case UR_GET_STATUS: 1829 goto tr_handle_get_ep_status; 1830 default: 1831 goto tr_stalled; 1832 } 1833 break; 1834 1835 case UT_WRITE_INTERFACE: 1836 switch (std->req.bRequest) { 1837 case UR_SET_INTERFACE: 1838 goto tr_handle_set_interface; 1839 case UR_CLEAR_FEATURE: 1840 goto tr_valid; /* nop */ 1841 case UR_SET_FEATURE: 1842 default: 1843 goto tr_stalled; 1844 } 1845 break; 1846 1847 case UT_READ_INTERFACE: 1848 switch (std->req.bRequest) { 1849 case UR_GET_INTERFACE: 1850 goto tr_handle_get_interface; 1851 case UR_GET_STATUS: 1852 goto tr_handle_get_iface_status; 1853 default: 1854 goto tr_stalled; 1855 } 1856 break; 1857 1858 case UT_WRITE_CLASS_INTERFACE: 1859 case UT_WRITE_VENDOR_INTERFACE: 1860 /* XXX forward */ 1861 break; 1862 1863 case UT_READ_CLASS_INTERFACE: 1864 case UT_READ_VENDOR_INTERFACE: 1865 /* XXX forward */ 1866 break; 1867 1868 case UT_WRITE_CLASS_DEVICE: 1869 switch (std->req.bRequest) { 1870 case UR_CLEAR_FEATURE: 1871 goto tr_valid; 1872 case UR_SET_DESCRIPTOR: 1873 case UR_SET_FEATURE: 1874 break; 1875 default: 1876 goto tr_stalled; 1877 } 1878 break; 1879 1880 case UT_WRITE_CLASS_OTHER: 1881 switch (std->req.bRequest) { 1882 case UR_CLEAR_FEATURE: 1883 goto tr_handle_clear_port_feature; 1884 case UR_SET_FEATURE: 1885 goto tr_handle_set_port_feature; 1886 case UR_CLEAR_TT_BUFFER: 1887 case UR_RESET_TT: 1888 case UR_STOP_TT: 1889 goto tr_valid; 1890 1891 default: 1892 goto tr_stalled; 1893 } 1894 break; 1895 1896 case UT_READ_CLASS_OTHER: 1897 switch (std->req.bRequest) { 1898 case UR_GET_TT_STATE: 1899 goto tr_handle_get_tt_state; 1900 case UR_GET_STATUS: 1901 goto tr_handle_get_port_status; 1902 default: 1903 goto tr_stalled; 1904 } 1905 break; 1906 1907 case UT_READ_CLASS_DEVICE: 1908 switch (std->req.bRequest) { 1909 case UR_GET_DESCRIPTOR: 1910 goto tr_handle_get_class_descriptor; 1911 case UR_GET_STATUS: 1912 goto tr_handle_get_class_status; 1913 1914 default: 1915 goto tr_stalled; 1916 } 1917 break; 1918 default: 1919 goto tr_stalled; 1920 } 1921 goto tr_valid; 1922 1923tr_handle_get_descriptor: 1924 switch (value >> 8) { 1925 case UDESC_DEVICE: 1926 if (value & 0xff) { 1927 goto tr_stalled; 1928 } 1929 std->len = sizeof(at91dci_devd); 1930 std->ptr = USB_ADD_BYTES(&at91dci_devd, 0); 1931 goto tr_valid; 1932 case UDESC_CONFIG: 1933 if (value & 0xff) { 1934 goto tr_stalled; 1935 } 1936 std->len = sizeof(at91dci_confd); 1937 std->ptr = USB_ADD_BYTES(&at91dci_confd, 0); 1938 goto tr_valid; 1939 case UDESC_STRING: 1940 switch (value & 0xff) { 1941 case 0: /* Language table */ 1942 std->len = sizeof(at91dci_langtab); 1943 std->ptr = USB_ADD_BYTES(&at91dci_langtab, 0); 1944 goto tr_valid; 1945 1946 case 1: /* Vendor */ 1947 std->len = sizeof(at91dci_vendor); 1948 std->ptr = USB_ADD_BYTES(&at91dci_vendor, 0); 1949 goto tr_valid; 1950 1951 case 2: /* Product */ 1952 std->len = sizeof(at91dci_product); 1953 std->ptr = USB_ADD_BYTES(&at91dci_product, 0); 1954 goto tr_valid; 1955 default: 1956 break; 1957 } 1958 break; 1959 default: 1960 goto tr_stalled; 1961 } 1962 goto tr_stalled; 1963 1964tr_handle_get_config: 1965 std->len = 1; 1966 sc->sc_hub_temp.wValue[0] = sc->sc_conf; 1967 goto tr_valid; 1968 1969tr_handle_get_status: 1970 std->len = 2; 1971 USETW(sc->sc_hub_temp.wValue, UDS_SELF_POWERED); 1972 goto tr_valid; 1973 1974tr_handle_set_address: 1975 if (value & 0xFF00) { 1976 goto tr_stalled; 1977 } 1978 sc->sc_rt_addr = value; 1979 goto tr_valid; 1980 1981tr_handle_set_config: 1982 if (value >= 2) { 1983 goto tr_stalled; 1984 } 1985 sc->sc_conf = value; 1986 goto tr_valid; 1987 1988tr_handle_get_interface: 1989 std->len = 1; 1990 sc->sc_hub_temp.wValue[0] = 0; 1991 goto tr_valid; 1992 1993tr_handle_get_tt_state: 1994tr_handle_get_class_status: 1995tr_handle_get_iface_status: 1996tr_handle_get_ep_status: 1997 std->len = 2; 1998 USETW(sc->sc_hub_temp.wValue, 0); 1999 goto tr_valid; 2000 2001tr_handle_set_halt: 2002tr_handle_set_interface: 2003tr_handle_set_wakeup: 2004tr_handle_clear_wakeup: 2005tr_handle_clear_halt: 2006 goto tr_valid; 2007 2008tr_handle_clear_port_feature: 2009 if (index != 1) { 2010 goto tr_stalled; 2011 } 2012 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE on port %d\n", index); 2013 2014 switch (value) { 2015 case UHF_PORT_SUSPEND: 2016 at91dci_wakeup_peer(sc); 2017 break; 2018 2019 case UHF_PORT_ENABLE: 2020 sc->sc_flags.port_enabled = 0; 2021 break; 2022 2023 case UHF_PORT_TEST: 2024 case UHF_PORT_INDICATOR: 2025 case UHF_C_PORT_ENABLE: 2026 case UHF_C_PORT_OVER_CURRENT: 2027 case UHF_C_PORT_RESET: 2028 /* nops */ 2029 break; 2030 case UHF_PORT_POWER: 2031 sc->sc_flags.port_powered = 0; 2032 at91dci_pull_down(sc); 2033 at91dci_clocks_off(sc); 2034 break; 2035 case UHF_C_PORT_CONNECTION: 2036 sc->sc_flags.change_connect = 0; 2037 break; 2038 case UHF_C_PORT_SUSPEND: 2039 sc->sc_flags.change_suspend = 0; 2040 break; 2041 default: 2042 std->err = USB_ERR_IOERROR; 2043 goto done; 2044 } 2045 goto tr_valid; 2046 2047tr_handle_set_port_feature: 2048 if (index != 1) { 2049 goto tr_stalled; 2050 } 2051 DPRINTFN(9, "UR_SET_PORT_FEATURE\n"); 2052 2053 switch (value) { 2054 case UHF_PORT_ENABLE: 2055 sc->sc_flags.port_enabled = 1; 2056 break; 2057 case UHF_PORT_SUSPEND: 2058 case UHF_PORT_RESET: 2059 case UHF_PORT_TEST: 2060 case UHF_PORT_INDICATOR: 2061 /* nops */ 2062 break; 2063 case UHF_PORT_POWER: 2064 sc->sc_flags.port_powered = 1; 2065 break; 2066 default: 2067 std->err = USB_ERR_IOERROR; 2068 goto done; 2069 } 2070 goto tr_valid; 2071 2072tr_handle_get_port_status: 2073 2074 DPRINTFN(9, "UR_GET_PORT_STATUS\n"); 2075 2076 if (index != 1) { 2077 goto tr_stalled; 2078 } 2079 if (sc->sc_flags.status_vbus) { 2080 at91dci_clocks_on(sc); 2081 at91dci_pull_up(sc); 2082 } else { 2083 at91dci_pull_down(sc); 2084 at91dci_clocks_off(sc); 2085 } 2086 2087 /* Select FULL-speed and Device Side Mode */ 2088 2089 value = UPS_PORT_MODE_DEVICE; 2090 2091 if (sc->sc_flags.port_powered) { 2092 value |= UPS_PORT_POWER; 2093 } 2094 if (sc->sc_flags.port_enabled) { 2095 value |= UPS_PORT_ENABLED; 2096 } 2097 if (sc->sc_flags.status_vbus && 2098 sc->sc_flags.status_bus_reset) { 2099 value |= UPS_CURRENT_CONNECT_STATUS; 2100 } 2101 if (sc->sc_flags.status_suspend) { 2102 value |= UPS_SUSPEND; 2103 } 2104 USETW(sc->sc_hub_temp.ps.wPortStatus, value); 2105 2106 value = 0; 2107 2108 if (sc->sc_flags.change_connect) { 2109 value |= UPS_C_CONNECT_STATUS; 2110 2111 if (sc->sc_flags.status_vbus && 2112 sc->sc_flags.status_bus_reset) { 2113 /* reset endpoint flags */ 2114 bzero(sc->sc_ep_flags, sizeof(sc->sc_ep_flags)); 2115 } 2116 } 2117 if (sc->sc_flags.change_suspend) { 2118 value |= UPS_C_SUSPEND; 2119 } 2120 USETW(sc->sc_hub_temp.ps.wPortChange, value); 2121 std->len = sizeof(sc->sc_hub_temp.ps); 2122 goto tr_valid; 2123 2124tr_handle_get_class_descriptor: 2125 if (value & 0xFF) { 2126 goto tr_stalled; 2127 } 2128 std->ptr = USB_ADD_BYTES(&at91dci_hubd, 0); 2129 std->len = sizeof(at91dci_hubd); 2130 goto tr_valid; 2131 2132tr_stalled: 2133 std->err = USB_ERR_STALLED; 2134tr_valid: 2135done: 2136 return; 2137} 2138 2139static void 2140at91dci_xfer_setup(struct usb2_setup_params *parm) 2141{ 2142 const struct usb2_hw_ep_profile *pf; 2143 struct at91dci_softc *sc; 2144 struct usb2_xfer *xfer; 2145 void *last_obj; 2146 uint32_t ntd; 2147 uint32_t n; 2148 uint8_t ep_no; 2149 2150 sc = AT9100_DCI_BUS2SC(parm->udev->bus); 2151 xfer = parm->curr_xfer; 2152 2153 /* 2154 * NOTE: This driver does not use any of the parameters that 2155 * are computed from the following values. Just set some 2156 * reasonable dummies: 2157 */ 2158 parm->hc_max_packet_size = 0x500; 2159 parm->hc_max_packet_count = 1; 2160 parm->hc_max_frame_size = 0x500; 2161 2162 usb2_transfer_setup_sub(parm); 2163 2164 /* 2165 * compute maximum number of TDs 2166 */ 2167 if (parm->methods == &at91dci_device_ctrl_methods) { 2168 2169 ntd = xfer->nframes + 1 /* STATUS */ + 1 /* SYNC 1 */ 2170 + 1 /* SYNC 2 */ ; 2171 2172 } else if (parm->methods == &at91dci_device_bulk_methods) { 2173 2174 ntd = xfer->nframes + 1 /* SYNC */ ; 2175 2176 } else if (parm->methods == &at91dci_device_intr_methods) { 2177 2178 ntd = xfer->nframes + 1 /* SYNC */ ; 2179 2180 } else if (parm->methods == &at91dci_device_isoc_fs_methods) { 2181 2182 ntd = xfer->nframes + 1 /* SYNC */ ; 2183 2184 } else { 2185 2186 ntd = 0; 2187 } 2188 2189 /* 2190 * check if "usb2_transfer_setup_sub" set an error 2191 */ 2192 if (parm->err) { 2193 return; 2194 } 2195 /* 2196 * allocate transfer descriptors 2197 */ 2198 last_obj = NULL; 2199 2200 /* 2201 * get profile stuff 2202 */ 2203 if (ntd) { 2204 2205 ep_no = xfer->endpoint & UE_ADDR; 2206 at91dci_get_hw_ep_profile(parm->udev, &pf, ep_no); 2207 2208 if (pf == NULL) { 2209 /* should not happen */ 2210 parm->err = USB_ERR_INVAL; 2211 return; 2212 } 2213 } else { 2214 ep_no = 0; 2215 pf = NULL; 2216 } 2217 2218 /* align data */ 2219 parm->size[0] += ((-parm->size[0]) & (USB_HOST_ALIGN - 1)); 2220 2221 for (n = 0; n != ntd; n++) { 2222 2223 struct at91dci_td *td; 2224 2225 if (parm->buf) { 2226 2227 td = USB_ADD_BYTES(parm->buf, parm->size[0]); 2228 2229 /* init TD */ 2230 td->io_tag = sc->sc_io_tag; 2231 td->io_hdl = sc->sc_io_hdl; 2232 td->max_packet_size = xfer->max_packet_size; 2233 td->status_reg = AT91_UDP_CSR(ep_no); 2234 td->fifo_reg = AT91_UDP_FDR(ep_no); 2235 if (pf->support_multi_buffer) { 2236 td->support_multi_buffer = 1; 2237 } 2238 td->obj_next = last_obj; 2239 2240 last_obj = td; 2241 } 2242 parm->size[0] += sizeof(*td); 2243 } 2244 2245 xfer->td_start[0] = last_obj; 2246} 2247 2248static void 2249at91dci_xfer_unsetup(struct usb2_xfer *xfer) 2250{ 2251 return; 2252} 2253 2254static void 2255at91dci_pipe_init(struct usb2_device *udev, struct usb2_endpoint_descriptor *edesc, 2256 struct usb2_pipe *pipe) 2257{ 2258 struct at91dci_softc *sc = AT9100_DCI_BUS2SC(udev->bus); 2259 2260 DPRINTFN(2, "pipe=%p, addr=%d, endpt=%d, mode=%d (%d)\n", 2261 pipe, udev->address, 2262 edesc->bEndpointAddress, udev->flags.usb2_mode, 2263 sc->sc_rt_addr); 2264 2265 if (udev->device_index != sc->sc_rt_addr) { 2266 2267 if (udev->flags.usb2_mode != USB_MODE_DEVICE) { 2268 /* not supported */ 2269 return; 2270 } 2271 if (udev->speed != USB_SPEED_FULL) { 2272 /* not supported */ 2273 return; 2274 } 2275 switch (edesc->bmAttributes & UE_XFERTYPE) { 2276 case UE_CONTROL: 2277 pipe->methods = &at91dci_device_ctrl_methods; 2278 break; 2279 case UE_INTERRUPT: 2280 pipe->methods = &at91dci_device_intr_methods; 2281 break; 2282 case UE_ISOCHRONOUS: 2283 pipe->methods = &at91dci_device_isoc_fs_methods; 2284 break; 2285 case UE_BULK: 2286 pipe->methods = &at91dci_device_bulk_methods; 2287 break; 2288 default: 2289 /* do nothing */ 2290 break; 2291 } 2292 } 2293} 2294 2295struct usb2_bus_methods at91dci_bus_methods = 2296{ 2297 .pipe_init = &at91dci_pipe_init, 2298 .xfer_setup = &at91dci_xfer_setup, 2299 .xfer_unsetup = &at91dci_xfer_unsetup, 2300 .get_hw_ep_profile = &at91dci_get_hw_ep_profile, 2301 .set_stall = &at91dci_set_stall, 2302 .clear_stall = &at91dci_clear_stall, 2303 .roothub_exec = &at91dci_roothub_exec, 2304}; 2305