at91dci.c revision 190181
1#include <sys/cdefs.h> 2__FBSDID("$FreeBSD: head/sys/dev/usb/controller/at91dci.c 190181 2009-03-20 21:50:54Z thompsa $"); 3 4/*- 5 * Copyright (c) 2007-2008 Hans Petter Selasky. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29/* 30 * This file contains the driver for the AT91 series USB Device 31 * Controller 32 */ 33 34/* 35 * Thanks to "David Brownell" for helping out regarding the hardware 36 * endpoint profiles. 37 */ 38 39/* 40 * NOTE: The "fifo_bank" is not reset in hardware when the endpoint is 41 * reset ! 42 * 43 * NOTE: When the chip detects BUS-reset it will also reset the 44 * endpoints, Function-address and more. 45 */ 46 47#include <dev/usb/usb.h> 48#include <dev/usb/usb_mfunc.h> 49#include <dev/usb/usb_error.h> 50 51#define USB_DEBUG_VAR at91dcidebug 52 53#include <dev/usb/usb_core.h> 54#include <dev/usb/usb_debug.h> 55#include <dev/usb/usb_busdma.h> 56#include <dev/usb/usb_process.h> 57#include <dev/usb/usb_sw_transfer.h> 58#include <dev/usb/usb_transfer.h> 59#include <dev/usb/usb_device.h> 60#include <dev/usb/usb_hub.h> 61#include <dev/usb/usb_util.h> 62 63#include <dev/usb/usb_controller.h> 64#include <dev/usb/usb_bus.h> 65#include <dev/usb/controller/at91dci.h> 66 67#define AT9100_DCI_BUS2SC(bus) \ 68 ((struct at91dci_softc *)(((uint8_t *)(bus)) - \ 69 ((uint8_t *)&(((struct at91dci_softc *)0)->sc_bus)))) 70 71#define AT9100_DCI_PC2SC(pc) \ 72 AT9100_DCI_BUS2SC(USB_DMATAG_TO_XROOT((pc)->tag_parent)->bus) 73 74#if USB_DEBUG 75static int at91dcidebug = 0; 76 77SYSCTL_NODE(_hw_usb2, OID_AUTO, at91dci, CTLFLAG_RW, 0, "USB at91dci"); 78SYSCTL_INT(_hw_usb2_at91dci, OID_AUTO, debug, CTLFLAG_RW, 79 &at91dcidebug, 0, "at91dci debug level"); 80#endif 81 82#define AT9100_DCI_INTR_ENDPT 1 83 84/* prototypes */ 85 86struct usb2_bus_methods at91dci_bus_methods; 87struct usb2_pipe_methods at91dci_device_bulk_methods; 88struct usb2_pipe_methods at91dci_device_ctrl_methods; 89struct usb2_pipe_methods at91dci_device_intr_methods; 90struct usb2_pipe_methods at91dci_device_isoc_fs_methods; 91struct usb2_pipe_methods at91dci_root_ctrl_methods; 92struct usb2_pipe_methods at91dci_root_intr_methods; 93 94static at91dci_cmd_t at91dci_setup_rx; 95static at91dci_cmd_t at91dci_data_rx; 96static at91dci_cmd_t at91dci_data_tx; 97static at91dci_cmd_t at91dci_data_tx_sync; 98static void at91dci_device_done(struct usb2_xfer *, usb2_error_t); 99static void at91dci_do_poll(struct usb2_bus *); 100static void at91dci_root_ctrl_poll(struct at91dci_softc *); 101static void at91dci_standard_done(struct usb2_xfer *); 102 103static usb2_sw_transfer_func_t at91dci_root_intr_done; 104static usb2_sw_transfer_func_t at91dci_root_ctrl_done; 105 106/* 107 * NOTE: Some of the bits in the CSR register have inverse meaning so 108 * we need a helper macro when acknowledging events: 109 */ 110#define AT91_CSR_ACK(csr, what) do { \ 111 (csr) &= ~((AT91_UDP_CSR_FORCESTALL| \ 112 AT91_UDP_CSR_TXPKTRDY| \ 113 AT91_UDP_CSR_RXBYTECNT) ^ (what));\ 114 (csr) |= ((AT91_UDP_CSR_RX_DATA_BK0| \ 115 AT91_UDP_CSR_RX_DATA_BK1| \ 116 AT91_UDP_CSR_TXCOMP| \ 117 AT91_UDP_CSR_RXSETUP| \ 118 AT91_UDP_CSR_STALLSENT) ^ (what)); \ 119} while (0) 120 121/* 122 * Here is a list of what the chip supports. 123 * Probably it supports more than listed here! 124 */ 125static const struct usb2_hw_ep_profile 126 at91dci_ep_profile[AT91_UDP_EP_MAX] = { 127 128 [0] = { 129 .max_in_frame_size = 8, 130 .max_out_frame_size = 8, 131 .is_simplex = 1, 132 .support_control = 1, 133 }, 134 [1] = { 135 .max_in_frame_size = 64, 136 .max_out_frame_size = 64, 137 .is_simplex = 1, 138 .support_multi_buffer = 1, 139 .support_bulk = 1, 140 .support_interrupt = 1, 141 .support_isochronous = 1, 142 .support_in = 1, 143 .support_out = 1, 144 }, 145 [2] = { 146 .max_in_frame_size = 64, 147 .max_out_frame_size = 64, 148 .is_simplex = 1, 149 .support_multi_buffer = 1, 150 .support_bulk = 1, 151 .support_interrupt = 1, 152 .support_isochronous = 1, 153 .support_in = 1, 154 .support_out = 1, 155 }, 156 [3] = { 157 /* can also do BULK */ 158 .max_in_frame_size = 8, 159 .max_out_frame_size = 8, 160 .is_simplex = 1, 161 .support_interrupt = 1, 162 .support_in = 1, 163 .support_out = 1, 164 }, 165 [4] = { 166 .max_in_frame_size = 256, 167 .max_out_frame_size = 256, 168 .is_simplex = 1, 169 .support_multi_buffer = 1, 170 .support_bulk = 1, 171 .support_interrupt = 1, 172 .support_isochronous = 1, 173 .support_in = 1, 174 .support_out = 1, 175 }, 176 [5] = { 177 .max_in_frame_size = 256, 178 .max_out_frame_size = 256, 179 .is_simplex = 1, 180 .support_multi_buffer = 1, 181 .support_bulk = 1, 182 .support_interrupt = 1, 183 .support_isochronous = 1, 184 .support_in = 1, 185 .support_out = 1, 186 }, 187}; 188 189static void 190at91dci_get_hw_ep_profile(struct usb2_device *udev, 191 const struct usb2_hw_ep_profile **ppf, uint8_t ep_addr) 192{ 193 if (ep_addr < AT91_UDP_EP_MAX) { 194 *ppf = (at91dci_ep_profile + ep_addr); 195 } else { 196 *ppf = NULL; 197 } 198} 199 200static void 201at91dci_clocks_on(struct at91dci_softc *sc) 202{ 203 if (sc->sc_flags.clocks_off && 204 sc->sc_flags.port_powered) { 205 206 DPRINTFN(5, "\n"); 207 208 if (sc->sc_clocks_on) { 209 (sc->sc_clocks_on) (sc->sc_clocks_arg); 210 } 211 sc->sc_flags.clocks_off = 0; 212 213 /* enable Transceiver */ 214 AT91_UDP_WRITE_4(sc, AT91_UDP_TXVC, 0); 215 } 216} 217 218static void 219at91dci_clocks_off(struct at91dci_softc *sc) 220{ 221 if (!sc->sc_flags.clocks_off) { 222 223 DPRINTFN(5, "\n"); 224 225 /* disable Transceiver */ 226 AT91_UDP_WRITE_4(sc, AT91_UDP_TXVC, AT91_UDP_TXVC_DIS); 227 228 if (sc->sc_clocks_off) { 229 (sc->sc_clocks_off) (sc->sc_clocks_arg); 230 } 231 sc->sc_flags.clocks_off = 1; 232 } 233} 234 235static void 236at91dci_pull_up(struct at91dci_softc *sc) 237{ 238 /* pullup D+, if possible */ 239 240 if (!sc->sc_flags.d_pulled_up && 241 sc->sc_flags.port_powered) { 242 sc->sc_flags.d_pulled_up = 1; 243 (sc->sc_pull_up) (sc->sc_pull_arg); 244 } 245} 246 247static void 248at91dci_pull_down(struct at91dci_softc *sc) 249{ 250 /* pulldown D+, if possible */ 251 252 if (sc->sc_flags.d_pulled_up) { 253 sc->sc_flags.d_pulled_up = 0; 254 (sc->sc_pull_down) (sc->sc_pull_arg); 255 } 256} 257 258static void 259at91dci_wakeup_peer(struct usb2_xfer *xfer) 260{ 261 struct at91dci_softc *sc = AT9100_DCI_BUS2SC(xfer->xroot->bus); 262 263 if (!(sc->sc_flags.status_suspend)) { 264 return; 265 } 266 267 AT91_UDP_WRITE_4(sc, AT91_UDP_GSTATE, AT91_UDP_GSTATE_ESR); 268 269 /* wait 8 milliseconds */ 270 /* Wait for reset to complete. */ 271 usb2_pause_mtx(&sc->sc_bus.bus_mtx, hz / 125); 272 273 AT91_UDP_WRITE_4(sc, AT91_UDP_GSTATE, 0); 274} 275 276static void 277at91dci_set_address(struct at91dci_softc *sc, uint8_t addr) 278{ 279 DPRINTFN(5, "addr=%d\n", addr); 280 281 AT91_UDP_WRITE_4(sc, AT91_UDP_FADDR, addr | 282 AT91_UDP_FADDR_EN); 283} 284 285static uint8_t 286at91dci_setup_rx(struct at91dci_td *td) 287{ 288 struct at91dci_softc *sc; 289 struct usb2_device_request req; 290 uint32_t csr; 291 uint32_t temp; 292 uint16_t count; 293 294 /* read out FIFO status */ 295 csr = bus_space_read_4(td->io_tag, td->io_hdl, 296 td->status_reg); 297 298 DPRINTFN(5, "csr=0x%08x rem=%u\n", csr, td->remainder); 299 300 temp = csr; 301 temp &= (AT91_UDP_CSR_RX_DATA_BK0 | 302 AT91_UDP_CSR_RX_DATA_BK1 | 303 AT91_UDP_CSR_STALLSENT | 304 AT91_UDP_CSR_RXSETUP | 305 AT91_UDP_CSR_TXCOMP); 306 307 if (!(csr & AT91_UDP_CSR_RXSETUP)) { 308 /* abort any ongoing transfer */ 309 if (!td->did_stall) { 310 DPRINTFN(5, "stalling\n"); 311 temp |= AT91_UDP_CSR_FORCESTALL; 312 td->did_stall = 1; 313 } 314 goto not_complete; 315 } 316 /* get the packet byte count */ 317 count = (csr & AT91_UDP_CSR_RXBYTECNT) >> 16; 318 319 /* verify data length */ 320 if (count != td->remainder) { 321 DPRINTFN(0, "Invalid SETUP packet " 322 "length, %d bytes\n", count); 323 goto not_complete; 324 } 325 if (count != sizeof(req)) { 326 DPRINTFN(0, "Unsupported SETUP packet " 327 "length, %d bytes\n", count); 328 goto not_complete; 329 } 330 /* receive data */ 331 bus_space_read_multi_1(td->io_tag, td->io_hdl, 332 td->fifo_reg, (void *)&req, sizeof(req)); 333 334 /* copy data into real buffer */ 335 usb2_copy_in(td->pc, 0, &req, sizeof(req)); 336 337 td->offset = sizeof(req); 338 td->remainder = 0; 339 340 /* get pointer to softc */ 341 sc = AT9100_DCI_PC2SC(td->pc); 342 343 /* sneak peek the set address */ 344 if ((req.bmRequestType == UT_WRITE_DEVICE) && 345 (req.bRequest == UR_SET_ADDRESS)) { 346 sc->sc_dv_addr = req.wValue[0] & 0x7F; 347 } else { 348 sc->sc_dv_addr = 0xFF; 349 } 350 351 /* sneak peek the endpoint direction */ 352 if (req.bmRequestType & UE_DIR_IN) { 353 csr |= AT91_UDP_CSR_DIR; 354 } else { 355 csr &= ~AT91_UDP_CSR_DIR; 356 } 357 358 /* write the direction of the control transfer */ 359 AT91_CSR_ACK(csr, temp); 360 bus_space_write_4(td->io_tag, td->io_hdl, 361 td->status_reg, csr); 362 return (0); /* complete */ 363 364not_complete: 365 /* clear interrupts, if any */ 366 if (temp) { 367 DPRINTFN(5, "clearing 0x%08x\n", temp); 368 AT91_CSR_ACK(csr, temp); 369 bus_space_write_4(td->io_tag, td->io_hdl, 370 td->status_reg, csr); 371 } 372 return (1); /* not complete */ 373 374} 375 376static uint8_t 377at91dci_data_rx(struct at91dci_td *td) 378{ 379 struct usb2_page_search buf_res; 380 uint32_t csr; 381 uint32_t temp; 382 uint16_t count; 383 uint8_t to; 384 uint8_t got_short; 385 386 to = 2; /* don't loop forever! */ 387 got_short = 0; 388 389 /* check if any of the FIFO banks have data */ 390repeat: 391 /* read out FIFO status */ 392 csr = bus_space_read_4(td->io_tag, td->io_hdl, 393 td->status_reg); 394 395 DPRINTFN(5, "csr=0x%08x rem=%u\n", csr, td->remainder); 396 397 if (csr & AT91_UDP_CSR_RXSETUP) { 398 if (td->remainder == 0) { 399 /* 400 * We are actually complete and have 401 * received the next SETUP 402 */ 403 DPRINTFN(5, "faking complete\n"); 404 return (0); /* complete */ 405 } 406 /* 407 * USB Host Aborted the transfer. 408 */ 409 td->error = 1; 410 return (0); /* complete */ 411 } 412 /* Make sure that "STALLSENT" gets cleared */ 413 temp = csr; 414 temp &= AT91_UDP_CSR_STALLSENT; 415 416 /* check status */ 417 if (!(csr & (AT91_UDP_CSR_RX_DATA_BK0 | 418 AT91_UDP_CSR_RX_DATA_BK1))) { 419 if (temp) { 420 /* write command */ 421 AT91_CSR_ACK(csr, temp); 422 bus_space_write_4(td->io_tag, td->io_hdl, 423 td->status_reg, csr); 424 } 425 return (1); /* not complete */ 426 } 427 /* get the packet byte count */ 428 count = (csr & AT91_UDP_CSR_RXBYTECNT) >> 16; 429 430 /* verify the packet byte count */ 431 if (count != td->max_packet_size) { 432 if (count < td->max_packet_size) { 433 /* we have a short packet */ 434 td->short_pkt = 1; 435 got_short = 1; 436 } else { 437 /* invalid USB packet */ 438 td->error = 1; 439 return (0); /* we are complete */ 440 } 441 } 442 /* verify the packet byte count */ 443 if (count > td->remainder) { 444 /* invalid USB packet */ 445 td->error = 1; 446 return (0); /* we are complete */ 447 } 448 while (count > 0) { 449 usb2_get_page(td->pc, td->offset, &buf_res); 450 451 /* get correct length */ 452 if (buf_res.length > count) { 453 buf_res.length = count; 454 } 455 /* receive data */ 456 bus_space_read_multi_1(td->io_tag, td->io_hdl, 457 td->fifo_reg, buf_res.buffer, buf_res.length); 458 459 /* update counters */ 460 count -= buf_res.length; 461 td->offset += buf_res.length; 462 td->remainder -= buf_res.length; 463 } 464 465 /* clear status bits */ 466 if (td->support_multi_buffer) { 467 if (td->fifo_bank) { 468 td->fifo_bank = 0; 469 temp |= AT91_UDP_CSR_RX_DATA_BK1; 470 } else { 471 td->fifo_bank = 1; 472 temp |= AT91_UDP_CSR_RX_DATA_BK0; 473 } 474 } else { 475 temp |= (AT91_UDP_CSR_RX_DATA_BK0 | 476 AT91_UDP_CSR_RX_DATA_BK1); 477 } 478 479 /* write command */ 480 AT91_CSR_ACK(csr, temp); 481 bus_space_write_4(td->io_tag, td->io_hdl, 482 td->status_reg, csr); 483 484 /* 485 * NOTE: We may have to delay a little bit before 486 * proceeding after clearing the DATA_BK bits. 487 */ 488 489 /* check if we are complete */ 490 if ((td->remainder == 0) || got_short) { 491 if (td->short_pkt) { 492 /* we are complete */ 493 return (0); 494 } 495 /* else need to receive a zero length packet */ 496 } 497 if (--to) { 498 goto repeat; 499 } 500 return (1); /* not complete */ 501} 502 503static uint8_t 504at91dci_data_tx(struct at91dci_td *td) 505{ 506 struct usb2_page_search buf_res; 507 uint32_t csr; 508 uint32_t temp; 509 uint16_t count; 510 uint8_t to; 511 512 to = 2; /* don't loop forever! */ 513 514repeat: 515 516 /* read out FIFO status */ 517 csr = bus_space_read_4(td->io_tag, td->io_hdl, 518 td->status_reg); 519 520 DPRINTFN(5, "csr=0x%08x rem=%u\n", csr, td->remainder); 521 522 if (csr & AT91_UDP_CSR_RXSETUP) { 523 /* 524 * The current transfer was aborted 525 * by the USB Host 526 */ 527 td->error = 1; 528 return (0); /* complete */ 529 } 530 /* Make sure that "STALLSENT" gets cleared */ 531 temp = csr; 532 temp &= AT91_UDP_CSR_STALLSENT; 533 534 if (csr & AT91_UDP_CSR_TXPKTRDY) { 535 if (temp) { 536 /* write command */ 537 AT91_CSR_ACK(csr, temp); 538 bus_space_write_4(td->io_tag, td->io_hdl, 539 td->status_reg, csr); 540 } 541 return (1); /* not complete */ 542 } else { 543 /* clear TXCOMP and set TXPKTRDY */ 544 temp |= (AT91_UDP_CSR_TXCOMP | 545 AT91_UDP_CSR_TXPKTRDY); 546 } 547 548 count = td->max_packet_size; 549 if (td->remainder < count) { 550 /* we have a short packet */ 551 td->short_pkt = 1; 552 count = td->remainder; 553 } 554 while (count > 0) { 555 556 usb2_get_page(td->pc, td->offset, &buf_res); 557 558 /* get correct length */ 559 if (buf_res.length > count) { 560 buf_res.length = count; 561 } 562 /* transmit data */ 563 bus_space_write_multi_1(td->io_tag, td->io_hdl, 564 td->fifo_reg, buf_res.buffer, buf_res.length); 565 566 /* update counters */ 567 count -= buf_res.length; 568 td->offset += buf_res.length; 569 td->remainder -= buf_res.length; 570 } 571 572 /* write command */ 573 AT91_CSR_ACK(csr, temp); 574 bus_space_write_4(td->io_tag, td->io_hdl, 575 td->status_reg, csr); 576 577 /* check remainder */ 578 if (td->remainder == 0) { 579 if (td->short_pkt) { 580 return (0); /* complete */ 581 } 582 /* else we need to transmit a short packet */ 583 } 584 if (--to) { 585 goto repeat; 586 } 587 return (1); /* not complete */ 588} 589 590static uint8_t 591at91dci_data_tx_sync(struct at91dci_td *td) 592{ 593 struct at91dci_softc *sc; 594 uint32_t csr; 595 uint32_t temp; 596 597#if 0 598repeat: 599#endif 600 601 /* read out FIFO status */ 602 csr = bus_space_read_4(td->io_tag, td->io_hdl, 603 td->status_reg); 604 605 DPRINTFN(5, "csr=0x%08x\n", csr); 606 607 if (csr & AT91_UDP_CSR_RXSETUP) { 608 DPRINTFN(5, "faking complete\n"); 609 /* Race condition */ 610 return (0); /* complete */ 611 } 612 temp = csr; 613 temp &= (AT91_UDP_CSR_STALLSENT | 614 AT91_UDP_CSR_TXCOMP); 615 616 /* check status */ 617 if (csr & AT91_UDP_CSR_TXPKTRDY) { 618 goto not_complete; 619 } 620 if (!(csr & AT91_UDP_CSR_TXCOMP)) { 621 goto not_complete; 622 } 623 sc = AT9100_DCI_PC2SC(td->pc); 624 if (sc->sc_dv_addr != 0xFF) { 625 /* 626 * The AT91 has a special requirement with regard to 627 * setting the address and that is to write the new 628 * address before clearing TXCOMP: 629 */ 630 at91dci_set_address(sc, sc->sc_dv_addr); 631 } 632 /* write command */ 633 AT91_CSR_ACK(csr, temp); 634 bus_space_write_4(td->io_tag, td->io_hdl, 635 td->status_reg, csr); 636 637 return (0); /* complete */ 638 639not_complete: 640 if (temp) { 641 /* write command */ 642 AT91_CSR_ACK(csr, temp); 643 bus_space_write_4(td->io_tag, td->io_hdl, 644 td->status_reg, csr); 645 } 646 return (1); /* not complete */ 647} 648 649static uint8_t 650at91dci_xfer_do_fifo(struct usb2_xfer *xfer) 651{ 652 struct at91dci_softc *sc; 653 struct at91dci_td *td; 654 uint8_t temp; 655 656 DPRINTFN(9, "\n"); 657 658 td = xfer->td_transfer_cache; 659 while (1) { 660 if ((td->func) (td)) { 661 /* operation in progress */ 662 break; 663 } 664 if (((void *)td) == xfer->td_transfer_last) { 665 goto done; 666 } 667 if (td->error) { 668 goto done; 669 } else if (td->remainder > 0) { 670 /* 671 * We had a short transfer. If there is no alternate 672 * next, stop processing ! 673 */ 674 if (!td->alt_next) { 675 goto done; 676 } 677 } 678 /* 679 * Fetch the next transfer descriptor and transfer 680 * some flags to the next transfer descriptor 681 */ 682 temp = 0; 683 if (td->fifo_bank) 684 temp |= 1; 685 td = td->obj_next; 686 xfer->td_transfer_cache = td; 687 if (temp & 1) 688 td->fifo_bank = 1; 689 } 690 return (1); /* not complete */ 691 692done: 693 sc = AT9100_DCI_BUS2SC(xfer->xroot->bus); 694 temp = (xfer->endpoint & UE_ADDR); 695 696 /* update FIFO bank flag and multi buffer */ 697 if (td->fifo_bank) { 698 sc->sc_ep_flags[temp].fifo_bank = 1; 699 } else { 700 sc->sc_ep_flags[temp].fifo_bank = 0; 701 } 702 703 /* compute all actual lengths */ 704 705 at91dci_standard_done(xfer); 706 707 return (0); /* complete */ 708} 709 710static void 711at91dci_interrupt_poll(struct at91dci_softc *sc) 712{ 713 struct usb2_xfer *xfer; 714 715repeat: 716 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 717 if (!at91dci_xfer_do_fifo(xfer)) { 718 /* queue has been modified */ 719 goto repeat; 720 } 721 } 722} 723 724void 725at91dci_vbus_interrupt(struct at91dci_softc *sc, uint8_t is_on) 726{ 727 DPRINTFN(5, "vbus = %u\n", is_on); 728 729 USB_BUS_LOCK(&sc->sc_bus); 730 if (is_on) { 731 if (!sc->sc_flags.status_vbus) { 732 sc->sc_flags.status_vbus = 1; 733 734 /* complete root HUB interrupt endpoint */ 735 736 usb2_sw_transfer(&sc->sc_root_intr, 737 &at91dci_root_intr_done); 738 } 739 } else { 740 if (sc->sc_flags.status_vbus) { 741 sc->sc_flags.status_vbus = 0; 742 sc->sc_flags.status_bus_reset = 0; 743 sc->sc_flags.status_suspend = 0; 744 sc->sc_flags.change_suspend = 0; 745 sc->sc_flags.change_connect = 1; 746 747 /* complete root HUB interrupt endpoint */ 748 749 usb2_sw_transfer(&sc->sc_root_intr, 750 &at91dci_root_intr_done); 751 } 752 } 753 USB_BUS_UNLOCK(&sc->sc_bus); 754} 755 756void 757at91dci_interrupt(struct at91dci_softc *sc) 758{ 759 uint32_t status; 760 761 USB_BUS_LOCK(&sc->sc_bus); 762 763 status = AT91_UDP_READ_4(sc, AT91_UDP_ISR); 764 status &= AT91_UDP_INT_DEFAULT; 765 766 if (!status) { 767 USB_BUS_UNLOCK(&sc->sc_bus); 768 return; 769 } 770 /* acknowledge interrupts */ 771 772 AT91_UDP_WRITE_4(sc, AT91_UDP_ICR, status); 773 774 /* check for any bus state change interrupts */ 775 776 if (status & AT91_UDP_INT_BUS) { 777 778 DPRINTFN(5, "real bus interrupt 0x%08x\n", status); 779 780 if (status & AT91_UDP_INT_END_BR) { 781 782 /* set correct state */ 783 sc->sc_flags.status_bus_reset = 1; 784 sc->sc_flags.status_suspend = 0; 785 sc->sc_flags.change_suspend = 0; 786 sc->sc_flags.change_connect = 1; 787 788 /* disable resume interrupt */ 789 AT91_UDP_WRITE_4(sc, AT91_UDP_IDR, 790 AT91_UDP_INT_RXRSM); 791 /* enable suspend interrupt */ 792 AT91_UDP_WRITE_4(sc, AT91_UDP_IER, 793 AT91_UDP_INT_RXSUSP); 794 } 795 /* 796 * If RXRSM and RXSUSP is set at the same time we interpret 797 * that like RESUME. Resume is set when there is at least 3 798 * milliseconds of inactivity on the USB BUS. 799 */ 800 if (status & AT91_UDP_INT_RXRSM) { 801 if (sc->sc_flags.status_suspend) { 802 sc->sc_flags.status_suspend = 0; 803 sc->sc_flags.change_suspend = 1; 804 805 /* disable resume interrupt */ 806 AT91_UDP_WRITE_4(sc, AT91_UDP_IDR, 807 AT91_UDP_INT_RXRSM); 808 /* enable suspend interrupt */ 809 AT91_UDP_WRITE_4(sc, AT91_UDP_IER, 810 AT91_UDP_INT_RXSUSP); 811 } 812 } else if (status & AT91_UDP_INT_RXSUSP) { 813 if (!sc->sc_flags.status_suspend) { 814 sc->sc_flags.status_suspend = 1; 815 sc->sc_flags.change_suspend = 1; 816 817 /* disable suspend interrupt */ 818 AT91_UDP_WRITE_4(sc, AT91_UDP_IDR, 819 AT91_UDP_INT_RXSUSP); 820 821 /* enable resume interrupt */ 822 AT91_UDP_WRITE_4(sc, AT91_UDP_IER, 823 AT91_UDP_INT_RXRSM); 824 } 825 } 826 /* complete root HUB interrupt endpoint */ 827 828 usb2_sw_transfer(&sc->sc_root_intr, 829 &at91dci_root_intr_done); 830 } 831 /* check for any endpoint interrupts */ 832 833 if (status & AT91_UDP_INT_EPS) { 834 835 DPRINTFN(5, "real endpoint interrupt 0x%08x\n", status); 836 837 at91dci_interrupt_poll(sc); 838 } 839 USB_BUS_UNLOCK(&sc->sc_bus); 840} 841 842static void 843at91dci_setup_standard_chain_sub(struct at91dci_std_temp *temp) 844{ 845 struct at91dci_td *td; 846 847 /* get current Transfer Descriptor */ 848 td = temp->td_next; 849 temp->td = td; 850 851 /* prepare for next TD */ 852 temp->td_next = td->obj_next; 853 854 /* fill out the Transfer Descriptor */ 855 td->func = temp->func; 856 td->pc = temp->pc; 857 td->offset = temp->offset; 858 td->remainder = temp->len; 859 td->fifo_bank = 0; 860 td->error = 0; 861 td->did_stall = 0; 862 td->short_pkt = temp->short_pkt; 863 td->alt_next = temp->setup_alt_next; 864} 865 866static void 867at91dci_setup_standard_chain(struct usb2_xfer *xfer) 868{ 869 struct at91dci_std_temp temp; 870 struct at91dci_softc *sc; 871 struct at91dci_td *td; 872 uint32_t x; 873 uint8_t ep_no; 874 uint8_t need_sync; 875 876 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n", 877 xfer->address, UE_GET_ADDR(xfer->endpoint), 878 xfer->sumlen, usb2_get_speed(xfer->xroot->udev)); 879 880 temp.max_frame_size = xfer->max_frame_size; 881 882 td = xfer->td_start[0]; 883 xfer->td_transfer_first = td; 884 xfer->td_transfer_cache = td; 885 886 /* setup temp */ 887 888 temp.td = NULL; 889 temp.td_next = xfer->td_start[0]; 890 temp.setup_alt_next = xfer->flags_int.short_frames_ok; 891 temp.offset = 0; 892 893 sc = AT9100_DCI_BUS2SC(xfer->xroot->bus); 894 ep_no = (xfer->endpoint & UE_ADDR); 895 896 /* check if we should prepend a setup message */ 897 898 if (xfer->flags_int.control_xfr) { 899 if (xfer->flags_int.control_hdr) { 900 901 temp.func = &at91dci_setup_rx; 902 temp.len = xfer->frlengths[0]; 903 temp.pc = xfer->frbuffers + 0; 904 temp.short_pkt = temp.len ? 1 : 0; 905 906 at91dci_setup_standard_chain_sub(&temp); 907 } 908 x = 1; 909 } else { 910 x = 0; 911 } 912 913 if (x != xfer->nframes) { 914 if (xfer->endpoint & UE_DIR_IN) { 915 temp.func = &at91dci_data_tx; 916 need_sync = 1; 917 } else { 918 temp.func = &at91dci_data_rx; 919 need_sync = 0; 920 } 921 922 /* setup "pc" pointer */ 923 temp.pc = xfer->frbuffers + x; 924 } else { 925 need_sync = 0; 926 } 927 while (x != xfer->nframes) { 928 929 /* DATA0 / DATA1 message */ 930 931 temp.len = xfer->frlengths[x]; 932 933 x++; 934 935 if (x == xfer->nframes) { 936 temp.setup_alt_next = 0; 937 } 938 if (temp.len == 0) { 939 940 /* make sure that we send an USB packet */ 941 942 temp.short_pkt = 0; 943 944 } else { 945 946 /* regular data transfer */ 947 948 temp.short_pkt = (xfer->flags.force_short_xfer) ? 0 : 1; 949 } 950 951 at91dci_setup_standard_chain_sub(&temp); 952 953 if (xfer->flags_int.isochronous_xfr) { 954 temp.offset += temp.len; 955 } else { 956 /* get next Page Cache pointer */ 957 temp.pc = xfer->frbuffers + x; 958 } 959 } 960 961 /* always setup a valid "pc" pointer for status and sync */ 962 temp.pc = xfer->frbuffers + 0; 963 964 /* check if we need to sync */ 965 if (need_sync && xfer->flags_int.control_xfr) { 966 967 /* we need a SYNC point after TX */ 968 temp.func = &at91dci_data_tx_sync; 969 temp.len = 0; 970 temp.short_pkt = 0; 971 972 at91dci_setup_standard_chain_sub(&temp); 973 } 974 /* check if we should append a status stage */ 975 if (xfer->flags_int.control_xfr && 976 !xfer->flags_int.control_act) { 977 978 /* 979 * Send a DATA1 message and invert the current 980 * endpoint direction. 981 */ 982 if (xfer->endpoint & UE_DIR_IN) { 983 temp.func = &at91dci_data_rx; 984 need_sync = 0; 985 } else { 986 temp.func = &at91dci_data_tx; 987 need_sync = 1; 988 } 989 temp.len = 0; 990 temp.short_pkt = 0; 991 992 at91dci_setup_standard_chain_sub(&temp); 993 if (need_sync) { 994 /* we need a SYNC point after TX */ 995 temp.func = &at91dci_data_tx_sync; 996 temp.len = 0; 997 temp.short_pkt = 0; 998 999 at91dci_setup_standard_chain_sub(&temp); 1000 } 1001 } 1002 /* must have at least one frame! */ 1003 td = temp.td; 1004 xfer->td_transfer_last = td; 1005 1006 /* setup the correct fifo bank */ 1007 if (sc->sc_ep_flags[ep_no].fifo_bank) { 1008 td = xfer->td_transfer_first; 1009 td->fifo_bank = 1; 1010 } 1011} 1012 1013static void 1014at91dci_timeout(void *arg) 1015{ 1016 struct usb2_xfer *xfer = arg; 1017 1018 DPRINTF("xfer=%p\n", xfer); 1019 1020 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 1021 1022 /* transfer is transferred */ 1023 at91dci_device_done(xfer, USB_ERR_TIMEOUT); 1024} 1025 1026static void 1027at91dci_start_standard_chain(struct usb2_xfer *xfer) 1028{ 1029 DPRINTFN(9, "\n"); 1030 1031 /* poll one time */ 1032 if (at91dci_xfer_do_fifo(xfer)) { 1033 1034 struct at91dci_softc *sc = AT9100_DCI_BUS2SC(xfer->xroot->bus); 1035 uint8_t ep_no = xfer->endpoint & UE_ADDR; 1036 1037 /* 1038 * Only enable the endpoint interrupt when we are actually 1039 * waiting for data, hence we are dealing with level 1040 * triggered interrupts ! 1041 */ 1042 AT91_UDP_WRITE_4(sc, AT91_UDP_IER, AT91_UDP_INT_EP(ep_no)); 1043 1044 DPRINTFN(15, "enable interrupts on endpoint %d\n", ep_no); 1045 1046 /* put transfer on interrupt queue */ 1047 usb2_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 1048 1049 /* start timeout, if any */ 1050 if (xfer->timeout != 0) { 1051 usb2_transfer_timeout_ms(xfer, 1052 &at91dci_timeout, xfer->timeout); 1053 } 1054 } 1055} 1056 1057static void 1058at91dci_root_intr_done(struct usb2_xfer *xfer, 1059 struct usb2_sw_transfer *std) 1060{ 1061 struct at91dci_softc *sc = AT9100_DCI_BUS2SC(xfer->xroot->bus); 1062 1063 DPRINTFN(9, "\n"); 1064 1065 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1066 1067 if (std->state != USB_SW_TR_PRE_DATA) { 1068 if (std->state == USB_SW_TR_PRE_CALLBACK) { 1069 /* transfer transferred */ 1070 at91dci_device_done(xfer, std->err); 1071 } 1072 goto done; 1073 } 1074 /* setup buffer */ 1075 std->ptr = sc->sc_hub_idata; 1076 std->len = sizeof(sc->sc_hub_idata); 1077 1078 /* set port bit */ 1079 sc->sc_hub_idata[0] = 0x02; /* we only have one port */ 1080 1081done: 1082 return; 1083} 1084 1085static usb2_error_t 1086at91dci_standard_done_sub(struct usb2_xfer *xfer) 1087{ 1088 struct at91dci_td *td; 1089 uint32_t len; 1090 uint8_t error; 1091 1092 DPRINTFN(9, "\n"); 1093 1094 td = xfer->td_transfer_cache; 1095 1096 do { 1097 len = td->remainder; 1098 1099 if (xfer->aframes != xfer->nframes) { 1100 /* 1101 * Verify the length and subtract 1102 * the remainder from "frlengths[]": 1103 */ 1104 if (len > xfer->frlengths[xfer->aframes]) { 1105 td->error = 1; 1106 } else { 1107 xfer->frlengths[xfer->aframes] -= len; 1108 } 1109 } 1110 /* Check for transfer error */ 1111 if (td->error) { 1112 /* the transfer is finished */ 1113 error = 1; 1114 td = NULL; 1115 break; 1116 } 1117 /* Check for short transfer */ 1118 if (len > 0) { 1119 if (xfer->flags_int.short_frames_ok) { 1120 /* follow alt next */ 1121 if (td->alt_next) { 1122 td = td->obj_next; 1123 } else { 1124 td = NULL; 1125 } 1126 } else { 1127 /* the transfer is finished */ 1128 td = NULL; 1129 } 1130 error = 0; 1131 break; 1132 } 1133 td = td->obj_next; 1134 1135 /* this USB frame is complete */ 1136 error = 0; 1137 break; 1138 1139 } while (0); 1140 1141 /* update transfer cache */ 1142 1143 xfer->td_transfer_cache = td; 1144 1145 return (error ? 1146 USB_ERR_STALLED : USB_ERR_NORMAL_COMPLETION); 1147} 1148 1149static void 1150at91dci_standard_done(struct usb2_xfer *xfer) 1151{ 1152 usb2_error_t err = 0; 1153 1154 DPRINTFN(13, "xfer=%p pipe=%p transfer done\n", 1155 xfer, xfer->pipe); 1156 1157 /* reset scanner */ 1158 1159 xfer->td_transfer_cache = xfer->td_transfer_first; 1160 1161 if (xfer->flags_int.control_xfr) { 1162 1163 if (xfer->flags_int.control_hdr) { 1164 1165 err = at91dci_standard_done_sub(xfer); 1166 } 1167 xfer->aframes = 1; 1168 1169 if (xfer->td_transfer_cache == NULL) { 1170 goto done; 1171 } 1172 } 1173 while (xfer->aframes != xfer->nframes) { 1174 1175 err = at91dci_standard_done_sub(xfer); 1176 xfer->aframes++; 1177 1178 if (xfer->td_transfer_cache == NULL) { 1179 goto done; 1180 } 1181 } 1182 1183 if (xfer->flags_int.control_xfr && 1184 !xfer->flags_int.control_act) { 1185 1186 err = at91dci_standard_done_sub(xfer); 1187 } 1188done: 1189 at91dci_device_done(xfer, err); 1190} 1191 1192/*------------------------------------------------------------------------* 1193 * at91dci_device_done 1194 * 1195 * NOTE: this function can be called more than one time on the 1196 * same USB transfer! 1197 *------------------------------------------------------------------------*/ 1198static void 1199at91dci_device_done(struct usb2_xfer *xfer, usb2_error_t error) 1200{ 1201 struct at91dci_softc *sc = AT9100_DCI_BUS2SC(xfer->xroot->bus); 1202 uint8_t ep_no; 1203 1204 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1205 1206 DPRINTFN(2, "xfer=%p, pipe=%p, error=%d\n", 1207 xfer, xfer->pipe, error); 1208 1209 if (xfer->flags_int.usb2_mode == USB_MODE_DEVICE) { 1210 ep_no = (xfer->endpoint & UE_ADDR); 1211 1212 /* disable endpoint interrupt */ 1213 AT91_UDP_WRITE_4(sc, AT91_UDP_IDR, AT91_UDP_INT_EP(ep_no)); 1214 1215 DPRINTFN(15, "disable interrupts on endpoint %d\n", ep_no); 1216 } 1217 /* dequeue transfer and start next transfer */ 1218 usb2_transfer_done(xfer, error); 1219} 1220 1221static void 1222at91dci_set_stall(struct usb2_device *udev, struct usb2_xfer *xfer, 1223 struct usb2_pipe *pipe) 1224{ 1225 struct at91dci_softc *sc; 1226 uint32_t csr_val; 1227 uint8_t csr_reg; 1228 1229 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 1230 1231 DPRINTFN(5, "pipe=%p\n", pipe); 1232 1233 if (xfer) { 1234 /* cancel any ongoing transfers */ 1235 at91dci_device_done(xfer, USB_ERR_STALLED); 1236 } 1237 /* set FORCESTALL */ 1238 sc = AT9100_DCI_BUS2SC(udev->bus); 1239 csr_reg = (pipe->edesc->bEndpointAddress & UE_ADDR); 1240 csr_reg = AT91_UDP_CSR(csr_reg); 1241 csr_val = AT91_UDP_READ_4(sc, csr_reg); 1242 AT91_CSR_ACK(csr_val, AT91_UDP_CSR_FORCESTALL); 1243 AT91_UDP_WRITE_4(sc, csr_reg, csr_val); 1244} 1245 1246static void 1247at91dci_clear_stall_sub(struct at91dci_softc *sc, uint8_t ep_no, 1248 uint8_t ep_type, uint8_t ep_dir) 1249{ 1250 const struct usb2_hw_ep_profile *pf; 1251 uint32_t csr_val; 1252 uint32_t temp; 1253 uint8_t csr_reg; 1254 uint8_t to; 1255 1256 if (ep_type == UE_CONTROL) { 1257 /* clearing stall is not needed */ 1258 return; 1259 } 1260 /* compute CSR register offset */ 1261 csr_reg = AT91_UDP_CSR(ep_no); 1262 1263 /* compute default CSR value */ 1264 csr_val = 0; 1265 AT91_CSR_ACK(csr_val, 0); 1266 1267 /* disable endpoint */ 1268 AT91_UDP_WRITE_4(sc, csr_reg, csr_val); 1269 1270 /* get endpoint profile */ 1271 at91dci_get_hw_ep_profile(NULL, &pf, ep_no); 1272 1273 /* reset FIFO */ 1274 AT91_UDP_WRITE_4(sc, AT91_UDP_RST, AT91_UDP_RST_EP(ep_no)); 1275 AT91_UDP_WRITE_4(sc, AT91_UDP_RST, 0); 1276 1277 /* 1278 * NOTE: One would assume that a FIFO reset would release the 1279 * FIFO banks aswell, but it doesn't! We have to do this 1280 * manually! 1281 */ 1282 1283 /* release FIFO banks, if any */ 1284 for (to = 0; to != 2; to++) { 1285 1286 /* get csr value */ 1287 csr_val = AT91_UDP_READ_4(sc, csr_reg); 1288 1289 if (csr_val & (AT91_UDP_CSR_RX_DATA_BK0 | 1290 AT91_UDP_CSR_RX_DATA_BK1)) { 1291 /* clear status bits */ 1292 if (pf->support_multi_buffer) { 1293 if (sc->sc_ep_flags[ep_no].fifo_bank) { 1294 sc->sc_ep_flags[ep_no].fifo_bank = 0; 1295 temp = AT91_UDP_CSR_RX_DATA_BK1; 1296 } else { 1297 sc->sc_ep_flags[ep_no].fifo_bank = 1; 1298 temp = AT91_UDP_CSR_RX_DATA_BK0; 1299 } 1300 } else { 1301 temp = (AT91_UDP_CSR_RX_DATA_BK0 | 1302 AT91_UDP_CSR_RX_DATA_BK1); 1303 } 1304 } else { 1305 temp = 0; 1306 } 1307 1308 /* clear FORCESTALL */ 1309 temp |= AT91_UDP_CSR_STALLSENT; 1310 1311 AT91_CSR_ACK(csr_val, temp); 1312 AT91_UDP_WRITE_4(sc, csr_reg, csr_val); 1313 } 1314 1315 /* compute default CSR value */ 1316 csr_val = 0; 1317 AT91_CSR_ACK(csr_val, 0); 1318 1319 /* enable endpoint */ 1320 csr_val &= ~AT91_UDP_CSR_ET_MASK; 1321 csr_val |= AT91_UDP_CSR_EPEDS; 1322 1323 if (ep_type == UE_CONTROL) { 1324 csr_val |= AT91_UDP_CSR_ET_CTRL; 1325 } else { 1326 if (ep_type == UE_BULK) { 1327 csr_val |= AT91_UDP_CSR_ET_BULK; 1328 } else if (ep_type == UE_INTERRUPT) { 1329 csr_val |= AT91_UDP_CSR_ET_INT; 1330 } else { 1331 csr_val |= AT91_UDP_CSR_ET_ISO; 1332 } 1333 if (ep_dir & UE_DIR_IN) { 1334 csr_val |= AT91_UDP_CSR_ET_DIR_IN; 1335 } 1336 } 1337 1338 /* enable endpoint */ 1339 AT91_UDP_WRITE_4(sc, AT91_UDP_CSR(ep_no), csr_val); 1340} 1341 1342static void 1343at91dci_clear_stall(struct usb2_device *udev, struct usb2_pipe *pipe) 1344{ 1345 struct at91dci_softc *sc; 1346 struct usb2_endpoint_descriptor *ed; 1347 1348 DPRINTFN(5, "pipe=%p\n", pipe); 1349 1350 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 1351 1352 /* check mode */ 1353 if (udev->flags.usb2_mode != USB_MODE_DEVICE) { 1354 /* not supported */ 1355 return; 1356 } 1357 /* get softc */ 1358 sc = AT9100_DCI_BUS2SC(udev->bus); 1359 1360 /* get endpoint descriptor */ 1361 ed = pipe->edesc; 1362 1363 /* reset endpoint */ 1364 at91dci_clear_stall_sub(sc, 1365 (ed->bEndpointAddress & UE_ADDR), 1366 (ed->bmAttributes & UE_XFERTYPE), 1367 (ed->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT))); 1368} 1369 1370usb2_error_t 1371at91dci_init(struct at91dci_softc *sc) 1372{ 1373 uint32_t csr_val; 1374 uint8_t n; 1375 1376 DPRINTF("start\n"); 1377 1378 /* set up the bus structure */ 1379 sc->sc_bus.usbrev = USB_REV_1_1; 1380 sc->sc_bus.methods = &at91dci_bus_methods; 1381 1382 USB_BUS_LOCK(&sc->sc_bus); 1383 1384 /* turn on clocks */ 1385 1386 if (sc->sc_clocks_on) { 1387 (sc->sc_clocks_on) (sc->sc_clocks_arg); 1388 } 1389 /* wait a little for things to stabilise */ 1390 usb2_pause_mtx(&sc->sc_bus.bus_mtx, hz / 1000); 1391 1392 /* disable and clear all interrupts */ 1393 1394 AT91_UDP_WRITE_4(sc, AT91_UDP_IDR, 0xFFFFFFFF); 1395 AT91_UDP_WRITE_4(sc, AT91_UDP_ICR, 0xFFFFFFFF); 1396 1397 /* compute default CSR value */ 1398 1399 csr_val = 0; 1400 AT91_CSR_ACK(csr_val, 0); 1401 1402 /* disable all endpoints */ 1403 1404 for (n = 0; n != AT91_UDP_EP_MAX; n++) { 1405 1406 /* disable endpoint */ 1407 AT91_UDP_WRITE_4(sc, AT91_UDP_CSR(n), csr_val); 1408 } 1409 1410 /* enable the control endpoint */ 1411 1412 AT91_CSR_ACK(csr_val, AT91_UDP_CSR_ET_CTRL | 1413 AT91_UDP_CSR_EPEDS); 1414 1415 /* write to FIFO control register */ 1416 1417 AT91_UDP_WRITE_4(sc, AT91_UDP_CSR(0), csr_val); 1418 1419 /* enable the interrupts we want */ 1420 1421 AT91_UDP_WRITE_4(sc, AT91_UDP_IER, AT91_UDP_INT_BUS); 1422 1423 /* turn off clocks */ 1424 1425 at91dci_clocks_off(sc); 1426 1427 USB_BUS_UNLOCK(&sc->sc_bus); 1428 1429 /* catch any lost interrupts */ 1430 1431 at91dci_do_poll(&sc->sc_bus); 1432 1433 return (0); /* success */ 1434} 1435 1436void 1437at91dci_uninit(struct at91dci_softc *sc) 1438{ 1439 USB_BUS_LOCK(&sc->sc_bus); 1440 1441 /* disable and clear all interrupts */ 1442 AT91_UDP_WRITE_4(sc, AT91_UDP_IDR, 0xFFFFFFFF); 1443 AT91_UDP_WRITE_4(sc, AT91_UDP_ICR, 0xFFFFFFFF); 1444 1445 sc->sc_flags.port_powered = 0; 1446 sc->sc_flags.status_vbus = 0; 1447 sc->sc_flags.status_bus_reset = 0; 1448 sc->sc_flags.status_suspend = 0; 1449 sc->sc_flags.change_suspend = 0; 1450 sc->sc_flags.change_connect = 1; 1451 1452 at91dci_pull_down(sc); 1453 at91dci_clocks_off(sc); 1454 USB_BUS_UNLOCK(&sc->sc_bus); 1455} 1456 1457void 1458at91dci_suspend(struct at91dci_softc *sc) 1459{ 1460 return; 1461} 1462 1463void 1464at91dci_resume(struct at91dci_softc *sc) 1465{ 1466 return; 1467} 1468 1469static void 1470at91dci_do_poll(struct usb2_bus *bus) 1471{ 1472 struct at91dci_softc *sc = AT9100_DCI_BUS2SC(bus); 1473 1474 USB_BUS_LOCK(&sc->sc_bus); 1475 at91dci_interrupt_poll(sc); 1476 at91dci_root_ctrl_poll(sc); 1477 USB_BUS_UNLOCK(&sc->sc_bus); 1478} 1479 1480/*------------------------------------------------------------------------* 1481 * at91dci bulk support 1482 *------------------------------------------------------------------------*/ 1483static void 1484at91dci_device_bulk_open(struct usb2_xfer *xfer) 1485{ 1486 return; 1487} 1488 1489static void 1490at91dci_device_bulk_close(struct usb2_xfer *xfer) 1491{ 1492 at91dci_device_done(xfer, USB_ERR_CANCELLED); 1493} 1494 1495static void 1496at91dci_device_bulk_enter(struct usb2_xfer *xfer) 1497{ 1498 return; 1499} 1500 1501static void 1502at91dci_device_bulk_start(struct usb2_xfer *xfer) 1503{ 1504 /* setup TDs */ 1505 at91dci_setup_standard_chain(xfer); 1506 at91dci_start_standard_chain(xfer); 1507} 1508 1509struct usb2_pipe_methods at91dci_device_bulk_methods = 1510{ 1511 .open = at91dci_device_bulk_open, 1512 .close = at91dci_device_bulk_close, 1513 .enter = at91dci_device_bulk_enter, 1514 .start = at91dci_device_bulk_start, 1515 .enter_is_cancelable = 1, 1516 .start_is_cancelable = 1, 1517}; 1518 1519/*------------------------------------------------------------------------* 1520 * at91dci control support 1521 *------------------------------------------------------------------------*/ 1522static void 1523at91dci_device_ctrl_open(struct usb2_xfer *xfer) 1524{ 1525 return; 1526} 1527 1528static void 1529at91dci_device_ctrl_close(struct usb2_xfer *xfer) 1530{ 1531 at91dci_device_done(xfer, USB_ERR_CANCELLED); 1532} 1533 1534static void 1535at91dci_device_ctrl_enter(struct usb2_xfer *xfer) 1536{ 1537 return; 1538} 1539 1540static void 1541at91dci_device_ctrl_start(struct usb2_xfer *xfer) 1542{ 1543 /* setup TDs */ 1544 at91dci_setup_standard_chain(xfer); 1545 at91dci_start_standard_chain(xfer); 1546} 1547 1548struct usb2_pipe_methods at91dci_device_ctrl_methods = 1549{ 1550 .open = at91dci_device_ctrl_open, 1551 .close = at91dci_device_ctrl_close, 1552 .enter = at91dci_device_ctrl_enter, 1553 .start = at91dci_device_ctrl_start, 1554 .enter_is_cancelable = 1, 1555 .start_is_cancelable = 1, 1556}; 1557 1558/*------------------------------------------------------------------------* 1559 * at91dci interrupt support 1560 *------------------------------------------------------------------------*/ 1561static void 1562at91dci_device_intr_open(struct usb2_xfer *xfer) 1563{ 1564 return; 1565} 1566 1567static void 1568at91dci_device_intr_close(struct usb2_xfer *xfer) 1569{ 1570 at91dci_device_done(xfer, USB_ERR_CANCELLED); 1571} 1572 1573static void 1574at91dci_device_intr_enter(struct usb2_xfer *xfer) 1575{ 1576 return; 1577} 1578 1579static void 1580at91dci_device_intr_start(struct usb2_xfer *xfer) 1581{ 1582 /* setup TDs */ 1583 at91dci_setup_standard_chain(xfer); 1584 at91dci_start_standard_chain(xfer); 1585} 1586 1587struct usb2_pipe_methods at91dci_device_intr_methods = 1588{ 1589 .open = at91dci_device_intr_open, 1590 .close = at91dci_device_intr_close, 1591 .enter = at91dci_device_intr_enter, 1592 .start = at91dci_device_intr_start, 1593 .enter_is_cancelable = 1, 1594 .start_is_cancelable = 1, 1595}; 1596 1597/*------------------------------------------------------------------------* 1598 * at91dci full speed isochronous support 1599 *------------------------------------------------------------------------*/ 1600static void 1601at91dci_device_isoc_fs_open(struct usb2_xfer *xfer) 1602{ 1603 return; 1604} 1605 1606static void 1607at91dci_device_isoc_fs_close(struct usb2_xfer *xfer) 1608{ 1609 at91dci_device_done(xfer, USB_ERR_CANCELLED); 1610} 1611 1612static void 1613at91dci_device_isoc_fs_enter(struct usb2_xfer *xfer) 1614{ 1615 struct at91dci_softc *sc = AT9100_DCI_BUS2SC(xfer->xroot->bus); 1616 uint32_t temp; 1617 uint32_t nframes; 1618 1619 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n", 1620 xfer, xfer->pipe->isoc_next, xfer->nframes); 1621 1622 /* get the current frame index */ 1623 1624 nframes = AT91_UDP_READ_4(sc, AT91_UDP_FRM); 1625 1626 /* 1627 * check if the frame index is within the window where the frames 1628 * will be inserted 1629 */ 1630 temp = (nframes - xfer->pipe->isoc_next) & AT91_UDP_FRM_MASK; 1631 1632 if ((xfer->pipe->is_synced == 0) || 1633 (temp < xfer->nframes)) { 1634 /* 1635 * If there is data underflow or the pipe queue is 1636 * empty we schedule the transfer a few frames ahead 1637 * of the current frame position. Else two isochronous 1638 * transfers might overlap. 1639 */ 1640 xfer->pipe->isoc_next = (nframes + 3) & AT91_UDP_FRM_MASK; 1641 xfer->pipe->is_synced = 1; 1642 DPRINTFN(3, "start next=%d\n", xfer->pipe->isoc_next); 1643 } 1644 /* 1645 * compute how many milliseconds the insertion is ahead of the 1646 * current frame position: 1647 */ 1648 temp = (xfer->pipe->isoc_next - nframes) & AT91_UDP_FRM_MASK; 1649 1650 /* 1651 * pre-compute when the isochronous transfer will be finished: 1652 */ 1653 xfer->isoc_time_complete = 1654 usb2_isoc_time_expand(&sc->sc_bus, nframes) + temp + 1655 xfer->nframes; 1656 1657 /* compute frame number for next insertion */ 1658 xfer->pipe->isoc_next += xfer->nframes; 1659 1660 /* setup TDs */ 1661 at91dci_setup_standard_chain(xfer); 1662} 1663 1664static void 1665at91dci_device_isoc_fs_start(struct usb2_xfer *xfer) 1666{ 1667 /* start TD chain */ 1668 at91dci_start_standard_chain(xfer); 1669} 1670 1671struct usb2_pipe_methods at91dci_device_isoc_fs_methods = 1672{ 1673 .open = at91dci_device_isoc_fs_open, 1674 .close = at91dci_device_isoc_fs_close, 1675 .enter = at91dci_device_isoc_fs_enter, 1676 .start = at91dci_device_isoc_fs_start, 1677 .enter_is_cancelable = 1, 1678 .start_is_cancelable = 1, 1679}; 1680 1681/*------------------------------------------------------------------------* 1682 * at91dci root control support 1683 *------------------------------------------------------------------------* 1684 * simulate a hardware HUB by handling 1685 * all the necessary requests 1686 *------------------------------------------------------------------------*/ 1687 1688static void 1689at91dci_root_ctrl_open(struct usb2_xfer *xfer) 1690{ 1691 return; 1692} 1693 1694static void 1695at91dci_root_ctrl_close(struct usb2_xfer *xfer) 1696{ 1697 struct at91dci_softc *sc = AT9100_DCI_BUS2SC(xfer->xroot->bus); 1698 1699 if (sc->sc_root_ctrl.xfer == xfer) { 1700 sc->sc_root_ctrl.xfer = NULL; 1701 } 1702 at91dci_device_done(xfer, USB_ERR_CANCELLED); 1703} 1704 1705/* 1706 * USB descriptors for the virtual Root HUB: 1707 */ 1708 1709static const struct usb2_device_descriptor at91dci_devd = { 1710 .bLength = sizeof(struct usb2_device_descriptor), 1711 .bDescriptorType = UDESC_DEVICE, 1712 .bcdUSB = {0x00, 0x02}, 1713 .bDeviceClass = UDCLASS_HUB, 1714 .bDeviceSubClass = UDSUBCLASS_HUB, 1715 .bDeviceProtocol = UDPROTO_HSHUBSTT, 1716 .bMaxPacketSize = 64, 1717 .bcdDevice = {0x00, 0x01}, 1718 .iManufacturer = 1, 1719 .iProduct = 2, 1720 .bNumConfigurations = 1, 1721}; 1722 1723static const struct usb2_device_qualifier at91dci_odevd = { 1724 .bLength = sizeof(struct usb2_device_qualifier), 1725 .bDescriptorType = UDESC_DEVICE_QUALIFIER, 1726 .bcdUSB = {0x00, 0x02}, 1727 .bDeviceClass = UDCLASS_HUB, 1728 .bDeviceSubClass = UDSUBCLASS_HUB, 1729 .bDeviceProtocol = UDPROTO_FSHUB, 1730 .bMaxPacketSize0 = 0, 1731 .bNumConfigurations = 0, 1732}; 1733 1734static const struct at91dci_config_desc at91dci_confd = { 1735 .confd = { 1736 .bLength = sizeof(struct usb2_config_descriptor), 1737 .bDescriptorType = UDESC_CONFIG, 1738 .wTotalLength[0] = sizeof(at91dci_confd), 1739 .bNumInterface = 1, 1740 .bConfigurationValue = 1, 1741 .iConfiguration = 0, 1742 .bmAttributes = UC_SELF_POWERED, 1743 .bMaxPower = 0, 1744 }, 1745 .ifcd = { 1746 .bLength = sizeof(struct usb2_interface_descriptor), 1747 .bDescriptorType = UDESC_INTERFACE, 1748 .bNumEndpoints = 1, 1749 .bInterfaceClass = UICLASS_HUB, 1750 .bInterfaceSubClass = UISUBCLASS_HUB, 1751 .bInterfaceProtocol = UIPROTO_HSHUBSTT, 1752 }, 1753 1754 .endpd = { 1755 .bLength = sizeof(struct usb2_endpoint_descriptor), 1756 .bDescriptorType = UDESC_ENDPOINT, 1757 .bEndpointAddress = (UE_DIR_IN | AT9100_DCI_INTR_ENDPT), 1758 .bmAttributes = UE_INTERRUPT, 1759 .wMaxPacketSize[0] = 8, 1760 .bInterval = 255, 1761 }, 1762}; 1763 1764static const struct usb2_hub_descriptor_min at91dci_hubd = { 1765 .bDescLength = sizeof(at91dci_hubd), 1766 .bDescriptorType = UDESC_HUB, 1767 .bNbrPorts = 1, 1768 .wHubCharacteristics[0] = 1769 (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL) & 0xFF, 1770 .wHubCharacteristics[1] = 1771 (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL) >> 8, 1772 .bPwrOn2PwrGood = 50, 1773 .bHubContrCurrent = 0, 1774 .DeviceRemovable = {0}, /* port is removable */ 1775}; 1776 1777#define STRING_LANG \ 1778 0x09, 0x04, /* American English */ 1779 1780#define STRING_VENDOR \ 1781 'A', 0, 'T', 0, 'M', 0, 'E', 0, 'L', 0 1782 1783#define STRING_PRODUCT \ 1784 'D', 0, 'C', 0, 'I', 0, ' ', 0, 'R', 0, \ 1785 'o', 0, 'o', 0, 't', 0, ' ', 0, 'H', 0, \ 1786 'U', 0, 'B', 0, 1787 1788USB_MAKE_STRING_DESC(STRING_LANG, at91dci_langtab); 1789USB_MAKE_STRING_DESC(STRING_VENDOR, at91dci_vendor); 1790USB_MAKE_STRING_DESC(STRING_PRODUCT, at91dci_product); 1791 1792static void 1793at91dci_root_ctrl_enter(struct usb2_xfer *xfer) 1794{ 1795 return; 1796} 1797 1798static void 1799at91dci_root_ctrl_start(struct usb2_xfer *xfer) 1800{ 1801 struct at91dci_softc *sc = AT9100_DCI_BUS2SC(xfer->xroot->bus); 1802 1803 sc->sc_root_ctrl.xfer = xfer; 1804 1805 usb2_bus_roothub_exec(xfer->xroot->bus); 1806} 1807 1808static void 1809at91dci_root_ctrl_task(struct usb2_bus *bus) 1810{ 1811 at91dci_root_ctrl_poll(AT9100_DCI_BUS2SC(bus)); 1812} 1813 1814static void 1815at91dci_root_ctrl_done(struct usb2_xfer *xfer, 1816 struct usb2_sw_transfer *std) 1817{ 1818 struct at91dci_softc *sc = AT9100_DCI_BUS2SC(xfer->xroot->bus); 1819 uint16_t value; 1820 uint16_t index; 1821 1822 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1823 1824 if (std->state != USB_SW_TR_SETUP) { 1825 if (std->state == USB_SW_TR_PRE_CALLBACK) { 1826 /* transfer transferred */ 1827 at91dci_device_done(xfer, std->err); 1828 } 1829 goto done; 1830 } 1831 /* buffer reset */ 1832 std->ptr = USB_ADD_BYTES(&sc->sc_hub_temp, 0); 1833 std->len = 0; 1834 1835 value = UGETW(std->req.wValue); 1836 index = UGETW(std->req.wIndex); 1837 1838 /* demultiplex the control request */ 1839 1840 switch (std->req.bmRequestType) { 1841 case UT_READ_DEVICE: 1842 switch (std->req.bRequest) { 1843 case UR_GET_DESCRIPTOR: 1844 goto tr_handle_get_descriptor; 1845 case UR_GET_CONFIG: 1846 goto tr_handle_get_config; 1847 case UR_GET_STATUS: 1848 goto tr_handle_get_status; 1849 default: 1850 goto tr_stalled; 1851 } 1852 break; 1853 1854 case UT_WRITE_DEVICE: 1855 switch (std->req.bRequest) { 1856 case UR_SET_ADDRESS: 1857 goto tr_handle_set_address; 1858 case UR_SET_CONFIG: 1859 goto tr_handle_set_config; 1860 case UR_CLEAR_FEATURE: 1861 goto tr_valid; /* nop */ 1862 case UR_SET_DESCRIPTOR: 1863 goto tr_valid; /* nop */ 1864 case UR_SET_FEATURE: 1865 default: 1866 goto tr_stalled; 1867 } 1868 break; 1869 1870 case UT_WRITE_ENDPOINT: 1871 switch (std->req.bRequest) { 1872 case UR_CLEAR_FEATURE: 1873 switch (UGETW(std->req.wValue)) { 1874 case UF_ENDPOINT_HALT: 1875 goto tr_handle_clear_halt; 1876 case UF_DEVICE_REMOTE_WAKEUP: 1877 goto tr_handle_clear_wakeup; 1878 default: 1879 goto tr_stalled; 1880 } 1881 break; 1882 case UR_SET_FEATURE: 1883 switch (UGETW(std->req.wValue)) { 1884 case UF_ENDPOINT_HALT: 1885 goto tr_handle_set_halt; 1886 case UF_DEVICE_REMOTE_WAKEUP: 1887 goto tr_handle_set_wakeup; 1888 default: 1889 goto tr_stalled; 1890 } 1891 break; 1892 case UR_SYNCH_FRAME: 1893 goto tr_valid; /* nop */ 1894 default: 1895 goto tr_stalled; 1896 } 1897 break; 1898 1899 case UT_READ_ENDPOINT: 1900 switch (std->req.bRequest) { 1901 case UR_GET_STATUS: 1902 goto tr_handle_get_ep_status; 1903 default: 1904 goto tr_stalled; 1905 } 1906 break; 1907 1908 case UT_WRITE_INTERFACE: 1909 switch (std->req.bRequest) { 1910 case UR_SET_INTERFACE: 1911 goto tr_handle_set_interface; 1912 case UR_CLEAR_FEATURE: 1913 goto tr_valid; /* nop */ 1914 case UR_SET_FEATURE: 1915 default: 1916 goto tr_stalled; 1917 } 1918 break; 1919 1920 case UT_READ_INTERFACE: 1921 switch (std->req.bRequest) { 1922 case UR_GET_INTERFACE: 1923 goto tr_handle_get_interface; 1924 case UR_GET_STATUS: 1925 goto tr_handle_get_iface_status; 1926 default: 1927 goto tr_stalled; 1928 } 1929 break; 1930 1931 case UT_WRITE_CLASS_INTERFACE: 1932 case UT_WRITE_VENDOR_INTERFACE: 1933 /* XXX forward */ 1934 break; 1935 1936 case UT_READ_CLASS_INTERFACE: 1937 case UT_READ_VENDOR_INTERFACE: 1938 /* XXX forward */ 1939 break; 1940 1941 case UT_WRITE_CLASS_DEVICE: 1942 switch (std->req.bRequest) { 1943 case UR_CLEAR_FEATURE: 1944 goto tr_valid; 1945 case UR_SET_DESCRIPTOR: 1946 case UR_SET_FEATURE: 1947 break; 1948 default: 1949 goto tr_stalled; 1950 } 1951 break; 1952 1953 case UT_WRITE_CLASS_OTHER: 1954 switch (std->req.bRequest) { 1955 case UR_CLEAR_FEATURE: 1956 goto tr_handle_clear_port_feature; 1957 case UR_SET_FEATURE: 1958 goto tr_handle_set_port_feature; 1959 case UR_CLEAR_TT_BUFFER: 1960 case UR_RESET_TT: 1961 case UR_STOP_TT: 1962 goto tr_valid; 1963 1964 default: 1965 goto tr_stalled; 1966 } 1967 break; 1968 1969 case UT_READ_CLASS_OTHER: 1970 switch (std->req.bRequest) { 1971 case UR_GET_TT_STATE: 1972 goto tr_handle_get_tt_state; 1973 case UR_GET_STATUS: 1974 goto tr_handle_get_port_status; 1975 default: 1976 goto tr_stalled; 1977 } 1978 break; 1979 1980 case UT_READ_CLASS_DEVICE: 1981 switch (std->req.bRequest) { 1982 case UR_GET_DESCRIPTOR: 1983 goto tr_handle_get_class_descriptor; 1984 case UR_GET_STATUS: 1985 goto tr_handle_get_class_status; 1986 1987 default: 1988 goto tr_stalled; 1989 } 1990 break; 1991 default: 1992 goto tr_stalled; 1993 } 1994 goto tr_valid; 1995 1996tr_handle_get_descriptor: 1997 switch (value >> 8) { 1998 case UDESC_DEVICE: 1999 if (value & 0xff) { 2000 goto tr_stalled; 2001 } 2002 std->len = sizeof(at91dci_devd); 2003 std->ptr = USB_ADD_BYTES(&at91dci_devd, 0); 2004 goto tr_valid; 2005 case UDESC_CONFIG: 2006 if (value & 0xff) { 2007 goto tr_stalled; 2008 } 2009 std->len = sizeof(at91dci_confd); 2010 std->ptr = USB_ADD_BYTES(&at91dci_confd, 0); 2011 goto tr_valid; 2012 case UDESC_STRING: 2013 switch (value & 0xff) { 2014 case 0: /* Language table */ 2015 std->len = sizeof(at91dci_langtab); 2016 std->ptr = USB_ADD_BYTES(&at91dci_langtab, 0); 2017 goto tr_valid; 2018 2019 case 1: /* Vendor */ 2020 std->len = sizeof(at91dci_vendor); 2021 std->ptr = USB_ADD_BYTES(&at91dci_vendor, 0); 2022 goto tr_valid; 2023 2024 case 2: /* Product */ 2025 std->len = sizeof(at91dci_product); 2026 std->ptr = USB_ADD_BYTES(&at91dci_product, 0); 2027 goto tr_valid; 2028 default: 2029 break; 2030 } 2031 break; 2032 default: 2033 goto tr_stalled; 2034 } 2035 goto tr_stalled; 2036 2037tr_handle_get_config: 2038 std->len = 1; 2039 sc->sc_hub_temp.wValue[0] = sc->sc_conf; 2040 goto tr_valid; 2041 2042tr_handle_get_status: 2043 std->len = 2; 2044 USETW(sc->sc_hub_temp.wValue, UDS_SELF_POWERED); 2045 goto tr_valid; 2046 2047tr_handle_set_address: 2048 if (value & 0xFF00) { 2049 goto tr_stalled; 2050 } 2051 sc->sc_rt_addr = value; 2052 goto tr_valid; 2053 2054tr_handle_set_config: 2055 if (value >= 2) { 2056 goto tr_stalled; 2057 } 2058 sc->sc_conf = value; 2059 goto tr_valid; 2060 2061tr_handle_get_interface: 2062 std->len = 1; 2063 sc->sc_hub_temp.wValue[0] = 0; 2064 goto tr_valid; 2065 2066tr_handle_get_tt_state: 2067tr_handle_get_class_status: 2068tr_handle_get_iface_status: 2069tr_handle_get_ep_status: 2070 std->len = 2; 2071 USETW(sc->sc_hub_temp.wValue, 0); 2072 goto tr_valid; 2073 2074tr_handle_set_halt: 2075tr_handle_set_interface: 2076tr_handle_set_wakeup: 2077tr_handle_clear_wakeup: 2078tr_handle_clear_halt: 2079 goto tr_valid; 2080 2081tr_handle_clear_port_feature: 2082 if (index != 1) { 2083 goto tr_stalled; 2084 } 2085 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE on port %d\n", index); 2086 2087 switch (value) { 2088 case UHF_PORT_SUSPEND: 2089 at91dci_wakeup_peer(xfer); 2090 break; 2091 2092 case UHF_PORT_ENABLE: 2093 sc->sc_flags.port_enabled = 0; 2094 break; 2095 2096 case UHF_PORT_TEST: 2097 case UHF_PORT_INDICATOR: 2098 case UHF_C_PORT_ENABLE: 2099 case UHF_C_PORT_OVER_CURRENT: 2100 case UHF_C_PORT_RESET: 2101 /* nops */ 2102 break; 2103 case UHF_PORT_POWER: 2104 sc->sc_flags.port_powered = 0; 2105 at91dci_pull_down(sc); 2106 at91dci_clocks_off(sc); 2107 break; 2108 case UHF_C_PORT_CONNECTION: 2109 sc->sc_flags.change_connect = 0; 2110 break; 2111 case UHF_C_PORT_SUSPEND: 2112 sc->sc_flags.change_suspend = 0; 2113 break; 2114 default: 2115 std->err = USB_ERR_IOERROR; 2116 goto done; 2117 } 2118 goto tr_valid; 2119 2120tr_handle_set_port_feature: 2121 if (index != 1) { 2122 goto tr_stalled; 2123 } 2124 DPRINTFN(9, "UR_SET_PORT_FEATURE\n"); 2125 2126 switch (value) { 2127 case UHF_PORT_ENABLE: 2128 sc->sc_flags.port_enabled = 1; 2129 break; 2130 case UHF_PORT_SUSPEND: 2131 case UHF_PORT_RESET: 2132 case UHF_PORT_TEST: 2133 case UHF_PORT_INDICATOR: 2134 /* nops */ 2135 break; 2136 case UHF_PORT_POWER: 2137 sc->sc_flags.port_powered = 1; 2138 break; 2139 default: 2140 std->err = USB_ERR_IOERROR; 2141 goto done; 2142 } 2143 goto tr_valid; 2144 2145tr_handle_get_port_status: 2146 2147 DPRINTFN(9, "UR_GET_PORT_STATUS\n"); 2148 2149 if (index != 1) { 2150 goto tr_stalled; 2151 } 2152 if (sc->sc_flags.status_vbus) { 2153 at91dci_clocks_on(sc); 2154 at91dci_pull_up(sc); 2155 } else { 2156 at91dci_pull_down(sc); 2157 at91dci_clocks_off(sc); 2158 } 2159 2160 /* Select FULL-speed and Device Side Mode */ 2161 2162 value = UPS_PORT_MODE_DEVICE; 2163 2164 if (sc->sc_flags.port_powered) { 2165 value |= UPS_PORT_POWER; 2166 } 2167 if (sc->sc_flags.port_enabled) { 2168 value |= UPS_PORT_ENABLED; 2169 } 2170 if (sc->sc_flags.status_vbus && 2171 sc->sc_flags.status_bus_reset) { 2172 value |= UPS_CURRENT_CONNECT_STATUS; 2173 } 2174 if (sc->sc_flags.status_suspend) { 2175 value |= UPS_SUSPEND; 2176 } 2177 USETW(sc->sc_hub_temp.ps.wPortStatus, value); 2178 2179 value = 0; 2180 2181 if (sc->sc_flags.change_connect) { 2182 value |= UPS_C_CONNECT_STATUS; 2183 2184 if (sc->sc_flags.status_vbus && 2185 sc->sc_flags.status_bus_reset) { 2186 /* reset endpoint flags */ 2187 bzero(sc->sc_ep_flags, sizeof(sc->sc_ep_flags)); 2188 } 2189 } 2190 if (sc->sc_flags.change_suspend) { 2191 value |= UPS_C_SUSPEND; 2192 } 2193 USETW(sc->sc_hub_temp.ps.wPortChange, value); 2194 std->len = sizeof(sc->sc_hub_temp.ps); 2195 goto tr_valid; 2196 2197tr_handle_get_class_descriptor: 2198 if (value & 0xFF) { 2199 goto tr_stalled; 2200 } 2201 std->ptr = USB_ADD_BYTES(&at91dci_hubd, 0); 2202 std->len = sizeof(at91dci_hubd); 2203 goto tr_valid; 2204 2205tr_stalled: 2206 std->err = USB_ERR_STALLED; 2207tr_valid: 2208done: 2209 return; 2210} 2211 2212static void 2213at91dci_root_ctrl_poll(struct at91dci_softc *sc) 2214{ 2215 usb2_sw_transfer(&sc->sc_root_ctrl, 2216 &at91dci_root_ctrl_done); 2217} 2218 2219struct usb2_pipe_methods at91dci_root_ctrl_methods = 2220{ 2221 .open = at91dci_root_ctrl_open, 2222 .close = at91dci_root_ctrl_close, 2223 .enter = at91dci_root_ctrl_enter, 2224 .start = at91dci_root_ctrl_start, 2225 .enter_is_cancelable = 1, 2226 .start_is_cancelable = 0, 2227}; 2228 2229/*------------------------------------------------------------------------* 2230 * at91dci root interrupt support 2231 *------------------------------------------------------------------------*/ 2232static void 2233at91dci_root_intr_open(struct usb2_xfer *xfer) 2234{ 2235 return; 2236} 2237 2238static void 2239at91dci_root_intr_close(struct usb2_xfer *xfer) 2240{ 2241 struct at91dci_softc *sc = AT9100_DCI_BUS2SC(xfer->xroot->bus); 2242 2243 if (sc->sc_root_intr.xfer == xfer) { 2244 sc->sc_root_intr.xfer = NULL; 2245 } 2246 at91dci_device_done(xfer, USB_ERR_CANCELLED); 2247} 2248 2249static void 2250at91dci_root_intr_enter(struct usb2_xfer *xfer) 2251{ 2252 return; 2253} 2254 2255static void 2256at91dci_root_intr_start(struct usb2_xfer *xfer) 2257{ 2258 struct at91dci_softc *sc = AT9100_DCI_BUS2SC(xfer->xroot->bus); 2259 2260 sc->sc_root_intr.xfer = xfer; 2261} 2262 2263struct usb2_pipe_methods at91dci_root_intr_methods = 2264{ 2265 .open = at91dci_root_intr_open, 2266 .close = at91dci_root_intr_close, 2267 .enter = at91dci_root_intr_enter, 2268 .start = at91dci_root_intr_start, 2269 .enter_is_cancelable = 1, 2270 .start_is_cancelable = 1, 2271}; 2272 2273static void 2274at91dci_xfer_setup(struct usb2_setup_params *parm) 2275{ 2276 const struct usb2_hw_ep_profile *pf; 2277 struct at91dci_softc *sc; 2278 struct usb2_xfer *xfer; 2279 void *last_obj; 2280 uint32_t ntd; 2281 uint32_t n; 2282 uint8_t ep_no; 2283 2284 sc = AT9100_DCI_BUS2SC(parm->udev->bus); 2285 xfer = parm->curr_xfer; 2286 2287 /* 2288 * NOTE: This driver does not use any of the parameters that 2289 * are computed from the following values. Just set some 2290 * reasonable dummies: 2291 */ 2292 parm->hc_max_packet_size = 0x500; 2293 parm->hc_max_packet_count = 1; 2294 parm->hc_max_frame_size = 0x500; 2295 2296 usb2_transfer_setup_sub(parm); 2297 2298 /* 2299 * compute maximum number of TDs 2300 */ 2301 if (parm->methods == &at91dci_device_ctrl_methods) { 2302 2303 ntd = xfer->nframes + 1 /* STATUS */ + 1 /* SYNC 1 */ 2304 + 1 /* SYNC 2 */ ; 2305 2306 } else if (parm->methods == &at91dci_device_bulk_methods) { 2307 2308 ntd = xfer->nframes + 1 /* SYNC */ ; 2309 2310 } else if (parm->methods == &at91dci_device_intr_methods) { 2311 2312 ntd = xfer->nframes + 1 /* SYNC */ ; 2313 2314 } else if (parm->methods == &at91dci_device_isoc_fs_methods) { 2315 2316 ntd = xfer->nframes + 1 /* SYNC */ ; 2317 2318 } else { 2319 2320 ntd = 0; 2321 } 2322 2323 /* 2324 * check if "usb2_transfer_setup_sub" set an error 2325 */ 2326 if (parm->err) { 2327 return; 2328 } 2329 /* 2330 * allocate transfer descriptors 2331 */ 2332 last_obj = NULL; 2333 2334 /* 2335 * get profile stuff 2336 */ 2337 if (ntd) { 2338 2339 ep_no = xfer->endpoint & UE_ADDR; 2340 at91dci_get_hw_ep_profile(parm->udev, &pf, ep_no); 2341 2342 if (pf == NULL) { 2343 /* should not happen */ 2344 parm->err = USB_ERR_INVAL; 2345 return; 2346 } 2347 } else { 2348 ep_no = 0; 2349 pf = NULL; 2350 } 2351 2352 /* align data */ 2353 parm->size[0] += ((-parm->size[0]) & (USB_HOST_ALIGN - 1)); 2354 2355 for (n = 0; n != ntd; n++) { 2356 2357 struct at91dci_td *td; 2358 2359 if (parm->buf) { 2360 2361 td = USB_ADD_BYTES(parm->buf, parm->size[0]); 2362 2363 /* init TD */ 2364 td->io_tag = sc->sc_io_tag; 2365 td->io_hdl = sc->sc_io_hdl; 2366 td->max_packet_size = xfer->max_packet_size; 2367 td->status_reg = AT91_UDP_CSR(ep_no); 2368 td->fifo_reg = AT91_UDP_FDR(ep_no); 2369 if (pf->support_multi_buffer) { 2370 td->support_multi_buffer = 1; 2371 } 2372 td->obj_next = last_obj; 2373 2374 last_obj = td; 2375 } 2376 parm->size[0] += sizeof(*td); 2377 } 2378 2379 xfer->td_start[0] = last_obj; 2380} 2381 2382static void 2383at91dci_xfer_unsetup(struct usb2_xfer *xfer) 2384{ 2385 return; 2386} 2387 2388static void 2389at91dci_pipe_init(struct usb2_device *udev, struct usb2_endpoint_descriptor *edesc, 2390 struct usb2_pipe *pipe) 2391{ 2392 struct at91dci_softc *sc = AT9100_DCI_BUS2SC(udev->bus); 2393 2394 DPRINTFN(2, "pipe=%p, addr=%d, endpt=%d, mode=%d (%d)\n", 2395 pipe, udev->address, 2396 edesc->bEndpointAddress, udev->flags.usb2_mode, 2397 sc->sc_rt_addr); 2398 2399 if (udev->device_index == sc->sc_rt_addr) { 2400 2401 if (udev->flags.usb2_mode != USB_MODE_HOST) { 2402 /* not supported */ 2403 return; 2404 } 2405 switch (edesc->bEndpointAddress) { 2406 case USB_CONTROL_ENDPOINT: 2407 pipe->methods = &at91dci_root_ctrl_methods; 2408 break; 2409 case UE_DIR_IN | AT9100_DCI_INTR_ENDPT: 2410 pipe->methods = &at91dci_root_intr_methods; 2411 break; 2412 default: 2413 /* do nothing */ 2414 break; 2415 } 2416 } else { 2417 2418 if (udev->flags.usb2_mode != USB_MODE_DEVICE) { 2419 /* not supported */ 2420 return; 2421 } 2422 if (udev->speed != USB_SPEED_FULL) { 2423 /* not supported */ 2424 return; 2425 } 2426 switch (edesc->bmAttributes & UE_XFERTYPE) { 2427 case UE_CONTROL: 2428 pipe->methods = &at91dci_device_ctrl_methods; 2429 break; 2430 case UE_INTERRUPT: 2431 pipe->methods = &at91dci_device_intr_methods; 2432 break; 2433 case UE_ISOCHRONOUS: 2434 pipe->methods = &at91dci_device_isoc_fs_methods; 2435 break; 2436 case UE_BULK: 2437 pipe->methods = &at91dci_device_bulk_methods; 2438 break; 2439 default: 2440 /* do nothing */ 2441 break; 2442 } 2443 } 2444} 2445 2446struct usb2_bus_methods at91dci_bus_methods = 2447{ 2448 .pipe_init = &at91dci_pipe_init, 2449 .xfer_setup = &at91dci_xfer_setup, 2450 .xfer_unsetup = &at91dci_xfer_unsetup, 2451 .get_hw_ep_profile = &at91dci_get_hw_ep_profile, 2452 .set_stall = &at91dci_set_stall, 2453 .clear_stall = &at91dci_clear_stall, 2454 .roothub_exec = &at91dci_root_ctrl_task, 2455}; 2456