at91dci.c revision 186454
1#include <sys/cdefs.h> 2__FBSDID("$FreeBSD: head/sys/dev/usb2/controller/at91dci.c 186454 2008-12-23 19:59:21Z thompsa $"); 3 4/*- 5 * Copyright (c) 2007-2008 Hans Petter Selasky. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29/* 30 * This file contains the driver for the AT91 series USB Device 31 * Controller 32 */ 33 34/* 35 * Thanks to "David Brownell" for helping out regarding the hardware 36 * endpoint profiles. 37 */ 38 39/* 40 * NOTE: The "fifo_bank" is not reset in hardware when the endpoint is 41 * reset ! 42 * 43 * NOTE: When the chip detects BUS-reset it will also reset the 44 * endpoints, Function-address and more. 45 */ 46 47#include <dev/usb2/include/usb2_standard.h> 48#include <dev/usb2/include/usb2_mfunc.h> 49#include <dev/usb2/include/usb2_error.h> 50#include <dev/usb2/include/usb2_defs.h> 51 52#define USB_DEBUG_VAR at91dcidebug 53#define usb2_config_td_cc at91dci_config_copy 54#define usb2_config_td_softc at91dci_softc 55 56#include <dev/usb2/core/usb2_core.h> 57#include <dev/usb2/core/usb2_debug.h> 58#include <dev/usb2/core/usb2_busdma.h> 59#include <dev/usb2/core/usb2_process.h> 60#include <dev/usb2/core/usb2_config_td.h> 61#include <dev/usb2/core/usb2_sw_transfer.h> 62#include <dev/usb2/core/usb2_transfer.h> 63#include <dev/usb2/core/usb2_device.h> 64#include <dev/usb2/core/usb2_hub.h> 65#include <dev/usb2/core/usb2_util.h> 66 67#include <dev/usb2/controller/usb2_controller.h> 68#include <dev/usb2/controller/usb2_bus.h> 69#include <dev/usb2/controller/at91dci.h> 70 71#define AT9100_DCI_BUS2SC(bus) \ 72 ((struct at91dci_softc *)(((uint8_t *)(bus)) - \ 73 USB_P2U(&(((struct at91dci_softc *)0)->sc_bus)))) 74 75#define AT9100_DCI_PC2SC(pc) \ 76 AT9100_DCI_BUS2SC((pc)->tag_parent->info->bus) 77 78#if USB_DEBUG 79static int at91dcidebug = 0; 80 81SYSCTL_NODE(_hw_usb2, OID_AUTO, at91dci, CTLFLAG_RW, 0, "USB at91dci"); 82SYSCTL_INT(_hw_usb2_at91dci, OID_AUTO, debug, CTLFLAG_RW, 83 &at91dcidebug, 0, "at91dci debug level"); 84#endif 85 86#define AT9100_DCI_INTR_ENDPT 1 87 88/* prototypes */ 89 90struct usb2_bus_methods at91dci_bus_methods; 91struct usb2_pipe_methods at91dci_device_bulk_methods; 92struct usb2_pipe_methods at91dci_device_ctrl_methods; 93struct usb2_pipe_methods at91dci_device_intr_methods; 94struct usb2_pipe_methods at91dci_device_isoc_fs_methods; 95struct usb2_pipe_methods at91dci_root_ctrl_methods; 96struct usb2_pipe_methods at91dci_root_intr_methods; 97 98static at91dci_cmd_t at91dci_setup_rx; 99static at91dci_cmd_t at91dci_data_rx; 100static at91dci_cmd_t at91dci_data_tx; 101static at91dci_cmd_t at91dci_data_tx_sync; 102static void at91dci_device_done(struct usb2_xfer *, usb2_error_t); 103static void at91dci_do_poll(struct usb2_bus *); 104static void at91dci_root_ctrl_poll(struct at91dci_softc *); 105static void at91dci_standard_done(struct usb2_xfer *); 106 107static usb2_sw_transfer_func_t at91dci_root_intr_done; 108static usb2_sw_transfer_func_t at91dci_root_ctrl_done; 109static usb2_config_td_command_t at91dci_root_ctrl_task; 110 111/* 112 * NOTE: Some of the bits in the CSR register have inverse meaning so 113 * we need a helper macro when acknowledging events: 114 */ 115#define AT91_CSR_ACK(csr, what) do { \ 116 (csr) &= ~((AT91_UDP_CSR_FORCESTALL| \ 117 AT91_UDP_CSR_TXPKTRDY| \ 118 AT91_UDP_CSR_RXBYTECNT) ^ (what));\ 119 (csr) |= ((AT91_UDP_CSR_RX_DATA_BK0| \ 120 AT91_UDP_CSR_RX_DATA_BK1| \ 121 AT91_UDP_CSR_TXCOMP| \ 122 AT91_UDP_CSR_RXSETUP| \ 123 AT91_UDP_CSR_STALLSENT) ^ (what)); \ 124} while (0) 125 126/* 127 * Here is a list of what the chip supports. 128 * Probably it supports more than listed here! 129 */ 130static const struct usb2_hw_ep_profile 131 at91dci_ep_profile[AT91_UDP_EP_MAX] = { 132 133 [0] = { 134 .max_in_frame_size = 8, 135 .max_out_frame_size = 8, 136 .is_simplex = 1, 137 .support_control = 1, 138 }, 139 [1] = { 140 .max_in_frame_size = 64, 141 .max_out_frame_size = 64, 142 .is_simplex = 1, 143 .support_multi_buffer = 1, 144 .support_bulk = 1, 145 .support_interrupt = 1, 146 .support_isochronous = 1, 147 .support_in = 1, 148 .support_out = 1, 149 }, 150 [2] = { 151 .max_in_frame_size = 64, 152 .max_out_frame_size = 64, 153 .is_simplex = 1, 154 .support_multi_buffer = 1, 155 .support_bulk = 1, 156 .support_interrupt = 1, 157 .support_isochronous = 1, 158 .support_in = 1, 159 .support_out = 1, 160 }, 161 [3] = { 162 /* can also do BULK */ 163 .max_in_frame_size = 8, 164 .max_out_frame_size = 8, 165 .is_simplex = 1, 166 .support_interrupt = 1, 167 .support_in = 1, 168 .support_out = 1, 169 }, 170 [4] = { 171 .max_in_frame_size = 256, 172 .max_out_frame_size = 256, 173 .is_simplex = 1, 174 .support_multi_buffer = 1, 175 .support_bulk = 1, 176 .support_interrupt = 1, 177 .support_isochronous = 1, 178 .support_in = 1, 179 .support_out = 1, 180 }, 181 [5] = { 182 .max_in_frame_size = 256, 183 .max_out_frame_size = 256, 184 .is_simplex = 1, 185 .support_multi_buffer = 1, 186 .support_bulk = 1, 187 .support_interrupt = 1, 188 .support_isochronous = 1, 189 .support_in = 1, 190 .support_out = 1, 191 }, 192}; 193 194static void 195at91dci_get_hw_ep_profile(struct usb2_device *udev, 196 const struct usb2_hw_ep_profile **ppf, uint8_t ep_addr) 197{ 198 if (ep_addr < AT91_UDP_EP_MAX) { 199 *ppf = (at91dci_ep_profile + ep_addr); 200 } else { 201 *ppf = NULL; 202 } 203} 204 205static void 206at91dci_clocks_on(struct at91dci_softc *sc) 207{ 208 if (sc->sc_flags.clocks_off && 209 sc->sc_flags.port_powered) { 210 211 DPRINTFN(5, "\n"); 212 213 if (sc->sc_clocks_on) { 214 (sc->sc_clocks_on) (sc->sc_clocks_arg); 215 } 216 sc->sc_flags.clocks_off = 0; 217 218 /* enable Transceiver */ 219 AT91_UDP_WRITE_4(sc, AT91_UDP_TXVC, 0); 220 } 221} 222 223static void 224at91dci_clocks_off(struct at91dci_softc *sc) 225{ 226 if (!sc->sc_flags.clocks_off) { 227 228 DPRINTFN(5, "\n"); 229 230 /* disable Transceiver */ 231 AT91_UDP_WRITE_4(sc, AT91_UDP_TXVC, AT91_UDP_TXVC_DIS); 232 233 if (sc->sc_clocks_off) { 234 (sc->sc_clocks_off) (sc->sc_clocks_arg); 235 } 236 sc->sc_flags.clocks_off = 1; 237 } 238} 239 240static void 241at91dci_pull_up(struct at91dci_softc *sc) 242{ 243 /* pullup D+, if possible */ 244 245 if (!sc->sc_flags.d_pulled_up && 246 sc->sc_flags.port_powered) { 247 sc->sc_flags.d_pulled_up = 1; 248 (sc->sc_pull_up) (sc->sc_pull_arg); 249 } 250} 251 252static void 253at91dci_pull_down(struct at91dci_softc *sc) 254{ 255 /* pulldown D+, if possible */ 256 257 if (sc->sc_flags.d_pulled_up) { 258 sc->sc_flags.d_pulled_up = 0; 259 (sc->sc_pull_down) (sc->sc_pull_arg); 260 } 261} 262 263static void 264at91dci_wakeup_peer(struct at91dci_softc *sc) 265{ 266 uint32_t temp; 267 268 if (!(sc->sc_flags.status_suspend)) { 269 return; 270 } 271 temp = AT91_UDP_READ_4(sc, AT91_UDP_GSTATE); 272 273 if (!(temp & AT91_UDP_GSTATE_ESR)) { 274 return; 275 } 276 AT91_UDP_WRITE_4(sc, AT91_UDP_GSTATE, temp); 277} 278 279static void 280at91dci_rem_wakeup_set(struct usb2_device *udev, uint8_t is_on) 281{ 282 struct at91dci_softc *sc; 283 uint32_t temp; 284 285 DPRINTFN(5, "is_on=%u\n", is_on); 286 287 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 288 289 sc = AT9100_DCI_BUS2SC(udev->bus); 290 291 temp = AT91_UDP_READ_4(sc, AT91_UDP_GSTATE); 292 293 if (is_on) { 294 temp |= AT91_UDP_GSTATE_ESR; 295 } else { 296 temp &= ~AT91_UDP_GSTATE_ESR; 297 } 298 299 AT91_UDP_WRITE_4(sc, AT91_UDP_GSTATE, temp); 300} 301 302static void 303at91dci_set_address(struct at91dci_softc *sc, uint8_t addr) 304{ 305 DPRINTFN(5, "addr=%d\n", addr); 306 307 AT91_UDP_WRITE_4(sc, AT91_UDP_FADDR, addr | 308 AT91_UDP_FADDR_EN); 309} 310 311static uint8_t 312at91dci_setup_rx(struct at91dci_td *td) 313{ 314 struct at91dci_softc *sc; 315 struct usb2_device_request req; 316 uint32_t csr; 317 uint32_t temp; 318 uint16_t count; 319 320 /* read out FIFO status */ 321 csr = bus_space_read_4(td->io_tag, td->io_hdl, 322 td->status_reg); 323 324 DPRINTFN(5, "csr=0x%08x rem=%u\n", csr, td->remainder); 325 326 temp = csr; 327 temp &= (AT91_UDP_CSR_RX_DATA_BK0 | 328 AT91_UDP_CSR_RX_DATA_BK1 | 329 AT91_UDP_CSR_STALLSENT | 330 AT91_UDP_CSR_RXSETUP | 331 AT91_UDP_CSR_TXCOMP); 332 333 if (!(csr & AT91_UDP_CSR_RXSETUP)) { 334 /* abort any ongoing transfer */ 335 if (!td->did_stall) { 336 DPRINTFN(5, "stalling\n"); 337 temp |= AT91_UDP_CSR_FORCESTALL; 338 td->did_stall = 1; 339 } 340 goto not_complete; 341 } 342 /* get the packet byte count */ 343 count = (csr & AT91_UDP_CSR_RXBYTECNT) >> 16; 344 345 /* verify data length */ 346 if (count != td->remainder) { 347 DPRINTFN(0, "Invalid SETUP packet " 348 "length, %d bytes\n", count); 349 goto not_complete; 350 } 351 if (count != sizeof(req)) { 352 DPRINTFN(0, "Unsupported SETUP packet " 353 "length, %d bytes\n", count); 354 goto not_complete; 355 } 356 /* receive data */ 357 bus_space_read_multi_1(td->io_tag, td->io_hdl, 358 td->fifo_reg, (void *)&req, sizeof(req)); 359 360 /* copy data into real buffer */ 361 usb2_copy_in(td->pc, 0, &req, sizeof(req)); 362 363 td->offset = sizeof(req); 364 td->remainder = 0; 365 366 /* get pointer to softc */ 367 sc = AT9100_DCI_PC2SC(td->pc); 368 369 /* sneak peek the set address */ 370 if ((req.bmRequestType == UT_WRITE_DEVICE) && 371 (req.bRequest == UR_SET_ADDRESS)) { 372 sc->sc_dv_addr = req.wValue[0] & 0x7F; 373 } else { 374 sc->sc_dv_addr = 0xFF; 375 } 376 377 /* sneak peek the endpoint direction */ 378 if (req.bmRequestType & UE_DIR_IN) { 379 csr |= AT91_UDP_CSR_DIR; 380 } else { 381 csr &= ~AT91_UDP_CSR_DIR; 382 } 383 384 /* write the direction of the control transfer */ 385 AT91_CSR_ACK(csr, temp); 386 bus_space_write_4(td->io_tag, td->io_hdl, 387 td->status_reg, csr); 388 return (0); /* complete */ 389 390not_complete: 391 /* clear interrupts, if any */ 392 if (temp) { 393 DPRINTFN(5, "clearing 0x%08x\n", temp); 394 AT91_CSR_ACK(csr, temp); 395 bus_space_write_4(td->io_tag, td->io_hdl, 396 td->status_reg, csr); 397 } 398 return (1); /* not complete */ 399 400} 401 402static uint8_t 403at91dci_data_rx(struct at91dci_td *td) 404{ 405 struct usb2_page_search buf_res; 406 uint32_t csr; 407 uint32_t temp; 408 uint16_t count; 409 uint8_t to; 410 uint8_t got_short; 411 412 to = 2; /* don't loop forever! */ 413 got_short = 0; 414 415 /* check if any of the FIFO banks have data */ 416repeat: 417 /* read out FIFO status */ 418 csr = bus_space_read_4(td->io_tag, td->io_hdl, 419 td->status_reg); 420 421 DPRINTFN(5, "csr=0x%08x rem=%u\n", csr, td->remainder); 422 423 if (csr & AT91_UDP_CSR_RXSETUP) { 424 if (td->remainder == 0) { 425 /* 426 * We are actually complete and have 427 * received the next SETUP 428 */ 429 DPRINTFN(5, "faking complete\n"); 430 return (0); /* complete */ 431 } 432 /* 433 * USB Host Aborted the transfer. 434 */ 435 td->error = 1; 436 return (0); /* complete */ 437 } 438 /* Make sure that "STALLSENT" gets cleared */ 439 temp = csr; 440 temp &= AT91_UDP_CSR_STALLSENT; 441 442 /* check status */ 443 if (!(csr & (AT91_UDP_CSR_RX_DATA_BK0 | 444 AT91_UDP_CSR_RX_DATA_BK1))) { 445 if (temp) { 446 /* write command */ 447 AT91_CSR_ACK(csr, temp); 448 bus_space_write_4(td->io_tag, td->io_hdl, 449 td->status_reg, csr); 450 } 451 return (1); /* not complete */ 452 } 453 /* get the packet byte count */ 454 count = (csr & AT91_UDP_CSR_RXBYTECNT) >> 16; 455 456 /* verify the packet byte count */ 457 if (count != td->max_packet_size) { 458 if (count < td->max_packet_size) { 459 /* we have a short packet */ 460 td->short_pkt = 1; 461 got_short = 1; 462 } else { 463 /* invalid USB packet */ 464 td->error = 1; 465 return (0); /* we are complete */ 466 } 467 } 468 /* verify the packet byte count */ 469 if (count > td->remainder) { 470 /* invalid USB packet */ 471 td->error = 1; 472 return (0); /* we are complete */ 473 } 474 while (count > 0) { 475 usb2_get_page(td->pc, td->offset, &buf_res); 476 477 /* get correct length */ 478 if (buf_res.length > count) { 479 buf_res.length = count; 480 } 481 /* receive data */ 482 bus_space_read_multi_1(td->io_tag, td->io_hdl, 483 td->fifo_reg, buf_res.buffer, buf_res.length); 484 485 /* update counters */ 486 count -= buf_res.length; 487 td->offset += buf_res.length; 488 td->remainder -= buf_res.length; 489 } 490 491 /* clear status bits */ 492 if (td->support_multi_buffer) { 493 if (td->fifo_bank) { 494 td->fifo_bank = 0; 495 temp |= AT91_UDP_CSR_RX_DATA_BK1; 496 } else { 497 td->fifo_bank = 1; 498 temp |= AT91_UDP_CSR_RX_DATA_BK0; 499 } 500 } else { 501 temp |= (AT91_UDP_CSR_RX_DATA_BK0 | 502 AT91_UDP_CSR_RX_DATA_BK1); 503 } 504 505 /* write command */ 506 AT91_CSR_ACK(csr, temp); 507 bus_space_write_4(td->io_tag, td->io_hdl, 508 td->status_reg, csr); 509 510 /* 511 * NOTE: We may have to delay a little bit before 512 * proceeding after clearing the DATA_BK bits. 513 */ 514 515 /* check if we are complete */ 516 if ((td->remainder == 0) || got_short) { 517 if (td->short_pkt) { 518 /* we are complete */ 519 return (0); 520 } 521 /* else need to receive a zero length packet */ 522 } 523 if (--to) { 524 goto repeat; 525 } 526 return (1); /* not complete */ 527} 528 529static uint8_t 530at91dci_data_tx(struct at91dci_td *td) 531{ 532 struct usb2_page_search buf_res; 533 uint32_t csr; 534 uint32_t temp; 535 uint16_t count; 536 uint8_t to; 537 538 to = 2; /* don't loop forever! */ 539 540repeat: 541 542 /* read out FIFO status */ 543 csr = bus_space_read_4(td->io_tag, td->io_hdl, 544 td->status_reg); 545 546 DPRINTFN(5, "csr=0x%08x rem=%u\n", csr, td->remainder); 547 548 if (csr & AT91_UDP_CSR_RXSETUP) { 549 /* 550 * The current transfer was aborted 551 * by the USB Host 552 */ 553 td->error = 1; 554 return (0); /* complete */ 555 } 556 /* Make sure that "STALLSENT" gets cleared */ 557 temp = csr; 558 temp &= AT91_UDP_CSR_STALLSENT; 559 560 if (csr & AT91_UDP_CSR_TXPKTRDY) { 561 if (temp) { 562 /* write command */ 563 AT91_CSR_ACK(csr, temp); 564 bus_space_write_4(td->io_tag, td->io_hdl, 565 td->status_reg, csr); 566 } 567 return (1); /* not complete */ 568 } else { 569 /* clear TXCOMP and set TXPKTRDY */ 570 temp |= (AT91_UDP_CSR_TXCOMP | 571 AT91_UDP_CSR_TXPKTRDY); 572 } 573 574 count = td->max_packet_size; 575 if (td->remainder < count) { 576 /* we have a short packet */ 577 td->short_pkt = 1; 578 count = td->remainder; 579 } 580 while (count > 0) { 581 582 usb2_get_page(td->pc, td->offset, &buf_res); 583 584 /* get correct length */ 585 if (buf_res.length > count) { 586 buf_res.length = count; 587 } 588 /* transmit data */ 589 bus_space_write_multi_1(td->io_tag, td->io_hdl, 590 td->fifo_reg, buf_res.buffer, buf_res.length); 591 592 /* update counters */ 593 count -= buf_res.length; 594 td->offset += buf_res.length; 595 td->remainder -= buf_res.length; 596 } 597 598 /* write command */ 599 AT91_CSR_ACK(csr, temp); 600 bus_space_write_4(td->io_tag, td->io_hdl, 601 td->status_reg, csr); 602 603 /* check remainder */ 604 if (td->remainder == 0) { 605 if (td->short_pkt) { 606 return (0); /* complete */ 607 } 608 /* else we need to transmit a short packet */ 609 } 610 if (--to) { 611 goto repeat; 612 } 613 return (1); /* not complete */ 614} 615 616static uint8_t 617at91dci_data_tx_sync(struct at91dci_td *td) 618{ 619 struct at91dci_softc *sc; 620 uint32_t csr; 621 uint32_t temp; 622 623#if 0 624repeat: 625#endif 626 627 /* read out FIFO status */ 628 csr = bus_space_read_4(td->io_tag, td->io_hdl, 629 td->status_reg); 630 631 DPRINTFN(5, "csr=0x%08x\n", csr); 632 633 if (csr & AT91_UDP_CSR_RXSETUP) { 634 DPRINTFN(5, "faking complete\n"); 635 /* Race condition */ 636 return (0); /* complete */ 637 } 638 temp = csr; 639 temp &= (AT91_UDP_CSR_STALLSENT | 640 AT91_UDP_CSR_TXCOMP); 641 642 /* check status */ 643 if (csr & AT91_UDP_CSR_TXPKTRDY) { 644 goto not_complete; 645 } 646 if (!(csr & AT91_UDP_CSR_TXCOMP)) { 647 goto not_complete; 648 } 649 sc = AT9100_DCI_PC2SC(td->pc); 650 if (sc->sc_dv_addr != 0xFF) { 651 /* 652 * The AT91 has a special requirement with regard to 653 * setting the address and that is to write the new 654 * address before clearing TXCOMP: 655 */ 656 at91dci_set_address(sc, sc->sc_dv_addr); 657 } 658 /* write command */ 659 AT91_CSR_ACK(csr, temp); 660 bus_space_write_4(td->io_tag, td->io_hdl, 661 td->status_reg, csr); 662 663 return (0); /* complete */ 664 665not_complete: 666 if (temp) { 667 /* write command */ 668 AT91_CSR_ACK(csr, temp); 669 bus_space_write_4(td->io_tag, td->io_hdl, 670 td->status_reg, csr); 671 } 672 return (1); /* not complete */ 673} 674 675static uint8_t 676at91dci_xfer_do_fifo(struct usb2_xfer *xfer) 677{ 678 struct at91dci_softc *sc; 679 struct at91dci_td *td; 680 uint8_t temp; 681 682 DPRINTFN(9, "\n"); 683 684 td = xfer->td_transfer_cache; 685 while (1) { 686 if ((td->func) (td)) { 687 /* operation in progress */ 688 break; 689 } 690 if (((void *)td) == xfer->td_transfer_last) { 691 goto done; 692 } 693 if (td->error) { 694 goto done; 695 } else if (td->remainder > 0) { 696 /* 697 * We had a short transfer. If there is no alternate 698 * next, stop processing ! 699 */ 700 if (!td->alt_next) { 701 goto done; 702 } 703 } 704 /* 705 * Fetch the next transfer descriptor and transfer 706 * some flags to the next transfer descriptor 707 */ 708 temp = 0; 709 if (td->fifo_bank) 710 temp |= 1; 711 td = td->obj_next; 712 xfer->td_transfer_cache = td; 713 if (temp & 1) 714 td->fifo_bank = 1; 715 } 716 return (1); /* not complete */ 717 718done: 719 sc = xfer->usb2_sc; 720 temp = (xfer->endpoint & UE_ADDR); 721 722 /* update FIFO bank flag and multi buffer */ 723 if (td->fifo_bank) { 724 sc->sc_ep_flags[temp].fifo_bank = 1; 725 } else { 726 sc->sc_ep_flags[temp].fifo_bank = 0; 727 } 728 729 /* compute all actual lengths */ 730 731 at91dci_standard_done(xfer); 732 733 return (0); /* complete */ 734} 735 736static void 737at91dci_interrupt_poll(struct at91dci_softc *sc) 738{ 739 struct usb2_xfer *xfer; 740 741repeat: 742 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 743 if (!at91dci_xfer_do_fifo(xfer)) { 744 /* queue has been modified */ 745 goto repeat; 746 } 747 } 748} 749 750static void 751at91dci_vbus_interrupt(struct usb2_bus *bus, uint8_t is_on) 752{ 753 struct at91dci_softc *sc = AT9100_DCI_BUS2SC(bus); 754 755 DPRINTFN(5, "vbus = %u\n", is_on); 756 757 USB_BUS_LOCK(&sc->sc_bus); 758 if (is_on) { 759 if (!sc->sc_flags.status_vbus) { 760 sc->sc_flags.status_vbus = 1; 761 762 /* complete root HUB interrupt endpoint */ 763 764 usb2_sw_transfer(&sc->sc_root_intr, 765 &at91dci_root_intr_done); 766 } 767 } else { 768 if (sc->sc_flags.status_vbus) { 769 sc->sc_flags.status_vbus = 0; 770 sc->sc_flags.status_bus_reset = 0; 771 sc->sc_flags.status_suspend = 0; 772 sc->sc_flags.change_suspend = 0; 773 sc->sc_flags.change_connect = 1; 774 775 /* complete root HUB interrupt endpoint */ 776 777 usb2_sw_transfer(&sc->sc_root_intr, 778 &at91dci_root_intr_done); 779 } 780 } 781 782 USB_BUS_UNLOCK(&sc->sc_bus); 783} 784 785void 786at91dci_interrupt(struct at91dci_softc *sc) 787{ 788 uint32_t status; 789 790 USB_BUS_LOCK(&sc->sc_bus); 791 792 status = AT91_UDP_READ_4(sc, AT91_UDP_ISR); 793 status &= AT91_UDP_INT_DEFAULT; 794 795 if (!status) { 796 USB_BUS_UNLOCK(&sc->sc_bus); 797 return; 798 } 799 /* acknowledge interrupts */ 800 801 AT91_UDP_WRITE_4(sc, AT91_UDP_ICR, status); 802 803 /* check for any bus state change interrupts */ 804 805 if (status & AT91_UDP_INT_BUS) { 806 807 DPRINTFN(5, "real bus interrupt 0x%08x\n", status); 808 809 if (status & AT91_UDP_INT_END_BR) { 810 811 /* set correct state */ 812 sc->sc_flags.status_bus_reset = 1; 813 sc->sc_flags.status_suspend = 0; 814 sc->sc_flags.change_suspend = 0; 815 sc->sc_flags.change_connect = 1; 816 817 /* disable resume interrupt */ 818 AT91_UDP_WRITE_4(sc, AT91_UDP_IDR, 819 AT91_UDP_INT_RXRSM); 820 /* enable suspend interrupt */ 821 AT91_UDP_WRITE_4(sc, AT91_UDP_IER, 822 AT91_UDP_INT_RXSUSP); 823 } 824 /* 825 * If RXRSM and RXSUSP is set at the same time we interpret 826 * that like RESUME. Resume is set when there is at least 3 827 * milliseconds of inactivity on the USB BUS. 828 */ 829 if (status & AT91_UDP_INT_RXRSM) { 830 if (sc->sc_flags.status_suspend) { 831 sc->sc_flags.status_suspend = 0; 832 sc->sc_flags.change_suspend = 1; 833 834 /* disable resume interrupt */ 835 AT91_UDP_WRITE_4(sc, AT91_UDP_IDR, 836 AT91_UDP_INT_RXRSM); 837 /* enable suspend interrupt */ 838 AT91_UDP_WRITE_4(sc, AT91_UDP_IER, 839 AT91_UDP_INT_RXSUSP); 840 } 841 } else if (status & AT91_UDP_INT_RXSUSP) { 842 if (!sc->sc_flags.status_suspend) { 843 sc->sc_flags.status_suspend = 1; 844 sc->sc_flags.change_suspend = 1; 845 846 /* disable suspend interrupt */ 847 AT91_UDP_WRITE_4(sc, AT91_UDP_IDR, 848 AT91_UDP_INT_RXSUSP); 849 850 /* enable resume interrupt */ 851 AT91_UDP_WRITE_4(sc, AT91_UDP_IER, 852 AT91_UDP_INT_RXRSM); 853 } 854 } 855 /* complete root HUB interrupt endpoint */ 856 857 usb2_sw_transfer(&sc->sc_root_intr, 858 &at91dci_root_intr_done); 859 } 860 /* check for any endpoint interrupts */ 861 862 if (status & AT91_UDP_INT_EPS) { 863 864 DPRINTFN(5, "real endpoint interrupt 0x%08x\n", status); 865 866 at91dci_interrupt_poll(sc); 867 } 868 USB_BUS_UNLOCK(&sc->sc_bus); 869} 870 871static void 872at91dci_setup_standard_chain_sub(struct at91dci_std_temp *temp) 873{ 874 struct at91dci_td *td; 875 876 /* get current Transfer Descriptor */ 877 td = temp->td_next; 878 temp->td = td; 879 880 /* prepare for next TD */ 881 temp->td_next = td->obj_next; 882 883 /* fill out the Transfer Descriptor */ 884 td->func = temp->func; 885 td->pc = temp->pc; 886 td->offset = temp->offset; 887 td->remainder = temp->len; 888 td->fifo_bank = 0; 889 td->error = 0; 890 td->did_stall = 0; 891 td->short_pkt = temp->short_pkt; 892 td->alt_next = temp->setup_alt_next; 893} 894 895static void 896at91dci_setup_standard_chain(struct usb2_xfer *xfer) 897{ 898 struct at91dci_std_temp temp; 899 struct at91dci_softc *sc; 900 struct at91dci_td *td; 901 uint32_t x; 902 uint8_t ep_no; 903 uint8_t need_sync; 904 905 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n", 906 xfer->address, UE_GET_ADDR(xfer->endpoint), 907 xfer->sumlen, usb2_get_speed(xfer->udev)); 908 909 temp.max_frame_size = xfer->max_frame_size; 910 911 td = xfer->td_start[0]; 912 xfer->td_transfer_first = td; 913 xfer->td_transfer_cache = td; 914 915 /* setup temp */ 916 917 temp.td = NULL; 918 temp.td_next = xfer->td_start[0]; 919 temp.setup_alt_next = xfer->flags_int.short_frames_ok; 920 temp.offset = 0; 921 922 sc = xfer->usb2_sc; 923 ep_no = (xfer->endpoint & UE_ADDR); 924 925 /* check if we should prepend a setup message */ 926 927 if (xfer->flags_int.control_xfr) { 928 if (xfer->flags_int.control_hdr) { 929 930 temp.func = &at91dci_setup_rx; 931 temp.len = xfer->frlengths[0]; 932 temp.pc = xfer->frbuffers + 0; 933 temp.short_pkt = temp.len ? 1 : 0; 934 935 at91dci_setup_standard_chain_sub(&temp); 936 } 937 x = 1; 938 } else { 939 x = 0; 940 } 941 942 if (x != xfer->nframes) { 943 if (xfer->endpoint & UE_DIR_IN) { 944 temp.func = &at91dci_data_tx; 945 need_sync = 1; 946 } else { 947 temp.func = &at91dci_data_rx; 948 need_sync = 0; 949 } 950 951 /* setup "pc" pointer */ 952 temp.pc = xfer->frbuffers + x; 953 } else { 954 need_sync = 0; 955 } 956 while (x != xfer->nframes) { 957 958 /* DATA0 / DATA1 message */ 959 960 temp.len = xfer->frlengths[x]; 961 962 x++; 963 964 if (x == xfer->nframes) { 965 temp.setup_alt_next = 0; 966 } 967 if (temp.len == 0) { 968 969 /* make sure that we send an USB packet */ 970 971 temp.short_pkt = 0; 972 973 } else { 974 975 /* regular data transfer */ 976 977 temp.short_pkt = (xfer->flags.force_short_xfer) ? 0 : 1; 978 } 979 980 at91dci_setup_standard_chain_sub(&temp); 981 982 if (xfer->flags_int.isochronous_xfr) { 983 temp.offset += temp.len; 984 } else { 985 /* get next Page Cache pointer */ 986 temp.pc = xfer->frbuffers + x; 987 } 988 } 989 990 /* always setup a valid "pc" pointer for status and sync */ 991 temp.pc = xfer->frbuffers + 0; 992 993 /* check if we need to sync */ 994 if (need_sync && xfer->flags_int.control_xfr) { 995 996 /* we need a SYNC point after TX */ 997 temp.func = &at91dci_data_tx_sync; 998 temp.len = 0; 999 temp.short_pkt = 0; 1000 1001 at91dci_setup_standard_chain_sub(&temp); 1002 } 1003 /* check if we should append a status stage */ 1004 if (xfer->flags_int.control_xfr && 1005 !xfer->flags_int.control_act) { 1006 1007 /* 1008 * Send a DATA1 message and invert the current 1009 * endpoint direction. 1010 */ 1011 if (xfer->endpoint & UE_DIR_IN) { 1012 temp.func = &at91dci_data_rx; 1013 need_sync = 0; 1014 } else { 1015 temp.func = &at91dci_data_tx; 1016 need_sync = 1; 1017 } 1018 temp.len = 0; 1019 temp.short_pkt = 0; 1020 1021 at91dci_setup_standard_chain_sub(&temp); 1022 if (need_sync) { 1023 /* we need a SYNC point after TX */ 1024 temp.func = &at91dci_data_tx_sync; 1025 temp.len = 0; 1026 temp.short_pkt = 0; 1027 1028 at91dci_setup_standard_chain_sub(&temp); 1029 } 1030 } 1031 /* must have at least one frame! */ 1032 td = temp.td; 1033 xfer->td_transfer_last = td; 1034 1035 /* setup the correct fifo bank */ 1036 if (sc->sc_ep_flags[ep_no].fifo_bank) { 1037 td = xfer->td_transfer_first; 1038 td->fifo_bank = 1; 1039 } 1040} 1041 1042static void 1043at91dci_timeout(void *arg) 1044{ 1045 struct usb2_xfer *xfer = arg; 1046 1047 DPRINTF("xfer=%p\n", xfer); 1048 1049 USB_BUS_LOCK_ASSERT(xfer->udev->bus, MA_OWNED); 1050 1051 /* transfer is transferred */ 1052 at91dci_device_done(xfer, USB_ERR_TIMEOUT); 1053} 1054 1055static void 1056at91dci_start_standard_chain(struct usb2_xfer *xfer) 1057{ 1058 DPRINTFN(9, "\n"); 1059 1060 /* poll one time */ 1061 if (at91dci_xfer_do_fifo(xfer)) { 1062 1063 struct at91dci_softc *sc = xfer->usb2_sc; 1064 uint8_t ep_no = xfer->endpoint & UE_ADDR; 1065 1066 /* 1067 * Only enable the endpoint interrupt when we are actually 1068 * waiting for data, hence we are dealing with level 1069 * triggered interrupts ! 1070 */ 1071 AT91_UDP_WRITE_4(sc, AT91_UDP_IER, AT91_UDP_INT_EP(ep_no)); 1072 1073 DPRINTFN(15, "enable interrupts on endpoint %d\n", ep_no); 1074 1075 /* put transfer on interrupt queue */ 1076 usb2_transfer_enqueue(&xfer->udev->bus->intr_q, xfer); 1077 1078 /* start timeout, if any */ 1079 if (xfer->timeout != 0) { 1080 usb2_transfer_timeout_ms(xfer, 1081 &at91dci_timeout, xfer->timeout); 1082 } 1083 } 1084} 1085 1086static void 1087at91dci_root_intr_done(struct usb2_xfer *xfer, 1088 struct usb2_sw_transfer *std) 1089{ 1090 struct at91dci_softc *sc = xfer->usb2_sc; 1091 1092 DPRINTFN(9, "\n"); 1093 1094 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1095 1096 if (std->state != USB_SW_TR_PRE_DATA) { 1097 if (std->state == USB_SW_TR_PRE_CALLBACK) { 1098 /* transfer transferred */ 1099 at91dci_device_done(xfer, std->err); 1100 } 1101 goto done; 1102 } 1103 /* setup buffer */ 1104 std->ptr = sc->sc_hub_idata; 1105 std->len = sizeof(sc->sc_hub_idata); 1106 1107 /* set port bit */ 1108 sc->sc_hub_idata[0] = 0x02; /* we only have one port */ 1109 1110done: 1111 return; 1112} 1113 1114static usb2_error_t 1115at91dci_standard_done_sub(struct usb2_xfer *xfer) 1116{ 1117 struct at91dci_td *td; 1118 uint32_t len; 1119 uint8_t error; 1120 1121 DPRINTFN(9, "\n"); 1122 1123 td = xfer->td_transfer_cache; 1124 1125 do { 1126 len = td->remainder; 1127 1128 if (xfer->aframes != xfer->nframes) { 1129 /* 1130 * Verify the length and subtract 1131 * the remainder from "frlengths[]": 1132 */ 1133 if (len > xfer->frlengths[xfer->aframes]) { 1134 td->error = 1; 1135 } else { 1136 xfer->frlengths[xfer->aframes] -= len; 1137 } 1138 } 1139 /* Check for transfer error */ 1140 if (td->error) { 1141 /* the transfer is finished */ 1142 error = 1; 1143 td = NULL; 1144 break; 1145 } 1146 /* Check for short transfer */ 1147 if (len > 0) { 1148 if (xfer->flags_int.short_frames_ok) { 1149 /* follow alt next */ 1150 if (td->alt_next) { 1151 td = td->obj_next; 1152 } else { 1153 td = NULL; 1154 } 1155 } else { 1156 /* the transfer is finished */ 1157 td = NULL; 1158 } 1159 error = 0; 1160 break; 1161 } 1162 td = td->obj_next; 1163 1164 /* this USB frame is complete */ 1165 error = 0; 1166 break; 1167 1168 } while (0); 1169 1170 /* update transfer cache */ 1171 1172 xfer->td_transfer_cache = td; 1173 1174 return (error ? 1175 USB_ERR_STALLED : USB_ERR_NORMAL_COMPLETION); 1176} 1177 1178static void 1179at91dci_standard_done(struct usb2_xfer *xfer) 1180{ 1181 usb2_error_t err = 0; 1182 1183 DPRINTFN(13, "xfer=%p pipe=%p transfer done\n", 1184 xfer, xfer->pipe); 1185 1186 /* reset scanner */ 1187 1188 xfer->td_transfer_cache = xfer->td_transfer_first; 1189 1190 if (xfer->flags_int.control_xfr) { 1191 1192 if (xfer->flags_int.control_hdr) { 1193 1194 err = at91dci_standard_done_sub(xfer); 1195 } 1196 xfer->aframes = 1; 1197 1198 if (xfer->td_transfer_cache == NULL) { 1199 goto done; 1200 } 1201 } 1202 while (xfer->aframes != xfer->nframes) { 1203 1204 err = at91dci_standard_done_sub(xfer); 1205 xfer->aframes++; 1206 1207 if (xfer->td_transfer_cache == NULL) { 1208 goto done; 1209 } 1210 } 1211 1212 if (xfer->flags_int.control_xfr && 1213 !xfer->flags_int.control_act) { 1214 1215 err = at91dci_standard_done_sub(xfer); 1216 } 1217done: 1218 at91dci_device_done(xfer, err); 1219} 1220 1221/*------------------------------------------------------------------------* 1222 * at91dci_device_done 1223 * 1224 * NOTE: this function can be called more than one time on the 1225 * same USB transfer! 1226 *------------------------------------------------------------------------*/ 1227static void 1228at91dci_device_done(struct usb2_xfer *xfer, usb2_error_t error) 1229{ 1230 struct at91dci_softc *sc = xfer->usb2_sc; 1231 uint8_t ep_no; 1232 1233 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1234 1235 DPRINTFN(2, "xfer=%p, pipe=%p, error=%d\n", 1236 xfer, xfer->pipe, error); 1237 1238 if (xfer->flags_int.usb2_mode == USB_MODE_DEVICE) { 1239 ep_no = (xfer->endpoint & UE_ADDR); 1240 1241 /* disable endpoint interrupt */ 1242 AT91_UDP_WRITE_4(sc, AT91_UDP_IDR, AT91_UDP_INT_EP(ep_no)); 1243 1244 DPRINTFN(15, "disable interrupts on endpoint %d\n", ep_no); 1245 } 1246 /* dequeue transfer and start next transfer */ 1247 usb2_transfer_done(xfer, error); 1248} 1249 1250static void 1251at91dci_set_stall(struct usb2_device *udev, struct usb2_xfer *xfer, 1252 struct usb2_pipe *pipe) 1253{ 1254 struct at91dci_softc *sc; 1255 uint32_t csr_val; 1256 uint8_t csr_reg; 1257 1258 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 1259 1260 DPRINTFN(5, "pipe=%p\n", pipe); 1261 1262 if (xfer) { 1263 /* cancel any ongoing transfers */ 1264 at91dci_device_done(xfer, USB_ERR_STALLED); 1265 } 1266 /* set FORCESTALL */ 1267 sc = AT9100_DCI_BUS2SC(udev->bus); 1268 csr_reg = (pipe->edesc->bEndpointAddress & UE_ADDR); 1269 csr_reg = AT91_UDP_CSR(csr_reg); 1270 csr_val = AT91_UDP_READ_4(sc, csr_reg); 1271 AT91_CSR_ACK(csr_val, AT91_UDP_CSR_FORCESTALL); 1272 AT91_UDP_WRITE_4(sc, csr_reg, csr_val); 1273} 1274 1275static void 1276at91dci_clear_stall_sub(struct at91dci_softc *sc, uint8_t ep_no, 1277 uint8_t ep_type, uint8_t ep_dir) 1278{ 1279 const struct usb2_hw_ep_profile *pf; 1280 uint32_t csr_val; 1281 uint32_t temp; 1282 uint8_t csr_reg; 1283 uint8_t to; 1284 1285 if (ep_type == UE_CONTROL) { 1286 /* clearing stall is not needed */ 1287 return; 1288 } 1289 /* compute CSR register offset */ 1290 csr_reg = AT91_UDP_CSR(ep_no); 1291 1292 /* compute default CSR value */ 1293 csr_val = 0; 1294 AT91_CSR_ACK(csr_val, 0); 1295 1296 /* disable endpoint */ 1297 AT91_UDP_WRITE_4(sc, csr_reg, csr_val); 1298 1299 /* get endpoint profile */ 1300 at91dci_get_hw_ep_profile(NULL, &pf, ep_no); 1301 1302 /* reset FIFO */ 1303 AT91_UDP_WRITE_4(sc, AT91_UDP_RST, AT91_UDP_RST_EP(ep_no)); 1304 AT91_UDP_WRITE_4(sc, AT91_UDP_RST, 0); 1305 1306 /* 1307 * NOTE: One would assume that a FIFO reset would release the 1308 * FIFO banks aswell, but it doesn't! We have to do this 1309 * manually! 1310 */ 1311 1312 /* release FIFO banks, if any */ 1313 for (to = 0; to != 2; to++) { 1314 1315 /* get csr value */ 1316 csr_val = AT91_UDP_READ_4(sc, csr_reg); 1317 1318 if (csr_val & (AT91_UDP_CSR_RX_DATA_BK0 | 1319 AT91_UDP_CSR_RX_DATA_BK1)) { 1320 /* clear status bits */ 1321 if (pf->support_multi_buffer) { 1322 if (sc->sc_ep_flags[ep_no].fifo_bank) { 1323 sc->sc_ep_flags[ep_no].fifo_bank = 0; 1324 temp = AT91_UDP_CSR_RX_DATA_BK1; 1325 } else { 1326 sc->sc_ep_flags[ep_no].fifo_bank = 1; 1327 temp = AT91_UDP_CSR_RX_DATA_BK0; 1328 } 1329 } else { 1330 temp = (AT91_UDP_CSR_RX_DATA_BK0 | 1331 AT91_UDP_CSR_RX_DATA_BK1); 1332 } 1333 } else { 1334 temp = 0; 1335 } 1336 1337 /* clear FORCESTALL */ 1338 temp |= AT91_UDP_CSR_STALLSENT; 1339 1340 AT91_CSR_ACK(csr_val, temp); 1341 AT91_UDP_WRITE_4(sc, csr_reg, csr_val); 1342 } 1343 1344 /* compute default CSR value */ 1345 csr_val = 0; 1346 AT91_CSR_ACK(csr_val, 0); 1347 1348 /* enable endpoint */ 1349 csr_val &= ~AT91_UDP_CSR_ET_MASK; 1350 csr_val |= AT91_UDP_CSR_EPEDS; 1351 1352 if (ep_type == UE_CONTROL) { 1353 csr_val |= AT91_UDP_CSR_ET_CTRL; 1354 } else { 1355 if (ep_type == UE_BULK) { 1356 csr_val |= AT91_UDP_CSR_ET_BULK; 1357 } else if (ep_type == UE_INTERRUPT) { 1358 csr_val |= AT91_UDP_CSR_ET_INT; 1359 } else { 1360 csr_val |= AT91_UDP_CSR_ET_ISO; 1361 } 1362 if (ep_dir & UE_DIR_IN) { 1363 csr_val |= AT91_UDP_CSR_ET_DIR_IN; 1364 } 1365 } 1366 1367 /* enable endpoint */ 1368 AT91_UDP_WRITE_4(sc, AT91_UDP_CSR(ep_no), csr_val); 1369} 1370 1371static void 1372at91dci_clear_stall(struct usb2_device *udev, struct usb2_pipe *pipe) 1373{ 1374 struct at91dci_softc *sc; 1375 struct usb2_endpoint_descriptor *ed; 1376 1377 DPRINTFN(5, "pipe=%p\n", pipe); 1378 1379 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 1380 1381 /* check mode */ 1382 if (udev->flags.usb2_mode != USB_MODE_DEVICE) { 1383 /* not supported */ 1384 return; 1385 } 1386 /* get softc */ 1387 sc = AT9100_DCI_BUS2SC(udev->bus); 1388 1389 /* get endpoint descriptor */ 1390 ed = pipe->edesc; 1391 1392 /* reset endpoint */ 1393 at91dci_clear_stall_sub(sc, 1394 (ed->bEndpointAddress & UE_ADDR), 1395 (ed->bmAttributes & UE_XFERTYPE), 1396 (ed->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT))); 1397} 1398 1399usb2_error_t 1400at91dci_init(struct at91dci_softc *sc) 1401{ 1402 uint32_t csr_val; 1403 uint8_t n; 1404 1405 DPRINTF("start\n"); 1406 1407 /* set up the bus structure */ 1408 sc->sc_bus.usbrev = USB_REV_1_1; 1409 sc->sc_bus.methods = &at91dci_bus_methods; 1410 1411 USB_BUS_LOCK(&sc->sc_bus); 1412 1413 /* turn on clocks */ 1414 1415 if (sc->sc_clocks_on) { 1416 (sc->sc_clocks_on) (sc->sc_clocks_arg); 1417 } 1418 /* wait a little for things to stabilise */ 1419 usb2_pause_mtx(&sc->sc_bus.bus_mtx, 1); 1420 1421 /* disable and clear all interrupts */ 1422 1423 AT91_UDP_WRITE_4(sc, AT91_UDP_IDR, 0xFFFFFFFF); 1424 AT91_UDP_WRITE_4(sc, AT91_UDP_ICR, 0xFFFFFFFF); 1425 1426 /* compute default CSR value */ 1427 1428 csr_val = 0; 1429 AT91_CSR_ACK(csr_val, 0); 1430 1431 /* disable all endpoints */ 1432 1433 for (n = 0; n != AT91_UDP_EP_MAX; n++) { 1434 1435 /* disable endpoint */ 1436 AT91_UDP_WRITE_4(sc, AT91_UDP_CSR(n), csr_val); 1437 } 1438 1439 /* enable the control endpoint */ 1440 1441 AT91_CSR_ACK(csr_val, AT91_UDP_CSR_ET_CTRL | 1442 AT91_UDP_CSR_EPEDS); 1443 1444 /* write to FIFO control register */ 1445 1446 AT91_UDP_WRITE_4(sc, AT91_UDP_CSR(0), csr_val); 1447 1448 /* enable the interrupts we want */ 1449 1450 AT91_UDP_WRITE_4(sc, AT91_UDP_IER, AT91_UDP_INT_BUS); 1451 1452 /* turn off clocks */ 1453 1454 at91dci_clocks_off(sc); 1455 1456 USB_BUS_UNLOCK(&sc->sc_bus); 1457 1458 /* catch any lost interrupts */ 1459 1460 at91dci_do_poll(&sc->sc_bus); 1461 1462 return (0); /* success */ 1463} 1464 1465void 1466at91dci_uninit(struct at91dci_softc *sc) 1467{ 1468 USB_BUS_LOCK(&sc->sc_bus); 1469 1470 /* disable and clear all interrupts */ 1471 AT91_UDP_WRITE_4(sc, AT91_UDP_IDR, 0xFFFFFFFF); 1472 AT91_UDP_WRITE_4(sc, AT91_UDP_ICR, 0xFFFFFFFF); 1473 1474 sc->sc_flags.port_powered = 0; 1475 sc->sc_flags.status_vbus = 0; 1476 sc->sc_flags.status_bus_reset = 0; 1477 sc->sc_flags.status_suspend = 0; 1478 sc->sc_flags.change_suspend = 0; 1479 sc->sc_flags.change_connect = 1; 1480 1481 at91dci_pull_down(sc); 1482 at91dci_clocks_off(sc); 1483 USB_BUS_UNLOCK(&sc->sc_bus); 1484} 1485 1486void 1487at91dci_suspend(struct at91dci_softc *sc) 1488{ 1489 return; 1490} 1491 1492void 1493at91dci_resume(struct at91dci_softc *sc) 1494{ 1495 return; 1496} 1497 1498static void 1499at91dci_do_poll(struct usb2_bus *bus) 1500{ 1501 struct at91dci_softc *sc = AT9100_DCI_BUS2SC(bus); 1502 1503 USB_BUS_LOCK(&sc->sc_bus); 1504 at91dci_interrupt_poll(sc); 1505 at91dci_root_ctrl_poll(sc); 1506 USB_BUS_UNLOCK(&sc->sc_bus); 1507} 1508 1509/*------------------------------------------------------------------------* 1510 * at91dci bulk support 1511 *------------------------------------------------------------------------*/ 1512static void 1513at91dci_device_bulk_open(struct usb2_xfer *xfer) 1514{ 1515 return; 1516} 1517 1518static void 1519at91dci_device_bulk_close(struct usb2_xfer *xfer) 1520{ 1521 at91dci_device_done(xfer, USB_ERR_CANCELLED); 1522} 1523 1524static void 1525at91dci_device_bulk_enter(struct usb2_xfer *xfer) 1526{ 1527 return; 1528} 1529 1530static void 1531at91dci_device_bulk_start(struct usb2_xfer *xfer) 1532{ 1533 /* setup TDs */ 1534 at91dci_setup_standard_chain(xfer); 1535 at91dci_start_standard_chain(xfer); 1536} 1537 1538struct usb2_pipe_methods at91dci_device_bulk_methods = 1539{ 1540 .open = at91dci_device_bulk_open, 1541 .close = at91dci_device_bulk_close, 1542 .enter = at91dci_device_bulk_enter, 1543 .start = at91dci_device_bulk_start, 1544 .enter_is_cancelable = 1, 1545 .start_is_cancelable = 1, 1546}; 1547 1548/*------------------------------------------------------------------------* 1549 * at91dci control support 1550 *------------------------------------------------------------------------*/ 1551static void 1552at91dci_device_ctrl_open(struct usb2_xfer *xfer) 1553{ 1554 return; 1555} 1556 1557static void 1558at91dci_device_ctrl_close(struct usb2_xfer *xfer) 1559{ 1560 at91dci_device_done(xfer, USB_ERR_CANCELLED); 1561} 1562 1563static void 1564at91dci_device_ctrl_enter(struct usb2_xfer *xfer) 1565{ 1566 return; 1567} 1568 1569static void 1570at91dci_device_ctrl_start(struct usb2_xfer *xfer) 1571{ 1572 /* setup TDs */ 1573 at91dci_setup_standard_chain(xfer); 1574 at91dci_start_standard_chain(xfer); 1575} 1576 1577struct usb2_pipe_methods at91dci_device_ctrl_methods = 1578{ 1579 .open = at91dci_device_ctrl_open, 1580 .close = at91dci_device_ctrl_close, 1581 .enter = at91dci_device_ctrl_enter, 1582 .start = at91dci_device_ctrl_start, 1583 .enter_is_cancelable = 1, 1584 .start_is_cancelable = 1, 1585}; 1586 1587/*------------------------------------------------------------------------* 1588 * at91dci interrupt support 1589 *------------------------------------------------------------------------*/ 1590static void 1591at91dci_device_intr_open(struct usb2_xfer *xfer) 1592{ 1593 return; 1594} 1595 1596static void 1597at91dci_device_intr_close(struct usb2_xfer *xfer) 1598{ 1599 at91dci_device_done(xfer, USB_ERR_CANCELLED); 1600} 1601 1602static void 1603at91dci_device_intr_enter(struct usb2_xfer *xfer) 1604{ 1605 return; 1606} 1607 1608static void 1609at91dci_device_intr_start(struct usb2_xfer *xfer) 1610{ 1611 /* setup TDs */ 1612 at91dci_setup_standard_chain(xfer); 1613 at91dci_start_standard_chain(xfer); 1614} 1615 1616struct usb2_pipe_methods at91dci_device_intr_methods = 1617{ 1618 .open = at91dci_device_intr_open, 1619 .close = at91dci_device_intr_close, 1620 .enter = at91dci_device_intr_enter, 1621 .start = at91dci_device_intr_start, 1622 .enter_is_cancelable = 1, 1623 .start_is_cancelable = 1, 1624}; 1625 1626/*------------------------------------------------------------------------* 1627 * at91dci full speed isochronous support 1628 *------------------------------------------------------------------------*/ 1629static void 1630at91dci_device_isoc_fs_open(struct usb2_xfer *xfer) 1631{ 1632 return; 1633} 1634 1635static void 1636at91dci_device_isoc_fs_close(struct usb2_xfer *xfer) 1637{ 1638 at91dci_device_done(xfer, USB_ERR_CANCELLED); 1639} 1640 1641static void 1642at91dci_device_isoc_fs_enter(struct usb2_xfer *xfer) 1643{ 1644 struct at91dci_softc *sc = xfer->usb2_sc; 1645 uint32_t temp; 1646 uint32_t nframes; 1647 1648 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n", 1649 xfer, xfer->pipe->isoc_next, xfer->nframes); 1650 1651 /* get the current frame index */ 1652 1653 nframes = AT91_UDP_READ_4(sc, AT91_UDP_FRM); 1654 1655 /* 1656 * check if the frame index is within the window where the frames 1657 * will be inserted 1658 */ 1659 temp = (nframes - xfer->pipe->isoc_next) & AT91_UDP_FRM_MASK; 1660 1661 if ((xfer->pipe->is_synced == 0) || 1662 (temp < xfer->nframes)) { 1663 /* 1664 * If there is data underflow or the pipe queue is 1665 * empty we schedule the transfer a few frames ahead 1666 * of the current frame position. Else two isochronous 1667 * transfers might overlap. 1668 */ 1669 xfer->pipe->isoc_next = (nframes + 3) & AT91_UDP_FRM_MASK; 1670 xfer->pipe->is_synced = 1; 1671 DPRINTFN(3, "start next=%d\n", xfer->pipe->isoc_next); 1672 } 1673 /* 1674 * compute how many milliseconds the insertion is ahead of the 1675 * current frame position: 1676 */ 1677 temp = (xfer->pipe->isoc_next - nframes) & AT91_UDP_FRM_MASK; 1678 1679 /* 1680 * pre-compute when the isochronous transfer will be finished: 1681 */ 1682 xfer->isoc_time_complete = 1683 usb2_isoc_time_expand(&sc->sc_bus, nframes) + temp + 1684 xfer->nframes; 1685 1686 /* compute frame number for next insertion */ 1687 xfer->pipe->isoc_next += xfer->nframes; 1688 1689 /* setup TDs */ 1690 at91dci_setup_standard_chain(xfer); 1691} 1692 1693static void 1694at91dci_device_isoc_fs_start(struct usb2_xfer *xfer) 1695{ 1696 /* start TD chain */ 1697 at91dci_start_standard_chain(xfer); 1698} 1699 1700struct usb2_pipe_methods at91dci_device_isoc_fs_methods = 1701{ 1702 .open = at91dci_device_isoc_fs_open, 1703 .close = at91dci_device_isoc_fs_close, 1704 .enter = at91dci_device_isoc_fs_enter, 1705 .start = at91dci_device_isoc_fs_start, 1706 .enter_is_cancelable = 1, 1707 .start_is_cancelable = 1, 1708}; 1709 1710/*------------------------------------------------------------------------* 1711 * at91dci root control support 1712 *------------------------------------------------------------------------* 1713 * simulate a hardware HUB by handling 1714 * all the necessary requests 1715 *------------------------------------------------------------------------*/ 1716 1717static void 1718at91dci_root_ctrl_open(struct usb2_xfer *xfer) 1719{ 1720 return; 1721} 1722 1723static void 1724at91dci_root_ctrl_close(struct usb2_xfer *xfer) 1725{ 1726 struct at91dci_softc *sc = xfer->usb2_sc; 1727 1728 if (sc->sc_root_ctrl.xfer == xfer) { 1729 sc->sc_root_ctrl.xfer = NULL; 1730 } 1731 at91dci_device_done(xfer, USB_ERR_CANCELLED); 1732} 1733 1734/* 1735 * USB descriptors for the virtual Root HUB: 1736 */ 1737 1738static const struct usb2_device_descriptor at91dci_devd = { 1739 .bLength = sizeof(struct usb2_device_descriptor), 1740 .bDescriptorType = UDESC_DEVICE, 1741 .bcdUSB = {0x00, 0x02}, 1742 .bDeviceClass = UDCLASS_HUB, 1743 .bDeviceSubClass = UDSUBCLASS_HUB, 1744 .bDeviceProtocol = UDPROTO_HSHUBSTT, 1745 .bMaxPacketSize = 64, 1746 .bcdDevice = {0x00, 0x01}, 1747 .iManufacturer = 1, 1748 .iProduct = 2, 1749 .bNumConfigurations = 1, 1750}; 1751 1752static const struct usb2_device_qualifier at91dci_odevd = { 1753 .bLength = sizeof(struct usb2_device_qualifier), 1754 .bDescriptorType = UDESC_DEVICE_QUALIFIER, 1755 .bcdUSB = {0x00, 0x02}, 1756 .bDeviceClass = UDCLASS_HUB, 1757 .bDeviceSubClass = UDSUBCLASS_HUB, 1758 .bDeviceProtocol = UDPROTO_FSHUB, 1759 .bMaxPacketSize0 = 0, 1760 .bNumConfigurations = 0, 1761}; 1762 1763static const struct at91dci_config_desc at91dci_confd = { 1764 .confd = { 1765 .bLength = sizeof(struct usb2_config_descriptor), 1766 .bDescriptorType = UDESC_CONFIG, 1767 .wTotalLength[0] = sizeof(at91dci_confd), 1768 .bNumInterface = 1, 1769 .bConfigurationValue = 1, 1770 .iConfiguration = 0, 1771 .bmAttributes = UC_SELF_POWERED, 1772 .bMaxPower = 0, 1773 }, 1774 .ifcd = { 1775 .bLength = sizeof(struct usb2_interface_descriptor), 1776 .bDescriptorType = UDESC_INTERFACE, 1777 .bNumEndpoints = 1, 1778 .bInterfaceClass = UICLASS_HUB, 1779 .bInterfaceSubClass = UISUBCLASS_HUB, 1780 .bInterfaceProtocol = UIPROTO_HSHUBSTT, 1781 }, 1782 1783 .endpd = { 1784 .bLength = sizeof(struct usb2_endpoint_descriptor), 1785 .bDescriptorType = UDESC_ENDPOINT, 1786 .bEndpointAddress = (UE_DIR_IN | AT9100_DCI_INTR_ENDPT), 1787 .bmAttributes = UE_INTERRUPT, 1788 .wMaxPacketSize[0] = 8, 1789 .bInterval = 255, 1790 }, 1791}; 1792 1793static const struct usb2_hub_descriptor_min at91dci_hubd = { 1794 .bDescLength = sizeof(at91dci_hubd), 1795 .bDescriptorType = UDESC_HUB, 1796 .bNbrPorts = 1, 1797 .wHubCharacteristics[0] = 1798 (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL) & 0xFF, 1799 .wHubCharacteristics[1] = 1800 (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL) >> 16, 1801 .bPwrOn2PwrGood = 50, 1802 .bHubContrCurrent = 0, 1803 .DeviceRemovable = {0}, /* port is removable */ 1804}; 1805 1806#define STRING_LANG \ 1807 0x09, 0x04, /* American English */ 1808 1809#define STRING_VENDOR \ 1810 'A', 0, 'T', 0, 'M', 0, 'E', 0, 'L', 0 1811 1812#define STRING_PRODUCT \ 1813 'D', 0, 'C', 0, 'I', 0, ' ', 0, 'R', 0, \ 1814 'o', 0, 'o', 0, 't', 0, ' ', 0, 'H', 0, \ 1815 'U', 0, 'B', 0, 1816 1817USB_MAKE_STRING_DESC(STRING_LANG, at91dci_langtab); 1818USB_MAKE_STRING_DESC(STRING_VENDOR, at91dci_vendor); 1819USB_MAKE_STRING_DESC(STRING_PRODUCT, at91dci_product); 1820 1821static void 1822at91dci_root_ctrl_enter(struct usb2_xfer *xfer) 1823{ 1824 return; 1825} 1826 1827static void 1828at91dci_root_ctrl_start(struct usb2_xfer *xfer) 1829{ 1830 struct at91dci_softc *sc = xfer->usb2_sc; 1831 1832 sc->sc_root_ctrl.xfer = xfer; 1833 1834 usb2_config_td_queue_command( 1835 &sc->sc_config_td, NULL, &at91dci_root_ctrl_task, 0, 0); 1836} 1837 1838static void 1839at91dci_root_ctrl_task(struct at91dci_softc *sc, 1840 struct at91dci_config_copy *cc, uint16_t refcount) 1841{ 1842 at91dci_root_ctrl_poll(sc); 1843} 1844 1845static void 1846at91dci_root_ctrl_done(struct usb2_xfer *xfer, 1847 struct usb2_sw_transfer *std) 1848{ 1849 struct at91dci_softc *sc = xfer->usb2_sc; 1850 uint16_t value; 1851 uint16_t index; 1852 uint8_t use_polling; 1853 1854 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1855 1856 if (std->state != USB_SW_TR_SETUP) { 1857 if (std->state == USB_SW_TR_PRE_CALLBACK) { 1858 /* transfer transferred */ 1859 at91dci_device_done(xfer, std->err); 1860 } 1861 goto done; 1862 } 1863 /* buffer reset */ 1864 std->ptr = USB_ADD_BYTES(&sc->sc_hub_temp, 0); 1865 std->len = 0; 1866 1867 value = UGETW(std->req.wValue); 1868 index = UGETW(std->req.wIndex); 1869 1870 use_polling = mtx_owned(xfer->xfer_mtx) ? 1 : 0; 1871 1872 /* demultiplex the control request */ 1873 1874 switch (std->req.bmRequestType) { 1875 case UT_READ_DEVICE: 1876 switch (std->req.bRequest) { 1877 case UR_GET_DESCRIPTOR: 1878 goto tr_handle_get_descriptor; 1879 case UR_GET_CONFIG: 1880 goto tr_handle_get_config; 1881 case UR_GET_STATUS: 1882 goto tr_handle_get_status; 1883 default: 1884 goto tr_stalled; 1885 } 1886 break; 1887 1888 case UT_WRITE_DEVICE: 1889 switch (std->req.bRequest) { 1890 case UR_SET_ADDRESS: 1891 goto tr_handle_set_address; 1892 case UR_SET_CONFIG: 1893 goto tr_handle_set_config; 1894 case UR_CLEAR_FEATURE: 1895 goto tr_valid; /* nop */ 1896 case UR_SET_DESCRIPTOR: 1897 goto tr_valid; /* nop */ 1898 case UR_SET_FEATURE: 1899 default: 1900 goto tr_stalled; 1901 } 1902 break; 1903 1904 case UT_WRITE_ENDPOINT: 1905 switch (std->req.bRequest) { 1906 case UR_CLEAR_FEATURE: 1907 switch (UGETW(std->req.wValue)) { 1908 case UF_ENDPOINT_HALT: 1909 goto tr_handle_clear_halt; 1910 case UF_DEVICE_REMOTE_WAKEUP: 1911 goto tr_handle_clear_wakeup; 1912 default: 1913 goto tr_stalled; 1914 } 1915 break; 1916 case UR_SET_FEATURE: 1917 switch (UGETW(std->req.wValue)) { 1918 case UF_ENDPOINT_HALT: 1919 goto tr_handle_set_halt; 1920 case UF_DEVICE_REMOTE_WAKEUP: 1921 goto tr_handle_set_wakeup; 1922 default: 1923 goto tr_stalled; 1924 } 1925 break; 1926 case UR_SYNCH_FRAME: 1927 goto tr_valid; /* nop */ 1928 default: 1929 goto tr_stalled; 1930 } 1931 break; 1932 1933 case UT_READ_ENDPOINT: 1934 switch (std->req.bRequest) { 1935 case UR_GET_STATUS: 1936 goto tr_handle_get_ep_status; 1937 default: 1938 goto tr_stalled; 1939 } 1940 break; 1941 1942 case UT_WRITE_INTERFACE: 1943 switch (std->req.bRequest) { 1944 case UR_SET_INTERFACE: 1945 goto tr_handle_set_interface; 1946 case UR_CLEAR_FEATURE: 1947 goto tr_valid; /* nop */ 1948 case UR_SET_FEATURE: 1949 default: 1950 goto tr_stalled; 1951 } 1952 break; 1953 1954 case UT_READ_INTERFACE: 1955 switch (std->req.bRequest) { 1956 case UR_GET_INTERFACE: 1957 goto tr_handle_get_interface; 1958 case UR_GET_STATUS: 1959 goto tr_handle_get_iface_status; 1960 default: 1961 goto tr_stalled; 1962 } 1963 break; 1964 1965 case UT_WRITE_CLASS_INTERFACE: 1966 case UT_WRITE_VENDOR_INTERFACE: 1967 /* XXX forward */ 1968 break; 1969 1970 case UT_READ_CLASS_INTERFACE: 1971 case UT_READ_VENDOR_INTERFACE: 1972 /* XXX forward */ 1973 break; 1974 1975 case UT_WRITE_CLASS_DEVICE: 1976 switch (std->req.bRequest) { 1977 case UR_CLEAR_FEATURE: 1978 goto tr_valid; 1979 case UR_SET_DESCRIPTOR: 1980 case UR_SET_FEATURE: 1981 break; 1982 default: 1983 goto tr_stalled; 1984 } 1985 break; 1986 1987 case UT_WRITE_CLASS_OTHER: 1988 switch (std->req.bRequest) { 1989 case UR_CLEAR_FEATURE: 1990 goto tr_handle_clear_port_feature; 1991 case UR_SET_FEATURE: 1992 goto tr_handle_set_port_feature; 1993 case UR_CLEAR_TT_BUFFER: 1994 case UR_RESET_TT: 1995 case UR_STOP_TT: 1996 goto tr_valid; 1997 1998 default: 1999 goto tr_stalled; 2000 } 2001 break; 2002 2003 case UT_READ_CLASS_OTHER: 2004 switch (std->req.bRequest) { 2005 case UR_GET_TT_STATE: 2006 goto tr_handle_get_tt_state; 2007 case UR_GET_STATUS: 2008 goto tr_handle_get_port_status; 2009 default: 2010 goto tr_stalled; 2011 } 2012 break; 2013 2014 case UT_READ_CLASS_DEVICE: 2015 switch (std->req.bRequest) { 2016 case UR_GET_DESCRIPTOR: 2017 goto tr_handle_get_class_descriptor; 2018 case UR_GET_STATUS: 2019 goto tr_handle_get_class_status; 2020 2021 default: 2022 goto tr_stalled; 2023 } 2024 break; 2025 default: 2026 goto tr_stalled; 2027 } 2028 goto tr_valid; 2029 2030tr_handle_get_descriptor: 2031 switch (value >> 8) { 2032 case UDESC_DEVICE: 2033 if (value & 0xff) { 2034 goto tr_stalled; 2035 } 2036 std->len = sizeof(at91dci_devd); 2037 std->ptr = USB_ADD_BYTES(&at91dci_devd, 0); 2038 goto tr_valid; 2039 case UDESC_CONFIG: 2040 if (value & 0xff) { 2041 goto tr_stalled; 2042 } 2043 std->len = sizeof(at91dci_confd); 2044 std->ptr = USB_ADD_BYTES(&at91dci_confd, 0); 2045 goto tr_valid; 2046 case UDESC_STRING: 2047 switch (value & 0xff) { 2048 case 0: /* Language table */ 2049 std->len = sizeof(at91dci_langtab); 2050 std->ptr = USB_ADD_BYTES(&at91dci_langtab, 0); 2051 goto tr_valid; 2052 2053 case 1: /* Vendor */ 2054 std->len = sizeof(at91dci_vendor); 2055 std->ptr = USB_ADD_BYTES(&at91dci_vendor, 0); 2056 goto tr_valid; 2057 2058 case 2: /* Product */ 2059 std->len = sizeof(at91dci_product); 2060 std->ptr = USB_ADD_BYTES(&at91dci_product, 0); 2061 goto tr_valid; 2062 default: 2063 break; 2064 } 2065 break; 2066 default: 2067 goto tr_stalled; 2068 } 2069 goto tr_stalled; 2070 2071tr_handle_get_config: 2072 std->len = 1; 2073 sc->sc_hub_temp.wValue[0] = sc->sc_conf; 2074 goto tr_valid; 2075 2076tr_handle_get_status: 2077 std->len = 2; 2078 USETW(sc->sc_hub_temp.wValue, UDS_SELF_POWERED); 2079 goto tr_valid; 2080 2081tr_handle_set_address: 2082 if (value & 0xFF00) { 2083 goto tr_stalled; 2084 } 2085 sc->sc_rt_addr = value; 2086 goto tr_valid; 2087 2088tr_handle_set_config: 2089 if (value >= 2) { 2090 goto tr_stalled; 2091 } 2092 sc->sc_conf = value; 2093 goto tr_valid; 2094 2095tr_handle_get_interface: 2096 std->len = 1; 2097 sc->sc_hub_temp.wValue[0] = 0; 2098 goto tr_valid; 2099 2100tr_handle_get_tt_state: 2101tr_handle_get_class_status: 2102tr_handle_get_iface_status: 2103tr_handle_get_ep_status: 2104 std->len = 2; 2105 USETW(sc->sc_hub_temp.wValue, 0); 2106 goto tr_valid; 2107 2108tr_handle_set_halt: 2109tr_handle_set_interface: 2110tr_handle_set_wakeup: 2111tr_handle_clear_wakeup: 2112tr_handle_clear_halt: 2113 goto tr_valid; 2114 2115tr_handle_clear_port_feature: 2116 if (index != 1) { 2117 goto tr_stalled; 2118 } 2119 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE on port %d\n", index); 2120 2121 switch (value) { 2122 case UHF_PORT_SUSPEND: 2123 at91dci_wakeup_peer(sc); 2124 break; 2125 2126 case UHF_PORT_ENABLE: 2127 sc->sc_flags.port_enabled = 0; 2128 break; 2129 2130 case UHF_PORT_TEST: 2131 case UHF_PORT_INDICATOR: 2132 case UHF_C_PORT_ENABLE: 2133 case UHF_C_PORT_OVER_CURRENT: 2134 case UHF_C_PORT_RESET: 2135 /* nops */ 2136 break; 2137 case UHF_PORT_POWER: 2138 sc->sc_flags.port_powered = 0; 2139 at91dci_pull_down(sc); 2140 at91dci_clocks_off(sc); 2141 break; 2142 case UHF_C_PORT_CONNECTION: 2143 sc->sc_flags.change_connect = 0; 2144 break; 2145 case UHF_C_PORT_SUSPEND: 2146 sc->sc_flags.change_suspend = 0; 2147 break; 2148 default: 2149 std->err = USB_ERR_IOERROR; 2150 goto done; 2151 } 2152 goto tr_valid; 2153 2154tr_handle_set_port_feature: 2155 if (index != 1) { 2156 goto tr_stalled; 2157 } 2158 DPRINTFN(9, "UR_SET_PORT_FEATURE\n"); 2159 2160 switch (value) { 2161 case UHF_PORT_ENABLE: 2162 sc->sc_flags.port_enabled = 1; 2163 break; 2164 case UHF_PORT_SUSPEND: 2165 case UHF_PORT_RESET: 2166 case UHF_PORT_TEST: 2167 case UHF_PORT_INDICATOR: 2168 /* nops */ 2169 break; 2170 case UHF_PORT_POWER: 2171 sc->sc_flags.port_powered = 1; 2172 break; 2173 default: 2174 std->err = USB_ERR_IOERROR; 2175 goto done; 2176 } 2177 goto tr_valid; 2178 2179tr_handle_get_port_status: 2180 2181 DPRINTFN(9, "UR_GET_PORT_STATUS\n"); 2182 2183 if (index != 1) { 2184 goto tr_stalled; 2185 } 2186 if (sc->sc_flags.status_vbus) { 2187 at91dci_clocks_on(sc); 2188 at91dci_pull_up(sc); 2189 } else { 2190 at91dci_pull_down(sc); 2191 at91dci_clocks_off(sc); 2192 } 2193 2194 /* Select FULL-speed and Device Side Mode */ 2195 2196 value = UPS_PORT_MODE_DEVICE; 2197 2198 if (sc->sc_flags.port_powered) { 2199 value |= UPS_PORT_POWER; 2200 } 2201 if (sc->sc_flags.port_enabled) { 2202 value |= UPS_PORT_ENABLED; 2203 } 2204 if (sc->sc_flags.status_vbus && 2205 sc->sc_flags.status_bus_reset) { 2206 value |= UPS_CURRENT_CONNECT_STATUS; 2207 } 2208 if (sc->sc_flags.status_suspend) { 2209 value |= UPS_SUSPEND; 2210 } 2211 USETW(sc->sc_hub_temp.ps.wPortStatus, value); 2212 2213 value = 0; 2214 2215 if (sc->sc_flags.change_connect) { 2216 value |= UPS_C_CONNECT_STATUS; 2217 2218 if (sc->sc_flags.status_vbus && 2219 sc->sc_flags.status_bus_reset) { 2220 /* reset endpoint flags */ 2221 bzero(sc->sc_ep_flags, sizeof(sc->sc_ep_flags)); 2222 } 2223 } 2224 if (sc->sc_flags.change_suspend) { 2225 value |= UPS_C_SUSPEND; 2226 } 2227 USETW(sc->sc_hub_temp.ps.wPortChange, value); 2228 std->len = sizeof(sc->sc_hub_temp.ps); 2229 goto tr_valid; 2230 2231tr_handle_get_class_descriptor: 2232 if (value & 0xFF) { 2233 goto tr_stalled; 2234 } 2235 std->ptr = USB_ADD_BYTES(&at91dci_hubd, 0); 2236 std->len = sizeof(at91dci_hubd); 2237 goto tr_valid; 2238 2239tr_stalled: 2240 std->err = USB_ERR_STALLED; 2241tr_valid: 2242done: 2243 return; 2244} 2245 2246static void 2247at91dci_root_ctrl_poll(struct at91dci_softc *sc) 2248{ 2249 usb2_sw_transfer(&sc->sc_root_ctrl, 2250 &at91dci_root_ctrl_done); 2251} 2252 2253struct usb2_pipe_methods at91dci_root_ctrl_methods = 2254{ 2255 .open = at91dci_root_ctrl_open, 2256 .close = at91dci_root_ctrl_close, 2257 .enter = at91dci_root_ctrl_enter, 2258 .start = at91dci_root_ctrl_start, 2259 .enter_is_cancelable = 1, 2260 .start_is_cancelable = 0, 2261}; 2262 2263/*------------------------------------------------------------------------* 2264 * at91dci root interrupt support 2265 *------------------------------------------------------------------------*/ 2266static void 2267at91dci_root_intr_open(struct usb2_xfer *xfer) 2268{ 2269 return; 2270} 2271 2272static void 2273at91dci_root_intr_close(struct usb2_xfer *xfer) 2274{ 2275 struct at91dci_softc *sc = xfer->usb2_sc; 2276 2277 if (sc->sc_root_intr.xfer == xfer) { 2278 sc->sc_root_intr.xfer = NULL; 2279 } 2280 at91dci_device_done(xfer, USB_ERR_CANCELLED); 2281} 2282 2283static void 2284at91dci_root_intr_enter(struct usb2_xfer *xfer) 2285{ 2286 return; 2287} 2288 2289static void 2290at91dci_root_intr_start(struct usb2_xfer *xfer) 2291{ 2292 struct at91dci_softc *sc = xfer->usb2_sc; 2293 2294 sc->sc_root_intr.xfer = xfer; 2295} 2296 2297struct usb2_pipe_methods at91dci_root_intr_methods = 2298{ 2299 .open = at91dci_root_intr_open, 2300 .close = at91dci_root_intr_close, 2301 .enter = at91dci_root_intr_enter, 2302 .start = at91dci_root_intr_start, 2303 .enter_is_cancelable = 1, 2304 .start_is_cancelable = 1, 2305}; 2306 2307static void 2308at91dci_xfer_setup(struct usb2_setup_params *parm) 2309{ 2310 const struct usb2_hw_ep_profile *pf; 2311 struct at91dci_softc *sc; 2312 struct usb2_xfer *xfer; 2313 void *last_obj; 2314 uint32_t ntd; 2315 uint32_t n; 2316 uint8_t ep_no; 2317 2318 sc = AT9100_DCI_BUS2SC(parm->udev->bus); 2319 xfer = parm->curr_xfer; 2320 2321 /* 2322 * setup xfer 2323 */ 2324 xfer->usb2_sc = sc; 2325 2326 /* 2327 * NOTE: This driver does not use any of the parameters that 2328 * are computed from the following values. Just set some 2329 * reasonable dummies: 2330 */ 2331 parm->hc_max_packet_size = 0x500; 2332 parm->hc_max_packet_count = 1; 2333 parm->hc_max_frame_size = 0x500; 2334 2335 usb2_transfer_setup_sub(parm); 2336 2337 /* 2338 * compute maximum number of TDs 2339 */ 2340 if (parm->methods == &at91dci_device_ctrl_methods) { 2341 2342 ntd = xfer->nframes + 1 /* STATUS */ + 1 /* SYNC 1 */ 2343 + 1 /* SYNC 2 */ ; 2344 2345 } else if (parm->methods == &at91dci_device_bulk_methods) { 2346 2347 ntd = xfer->nframes + 1 /* SYNC */ ; 2348 2349 } else if (parm->methods == &at91dci_device_intr_methods) { 2350 2351 ntd = xfer->nframes + 1 /* SYNC */ ; 2352 2353 } else if (parm->methods == &at91dci_device_isoc_fs_methods) { 2354 2355 ntd = xfer->nframes + 1 /* SYNC */ ; 2356 2357 } else { 2358 2359 ntd = 0; 2360 } 2361 2362 /* 2363 * check if "usb2_transfer_setup_sub" set an error 2364 */ 2365 if (parm->err) { 2366 return; 2367 } 2368 /* 2369 * allocate transfer descriptors 2370 */ 2371 last_obj = NULL; 2372 2373 /* 2374 * get profile stuff 2375 */ 2376 if (ntd) { 2377 2378 ep_no = xfer->endpoint & UE_ADDR; 2379 at91dci_get_hw_ep_profile(parm->udev, &pf, ep_no); 2380 2381 if (pf == NULL) { 2382 /* should not happen */ 2383 parm->err = USB_ERR_INVAL; 2384 return; 2385 } 2386 } else { 2387 ep_no = 0; 2388 pf = NULL; 2389 } 2390 2391 /* align data */ 2392 parm->size[0] += ((-parm->size[0]) & (USB_HOST_ALIGN - 1)); 2393 2394 for (n = 0; n != ntd; n++) { 2395 2396 struct at91dci_td *td; 2397 2398 if (parm->buf) { 2399 2400 td = USB_ADD_BYTES(parm->buf, parm->size[0]); 2401 2402 /* init TD */ 2403 td->io_tag = sc->sc_io_tag; 2404 td->io_hdl = sc->sc_io_hdl; 2405 td->max_packet_size = xfer->max_packet_size; 2406 td->status_reg = AT91_UDP_CSR(ep_no); 2407 td->fifo_reg = AT91_UDP_FDR(ep_no); 2408 if (pf->support_multi_buffer) { 2409 td->support_multi_buffer = 1; 2410 } 2411 td->obj_next = last_obj; 2412 2413 last_obj = td; 2414 } 2415 parm->size[0] += sizeof(*td); 2416 } 2417 2418 xfer->td_start[0] = last_obj; 2419} 2420 2421static void 2422at91dci_xfer_unsetup(struct usb2_xfer *xfer) 2423{ 2424 return; 2425} 2426 2427static void 2428at91dci_pipe_init(struct usb2_device *udev, struct usb2_endpoint_descriptor *edesc, 2429 struct usb2_pipe *pipe) 2430{ 2431 struct at91dci_softc *sc = AT9100_DCI_BUS2SC(udev->bus); 2432 2433 DPRINTFN(2, "pipe=%p, addr=%d, endpt=%d, mode=%d (%d)\n", 2434 pipe, udev->address, 2435 edesc->bEndpointAddress, udev->flags.usb2_mode, 2436 sc->sc_rt_addr); 2437 2438 if (udev->device_index == sc->sc_rt_addr) { 2439 2440 if (udev->flags.usb2_mode != USB_MODE_HOST) { 2441 /* not supported */ 2442 return; 2443 } 2444 switch (edesc->bEndpointAddress) { 2445 case USB_CONTROL_ENDPOINT: 2446 pipe->methods = &at91dci_root_ctrl_methods; 2447 break; 2448 case UE_DIR_IN | AT9100_DCI_INTR_ENDPT: 2449 pipe->methods = &at91dci_root_intr_methods; 2450 break; 2451 default: 2452 /* do nothing */ 2453 break; 2454 } 2455 } else { 2456 2457 if (udev->flags.usb2_mode != USB_MODE_DEVICE) { 2458 /* not supported */ 2459 return; 2460 } 2461 if (udev->speed != USB_SPEED_FULL) { 2462 /* not supported */ 2463 return; 2464 } 2465 switch (edesc->bmAttributes & UE_XFERTYPE) { 2466 case UE_CONTROL: 2467 pipe->methods = &at91dci_device_ctrl_methods; 2468 break; 2469 case UE_INTERRUPT: 2470 pipe->methods = &at91dci_device_intr_methods; 2471 break; 2472 case UE_ISOCHRONOUS: 2473 pipe->methods = &at91dci_device_isoc_fs_methods; 2474 break; 2475 case UE_BULK: 2476 pipe->methods = &at91dci_device_bulk_methods; 2477 break; 2478 default: 2479 /* do nothing */ 2480 break; 2481 } 2482 } 2483} 2484 2485struct usb2_bus_methods at91dci_bus_methods = 2486{ 2487 .pipe_init = &at91dci_pipe_init, 2488 .xfer_setup = &at91dci_xfer_setup, 2489 .xfer_unsetup = &at91dci_xfer_unsetup, 2490 .do_poll = &at91dci_do_poll, 2491 .get_hw_ep_profile = &at91dci_get_hw_ep_profile, 2492 .set_stall = &at91dci_set_stall, 2493 .clear_stall = &at91dci_clear_stall, 2494 .vbus_interrupt = &at91dci_vbus_interrupt, 2495 .rem_wakeup_set = &at91dci_rem_wakeup_set, 2496}; 2497