at91dci.c revision 185950
1#include <sys/cdefs.h> 2__FBSDID("$FreeBSD: head/sys/dev/usb2/controller/at91dci.c 185950 2008-12-11 23:17:48Z thompsa $"); 3 4/*- 5 * Copyright (c) 2007-2008 Hans Petter Selasky. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29/* 30 * This file contains the driver for the AT91 series USB Device 31 * Controller 32 */ 33 34/* 35 * Thanks to "David Brownell" for helping out regarding the hardware 36 * endpoint profiles. 37 */ 38 39/* 40 * NOTE: The "fifo_bank" is not reset in hardware when the endpoint is 41 * reset ! 42 * 43 * NOTE: When the chip detects BUS-reset it will also reset the 44 * endpoints, Function-address and more. 45 */ 46 47#include <dev/usb2/include/usb2_standard.h> 48#include <dev/usb2/include/usb2_mfunc.h> 49#include <dev/usb2/include/usb2_error.h> 50#include <dev/usb2/include/usb2_defs.h> 51 52#define USB_DEBUG_VAR at91dcidebug 53#define usb2_config_td_cc at91dci_config_copy 54#define usb2_config_td_softc at91dci_softc 55 56#include <dev/usb2/core/usb2_core.h> 57#include <dev/usb2/core/usb2_debug.h> 58#include <dev/usb2/core/usb2_busdma.h> 59#include <dev/usb2/core/usb2_process.h> 60#include <dev/usb2/core/usb2_config_td.h> 61#include <dev/usb2/core/usb2_sw_transfer.h> 62#include <dev/usb2/core/usb2_transfer.h> 63#include <dev/usb2/core/usb2_device.h> 64#include <dev/usb2/core/usb2_hub.h> 65#include <dev/usb2/core/usb2_util.h> 66 67#include <dev/usb2/controller/usb2_controller.h> 68#include <dev/usb2/controller/usb2_bus.h> 69#include <dev/usb2/controller/at91dci.h> 70 71#define AT9100_DCI_BUS2SC(bus) \ 72 ((struct at91dci_softc *)(((uint8_t *)(bus)) - \ 73 USB_P2U(&(((struct at91dci_softc *)0)->sc_bus)))) 74 75#define AT9100_DCI_PC2SC(pc) \ 76 AT9100_DCI_BUS2SC((pc)->tag_parent->info->bus) 77 78#if USB_DEBUG 79static int at91dcidebug = 0; 80 81SYSCTL_NODE(_hw_usb2, OID_AUTO, at91dci, CTLFLAG_RW, 0, "USB at91dci"); 82SYSCTL_INT(_hw_usb2_at91dci, OID_AUTO, debug, CTLFLAG_RW, 83 &at91dcidebug, 0, "at91dci debug level"); 84#endif 85 86#define AT9100_DCI_INTR_ENDPT 1 87 88/* prototypes */ 89 90struct usb2_bus_methods at91dci_bus_methods; 91struct usb2_pipe_methods at91dci_device_bulk_methods; 92struct usb2_pipe_methods at91dci_device_ctrl_methods; 93struct usb2_pipe_methods at91dci_device_intr_methods; 94struct usb2_pipe_methods at91dci_device_isoc_fs_methods; 95struct usb2_pipe_methods at91dci_root_ctrl_methods; 96struct usb2_pipe_methods at91dci_root_intr_methods; 97 98static at91dci_cmd_t at91dci_setup_rx; 99static at91dci_cmd_t at91dci_data_rx; 100static at91dci_cmd_t at91dci_data_tx; 101static at91dci_cmd_t at91dci_data_tx_sync; 102static void at91dci_device_done(struct usb2_xfer *, usb2_error_t); 103static void at91dci_do_poll(struct usb2_bus *); 104static void at91dci_root_ctrl_poll(struct at91dci_softc *); 105static void at91dci_standard_done(struct usb2_xfer *); 106 107static usb2_sw_transfer_func_t at91dci_root_intr_done; 108static usb2_sw_transfer_func_t at91dci_root_ctrl_done; 109static usb2_config_td_command_t at91dci_root_ctrl_task; 110 111/* 112 * NOTE: Some of the bits in the CSR register have inverse meaning so 113 * we need a helper macro when acknowledging events: 114 */ 115#define AT91_CSR_ACK(csr, what) do { \ 116 (csr) &= ~((AT91_UDP_CSR_FORCESTALL| \ 117 AT91_UDP_CSR_TXPKTRDY| \ 118 AT91_UDP_CSR_RXBYTECNT) ^ (what));\ 119 (csr) |= ((AT91_UDP_CSR_RX_DATA_BK0| \ 120 AT91_UDP_CSR_RX_DATA_BK1| \ 121 AT91_UDP_CSR_TXCOMP| \ 122 AT91_UDP_CSR_RXSETUP| \ 123 AT91_UDP_CSR_STALLSENT) ^ (what)); \ 124} while (0) 125 126/* 127 * Here is a list of what the chip supports. 128 * Probably it supports more than listed here! 129 */ 130static const struct usb2_hw_ep_profile 131 at91dci_ep_profile[AT91_UDP_EP_MAX] = { 132 133 [0] = { 134 .max_in_frame_size = 8, 135 .max_out_frame_size = 8, 136 .is_simplex = 1, 137 .support_control = 1, 138 }, 139 [1] = { 140 .max_in_frame_size = 64, 141 .max_out_frame_size = 64, 142 .is_simplex = 1, 143 .support_multi_buffer = 1, 144 .support_bulk = 1, 145 .support_interrupt = 1, 146 .support_isochronous = 1, 147 .support_in = 1, 148 .support_out = 1, 149 }, 150 [2] = { 151 .max_in_frame_size = 64, 152 .max_out_frame_size = 64, 153 .is_simplex = 1, 154 .support_multi_buffer = 1, 155 .support_bulk = 1, 156 .support_interrupt = 1, 157 .support_isochronous = 1, 158 .support_in = 1, 159 .support_out = 1, 160 }, 161 [3] = { 162 /* can also do BULK */ 163 .max_in_frame_size = 8, 164 .max_out_frame_size = 8, 165 .is_simplex = 1, 166 .support_interrupt = 1, 167 .support_in = 1, 168 .support_out = 1, 169 }, 170 [4] = { 171 .max_in_frame_size = 256, 172 .max_out_frame_size = 256, 173 .is_simplex = 1, 174 .support_multi_buffer = 1, 175 .support_bulk = 1, 176 .support_interrupt = 1, 177 .support_isochronous = 1, 178 .support_in = 1, 179 .support_out = 1, 180 }, 181 [5] = { 182 .max_in_frame_size = 256, 183 .max_out_frame_size = 256, 184 .is_simplex = 1, 185 .support_multi_buffer = 1, 186 .support_bulk = 1, 187 .support_interrupt = 1, 188 .support_isochronous = 1, 189 .support_in = 1, 190 .support_out = 1, 191 }, 192}; 193 194static void 195at91dci_get_hw_ep_profile(struct usb2_device *udev, 196 const struct usb2_hw_ep_profile **ppf, uint8_t ep_addr) 197{ 198 if (ep_addr < AT91_UDP_EP_MAX) { 199 *ppf = (at91dci_ep_profile + ep_addr); 200 } else { 201 *ppf = NULL; 202 } 203} 204 205static void 206at91dci_clocks_on(struct at91dci_softc *sc) 207{ 208 if (sc->sc_flags.clocks_off && 209 sc->sc_flags.port_powered) { 210 211 DPRINTFN(5, "\n"); 212 213 if (sc->sc_clocks_on) { 214 (sc->sc_clocks_on) (sc->sc_clocks_arg); 215 } 216 sc->sc_flags.clocks_off = 0; 217 218 /* enable Transceiver */ 219 AT91_UDP_WRITE_4(sc, AT91_UDP_TXVC, 0); 220 } 221} 222 223static void 224at91dci_clocks_off(struct at91dci_softc *sc) 225{ 226 if (!sc->sc_flags.clocks_off) { 227 228 DPRINTFN(5, "\n"); 229 230 /* disable Transceiver */ 231 AT91_UDP_WRITE_4(sc, AT91_UDP_TXVC, AT91_UDP_TXVC_DIS); 232 233 if (sc->sc_clocks_off) { 234 (sc->sc_clocks_off) (sc->sc_clocks_arg); 235 } 236 sc->sc_flags.clocks_off = 1; 237 } 238} 239 240static void 241at91dci_pull_up(struct at91dci_softc *sc) 242{ 243 /* pullup D+, if possible */ 244 245 if (!sc->sc_flags.d_pulled_up && 246 sc->sc_flags.port_powered) { 247 sc->sc_flags.d_pulled_up = 1; 248 (sc->sc_pull_up) (sc->sc_pull_arg); 249 } 250} 251 252static void 253at91dci_pull_down(struct at91dci_softc *sc) 254{ 255 /* pulldown D+, if possible */ 256 257 if (sc->sc_flags.d_pulled_up) { 258 sc->sc_flags.d_pulled_up = 0; 259 (sc->sc_pull_down) (sc->sc_pull_arg); 260 } 261} 262 263static void 264at91dci_wakeup_peer(struct at91dci_softc *sc) 265{ 266 uint32_t temp; 267 268 if (!(sc->sc_flags.status_suspend)) { 269 return; 270 } 271 temp = AT91_UDP_READ_4(sc, AT91_UDP_GSTATE); 272 273 if (!(temp & AT91_UDP_GSTATE_ESR)) { 274 return; 275 } 276 AT91_UDP_WRITE_4(sc, AT91_UDP_GSTATE, temp); 277} 278 279static void 280at91dci_rem_wakeup_set(struct usb2_device *udev, uint8_t is_on) 281{ 282 struct at91dci_softc *sc; 283 uint32_t temp; 284 285 DPRINTFN(5, "is_on=%u\n", is_on); 286 287 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 288 289 sc = AT9100_DCI_BUS2SC(udev->bus); 290 291 temp = AT91_UDP_READ_4(sc, AT91_UDP_GSTATE); 292 293 if (is_on) { 294 temp |= AT91_UDP_GSTATE_ESR; 295 } else { 296 temp &= ~AT91_UDP_GSTATE_ESR; 297 } 298 299 AT91_UDP_WRITE_4(sc, AT91_UDP_GSTATE, temp); 300} 301 302static void 303at91dci_set_address(struct at91dci_softc *sc, uint8_t addr) 304{ 305 DPRINTFN(5, "addr=%d\n", addr); 306 307 AT91_UDP_WRITE_4(sc, AT91_UDP_FADDR, addr | 308 AT91_UDP_FADDR_EN); 309} 310 311static uint8_t 312at91dci_setup_rx(struct at91dci_td *td) 313{ 314 struct at91dci_softc *sc; 315 struct usb2_device_request req; 316 uint32_t csr; 317 uint32_t temp; 318 uint16_t count; 319 320 /* read out FIFO status */ 321 csr = bus_space_read_4(td->io_tag, td->io_hdl, 322 td->status_reg); 323 324 DPRINTFN(5, "csr=0x%08x rem=%u\n", csr, td->remainder); 325 326 temp = csr; 327 temp &= (AT91_UDP_CSR_RX_DATA_BK0 | 328 AT91_UDP_CSR_RX_DATA_BK1 | 329 AT91_UDP_CSR_STALLSENT | 330 AT91_UDP_CSR_RXSETUP | 331 AT91_UDP_CSR_TXCOMP); 332 333 if (!(csr & AT91_UDP_CSR_RXSETUP)) { 334 /* abort any ongoing transfer */ 335 if (!td->did_stall) { 336 DPRINTFN(5, "stalling\n"); 337 temp |= AT91_UDP_CSR_FORCESTALL; 338 td->did_stall = 1; 339 } 340 goto not_complete; 341 } 342 /* get the packet byte count */ 343 count = (csr & AT91_UDP_CSR_RXBYTECNT) >> 16; 344 345 /* verify data length */ 346 if (count != td->remainder) { 347 DPRINTFN(0, "Invalid SETUP packet " 348 "length, %d bytes\n", count); 349 goto not_complete; 350 } 351 if (count != sizeof(req)) { 352 DPRINTFN(0, "Unsupported SETUP packet " 353 "length, %d bytes\n", count); 354 goto not_complete; 355 } 356 /* receive data */ 357 bus_space_read_multi_1(td->io_tag, td->io_hdl, 358 td->fifo_reg, (void *)&req, sizeof(req)); 359 360 /* copy data into real buffer */ 361 usb2_copy_in(td->pc, 0, &req, sizeof(req)); 362 363 td->offset = sizeof(req); 364 td->remainder = 0; 365 366 /* get pointer to softc */ 367 sc = AT9100_DCI_PC2SC(td->pc); 368 369 /* sneak peek the set address */ 370 if ((req.bmRequestType == UT_WRITE_DEVICE) && 371 (req.bRequest == UR_SET_ADDRESS)) { 372 sc->sc_dv_addr = req.wValue[0] & 0x7F; 373 } else { 374 sc->sc_dv_addr = 0xFF; 375 } 376 377 /* sneak peek the endpoint direction */ 378 if (req.bmRequestType & UE_DIR_IN) { 379 csr |= AT91_UDP_CSR_DIR; 380 } else { 381 csr &= ~AT91_UDP_CSR_DIR; 382 } 383 384 /* write the direction of the control transfer */ 385 AT91_CSR_ACK(csr, temp); 386 bus_space_write_4(td->io_tag, td->io_hdl, 387 td->status_reg, csr); 388 return (0); /* complete */ 389 390not_complete: 391 /* clear interrupts, if any */ 392 if (temp) { 393 DPRINTFN(5, "clearing 0x%08x\n", temp); 394 AT91_CSR_ACK(csr, temp); 395 bus_space_write_4(td->io_tag, td->io_hdl, 396 td->status_reg, csr); 397 } 398 return (1); /* not complete */ 399 400} 401 402static uint8_t 403at91dci_data_rx(struct at91dci_td *td) 404{ 405 struct usb2_page_search buf_res; 406 uint32_t csr; 407 uint32_t temp; 408 uint16_t count; 409 uint8_t to; 410 uint8_t got_short; 411 412 to = 2; /* don't loop forever! */ 413 got_short = 0; 414 415 /* check if any of the FIFO banks have data */ 416repeat: 417 /* read out FIFO status */ 418 csr = bus_space_read_4(td->io_tag, td->io_hdl, 419 td->status_reg); 420 421 DPRINTFN(5, "csr=0x%08x rem=%u\n", csr, td->remainder); 422 423 if (csr & AT91_UDP_CSR_RXSETUP) { 424 if (td->remainder == 0) { 425 /* 426 * We are actually complete and have 427 * received the next SETUP 428 */ 429 DPRINTFN(5, "faking complete\n"); 430 return (0); /* complete */ 431 } 432 /* 433 * USB Host Aborted the transfer. 434 */ 435 td->error = 1; 436 return (0); /* complete */ 437 } 438 /* Make sure that "STALLSENT" gets cleared */ 439 temp = csr; 440 temp &= AT91_UDP_CSR_STALLSENT; 441 442 /* check status */ 443 if (!(csr & (AT91_UDP_CSR_RX_DATA_BK0 | 444 AT91_UDP_CSR_RX_DATA_BK1))) { 445 if (temp) { 446 /* write command */ 447 AT91_CSR_ACK(csr, temp); 448 bus_space_write_4(td->io_tag, td->io_hdl, 449 td->status_reg, csr); 450 } 451 return (1); /* not complete */ 452 } 453 /* get the packet byte count */ 454 count = (csr & AT91_UDP_CSR_RXBYTECNT) >> 16; 455 456 /* verify the packet byte count */ 457 if (count != td->max_packet_size) { 458 if (count < td->max_packet_size) { 459 /* we have a short packet */ 460 td->short_pkt = 1; 461 got_short = 1; 462 } else { 463 /* invalid USB packet */ 464 td->error = 1; 465 return (0); /* we are complete */ 466 } 467 } 468 /* verify the packet byte count */ 469 if (count > td->remainder) { 470 /* invalid USB packet */ 471 td->error = 1; 472 return (0); /* we are complete */ 473 } 474 while (count > 0) { 475 usb2_get_page(td->pc, td->offset, &buf_res); 476 477 /* get correct length */ 478 if (buf_res.length > count) { 479 buf_res.length = count; 480 } 481 /* receive data */ 482 bus_space_read_multi_1(td->io_tag, td->io_hdl, 483 td->fifo_reg, buf_res.buffer, buf_res.length); 484 485 /* update counters */ 486 count -= buf_res.length; 487 td->offset += buf_res.length; 488 td->remainder -= buf_res.length; 489 } 490 491 /* clear status bits */ 492 if (td->support_multi_buffer) { 493 if (td->fifo_bank) { 494 td->fifo_bank = 0; 495 temp |= AT91_UDP_CSR_RX_DATA_BK1; 496 } else { 497 td->fifo_bank = 1; 498 temp |= AT91_UDP_CSR_RX_DATA_BK0; 499 } 500 } else { 501 temp |= (AT91_UDP_CSR_RX_DATA_BK0 | 502 AT91_UDP_CSR_RX_DATA_BK1); 503 } 504 505 /* write command */ 506 AT91_CSR_ACK(csr, temp); 507 bus_space_write_4(td->io_tag, td->io_hdl, 508 td->status_reg, csr); 509 510 /* 511 * NOTE: We may have to delay a little bit before 512 * proceeding after clearing the DATA_BK bits. 513 */ 514 515 /* check if we are complete */ 516 if ((td->remainder == 0) || got_short) { 517 if (td->short_pkt) { 518 /* we are complete */ 519 return (0); 520 } 521 /* else need to receive a zero length packet */ 522 } 523 if (--to) { 524 goto repeat; 525 } 526 return (1); /* not complete */ 527} 528 529static uint8_t 530at91dci_data_tx(struct at91dci_td *td) 531{ 532 struct usb2_page_search buf_res; 533 uint32_t csr; 534 uint32_t temp; 535 uint16_t count; 536 uint8_t to; 537 538 to = 2; /* don't loop forever! */ 539 540repeat: 541 542 /* read out FIFO status */ 543 csr = bus_space_read_4(td->io_tag, td->io_hdl, 544 td->status_reg); 545 546 DPRINTFN(5, "csr=0x%08x rem=%u\n", csr, td->remainder); 547 548 if (csr & AT91_UDP_CSR_RXSETUP) { 549 /* 550 * The current transfer was aborted 551 * by the USB Host 552 */ 553 td->error = 1; 554 return (0); /* complete */ 555 } 556 /* Make sure that "STALLSENT" gets cleared */ 557 temp = csr; 558 temp &= AT91_UDP_CSR_STALLSENT; 559 560 if (csr & AT91_UDP_CSR_TXPKTRDY) { 561 if (temp) { 562 /* write command */ 563 AT91_CSR_ACK(csr, temp); 564 bus_space_write_4(td->io_tag, td->io_hdl, 565 td->status_reg, csr); 566 } 567 return (1); /* not complete */ 568 } else { 569 /* clear TXCOMP and set TXPKTRDY */ 570 temp |= (AT91_UDP_CSR_TXCOMP | 571 AT91_UDP_CSR_TXPKTRDY); 572 } 573 574 count = td->max_packet_size; 575 if (td->remainder < count) { 576 /* we have a short packet */ 577 td->short_pkt = 1; 578 count = td->remainder; 579 } 580 while (count > 0) { 581 582 usb2_get_page(td->pc, td->offset, &buf_res); 583 584 /* get correct length */ 585 if (buf_res.length > count) { 586 buf_res.length = count; 587 } 588 /* transmit data */ 589 bus_space_write_multi_1(td->io_tag, td->io_hdl, 590 td->fifo_reg, buf_res.buffer, buf_res.length); 591 592 /* update counters */ 593 count -= buf_res.length; 594 td->offset += buf_res.length; 595 td->remainder -= buf_res.length; 596 } 597 598 /* write command */ 599 AT91_CSR_ACK(csr, temp); 600 bus_space_write_4(td->io_tag, td->io_hdl, 601 td->status_reg, csr); 602 603 /* check remainder */ 604 if (td->remainder == 0) { 605 if (td->short_pkt) { 606 return (0); /* complete */ 607 } 608 /* else we need to transmit a short packet */ 609 } 610 if (--to) { 611 goto repeat; 612 } 613 return (1); /* not complete */ 614} 615 616static uint8_t 617at91dci_data_tx_sync(struct at91dci_td *td) 618{ 619 struct at91dci_softc *sc; 620 uint32_t csr; 621 uint32_t temp; 622 623#if 0 624repeat: 625#endif 626 627 /* read out FIFO status */ 628 csr = bus_space_read_4(td->io_tag, td->io_hdl, 629 td->status_reg); 630 631 DPRINTFN(5, "csr=0x%08x\n", csr); 632 633 if (csr & AT91_UDP_CSR_RXSETUP) { 634 DPRINTFN(5, "faking complete\n"); 635 /* Race condition */ 636 return (0); /* complete */ 637 } 638 temp = csr; 639 temp &= (AT91_UDP_CSR_STALLSENT | 640 AT91_UDP_CSR_TXCOMP); 641 642 /* check status */ 643 if (csr & AT91_UDP_CSR_TXPKTRDY) { 644 goto not_complete; 645 } 646 if (!(csr & AT91_UDP_CSR_TXCOMP)) { 647 goto not_complete; 648 } 649 sc = AT9100_DCI_PC2SC(td->pc); 650 if (sc->sc_dv_addr != 0xFF) { 651 /* 652 * The AT91 has a special requirement with regard to 653 * setting the address and that is to write the new 654 * address before clearing TXCOMP: 655 */ 656 at91dci_set_address(sc, sc->sc_dv_addr); 657 } 658 /* write command */ 659 AT91_CSR_ACK(csr, temp); 660 bus_space_write_4(td->io_tag, td->io_hdl, 661 td->status_reg, csr); 662 663 return (0); /* complete */ 664 665not_complete: 666 if (temp) { 667 /* write command */ 668 AT91_CSR_ACK(csr, temp); 669 bus_space_write_4(td->io_tag, td->io_hdl, 670 td->status_reg, csr); 671 } 672 return (1); /* not complete */ 673} 674 675static uint8_t 676at91dci_xfer_do_fifo(struct usb2_xfer *xfer) 677{ 678 struct at91dci_softc *sc; 679 struct at91dci_td *td; 680 uint8_t temp; 681 682 DPRINTFN(9, "\n"); 683 684 td = xfer->td_transfer_cache; 685 while (1) { 686 if ((td->func) (td)) { 687 /* operation in progress */ 688 break; 689 } 690 if (((void *)td) == xfer->td_transfer_last) { 691 goto done; 692 } 693 if (td->error) { 694 goto done; 695 } else if (td->remainder > 0) { 696 /* 697 * We had a short transfer. If there is no alternate 698 * next, stop processing ! 699 */ 700 if (!td->alt_next) { 701 goto done; 702 } 703 } 704 /* 705 * Fetch the next transfer descriptor and transfer 706 * some flags to the next transfer descriptor 707 */ 708 temp = 0; 709 if (td->fifo_bank) 710 temp |= 1; 711 td = td->obj_next; 712 xfer->td_transfer_cache = td; 713 if (temp & 1) 714 td->fifo_bank = 1; 715 } 716 return (1); /* not complete */ 717 718done: 719 sc = xfer->usb2_sc; 720 temp = (xfer->endpoint & UE_ADDR); 721 722 /* update FIFO bank flag and multi buffer */ 723 if (td->fifo_bank) { 724 sc->sc_ep_flags[temp].fifo_bank = 1; 725 } else { 726 sc->sc_ep_flags[temp].fifo_bank = 0; 727 } 728 729 /* compute all actual lengths */ 730 731 at91dci_standard_done(xfer); 732 733 return (0); /* complete */ 734} 735 736static void 737at91dci_interrupt_poll(struct at91dci_softc *sc) 738{ 739 struct usb2_xfer *xfer; 740 741repeat: 742 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 743 if (!at91dci_xfer_do_fifo(xfer)) { 744 /* queue has been modified */ 745 goto repeat; 746 } 747 } 748} 749 750static void 751at91dci_vbus_interrupt(struct usb2_bus *bus, uint8_t is_on) 752{ 753 struct at91dci_softc *sc = AT9100_DCI_BUS2SC(bus); 754 755 DPRINTFN(5, "vbus = %u\n", is_on); 756 757 USB_BUS_LOCK(&sc->sc_bus); 758 if (is_on) { 759 if (!sc->sc_flags.status_vbus) { 760 sc->sc_flags.status_vbus = 1; 761 762 /* complete root HUB interrupt endpoint */ 763 764 usb2_sw_transfer(&sc->sc_root_intr, 765 &at91dci_root_intr_done); 766 } 767 } else { 768 if (sc->sc_flags.status_vbus) { 769 sc->sc_flags.status_vbus = 0; 770 sc->sc_flags.status_bus_reset = 0; 771 sc->sc_flags.status_suspend = 0; 772 sc->sc_flags.change_suspend = 0; 773 sc->sc_flags.change_connect = 1; 774 775 /* complete root HUB interrupt endpoint */ 776 777 usb2_sw_transfer(&sc->sc_root_intr, 778 &at91dci_root_intr_done); 779 } 780 } 781 782 USB_BUS_UNLOCK(&sc->sc_bus); 783} 784 785void 786at91dci_interrupt(struct at91dci_softc *sc) 787{ 788 uint32_t status; 789 790 USB_BUS_LOCK(&sc->sc_bus); 791 792 status = AT91_UDP_READ_4(sc, AT91_UDP_ISR); 793 status &= AT91_UDP_INT_DEFAULT; 794 795 if (!status) { 796 USB_BUS_UNLOCK(&sc->sc_bus); 797 return; 798 } 799 /* acknowledge interrupts */ 800 801 AT91_UDP_WRITE_4(sc, AT91_UDP_ICR, status); 802 803 /* check for any bus state change interrupts */ 804 805 if (status & AT91_UDP_INT_BUS) { 806 807 DPRINTFN(5, "real bus interrupt 0x%08x\n", status); 808 809 if (status & AT91_UDP_INT_END_BR) { 810 811 /* set correct state */ 812 sc->sc_flags.status_bus_reset = 1; 813 sc->sc_flags.status_suspend = 0; 814 sc->sc_flags.change_suspend = 0; 815 sc->sc_flags.change_connect = 1; 816 817 /* disable resume interrupt */ 818 AT91_UDP_WRITE_4(sc, AT91_UDP_IDR, 819 AT91_UDP_INT_RXRSM); 820 /* enable suspend interrupt */ 821 AT91_UDP_WRITE_4(sc, AT91_UDP_IER, 822 AT91_UDP_INT_RXSUSP); 823 } 824 /* 825 * If RXRSM and RXSUSP is set at the same time we interpret 826 * that like RESUME. Resume is set when there is at least 3 827 * milliseconds of inactivity on the USB BUS. 828 */ 829 if (status & AT91_UDP_INT_RXRSM) { 830 if (sc->sc_flags.status_suspend) { 831 sc->sc_flags.status_suspend = 0; 832 sc->sc_flags.change_suspend = 1; 833 834 /* disable resume interrupt */ 835 AT91_UDP_WRITE_4(sc, AT91_UDP_IDR, 836 AT91_UDP_INT_RXRSM); 837 /* enable suspend interrupt */ 838 AT91_UDP_WRITE_4(sc, AT91_UDP_IER, 839 AT91_UDP_INT_RXSUSP); 840 } 841 } else if (status & AT91_UDP_INT_RXSUSP) { 842 if (!sc->sc_flags.status_suspend) { 843 sc->sc_flags.status_suspend = 1; 844 sc->sc_flags.change_suspend = 1; 845 846 /* disable suspend interrupt */ 847 AT91_UDP_WRITE_4(sc, AT91_UDP_IDR, 848 AT91_UDP_INT_RXSUSP); 849 850 /* enable resume interrupt */ 851 AT91_UDP_WRITE_4(sc, AT91_UDP_IER, 852 AT91_UDP_INT_RXRSM); 853 } 854 } 855 /* complete root HUB interrupt endpoint */ 856 857 usb2_sw_transfer(&sc->sc_root_intr, 858 &at91dci_root_intr_done); 859 } 860 /* check for any endpoint interrupts */ 861 862 if (status & AT91_UDP_INT_EPS) { 863 864 DPRINTFN(5, "real endpoint interrupt 0x%08x\n", status); 865 866 at91dci_interrupt_poll(sc); 867 } 868 USB_BUS_UNLOCK(&sc->sc_bus); 869} 870 871static void 872at91dci_setup_standard_chain_sub(struct at91dci_std_temp *temp) 873{ 874 struct at91dci_td *td; 875 876 /* get current Transfer Descriptor */ 877 td = temp->td_next; 878 temp->td = td; 879 880 /* prepare for next TD */ 881 temp->td_next = td->obj_next; 882 883 /* fill out the Transfer Descriptor */ 884 td->func = temp->func; 885 td->pc = temp->pc; 886 td->offset = temp->offset; 887 td->remainder = temp->len; 888 td->fifo_bank = 0; 889 td->error = 0; 890 td->did_stall = 0; 891 td->short_pkt = temp->short_pkt; 892 td->alt_next = temp->setup_alt_next; 893} 894 895static void 896at91dci_setup_standard_chain(struct usb2_xfer *xfer) 897{ 898 struct at91dci_std_temp temp; 899 struct at91dci_softc *sc; 900 struct at91dci_td *td; 901 uint32_t x; 902 uint8_t ep_no; 903 uint8_t need_sync; 904 905 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n", 906 xfer->address, UE_GET_ADDR(xfer->endpoint), 907 xfer->sumlen, usb2_get_speed(xfer->udev)); 908 909 temp.max_frame_size = xfer->max_frame_size; 910 911 td = xfer->td_start[0]; 912 xfer->td_transfer_first = td; 913 xfer->td_transfer_cache = td; 914 915 /* setup temp */ 916 917 temp.td = NULL; 918 temp.td_next = xfer->td_start[0]; 919 temp.setup_alt_next = xfer->flags_int.short_frames_ok; 920 temp.offset = 0; 921 922 sc = xfer->usb2_sc; 923 ep_no = (xfer->endpoint & UE_ADDR); 924 925 /* check if we should prepend a setup message */ 926 927 if (xfer->flags_int.control_xfr) { 928 if (xfer->flags_int.control_hdr) { 929 930 temp.func = &at91dci_setup_rx; 931 temp.len = xfer->frlengths[0]; 932 temp.pc = xfer->frbuffers + 0; 933 temp.short_pkt = temp.len ? 1 : 0; 934 935 at91dci_setup_standard_chain_sub(&temp); 936 } 937 x = 1; 938 } else { 939 x = 0; 940 } 941 942 if (x != xfer->nframes) { 943 if (xfer->endpoint & UE_DIR_IN) { 944 temp.func = &at91dci_data_tx; 945 need_sync = 1; 946 } else { 947 temp.func = &at91dci_data_rx; 948 need_sync = 0; 949 } 950 951 /* setup "pc" pointer */ 952 temp.pc = xfer->frbuffers + x; 953 } else { 954 need_sync = 0; 955 } 956 while (x != xfer->nframes) { 957 958 /* DATA0 / DATA1 message */ 959 960 temp.len = xfer->frlengths[x]; 961 962 x++; 963 964 if (x == xfer->nframes) { 965 temp.setup_alt_next = 0; 966 } 967 if (temp.len == 0) { 968 969 /* make sure that we send an USB packet */ 970 971 temp.short_pkt = 0; 972 973 } else { 974 975 /* regular data transfer */ 976 977 temp.short_pkt = (xfer->flags.force_short_xfer) ? 0 : 1; 978 } 979 980 at91dci_setup_standard_chain_sub(&temp); 981 982 if (xfer->flags_int.isochronous_xfr) { 983 temp.offset += temp.len; 984 } else { 985 /* get next Page Cache pointer */ 986 temp.pc = xfer->frbuffers + x; 987 } 988 } 989 990 /* always setup a valid "pc" pointer for status and sync */ 991 temp.pc = xfer->frbuffers + 0; 992 993 /* check if we need to sync */ 994 if (need_sync && xfer->flags_int.control_xfr) { 995 996 /* we need a SYNC point after TX */ 997 temp.func = &at91dci_data_tx_sync; 998 temp.len = 0; 999 temp.short_pkt = 0; 1000 1001 at91dci_setup_standard_chain_sub(&temp); 1002 } 1003 /* check if we should append a status stage */ 1004 if (xfer->flags_int.control_xfr && 1005 !xfer->flags_int.control_act) { 1006 1007 /* 1008 * Send a DATA1 message and invert the current 1009 * endpoint direction. 1010 */ 1011 if (xfer->endpoint & UE_DIR_IN) { 1012 temp.func = &at91dci_data_rx; 1013 need_sync = 0; 1014 } else { 1015 temp.func = &at91dci_data_tx; 1016 need_sync = 1; 1017 } 1018 temp.len = 0; 1019 temp.short_pkt = 0; 1020 1021 at91dci_setup_standard_chain_sub(&temp); 1022 if (need_sync) { 1023 /* we need a SYNC point after TX */ 1024 temp.func = &at91dci_data_tx_sync; 1025 temp.len = 0; 1026 temp.short_pkt = 0; 1027 1028 at91dci_setup_standard_chain_sub(&temp); 1029 } 1030 } 1031 /* must have at least one frame! */ 1032 td = temp.td; 1033 xfer->td_transfer_last = td; 1034 1035 /* setup the correct fifo bank */ 1036 if (sc->sc_ep_flags[ep_no].fifo_bank) { 1037 td = xfer->td_transfer_first; 1038 td->fifo_bank = 1; 1039 } 1040} 1041 1042static void 1043at91dci_timeout(void *arg) 1044{ 1045 struct usb2_xfer *xfer = arg; 1046 struct at91dci_softc *sc = xfer->usb2_sc; 1047 1048 DPRINTF("xfer=%p\n", xfer); 1049 1050 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1051 1052 /* transfer is transferred */ 1053 at91dci_device_done(xfer, USB_ERR_TIMEOUT); 1054 1055 USB_BUS_UNLOCK(&sc->sc_bus); 1056} 1057 1058static void 1059at91dci_start_standard_chain(struct usb2_xfer *xfer) 1060{ 1061 DPRINTFN(9, "\n"); 1062 1063 /* poll one time */ 1064 if (at91dci_xfer_do_fifo(xfer)) { 1065 1066 struct at91dci_softc *sc = xfer->usb2_sc; 1067 uint8_t ep_no = xfer->endpoint & UE_ADDR; 1068 1069 /* 1070 * Only enable the endpoint interrupt when we are actually 1071 * waiting for data, hence we are dealing with level 1072 * triggered interrupts ! 1073 */ 1074 AT91_UDP_WRITE_4(sc, AT91_UDP_IER, AT91_UDP_INT_EP(ep_no)); 1075 1076 DPRINTFN(15, "enable interrupts on endpoint %d\n", ep_no); 1077 1078 /* put transfer on interrupt queue */ 1079 usb2_transfer_enqueue(&xfer->udev->bus->intr_q, xfer); 1080 1081 /* start timeout, if any */ 1082 if (xfer->timeout != 0) { 1083 usb2_transfer_timeout_ms(xfer, 1084 &at91dci_timeout, xfer->timeout); 1085 } 1086 } 1087} 1088 1089static void 1090at91dci_root_intr_done(struct usb2_xfer *xfer, 1091 struct usb2_sw_transfer *std) 1092{ 1093 struct at91dci_softc *sc = xfer->usb2_sc; 1094 1095 DPRINTFN(9, "\n"); 1096 1097 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1098 1099 if (std->state != USB_SW_TR_PRE_DATA) { 1100 if (std->state == USB_SW_TR_PRE_CALLBACK) { 1101 /* transfer transferred */ 1102 at91dci_device_done(xfer, std->err); 1103 } 1104 goto done; 1105 } 1106 /* setup buffer */ 1107 std->ptr = sc->sc_hub_idata; 1108 std->len = sizeof(sc->sc_hub_idata); 1109 1110 /* set port bit */ 1111 sc->sc_hub_idata[0] = 0x02; /* we only have one port */ 1112 1113done: 1114 return; 1115} 1116 1117static usb2_error_t 1118at91dci_standard_done_sub(struct usb2_xfer *xfer) 1119{ 1120 struct at91dci_td *td; 1121 uint32_t len; 1122 uint8_t error; 1123 1124 DPRINTFN(9, "\n"); 1125 1126 td = xfer->td_transfer_cache; 1127 1128 do { 1129 len = td->remainder; 1130 1131 if (xfer->aframes != xfer->nframes) { 1132 /* 1133 * Verify the length and subtract 1134 * the remainder from "frlengths[]": 1135 */ 1136 if (len > xfer->frlengths[xfer->aframes]) { 1137 td->error = 1; 1138 } else { 1139 xfer->frlengths[xfer->aframes] -= len; 1140 } 1141 } 1142 /* Check for transfer error */ 1143 if (td->error) { 1144 /* the transfer is finished */ 1145 error = 1; 1146 td = NULL; 1147 break; 1148 } 1149 /* Check for short transfer */ 1150 if (len > 0) { 1151 if (xfer->flags_int.short_frames_ok) { 1152 /* follow alt next */ 1153 if (td->alt_next) { 1154 td = td->obj_next; 1155 } else { 1156 td = NULL; 1157 } 1158 } else { 1159 /* the transfer is finished */ 1160 td = NULL; 1161 } 1162 error = 0; 1163 break; 1164 } 1165 td = td->obj_next; 1166 1167 /* this USB frame is complete */ 1168 error = 0; 1169 break; 1170 1171 } while (0); 1172 1173 /* update transfer cache */ 1174 1175 xfer->td_transfer_cache = td; 1176 1177 return (error ? 1178 USB_ERR_STALLED : USB_ERR_NORMAL_COMPLETION); 1179} 1180 1181static void 1182at91dci_standard_done(struct usb2_xfer *xfer) 1183{ 1184 usb2_error_t err = 0; 1185 1186 DPRINTFN(13, "xfer=%p pipe=%p transfer done\n", 1187 xfer, xfer->pipe); 1188 1189 /* reset scanner */ 1190 1191 xfer->td_transfer_cache = xfer->td_transfer_first; 1192 1193 if (xfer->flags_int.control_xfr) { 1194 1195 if (xfer->flags_int.control_hdr) { 1196 1197 err = at91dci_standard_done_sub(xfer); 1198 } 1199 xfer->aframes = 1; 1200 1201 if (xfer->td_transfer_cache == NULL) { 1202 goto done; 1203 } 1204 } 1205 while (xfer->aframes != xfer->nframes) { 1206 1207 err = at91dci_standard_done_sub(xfer); 1208 xfer->aframes++; 1209 1210 if (xfer->td_transfer_cache == NULL) { 1211 goto done; 1212 } 1213 } 1214 1215 if (xfer->flags_int.control_xfr && 1216 !xfer->flags_int.control_act) { 1217 1218 err = at91dci_standard_done_sub(xfer); 1219 } 1220done: 1221 at91dci_device_done(xfer, err); 1222} 1223 1224/*------------------------------------------------------------------------* 1225 * at91dci_device_done 1226 * 1227 * NOTE: this function can be called more than one time on the 1228 * same USB transfer! 1229 *------------------------------------------------------------------------*/ 1230static void 1231at91dci_device_done(struct usb2_xfer *xfer, usb2_error_t error) 1232{ 1233 struct at91dci_softc *sc = xfer->usb2_sc; 1234 uint8_t ep_no; 1235 1236 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1237 1238 DPRINTFN(2, "xfer=%p, pipe=%p, error=%d\n", 1239 xfer, xfer->pipe, error); 1240 1241 if (xfer->flags_int.usb2_mode == USB_MODE_DEVICE) { 1242 ep_no = (xfer->endpoint & UE_ADDR); 1243 1244 /* disable endpoint interrupt */ 1245 AT91_UDP_WRITE_4(sc, AT91_UDP_IDR, AT91_UDP_INT_EP(ep_no)); 1246 1247 DPRINTFN(15, "disable interrupts on endpoint %d\n", ep_no); 1248 } 1249 /* dequeue transfer and start next transfer */ 1250 usb2_transfer_done(xfer, error); 1251} 1252 1253static void 1254at91dci_set_stall(struct usb2_device *udev, struct usb2_xfer *xfer, 1255 struct usb2_pipe *pipe) 1256{ 1257 struct at91dci_softc *sc; 1258 uint32_t csr_val; 1259 uint8_t csr_reg; 1260 1261 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 1262 1263 DPRINTFN(5, "pipe=%p\n", pipe); 1264 1265 if (xfer) { 1266 /* cancel any ongoing transfers */ 1267 at91dci_device_done(xfer, USB_ERR_STALLED); 1268 } 1269 /* set FORCESTALL */ 1270 sc = AT9100_DCI_BUS2SC(udev->bus); 1271 csr_reg = (pipe->edesc->bEndpointAddress & UE_ADDR); 1272 csr_reg = AT91_UDP_CSR(csr_reg); 1273 csr_val = AT91_UDP_READ_4(sc, csr_reg); 1274 AT91_CSR_ACK(csr_val, AT91_UDP_CSR_FORCESTALL); 1275 AT91_UDP_WRITE_4(sc, csr_reg, csr_val); 1276} 1277 1278static void 1279at91dci_clear_stall_sub(struct at91dci_softc *sc, uint8_t ep_no, 1280 uint8_t ep_type, uint8_t ep_dir) 1281{ 1282 const struct usb2_hw_ep_profile *pf; 1283 uint32_t csr_val; 1284 uint32_t temp; 1285 uint8_t csr_reg; 1286 uint8_t to; 1287 1288 if (ep_type == UE_CONTROL) { 1289 /* clearing stall is not needed */ 1290 return; 1291 } 1292 /* compute CSR register offset */ 1293 csr_reg = AT91_UDP_CSR(ep_no); 1294 1295 /* compute default CSR value */ 1296 csr_val = 0; 1297 AT91_CSR_ACK(csr_val, 0); 1298 1299 /* disable endpoint */ 1300 AT91_UDP_WRITE_4(sc, csr_reg, csr_val); 1301 1302 /* get endpoint profile */ 1303 at91dci_get_hw_ep_profile(NULL, &pf, ep_no); 1304 1305 /* reset FIFO */ 1306 AT91_UDP_WRITE_4(sc, AT91_UDP_RST, AT91_UDP_RST_EP(ep_no)); 1307 AT91_UDP_WRITE_4(sc, AT91_UDP_RST, 0); 1308 1309 /* 1310 * NOTE: One would assume that a FIFO reset would release the 1311 * FIFO banks aswell, but it doesn't! We have to do this 1312 * manually! 1313 */ 1314 1315 /* release FIFO banks, if any */ 1316 for (to = 0; to != 2; to++) { 1317 1318 /* get csr value */ 1319 csr_val = AT91_UDP_READ_4(sc, csr_reg); 1320 1321 if (csr_val & (AT91_UDP_CSR_RX_DATA_BK0 | 1322 AT91_UDP_CSR_RX_DATA_BK1)) { 1323 /* clear status bits */ 1324 if (pf->support_multi_buffer) { 1325 if (sc->sc_ep_flags[ep_no].fifo_bank) { 1326 sc->sc_ep_flags[ep_no].fifo_bank = 0; 1327 temp = AT91_UDP_CSR_RX_DATA_BK1; 1328 } else { 1329 sc->sc_ep_flags[ep_no].fifo_bank = 1; 1330 temp = AT91_UDP_CSR_RX_DATA_BK0; 1331 } 1332 } else { 1333 temp = (AT91_UDP_CSR_RX_DATA_BK0 | 1334 AT91_UDP_CSR_RX_DATA_BK1); 1335 } 1336 } else { 1337 temp = 0; 1338 } 1339 1340 /* clear FORCESTALL */ 1341 temp |= AT91_UDP_CSR_STALLSENT; 1342 1343 AT91_CSR_ACK(csr_val, temp); 1344 AT91_UDP_WRITE_4(sc, csr_reg, csr_val); 1345 } 1346 1347 /* compute default CSR value */ 1348 csr_val = 0; 1349 AT91_CSR_ACK(csr_val, 0); 1350 1351 /* enable endpoint */ 1352 csr_val &= ~AT91_UDP_CSR_ET_MASK; 1353 csr_val |= AT91_UDP_CSR_EPEDS; 1354 1355 if (ep_type == UE_CONTROL) { 1356 csr_val |= AT91_UDP_CSR_ET_CTRL; 1357 } else { 1358 if (ep_type == UE_BULK) { 1359 csr_val |= AT91_UDP_CSR_ET_BULK; 1360 } else if (ep_type == UE_INTERRUPT) { 1361 csr_val |= AT91_UDP_CSR_ET_INT; 1362 } else { 1363 csr_val |= AT91_UDP_CSR_ET_ISO; 1364 } 1365 if (ep_dir & UE_DIR_IN) { 1366 csr_val |= AT91_UDP_CSR_ET_DIR_IN; 1367 } 1368 } 1369 1370 /* enable endpoint */ 1371 AT91_UDP_WRITE_4(sc, AT91_UDP_CSR(ep_no), csr_val); 1372} 1373 1374static void 1375at91dci_clear_stall(struct usb2_device *udev, struct usb2_pipe *pipe) 1376{ 1377 struct at91dci_softc *sc; 1378 struct usb2_endpoint_descriptor *ed; 1379 1380 DPRINTFN(5, "pipe=%p\n", pipe); 1381 1382 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 1383 1384 /* check mode */ 1385 if (udev->flags.usb2_mode != USB_MODE_DEVICE) { 1386 /* not supported */ 1387 return; 1388 } 1389 /* get softc */ 1390 sc = AT9100_DCI_BUS2SC(udev->bus); 1391 1392 /* get endpoint descriptor */ 1393 ed = pipe->edesc; 1394 1395 /* reset endpoint */ 1396 at91dci_clear_stall_sub(sc, 1397 (ed->bEndpointAddress & UE_ADDR), 1398 (ed->bmAttributes & UE_XFERTYPE), 1399 (ed->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT))); 1400} 1401 1402usb2_error_t 1403at91dci_init(struct at91dci_softc *sc) 1404{ 1405 uint32_t csr_val; 1406 uint8_t n; 1407 1408 DPRINTF("start\n"); 1409 1410 /* set up the bus structure */ 1411 sc->sc_bus.usbrev = USB_REV_1_1; 1412 sc->sc_bus.methods = &at91dci_bus_methods; 1413 1414 USB_BUS_LOCK(&sc->sc_bus); 1415 1416 /* turn on clocks */ 1417 1418 if (sc->sc_clocks_on) { 1419 (sc->sc_clocks_on) (sc->sc_clocks_arg); 1420 } 1421 /* wait a little for things to stabilise */ 1422 usb2_pause_mtx(&sc->sc_bus.bus_mtx, 1); 1423 1424 /* disable and clear all interrupts */ 1425 1426 AT91_UDP_WRITE_4(sc, AT91_UDP_IDR, 0xFFFFFFFF); 1427 AT91_UDP_WRITE_4(sc, AT91_UDP_ICR, 0xFFFFFFFF); 1428 1429 /* compute default CSR value */ 1430 1431 csr_val = 0; 1432 AT91_CSR_ACK(csr_val, 0); 1433 1434 /* disable all endpoints */ 1435 1436 for (n = 0; n != AT91_UDP_EP_MAX; n++) { 1437 1438 /* disable endpoint */ 1439 AT91_UDP_WRITE_4(sc, AT91_UDP_CSR(n), csr_val); 1440 } 1441 1442 /* enable the control endpoint */ 1443 1444 AT91_CSR_ACK(csr_val, AT91_UDP_CSR_ET_CTRL | 1445 AT91_UDP_CSR_EPEDS); 1446 1447 /* write to FIFO control register */ 1448 1449 AT91_UDP_WRITE_4(sc, AT91_UDP_CSR(0), csr_val); 1450 1451 /* enable the interrupts we want */ 1452 1453 AT91_UDP_WRITE_4(sc, AT91_UDP_IER, AT91_UDP_INT_BUS); 1454 1455 /* turn off clocks */ 1456 1457 at91dci_clocks_off(sc); 1458 1459 USB_BUS_UNLOCK(&sc->sc_bus); 1460 1461 /* catch any lost interrupts */ 1462 1463 at91dci_do_poll(&sc->sc_bus); 1464 1465 return (0); /* success */ 1466} 1467 1468void 1469at91dci_uninit(struct at91dci_softc *sc) 1470{ 1471 USB_BUS_LOCK(&sc->sc_bus); 1472 1473 /* disable and clear all interrupts */ 1474 AT91_UDP_WRITE_4(sc, AT91_UDP_IDR, 0xFFFFFFFF); 1475 AT91_UDP_WRITE_4(sc, AT91_UDP_ICR, 0xFFFFFFFF); 1476 1477 sc->sc_flags.port_powered = 0; 1478 sc->sc_flags.status_vbus = 0; 1479 sc->sc_flags.status_bus_reset = 0; 1480 sc->sc_flags.status_suspend = 0; 1481 sc->sc_flags.change_suspend = 0; 1482 sc->sc_flags.change_connect = 1; 1483 1484 at91dci_pull_down(sc); 1485 at91dci_clocks_off(sc); 1486 USB_BUS_UNLOCK(&sc->sc_bus); 1487} 1488 1489void 1490at91dci_suspend(struct at91dci_softc *sc) 1491{ 1492 return; 1493} 1494 1495void 1496at91dci_resume(struct at91dci_softc *sc) 1497{ 1498 return; 1499} 1500 1501static void 1502at91dci_do_poll(struct usb2_bus *bus) 1503{ 1504 struct at91dci_softc *sc = AT9100_DCI_BUS2SC(bus); 1505 1506 USB_BUS_LOCK(&sc->sc_bus); 1507 at91dci_interrupt_poll(sc); 1508 at91dci_root_ctrl_poll(sc); 1509 USB_BUS_UNLOCK(&sc->sc_bus); 1510} 1511 1512/*------------------------------------------------------------------------* 1513 * at91dci bulk support 1514 *------------------------------------------------------------------------*/ 1515static void 1516at91dci_device_bulk_open(struct usb2_xfer *xfer) 1517{ 1518 return; 1519} 1520 1521static void 1522at91dci_device_bulk_close(struct usb2_xfer *xfer) 1523{ 1524 at91dci_device_done(xfer, USB_ERR_CANCELLED); 1525} 1526 1527static void 1528at91dci_device_bulk_enter(struct usb2_xfer *xfer) 1529{ 1530 return; 1531} 1532 1533static void 1534at91dci_device_bulk_start(struct usb2_xfer *xfer) 1535{ 1536 /* setup TDs */ 1537 at91dci_setup_standard_chain(xfer); 1538 at91dci_start_standard_chain(xfer); 1539} 1540 1541struct usb2_pipe_methods at91dci_device_bulk_methods = 1542{ 1543 .open = at91dci_device_bulk_open, 1544 .close = at91dci_device_bulk_close, 1545 .enter = at91dci_device_bulk_enter, 1546 .start = at91dci_device_bulk_start, 1547 .enter_is_cancelable = 1, 1548 .start_is_cancelable = 1, 1549}; 1550 1551/*------------------------------------------------------------------------* 1552 * at91dci control support 1553 *------------------------------------------------------------------------*/ 1554static void 1555at91dci_device_ctrl_open(struct usb2_xfer *xfer) 1556{ 1557 return; 1558} 1559 1560static void 1561at91dci_device_ctrl_close(struct usb2_xfer *xfer) 1562{ 1563 at91dci_device_done(xfer, USB_ERR_CANCELLED); 1564} 1565 1566static void 1567at91dci_device_ctrl_enter(struct usb2_xfer *xfer) 1568{ 1569 return; 1570} 1571 1572static void 1573at91dci_device_ctrl_start(struct usb2_xfer *xfer) 1574{ 1575 /* setup TDs */ 1576 at91dci_setup_standard_chain(xfer); 1577 at91dci_start_standard_chain(xfer); 1578} 1579 1580struct usb2_pipe_methods at91dci_device_ctrl_methods = 1581{ 1582 .open = at91dci_device_ctrl_open, 1583 .close = at91dci_device_ctrl_close, 1584 .enter = at91dci_device_ctrl_enter, 1585 .start = at91dci_device_ctrl_start, 1586 .enter_is_cancelable = 1, 1587 .start_is_cancelable = 1, 1588}; 1589 1590/*------------------------------------------------------------------------* 1591 * at91dci interrupt support 1592 *------------------------------------------------------------------------*/ 1593static void 1594at91dci_device_intr_open(struct usb2_xfer *xfer) 1595{ 1596 return; 1597} 1598 1599static void 1600at91dci_device_intr_close(struct usb2_xfer *xfer) 1601{ 1602 at91dci_device_done(xfer, USB_ERR_CANCELLED); 1603} 1604 1605static void 1606at91dci_device_intr_enter(struct usb2_xfer *xfer) 1607{ 1608 return; 1609} 1610 1611static void 1612at91dci_device_intr_start(struct usb2_xfer *xfer) 1613{ 1614 /* setup TDs */ 1615 at91dci_setup_standard_chain(xfer); 1616 at91dci_start_standard_chain(xfer); 1617} 1618 1619struct usb2_pipe_methods at91dci_device_intr_methods = 1620{ 1621 .open = at91dci_device_intr_open, 1622 .close = at91dci_device_intr_close, 1623 .enter = at91dci_device_intr_enter, 1624 .start = at91dci_device_intr_start, 1625 .enter_is_cancelable = 1, 1626 .start_is_cancelable = 1, 1627}; 1628 1629/*------------------------------------------------------------------------* 1630 * at91dci full speed isochronous support 1631 *------------------------------------------------------------------------*/ 1632static void 1633at91dci_device_isoc_fs_open(struct usb2_xfer *xfer) 1634{ 1635 return; 1636} 1637 1638static void 1639at91dci_device_isoc_fs_close(struct usb2_xfer *xfer) 1640{ 1641 at91dci_device_done(xfer, USB_ERR_CANCELLED); 1642} 1643 1644static void 1645at91dci_device_isoc_fs_enter(struct usb2_xfer *xfer) 1646{ 1647 struct at91dci_softc *sc = xfer->usb2_sc; 1648 uint32_t temp; 1649 uint32_t nframes; 1650 1651 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n", 1652 xfer, xfer->pipe->isoc_next, xfer->nframes); 1653 1654 /* get the current frame index */ 1655 1656 nframes = AT91_UDP_READ_4(sc, AT91_UDP_FRM); 1657 1658 /* 1659 * check if the frame index is within the window where the frames 1660 * will be inserted 1661 */ 1662 temp = (nframes - xfer->pipe->isoc_next) & AT91_UDP_FRM_MASK; 1663 1664 if ((xfer->pipe->is_synced == 0) || 1665 (temp < xfer->nframes)) { 1666 /* 1667 * If there is data underflow or the pipe queue is 1668 * empty we schedule the transfer a few frames ahead 1669 * of the current frame position. Else two isochronous 1670 * transfers might overlap. 1671 */ 1672 xfer->pipe->isoc_next = (nframes + 3) & AT91_UDP_FRM_MASK; 1673 xfer->pipe->is_synced = 1; 1674 DPRINTFN(3, "start next=%d\n", xfer->pipe->isoc_next); 1675 } 1676 /* 1677 * compute how many milliseconds the insertion is ahead of the 1678 * current frame position: 1679 */ 1680 temp = (xfer->pipe->isoc_next - nframes) & AT91_UDP_FRM_MASK; 1681 1682 /* 1683 * pre-compute when the isochronous transfer will be finished: 1684 */ 1685 xfer->isoc_time_complete = 1686 usb2_isoc_time_expand(&sc->sc_bus, nframes) + temp + 1687 xfer->nframes; 1688 1689 /* compute frame number for next insertion */ 1690 xfer->pipe->isoc_next += xfer->nframes; 1691 1692 /* setup TDs */ 1693 at91dci_setup_standard_chain(xfer); 1694} 1695 1696static void 1697at91dci_device_isoc_fs_start(struct usb2_xfer *xfer) 1698{ 1699 /* start TD chain */ 1700 at91dci_start_standard_chain(xfer); 1701} 1702 1703struct usb2_pipe_methods at91dci_device_isoc_fs_methods = 1704{ 1705 .open = at91dci_device_isoc_fs_open, 1706 .close = at91dci_device_isoc_fs_close, 1707 .enter = at91dci_device_isoc_fs_enter, 1708 .start = at91dci_device_isoc_fs_start, 1709 .enter_is_cancelable = 1, 1710 .start_is_cancelable = 1, 1711}; 1712 1713/*------------------------------------------------------------------------* 1714 * at91dci root control support 1715 *------------------------------------------------------------------------* 1716 * simulate a hardware HUB by handling 1717 * all the necessary requests 1718 *------------------------------------------------------------------------*/ 1719 1720static void 1721at91dci_root_ctrl_open(struct usb2_xfer *xfer) 1722{ 1723 return; 1724} 1725 1726static void 1727at91dci_root_ctrl_close(struct usb2_xfer *xfer) 1728{ 1729 struct at91dci_softc *sc = xfer->usb2_sc; 1730 1731 if (sc->sc_root_ctrl.xfer == xfer) { 1732 sc->sc_root_ctrl.xfer = NULL; 1733 } 1734 at91dci_device_done(xfer, USB_ERR_CANCELLED); 1735} 1736 1737/* 1738 * USB descriptors for the virtual Root HUB: 1739 */ 1740 1741static const struct usb2_device_descriptor at91dci_devd = { 1742 .bLength = sizeof(struct usb2_device_descriptor), 1743 .bDescriptorType = UDESC_DEVICE, 1744 .bcdUSB = {0x00, 0x02}, 1745 .bDeviceClass = UDCLASS_HUB, 1746 .bDeviceSubClass = UDSUBCLASS_HUB, 1747 .bDeviceProtocol = UDPROTO_HSHUBSTT, 1748 .bMaxPacketSize = 64, 1749 .bcdDevice = {0x00, 0x01}, 1750 .iManufacturer = 1, 1751 .iProduct = 2, 1752 .bNumConfigurations = 1, 1753}; 1754 1755static const struct usb2_device_qualifier at91dci_odevd = { 1756 .bLength = sizeof(struct usb2_device_qualifier), 1757 .bDescriptorType = UDESC_DEVICE_QUALIFIER, 1758 .bcdUSB = {0x00, 0x02}, 1759 .bDeviceClass = UDCLASS_HUB, 1760 .bDeviceSubClass = UDSUBCLASS_HUB, 1761 .bDeviceProtocol = UDPROTO_FSHUB, 1762 .bMaxPacketSize0 = 0, 1763 .bNumConfigurations = 0, 1764}; 1765 1766static const struct at91dci_config_desc at91dci_confd = { 1767 .confd = { 1768 .bLength = sizeof(struct usb2_config_descriptor), 1769 .bDescriptorType = UDESC_CONFIG, 1770 .wTotalLength[0] = sizeof(at91dci_confd), 1771 .bNumInterface = 1, 1772 .bConfigurationValue = 1, 1773 .iConfiguration = 0, 1774 .bmAttributes = UC_SELF_POWERED, 1775 .bMaxPower = 0, 1776 }, 1777 .ifcd = { 1778 .bLength = sizeof(struct usb2_interface_descriptor), 1779 .bDescriptorType = UDESC_INTERFACE, 1780 .bNumEndpoints = 1, 1781 .bInterfaceClass = UICLASS_HUB, 1782 .bInterfaceSubClass = UISUBCLASS_HUB, 1783 .bInterfaceProtocol = UIPROTO_HSHUBSTT, 1784 }, 1785 1786 .endpd = { 1787 .bLength = sizeof(struct usb2_endpoint_descriptor), 1788 .bDescriptorType = UDESC_ENDPOINT, 1789 .bEndpointAddress = (UE_DIR_IN | AT9100_DCI_INTR_ENDPT), 1790 .bmAttributes = UE_INTERRUPT, 1791 .wMaxPacketSize[0] = 8, 1792 .bInterval = 255, 1793 }, 1794}; 1795 1796static const struct usb2_hub_descriptor_min at91dci_hubd = { 1797 .bDescLength = sizeof(at91dci_hubd), 1798 .bDescriptorType = UDESC_HUB, 1799 .bNbrPorts = 1, 1800 .wHubCharacteristics[0] = 1801 (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL) & 0xFF, 1802 .wHubCharacteristics[1] = 1803 (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL) >> 16, 1804 .bPwrOn2PwrGood = 50, 1805 .bHubContrCurrent = 0, 1806 .DeviceRemovable = {0}, /* port is removable */ 1807}; 1808 1809#define STRING_LANG \ 1810 0x09, 0x04, /* American English */ 1811 1812#define STRING_VENDOR \ 1813 'A', 0, 'T', 0, 'M', 0, 'E', 0, 'L', 0 1814 1815#define STRING_PRODUCT \ 1816 'D', 0, 'C', 0, 'I', 0, ' ', 0, 'R', 0, \ 1817 'o', 0, 'o', 0, 't', 0, ' ', 0, 'H', 0, \ 1818 'U', 0, 'B', 0, 1819 1820USB_MAKE_STRING_DESC(STRING_LANG, at91dci_langtab); 1821USB_MAKE_STRING_DESC(STRING_VENDOR, at91dci_vendor); 1822USB_MAKE_STRING_DESC(STRING_PRODUCT, at91dci_product); 1823 1824static void 1825at91dci_root_ctrl_enter(struct usb2_xfer *xfer) 1826{ 1827 return; 1828} 1829 1830static void 1831at91dci_root_ctrl_start(struct usb2_xfer *xfer) 1832{ 1833 struct at91dci_softc *sc = xfer->usb2_sc; 1834 1835 sc->sc_root_ctrl.xfer = xfer; 1836 1837 usb2_config_td_queue_command( 1838 &sc->sc_config_td, NULL, &at91dci_root_ctrl_task, 0, 0); 1839} 1840 1841static void 1842at91dci_root_ctrl_task(struct at91dci_softc *sc, 1843 struct at91dci_config_copy *cc, uint16_t refcount) 1844{ 1845 at91dci_root_ctrl_poll(sc); 1846} 1847 1848static void 1849at91dci_root_ctrl_done(struct usb2_xfer *xfer, 1850 struct usb2_sw_transfer *std) 1851{ 1852 struct at91dci_softc *sc = xfer->usb2_sc; 1853 uint16_t value; 1854 uint16_t index; 1855 uint8_t use_polling; 1856 1857 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1858 1859 if (std->state != USB_SW_TR_SETUP) { 1860 if (std->state == USB_SW_TR_PRE_CALLBACK) { 1861 /* transfer transferred */ 1862 at91dci_device_done(xfer, std->err); 1863 } 1864 goto done; 1865 } 1866 /* buffer reset */ 1867 std->ptr = USB_ADD_BYTES(&sc->sc_hub_temp, 0); 1868 std->len = 0; 1869 1870 value = UGETW(std->req.wValue); 1871 index = UGETW(std->req.wIndex); 1872 1873 use_polling = mtx_owned(xfer->xfer_mtx) ? 1 : 0; 1874 1875 /* demultiplex the control request */ 1876 1877 switch (std->req.bmRequestType) { 1878 case UT_READ_DEVICE: 1879 switch (std->req.bRequest) { 1880 case UR_GET_DESCRIPTOR: 1881 goto tr_handle_get_descriptor; 1882 case UR_GET_CONFIG: 1883 goto tr_handle_get_config; 1884 case UR_GET_STATUS: 1885 goto tr_handle_get_status; 1886 default: 1887 goto tr_stalled; 1888 } 1889 break; 1890 1891 case UT_WRITE_DEVICE: 1892 switch (std->req.bRequest) { 1893 case UR_SET_ADDRESS: 1894 goto tr_handle_set_address; 1895 case UR_SET_CONFIG: 1896 goto tr_handle_set_config; 1897 case UR_CLEAR_FEATURE: 1898 goto tr_valid; /* nop */ 1899 case UR_SET_DESCRIPTOR: 1900 goto tr_valid; /* nop */ 1901 case UR_SET_FEATURE: 1902 default: 1903 goto tr_stalled; 1904 } 1905 break; 1906 1907 case UT_WRITE_ENDPOINT: 1908 switch (std->req.bRequest) { 1909 case UR_CLEAR_FEATURE: 1910 switch (UGETW(std->req.wValue)) { 1911 case UF_ENDPOINT_HALT: 1912 goto tr_handle_clear_halt; 1913 case UF_DEVICE_REMOTE_WAKEUP: 1914 goto tr_handle_clear_wakeup; 1915 default: 1916 goto tr_stalled; 1917 } 1918 break; 1919 case UR_SET_FEATURE: 1920 switch (UGETW(std->req.wValue)) { 1921 case UF_ENDPOINT_HALT: 1922 goto tr_handle_set_halt; 1923 case UF_DEVICE_REMOTE_WAKEUP: 1924 goto tr_handle_set_wakeup; 1925 default: 1926 goto tr_stalled; 1927 } 1928 break; 1929 case UR_SYNCH_FRAME: 1930 goto tr_valid; /* nop */ 1931 default: 1932 goto tr_stalled; 1933 } 1934 break; 1935 1936 case UT_READ_ENDPOINT: 1937 switch (std->req.bRequest) { 1938 case UR_GET_STATUS: 1939 goto tr_handle_get_ep_status; 1940 default: 1941 goto tr_stalled; 1942 } 1943 break; 1944 1945 case UT_WRITE_INTERFACE: 1946 switch (std->req.bRequest) { 1947 case UR_SET_INTERFACE: 1948 goto tr_handle_set_interface; 1949 case UR_CLEAR_FEATURE: 1950 goto tr_valid; /* nop */ 1951 case UR_SET_FEATURE: 1952 default: 1953 goto tr_stalled; 1954 } 1955 break; 1956 1957 case UT_READ_INTERFACE: 1958 switch (std->req.bRequest) { 1959 case UR_GET_INTERFACE: 1960 goto tr_handle_get_interface; 1961 case UR_GET_STATUS: 1962 goto tr_handle_get_iface_status; 1963 default: 1964 goto tr_stalled; 1965 } 1966 break; 1967 1968 case UT_WRITE_CLASS_INTERFACE: 1969 case UT_WRITE_VENDOR_INTERFACE: 1970 /* XXX forward */ 1971 break; 1972 1973 case UT_READ_CLASS_INTERFACE: 1974 case UT_READ_VENDOR_INTERFACE: 1975 /* XXX forward */ 1976 break; 1977 1978 case UT_WRITE_CLASS_DEVICE: 1979 switch (std->req.bRequest) { 1980 case UR_CLEAR_FEATURE: 1981 goto tr_valid; 1982 case UR_SET_DESCRIPTOR: 1983 case UR_SET_FEATURE: 1984 break; 1985 default: 1986 goto tr_stalled; 1987 } 1988 break; 1989 1990 case UT_WRITE_CLASS_OTHER: 1991 switch (std->req.bRequest) { 1992 case UR_CLEAR_FEATURE: 1993 goto tr_handle_clear_port_feature; 1994 case UR_SET_FEATURE: 1995 goto tr_handle_set_port_feature; 1996 case UR_CLEAR_TT_BUFFER: 1997 case UR_RESET_TT: 1998 case UR_STOP_TT: 1999 goto tr_valid; 2000 2001 default: 2002 goto tr_stalled; 2003 } 2004 break; 2005 2006 case UT_READ_CLASS_OTHER: 2007 switch (std->req.bRequest) { 2008 case UR_GET_TT_STATE: 2009 goto tr_handle_get_tt_state; 2010 case UR_GET_STATUS: 2011 goto tr_handle_get_port_status; 2012 default: 2013 goto tr_stalled; 2014 } 2015 break; 2016 2017 case UT_READ_CLASS_DEVICE: 2018 switch (std->req.bRequest) { 2019 case UR_GET_DESCRIPTOR: 2020 goto tr_handle_get_class_descriptor; 2021 case UR_GET_STATUS: 2022 goto tr_handle_get_class_status; 2023 2024 default: 2025 goto tr_stalled; 2026 } 2027 break; 2028 default: 2029 goto tr_stalled; 2030 } 2031 goto tr_valid; 2032 2033tr_handle_get_descriptor: 2034 switch (value >> 8) { 2035 case UDESC_DEVICE: 2036 if (value & 0xff) { 2037 goto tr_stalled; 2038 } 2039 std->len = sizeof(at91dci_devd); 2040 std->ptr = USB_ADD_BYTES(&at91dci_devd, 0); 2041 goto tr_valid; 2042 case UDESC_CONFIG: 2043 if (value & 0xff) { 2044 goto tr_stalled; 2045 } 2046 std->len = sizeof(at91dci_confd); 2047 std->ptr = USB_ADD_BYTES(&at91dci_confd, 0); 2048 goto tr_valid; 2049 case UDESC_STRING: 2050 switch (value & 0xff) { 2051 case 0: /* Language table */ 2052 std->len = sizeof(at91dci_langtab); 2053 std->ptr = USB_ADD_BYTES(&at91dci_langtab, 0); 2054 goto tr_valid; 2055 2056 case 1: /* Vendor */ 2057 std->len = sizeof(at91dci_vendor); 2058 std->ptr = USB_ADD_BYTES(&at91dci_vendor, 0); 2059 goto tr_valid; 2060 2061 case 2: /* Product */ 2062 std->len = sizeof(at91dci_product); 2063 std->ptr = USB_ADD_BYTES(&at91dci_product, 0); 2064 goto tr_valid; 2065 default: 2066 break; 2067 } 2068 break; 2069 default: 2070 goto tr_stalled; 2071 } 2072 goto tr_stalled; 2073 2074tr_handle_get_config: 2075 std->len = 1; 2076 sc->sc_hub_temp.wValue[0] = sc->sc_conf; 2077 goto tr_valid; 2078 2079tr_handle_get_status: 2080 std->len = 2; 2081 USETW(sc->sc_hub_temp.wValue, UDS_SELF_POWERED); 2082 goto tr_valid; 2083 2084tr_handle_set_address: 2085 if (value & 0xFF00) { 2086 goto tr_stalled; 2087 } 2088 sc->sc_rt_addr = value; 2089 goto tr_valid; 2090 2091tr_handle_set_config: 2092 if (value >= 2) { 2093 goto tr_stalled; 2094 } 2095 sc->sc_conf = value; 2096 goto tr_valid; 2097 2098tr_handle_get_interface: 2099 std->len = 1; 2100 sc->sc_hub_temp.wValue[0] = 0; 2101 goto tr_valid; 2102 2103tr_handle_get_tt_state: 2104tr_handle_get_class_status: 2105tr_handle_get_iface_status: 2106tr_handle_get_ep_status: 2107 std->len = 2; 2108 USETW(sc->sc_hub_temp.wValue, 0); 2109 goto tr_valid; 2110 2111tr_handle_set_halt: 2112tr_handle_set_interface: 2113tr_handle_set_wakeup: 2114tr_handle_clear_wakeup: 2115tr_handle_clear_halt: 2116 goto tr_valid; 2117 2118tr_handle_clear_port_feature: 2119 if (index != 1) { 2120 goto tr_stalled; 2121 } 2122 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE on port %d\n", index); 2123 2124 switch (value) { 2125 case UHF_PORT_SUSPEND: 2126 at91dci_wakeup_peer(sc); 2127 break; 2128 2129 case UHF_PORT_ENABLE: 2130 sc->sc_flags.port_enabled = 0; 2131 break; 2132 2133 case UHF_PORT_TEST: 2134 case UHF_PORT_INDICATOR: 2135 case UHF_C_PORT_ENABLE: 2136 case UHF_C_PORT_OVER_CURRENT: 2137 case UHF_C_PORT_RESET: 2138 /* nops */ 2139 break; 2140 case UHF_PORT_POWER: 2141 sc->sc_flags.port_powered = 0; 2142 at91dci_pull_down(sc); 2143 at91dci_clocks_off(sc); 2144 break; 2145 case UHF_C_PORT_CONNECTION: 2146 sc->sc_flags.change_connect = 0; 2147 break; 2148 case UHF_C_PORT_SUSPEND: 2149 sc->sc_flags.change_suspend = 0; 2150 break; 2151 default: 2152 std->err = USB_ERR_IOERROR; 2153 goto done; 2154 } 2155 goto tr_valid; 2156 2157tr_handle_set_port_feature: 2158 if (index != 1) { 2159 goto tr_stalled; 2160 } 2161 DPRINTFN(9, "UR_SET_PORT_FEATURE\n"); 2162 2163 switch (value) { 2164 case UHF_PORT_ENABLE: 2165 sc->sc_flags.port_enabled = 1; 2166 break; 2167 case UHF_PORT_SUSPEND: 2168 case UHF_PORT_RESET: 2169 case UHF_PORT_TEST: 2170 case UHF_PORT_INDICATOR: 2171 /* nops */ 2172 break; 2173 case UHF_PORT_POWER: 2174 sc->sc_flags.port_powered = 1; 2175 break; 2176 default: 2177 std->err = USB_ERR_IOERROR; 2178 goto done; 2179 } 2180 goto tr_valid; 2181 2182tr_handle_get_port_status: 2183 2184 DPRINTFN(9, "UR_GET_PORT_STATUS\n"); 2185 2186 if (index != 1) { 2187 goto tr_stalled; 2188 } 2189 if (sc->sc_flags.status_vbus) { 2190 at91dci_clocks_on(sc); 2191 at91dci_pull_up(sc); 2192 } else { 2193 at91dci_pull_down(sc); 2194 at91dci_clocks_off(sc); 2195 } 2196 2197 /* Select FULL-speed and Device Side Mode */ 2198 2199 value = UPS_PORT_MODE_DEVICE; 2200 2201 if (sc->sc_flags.port_powered) { 2202 value |= UPS_PORT_POWER; 2203 } 2204 if (sc->sc_flags.port_enabled) { 2205 value |= UPS_PORT_ENABLED; 2206 } 2207 if (sc->sc_flags.status_vbus && 2208 sc->sc_flags.status_bus_reset) { 2209 value |= UPS_CURRENT_CONNECT_STATUS; 2210 } 2211 if (sc->sc_flags.status_suspend) { 2212 value |= UPS_SUSPEND; 2213 } 2214 USETW(sc->sc_hub_temp.ps.wPortStatus, value); 2215 2216 value = 0; 2217 2218 if (sc->sc_flags.change_connect) { 2219 value |= UPS_C_CONNECT_STATUS; 2220 2221 if (sc->sc_flags.status_vbus && 2222 sc->sc_flags.status_bus_reset) { 2223 /* reset endpoint flags */ 2224 bzero(sc->sc_ep_flags, sizeof(sc->sc_ep_flags)); 2225 } 2226 } 2227 if (sc->sc_flags.change_suspend) { 2228 value |= UPS_C_SUSPEND; 2229 } 2230 USETW(sc->sc_hub_temp.ps.wPortChange, value); 2231 std->len = sizeof(sc->sc_hub_temp.ps); 2232 goto tr_valid; 2233 2234tr_handle_get_class_descriptor: 2235 if (value & 0xFF) { 2236 goto tr_stalled; 2237 } 2238 std->ptr = USB_ADD_BYTES(&at91dci_hubd, 0); 2239 std->len = sizeof(at91dci_hubd); 2240 goto tr_valid; 2241 2242tr_stalled: 2243 std->err = USB_ERR_STALLED; 2244tr_valid: 2245done: 2246 return; 2247} 2248 2249static void 2250at91dci_root_ctrl_poll(struct at91dci_softc *sc) 2251{ 2252 usb2_sw_transfer(&sc->sc_root_ctrl, 2253 &at91dci_root_ctrl_done); 2254} 2255 2256struct usb2_pipe_methods at91dci_root_ctrl_methods = 2257{ 2258 .open = at91dci_root_ctrl_open, 2259 .close = at91dci_root_ctrl_close, 2260 .enter = at91dci_root_ctrl_enter, 2261 .start = at91dci_root_ctrl_start, 2262 .enter_is_cancelable = 1, 2263 .start_is_cancelable = 0, 2264}; 2265 2266/*------------------------------------------------------------------------* 2267 * at91dci root interrupt support 2268 *------------------------------------------------------------------------*/ 2269static void 2270at91dci_root_intr_open(struct usb2_xfer *xfer) 2271{ 2272 return; 2273} 2274 2275static void 2276at91dci_root_intr_close(struct usb2_xfer *xfer) 2277{ 2278 struct at91dci_softc *sc = xfer->usb2_sc; 2279 2280 if (sc->sc_root_intr.xfer == xfer) { 2281 sc->sc_root_intr.xfer = NULL; 2282 } 2283 at91dci_device_done(xfer, USB_ERR_CANCELLED); 2284} 2285 2286static void 2287at91dci_root_intr_enter(struct usb2_xfer *xfer) 2288{ 2289 return; 2290} 2291 2292static void 2293at91dci_root_intr_start(struct usb2_xfer *xfer) 2294{ 2295 struct at91dci_softc *sc = xfer->usb2_sc; 2296 2297 sc->sc_root_intr.xfer = xfer; 2298} 2299 2300struct usb2_pipe_methods at91dci_root_intr_methods = 2301{ 2302 .open = at91dci_root_intr_open, 2303 .close = at91dci_root_intr_close, 2304 .enter = at91dci_root_intr_enter, 2305 .start = at91dci_root_intr_start, 2306 .enter_is_cancelable = 1, 2307 .start_is_cancelable = 1, 2308}; 2309 2310static void 2311at91dci_xfer_setup(struct usb2_setup_params *parm) 2312{ 2313 const struct usb2_hw_ep_profile *pf; 2314 struct at91dci_softc *sc; 2315 struct usb2_xfer *xfer; 2316 void *last_obj; 2317 uint32_t ntd; 2318 uint32_t n; 2319 uint8_t ep_no; 2320 2321 sc = AT9100_DCI_BUS2SC(parm->udev->bus); 2322 xfer = parm->curr_xfer; 2323 2324 /* 2325 * setup xfer 2326 */ 2327 xfer->usb2_sc = sc; 2328 2329 /* 2330 * NOTE: This driver does not use any of the parameters that 2331 * are computed from the following values. Just set some 2332 * reasonable dummies: 2333 */ 2334 parm->hc_max_packet_size = 0x500; 2335 parm->hc_max_packet_count = 1; 2336 parm->hc_max_frame_size = 0x500; 2337 2338 usb2_transfer_setup_sub(parm); 2339 2340 /* 2341 * compute maximum number of TDs 2342 */ 2343 if (parm->methods == &at91dci_device_ctrl_methods) { 2344 2345 ntd = xfer->nframes + 1 /* STATUS */ + 1 /* SYNC 1 */ 2346 + 1 /* SYNC 2 */ ; 2347 2348 } else if (parm->methods == &at91dci_device_bulk_methods) { 2349 2350 ntd = xfer->nframes + 1 /* SYNC */ ; 2351 2352 } else if (parm->methods == &at91dci_device_intr_methods) { 2353 2354 ntd = xfer->nframes + 1 /* SYNC */ ; 2355 2356 } else if (parm->methods == &at91dci_device_isoc_fs_methods) { 2357 2358 ntd = xfer->nframes + 1 /* SYNC */ ; 2359 2360 } else { 2361 2362 ntd = 0; 2363 } 2364 2365 /* 2366 * check if "usb2_transfer_setup_sub" set an error 2367 */ 2368 if (parm->err) { 2369 return; 2370 } 2371 /* 2372 * allocate transfer descriptors 2373 */ 2374 last_obj = NULL; 2375 2376 /* 2377 * get profile stuff 2378 */ 2379 if (ntd) { 2380 2381 ep_no = xfer->endpoint & UE_ADDR; 2382 at91dci_get_hw_ep_profile(parm->udev, &pf, ep_no); 2383 2384 if (pf == NULL) { 2385 /* should not happen */ 2386 parm->err = USB_ERR_INVAL; 2387 return; 2388 } 2389 } else { 2390 ep_no = 0; 2391 pf = NULL; 2392 } 2393 2394 /* align data */ 2395 parm->size[0] += ((-parm->size[0]) & (USB_HOST_ALIGN - 1)); 2396 2397 for (n = 0; n != ntd; n++) { 2398 2399 struct at91dci_td *td; 2400 2401 if (parm->buf) { 2402 2403 td = USB_ADD_BYTES(parm->buf, parm->size[0]); 2404 2405 /* init TD */ 2406 td->io_tag = sc->sc_io_tag; 2407 td->io_hdl = sc->sc_io_hdl; 2408 td->max_packet_size = xfer->max_packet_size; 2409 td->status_reg = AT91_UDP_CSR(ep_no); 2410 td->fifo_reg = AT91_UDP_FDR(ep_no); 2411 if (pf->support_multi_buffer) { 2412 td->support_multi_buffer = 1; 2413 } 2414 td->obj_next = last_obj; 2415 2416 last_obj = td; 2417 } 2418 parm->size[0] += sizeof(*td); 2419 } 2420 2421 xfer->td_start[0] = last_obj; 2422} 2423 2424static void 2425at91dci_xfer_unsetup(struct usb2_xfer *xfer) 2426{ 2427 return; 2428} 2429 2430static void 2431at91dci_pipe_init(struct usb2_device *udev, struct usb2_endpoint_descriptor *edesc, 2432 struct usb2_pipe *pipe) 2433{ 2434 struct at91dci_softc *sc = AT9100_DCI_BUS2SC(udev->bus); 2435 2436 DPRINTFN(2, "pipe=%p, addr=%d, endpt=%d, mode=%d (%d)\n", 2437 pipe, udev->address, 2438 edesc->bEndpointAddress, udev->flags.usb2_mode, 2439 sc->sc_rt_addr); 2440 2441 if (udev->device_index == sc->sc_rt_addr) { 2442 2443 if (udev->flags.usb2_mode != USB_MODE_HOST) { 2444 /* not supported */ 2445 return; 2446 } 2447 switch (edesc->bEndpointAddress) { 2448 case USB_CONTROL_ENDPOINT: 2449 pipe->methods = &at91dci_root_ctrl_methods; 2450 break; 2451 case UE_DIR_IN | AT9100_DCI_INTR_ENDPT: 2452 pipe->methods = &at91dci_root_intr_methods; 2453 break; 2454 default: 2455 /* do nothing */ 2456 break; 2457 } 2458 } else { 2459 2460 if (udev->flags.usb2_mode != USB_MODE_DEVICE) { 2461 /* not supported */ 2462 return; 2463 } 2464 if (udev->speed != USB_SPEED_FULL) { 2465 /* not supported */ 2466 return; 2467 } 2468 switch (edesc->bmAttributes & UE_XFERTYPE) { 2469 case UE_CONTROL: 2470 pipe->methods = &at91dci_device_ctrl_methods; 2471 break; 2472 case UE_INTERRUPT: 2473 pipe->methods = &at91dci_device_intr_methods; 2474 break; 2475 case UE_ISOCHRONOUS: 2476 pipe->methods = &at91dci_device_isoc_fs_methods; 2477 break; 2478 case UE_BULK: 2479 pipe->methods = &at91dci_device_bulk_methods; 2480 break; 2481 default: 2482 /* do nothing */ 2483 break; 2484 } 2485 } 2486} 2487 2488struct usb2_bus_methods at91dci_bus_methods = 2489{ 2490 .pipe_init = &at91dci_pipe_init, 2491 .xfer_setup = &at91dci_xfer_setup, 2492 .xfer_unsetup = &at91dci_xfer_unsetup, 2493 .do_poll = &at91dci_do_poll, 2494 .get_hw_ep_profile = &at91dci_get_hw_ep_profile, 2495 .set_stall = &at91dci_set_stall, 2496 .clear_stall = &at91dci_clear_stall, 2497 .vbus_interrupt = &at91dci_vbus_interrupt, 2498 .rem_wakeup_set = &at91dci_rem_wakeup_set, 2499}; 2500